About memory allocation for DMA on platforms with MMU/cache

[KIKUCHI Takeyoshi <ki...@centurysys.co.jp>]

Hi all,

I am developing on an ARMv7-a Microchip SAMA5D2 board.

When interacting with peripherals that have DMA capabilities, there are
processes here and there to flush/invalidate the cache.
However, I am seeing problems with various drivers that may not be
handled properly.

For example,
Ethernet(sam_ethernet): sometimes the owner bit of the ring buffer
descriptor is not passed to the hardware, and the sending/receiving
stops.
USB EHCI: Data received via BULK IN may be corrupted.

I think it would be inefficient to flush/invalidate the cache each time,
as there is not much effect from the cache to the extent of changing
bits in the descriptor.
Therefore, I think it would be useful to have a Linux-like mechanism
(like dma_alloc_coherent() ) to allocate memory with the cache disabled,
but how do you think it should be implemented?

As for the SAM5D2 Ethernet driver problem described above, I tentatively
addressed it by referring to the graphics framebuffer driver and using a
static allocation of non-cacheable space.


Regards,

KIKUCHI Takeyoshi

kikuchi@centurysys.co.jp