trafficserver git commit: Fix compiliation issues for older compilers (thanx zwoop).

[jp...@apache.org]

Repository: trafficserver
Updated Branches:
  refs/heads/master 7dec45b3d -> d3ce6b55f


Fix compiliation issues for older compilers (thanx zwoop).


Project: http://git-wip-us.apache.org/repos/asf/trafficserver/repo
Commit: http://git-wip-us.apache.org/repos/asf/trafficserver/commit/d3ce6b55
Tree: http://git-wip-us.apache.org/repos/asf/trafficserver/tree/d3ce6b55
Diff: http://git-wip-us.apache.org/repos/asf/trafficserver/diff/d3ce6b55

Branch: refs/heads/master
Commit: d3ce6b55f922fa391a21f6d7d1f87ab1787bf1f8
Parents: 7dec45b
Author: John Plevyak <jp...@apache.org>
Authored: Mon Feb 2 07:09:32 2015 -0800
Committer: John Plevyak <jp...@acm.org>
Committed: Mon Feb 2 07:15:25 2015 -0800

----------------------------------------------------------------------
 iocore/cache/CacheTest.cc | 27 +++++++++++++++++++--------
 1 file changed, 19 insertions(+), 8 deletions(-)
----------------------------------------------------------------------


http://git-wip-us.apache.org/repos/asf/trafficserver/blob/d3ce6b55/iocore/cache/CacheTest.cc
----------------------------------------------------------------------
diff --git a/iocore/cache/CacheTest.cc b/iocore/cache/CacheTest.cc
index 9b5f4ff..734f7a7 100644
--- a/iocore/cache/CacheTest.cc
+++ b/iocore/cache/CacheTest.cc
@@ -491,43 +491,54 @@ REGRESSION_TEST(cache_disk_replacement_stability)(RegressionTest *t, int level,
   hr2.vols = 0;
 }
 
-bool test_RamCache(RegressionTest *t, RamCache *cache) {
+bool
+test_RamCache(RegressionTest *t, RamCache *cache)
+{
   bool pass = true;
   CacheKey key;
   Vol *vol = theCache->key_to_vol(&key, "example.com", sizeof("example.com")-1);
+  vector< Ptr<IOBufferData> > data;
+
   cache->init(1 << 20, vol);
-  vector<Ptr<IOBufferData>> data;
+
   for (int l = 0; l < 10; l++) {
     for (int i = 0; i < 200; i++) {
       IOBufferData *d = new IOBufferData;
-      d->alloc(BUFFER_SIZE_INDEX_16K);
-      data.emplace_back(d);
       INK_MD5 md5;
+
+      d->alloc(BUFFER_SIZE_INDEX_16K);
+      data.push_back(Ptr<IOBufferData>(d));
       md5.u64[0] = ((uint64_t)i << 32) + i;
       md5.u64[1] = ((uint64_t)i << 32) + i;
       cache->put(&md5, data[i], 1 << 15);
       // More hits for the first 10.
       for (int j = 0; j <= i && j < 10; j++) {
+        Ptr<IOBufferData> data;
         INK_MD5 md5;
+
         md5.u64[0] = ((uint64_t)j << 32) + j;
         md5.u64[1] = ((uint64_t)j << 32) + j;
-        Ptr<IOBufferData> data;
         cache->get(&md5, &data);
       }
     }
   }
+
   for (int i = 0; i < 10; i++) {
     INK_MD5 md5;
+    Ptr<IOBufferData> data;
+
     md5.u64[0] = ((uint64_t)i << 32) + i;
     md5.u64[1] = ((uint64_t)i << 32) + i;
-    Ptr<IOBufferData> data;
-    if (!cache->get(&md5, &data)) pass = false;
+    if (!cache->get(&md5, &data)) {
+      pass = false;
+    }
   }
   rprintf(t, "RamCache Test Done");
   return pass;
 }
 
-REGRESSION_TEST(ram_cache)(RegressionTest *t, int /* level ATS_UNUSED */, int *pstatus) {
+REGRESSION_TEST(ram_cache)(RegressionTest *t, int /* level ATS_UNUSED */, int *pstatus)
+{
   if (cacheProcessor.IsCacheEnabled() != CACHE_INITIALIZED) {
     rprintf(t, "cache not initialized");
     *pstatus = REGRESSION_TEST_FAILED;