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Posted to commits@mynewt.apache.org by cc...@apache.org on 2016/11/08 04:52:02 UTC
[1/3] incubator-mynewt-core git commit: Move startup code back into
BSP pgks (from MCU).
Repository: incubator-mynewt-core
Updated Branches:
refs/heads/develop 06c02a55d -> 90067c9ac
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/90067c9a/hw/mcu/nordic/nrf51xxx/src/arch/cortex_m0/gcc_startup_nrf51_split.s
----------------------------------------------------------------------
diff --git a/hw/mcu/nordic/nrf51xxx/src/arch/cortex_m0/gcc_startup_nrf51_split.s b/hw/mcu/nordic/nrf51xxx/src/arch/cortex_m0/gcc_startup_nrf51_split.s
deleted file mode 100755
index ed5f207..0000000
--- a/hw/mcu/nordic/nrf51xxx/src/arch/cortex_m0/gcc_startup_nrf51_split.s
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
-Copyright (c) 2015, Nordic Semiconductor ASA
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-
-* Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
- and/or other materials provided with the distribution.
-
-* Neither the name of Nordic Semiconductor ASA nor the names of its
- contributors may be used to endorse or promote products derived from
- this software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/*
-NOTE: Template files (including this one) are application specific and therefore
-expected to be copied into the application project folder prior to its use!
-*/
-
- .syntax unified
- .arch armv6-m
-
- .section .stack
- .align 3
- .equ Stack_Size, 432
- .globl __StackTop
- .globl __StackLimit
-__StackLimit:
- .space Stack_Size
- .size __StackLimit, . - __StackLimit
-__StackTop:
- .size __StackTop, . - __StackTop
-
- .section .heap
- .align 3
-#ifdef __HEAP_SIZE
- .equ Heap_Size, __HEAP_SIZE
-#else
- .equ Heap_Size, 0
-#endif
- .globl __HeapBase
- .globl __HeapLimit
-__HeapBase:
- .if Heap_Size
- .space Heap_Size
- .endif
- .size __HeapBase, . - __HeapBase
-__HeapLimit:
- .size __HeapLimit, . - __HeapLimit
-
- .section .isr_vector_split
- .align 2
- .globl __isr_vector_split
-__isr_vector_split:
- .long __StackTop /* Top of Stack */
- .long Reset_Handler_split /* Reset Handler */
-
- .size __isr_vector_split, . - __isr_vector_split
-
-/* Reset Handler */
-
- .equ NRF_POWER_RAMON_ADDRESS, 0x40000524
- .equ NRF_POWER_RAMONB_ADDRESS, 0x40000554
- .equ NRF_POWER_RAMONx_RAMxON_ONMODE_Msk, 0x3
-
- .text
- .thumb
- .thumb_func
- .align 1
- .globl Reset_Handler_split
- .type Reset_Handler_split, %function
-Reset_Handler_split:
- .fnstart
-
-/* Make sure ALL RAM banks are powered on */
- MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
-
- LDR R0, =NRF_POWER_RAMON_ADDRESS
- LDR R2, [R0]
- ORRS R2, R1
- STR R2, [R0]
-
- LDR R0, =NRF_POWER_RAMONB_ADDRESS
- LDR R2, [R0]
- ORRS R2, R1
- STR R2, [R0]
-
-/* Loop to copy data from read only memory to RAM. The ranges
- * of copy from/to are specified by following symbols evaluated in
- * linker script.
- * __etext: End of code section, i.e., begin of data sections to copy from.
- * __data_start__/__data_end__: RAM address range that data should be
- * copied to. Both must be aligned to 4 bytes boundary. */
-
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
-
- subs r3, r2
- ble .LC0
-
-.LC1:
- subs r3, 4
- ldr r0, [r1,r3]
- str r0, [r2,r3]
- bgt .LC1
-.LC0:
- ldr r1, =__etext_loader
- ldr r2, =__data_start___loader
- ldr r3, =__data_end___loader
-
- subs r3, r2
- ble .LC2
-
-.LC3:
- subs r3, 4
- ldr r0, [r1,r3]
- str r0, [r2,r3]
- bgt .LC3
-.LC2:
-
- subs r0, r0
- ldr r2, =__bss_start___loader
- ldr r3, =__bss_end___loader
-
- subs r3, r2
- ble .LC4
-
-.LC5:
- subs r3, 4
- str r0, [r2,r3]
- bgt .LC5
-.LC4:
- LDR R0, =__HeapBase
- LDR R1, =__HeapLimit
- BL _sbrkInit
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =_start
- BX R0
-
- .pool
- .cantunwind
- .fnend
- .size Reset_Handler_split,.-Reset_Handler_split
-
- .section ".text"
-
- .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/90067c9a/hw/mcu/nordic/nrf52xxx/src/arch/cortex_m4/gcc_startup_nrf52.s
----------------------------------------------------------------------
diff --git a/hw/mcu/nordic/nrf52xxx/src/arch/cortex_m4/gcc_startup_nrf52.s b/hw/mcu/nordic/nrf52xxx/src/arch/cortex_m4/gcc_startup_nrf52.s
deleted file mode 100755
index fb804fd..0000000
--- a/hw/mcu/nordic/nrf52xxx/src/arch/cortex_m4/gcc_startup_nrf52.s
+++ /dev/null
@@ -1,289 +0,0 @@
-/*
-Copyright (c) 2015, Nordic Semiconductor ASA
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-
-* Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
- and/or other materials provided with the distribution.
-
-* Neither the name of Nordic Semiconductor ASA nor the names of its
- contributors may be used to endorse or promote products derived from
- this software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/*
-NOTE: Template files (including this one) are application specific and therefore
-expected to be copied into the application project folder prior to its use!
-*/
-
- .syntax unified
- .arch armv7-m
-
- .section .stack
- .align 3
- .equ Stack_Size, 432
- .globl __StackTop
- .globl __StackLimit
-__StackLimit:
- .space Stack_Size
- .size __StackLimit, . - __StackLimit
-__StackTop:
- .size __StackTop, . - __StackTop
-
- .section .heap
- .align 3
-#ifdef __HEAP_SIZE
- .equ Heap_Size, __HEAP_SIZE
-#else
- .equ Heap_Size, 0
-#endif
- .globl __HeapBase
- .globl __HeapLimit
-__HeapBase:
- .if Heap_Size
- .space Heap_Size
- .endif
- .size __HeapBase, . - __HeapBase
-__HeapLimit:
- .size __HeapLimit, . - __HeapLimit
-
- .section .isr_vector
- .align 2
- .globl __isr_vector
-__isr_vector:
- .long __StackTop /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
-
- /* External Interrupts */
- .long POWER_CLOCK_IRQHandler
- .long RADIO_IRQHandler
- .long UARTE0_UART0_IRQHandler
- .long SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
- .long SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
- .long NFCT_IRQHandler
- .long GPIOTE_IRQHandler
- .long SAADC_IRQHandler
- .long TIMER0_IRQHandler
- .long TIMER1_IRQHandler
- .long TIMER2_IRQHandler
- .long RTC0_IRQHandler
- .long TEMP_IRQHandler
- .long RNG_IRQHandler
- .long ECB_IRQHandler
- .long CCM_AAR_IRQHandler
- .long WDT_IRQHandler
- .long RTC1_IRQHandler
- .long QDEC_IRQHandler
- .long COMP_LPCOMP_IRQHandler
- .long SWI0_EGU0_IRQHandler
- .long SWI1_EGU1_IRQHandler
- .long SWI2_EGU2_IRQHandler
- .long SWI3_EGU3_IRQHandler
- .long SWI4_EGU4_IRQHandler
- .long SWI5_EGU5_IRQHandler
- .long TIMER3_IRQHandler
- .long TIMER4_IRQHandler
- .long PWM0_IRQHandler
- .long PDM_IRQHandler
- .long 0 /*Reserved */
- .long 0 /*Reserved */
- .long MWU_IRQHandler
- .long PWM1_IRQHandler
- .long PWM2_IRQHandler
- .long SPIM2_SPIS2_SPI2_IRQHandler
- .long RTC2_IRQHandler
- .long I2S_IRQHandler
-
- .size __isr_vector, . - __isr_vector
-
-/* Reset Handler */
-
- .text
- .thumb
- .thumb_func
- .align 1
- .globl Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- .fnstart
-
-/* Loop to copy data from read only memory to RAM. The ranges
- * of copy from/to are specified by following symbols evaluated in
- * linker script.
- * __etext: End of code section, i.e., begin of data sections to copy from.
- * __data_start__/__data_end__: RAM address range that data should be
- * copied to. Both must be aligned to 4 bytes boundary. */
-
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
-
- subs r3, r2
- ble .LC0
-
-.LC1:
- subs r3, 4
- ldr r0, [r1,r3]
- str r0, [r2,r3]
- bgt .LC1
-
-.LC0:
-
- LDR R0, =__HeapBase
- LDR R1, =__HeapLimit
- BL _sbrkInit
-
- LDR R0, =SystemInit
- BLX R0
-
- LDR R0, =_start
- BX R0
-
- .pool
- .cantunwind
- .fnend
- .size Reset_Handler,.-Reset_Handler
-
- .section ".text"
-
-
-/* Dummy Exception Handlers (infinite loops which can be modified) */
-
- .weak NMI_Handler
- .type NMI_Handler, %function
-NMI_Handler:
- B .
- .size NMI_Handler, . - NMI_Handler
-
-
- .weak HardFault_Handler
- .type HardFault_Handler, %function
-HardFault_Handler:
- B .
- .size HardFault_Handler, . - HardFault_Handler
-
-
- .weak MemoryManagement_Handler
- .type MemoryManagement_Handler, %function
-MemoryManagement_Handler:
- B .
- .size MemoryManagement_Handler, . - MemoryManagement_Handler
-
-
- .weak BusFault_Handler
- .type BusFault_Handler, %function
-BusFault_Handler:
- B .
- .size BusFault_Handler, . - BusFault_Handler
-
-
- .weak UsageFault_Handler
- .type UsageFault_Handler, %function
-UsageFault_Handler:
- B .
- .size UsageFault_Handler, . - UsageFault_Handler
-
-
- .weak SVC_Handler
- .type SVC_Handler, %function
-SVC_Handler:
- B .
- .size SVC_Handler, . - SVC_Handler
-
-
- .weak PendSV_Handler
- .type PendSV_Handler, %function
-PendSV_Handler:
- B .
- .size PendSV_Handler, . - PendSV_Handler
-
-
- .weak SysTick_Handler
- .type SysTick_Handler, %function
-SysTick_Handler:
- B .
- .size SysTick_Handler, . - SysTick_Handler
-
-
-/* IRQ Handlers */
-
- .globl Default_Handler
- .type Default_Handler, %function
-Default_Handler:
- B .
- .size Default_Handler, . - Default_Handler
-
- .macro IRQ handler
- .weak \handler
- .set \handler, Default_Handler
- .endm
-
- IRQ POWER_CLOCK_IRQHandler
- IRQ RADIO_IRQHandler
- IRQ UARTE0_UART0_IRQHandler
- IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
- IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
- IRQ NFCT_IRQHandler
- IRQ GPIOTE_IRQHandler
- IRQ SAADC_IRQHandler
- IRQ TIMER0_IRQHandler
- IRQ TIMER1_IRQHandler
- IRQ TIMER2_IRQHandler
- IRQ RTC0_IRQHandler
- IRQ TEMP_IRQHandler
- IRQ RNG_IRQHandler
- IRQ ECB_IRQHandler
- IRQ CCM_AAR_IRQHandler
- IRQ WDT_IRQHandler
- IRQ RTC1_IRQHandler
- IRQ QDEC_IRQHandler
- IRQ COMP_LPCOMP_IRQHandler
- IRQ SWI0_EGU0_IRQHandler
- IRQ SWI1_EGU1_IRQHandler
- IRQ SWI2_EGU2_IRQHandler
- IRQ SWI3_EGU3_IRQHandler
- IRQ SWI4_EGU4_IRQHandler
- IRQ SWI5_EGU5_IRQHandler
- IRQ TIMER3_IRQHandler
- IRQ TIMER4_IRQHandler
- IRQ PWM0_IRQHandler
- IRQ PDM_IRQHandler
- IRQ MWU_IRQHandler
- IRQ PWM1_IRQHandler
- IRQ PWM2_IRQHandler
- IRQ SPIM2_SPIS2_SPI2_IRQHandler
- IRQ RTC2_IRQHandler
- IRQ I2S_IRQHandler
-
- .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/90067c9a/hw/mcu/nordic/nrf52xxx/src/arch/cortex_m4/gcc_startup_nrf52_split.s
----------------------------------------------------------------------
diff --git a/hw/mcu/nordic/nrf52xxx/src/arch/cortex_m4/gcc_startup_nrf52_split.s b/hw/mcu/nordic/nrf52xxx/src/arch/cortex_m4/gcc_startup_nrf52_split.s
deleted file mode 100755
index 7426848..0000000
--- a/hw/mcu/nordic/nrf52xxx/src/arch/cortex_m4/gcc_startup_nrf52_split.s
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
-Copyright (c) 2015, Nordic Semiconductor ASA
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-
-* Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
- and/or other materials provided with the distribution.
-
-* Neither the name of Nordic Semiconductor ASA nor the names of its
- contributors may be used to endorse or promote products derived from
- this software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/*
-NOTE: Template files (including this one) are application specific and therefore
-expected to be copied into the application project folder prior to its use!
-*/
-
- .syntax unified
- .arch armv7-m
- .section .stack
- .align 3
- .equ Stack_Size, 432
- .globl __StackTop
- .globl __StackLimit
-__StackLimit:
- .space Stack_Size
- .size __StackLimit, . - __StackLimit
-__StackTop:
- .size __StackTop, . - __StackTop
-
- .section .heap
- .align 3
-#ifdef __HEAP_SIZE
- .equ Heap_Size, __HEAP_SIZE
-#else
- .equ Heap_Size, 0
-#endif
- .globl __HeapBase
- .globl __HeapLimit
-__HeapBase:
- .if Heap_Size
- .space Heap_Size
- .endif
- .size __HeapBase, . - __HeapBase
-__HeapLimit:
- .size __HeapLimit, . - __HeapLimit
-
- .section .isr_vector_split
- .align 2
- .globl __isr_vector_split
-__isr_vector_split:
- .long __StackTop /* Top of Stack */
- .long Reset_Handler_split /* Reset Handler */
-
- .size __isr_vector_split, . - __isr_vector_split
-
-/* Reset Handler */
-
- .text
- .thumb
- .thumb_func
- .align 1
- .globl Reset_Handler_split
- .type Reset_Handler_split, %function
-Reset_Handler_split:
- .fnstart
-
-
-/* Loop to copy data from read only memory to RAM. The ranges
- * of copy from/to are specified by following symbols evaluated in
- * linker script.
- * __etext: End of code section, i.e., begin of data sections to copy from.
- * __data_start__/__data_end__: RAM address range that data should be
- * copied to. Both must be aligned to 4 bytes boundary. */
-
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
-
- subs r3, r2
- ble .LC0
-
-.LC1:
- subs r3, 4
- ldr r0, [r1,r3]
- str r0, [r2,r3]
- bgt .LC1
-
-.LC0:
- ldr r1, =__etext_loader
- ldr r2, =__data_start___loader
- ldr r3, =__data_end___loader
-
- subs r3, r2
- ble .LC2
-
-.LC3:
- subs r3, 4
- ldr r0, [r1,r3]
- str r0, [r2,r3]
- bgt .LC3
-.LC2:
-
- subs r0, r0
- ldr r2, =__bss_start___loader
- ldr r3, =__bss_end___loader
-
- subs r3, r2
- ble .LC4
-
-.LC5:
- subs r3, 4
- str r0, [r2,r3]
- bgt .LC5
-.LC4:
-
- LDR R0, =__HeapBase
- LDR R1, =__HeapLimit
- BL _sbrkInit
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =_start
- BX R0
-
- .pool
- .cantunwind
- .fnend
- .size Reset_Handler_split,.-Reset_Handler_split
-
- .section ".text"
- .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/90067c9a/hw/mcu/stm/stm32f4xx/src/startup_STM32F40x.s
----------------------------------------------------------------------
diff --git a/hw/mcu/stm/stm32f4xx/src/startup_STM32F40x.s b/hw/mcu/stm/stm32f4xx/src/startup_STM32F40x.s
deleted file mode 100644
index 646b4bf..0000000
--- a/hw/mcu/stm/stm32f4xx/src/startup_STM32F40x.s
+++ /dev/null
@@ -1,343 +0,0 @@
-/* File: startup_STM32F40x.S
- * Purpose: startup file for Cortex-M4 devices. Should use with
- * GCC for ARM Embedded Processors
- * Version: V1.4
- * Date: 09 July 2012
- *
- * Copyright (c) 2011, 2012, ARM Limited
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- * Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- * Neither the name of the ARM Limited nor the
- names of its contributors may be used to endorse or promote products
- derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
- .syntax unified
- .arch armv7-m
-
- .section .stack
- .align 3
-#ifdef __STACK_SIZE
- .equ Stack_Size, __STACK_SIZE
-#else
- .equ Stack_Size, 0xc00
-#endif
- .globl __StackTop
- .globl __StackLimit
-__StackLimit:
- .space Stack_Size
- .size __StackLimit, . - __StackLimit
-__StackTop:
- .size __StackTop, . - __StackTop
-
- .section .heap
- .align 3
-#ifdef __HEAP_SIZE
- .equ Heap_Size, __HEAP_SIZE
-#else
- .equ Heap_Size, 0
-#endif
- .globl __HeapBase
- .globl __HeapLimit
-__HeapBase:
- .if Heap_Size
- .space Heap_Size
- .endif
- .size __HeapBase, . - __HeapBase
-__HeapLimit:
- .size __HeapLimit, . - __HeapLimit
-
- .section .isr_vector
- .align 2
- .globl __isr_vector
-__isr_vector:
- .long __StackTop /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long MemManage_Handler /* MPU Fault Handler */
- .long BusFault_Handler /* Bus Fault Handler */
- .long UsageFault_Handler /* Usage Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long DebugMon_Handler /* Debug Monitor Handler */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
-
- /* External interrupts */
- .long WWDG_IRQHandler /* Window WatchDog */
- .long PVD_IRQHandler /* PVD through EXTI Line detection */
- .long TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
- .long RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
- .long FLASH_IRQHandler /* FLASH */
- .long RCC_IRQHandler /* RCC */
- .long EXTI0_IRQHandler /* EXTI Line0 */
- .long EXTI1_IRQHandler /* EXTI Line1 */
- .long EXTI2_IRQHandler /* EXTI Line2 */
- .long EXTI3_IRQHandler /* EXTI Line3 */
- .long EXTI4_IRQHandler /* EXTI Line4 */
- .long DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
- .long DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
- .long DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
- .long DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
- .long DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
- .long DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
- .long DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
- .long ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
- .long CAN1_TX_IRQHandler /* CAN1 TX */
- .long CAN1_RX0_IRQHandler /* CAN1 RX0 */
- .long CAN1_RX1_IRQHandler /* CAN1 RX1 */
- .long CAN1_SCE_IRQHandler /* CAN1 SCE */
- .long EXTI9_5_IRQHandler /* External Line[9:5]s */
- .long TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
- .long TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
- .long TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
- .long TIM1_CC_IRQHandler /* TIM1 Capture Compare */
- .long TIM2_IRQHandler /* TIM2 */
- .long TIM3_IRQHandler /* TIM3 */
- .long TIM4_IRQHandler /* TIM4 */
- .long I2C1_EV_IRQHandler /* I2C1 Event */
- .long I2C1_ER_IRQHandler /* I2C1 Error */
- .long I2C2_EV_IRQHandler /* I2C2 Event */
- .long I2C2_ER_IRQHandler /* I2C2 Error */
- .long SPI1_IRQHandler /* SPI1 */
- .long SPI2_IRQHandler /* SPI2 */
- .long USART1_IRQHandler /* USART1 */
- .long USART2_IRQHandler /* USART2 */
- .long USART3_IRQHandler /* USART3 */
- .long EXTI15_10_IRQHandler /* External Line[15:10]s */
- .long RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
- .long OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
- .long TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
- .long TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
- .long TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
- .long TIM8_CC_IRQHandler /* TIM8 Capture Compare */
- .long DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
- .long FSMC_IRQHandler /* FSMC */
- .long SDIO_IRQHandler /* SDIO */
- .long TIM5_IRQHandler /* TIM5 */
- .long SPI3_IRQHandler /* SPI3 */
- .long UART4_IRQHandler /* UART4 */
- .long UART5_IRQHandler /* UART5 */
- .long TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
- .long TIM7_IRQHandler /* TIM7 */
- .long DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
- .long DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
- .long DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
- .long DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
- .long DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
- .long ETH_IRQHandler /* Ethernet */
- .long ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
- .long CAN2_TX_IRQHandler /* CAN2 TX */
- .long CAN2_RX0_IRQHandler /* CAN2 RX0 */
- .long CAN2_RX1_IRQHandler /* CAN2 RX1 */
- .long CAN2_SCE_IRQHandler /* CAN2 SCE */
- .long OTG_FS_IRQHandler /* USB OTG FS */
- .long DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
- .long DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
- .long DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
- .long USART6_IRQHandler /* USART6 */
- .long I2C3_EV_IRQHandler /* I2C3 event */
- .long I2C3_ER_IRQHandler /* I2C3 error */
- .long OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
- .long OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
- .long OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
- .long OTG_HS_IRQHandler /* USB OTG HS */
- .long DCMI_IRQHandler /* DCMI */
- .long CRYP_IRQHandler /* CRYP crypto */
- .long HASH_RNG_IRQHandler /* Hash and Rng */
- .long FPU_IRQHandler /* FPU */
-
- .size __isr_vector, . - __isr_vector
-
- .text
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
-/* Copy data core section from flash to RAM */
- ldr r1, =__etext
- ldr r2, =__coredata_start__
- ldr r3, =__coredata_end__
-
-.LC0:
- cmp r2, r3
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r2], #4
- blt .LC0
-
-/* Loop to copy data from read only memory to RAM. The ranges
- * of copy from/to are specified by following symbols evaluated in
- * linker script.
- * __etext: End of code section, i.e., begin of data sections to copy from.
- * __data_start__/__data_end__: RAM address range that data should be
- * copied to. Both must be aligned to 4 bytes boundary. */
- ldr r1, =__ecoredata
- ldr r2, =__data_start__
- ldr r3, =__data_end__
-
-.LC1:
- cmp r2, r3
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r2], #4
- blt .LC1
-
-/* Set the bss core section to zero */
- mov r0, #0
- ldr r1, =__corebss_start__
- ldr r2, =__corebss_end__
-
-.LC2:
- cmp r1, r2
- itt lt
- strlt r0, [r1], #4
- blt .LC2
-
-/* Call system initialization and startup routines */
- ldr r0, =SystemInit
- blx r0
- ldr r0, =_start
- bx r0
- .pool
- .size Reset_Handler, . - Reset_Handler
-
- .text
-/* Macro to define default handlers. Default handler
- * will be weak symbol and just dead loops. They can be
- * overwritten by other handlers */
- .macro def_default_handler handler_name
- .align 1
- .thumb_func
- .weak \handler_name
- .type \handler_name, %function
-\handler_name :
- b .
- .size \handler_name, . - \handler_name
- .endm
-
- def_default_handler NMI_Handler
- def_default_handler HardFault_Handler
- def_default_handler MemManage_Handler
- def_default_handler BusFault_Handler
- def_default_handler UsageFault_Handler
- def_default_handler SVC_Handler
- def_default_handler DebugMon_Handler
- def_default_handler PendSV_Handler
- def_default_handler SysTick_Handler
- def_default_handler Default_Handler
-
- .macro def_irq_default_handler handler_name
- .weak \handler_name
- .set \handler_name, Default_Handler
- .endm
-
- def_irq_default_handler WWDG_IRQHandler
- def_irq_default_handler PVD_IRQHandler
- def_irq_default_handler TAMP_STAMP_IRQHandler
- def_irq_default_handler RTC_WKUP_IRQHandler
- def_irq_default_handler FLASH_IRQHandler
- def_irq_default_handler RCC_IRQHandler
- def_irq_default_handler EXTI0_IRQHandler
- def_irq_default_handler EXTI1_IRQHandler
- def_irq_default_handler EXTI2_IRQHandler
- def_irq_default_handler EXTI3_IRQHandler
- def_irq_default_handler EXTI4_IRQHandler
- def_irq_default_handler DMA1_Stream0_IRQHandler
- def_irq_default_handler DMA1_Stream1_IRQHandler
- def_irq_default_handler DMA1_Stream2_IRQHandler
- def_irq_default_handler DMA1_Stream3_IRQHandler
- def_irq_default_handler DMA1_Stream4_IRQHandler
- def_irq_default_handler DMA1_Stream5_IRQHandler
- def_irq_default_handler DMA1_Stream6_IRQHandler
- def_irq_default_handler ADC_IRQHandler
- def_irq_default_handler CAN1_TX_IRQHandler
- def_irq_default_handler CAN1_RX0_IRQHandler
- def_irq_default_handler CAN1_RX1_IRQHandler
- def_irq_default_handler CAN1_SCE_IRQHandler
- def_irq_default_handler EXTI9_5_IRQHandler
- def_irq_default_handler TIM1_BRK_TIM9_IRQHandler
- def_irq_default_handler TIM1_UP_TIM10_IRQHandler
- def_irq_default_handler TIM1_TRG_COM_TIM11_IRQHandler
- def_irq_default_handler TIM1_CC_IRQHandler
- def_irq_default_handler TIM2_IRQHandler
- def_irq_default_handler TIM3_IRQHandler
- def_irq_default_handler TIM4_IRQHandler
- def_irq_default_handler I2C1_EV_IRQHandler
- def_irq_default_handler I2C1_ER_IRQHandler
- def_irq_default_handler I2C2_EV_IRQHandler
- def_irq_default_handler I2C2_ER_IRQHandler
- def_irq_default_handler SPI1_IRQHandler
- def_irq_default_handler SPI2_IRQHandler
- def_irq_default_handler USART1_IRQHandler
- def_irq_default_handler USART2_IRQHandler
- def_irq_default_handler USART3_IRQHandler
- def_irq_default_handler EXTI15_10_IRQHandler
- def_irq_default_handler RTC_Alarm_IRQHandler
- def_irq_default_handler OTG_FS_WKUP_IRQHandler
- def_irq_default_handler TIM8_BRK_TIM12_IRQHandler
- def_irq_default_handler TIM8_UP_TIM13_IRQHandler
- def_irq_default_handler TIM8_TRG_COM_TIM14_IRQHandler
- def_irq_default_handler TIM8_CC_IRQHandler
- def_irq_default_handler DMA1_Stream7_IRQHandler
- def_irq_default_handler FSMC_IRQHandler
- def_irq_default_handler SDIO_IRQHandler
- def_irq_default_handler TIM5_IRQHandler
- def_irq_default_handler SPI3_IRQHandler
- def_irq_default_handler UART4_IRQHandler
- def_irq_default_handler UART5_IRQHandler
- def_irq_default_handler TIM6_DAC_IRQHandler
- def_irq_default_handler TIM7_IRQHandler
- def_irq_default_handler DMA2_Stream0_IRQHandler
- def_irq_default_handler DMA2_Stream1_IRQHandler
- def_irq_default_handler DMA2_Stream2_IRQHandler
- def_irq_default_handler DMA2_Stream3_IRQHandler
- def_irq_default_handler DMA2_Stream4_IRQHandler
- def_irq_default_handler ETH_IRQHandler
- def_irq_default_handler ETH_WKUP_IRQHandler
- def_irq_default_handler CAN2_TX_IRQHandler
- def_irq_default_handler CAN2_RX0_IRQHandler
- def_irq_default_handler CAN2_RX1_IRQHandler
- def_irq_default_handler CAN2_SCE_IRQHandler
- def_irq_default_handler OTG_FS_IRQHandler
- def_irq_default_handler DMA2_Stream5_IRQHandler
- def_irq_default_handler DMA2_Stream6_IRQHandler
- def_irq_default_handler DMA2_Stream7_IRQHandler
- def_irq_default_handler USART6_IRQHandler
- def_irq_default_handler I2C3_EV_IRQHandler
- def_irq_default_handler I2C3_ER_IRQHandler
- def_irq_default_handler OTG_HS_EP1_OUT_IRQHandler
- def_irq_default_handler OTG_HS_EP1_IN_IRQHandler
- def_irq_default_handler OTG_HS_WKUP_IRQHandler
- def_irq_default_handler OTG_HS_IRQHandler
- def_irq_default_handler DCMI_IRQHandler
- def_irq_default_handler CRYP_IRQHandler
- def_irq_default_handler HASH_RNG_IRQHandler
- def_irq_default_handler FPU_IRQHandler
- def_irq_default_handler DEF_IRQHandler
-
- .end
[3/3] incubator-mynewt-core git commit: Move startup code back into
BSP pgks (from MCU).
Posted by cc...@apache.org.
Move startup code back into BSP pgks (from MCU).
The MCU packages are probably the correct place for these files, but
newt has issues building split images with them there. In particular,
newt doesn't recognize that the app (second slot) uses
Reset_Handler_split, so the resulting image is empty. This is a
temporary fix to keep split images working.
Project: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/repo
Commit: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/commit/90067c9a
Tree: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/tree/90067c9a
Diff: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/diff/90067c9a
Branch: refs/heads/develop
Commit: 90067c9acaf5466df9432a53c47a8c36b4317fb1
Parents: 06c02a5
Author: Christopher Collins <cc...@apache.org>
Authored: Mon Nov 7 20:47:43 2016 -0800
Committer: Christopher Collins <cc...@apache.org>
Committed: Mon Nov 7 20:51:36 2016 -0800
----------------------------------------------------------------------
.../src/arch/cortex_m4/gcc_startup_nrf52.s | 289 ++++++++++++++++
.../arch/cortex_m4/gcc_startup_nrf52_split.s | 150 ++++++++
.../src/arch/cortex_m4/gcc_startup_nrf52.s | 289 ++++++++++++++++
.../arch/cortex_m4/gcc_startup_nrf52_split.s | 150 ++++++++
.../src/arch/cortex_m0/gcc_startup_nrf51.s | 267 +++++++++++++++
hw/bsp/nrf51-arduino_101/src/sbrk.c | 20 +-
.../src/arch/cortex_m0/gcc_startup_nrf51.s | 270 +++++++++++++++
.../arch/cortex_m0/gcc_startup_nrf51_split.s | 166 +++++++++
.../src/arch/cortex_m0/gcc_startup_nrf51.s | 270 +++++++++++++++
.../arch/cortex_m0/gcc_startup_nrf51_split.s | 166 +++++++++
.../src/arch/cortex_m0/gcc_startup_nrf51.s | 270 +++++++++++++++
.../arch/cortex_m0/gcc_startup_nrf51_split.s | 166 +++++++++
.../src/arch/cortex_m4/gcc_startup_nrf52.s | 289 ++++++++++++++++
.../arch/cortex_m4/gcc_startup_nrf52_split.s | 150 ++++++++
.../src/arch/cortex_m4/startup_STM32F40x.s | 343 +++++++++++++++++++
.../src/arch/cortex_m4/startup_STM32F40x.s | 343 +++++++++++++++++++
.../src/arch/cortex_m4/gcc_startup_nrf52.s | 289 ++++++++++++++++
.../arch/cortex_m4/gcc_startup_nrf52_split.s | 150 ++++++++
.../src/arch/cortex_m4/startup_STM32F40x.s | 343 +++++++++++++++++++
.../src/arch/cortex_m0/gcc_startup_nrf51.s | 270 ---------------
.../arch/cortex_m0/gcc_startup_nrf51_split.s | 166 ---------
.../src/arch/cortex_m4/gcc_startup_nrf52.s | 289 ----------------
.../arch/cortex_m4/gcc_startup_nrf52_split.s | 150 --------
hw/mcu/stm/stm32f4xx/src/startup_STM32F40x.s | 343 -------------------
24 files changed, 4365 insertions(+), 1233 deletions(-)
----------------------------------------------------------------------
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/90067c9a/hw/bsp/arduino_primo_nrf52/src/arch/cortex_m4/gcc_startup_nrf52.s
----------------------------------------------------------------------
diff --git a/hw/bsp/arduino_primo_nrf52/src/arch/cortex_m4/gcc_startup_nrf52.s b/hw/bsp/arduino_primo_nrf52/src/arch/cortex_m4/gcc_startup_nrf52.s
new file mode 100755
index 0000000..fb804fd
--- /dev/null
+++ b/hw/bsp/arduino_primo_nrf52/src/arch/cortex_m4/gcc_startup_nrf52.s
@@ -0,0 +1,289 @@
+/*
+Copyright (c) 2015, Nordic Semiconductor ASA
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+* Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+NOTE: Template files (including this one) are application specific and therefore
+expected to be copied into the application project folder prior to its use!
+*/
+
+ .syntax unified
+ .arch armv7-m
+
+ .section .stack
+ .align 3
+ .equ Stack_Size, 432
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External Interrupts */
+ .long POWER_CLOCK_IRQHandler
+ .long RADIO_IRQHandler
+ .long UARTE0_UART0_IRQHandler
+ .long SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+ .long SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+ .long NFCT_IRQHandler
+ .long GPIOTE_IRQHandler
+ .long SAADC_IRQHandler
+ .long TIMER0_IRQHandler
+ .long TIMER1_IRQHandler
+ .long TIMER2_IRQHandler
+ .long RTC0_IRQHandler
+ .long TEMP_IRQHandler
+ .long RNG_IRQHandler
+ .long ECB_IRQHandler
+ .long CCM_AAR_IRQHandler
+ .long WDT_IRQHandler
+ .long RTC1_IRQHandler
+ .long QDEC_IRQHandler
+ .long COMP_LPCOMP_IRQHandler
+ .long SWI0_EGU0_IRQHandler
+ .long SWI1_EGU1_IRQHandler
+ .long SWI2_EGU2_IRQHandler
+ .long SWI3_EGU3_IRQHandler
+ .long SWI4_EGU4_IRQHandler
+ .long SWI5_EGU5_IRQHandler
+ .long TIMER3_IRQHandler
+ .long TIMER4_IRQHandler
+ .long PWM0_IRQHandler
+ .long PDM_IRQHandler
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long MWU_IRQHandler
+ .long PWM1_IRQHandler
+ .long PWM2_IRQHandler
+ .long SPIM2_SPIS2_SPI2_IRQHandler
+ .long RTC2_IRQHandler
+ .long I2S_IRQHandler
+
+ .size __isr_vector, . - __isr_vector
+
+/* Reset Handler */
+
+ .text
+ .thumb
+ .thumb_func
+ .align 1
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ .fnstart
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .LC0
+
+.LC1:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC1
+
+.LC0:
+
+ LDR R0, =__HeapBase
+ LDR R1, =__HeapLimit
+ BL _sbrkInit
+
+ LDR R0, =SystemInit
+ BLX R0
+
+ LDR R0, =_start
+ BX R0
+
+ .pool
+ .cantunwind
+ .fnend
+ .size Reset_Handler,.-Reset_Handler
+
+ .section ".text"
+
+
+/* Dummy Exception Handlers (infinite loops which can be modified) */
+
+ .weak NMI_Handler
+ .type NMI_Handler, %function
+NMI_Handler:
+ B .
+ .size NMI_Handler, . - NMI_Handler
+
+
+ .weak HardFault_Handler
+ .type HardFault_Handler, %function
+HardFault_Handler:
+ B .
+ .size HardFault_Handler, . - HardFault_Handler
+
+
+ .weak MemoryManagement_Handler
+ .type MemoryManagement_Handler, %function
+MemoryManagement_Handler:
+ B .
+ .size MemoryManagement_Handler, . - MemoryManagement_Handler
+
+
+ .weak BusFault_Handler
+ .type BusFault_Handler, %function
+BusFault_Handler:
+ B .
+ .size BusFault_Handler, . - BusFault_Handler
+
+
+ .weak UsageFault_Handler
+ .type UsageFault_Handler, %function
+UsageFault_Handler:
+ B .
+ .size UsageFault_Handler, . - UsageFault_Handler
+
+
+ .weak SVC_Handler
+ .type SVC_Handler, %function
+SVC_Handler:
+ B .
+ .size SVC_Handler, . - SVC_Handler
+
+
+ .weak PendSV_Handler
+ .type PendSV_Handler, %function
+PendSV_Handler:
+ B .
+ .size PendSV_Handler, . - PendSV_Handler
+
+
+ .weak SysTick_Handler
+ .type SysTick_Handler, %function
+SysTick_Handler:
+ B .
+ .size SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+ .globl Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ B .
+ .size Default_Handler, . - Default_Handler
+
+ .macro IRQ handler
+ .weak \handler
+ .set \handler, Default_Handler
+ .endm
+
+ IRQ POWER_CLOCK_IRQHandler
+ IRQ RADIO_IRQHandler
+ IRQ UARTE0_UART0_IRQHandler
+ IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+ IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+ IRQ NFCT_IRQHandler
+ IRQ GPIOTE_IRQHandler
+ IRQ SAADC_IRQHandler
+ IRQ TIMER0_IRQHandler
+ IRQ TIMER1_IRQHandler
+ IRQ TIMER2_IRQHandler
+ IRQ RTC0_IRQHandler
+ IRQ TEMP_IRQHandler
+ IRQ RNG_IRQHandler
+ IRQ ECB_IRQHandler
+ IRQ CCM_AAR_IRQHandler
+ IRQ WDT_IRQHandler
+ IRQ RTC1_IRQHandler
+ IRQ QDEC_IRQHandler
+ IRQ COMP_LPCOMP_IRQHandler
+ IRQ SWI0_EGU0_IRQHandler
+ IRQ SWI1_EGU1_IRQHandler
+ IRQ SWI2_EGU2_IRQHandler
+ IRQ SWI3_EGU3_IRQHandler
+ IRQ SWI4_EGU4_IRQHandler
+ IRQ SWI5_EGU5_IRQHandler
+ IRQ TIMER3_IRQHandler
+ IRQ TIMER4_IRQHandler
+ IRQ PWM0_IRQHandler
+ IRQ PDM_IRQHandler
+ IRQ MWU_IRQHandler
+ IRQ PWM1_IRQHandler
+ IRQ PWM2_IRQHandler
+ IRQ SPIM2_SPIS2_SPI2_IRQHandler
+ IRQ RTC2_IRQHandler
+ IRQ I2S_IRQHandler
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/90067c9a/hw/bsp/arduino_primo_nrf52/src/arch/cortex_m4/gcc_startup_nrf52_split.s
----------------------------------------------------------------------
diff --git a/hw/bsp/arduino_primo_nrf52/src/arch/cortex_m4/gcc_startup_nrf52_split.s b/hw/bsp/arduino_primo_nrf52/src/arch/cortex_m4/gcc_startup_nrf52_split.s
new file mode 100755
index 0000000..7426848
--- /dev/null
+++ b/hw/bsp/arduino_primo_nrf52/src/arch/cortex_m4/gcc_startup_nrf52_split.s
@@ -0,0 +1,150 @@
+/*
+Copyright (c) 2015, Nordic Semiconductor ASA
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+* Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+NOTE: Template files (including this one) are application specific and therefore
+expected to be copied into the application project folder prior to its use!
+*/
+
+ .syntax unified
+ .arch armv7-m
+ .section .stack
+ .align 3
+ .equ Stack_Size, 432
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector_split
+ .align 2
+ .globl __isr_vector_split
+__isr_vector_split:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler_split /* Reset Handler */
+
+ .size __isr_vector_split, . - __isr_vector_split
+
+/* Reset Handler */
+
+ .text
+ .thumb
+ .thumb_func
+ .align 1
+ .globl Reset_Handler_split
+ .type Reset_Handler_split, %function
+Reset_Handler_split:
+ .fnstart
+
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .LC0
+
+.LC1:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC1
+
+.LC0:
+ ldr r1, =__etext_loader
+ ldr r2, =__data_start___loader
+ ldr r3, =__data_end___loader
+
+ subs r3, r2
+ ble .LC2
+
+.LC3:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC3
+.LC2:
+
+ subs r0, r0
+ ldr r2, =__bss_start___loader
+ ldr r3, =__bss_end___loader
+
+ subs r3, r2
+ ble .LC4
+
+.LC5:
+ subs r3, 4
+ str r0, [r2,r3]
+ bgt .LC5
+.LC4:
+
+ LDR R0, =__HeapBase
+ LDR R1, =__HeapLimit
+ BL _sbrkInit
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =_start
+ BX R0
+
+ .pool
+ .cantunwind
+ .fnend
+ .size Reset_Handler_split,.-Reset_Handler_split
+
+ .section ".text"
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/90067c9a/hw/bsp/bmd300eval/src/arch/cortex_m4/gcc_startup_nrf52.s
----------------------------------------------------------------------
diff --git a/hw/bsp/bmd300eval/src/arch/cortex_m4/gcc_startup_nrf52.s b/hw/bsp/bmd300eval/src/arch/cortex_m4/gcc_startup_nrf52.s
new file mode 100755
index 0000000..fb804fd
--- /dev/null
+++ b/hw/bsp/bmd300eval/src/arch/cortex_m4/gcc_startup_nrf52.s
@@ -0,0 +1,289 @@
+/*
+Copyright (c) 2015, Nordic Semiconductor ASA
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+* Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+NOTE: Template files (including this one) are application specific and therefore
+expected to be copied into the application project folder prior to its use!
+*/
+
+ .syntax unified
+ .arch armv7-m
+
+ .section .stack
+ .align 3
+ .equ Stack_Size, 432
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External Interrupts */
+ .long POWER_CLOCK_IRQHandler
+ .long RADIO_IRQHandler
+ .long UARTE0_UART0_IRQHandler
+ .long SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+ .long SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+ .long NFCT_IRQHandler
+ .long GPIOTE_IRQHandler
+ .long SAADC_IRQHandler
+ .long TIMER0_IRQHandler
+ .long TIMER1_IRQHandler
+ .long TIMER2_IRQHandler
+ .long RTC0_IRQHandler
+ .long TEMP_IRQHandler
+ .long RNG_IRQHandler
+ .long ECB_IRQHandler
+ .long CCM_AAR_IRQHandler
+ .long WDT_IRQHandler
+ .long RTC1_IRQHandler
+ .long QDEC_IRQHandler
+ .long COMP_LPCOMP_IRQHandler
+ .long SWI0_EGU0_IRQHandler
+ .long SWI1_EGU1_IRQHandler
+ .long SWI2_EGU2_IRQHandler
+ .long SWI3_EGU3_IRQHandler
+ .long SWI4_EGU4_IRQHandler
+ .long SWI5_EGU5_IRQHandler
+ .long TIMER3_IRQHandler
+ .long TIMER4_IRQHandler
+ .long PWM0_IRQHandler
+ .long PDM_IRQHandler
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long MWU_IRQHandler
+ .long PWM1_IRQHandler
+ .long PWM2_IRQHandler
+ .long SPIM2_SPIS2_SPI2_IRQHandler
+ .long RTC2_IRQHandler
+ .long I2S_IRQHandler
+
+ .size __isr_vector, . - __isr_vector
+
+/* Reset Handler */
+
+ .text
+ .thumb
+ .thumb_func
+ .align 1
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ .fnstart
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .LC0
+
+.LC1:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC1
+
+.LC0:
+
+ LDR R0, =__HeapBase
+ LDR R1, =__HeapLimit
+ BL _sbrkInit
+
+ LDR R0, =SystemInit
+ BLX R0
+
+ LDR R0, =_start
+ BX R0
+
+ .pool
+ .cantunwind
+ .fnend
+ .size Reset_Handler,.-Reset_Handler
+
+ .section ".text"
+
+
+/* Dummy Exception Handlers (infinite loops which can be modified) */
+
+ .weak NMI_Handler
+ .type NMI_Handler, %function
+NMI_Handler:
+ B .
+ .size NMI_Handler, . - NMI_Handler
+
+
+ .weak HardFault_Handler
+ .type HardFault_Handler, %function
+HardFault_Handler:
+ B .
+ .size HardFault_Handler, . - HardFault_Handler
+
+
+ .weak MemoryManagement_Handler
+ .type MemoryManagement_Handler, %function
+MemoryManagement_Handler:
+ B .
+ .size MemoryManagement_Handler, . - MemoryManagement_Handler
+
+
+ .weak BusFault_Handler
+ .type BusFault_Handler, %function
+BusFault_Handler:
+ B .
+ .size BusFault_Handler, . - BusFault_Handler
+
+
+ .weak UsageFault_Handler
+ .type UsageFault_Handler, %function
+UsageFault_Handler:
+ B .
+ .size UsageFault_Handler, . - UsageFault_Handler
+
+
+ .weak SVC_Handler
+ .type SVC_Handler, %function
+SVC_Handler:
+ B .
+ .size SVC_Handler, . - SVC_Handler
+
+
+ .weak PendSV_Handler
+ .type PendSV_Handler, %function
+PendSV_Handler:
+ B .
+ .size PendSV_Handler, . - PendSV_Handler
+
+
+ .weak SysTick_Handler
+ .type SysTick_Handler, %function
+SysTick_Handler:
+ B .
+ .size SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+ .globl Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ B .
+ .size Default_Handler, . - Default_Handler
+
+ .macro IRQ handler
+ .weak \handler
+ .set \handler, Default_Handler
+ .endm
+
+ IRQ POWER_CLOCK_IRQHandler
+ IRQ RADIO_IRQHandler
+ IRQ UARTE0_UART0_IRQHandler
+ IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+ IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+ IRQ NFCT_IRQHandler
+ IRQ GPIOTE_IRQHandler
+ IRQ SAADC_IRQHandler
+ IRQ TIMER0_IRQHandler
+ IRQ TIMER1_IRQHandler
+ IRQ TIMER2_IRQHandler
+ IRQ RTC0_IRQHandler
+ IRQ TEMP_IRQHandler
+ IRQ RNG_IRQHandler
+ IRQ ECB_IRQHandler
+ IRQ CCM_AAR_IRQHandler
+ IRQ WDT_IRQHandler
+ IRQ RTC1_IRQHandler
+ IRQ QDEC_IRQHandler
+ IRQ COMP_LPCOMP_IRQHandler
+ IRQ SWI0_EGU0_IRQHandler
+ IRQ SWI1_EGU1_IRQHandler
+ IRQ SWI2_EGU2_IRQHandler
+ IRQ SWI3_EGU3_IRQHandler
+ IRQ SWI4_EGU4_IRQHandler
+ IRQ SWI5_EGU5_IRQHandler
+ IRQ TIMER3_IRQHandler
+ IRQ TIMER4_IRQHandler
+ IRQ PWM0_IRQHandler
+ IRQ PDM_IRQHandler
+ IRQ MWU_IRQHandler
+ IRQ PWM1_IRQHandler
+ IRQ PWM2_IRQHandler
+ IRQ SPIM2_SPIS2_SPI2_IRQHandler
+ IRQ RTC2_IRQHandler
+ IRQ I2S_IRQHandler
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/90067c9a/hw/bsp/bmd300eval/src/arch/cortex_m4/gcc_startup_nrf52_split.s
----------------------------------------------------------------------
diff --git a/hw/bsp/bmd300eval/src/arch/cortex_m4/gcc_startup_nrf52_split.s b/hw/bsp/bmd300eval/src/arch/cortex_m4/gcc_startup_nrf52_split.s
new file mode 100755
index 0000000..7426848
--- /dev/null
+++ b/hw/bsp/bmd300eval/src/arch/cortex_m4/gcc_startup_nrf52_split.s
@@ -0,0 +1,150 @@
+/*
+Copyright (c) 2015, Nordic Semiconductor ASA
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+* Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+NOTE: Template files (including this one) are application specific and therefore
+expected to be copied into the application project folder prior to its use!
+*/
+
+ .syntax unified
+ .arch armv7-m
+ .section .stack
+ .align 3
+ .equ Stack_Size, 432
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector_split
+ .align 2
+ .globl __isr_vector_split
+__isr_vector_split:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler_split /* Reset Handler */
+
+ .size __isr_vector_split, . - __isr_vector_split
+
+/* Reset Handler */
+
+ .text
+ .thumb
+ .thumb_func
+ .align 1
+ .globl Reset_Handler_split
+ .type Reset_Handler_split, %function
+Reset_Handler_split:
+ .fnstart
+
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .LC0
+
+.LC1:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC1
+
+.LC0:
+ ldr r1, =__etext_loader
+ ldr r2, =__data_start___loader
+ ldr r3, =__data_end___loader
+
+ subs r3, r2
+ ble .LC2
+
+.LC3:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC3
+.LC2:
+
+ subs r0, r0
+ ldr r2, =__bss_start___loader
+ ldr r3, =__bss_end___loader
+
+ subs r3, r2
+ ble .LC4
+
+.LC5:
+ subs r3, 4
+ str r0, [r2,r3]
+ bgt .LC5
+.LC4:
+
+ LDR R0, =__HeapBase
+ LDR R1, =__HeapLimit
+ BL _sbrkInit
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =_start
+ BX R0
+
+ .pool
+ .cantunwind
+ .fnend
+ .size Reset_Handler_split,.-Reset_Handler_split
+
+ .section ".text"
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/90067c9a/hw/bsp/nrf51-arduino_101/src/arch/cortex_m0/gcc_startup_nrf51.s
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf51-arduino_101/src/arch/cortex_m0/gcc_startup_nrf51.s b/hw/bsp/nrf51-arduino_101/src/arch/cortex_m0/gcc_startup_nrf51.s
new file mode 100755
index 0000000..89fcf6d
--- /dev/null
+++ b/hw/bsp/nrf51-arduino_101/src/arch/cortex_m0/gcc_startup_nrf51.s
@@ -0,0 +1,267 @@
+/*
+Copyright (c) 2015, Nordic Semiconductor ASA
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+* Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+NOTE: Template files (including this one) are application specific and therefore
+expected to be copied into the application project folder prior to its use!
+*/
+
+ .syntax unified
+ .arch armv6-m
+
+ .section .stack
+ .align 3
+ .equ Stack_Size, 384
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long _NMI_Handler /* NMI Handler */
+ .long _HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long _SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long _PendSV_Handler /* PendSV Handler */
+ .long _SysTick_Handler /* SysTick Handler */
+
+ /* External Interrupts */
+ .long _POWER_CLOCK_IRQHandler
+ .long _RADIO_IRQHandler
+ .long _UART0_IRQHandler
+ .long _SPI0_TWI0_IRQHandler
+ .long _SPI1_TWI1_IRQHandler
+ .long 0 /*Reserved */
+ .long _GPIOTE_IRQHandler
+ .long _ADC_IRQHandler
+ .long _TIMER0_IRQHandler
+ .long _TIMER1_IRQHandler
+ .long _TIMER2_IRQHandler
+ .long _RTC0_IRQHandler
+ .long _TEMP_IRQHandler
+ .long _RNG_IRQHandler
+ .long _ECB_IRQHandler
+ .long _CCM_AAR_IRQHandler
+ .long _WDT_IRQHandler
+ .long _RTC1_IRQHandler
+ .long _QDEC_IRQHandler
+ .long _LPCOMP_IRQHandler
+ .long _SWI0_IRQHandler
+ .long _SWI1_IRQHandler
+ .long _SWI2_IRQHandler
+ .long _SWI3_IRQHandler
+ .long _SWI4_IRQHandler
+ .long _SWI5_IRQHandler
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+
+ .size __isr_vector, . - __isr_vector
+
+/* Reset Handler */
+
+ .equ NRF_POWER_RAMON_ADDRESS, 0x40000524
+ .equ NRF_POWER_RAMONB_ADDRESS, 0x40000554
+ .equ NRF_POWER_RAMONx_RAMxON_ONMODE_Msk, 0x3
+
+ .text
+ .thumb
+ .thumb_func
+ .align 1
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ .fnstart
+
+/* Make sure ALL RAM banks are powered on */
+ MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
+
+ LDR R0, =NRF_POWER_RAMON_ADDRESS
+ LDR R2, [R0]
+ ORRS R2, R1
+ STR R2, [R0]
+
+ LDR R0, =NRF_POWER_RAMONB_ADDRESS
+ LDR R2, [R0]
+ ORRS R2, R1
+ STR R2, [R0]
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .LC0
+
+.LC1:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC1
+.LC0:
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =_start
+ BX R0
+
+ .pool
+ .cantunwind
+ .fnend
+ .size Reset_Handler,.-Reset_Handler
+
+ .section ".text"
+
+
+/* Dummy Exception Handlers (infinite loops which can be modified) */
+
+ .weak NMI_Handler
+ .type NMI_Handler, %function
+NMI_Handler:
+ B .
+ .size NMI_Handler, . - NMI_Handler
+
+ .weak SVC_Handler
+ .type SVC_Handler, %function
+SVC_Handler:
+ B .
+ .size SVC_Handler, . - SVC_Handler
+
+
+ .weak PendSV_Handler
+ .type PendSV_Handler, %function
+PendSV_Handler:
+ B .
+ .size PendSV_Handler, . - PendSV_Handler
+
+
+ .weak SysTick_Handler
+ .type SysTick_Handler, %function
+SysTick_Handler:
+ B .
+ .size SysTick_Handler, . - SysTick_Handler
+
+/* Default handler. This uses the vector in the relocated vector table */
+ .globl Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ LDR R2, =__vector_tbl_reloc__
+ MRS R0, PSR
+ MOVS R1, #0x3F
+ ANDS R0, R1
+ LSLS R0, R0, #2
+ LDR R0, [R0, R2]
+ BX R0
+ .size Default_Handler, . - Default_Handler
+
+/*
+ * All of the following IRQ Handlers will point to the default handler unless
+ * they are defined elsewhere.
+ */
+ .macro IRQ handler
+ .weak \handler
+ .set \handler, Default_Handler
+ .endm
+
+ IRQ _NMI_Handler
+ IRQ _HardFault_Handler
+ IRQ _SVC_Handler
+ IRQ _PendSV_Handler
+ IRQ _SysTick_Handler
+ IRQ _POWER_CLOCK_IRQHandler
+ IRQ _RADIO_IRQHandler
+ IRQ _UART0_IRQHandler
+ IRQ _SPI0_TWI0_IRQHandler
+ IRQ _SPI1_TWI1_IRQHandler
+ IRQ _GPIOTE_IRQHandler
+ IRQ _ADC_IRQHandler
+ IRQ _TIMER0_IRQHandler
+ IRQ _TIMER1_IRQHandler
+ IRQ _TIMER2_IRQHandler
+ IRQ _RTC0_IRQHandler
+ IRQ _TEMP_IRQHandler
+ IRQ _RNG_IRQHandler
+ IRQ _ECB_IRQHandler
+ IRQ _CCM_AAR_IRQHandler
+ IRQ _WDT_IRQHandler
+ IRQ _RTC1_IRQHandler
+ IRQ _QDEC_IRQHandler
+ IRQ _LPCOMP_IRQHandler
+ IRQ _SWI0_IRQHandler
+ IRQ _SWI1_IRQHandler
+ IRQ _SWI2_IRQHandler
+ IRQ _SWI3_IRQHandler
+ IRQ _SWI4_IRQHandler
+ IRQ _SWI5_IRQHandler
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/90067c9a/hw/bsp/nrf51-arduino_101/src/sbrk.c
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf51-arduino_101/src/sbrk.c b/hw/bsp/nrf51-arduino_101/src/sbrk.c
index 5df43c9..cee2590 100644
--- a/hw/bsp/nrf51-arduino_101/src/sbrk.c
+++ b/hw/bsp/nrf51-arduino_101/src/sbrk.c
@@ -17,20 +17,10 @@
* under the License.
*/
-#include <hal/hal_bsp.h>
-
-/* put these in the data section so they are not cleared by _start */
-static char *sbrkBase __attribute__ ((section (".data")));
-static char *sbrkLimit __attribute__ ((section (".data")));
-static char *brk __attribute__ ((section (".data")));
-
-void
-_sbrkInit(char *base, char *limit) {
- sbrkBase = base;
- sbrkLimit = limit;
- brk = base;
-}
+extern char __HeapBase;
+extern char __HeapLimit;
+static char *brk = &__HeapBase;
void *
_sbrk(int incr)
{
@@ -39,7 +29,7 @@ _sbrk(int incr)
if (incr < 0) {
/* Returning memory to the heap. */
incr = -incr;
- if (brk - incr < sbrkBase) {
+ if (brk - incr < &__HeapBase) {
prev_brk = (void *)-1;
} else {
prev_brk = brk;
@@ -47,7 +37,7 @@ _sbrk(int incr)
}
} else {
/* Allocating memory from the heap. */
- if (sbrkLimit - brk >= incr) {
+ if (&__HeapLimit - brk >= incr) {
prev_brk = brk;
brk += incr;
} else {
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/90067c9a/hw/bsp/nrf51-blenano/src/arch/cortex_m0/gcc_startup_nrf51.s
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf51-blenano/src/arch/cortex_m0/gcc_startup_nrf51.s b/hw/bsp/nrf51-blenano/src/arch/cortex_m0/gcc_startup_nrf51.s
new file mode 100755
index 0000000..e4a887b
--- /dev/null
+++ b/hw/bsp/nrf51-blenano/src/arch/cortex_m0/gcc_startup_nrf51.s
@@ -0,0 +1,270 @@
+/*
+Copyright (c) 2015, Nordic Semiconductor ASA
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+* Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+NOTE: Template files (including this one) are application specific and therefore
+expected to be copied into the application project folder prior to its use!
+*/
+
+ .syntax unified
+ .arch armv6-m
+
+ .section .stack
+ .align 3
+ .equ Stack_Size, 432
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long _NMI_Handler /* NMI Handler */
+ .long _HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long _SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long _PendSV_Handler /* PendSV Handler */
+ .long _SysTick_Handler /* SysTick Handler */
+
+ /* External Interrupts */
+ .long _POWER_CLOCK_IRQHandler
+ .long _RADIO_IRQHandler
+ .long _UART0_IRQHandler
+ .long _SPI0_TWI0_IRQHandler
+ .long _SPI1_TWI1_IRQHandler
+ .long 0 /*Reserved */
+ .long _GPIOTE_IRQHandler
+ .long _ADC_IRQHandler
+ .long _TIMER0_IRQHandler
+ .long _TIMER1_IRQHandler
+ .long _TIMER2_IRQHandler
+ .long _RTC0_IRQHandler
+ .long _TEMP_IRQHandler
+ .long _RNG_IRQHandler
+ .long _ECB_IRQHandler
+ .long _CCM_AAR_IRQHandler
+ .long _WDT_IRQHandler
+ .long _RTC1_IRQHandler
+ .long _QDEC_IRQHandler
+ .long _LPCOMP_IRQHandler
+ .long _SWI0_IRQHandler
+ .long _SWI1_IRQHandler
+ .long _SWI2_IRQHandler
+ .long _SWI3_IRQHandler
+ .long _SWI4_IRQHandler
+ .long _SWI5_IRQHandler
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+
+ .size __isr_vector, . - __isr_vector
+
+/* Reset Handler */
+
+ .equ NRF_POWER_RAMON_ADDRESS, 0x40000524
+ .equ NRF_POWER_RAMONB_ADDRESS, 0x40000554
+ .equ NRF_POWER_RAMONx_RAMxON_ONMODE_Msk, 0x3
+
+ .text
+ .thumb
+ .thumb_func
+ .align 1
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ .fnstart
+
+/* Make sure ALL RAM banks are powered on */
+ MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
+
+ LDR R0, =NRF_POWER_RAMON_ADDRESS
+ LDR R2, [R0]
+ ORRS R2, R1
+ STR R2, [R0]
+
+ LDR R0, =NRF_POWER_RAMONB_ADDRESS
+ LDR R2, [R0]
+ ORRS R2, R1
+ STR R2, [R0]
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .LC0
+
+.LC1:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC1
+.LC0:
+ LDR R0, =__HeapBase
+ LDR R1, =__HeapLimit
+ BL _sbrkInit
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =_start
+ BX R0
+
+ .pool
+ .cantunwind
+ .fnend
+ .size Reset_Handler,.-Reset_Handler
+
+ .section ".text"
+
+
+/* Dummy Exception Handlers (infinite loops which can be modified) */
+
+ .weak NMI_Handler
+ .type NMI_Handler, %function
+NMI_Handler:
+ B .
+ .size NMI_Handler, . - NMI_Handler
+
+ .weak SVC_Handler
+ .type SVC_Handler, %function
+SVC_Handler:
+ B .
+ .size SVC_Handler, . - SVC_Handler
+
+
+ .weak PendSV_Handler
+ .type PendSV_Handler, %function
+PendSV_Handler:
+ B .
+ .size PendSV_Handler, . - PendSV_Handler
+
+
+ .weak SysTick_Handler
+ .type SysTick_Handler, %function
+SysTick_Handler:
+ B .
+ .size SysTick_Handler, . - SysTick_Handler
+
+/* Default handler. This uses the vector in the relocated vector table */
+ .globl Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ LDR R2, =__vector_tbl_reloc__
+ MRS R0, PSR
+ MOVS R1, #0x3F
+ ANDS R0, R1
+ LSLS R0, R0, #2
+ LDR R0, [R0, R2]
+ BX R0
+ .size Default_Handler, . - Default_Handler
+
+/*
+ * All of the following IRQ Handlers will point to the default handler unless
+ * they are defined elsewhere.
+ */
+ .macro IRQ handler
+ .weak \handler
+ .set \handler, Default_Handler
+ .endm
+
+ IRQ _NMI_Handler
+ IRQ _HardFault_Handler
+ IRQ _SVC_Handler
+ IRQ _PendSV_Handler
+ IRQ _SysTick_Handler
+ IRQ _POWER_CLOCK_IRQHandler
+ IRQ _RADIO_IRQHandler
+ IRQ _UART0_IRQHandler
+ IRQ _SPI0_TWI0_IRQHandler
+ IRQ _SPI1_TWI1_IRQHandler
+ IRQ _GPIOTE_IRQHandler
+ IRQ _ADC_IRQHandler
+ IRQ _TIMER0_IRQHandler
+ IRQ _TIMER1_IRQHandler
+ IRQ _TIMER2_IRQHandler
+ IRQ _RTC0_IRQHandler
+ IRQ _TEMP_IRQHandler
+ IRQ _RNG_IRQHandler
+ IRQ _ECB_IRQHandler
+ IRQ _CCM_AAR_IRQHandler
+ IRQ _WDT_IRQHandler
+ IRQ _RTC1_IRQHandler
+ IRQ _QDEC_IRQHandler
+ IRQ _LPCOMP_IRQHandler
+ IRQ _SWI0_IRQHandler
+ IRQ _SWI1_IRQHandler
+ IRQ _SWI2_IRQHandler
+ IRQ _SWI3_IRQHandler
+ IRQ _SWI4_IRQHandler
+ IRQ _SWI5_IRQHandler
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/90067c9a/hw/bsp/nrf51-blenano/src/arch/cortex_m0/gcc_startup_nrf51_split.s
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf51-blenano/src/arch/cortex_m0/gcc_startup_nrf51_split.s b/hw/bsp/nrf51-blenano/src/arch/cortex_m0/gcc_startup_nrf51_split.s
new file mode 100755
index 0000000..ed5f207
--- /dev/null
+++ b/hw/bsp/nrf51-blenano/src/arch/cortex_m0/gcc_startup_nrf51_split.s
@@ -0,0 +1,166 @@
+/*
+Copyright (c) 2015, Nordic Semiconductor ASA
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+* Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+NOTE: Template files (including this one) are application specific and therefore
+expected to be copied into the application project folder prior to its use!
+*/
+
+ .syntax unified
+ .arch armv6-m
+
+ .section .stack
+ .align 3
+ .equ Stack_Size, 432
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector_split
+ .align 2
+ .globl __isr_vector_split
+__isr_vector_split:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler_split /* Reset Handler */
+
+ .size __isr_vector_split, . - __isr_vector_split
+
+/* Reset Handler */
+
+ .equ NRF_POWER_RAMON_ADDRESS, 0x40000524
+ .equ NRF_POWER_RAMONB_ADDRESS, 0x40000554
+ .equ NRF_POWER_RAMONx_RAMxON_ONMODE_Msk, 0x3
+
+ .text
+ .thumb
+ .thumb_func
+ .align 1
+ .globl Reset_Handler_split
+ .type Reset_Handler_split, %function
+Reset_Handler_split:
+ .fnstart
+
+/* Make sure ALL RAM banks are powered on */
+ MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
+
+ LDR R0, =NRF_POWER_RAMON_ADDRESS
+ LDR R2, [R0]
+ ORRS R2, R1
+ STR R2, [R0]
+
+ LDR R0, =NRF_POWER_RAMONB_ADDRESS
+ LDR R2, [R0]
+ ORRS R2, R1
+ STR R2, [R0]
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .LC0
+
+.LC1:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC1
+.LC0:
+ ldr r1, =__etext_loader
+ ldr r2, =__data_start___loader
+ ldr r3, =__data_end___loader
+
+ subs r3, r2
+ ble .LC2
+
+.LC3:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC3
+.LC2:
+
+ subs r0, r0
+ ldr r2, =__bss_start___loader
+ ldr r3, =__bss_end___loader
+
+ subs r3, r2
+ ble .LC4
+
+.LC5:
+ subs r3, 4
+ str r0, [r2,r3]
+ bgt .LC5
+.LC4:
+ LDR R0, =__HeapBase
+ LDR R1, =__HeapLimit
+ BL _sbrkInit
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =_start
+ BX R0
+
+ .pool
+ .cantunwind
+ .fnend
+ .size Reset_Handler_split,.-Reset_Handler_split
+
+ .section ".text"
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/90067c9a/hw/bsp/nrf51dk-16kbram/src/arch/cortex_m0/gcc_startup_nrf51.s
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf51dk-16kbram/src/arch/cortex_m0/gcc_startup_nrf51.s b/hw/bsp/nrf51dk-16kbram/src/arch/cortex_m0/gcc_startup_nrf51.s
new file mode 100755
index 0000000..73c6265
--- /dev/null
+++ b/hw/bsp/nrf51dk-16kbram/src/arch/cortex_m0/gcc_startup_nrf51.s
@@ -0,0 +1,270 @@
+/*
+Copyright (c) 2015, Nordic Semiconductor ASA
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+* Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+NOTE: Template files (including this one) are application specific and therefore
+expected to be copied into the application project folder prior to its use!
+*/
+
+ .syntax unified
+ .arch armv6-m
+
+ .section .stack
+ .align 3
+ .equ Stack_Size, 384
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long _NMI_Handler /* NMI Handler */
+ .long _HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long _SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long _PendSV_Handler /* PendSV Handler */
+ .long _SysTick_Handler /* SysTick Handler */
+
+ /* External Interrupts */
+ .long _POWER_CLOCK_IRQHandler
+ .long _RADIO_IRQHandler
+ .long _UART0_IRQHandler
+ .long _SPI0_TWI0_IRQHandler
+ .long _SPI1_TWI1_IRQHandler
+ .long 0 /*Reserved */
+ .long _GPIOTE_IRQHandler
+ .long _ADC_IRQHandler
+ .long _TIMER0_IRQHandler
+ .long _TIMER1_IRQHandler
+ .long _TIMER2_IRQHandler
+ .long _RTC0_IRQHandler
+ .long _TEMP_IRQHandler
+ .long _RNG_IRQHandler
+ .long _ECB_IRQHandler
+ .long _CCM_AAR_IRQHandler
+ .long _WDT_IRQHandler
+ .long _RTC1_IRQHandler
+ .long _QDEC_IRQHandler
+ .long _LPCOMP_IRQHandler
+ .long _SWI0_IRQHandler
+ .long _SWI1_IRQHandler
+ .long _SWI2_IRQHandler
+ .long _SWI3_IRQHandler
+ .long _SWI4_IRQHandler
+ .long _SWI5_IRQHandler
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+
+ .size __isr_vector, . - __isr_vector
+
+/* Reset Handler */
+
+ .equ NRF_POWER_RAMON_ADDRESS, 0x40000524
+ .equ NRF_POWER_RAMONB_ADDRESS, 0x40000554
+ .equ NRF_POWER_RAMONx_RAMxON_ONMODE_Msk, 0x3
+
+ .text
+ .thumb
+ .thumb_func
+ .align 1
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ .fnstart
+
+/* Make sure ALL RAM banks are powered on */
+ MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
+
+ LDR R0, =NRF_POWER_RAMON_ADDRESS
+ LDR R2, [R0]
+ ORRS R2, R1
+ STR R2, [R0]
+
+ LDR R0, =NRF_POWER_RAMONB_ADDRESS
+ LDR R2, [R0]
+ ORRS R2, R1
+ STR R2, [R0]
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .LC0
+
+.LC1:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC1
+.LC0:
+ LDR R0, =__HeapBase
+ LDR R1, =__HeapLimit
+ BL _sbrkInit
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =_start
+ BX R0
+
+ .pool
+ .cantunwind
+ .fnend
+ .size Reset_Handler,.-Reset_Handler
+
+ .section ".text"
+
+
+/* Dummy Exception Handlers (infinite loops which can be modified) */
+
+ .weak NMI_Handler
+ .type NMI_Handler, %function
+NMI_Handler:
+ B .
+ .size NMI_Handler, . - NMI_Handler
+
+ .weak SVC_Handler
+ .type SVC_Handler, %function
+SVC_Handler:
+ B .
+ .size SVC_Handler, . - SVC_Handler
+
+
+ .weak PendSV_Handler
+ .type PendSV_Handler, %function
+PendSV_Handler:
+ B .
+ .size PendSV_Handler, . - PendSV_Handler
+
+
+ .weak SysTick_Handler
+ .type SysTick_Handler, %function
+SysTick_Handler:
+ B .
+ .size SysTick_Handler, . - SysTick_Handler
+
+/* Default handler. This uses the vector in the relocated vector table */
+ .globl Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ LDR R2, =__vector_tbl_reloc__
+ MRS R0, PSR
+ MOVS R1, #0x3F
+ ANDS R0, R1
+ LSLS R0, R0, #2
+ LDR R0, [R0, R2]
+ BX R0
+ .size Default_Handler, . - Default_Handler
+
+/*
+ * All of the following IRQ Handlers will point to the default handler unless
+ * they are defined elsewhere.
+ */
+ .macro IRQ handler
+ .weak \handler
+ .set \handler, Default_Handler
+ .endm
+
+ IRQ _NMI_Handler
+ IRQ _HardFault_Handler
+ IRQ _SVC_Handler
+ IRQ _PendSV_Handler
+ IRQ _SysTick_Handler
+ IRQ _POWER_CLOCK_IRQHandler
+ IRQ _RADIO_IRQHandler
+ IRQ _UART0_IRQHandler
+ IRQ _SPI0_TWI0_IRQHandler
+ IRQ _SPI1_TWI1_IRQHandler
+ IRQ _GPIOTE_IRQHandler
+ IRQ _ADC_IRQHandler
+ IRQ _TIMER0_IRQHandler
+ IRQ _TIMER1_IRQHandler
+ IRQ _TIMER2_IRQHandler
+ IRQ _RTC0_IRQHandler
+ IRQ _TEMP_IRQHandler
+ IRQ _RNG_IRQHandler
+ IRQ _ECB_IRQHandler
+ IRQ _CCM_AAR_IRQHandler
+ IRQ _WDT_IRQHandler
+ IRQ _RTC1_IRQHandler
+ IRQ _QDEC_IRQHandler
+ IRQ _LPCOMP_IRQHandler
+ IRQ _SWI0_IRQHandler
+ IRQ _SWI1_IRQHandler
+ IRQ _SWI2_IRQHandler
+ IRQ _SWI3_IRQHandler
+ IRQ _SWI4_IRQHandler
+ IRQ _SWI5_IRQHandler
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/90067c9a/hw/bsp/nrf51dk-16kbram/src/arch/cortex_m0/gcc_startup_nrf51_split.s
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf51dk-16kbram/src/arch/cortex_m0/gcc_startup_nrf51_split.s b/hw/bsp/nrf51dk-16kbram/src/arch/cortex_m0/gcc_startup_nrf51_split.s
new file mode 100755
index 0000000..e44c725
--- /dev/null
+++ b/hw/bsp/nrf51dk-16kbram/src/arch/cortex_m0/gcc_startup_nrf51_split.s
@@ -0,0 +1,166 @@
+/*
+Copyright (c) 2015, Nordic Semiconductor ASA
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+* Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+NOTE: Template files (including this one) are application specific and therefore
+expected to be copied into the application project folder prior to its use!
+*/
+
+ .syntax unified
+ .arch armv6-m
+
+ .section .stack
+ .align 3
+ .equ Stack_Size, 384
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector_split
+ .align 2
+ .globl __isr_vector_split
+__isr_vector_split:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler_split /* Reset Handler */
+
+ .size __isr_vector_split, . - __isr_vector_split
+
+/* Reset Handler */
+
+ .equ NRF_POWER_RAMON_ADDRESS, 0x40000524
+ .equ NRF_POWER_RAMONB_ADDRESS, 0x40000554
+ .equ NRF_POWER_RAMONx_RAMxON_ONMODE_Msk, 0x3
+
+ .text
+ .thumb
+ .thumb_func
+ .align 1
+ .globl Reset_Handler_split
+ .type Reset_Handler_split, %function
+Reset_Handler_split:
+ .fnstart
+
+/* Make sure ALL RAM banks are powered on */
+ MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
+
+ LDR R0, =NRF_POWER_RAMON_ADDRESS
+ LDR R2, [R0]
+ ORRS R2, R1
+ STR R2, [R0]
+
+ LDR R0, =NRF_POWER_RAMONB_ADDRESS
+ LDR R2, [R0]
+ ORRS R2, R1
+ STR R2, [R0]
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .LC0
+
+.LC1:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC1
+.LC0:
+ ldr r1, =__etext_loader
+ ldr r2, =__data_start___loader
+ ldr r3, =__data_end___loader
+
+ subs r3, r2
+ ble .LC2
+
+.LC3:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC3
+.LC2:
+
+ subs r0, r0
+ ldr r2, =__bss_start___loader
+ ldr r3, =__bss_end___loader
+
+ subs r3, r2
+ ble .LC4
+
+.LC5:
+ subs r3, 4
+ str r0, [r2,r3]
+ bgt .LC5
+.LC4:
+ LDR R0, =__HeapBase
+ LDR R1, =__HeapLimit
+ BL _sbrkInit
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =_start
+ BX R0
+
+ .pool
+ .cantunwind
+ .fnend
+ .size Reset_Handler_split,.-Reset_Handler_split
+
+ .section ".text"
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/90067c9a/hw/bsp/nrf51dk/src/arch/cortex_m0/gcc_startup_nrf51.s
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf51dk/src/arch/cortex_m0/gcc_startup_nrf51.s b/hw/bsp/nrf51dk/src/arch/cortex_m0/gcc_startup_nrf51.s
new file mode 100755
index 0000000..fbc88bd
--- /dev/null
+++ b/hw/bsp/nrf51dk/src/arch/cortex_m0/gcc_startup_nrf51.s
@@ -0,0 +1,270 @@
+/*
+Copyright (c) 2015, Nordic Semiconductor ASA
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+* Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+NOTE: Template files (including this one) are application specific and therefore
+expected to be copied into the application project folder prior to its use!
+*/
+
+ .syntax unified
+ .arch armv6-m
+
+ .section .stack
+ .align 3
+ .equ Stack_Size, 432
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long _NMI_Handler /* NMI Handler */
+ .long _HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long _SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long _PendSV_Handler /* PendSV Handler */
+ .long _SysTick_Handler /* SysTick Handler */
+
+ /* External Interrupts */
+ .long _POWER_CLOCK_IRQHandler
+ .long _RADIO_IRQHandler
+ .long _UART0_IRQHandler
+ .long _SPI0_TWI0_IRQHandler
+ .long _SPI1_TWI1_IRQHandler
+ .long 0 /*Reserved */
+ .long _GPIOTE_IRQHandler
+ .long ADC_IRQHandler
+ .long _TIMER0_IRQHandler
+ .long _TIMER1_IRQHandler
+ .long _TIMER2_IRQHandler
+ .long _RTC0_IRQHandler
+ .long _TEMP_IRQHandler
+ .long _RNG_IRQHandler
+ .long _ECB_IRQHandler
+ .long _CCM_AAR_IRQHandler
+ .long _WDT_IRQHandler
+ .long _RTC1_IRQHandler
+ .long _QDEC_IRQHandler
+ .long _LPCOMP_IRQHandler
+ .long _SWI0_IRQHandler
+ .long _SWI1_IRQHandler
+ .long _SWI2_IRQHandler
+ .long _SWI3_IRQHandler
+ .long _SWI4_IRQHandler
+ .long _SWI5_IRQHandler
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+
+ .size __isr_vector, . - __isr_vector
+
+/* Reset Handler */
+
+ .equ NRF_POWER_RAMON_ADDRESS, 0x40000524
+ .equ NRF_POWER_RAMONB_ADDRESS, 0x40000554
+ .equ NRF_POWER_RAMONx_RAMxON_ONMODE_Msk, 0x3
+
+ .text
+ .thumb
+ .thumb_func
+ .align 1
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ .fnstart
+
+/* Make sure ALL RAM banks are powered on */
+ MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
+
+ LDR R0, =NRF_POWER_RAMON_ADDRESS
+ LDR R2, [R0]
+ ORRS R2, R1
+ STR R2, [R0]
+
+ LDR R0, =NRF_POWER_RAMONB_ADDRESS
+ LDR R2, [R0]
+ ORRS R2, R1
+ STR R2, [R0]
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .LC0
+
+.LC1:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC1
+.LC0:
+ LDR R0, =__HeapBase
+ LDR R1, =__HeapLimit
+ BL _sbrkInit
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =_start
+ BX R0
+
+ .pool
+ .cantunwind
+ .fnend
+ .size Reset_Handler,.-Reset_Handler
+
+ .section ".text"
+
+
+/* Dummy Exception Handlers (infinite loops which can be modified) */
+
+ .weak NMI_Handler
+ .type NMI_Handler, %function
+NMI_Handler:
+ B .
+ .size NMI_Handler, . - NMI_Handler
+
+ .weak SVC_Handler
+ .type SVC_Handler, %function
+SVC_Handler:
+ B .
+ .size SVC_Handler, . - SVC_Handler
+
+
+ .weak PendSV_Handler
+ .type PendSV_Handler, %function
+PendSV_Handler:
+ B .
+ .size PendSV_Handler, . - PendSV_Handler
+
+
+ .weak SysTick_Handler
+ .type SysTick_Handler, %function
+SysTick_Handler:
+ B .
+ .size SysTick_Handler, . - SysTick_Handler
+
+/* Default handler. This uses the vector in the relocated vector table */
+ .globl Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ LDR R2, =__vector_tbl_reloc__
+ MRS R0, PSR
+ MOVS R1, #0x3F
+ ANDS R0, R1
+ LSLS R0, R0, #2
+ LDR R0, [R0, R2]
+ BX R0
+ .size Default_Handler, . - Default_Handler
+
+/*
+ * All of the following IRQ Handlers will point to the default handler unless
+ * they are defined elsewhere.
+ */
+ .macro IRQ handler
+ .weak \handler
+ .set \handler, Default_Handler
+ .endm
+
+ IRQ _NMI_Handler
+ IRQ _HardFault_Handler
+ IRQ _SVC_Handler
+ IRQ _PendSV_Handler
+ IRQ _SysTick_Handler
+ IRQ _POWER_CLOCK_IRQHandler
+ IRQ _RADIO_IRQHandler
+ IRQ _UART0_IRQHandler
+ IRQ _SPI0_TWI0_IRQHandler
+ IRQ _SPI1_TWI1_IRQHandler
+ IRQ _GPIOTE_IRQHandler
+ IRQ ADC_IRQHandler
+ IRQ _TIMER0_IRQHandler
+ IRQ _TIMER1_IRQHandler
+ IRQ _TIMER2_IRQHandler
+ IRQ _RTC0_IRQHandler
+ IRQ _TEMP_IRQHandler
+ IRQ _RNG_IRQHandler
+ IRQ _ECB_IRQHandler
+ IRQ _CCM_AAR_IRQHandler
+ IRQ _WDT_IRQHandler
+ IRQ _RTC1_IRQHandler
+ IRQ _QDEC_IRQHandler
+ IRQ _LPCOMP_IRQHandler
+ IRQ _SWI0_IRQHandler
+ IRQ _SWI1_IRQHandler
+ IRQ _SWI2_IRQHandler
+ IRQ _SWI3_IRQHandler
+ IRQ _SWI4_IRQHandler
+ IRQ _SWI5_IRQHandler
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/90067c9a/hw/bsp/nrf51dk/src/arch/cortex_m0/gcc_startup_nrf51_split.s
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf51dk/src/arch/cortex_m0/gcc_startup_nrf51_split.s b/hw/bsp/nrf51dk/src/arch/cortex_m0/gcc_startup_nrf51_split.s
new file mode 100755
index 0000000..ed5f207
--- /dev/null
+++ b/hw/bsp/nrf51dk/src/arch/cortex_m0/gcc_startup_nrf51_split.s
@@ -0,0 +1,166 @@
+/*
+Copyright (c) 2015, Nordic Semiconductor ASA
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+* Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+NOTE: Template files (including this one) are application specific and therefore
+expected to be copied into the application project folder prior to its use!
+*/
+
+ .syntax unified
+ .arch armv6-m
+
+ .section .stack
+ .align 3
+ .equ Stack_Size, 432
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector_split
+ .align 2
+ .globl __isr_vector_split
+__isr_vector_split:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler_split /* Reset Handler */
+
+ .size __isr_vector_split, . - __isr_vector_split
+
+/* Reset Handler */
+
+ .equ NRF_POWER_RAMON_ADDRESS, 0x40000524
+ .equ NRF_POWER_RAMONB_ADDRESS, 0x40000554
+ .equ NRF_POWER_RAMONx_RAMxON_ONMODE_Msk, 0x3
+
+ .text
+ .thumb
+ .thumb_func
+ .align 1
+ .globl Reset_Handler_split
+ .type Reset_Handler_split, %function
+Reset_Handler_split:
+ .fnstart
+
+/* Make sure ALL RAM banks are powered on */
+ MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
+
+ LDR R0, =NRF_POWER_RAMON_ADDRESS
+ LDR R2, [R0]
+ ORRS R2, R1
+ STR R2, [R0]
+
+ LDR R0, =NRF_POWER_RAMONB_ADDRESS
+ LDR R2, [R0]
+ ORRS R2, R1
+ STR R2, [R0]
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .LC0
+
+.LC1:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC1
+.LC0:
+ ldr r1, =__etext_loader
+ ldr r2, =__data_start___loader
+ ldr r3, =__data_end___loader
+
+ subs r3, r2
+ ble .LC2
+
+.LC3:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC3
+.LC2:
+
+ subs r0, r0
+ ldr r2, =__bss_start___loader
+ ldr r3, =__bss_end___loader
+
+ subs r3, r2
+ ble .LC4
+
+.LC5:
+ subs r3, 4
+ str r0, [r2,r3]
+ bgt .LC5
+.LC4:
+ LDR R0, =__HeapBase
+ LDR R1, =__HeapLimit
+ BL _sbrkInit
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =_start
+ BX R0
+
+ .pool
+ .cantunwind
+ .fnend
+ .size Reset_Handler_split,.-Reset_Handler_split
+
+ .section ".text"
+
+ .end
[2/3] incubator-mynewt-core git commit: Move startup code back into
BSP pgks (from MCU).
Posted by cc...@apache.org.
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/90067c9a/hw/bsp/nrf52dk/src/arch/cortex_m4/gcc_startup_nrf52.s
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf52dk/src/arch/cortex_m4/gcc_startup_nrf52.s b/hw/bsp/nrf52dk/src/arch/cortex_m4/gcc_startup_nrf52.s
new file mode 100755
index 0000000..fb804fd
--- /dev/null
+++ b/hw/bsp/nrf52dk/src/arch/cortex_m4/gcc_startup_nrf52.s
@@ -0,0 +1,289 @@
+/*
+Copyright (c) 2015, Nordic Semiconductor ASA
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+* Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+NOTE: Template files (including this one) are application specific and therefore
+expected to be copied into the application project folder prior to its use!
+*/
+
+ .syntax unified
+ .arch armv7-m
+
+ .section .stack
+ .align 3
+ .equ Stack_Size, 432
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External Interrupts */
+ .long POWER_CLOCK_IRQHandler
+ .long RADIO_IRQHandler
+ .long UARTE0_UART0_IRQHandler
+ .long SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+ .long SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+ .long NFCT_IRQHandler
+ .long GPIOTE_IRQHandler
+ .long SAADC_IRQHandler
+ .long TIMER0_IRQHandler
+ .long TIMER1_IRQHandler
+ .long TIMER2_IRQHandler
+ .long RTC0_IRQHandler
+ .long TEMP_IRQHandler
+ .long RNG_IRQHandler
+ .long ECB_IRQHandler
+ .long CCM_AAR_IRQHandler
+ .long WDT_IRQHandler
+ .long RTC1_IRQHandler
+ .long QDEC_IRQHandler
+ .long COMP_LPCOMP_IRQHandler
+ .long SWI0_EGU0_IRQHandler
+ .long SWI1_EGU1_IRQHandler
+ .long SWI2_EGU2_IRQHandler
+ .long SWI3_EGU3_IRQHandler
+ .long SWI4_EGU4_IRQHandler
+ .long SWI5_EGU5_IRQHandler
+ .long TIMER3_IRQHandler
+ .long TIMER4_IRQHandler
+ .long PWM0_IRQHandler
+ .long PDM_IRQHandler
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long MWU_IRQHandler
+ .long PWM1_IRQHandler
+ .long PWM2_IRQHandler
+ .long SPIM2_SPIS2_SPI2_IRQHandler
+ .long RTC2_IRQHandler
+ .long I2S_IRQHandler
+
+ .size __isr_vector, . - __isr_vector
+
+/* Reset Handler */
+
+ .text
+ .thumb
+ .thumb_func
+ .align 1
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ .fnstart
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .LC0
+
+.LC1:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC1
+
+.LC0:
+
+ LDR R0, =__HeapBase
+ LDR R1, =__HeapLimit
+ BL _sbrkInit
+
+ LDR R0, =SystemInit
+ BLX R0
+
+ LDR R0, =_start
+ BX R0
+
+ .pool
+ .cantunwind
+ .fnend
+ .size Reset_Handler,.-Reset_Handler
+
+ .section ".text"
+
+
+/* Dummy Exception Handlers (infinite loops which can be modified) */
+
+ .weak NMI_Handler
+ .type NMI_Handler, %function
+NMI_Handler:
+ B .
+ .size NMI_Handler, . - NMI_Handler
+
+
+ .weak HardFault_Handler
+ .type HardFault_Handler, %function
+HardFault_Handler:
+ B .
+ .size HardFault_Handler, . - HardFault_Handler
+
+
+ .weak MemoryManagement_Handler
+ .type MemoryManagement_Handler, %function
+MemoryManagement_Handler:
+ B .
+ .size MemoryManagement_Handler, . - MemoryManagement_Handler
+
+
+ .weak BusFault_Handler
+ .type BusFault_Handler, %function
+BusFault_Handler:
+ B .
+ .size BusFault_Handler, . - BusFault_Handler
+
+
+ .weak UsageFault_Handler
+ .type UsageFault_Handler, %function
+UsageFault_Handler:
+ B .
+ .size UsageFault_Handler, . - UsageFault_Handler
+
+
+ .weak SVC_Handler
+ .type SVC_Handler, %function
+SVC_Handler:
+ B .
+ .size SVC_Handler, . - SVC_Handler
+
+
+ .weak PendSV_Handler
+ .type PendSV_Handler, %function
+PendSV_Handler:
+ B .
+ .size PendSV_Handler, . - PendSV_Handler
+
+
+ .weak SysTick_Handler
+ .type SysTick_Handler, %function
+SysTick_Handler:
+ B .
+ .size SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+ .globl Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ B .
+ .size Default_Handler, . - Default_Handler
+
+ .macro IRQ handler
+ .weak \handler
+ .set \handler, Default_Handler
+ .endm
+
+ IRQ POWER_CLOCK_IRQHandler
+ IRQ RADIO_IRQHandler
+ IRQ UARTE0_UART0_IRQHandler
+ IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+ IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+ IRQ NFCT_IRQHandler
+ IRQ GPIOTE_IRQHandler
+ IRQ SAADC_IRQHandler
+ IRQ TIMER0_IRQHandler
+ IRQ TIMER1_IRQHandler
+ IRQ TIMER2_IRQHandler
+ IRQ RTC0_IRQHandler
+ IRQ TEMP_IRQHandler
+ IRQ RNG_IRQHandler
+ IRQ ECB_IRQHandler
+ IRQ CCM_AAR_IRQHandler
+ IRQ WDT_IRQHandler
+ IRQ RTC1_IRQHandler
+ IRQ QDEC_IRQHandler
+ IRQ COMP_LPCOMP_IRQHandler
+ IRQ SWI0_EGU0_IRQHandler
+ IRQ SWI1_EGU1_IRQHandler
+ IRQ SWI2_EGU2_IRQHandler
+ IRQ SWI3_EGU3_IRQHandler
+ IRQ SWI4_EGU4_IRQHandler
+ IRQ SWI5_EGU5_IRQHandler
+ IRQ TIMER3_IRQHandler
+ IRQ TIMER4_IRQHandler
+ IRQ PWM0_IRQHandler
+ IRQ PDM_IRQHandler
+ IRQ MWU_IRQHandler
+ IRQ PWM1_IRQHandler
+ IRQ PWM2_IRQHandler
+ IRQ SPIM2_SPIS2_SPI2_IRQHandler
+ IRQ RTC2_IRQHandler
+ IRQ I2S_IRQHandler
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/90067c9a/hw/bsp/nrf52dk/src/arch/cortex_m4/gcc_startup_nrf52_split.s
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf52dk/src/arch/cortex_m4/gcc_startup_nrf52_split.s b/hw/bsp/nrf52dk/src/arch/cortex_m4/gcc_startup_nrf52_split.s
new file mode 100755
index 0000000..7426848
--- /dev/null
+++ b/hw/bsp/nrf52dk/src/arch/cortex_m4/gcc_startup_nrf52_split.s
@@ -0,0 +1,150 @@
+/*
+Copyright (c) 2015, Nordic Semiconductor ASA
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+* Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+NOTE: Template files (including this one) are application specific and therefore
+expected to be copied into the application project folder prior to its use!
+*/
+
+ .syntax unified
+ .arch armv7-m
+ .section .stack
+ .align 3
+ .equ Stack_Size, 432
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector_split
+ .align 2
+ .globl __isr_vector_split
+__isr_vector_split:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler_split /* Reset Handler */
+
+ .size __isr_vector_split, . - __isr_vector_split
+
+/* Reset Handler */
+
+ .text
+ .thumb
+ .thumb_func
+ .align 1
+ .globl Reset_Handler_split
+ .type Reset_Handler_split, %function
+Reset_Handler_split:
+ .fnstart
+
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .LC0
+
+.LC1:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC1
+
+.LC0:
+ ldr r1, =__etext_loader
+ ldr r2, =__data_start___loader
+ ldr r3, =__data_end___loader
+
+ subs r3, r2
+ ble .LC2
+
+.LC3:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC3
+.LC2:
+
+ subs r0, r0
+ ldr r2, =__bss_start___loader
+ ldr r3, =__bss_end___loader
+
+ subs r3, r2
+ ble .LC4
+
+.LC5:
+ subs r3, 4
+ str r0, [r2,r3]
+ bgt .LC5
+.LC4:
+
+ LDR R0, =__HeapBase
+ LDR R1, =__HeapLimit
+ BL _sbrkInit
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =_start
+ BX R0
+
+ .pool
+ .cantunwind
+ .fnend
+ .size Reset_Handler_split,.-Reset_Handler_split
+
+ .section ".text"
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/90067c9a/hw/bsp/nucleo-f401re/src/arch/cortex_m4/startup_STM32F40x.s
----------------------------------------------------------------------
diff --git a/hw/bsp/nucleo-f401re/src/arch/cortex_m4/startup_STM32F40x.s b/hw/bsp/nucleo-f401re/src/arch/cortex_m4/startup_STM32F40x.s
new file mode 100644
index 0000000..646b4bf
--- /dev/null
+++ b/hw/bsp/nucleo-f401re/src/arch/cortex_m4/startup_STM32F40x.s
@@ -0,0 +1,343 @@
+/* File: startup_STM32F40x.S
+ * Purpose: startup file for Cortex-M4 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V1.4
+ * Date: 09 July 2012
+ *
+ * Copyright (c) 2011, 2012, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of the ARM Limited nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ .syntax unified
+ .arch armv7-m
+
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0xc00
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long WWDG_IRQHandler /* Window WatchDog */
+ .long PVD_IRQHandler /* PVD through EXTI Line detection */
+ .long TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .long RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .long FLASH_IRQHandler /* FLASH */
+ .long RCC_IRQHandler /* RCC */
+ .long EXTI0_IRQHandler /* EXTI Line0 */
+ .long EXTI1_IRQHandler /* EXTI Line1 */
+ .long EXTI2_IRQHandler /* EXTI Line2 */
+ .long EXTI3_IRQHandler /* EXTI Line3 */
+ .long EXTI4_IRQHandler /* EXTI Line4 */
+ .long DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .long DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .long DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .long DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .long DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .long DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .long DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .long ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .long CAN1_TX_IRQHandler /* CAN1 TX */
+ .long CAN1_RX0_IRQHandler /* CAN1 RX0 */
+ .long CAN1_RX1_IRQHandler /* CAN1 RX1 */
+ .long CAN1_SCE_IRQHandler /* CAN1 SCE */
+ .long EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .long TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
+ .long TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
+ .long TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
+ .long TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .long TIM2_IRQHandler /* TIM2 */
+ .long TIM3_IRQHandler /* TIM3 */
+ .long TIM4_IRQHandler /* TIM4 */
+ .long I2C1_EV_IRQHandler /* I2C1 Event */
+ .long I2C1_ER_IRQHandler /* I2C1 Error */
+ .long I2C2_EV_IRQHandler /* I2C2 Event */
+ .long I2C2_ER_IRQHandler /* I2C2 Error */
+ .long SPI1_IRQHandler /* SPI1 */
+ .long SPI2_IRQHandler /* SPI2 */
+ .long USART1_IRQHandler /* USART1 */
+ .long USART2_IRQHandler /* USART2 */
+ .long USART3_IRQHandler /* USART3 */
+ .long EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .long RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .long OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
+ .long TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .long TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .long TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .long TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .long DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .long FSMC_IRQHandler /* FSMC */
+ .long SDIO_IRQHandler /* SDIO */
+ .long TIM5_IRQHandler /* TIM5 */
+ .long SPI3_IRQHandler /* SPI3 */
+ .long UART4_IRQHandler /* UART4 */
+ .long UART5_IRQHandler /* UART5 */
+ .long TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .long TIM7_IRQHandler /* TIM7 */
+ .long DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .long DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .long DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .long DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .long DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .long ETH_IRQHandler /* Ethernet */
+ .long ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
+ .long CAN2_TX_IRQHandler /* CAN2 TX */
+ .long CAN2_RX0_IRQHandler /* CAN2 RX0 */
+ .long CAN2_RX1_IRQHandler /* CAN2 RX1 */
+ .long CAN2_SCE_IRQHandler /* CAN2 SCE */
+ .long OTG_FS_IRQHandler /* USB OTG FS */
+ .long DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .long DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .long DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .long USART6_IRQHandler /* USART6 */
+ .long I2C3_EV_IRQHandler /* I2C3 event */
+ .long I2C3_ER_IRQHandler /* I2C3 error */
+ .long OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .long OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .long OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .long OTG_HS_IRQHandler /* USB OTG HS */
+ .long DCMI_IRQHandler /* DCMI */
+ .long CRYP_IRQHandler /* CRYP crypto */
+ .long HASH_RNG_IRQHandler /* Hash and Rng */
+ .long FPU_IRQHandler /* FPU */
+
+ .size __isr_vector, . - __isr_vector
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Copy data core section from flash to RAM */
+ ldr r1, =__etext
+ ldr r2, =__coredata_start__
+ ldr r3, =__coredata_end__
+
+.LC0:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .LC0
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+ ldr r1, =__ecoredata
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.LC1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .LC1
+
+/* Set the bss core section to zero */
+ mov r0, #0
+ ldr r1, =__corebss_start__
+ ldr r2, =__corebss_end__
+
+.LC2:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .LC2
+
+/* Call system initialization and startup routines */
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler MemManage_Handler
+ def_default_handler BusFault_Handler
+ def_default_handler UsageFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler DebugMon_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_default_handler WWDG_IRQHandler
+ def_irq_default_handler PVD_IRQHandler
+ def_irq_default_handler TAMP_STAMP_IRQHandler
+ def_irq_default_handler RTC_WKUP_IRQHandler
+ def_irq_default_handler FLASH_IRQHandler
+ def_irq_default_handler RCC_IRQHandler
+ def_irq_default_handler EXTI0_IRQHandler
+ def_irq_default_handler EXTI1_IRQHandler
+ def_irq_default_handler EXTI2_IRQHandler
+ def_irq_default_handler EXTI3_IRQHandler
+ def_irq_default_handler EXTI4_IRQHandler
+ def_irq_default_handler DMA1_Stream0_IRQHandler
+ def_irq_default_handler DMA1_Stream1_IRQHandler
+ def_irq_default_handler DMA1_Stream2_IRQHandler
+ def_irq_default_handler DMA1_Stream3_IRQHandler
+ def_irq_default_handler DMA1_Stream4_IRQHandler
+ def_irq_default_handler DMA1_Stream5_IRQHandler
+ def_irq_default_handler DMA1_Stream6_IRQHandler
+ def_irq_default_handler ADC_IRQHandler
+ def_irq_default_handler CAN1_TX_IRQHandler
+ def_irq_default_handler CAN1_RX0_IRQHandler
+ def_irq_default_handler CAN1_RX1_IRQHandler
+ def_irq_default_handler CAN1_SCE_IRQHandler
+ def_irq_default_handler EXTI9_5_IRQHandler
+ def_irq_default_handler TIM1_BRK_TIM9_IRQHandler
+ def_irq_default_handler TIM1_UP_TIM10_IRQHandler
+ def_irq_default_handler TIM1_TRG_COM_TIM11_IRQHandler
+ def_irq_default_handler TIM1_CC_IRQHandler
+ def_irq_default_handler TIM2_IRQHandler
+ def_irq_default_handler TIM3_IRQHandler
+ def_irq_default_handler TIM4_IRQHandler
+ def_irq_default_handler I2C1_EV_IRQHandler
+ def_irq_default_handler I2C1_ER_IRQHandler
+ def_irq_default_handler I2C2_EV_IRQHandler
+ def_irq_default_handler I2C2_ER_IRQHandler
+ def_irq_default_handler SPI1_IRQHandler
+ def_irq_default_handler SPI2_IRQHandler
+ def_irq_default_handler USART1_IRQHandler
+ def_irq_default_handler USART2_IRQHandler
+ def_irq_default_handler USART3_IRQHandler
+ def_irq_default_handler EXTI15_10_IRQHandler
+ def_irq_default_handler RTC_Alarm_IRQHandler
+ def_irq_default_handler OTG_FS_WKUP_IRQHandler
+ def_irq_default_handler TIM8_BRK_TIM12_IRQHandler
+ def_irq_default_handler TIM8_UP_TIM13_IRQHandler
+ def_irq_default_handler TIM8_TRG_COM_TIM14_IRQHandler
+ def_irq_default_handler TIM8_CC_IRQHandler
+ def_irq_default_handler DMA1_Stream7_IRQHandler
+ def_irq_default_handler FSMC_IRQHandler
+ def_irq_default_handler SDIO_IRQHandler
+ def_irq_default_handler TIM5_IRQHandler
+ def_irq_default_handler SPI3_IRQHandler
+ def_irq_default_handler UART4_IRQHandler
+ def_irq_default_handler UART5_IRQHandler
+ def_irq_default_handler TIM6_DAC_IRQHandler
+ def_irq_default_handler TIM7_IRQHandler
+ def_irq_default_handler DMA2_Stream0_IRQHandler
+ def_irq_default_handler DMA2_Stream1_IRQHandler
+ def_irq_default_handler DMA2_Stream2_IRQHandler
+ def_irq_default_handler DMA2_Stream3_IRQHandler
+ def_irq_default_handler DMA2_Stream4_IRQHandler
+ def_irq_default_handler ETH_IRQHandler
+ def_irq_default_handler ETH_WKUP_IRQHandler
+ def_irq_default_handler CAN2_TX_IRQHandler
+ def_irq_default_handler CAN2_RX0_IRQHandler
+ def_irq_default_handler CAN2_RX1_IRQHandler
+ def_irq_default_handler CAN2_SCE_IRQHandler
+ def_irq_default_handler OTG_FS_IRQHandler
+ def_irq_default_handler DMA2_Stream5_IRQHandler
+ def_irq_default_handler DMA2_Stream6_IRQHandler
+ def_irq_default_handler DMA2_Stream7_IRQHandler
+ def_irq_default_handler USART6_IRQHandler
+ def_irq_default_handler I2C3_EV_IRQHandler
+ def_irq_default_handler I2C3_ER_IRQHandler
+ def_irq_default_handler OTG_HS_EP1_OUT_IRQHandler
+ def_irq_default_handler OTG_HS_EP1_IN_IRQHandler
+ def_irq_default_handler OTG_HS_WKUP_IRQHandler
+ def_irq_default_handler OTG_HS_IRQHandler
+ def_irq_default_handler DCMI_IRQHandler
+ def_irq_default_handler CRYP_IRQHandler
+ def_irq_default_handler HASH_RNG_IRQHandler
+ def_irq_default_handler FPU_IRQHandler
+ def_irq_default_handler DEF_IRQHandler
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/90067c9a/hw/bsp/olimex_stm32-e407_devboard/src/arch/cortex_m4/startup_STM32F40x.s
----------------------------------------------------------------------
diff --git a/hw/bsp/olimex_stm32-e407_devboard/src/arch/cortex_m4/startup_STM32F40x.s b/hw/bsp/olimex_stm32-e407_devboard/src/arch/cortex_m4/startup_STM32F40x.s
new file mode 100755
index 0000000..646b4bf
--- /dev/null
+++ b/hw/bsp/olimex_stm32-e407_devboard/src/arch/cortex_m4/startup_STM32F40x.s
@@ -0,0 +1,343 @@
+/* File: startup_STM32F40x.S
+ * Purpose: startup file for Cortex-M4 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V1.4
+ * Date: 09 July 2012
+ *
+ * Copyright (c) 2011, 2012, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of the ARM Limited nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ .syntax unified
+ .arch armv7-m
+
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0xc00
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long WWDG_IRQHandler /* Window WatchDog */
+ .long PVD_IRQHandler /* PVD through EXTI Line detection */
+ .long TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .long RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .long FLASH_IRQHandler /* FLASH */
+ .long RCC_IRQHandler /* RCC */
+ .long EXTI0_IRQHandler /* EXTI Line0 */
+ .long EXTI1_IRQHandler /* EXTI Line1 */
+ .long EXTI2_IRQHandler /* EXTI Line2 */
+ .long EXTI3_IRQHandler /* EXTI Line3 */
+ .long EXTI4_IRQHandler /* EXTI Line4 */
+ .long DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .long DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .long DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .long DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .long DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .long DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .long DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .long ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .long CAN1_TX_IRQHandler /* CAN1 TX */
+ .long CAN1_RX0_IRQHandler /* CAN1 RX0 */
+ .long CAN1_RX1_IRQHandler /* CAN1 RX1 */
+ .long CAN1_SCE_IRQHandler /* CAN1 SCE */
+ .long EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .long TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
+ .long TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
+ .long TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
+ .long TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .long TIM2_IRQHandler /* TIM2 */
+ .long TIM3_IRQHandler /* TIM3 */
+ .long TIM4_IRQHandler /* TIM4 */
+ .long I2C1_EV_IRQHandler /* I2C1 Event */
+ .long I2C1_ER_IRQHandler /* I2C1 Error */
+ .long I2C2_EV_IRQHandler /* I2C2 Event */
+ .long I2C2_ER_IRQHandler /* I2C2 Error */
+ .long SPI1_IRQHandler /* SPI1 */
+ .long SPI2_IRQHandler /* SPI2 */
+ .long USART1_IRQHandler /* USART1 */
+ .long USART2_IRQHandler /* USART2 */
+ .long USART3_IRQHandler /* USART3 */
+ .long EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .long RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .long OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
+ .long TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .long TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .long TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .long TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .long DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .long FSMC_IRQHandler /* FSMC */
+ .long SDIO_IRQHandler /* SDIO */
+ .long TIM5_IRQHandler /* TIM5 */
+ .long SPI3_IRQHandler /* SPI3 */
+ .long UART4_IRQHandler /* UART4 */
+ .long UART5_IRQHandler /* UART5 */
+ .long TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .long TIM7_IRQHandler /* TIM7 */
+ .long DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .long DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .long DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .long DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .long DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .long ETH_IRQHandler /* Ethernet */
+ .long ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
+ .long CAN2_TX_IRQHandler /* CAN2 TX */
+ .long CAN2_RX0_IRQHandler /* CAN2 RX0 */
+ .long CAN2_RX1_IRQHandler /* CAN2 RX1 */
+ .long CAN2_SCE_IRQHandler /* CAN2 SCE */
+ .long OTG_FS_IRQHandler /* USB OTG FS */
+ .long DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .long DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .long DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .long USART6_IRQHandler /* USART6 */
+ .long I2C3_EV_IRQHandler /* I2C3 event */
+ .long I2C3_ER_IRQHandler /* I2C3 error */
+ .long OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .long OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .long OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .long OTG_HS_IRQHandler /* USB OTG HS */
+ .long DCMI_IRQHandler /* DCMI */
+ .long CRYP_IRQHandler /* CRYP crypto */
+ .long HASH_RNG_IRQHandler /* Hash and Rng */
+ .long FPU_IRQHandler /* FPU */
+
+ .size __isr_vector, . - __isr_vector
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Copy data core section from flash to RAM */
+ ldr r1, =__etext
+ ldr r2, =__coredata_start__
+ ldr r3, =__coredata_end__
+
+.LC0:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .LC0
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+ ldr r1, =__ecoredata
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.LC1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .LC1
+
+/* Set the bss core section to zero */
+ mov r0, #0
+ ldr r1, =__corebss_start__
+ ldr r2, =__corebss_end__
+
+.LC2:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .LC2
+
+/* Call system initialization and startup routines */
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler MemManage_Handler
+ def_default_handler BusFault_Handler
+ def_default_handler UsageFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler DebugMon_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_default_handler WWDG_IRQHandler
+ def_irq_default_handler PVD_IRQHandler
+ def_irq_default_handler TAMP_STAMP_IRQHandler
+ def_irq_default_handler RTC_WKUP_IRQHandler
+ def_irq_default_handler FLASH_IRQHandler
+ def_irq_default_handler RCC_IRQHandler
+ def_irq_default_handler EXTI0_IRQHandler
+ def_irq_default_handler EXTI1_IRQHandler
+ def_irq_default_handler EXTI2_IRQHandler
+ def_irq_default_handler EXTI3_IRQHandler
+ def_irq_default_handler EXTI4_IRQHandler
+ def_irq_default_handler DMA1_Stream0_IRQHandler
+ def_irq_default_handler DMA1_Stream1_IRQHandler
+ def_irq_default_handler DMA1_Stream2_IRQHandler
+ def_irq_default_handler DMA1_Stream3_IRQHandler
+ def_irq_default_handler DMA1_Stream4_IRQHandler
+ def_irq_default_handler DMA1_Stream5_IRQHandler
+ def_irq_default_handler DMA1_Stream6_IRQHandler
+ def_irq_default_handler ADC_IRQHandler
+ def_irq_default_handler CAN1_TX_IRQHandler
+ def_irq_default_handler CAN1_RX0_IRQHandler
+ def_irq_default_handler CAN1_RX1_IRQHandler
+ def_irq_default_handler CAN1_SCE_IRQHandler
+ def_irq_default_handler EXTI9_5_IRQHandler
+ def_irq_default_handler TIM1_BRK_TIM9_IRQHandler
+ def_irq_default_handler TIM1_UP_TIM10_IRQHandler
+ def_irq_default_handler TIM1_TRG_COM_TIM11_IRQHandler
+ def_irq_default_handler TIM1_CC_IRQHandler
+ def_irq_default_handler TIM2_IRQHandler
+ def_irq_default_handler TIM3_IRQHandler
+ def_irq_default_handler TIM4_IRQHandler
+ def_irq_default_handler I2C1_EV_IRQHandler
+ def_irq_default_handler I2C1_ER_IRQHandler
+ def_irq_default_handler I2C2_EV_IRQHandler
+ def_irq_default_handler I2C2_ER_IRQHandler
+ def_irq_default_handler SPI1_IRQHandler
+ def_irq_default_handler SPI2_IRQHandler
+ def_irq_default_handler USART1_IRQHandler
+ def_irq_default_handler USART2_IRQHandler
+ def_irq_default_handler USART3_IRQHandler
+ def_irq_default_handler EXTI15_10_IRQHandler
+ def_irq_default_handler RTC_Alarm_IRQHandler
+ def_irq_default_handler OTG_FS_WKUP_IRQHandler
+ def_irq_default_handler TIM8_BRK_TIM12_IRQHandler
+ def_irq_default_handler TIM8_UP_TIM13_IRQHandler
+ def_irq_default_handler TIM8_TRG_COM_TIM14_IRQHandler
+ def_irq_default_handler TIM8_CC_IRQHandler
+ def_irq_default_handler DMA1_Stream7_IRQHandler
+ def_irq_default_handler FSMC_IRQHandler
+ def_irq_default_handler SDIO_IRQHandler
+ def_irq_default_handler TIM5_IRQHandler
+ def_irq_default_handler SPI3_IRQHandler
+ def_irq_default_handler UART4_IRQHandler
+ def_irq_default_handler UART5_IRQHandler
+ def_irq_default_handler TIM6_DAC_IRQHandler
+ def_irq_default_handler TIM7_IRQHandler
+ def_irq_default_handler DMA2_Stream0_IRQHandler
+ def_irq_default_handler DMA2_Stream1_IRQHandler
+ def_irq_default_handler DMA2_Stream2_IRQHandler
+ def_irq_default_handler DMA2_Stream3_IRQHandler
+ def_irq_default_handler DMA2_Stream4_IRQHandler
+ def_irq_default_handler ETH_IRQHandler
+ def_irq_default_handler ETH_WKUP_IRQHandler
+ def_irq_default_handler CAN2_TX_IRQHandler
+ def_irq_default_handler CAN2_RX0_IRQHandler
+ def_irq_default_handler CAN2_RX1_IRQHandler
+ def_irq_default_handler CAN2_SCE_IRQHandler
+ def_irq_default_handler OTG_FS_IRQHandler
+ def_irq_default_handler DMA2_Stream5_IRQHandler
+ def_irq_default_handler DMA2_Stream6_IRQHandler
+ def_irq_default_handler DMA2_Stream7_IRQHandler
+ def_irq_default_handler USART6_IRQHandler
+ def_irq_default_handler I2C3_EV_IRQHandler
+ def_irq_default_handler I2C3_ER_IRQHandler
+ def_irq_default_handler OTG_HS_EP1_OUT_IRQHandler
+ def_irq_default_handler OTG_HS_EP1_IN_IRQHandler
+ def_irq_default_handler OTG_HS_WKUP_IRQHandler
+ def_irq_default_handler OTG_HS_IRQHandler
+ def_irq_default_handler DCMI_IRQHandler
+ def_irq_default_handler CRYP_IRQHandler
+ def_irq_default_handler HASH_RNG_IRQHandler
+ def_irq_default_handler FPU_IRQHandler
+ def_irq_default_handler DEF_IRQHandler
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/90067c9a/hw/bsp/rb-nano2/src/arch/cortex_m4/gcc_startup_nrf52.s
----------------------------------------------------------------------
diff --git a/hw/bsp/rb-nano2/src/arch/cortex_m4/gcc_startup_nrf52.s b/hw/bsp/rb-nano2/src/arch/cortex_m4/gcc_startup_nrf52.s
new file mode 100755
index 0000000..fb804fd
--- /dev/null
+++ b/hw/bsp/rb-nano2/src/arch/cortex_m4/gcc_startup_nrf52.s
@@ -0,0 +1,289 @@
+/*
+Copyright (c) 2015, Nordic Semiconductor ASA
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+* Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+NOTE: Template files (including this one) are application specific and therefore
+expected to be copied into the application project folder prior to its use!
+*/
+
+ .syntax unified
+ .arch armv7-m
+
+ .section .stack
+ .align 3
+ .equ Stack_Size, 432
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External Interrupts */
+ .long POWER_CLOCK_IRQHandler
+ .long RADIO_IRQHandler
+ .long UARTE0_UART0_IRQHandler
+ .long SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+ .long SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+ .long NFCT_IRQHandler
+ .long GPIOTE_IRQHandler
+ .long SAADC_IRQHandler
+ .long TIMER0_IRQHandler
+ .long TIMER1_IRQHandler
+ .long TIMER2_IRQHandler
+ .long RTC0_IRQHandler
+ .long TEMP_IRQHandler
+ .long RNG_IRQHandler
+ .long ECB_IRQHandler
+ .long CCM_AAR_IRQHandler
+ .long WDT_IRQHandler
+ .long RTC1_IRQHandler
+ .long QDEC_IRQHandler
+ .long COMP_LPCOMP_IRQHandler
+ .long SWI0_EGU0_IRQHandler
+ .long SWI1_EGU1_IRQHandler
+ .long SWI2_EGU2_IRQHandler
+ .long SWI3_EGU3_IRQHandler
+ .long SWI4_EGU4_IRQHandler
+ .long SWI5_EGU5_IRQHandler
+ .long TIMER3_IRQHandler
+ .long TIMER4_IRQHandler
+ .long PWM0_IRQHandler
+ .long PDM_IRQHandler
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long MWU_IRQHandler
+ .long PWM1_IRQHandler
+ .long PWM2_IRQHandler
+ .long SPIM2_SPIS2_SPI2_IRQHandler
+ .long RTC2_IRQHandler
+ .long I2S_IRQHandler
+
+ .size __isr_vector, . - __isr_vector
+
+/* Reset Handler */
+
+ .text
+ .thumb
+ .thumb_func
+ .align 1
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ .fnstart
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .LC0
+
+.LC1:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC1
+
+.LC0:
+
+ LDR R0, =__HeapBase
+ LDR R1, =__HeapLimit
+ BL _sbrkInit
+
+ LDR R0, =SystemInit
+ BLX R0
+
+ LDR R0, =_start
+ BX R0
+
+ .pool
+ .cantunwind
+ .fnend
+ .size Reset_Handler,.-Reset_Handler
+
+ .section ".text"
+
+
+/* Dummy Exception Handlers (infinite loops which can be modified) */
+
+ .weak NMI_Handler
+ .type NMI_Handler, %function
+NMI_Handler:
+ B .
+ .size NMI_Handler, . - NMI_Handler
+
+
+ .weak HardFault_Handler
+ .type HardFault_Handler, %function
+HardFault_Handler:
+ B .
+ .size HardFault_Handler, . - HardFault_Handler
+
+
+ .weak MemoryManagement_Handler
+ .type MemoryManagement_Handler, %function
+MemoryManagement_Handler:
+ B .
+ .size MemoryManagement_Handler, . - MemoryManagement_Handler
+
+
+ .weak BusFault_Handler
+ .type BusFault_Handler, %function
+BusFault_Handler:
+ B .
+ .size BusFault_Handler, . - BusFault_Handler
+
+
+ .weak UsageFault_Handler
+ .type UsageFault_Handler, %function
+UsageFault_Handler:
+ B .
+ .size UsageFault_Handler, . - UsageFault_Handler
+
+
+ .weak SVC_Handler
+ .type SVC_Handler, %function
+SVC_Handler:
+ B .
+ .size SVC_Handler, . - SVC_Handler
+
+
+ .weak PendSV_Handler
+ .type PendSV_Handler, %function
+PendSV_Handler:
+ B .
+ .size PendSV_Handler, . - PendSV_Handler
+
+
+ .weak SysTick_Handler
+ .type SysTick_Handler, %function
+SysTick_Handler:
+ B .
+ .size SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+ .globl Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ B .
+ .size Default_Handler, . - Default_Handler
+
+ .macro IRQ handler
+ .weak \handler
+ .set \handler, Default_Handler
+ .endm
+
+ IRQ POWER_CLOCK_IRQHandler
+ IRQ RADIO_IRQHandler
+ IRQ UARTE0_UART0_IRQHandler
+ IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+ IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+ IRQ NFCT_IRQHandler
+ IRQ GPIOTE_IRQHandler
+ IRQ SAADC_IRQHandler
+ IRQ TIMER0_IRQHandler
+ IRQ TIMER1_IRQHandler
+ IRQ TIMER2_IRQHandler
+ IRQ RTC0_IRQHandler
+ IRQ TEMP_IRQHandler
+ IRQ RNG_IRQHandler
+ IRQ ECB_IRQHandler
+ IRQ CCM_AAR_IRQHandler
+ IRQ WDT_IRQHandler
+ IRQ RTC1_IRQHandler
+ IRQ QDEC_IRQHandler
+ IRQ COMP_LPCOMP_IRQHandler
+ IRQ SWI0_EGU0_IRQHandler
+ IRQ SWI1_EGU1_IRQHandler
+ IRQ SWI2_EGU2_IRQHandler
+ IRQ SWI3_EGU3_IRQHandler
+ IRQ SWI4_EGU4_IRQHandler
+ IRQ SWI5_EGU5_IRQHandler
+ IRQ TIMER3_IRQHandler
+ IRQ TIMER4_IRQHandler
+ IRQ PWM0_IRQHandler
+ IRQ PDM_IRQHandler
+ IRQ MWU_IRQHandler
+ IRQ PWM1_IRQHandler
+ IRQ PWM2_IRQHandler
+ IRQ SPIM2_SPIS2_SPI2_IRQHandler
+ IRQ RTC2_IRQHandler
+ IRQ I2S_IRQHandler
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/90067c9a/hw/bsp/rb-nano2/src/arch/cortex_m4/gcc_startup_nrf52_split.s
----------------------------------------------------------------------
diff --git a/hw/bsp/rb-nano2/src/arch/cortex_m4/gcc_startup_nrf52_split.s b/hw/bsp/rb-nano2/src/arch/cortex_m4/gcc_startup_nrf52_split.s
new file mode 100755
index 0000000..7426848
--- /dev/null
+++ b/hw/bsp/rb-nano2/src/arch/cortex_m4/gcc_startup_nrf52_split.s
@@ -0,0 +1,150 @@
+/*
+Copyright (c) 2015, Nordic Semiconductor ASA
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+* Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+NOTE: Template files (including this one) are application specific and therefore
+expected to be copied into the application project folder prior to its use!
+*/
+
+ .syntax unified
+ .arch armv7-m
+ .section .stack
+ .align 3
+ .equ Stack_Size, 432
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector_split
+ .align 2
+ .globl __isr_vector_split
+__isr_vector_split:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler_split /* Reset Handler */
+
+ .size __isr_vector_split, . - __isr_vector_split
+
+/* Reset Handler */
+
+ .text
+ .thumb
+ .thumb_func
+ .align 1
+ .globl Reset_Handler_split
+ .type Reset_Handler_split, %function
+Reset_Handler_split:
+ .fnstart
+
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .LC0
+
+.LC1:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC1
+
+.LC0:
+ ldr r1, =__etext_loader
+ ldr r2, =__data_start___loader
+ ldr r3, =__data_end___loader
+
+ subs r3, r2
+ ble .LC2
+
+.LC3:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC3
+.LC2:
+
+ subs r0, r0
+ ldr r2, =__bss_start___loader
+ ldr r3, =__bss_end___loader
+
+ subs r3, r2
+ ble .LC4
+
+.LC5:
+ subs r3, 4
+ str r0, [r2,r3]
+ bgt .LC5
+.LC4:
+
+ LDR R0, =__HeapBase
+ LDR R1, =__HeapLimit
+ BL _sbrkInit
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =_start
+ BX R0
+
+ .pool
+ .cantunwind
+ .fnend
+ .size Reset_Handler_split,.-Reset_Handler_split
+
+ .section ".text"
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/90067c9a/hw/bsp/stm32f4discovery/src/arch/cortex_m4/startup_STM32F40x.s
----------------------------------------------------------------------
diff --git a/hw/bsp/stm32f4discovery/src/arch/cortex_m4/startup_STM32F40x.s b/hw/bsp/stm32f4discovery/src/arch/cortex_m4/startup_STM32F40x.s
new file mode 100644
index 0000000..646b4bf
--- /dev/null
+++ b/hw/bsp/stm32f4discovery/src/arch/cortex_m4/startup_STM32F40x.s
@@ -0,0 +1,343 @@
+/* File: startup_STM32F40x.S
+ * Purpose: startup file for Cortex-M4 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V1.4
+ * Date: 09 July 2012
+ *
+ * Copyright (c) 2011, 2012, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of the ARM Limited nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ .syntax unified
+ .arch armv7-m
+
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0xc00
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long WWDG_IRQHandler /* Window WatchDog */
+ .long PVD_IRQHandler /* PVD through EXTI Line detection */
+ .long TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .long RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .long FLASH_IRQHandler /* FLASH */
+ .long RCC_IRQHandler /* RCC */
+ .long EXTI0_IRQHandler /* EXTI Line0 */
+ .long EXTI1_IRQHandler /* EXTI Line1 */
+ .long EXTI2_IRQHandler /* EXTI Line2 */
+ .long EXTI3_IRQHandler /* EXTI Line3 */
+ .long EXTI4_IRQHandler /* EXTI Line4 */
+ .long DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .long DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .long DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .long DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .long DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .long DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .long DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .long ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .long CAN1_TX_IRQHandler /* CAN1 TX */
+ .long CAN1_RX0_IRQHandler /* CAN1 RX0 */
+ .long CAN1_RX1_IRQHandler /* CAN1 RX1 */
+ .long CAN1_SCE_IRQHandler /* CAN1 SCE */
+ .long EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .long TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
+ .long TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
+ .long TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
+ .long TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .long TIM2_IRQHandler /* TIM2 */
+ .long TIM3_IRQHandler /* TIM3 */
+ .long TIM4_IRQHandler /* TIM4 */
+ .long I2C1_EV_IRQHandler /* I2C1 Event */
+ .long I2C1_ER_IRQHandler /* I2C1 Error */
+ .long I2C2_EV_IRQHandler /* I2C2 Event */
+ .long I2C2_ER_IRQHandler /* I2C2 Error */
+ .long SPI1_IRQHandler /* SPI1 */
+ .long SPI2_IRQHandler /* SPI2 */
+ .long USART1_IRQHandler /* USART1 */
+ .long USART2_IRQHandler /* USART2 */
+ .long USART3_IRQHandler /* USART3 */
+ .long EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .long RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .long OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
+ .long TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .long TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .long TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .long TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .long DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .long FSMC_IRQHandler /* FSMC */
+ .long SDIO_IRQHandler /* SDIO */
+ .long TIM5_IRQHandler /* TIM5 */
+ .long SPI3_IRQHandler /* SPI3 */
+ .long UART4_IRQHandler /* UART4 */
+ .long UART5_IRQHandler /* UART5 */
+ .long TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .long TIM7_IRQHandler /* TIM7 */
+ .long DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .long DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .long DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .long DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .long DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .long ETH_IRQHandler /* Ethernet */
+ .long ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
+ .long CAN2_TX_IRQHandler /* CAN2 TX */
+ .long CAN2_RX0_IRQHandler /* CAN2 RX0 */
+ .long CAN2_RX1_IRQHandler /* CAN2 RX1 */
+ .long CAN2_SCE_IRQHandler /* CAN2 SCE */
+ .long OTG_FS_IRQHandler /* USB OTG FS */
+ .long DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .long DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .long DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .long USART6_IRQHandler /* USART6 */
+ .long I2C3_EV_IRQHandler /* I2C3 event */
+ .long I2C3_ER_IRQHandler /* I2C3 error */
+ .long OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .long OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .long OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .long OTG_HS_IRQHandler /* USB OTG HS */
+ .long DCMI_IRQHandler /* DCMI */
+ .long CRYP_IRQHandler /* CRYP crypto */
+ .long HASH_RNG_IRQHandler /* Hash and Rng */
+ .long FPU_IRQHandler /* FPU */
+
+ .size __isr_vector, . - __isr_vector
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Copy data core section from flash to RAM */
+ ldr r1, =__etext
+ ldr r2, =__coredata_start__
+ ldr r3, =__coredata_end__
+
+.LC0:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .LC0
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+ ldr r1, =__ecoredata
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.LC1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .LC1
+
+/* Set the bss core section to zero */
+ mov r0, #0
+ ldr r1, =__corebss_start__
+ ldr r2, =__corebss_end__
+
+.LC2:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .LC2
+
+/* Call system initialization and startup routines */
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler MemManage_Handler
+ def_default_handler BusFault_Handler
+ def_default_handler UsageFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler DebugMon_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_default_handler WWDG_IRQHandler
+ def_irq_default_handler PVD_IRQHandler
+ def_irq_default_handler TAMP_STAMP_IRQHandler
+ def_irq_default_handler RTC_WKUP_IRQHandler
+ def_irq_default_handler FLASH_IRQHandler
+ def_irq_default_handler RCC_IRQHandler
+ def_irq_default_handler EXTI0_IRQHandler
+ def_irq_default_handler EXTI1_IRQHandler
+ def_irq_default_handler EXTI2_IRQHandler
+ def_irq_default_handler EXTI3_IRQHandler
+ def_irq_default_handler EXTI4_IRQHandler
+ def_irq_default_handler DMA1_Stream0_IRQHandler
+ def_irq_default_handler DMA1_Stream1_IRQHandler
+ def_irq_default_handler DMA1_Stream2_IRQHandler
+ def_irq_default_handler DMA1_Stream3_IRQHandler
+ def_irq_default_handler DMA1_Stream4_IRQHandler
+ def_irq_default_handler DMA1_Stream5_IRQHandler
+ def_irq_default_handler DMA1_Stream6_IRQHandler
+ def_irq_default_handler ADC_IRQHandler
+ def_irq_default_handler CAN1_TX_IRQHandler
+ def_irq_default_handler CAN1_RX0_IRQHandler
+ def_irq_default_handler CAN1_RX1_IRQHandler
+ def_irq_default_handler CAN1_SCE_IRQHandler
+ def_irq_default_handler EXTI9_5_IRQHandler
+ def_irq_default_handler TIM1_BRK_TIM9_IRQHandler
+ def_irq_default_handler TIM1_UP_TIM10_IRQHandler
+ def_irq_default_handler TIM1_TRG_COM_TIM11_IRQHandler
+ def_irq_default_handler TIM1_CC_IRQHandler
+ def_irq_default_handler TIM2_IRQHandler
+ def_irq_default_handler TIM3_IRQHandler
+ def_irq_default_handler TIM4_IRQHandler
+ def_irq_default_handler I2C1_EV_IRQHandler
+ def_irq_default_handler I2C1_ER_IRQHandler
+ def_irq_default_handler I2C2_EV_IRQHandler
+ def_irq_default_handler I2C2_ER_IRQHandler
+ def_irq_default_handler SPI1_IRQHandler
+ def_irq_default_handler SPI2_IRQHandler
+ def_irq_default_handler USART1_IRQHandler
+ def_irq_default_handler USART2_IRQHandler
+ def_irq_default_handler USART3_IRQHandler
+ def_irq_default_handler EXTI15_10_IRQHandler
+ def_irq_default_handler RTC_Alarm_IRQHandler
+ def_irq_default_handler OTG_FS_WKUP_IRQHandler
+ def_irq_default_handler TIM8_BRK_TIM12_IRQHandler
+ def_irq_default_handler TIM8_UP_TIM13_IRQHandler
+ def_irq_default_handler TIM8_TRG_COM_TIM14_IRQHandler
+ def_irq_default_handler TIM8_CC_IRQHandler
+ def_irq_default_handler DMA1_Stream7_IRQHandler
+ def_irq_default_handler FSMC_IRQHandler
+ def_irq_default_handler SDIO_IRQHandler
+ def_irq_default_handler TIM5_IRQHandler
+ def_irq_default_handler SPI3_IRQHandler
+ def_irq_default_handler UART4_IRQHandler
+ def_irq_default_handler UART5_IRQHandler
+ def_irq_default_handler TIM6_DAC_IRQHandler
+ def_irq_default_handler TIM7_IRQHandler
+ def_irq_default_handler DMA2_Stream0_IRQHandler
+ def_irq_default_handler DMA2_Stream1_IRQHandler
+ def_irq_default_handler DMA2_Stream2_IRQHandler
+ def_irq_default_handler DMA2_Stream3_IRQHandler
+ def_irq_default_handler DMA2_Stream4_IRQHandler
+ def_irq_default_handler ETH_IRQHandler
+ def_irq_default_handler ETH_WKUP_IRQHandler
+ def_irq_default_handler CAN2_TX_IRQHandler
+ def_irq_default_handler CAN2_RX0_IRQHandler
+ def_irq_default_handler CAN2_RX1_IRQHandler
+ def_irq_default_handler CAN2_SCE_IRQHandler
+ def_irq_default_handler OTG_FS_IRQHandler
+ def_irq_default_handler DMA2_Stream5_IRQHandler
+ def_irq_default_handler DMA2_Stream6_IRQHandler
+ def_irq_default_handler DMA2_Stream7_IRQHandler
+ def_irq_default_handler USART6_IRQHandler
+ def_irq_default_handler I2C3_EV_IRQHandler
+ def_irq_default_handler I2C3_ER_IRQHandler
+ def_irq_default_handler OTG_HS_EP1_OUT_IRQHandler
+ def_irq_default_handler OTG_HS_EP1_IN_IRQHandler
+ def_irq_default_handler OTG_HS_WKUP_IRQHandler
+ def_irq_default_handler OTG_HS_IRQHandler
+ def_irq_default_handler DCMI_IRQHandler
+ def_irq_default_handler CRYP_IRQHandler
+ def_irq_default_handler HASH_RNG_IRQHandler
+ def_irq_default_handler FPU_IRQHandler
+ def_irq_default_handler DEF_IRQHandler
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/90067c9a/hw/mcu/nordic/nrf51xxx/src/arch/cortex_m0/gcc_startup_nrf51.s
----------------------------------------------------------------------
diff --git a/hw/mcu/nordic/nrf51xxx/src/arch/cortex_m0/gcc_startup_nrf51.s b/hw/mcu/nordic/nrf51xxx/src/arch/cortex_m0/gcc_startup_nrf51.s
deleted file mode 100755
index fbc88bd..0000000
--- a/hw/mcu/nordic/nrf51xxx/src/arch/cortex_m0/gcc_startup_nrf51.s
+++ /dev/null
@@ -1,270 +0,0 @@
-/*
-Copyright (c) 2015, Nordic Semiconductor ASA
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-
-* Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
- and/or other materials provided with the distribution.
-
-* Neither the name of Nordic Semiconductor ASA nor the names of its
- contributors may be used to endorse or promote products derived from
- this software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/*
-NOTE: Template files (including this one) are application specific and therefore
-expected to be copied into the application project folder prior to its use!
-*/
-
- .syntax unified
- .arch armv6-m
-
- .section .stack
- .align 3
- .equ Stack_Size, 432
- .globl __StackTop
- .globl __StackLimit
-__StackLimit:
- .space Stack_Size
- .size __StackLimit, . - __StackLimit
-__StackTop:
- .size __StackTop, . - __StackTop
-
- .section .heap
- .align 3
-#ifdef __HEAP_SIZE
- .equ Heap_Size, __HEAP_SIZE
-#else
- .equ Heap_Size, 0
-#endif
- .globl __HeapBase
- .globl __HeapLimit
-__HeapBase:
- .if Heap_Size
- .space Heap_Size
- .endif
- .size __HeapBase, . - __HeapBase
-__HeapLimit:
- .size __HeapLimit, . - __HeapLimit
-
- .section .isr_vector
- .align 2
- .globl __isr_vector
-__isr_vector:
- .long __StackTop /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long _NMI_Handler /* NMI Handler */
- .long _HardFault_Handler /* Hard Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long _SVC_Handler /* SVCall Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long _PendSV_Handler /* PendSV Handler */
- .long _SysTick_Handler /* SysTick Handler */
-
- /* External Interrupts */
- .long _POWER_CLOCK_IRQHandler
- .long _RADIO_IRQHandler
- .long _UART0_IRQHandler
- .long _SPI0_TWI0_IRQHandler
- .long _SPI1_TWI1_IRQHandler
- .long 0 /*Reserved */
- .long _GPIOTE_IRQHandler
- .long ADC_IRQHandler
- .long _TIMER0_IRQHandler
- .long _TIMER1_IRQHandler
- .long _TIMER2_IRQHandler
- .long _RTC0_IRQHandler
- .long _TEMP_IRQHandler
- .long _RNG_IRQHandler
- .long _ECB_IRQHandler
- .long _CCM_AAR_IRQHandler
- .long _WDT_IRQHandler
- .long _RTC1_IRQHandler
- .long _QDEC_IRQHandler
- .long _LPCOMP_IRQHandler
- .long _SWI0_IRQHandler
- .long _SWI1_IRQHandler
- .long _SWI2_IRQHandler
- .long _SWI3_IRQHandler
- .long _SWI4_IRQHandler
- .long _SWI5_IRQHandler
- .long 0 /*Reserved */
- .long 0 /*Reserved */
- .long 0 /*Reserved */
- .long 0 /*Reserved */
- .long 0 /*Reserved */
- .long 0 /*Reserved */
-
- .size __isr_vector, . - __isr_vector
-
-/* Reset Handler */
-
- .equ NRF_POWER_RAMON_ADDRESS, 0x40000524
- .equ NRF_POWER_RAMONB_ADDRESS, 0x40000554
- .equ NRF_POWER_RAMONx_RAMxON_ONMODE_Msk, 0x3
-
- .text
- .thumb
- .thumb_func
- .align 1
- .globl Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- .fnstart
-
-/* Make sure ALL RAM banks are powered on */
- MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
-
- LDR R0, =NRF_POWER_RAMON_ADDRESS
- LDR R2, [R0]
- ORRS R2, R1
- STR R2, [R0]
-
- LDR R0, =NRF_POWER_RAMONB_ADDRESS
- LDR R2, [R0]
- ORRS R2, R1
- STR R2, [R0]
-
-/* Loop to copy data from read only memory to RAM. The ranges
- * of copy from/to are specified by following symbols evaluated in
- * linker script.
- * __etext: End of code section, i.e., begin of data sections to copy from.
- * __data_start__/__data_end__: RAM address range that data should be
- * copied to. Both must be aligned to 4 bytes boundary. */
-
- ldr r1, =__etext
- ldr r2, =__data_start__
- ldr r3, =__data_end__
-
- subs r3, r2
- ble .LC0
-
-.LC1:
- subs r3, 4
- ldr r0, [r1,r3]
- str r0, [r2,r3]
- bgt .LC1
-.LC0:
- LDR R0, =__HeapBase
- LDR R1, =__HeapLimit
- BL _sbrkInit
-
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =_start
- BX R0
-
- .pool
- .cantunwind
- .fnend
- .size Reset_Handler,.-Reset_Handler
-
- .section ".text"
-
-
-/* Dummy Exception Handlers (infinite loops which can be modified) */
-
- .weak NMI_Handler
- .type NMI_Handler, %function
-NMI_Handler:
- B .
- .size NMI_Handler, . - NMI_Handler
-
- .weak SVC_Handler
- .type SVC_Handler, %function
-SVC_Handler:
- B .
- .size SVC_Handler, . - SVC_Handler
-
-
- .weak PendSV_Handler
- .type PendSV_Handler, %function
-PendSV_Handler:
- B .
- .size PendSV_Handler, . - PendSV_Handler
-
-
- .weak SysTick_Handler
- .type SysTick_Handler, %function
-SysTick_Handler:
- B .
- .size SysTick_Handler, . - SysTick_Handler
-
-/* Default handler. This uses the vector in the relocated vector table */
- .globl Default_Handler
- .type Default_Handler, %function
-Default_Handler:
- LDR R2, =__vector_tbl_reloc__
- MRS R0, PSR
- MOVS R1, #0x3F
- ANDS R0, R1
- LSLS R0, R0, #2
- LDR R0, [R0, R2]
- BX R0
- .size Default_Handler, . - Default_Handler
-
-/*
- * All of the following IRQ Handlers will point to the default handler unless
- * they are defined elsewhere.
- */
- .macro IRQ handler
- .weak \handler
- .set \handler, Default_Handler
- .endm
-
- IRQ _NMI_Handler
- IRQ _HardFault_Handler
- IRQ _SVC_Handler
- IRQ _PendSV_Handler
- IRQ _SysTick_Handler
- IRQ _POWER_CLOCK_IRQHandler
- IRQ _RADIO_IRQHandler
- IRQ _UART0_IRQHandler
- IRQ _SPI0_TWI0_IRQHandler
- IRQ _SPI1_TWI1_IRQHandler
- IRQ _GPIOTE_IRQHandler
- IRQ ADC_IRQHandler
- IRQ _TIMER0_IRQHandler
- IRQ _TIMER1_IRQHandler
- IRQ _TIMER2_IRQHandler
- IRQ _RTC0_IRQHandler
- IRQ _TEMP_IRQHandler
- IRQ _RNG_IRQHandler
- IRQ _ECB_IRQHandler
- IRQ _CCM_AAR_IRQHandler
- IRQ _WDT_IRQHandler
- IRQ _RTC1_IRQHandler
- IRQ _QDEC_IRQHandler
- IRQ _LPCOMP_IRQHandler
- IRQ _SWI0_IRQHandler
- IRQ _SWI1_IRQHandler
- IRQ _SWI2_IRQHandler
- IRQ _SWI3_IRQHandler
- IRQ _SWI4_IRQHandler
- IRQ _SWI5_IRQHandler
-
- .end