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Posted to commits@mynewt.apache.org by ut...@apache.org on 2018/09/18 10:04:33 UTC
[mynewt-core] 03/04: [STM32] Common HAL support for L0
This is an automated email from the ASF dual-hosted git repository.
utzig pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit 2bf165aaa5f7fd60cabaf49843bc50fc1694f111
Author: Fabio Utzig <ut...@apache.org>
AuthorDate: Wed Jul 18 09:29:20 2018 -0300
[STM32] Common HAL support for L0
---
hw/mcu/stm/stm32_common/src/hal_gpio.c | 94 ++++++++++++++++++++++
hw/mcu/stm/stm32_common/src/hal_spi.c | 20 +++--
hw/mcu/stm/stm32_common/src/hal_system.c | 3 +-
hw/mcu/stm/stm32_common/src/hal_timer.c | 37 +++++++++
.../stm/stm32_common/src/stm32_driver_mod_timer.c | 86 ++++++++++++++++++++
5 files changed, 233 insertions(+), 7 deletions(-)
diff --git a/hw/mcu/stm/stm32_common/src/hal_gpio.c b/hw/mcu/stm/stm32_common/src/hal_gpio.c
index 872122e..96516c5 100644
--- a/hw/mcu/stm/stm32_common/src/hal_gpio.c
+++ b/hw/mcu/stm/stm32_common/src/hal_gpio.c
@@ -136,6 +136,7 @@ static struct gpio_irq_obj gpio_irq_handlers[16];
struct ext_irqs
{
+#if !MYNEWT_VAL(MCU_STM32L0)
volatile uint32_t irq0;
volatile uint32_t irq1;
volatile uint32_t irq2;
@@ -143,6 +144,11 @@ struct ext_irqs
volatile uint32_t irq4;
volatile uint32_t irq9_5;
volatile uint32_t irq15_10;
+#else
+ volatile uint32_t irq0_1;
+ volatile uint32_t irq2_3;
+ volatile uint32_t irq4_15;
+#endif
};
struct ext_irqs ext_irq_counts;
@@ -165,6 +171,7 @@ ext_irq_handler(int index)
}
}
+#if !MYNEWT_VAL(MCU_STM32L0)
/* External interrupt 0 */
static void
ext_irq0(void)
@@ -244,6 +251,61 @@ ext_irq15_10(void)
}
}
+#else /* MYNEWT_VAL(MCU_STM32L0) */
+
+/**
+ * ext irq0_1
+ *
+ * External interrupt handler for irqs 0 through 1.
+ *
+ */
+static void
+ext_irq0_1(void)
+{
+ int index;
+
+ ++ext_irq_counts.irq0_1;
+ for (index = 0; index <= 1; ++index) {
+ ext_irq_handler(index);
+ }
+}
+
+/**
+ * ext irq2_3
+ *
+ * External interrupt handler for irqs 2 through 3.
+ *
+ */
+static void
+ext_irq2_3(void)
+{
+ int index;
+
+ ++ext_irq_counts.irq2_3;
+ for (index = 2; index <= 3; ++index) {
+ ext_irq_handler(index);
+ }
+}
+
+/**
+ * ext irq4_15
+ *
+ * External interrupt handler for irqs 4 through 15.
+ *
+ */
+static void
+ext_irq4_15(void)
+{
+ int index;
+
+ ++ext_irq_counts.irq4_15;
+ for (index = 4; index <= 15; ++index) {
+ ext_irq_handler(index);
+ }
+}
+
+#endif /* MYNEWT_VAL(MCU_STM32L0) */
+
/**
* hal gpio clk enable
*
@@ -333,6 +395,8 @@ hal_gpio_pin_to_irq(int pin)
IRQn_Type irqn;
index = MCU_GPIO_PIN_NUM(pin);
+
+#if !MYNEWT_VAL(MCU_STM32L0)
if (index <= 4) {
irqn = EXTI0_IRQn + index;
} else if (index <= 9) {
@@ -340,6 +404,15 @@ hal_gpio_pin_to_irq(int pin)
} else {
irqn = EXTI15_10_IRQn;
}
+#else
+ if (index <= 1) {
+ irqn = EXTI0_1_IRQn;
+ } else if (index <= 3) {
+ irqn = EXTI2_3_IRQn;
+ } else {
+ irqn = EXTI4_15_IRQn;
+ }
+#endif
return irqn;
}
@@ -354,18 +427,33 @@ hal_gpio_set_nvic(IRQn_Type irqn)
uint32_t isr;
switch (irqn) {
+#if !MYNEWT_VAL(MCU_STM32L0)
case EXTI0_IRQn:
isr = (uint32_t)&ext_irq0;
break;
case EXTI1_IRQn:
isr = (uint32_t)&ext_irq1;
break;
+#else /* MYNEWT_VAL(MCU_STM32L0) */
+ case EXTI0_1_IRQn:
+ isr = (uint32_t)&ext_irq0_1;
+ break;
+#endif
+
+#if !MYNEWT_VAL(MCU_STM32L0)
case EXTI2_IRQn:
isr = (uint32_t)&ext_irq2;
break;
case EXTI3_IRQn:
isr = (uint32_t)&ext_irq3;
break;
+#else /* MYNEWT_VAL(MCU_STM32L0) */
+ case EXTI2_3_IRQn:
+ isr = (uint32_t)&ext_irq2_3;
+ break;
+#endif
+
+#if !MYNEWT_VAL(MCU_STM32L0)
case EXTI4_IRQn:
isr = (uint32_t)&ext_irq4;
break;
@@ -375,6 +463,12 @@ hal_gpio_set_nvic(IRQn_Type irqn)
case EXTI15_10_IRQn:
isr = (uint32_t)&ext_irq15_10;
break;
+#else /* MYNEWT_VAL(MCU_STM32L0) */
+ case EXTI4_15_IRQn:
+ isr = (uint32_t)&ext_irq4_15;
+ break;
+#endif
+
default:
assert(0);
break;
diff --git a/hw/mcu/stm/stm32_common/src/hal_spi.c b/hw/mcu/stm/stm32_common/src/hal_spi.c
index 60a0acc..f2df87e 100644
--- a/hw/mcu/stm/stm32_common/src/hal_spi.c
+++ b/hw/mcu/stm/stm32_common/src/hal_spi.c
@@ -602,8 +602,12 @@ hal_spi_config(int spi_num, struct hal_spi_settings *settings)
#if SPI_0_ENABLED
case 0:
__HAL_RCC_SPI1_CLK_ENABLE();
-#if !defined(STM32F1)
+#if !MYNEWT_VAL(MCU_STM32F1)
+ #if !MYNEWT_VAL(MCU_STM32L0)
gpio.Alternate = GPIO_AF5_SPI1;
+ #else
+ gpio.Alternate = GPIO_AF0_SPI1;
+ #endif
#endif
spi->handle.Instance = SPI1;
break;
@@ -611,8 +615,12 @@ hal_spi_config(int spi_num, struct hal_spi_settings *settings)
#if SPI_1_ENABLED
case 1:
__HAL_RCC_SPI2_CLK_ENABLE();
-#if !defined(STM32F1)
+#if !MYNEWT_VAL(MCU_STM32F1)
+ #if !MYNEWT_VAL(MCU_STM32L0)
gpio.Alternate = GPIO_AF5_SPI2;
+ #else
+ gpio.Alternate = GPIO_AF0_SPI2;
+ #endif
#endif
spi->handle.Instance = SPI2;
break;
@@ -620,7 +628,7 @@ hal_spi_config(int spi_num, struct hal_spi_settings *settings)
#if SPI_2_ENABLED
case 2:
__HAL_RCC_SPI3_CLK_ENABLE();
-#if !defined(STM32F1)
+#if !MYNEWT_VAL(MCU_STM32F1)
gpio.Alternate = GPIO_AF6_SPI3;
#endif
spi->handle.Instance = SPI3;
@@ -629,7 +637,7 @@ hal_spi_config(int spi_num, struct hal_spi_settings *settings)
#if SPI_3_ENABLED
case 3:
__HAL_RCC_SPI4_CLK_ENABLE();
-#if !defined(STM32F1)
+#if !MYNEWT_VAL(MCU_STM32F1)
gpio.Alternate = GPIO_AF5_SPI4;
#endif
spi->handle.Instance = SPI4;
@@ -638,7 +646,7 @@ hal_spi_config(int spi_num, struct hal_spi_settings *settings)
#if SPI_4_ENABLED
case 4:
__HAL_RCC_SPI5_CLK_ENABLE();
-#if !defined(STM32F1)
+#if !MYNEWT_VAL(MCU_STM32F1)
gpio.Alternate = GPIO_AF5_SPI5;
#endif
spi->handle.Instance = SPI5;
@@ -647,7 +655,7 @@ hal_spi_config(int spi_num, struct hal_spi_settings *settings)
#if SPI_5_ENABLED
case 5:
__HAL_RCC_SPI6_CLK_ENABLE();
-#if !defined(STM32F1)
+#if !MYNEWT_VAL(MCU_STM32F1)
gpio.Alternate = GPIO_AF5_SPI6;
#endif
spi->handle.Instance = SPI6;
diff --git a/hw/mcu/stm/stm32_common/src/hal_system.c b/hw/mcu/stm/stm32_common/src/hal_system.c
index d5815d3..cffb6c0 100644
--- a/hw/mcu/stm/stm32_common/src/hal_system.c
+++ b/hw/mcu/stm/stm32_common/src/hal_system.c
@@ -38,7 +38,8 @@ hal_system_reset(void)
int
hal_debugger_connected(void)
{
- return CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk;
+ /* FIXME */
+ return 0;
}
uint32_t
diff --git a/hw/mcu/stm/stm32_common/src/hal_timer.c b/hw/mcu/stm/stm32_common/src/hal_timer.c
index 7410668..1bd9e68 100644
--- a/hw/mcu/stm/stm32_common/src/hal_timer.c
+++ b/hw/mcu/stm/stm32_common/src/hal_timer.c
@@ -28,6 +28,11 @@
#include "mcu/stm32_hal.h"
#include "stm32_common/stm32_hal.h"
+#if MYNEWT_VAL(MCU_STM32L0)
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
+#endif
+
#define STM32_OFLOW_VALUE (0x10000UL)
#define STM32_NSEC_PER_SEC (1000000000UL)
@@ -275,6 +280,18 @@ stm32_hw_setup(int num, TIM_TypeDef *regs)
__HAL_RCC_TIM17_CLK_ENABLE();
}
#endif
+#ifdef TIM21
+ if (regs == TIM21) {
+ stm32_tmr_reg_irq(TIM21_IRQn, func);
+ __HAL_RCC_TIM21_CLK_ENABLE();
+ }
+#endif
+#ifdef TIM22
+ if (regs == TIM22) {
+ stm32_tmr_reg_irq(TIM22_IRQn, func);
+ __HAL_RCC_TIM22_CLK_ENABLE();
+ }
+#endif
}
static void
@@ -335,6 +352,16 @@ stm32_hw_setdown(TIM_TypeDef *regs)
__HAL_RCC_TIM17_CLK_DISABLE();
}
#endif
+#ifdef TIM21
+ if (regs == TIM21) {
+ __HAL_RCC_TIM21_CLK_DISABLE();
+ }
+#endif
+#ifdef TIM22
+ if (regs == TIM22) {
+ __HAL_RCC_TIM22_CLK_DISABLE();
+ }
+#endif
}
/**
@@ -424,6 +451,16 @@ hal_timer_init(int num, void *cfg)
__HAL_DBGMCU_FREEZE_TIM17();
}
#endif
+#ifdef TIM21
+ if (regs == TIM21) {
+ __HAL_DBGMCU_FREEZE_TIM21();
+ }
+#endif
+#ifdef TIM22
+ if (regs == TIM22) {
+ __HAL_DBGMCU_FREEZE_TIM22();
+ }
+#endif
return 0;
}
diff --git a/hw/mcu/stm/stm32_common/src/stm32_driver_mod_timer.c b/hw/mcu/stm/stm32_common/src/stm32_driver_mod_timer.c
new file mode 100644
index 0000000..e3b72e1
--- /dev/null
+++ b/hw/mcu/stm/stm32_common/src/stm32_driver_mod_timer.c
@@ -0,0 +1,86 @@
+/**
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "os/mynewt.h"
+#include "mcu/stm32_hal.h"
+
+/* XXX: Included functions are copied verbatim from stm32l0xx_hal_tim.c
+ * because they are defined in STM32Cube L0 as static functions.
+ */
+#if MYNEWT_VAL(MCU_STM32L0)
+#include "stm32l0xx_hal.h"
+
+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
+{
+ uint32_t tmpcr1 = 0U;
+ tmpcr1 = TIMx->CR1;
+
+ /* Set TIM Time Base Unit parameters ---------------------------------------*/
+ if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
+ {
+ /* Select the Counter Mode */
+ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+ tmpcr1 |= Structure->CounterMode;
+ }
+
+ if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
+ {
+ /* Set the clock division */
+ tmpcr1 &= ~TIM_CR1_CKD;
+ tmpcr1 |= (uint32_t)Structure->ClockDivision;
+ }
+
+ TIMx->CR1 = tmpcr1;
+
+ /* Set the Autoreload value */
+ TIMx->ARR = (uint32_t)Structure->Period ;
+
+ /* Set the Prescaler value */
+ TIMx->PSC = (uint32_t)Structure->Prescaler;
+
+ /* Generate an update event to reload the Prescaler value immediatly */
+ TIMx->EGR = TIM_EGR_UG;
+}
+
+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
+{
+ uint32_t tmp = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_TIM_CCX_INSTANCE(TIMx,Channel));
+
+ tmp = TIM_CCER_CC1E << Channel;
+
+ /* Reset the CCxE Bit */
+ TIMx->CCER &= ~tmp;
+
+ /* Set or reset the CCxE Bit */
+ TIMx->CCER |= (uint32_t)(ChannelState << Channel);
+}
+
+#endif
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/