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Posted to commits@nuttx.apache.org by gi...@apache.org on 2023/08/25 00:17:23 UTC
[nuttx-website] branch asf-site updated: Publishing web: 07abea83aab63736f2895f109c448ae631509f46 docs: 606b6d9310fb25c7d92c6f95bf61737e3c79fa0f
This is an automated email from the ASF dual-hosted git repository.
github-bot pushed a commit to branch asf-site
in repository https://gitbox.apache.org/repos/asf/nuttx-website.git
The following commit(s) were added to refs/heads/asf-site by this push:
new 5860049d Publishing web: 07abea83aab63736f2895f109c448ae631509f46 docs: 606b6d9310fb25c7d92c6f95bf61737e3c79fa0f
5860049d is described below
commit 5860049daf5c89d50fafe9df5f520c0e20d46c1f
Author: Alin Jerpelea <al...@sony.com>
AuthorDate: Fri Aug 25 00:13:28 2023 +0000
Publishing web: 07abea83aab63736f2895f109c448ae631509f46 docs: 606b6d9310fb25c7d92c6f95bf61737e3c79fa0f
---
content/docs/10.0.0/index.html | 2 +-
content/docs/10.0.0/searchindex.js | 2 +-
content/docs/10.0.1/index.html | 2 +-
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content/docs/12.2.1/index.html | 2 +-
content/docs/12.2.1/searchindex.js | 2 +-
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.../arm/stm32f1/boards/fire-stm32v2/index.rst.txt | 594 +++++
.../arm/stm32f1/boards/hymini-stm32/index.rst.txt | 514 ++++
.../arm/stm32f1/boards/maple/index.rst.txt | 214 ++
.../arm/stm32f1/boards/nucleo-f103rb/index.rst.txt | 71 +
.../stm32f1/boards/olimexino-stm32/index.rst.txt | 3 +
.../arm/stm32f1/boards/shenzhou/index.rst.txt | 570 +++++
.../arm/stm32f1/boards/stm3210e-eval/index.rst.txt | 912 +++++++
.../arm/stm32f1/boards/stm32_tiny/index.rst.txt | 456 ++++
.../stm32f1/boards/stm32butterfly2/index.rst.txt | 3 +
.../stm32f1/boards/stm32f103-minimum/index.rst.txt | 882 +++++++
.../stm32f1/boards/stm32vldiscovery/index.rst.txt | 215 ++
.../boards/viewtool-stm32f107/index.rst.txt | 1116 +++++++++
.../_sources/platforms/arm/stm32f1/index.rst.txt | 22 +
.../arm/stm32f4/boards/axoloti/index.rst.txt | 21 +
.../stm32f4/boards/clicker2-stm32/index.rst.txt | 798 ++++++
.../stm32f4/boards/mikroe-stm32f4/index.rst.txt | 372 +++
.../arm/stm32f4/boards/nucleo-f401re/index.rst.txt | 394 +++
.../arm/stm32f4/boards/nucleo-f410rb/index.rst.txt | 223 ++
.../arm/stm32f4/boards/nucleo-f411re/index.rst.txt | 394 +++
.../arm/stm32f4/boards/nucleo-f412zg/index.rst.txt | 222 ++
.../arm/stm32f4/boards/nucleo-f429zi/index.rst.txt | 3 +
.../arm/stm32f4/boards/nucleo-f446re/index.rst.txt | 494 ++++
.../stm32f4/boards/olimex-stm32-e407/index.rst.txt | 210 ++
.../stm32f4/boards/olimex-stm32-h405/index.rst.txt | 28 +
.../stm32f4/boards/olimex-stm32-h407/index.rst.txt | 33 +
.../stm32f4/boards/olimex-stm32-p407/index.rst.txt | 574 +++++
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.../stm32f4/boards/stm32f411-minimum/index.rst.txt | 123 +
.../stm32f4/boards/stm32f411e-disco/index.rst.txt | 8 +
.../stm32f4/boards/stm32f429i-disco/index.rst.txt | 749 ++++++
.../stm32f4/boards/stm32f4discovery/index.rst.txt | 2182 +++++++++++++++++
.../_sources/platforms/arm/stm32f4/index.rst.txt | 536 +++++
.../arm/stm32f7/boards/nucleo-f722/index.rst.txt | 379 +++
.../arm/stm32f7/boards/nucleo-f746/index.rst.txt | 421 ++++
.../arm/stm32f7/boards/nucleo-f767/index.rst.txt | 423 ++++
.../stm32f7/boards/steval-eth001v1/index.rst.txt | 18 +
.../arm/stm32f7/boards/stm32f746-ws/index.rst.txt | 3 +
.../stm32f7/boards/stm32f746g-disco/index.rst.txt | 302 +++
.../stm32f7/boards/stm32f769i-disco/index.rst.txt | 147 ++
.../boards/stm32f777zit6-meadow/index.rst.txt | 3 +
.../_sources/platforms/arm/stm32f7/index.rst.txt | 434 ++++
.../stm32l4/boards/b-l475e-iot01a/index.rst.txt | 620 +++++
.../arm/stm32l4/boards/nucleo-l432kc/index.rst.txt | 449 ++++
.../arm/stm32l4/boards/nucleo-l452re/index.rst.txt | 238 ++
.../arm/stm32l4/boards/nucleo-l476rg/index.rst.txt | 567 +++++
.../arm/stm32l4/boards/nucleo-l496zg/index.rst.txt | 256 ++
.../stm32l4/boards/steval-stlcs01v1/index.rst.txt | 16 +
.../arm/stm32l4/boards/stm32l476-mdk/index.rst.txt | 110 +
.../stm32l4/boards/stm32l476vg-disco/index.rst.txt | 527 ++++
.../stm32l4/boards/stm32l4r9ai-disco/index.rst.txt | 421 ++++
.../_sources/platforms/arm/stm32l4/index.rst.txt | 114 +
.../_sources/platforms/arm/stm32wl5/index.rst.txt | 6 +-
content/docs/latest/index.html | 2 +-
content/docs/latest/objects.inv | Bin 54447 -> 65378 bytes
.../platforms/arm/a64/boards/pinephone/index.html | 6 +-
content/docs/latest/platforms/arm/a64/index.html | 6 +-
.../arm/imxrt/boards/imxrt1020-evk/index.html | 6 +-
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.../arm/imxrt/boards/teensy-4.x/index.html | 6 +-
content/docs/latest/platforms/arm/imxrt/index.html | 6 +-
content/docs/latest/platforms/arm/index.html | 12 +-
.../boards/arduino-nano-33ble-rev2/index.html | 6 +-
.../arm/nrf52/boards/arduino-nano-33ble/index.html | 6 +-
.../arm/nrf52/boards/nrf52-feather/intex.html | 6 +-
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.../arm/nrf52/boards/nrf52840-dongle/index.html | 6 +-
.../platforms/arm/nrf52/boards/thingy52/index.html | 6 +-
content/docs/latest/platforms/arm/nrf52/index.html | 6 +-
.../arm/nrf53/boards/nrf5340-audio-dk/index.html | 6 +-
.../arm/nrf53/boards/nrf5340-dk/index.html | 6 +-
.../platforms/arm/nrf53/boards/thingy53/index.html | 6 +-
content/docs/latest/platforms/arm/nrf53/index.html | 6 +-
.../arm/nrf91/boards/nrf9160-dk/index.html | 6 +-
content/docs/latest/platforms/arm/nrf91/index.html | 6 +-
.../boards/adafruit-feather-rp2040/index.html | 6 +-
.../arm/rp2040/boards/adafruit-kb2040/index.html | 6 +-
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content/docs/latest/platforms/arm/samv7/index.html | 6 +-
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.../arm/stm32f0/boards/nucleo-f091rc/index.html | 6 +-
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.../docs/latest/platforms/arm/stm32f0/index.html | 6 +-
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.../arm/stm32f1/boards/fire-stm32v2/index.html | 434 ++++
.../arm/stm32f1/boards/hymini-stm32/index.html | 736 ++++++
.../boards/maple}/index.html | 432 ++--
.../boards/nucleo-f103rb}/index.html | 68 +-
.../boards/olimexino-stm32}/index.html | 51 +-
.../boards/shenzhou}/index.html | 434 ++--
.../arm/stm32f1/boards/stm3210e-eval/index.html | 958 ++++++++
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.../stm32f1/boards/viewtool-stm32f107/index.html | 1297 ++++++++++
.../platforms/arm/{stm32g4 => stm32f1}/index.html | 70 +-
.../arm/stm32f2/boards/emw3162/index.html | 6 +-
.../arm/stm32f2/boards/nucleo-f207zg/index.html | 6 +-
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.../arm/stm32f4/boards/clicker2-stm32/index.html | 1120 +++++++++
.../arm/stm32f4/boards/mikroe-stm32f4/index.html | 624 +++++
.../arm/stm32f4/boards/nucleo-f401re/index.html | 656 +++++
.../boards/nucleo-f410rb}/index.html | 402 ++--
.../arm/stm32f4/boards/nucleo-f411re/index.html | 656 +++++
.../boards/nucleo-f412zg}/index.html | 399 ++-
.../boards/nucleo-f429zi}/index.html | 95 +-
.../arm/stm32f4/boards/nucleo-f446re/index.html | 700 ++++++
.../stm32f4/boards/olimex-stm32-e407/index.html | 436 ++++
.../boards/olimex-stm32-h405}/index.html | 89 +-
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.../stm32f4/boards/olimex-stm32-p407/index.html | 713 ++++++
.../boards/omnibusf4}/index.html | 115 +-
.../boards/stm3240g-eval}/index.html | 880 ++++---
.../boards/stm32f411-minimum}/index.html | 270 ++-
.../boards/stm32f411e-disco}/index.html | 98 +-
.../arm/stm32f4/boards/stm32f429i-disco/index.html | 925 +++++++
.../arm/stm32f4/boards/stm32f4discovery/index.html | 2532 ++++++++++++++++++++
.../docs/latest/platforms/arm/stm32f4/index.html | 880 +++++++
.../arm/stm32f7/boards/nucleo-f722/index.html | 661 +++++
.../arm/stm32f7/boards/nucleo-f746/index.html | 700 ++++++
.../arm/stm32f7/boards/nucleo-f767/index.html | 701 ++++++
.../boards/steval-eth001v1}/index.html | 93 +-
.../boards/stm32f746-ws}/index.html | 60 +-
.../boards/stm32f746g-disco}/index.html | 442 ++--
.../boards/stm32f769i-disco}/index.html | 306 ++-
.../boards/stm32f777zit6-meadow}/index.html | 60 +-
.../platforms/arm/{stm32f3 => stm32f7}/index.html | 330 ++-
.../arm/stm32g0/boards/nucleo-g070rb/index.html | 6 +-
.../arm/stm32g0/boards/nucleo-g071rb/index.html | 6 +-
.../arm/stm32g0/boards/stm32g071b-disco/index.html | 6 +-
.../docs/latest/platforms/arm/stm32g0/index.html | 10 +-
.../arm/stm32g4/boards/b-g431b-esc1/index.html | 6 +-
.../arm/stm32g4/boards/b-g474e-dpow1/index.html | 6 +-
.../arm/stm32g4/boards/nucleo-g431kb/index.html | 6 +-
.../arm/stm32g4/boards/nucleo-g431rb/index.html | 6 +-
.../arm/stm32g4/boards/nucleo-g474re/index.html | 6 +-
.../docs/latest/platforms/arm/stm32g4/index.html | 6 +-
.../arm/stm32h7/boards/nucleo-h743zi/index.html | 6 +-
.../arm/stm32h7/boards/nucleo-h743zi2/index.html | 6 +-
.../arm/stm32h7/boards/nucleo-h745zi/index.html | 6 +-
.../arm/stm32h7/boards/stm32h745i-disco/index.html | 6 +-
.../arm/stm32h7/boards/stm32h747i-disco/index.html | 6 +-
.../docs/latest/platforms/arm/stm32h7/index.html | 6 +-
.../arm/stm32l0/boards/b-l072z-lrwan1/index.html | 6 +-
.../arm/stm32l0/boards/nucleo-l073rz/index.html | 6 +-
.../arm/stm32l0/boards/stm32l0538-disco/index.html | 6 +-
.../docs/latest/platforms/arm/stm32l0/index.html | 6 +-
.../arm/stm32l1/boards/nucleo-l152re/index.html | 6 +-
.../arm/stm32l1/boards/stm32ldiscovery/index.html | 10 +-
.../docs/latest/platforms/arm/stm32l1/index.html | 6 +-
.../arm/stm32l4/boards/b-l475e-iot01a/index.html | 841 +++++++
.../arm/stm32l4/boards/nucleo-l432kc/index.html | 694 ++++++
.../boards/nucleo-l452re}/index.html | 195 +-
.../arm/stm32l4/boards/nucleo-l476rg/index.html | 883 +++++++
.../boards/nucleo-l496zg}/index.html | 391 +--
.../boards/steval-stlcs01v1}/index.html | 88 +-
.../boards/stm32l476-mdk}/index.html | 265 +-
.../stm32l4/boards/stm32l476vg-disco/index.html | 872 +++++++
.../stm32l4/boards/stm32l4r9ai-disco/index.html | 676 ++++++
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.../arm/stm32l5/boards/nucleo-l552ze/index.html | 6 +-
.../arm/stm32l5/boards/stm32l562e-dk/index.html | 6 +-
.../docs/latest/platforms/arm/stm32l5/index.html | 10 +-
.../arm/stm32u5/boards/b-u585i-iot02a/index.html | 6 +-
.../arm/stm32u5/boards/nucleo-u5a5zj-q/index.html | 6 +-
.../docs/latest/platforms/arm/stm32u5/index.html | 6 +-
.../arm/stm32wb/boards/flipperzer/index.html | 6 +-
.../arm/stm32wb/boards/nucleo-wb55rg/index.html | 10 +-
.../docs/latest/platforms/arm/stm32wb/index.html | 6 +-
.../arm/stm32wl5/boards/nucleo-wl55jc/index.html | 12 +-
.../docs/latest/platforms/arm/stm32wl5/index.html | 14 +-
.../arm/xmc4/boards/xmc4500-relax/index.html | 6 +-
.../arm/xmc4/boards/xmc4700-relax/index.html | 6 +-
content/docs/latest/platforms/arm/xmc4/index.html | 6 +-
content/docs/latest/platforms/index.html | 64 +-
content/docs/latest/reference/user/07_signals.html | 4 +-
content/docs/latest/reference/user/structures.html | 2 +-
content/docs/latest/searchindex.js | 2 +-
content/feed.xml | 4 +-
235 files changed, 44574 insertions(+), 3456 deletions(-)
diff --git a/content/docs/10.0.0/index.html b/content/docs/10.0.0/index.html
index 11701ff5..a110ef91 100644
--- a/content/docs/10.0.0/index.html
+++ b/content/docs/10.0.0/index.html
@@ -131,7 +131,7 @@ by following these <a class="reference internal" href="contributing/documentatio
<section id="nuttx-documentation">
<h1>NuttX Documentation<a class="headerlink" href="#nuttx-documentation" title="Permalink to this heading"></a></h1>
<p>NuttX is a real-time operating system (RTOS) with an emphasis on standards compliance and small footprint. Scalable from 8-bit to 32-bit microcontroller environments, the primary governing standards in NuttX are Posix and ANSI standards. Additional standard APIs from Unix and other common RTOS’s (such as VxWorks) are adopted for functionality not available under these standards, or for functionality that is not appropriate for deeply-embedded environments (such as fork()).</p>
-<p>Last Updated: 24 August 23 at 00:09</p>
+<p>Last Updated: 25 August 23 at 00:09</p>
<div class="toctree-wrapper compound">
<p class="caption" role="heading"><span class="caption-text">Table of Contents</span></p>
<ul class="current">
diff --git a/content/docs/10.0.0/searchindex.js b/content/docs/10.0.0/searchindex.js
index aae61b79..f23717e7 100644
--- a/content/docs/10.0.0/searchindex.js
+++ b/content/docs/10.0.0/searchindex.js
@@ -1 +1 @@
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\ No newline at end of file
+Search.setIndex({"docnames": ["applications/index", "boards/index", "components/binfmt", "components/drivers/block/index", "components/drivers/character/analog", "components/drivers/character/can", "components/drivers/character/index", "components/drivers/character/keypad", "components/drivers/character/pwm", "components/drivers/character/quadrature", "components/drivers/character/rtc", "components/drivers/character/serial", "components/drivers/character/timer", "components/drivers/chara [...]
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diff --git a/content/docs/10.0.1/index.html b/content/docs/10.0.1/index.html
index ade46d1d..967ae236 100644
--- a/content/docs/10.0.1/index.html
+++ b/content/docs/10.0.1/index.html
@@ -151,7 +151,7 @@ by following these <a class="reference internal" href="contributing/documentatio
<section id="nuttx-documentation">
<h1>NuttX Documentation<a class="headerlink" href="#nuttx-documentation" title="Permalink to this heading"></a></h1>
<p>NuttX is a real-time operating system (RTOS) with an emphasis on standards compliance and small footprint. Scalable from 8-bit to 32-bit microcontroller environments, the primary governing standards in NuttX are Posix and ANSI standards. Additional standard APIs from Unix and other common RTOS’s (such as VxWorks) are adopted for functionality not available under these standards, or for functionality that is not appropriate for deeply-embedded environments (such as fork()).</p>
-<p>Last Updated: 24 August 23 at 00:09</p>
+<p>Last Updated: 25 August 23 at 00:09</p>
<div class="toctree-wrapper compound">
<p class="caption" role="heading"><span class="caption-text">Table of Contents</span></p>
<ul class="current">
diff --git a/content/docs/10.0.1/searchindex.js b/content/docs/10.0.1/searchindex.js
index ad10f217..3f248978 100644
--- a/content/docs/10.0.1/searchindex.js
+++ b/content/docs/10.0.1/searchindex.js
@@ -1 +1 @@
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\ No newline at end of file
+Search.setIndex({"docnames": ["applications/index", "boards/index", "components/binfmt", "components/drivers/block/index", "components/drivers/character/analog", "components/drivers/character/can", "components/drivers/character/index", "components/drivers/character/keypad", "components/drivers/character/pwm", "components/drivers/character/quadrature", "components/drivers/character/rtc", "components/drivers/character/serial", "components/drivers/character/timer", "components/drivers/chara [...]
\ No newline at end of file
diff --git a/content/docs/10.1.0/index.html b/content/docs/10.1.0/index.html
index bde92b71..dc35e852 100644
--- a/content/docs/10.1.0/index.html
+++ b/content/docs/10.1.0/index.html
@@ -150,7 +150,7 @@ by following these <a class="reference internal" href="contributing/documentatio
<section id="nuttx-documentation">
<h1>NuttX Documentation<a class="headerlink" href="#nuttx-documentation" title="Permalink to this heading"></a></h1>
<p>NuttX is a real-time operating system (RTOS) with an emphasis on standards compliance and small footprint. Scalable from 8-bit to 64-bit microcontroller environments, the primary governing standards in NuttX are POSIX and ANSI standards. Additional standard APIs from Unix and other common RTOS’s (such as VxWorks) are adopted for functionality not available under these standards, or for functionality that is not appropriate for deeply-embedded environments (such as fork()).</p>
-<p>Last Updated: 24 August 23 at 00:09</p>
+<p>Last Updated: 25 August 23 at 00:09</p>
<div class="toctree-wrapper compound">
<p class="caption" role="heading"><span class="caption-text">Table of Contents</span></p>
<ul class="current">
diff --git a/content/docs/10.1.0/searchindex.js b/content/docs/10.1.0/searchindex.js
index bf77bc69..16c90e09 100644
--- a/content/docs/10.1.0/searchindex.js
+++ b/content/docs/10.1.0/searchindex.js
@@ -1 +1 @@
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\ No newline at end of file
+Search.setIndex({"docnames": ["applications/index", "applications/nsh/builtin", "applications/nsh/commands", "applications/nsh/config", "applications/nsh/customizing", "applications/nsh/index", "applications/nsh/installation", "applications/nsh/login", "applications/nsh/nsh", "components/binfmt", "components/drivers/block/index", "components/drivers/character/analog", "components/drivers/character/can", "components/drivers/character/foc", "components/drivers/character/index", "components [...]
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diff --git a/content/docs/10.2.0/index.html b/content/docs/10.2.0/index.html
index b0a7c021..b9457412 100644
--- a/content/docs/10.2.0/index.html
+++ b/content/docs/10.2.0/index.html
@@ -151,7 +151,7 @@ by following these <a class="reference internal" href="contributing/documentatio
<section id="nuttx-documentation">
<h1>NuttX Documentation<a class="headerlink" href="#nuttx-documentation" title="Permalink to this heading"></a></h1>
<p>NuttX is a real-time operating system (RTOS) with an emphasis on standards compliance and small footprint. Scalable from 8-bit to 64-bit microcontroller environments, the primary governing standards in NuttX are POSIX and ANSI standards. Additional standard APIs from Unix and other common RTOS’s (such as VxWorks) are adopted for functionality not available under these standards, or for functionality that is not appropriate for deeply-embedded environments (such as fork()).</p>
-<p>Last Updated: 24 August 23 at 00:09</p>
+<p>Last Updated: 25 August 23 at 00:10</p>
<div class="toctree-wrapper compound">
<p class="caption" role="heading"><span class="caption-text">Table of Contents</span></p>
<ul class="current">
diff --git a/content/docs/10.2.0/searchindex.js b/content/docs/10.2.0/searchindex.js
index f7e3ef78..a7c3c0c9 100644
--- a/content/docs/10.2.0/searchindex.js
+++ b/content/docs/10.2.0/searchindex.js
@@ -1 +1 @@
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\ No newline at end of file
+Search.setIndex({"docnames": ["applications/index", "applications/nsh/builtin", "applications/nsh/commands", "applications/nsh/config", "applications/nsh/customizing", "applications/nsh/index", "applications/nsh/installation", "applications/nsh/login", "applications/nsh/nsh", "components/binfmt", "components/drivers/block/index", "components/drivers/character/analog", "components/drivers/character/can", "components/drivers/character/foc", "components/drivers/character/index", "components [...]
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diff --git a/content/docs/10.3.0/index.html b/content/docs/10.3.0/index.html
index fcf5a4d6..b9457412 100644
--- a/content/docs/10.3.0/index.html
+++ b/content/docs/10.3.0/index.html
@@ -151,7 +151,7 @@ by following these <a class="reference internal" href="contributing/documentatio
<section id="nuttx-documentation">
<h1>NuttX Documentation<a class="headerlink" href="#nuttx-documentation" title="Permalink to this heading"></a></h1>
<p>NuttX is a real-time operating system (RTOS) with an emphasis on standards compliance and small footprint. Scalable from 8-bit to 64-bit microcontroller environments, the primary governing standards in NuttX are POSIX and ANSI standards. Additional standard APIs from Unix and other common RTOS’s (such as VxWorks) are adopted for functionality not available under these standards, or for functionality that is not appropriate for deeply-embedded environments (such as fork()).</p>
-<p>Last Updated: 24 August 23 at 00:10</p>
+<p>Last Updated: 25 August 23 at 00:10</p>
<div class="toctree-wrapper compound">
<p class="caption" role="heading"><span class="caption-text">Table of Contents</span></p>
<ul class="current">
diff --git a/content/docs/10.3.0/searchindex.js b/content/docs/10.3.0/searchindex.js
index bc8ef527..517bec34 100644
--- a/content/docs/10.3.0/searchindex.js
+++ b/content/docs/10.3.0/searchindex.js
@@ -1 +1 @@
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\ No newline at end of file
+Search.setIndex({"docnames": ["applications/index", "applications/nsh/builtin", "applications/nsh/commands", "applications/nsh/config", "applications/nsh/customizing", "applications/nsh/index", "applications/nsh/installation", "applications/nsh/login", "applications/nsh/nsh", "components/binfmt", "components/drivers/block/index", "components/drivers/character/analog", "components/drivers/character/can", "components/drivers/character/foc", "components/drivers/character/index", "components [...]
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diff --git a/content/docs/11.0.0/index.html b/content/docs/11.0.0/index.html
index fcf5a4d6..b9457412 100644
--- a/content/docs/11.0.0/index.html
+++ b/content/docs/11.0.0/index.html
@@ -151,7 +151,7 @@ by following these <a class="reference internal" href="contributing/documentatio
<section id="nuttx-documentation">
<h1>NuttX Documentation<a class="headerlink" href="#nuttx-documentation" title="Permalink to this heading"></a></h1>
<p>NuttX is a real-time operating system (RTOS) with an emphasis on standards compliance and small footprint. Scalable from 8-bit to 64-bit microcontroller environments, the primary governing standards in NuttX are POSIX and ANSI standards. Additional standard APIs from Unix and other common RTOS’s (such as VxWorks) are adopted for functionality not available under these standards, or for functionality that is not appropriate for deeply-embedded environments (such as fork()).</p>
-<p>Last Updated: 24 August 23 at 00:10</p>
+<p>Last Updated: 25 August 23 at 00:10</p>
<div class="toctree-wrapper compound">
<p class="caption" role="heading"><span class="caption-text">Table of Contents</span></p>
<ul class="current">
diff --git a/content/docs/11.0.0/searchindex.js b/content/docs/11.0.0/searchindex.js
index 2941e949..bf3bebb6 100644
--- a/content/docs/11.0.0/searchindex.js
+++ b/content/docs/11.0.0/searchindex.js
@@ -1 +1 @@
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\ No newline at end of file
+Search.setIndex({"docnames": ["applications/index", "applications/nsh/builtin", "applications/nsh/commands", "applications/nsh/config", "applications/nsh/customizing", "applications/nsh/index", "applications/nsh/installation", "applications/nsh/login", "applications/nsh/nsh", "components/binfmt", "components/drivers/block/index", "components/drivers/character/analog", "components/drivers/character/can", "components/drivers/character/foc", "components/drivers/character/index", "components [...]
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diff --git a/content/docs/12.0.0/index.html b/content/docs/12.0.0/index.html
index f7eea16e..8de70210 100644
--- a/content/docs/12.0.0/index.html
+++ b/content/docs/12.0.0/index.html
@@ -151,7 +151,7 @@ by following these <a class="reference internal" href="contributing/documentatio
<section id="nuttx-documentation">
<h1>NuttX Documentation<a class="headerlink" href="#nuttx-documentation" title="Permalink to this heading"></a></h1>
<p>NuttX is a real-time operating system (RTOS) with an emphasis on standards compliance and small footprint. Scalable from 8-bit to 64-bit microcontroller environments, the primary governing standards in NuttX are POSIX and ANSI standards. Additional standard APIs from Unix and other common RTOS’s (such as VxWorks) are adopted for functionality not available under these standards, or for functionality that is not appropriate for deeply-embedded environments (such as fork()).</p>
-<p>Last Updated: 24 August 23 at 00:10</p>
+<p>Last Updated: 25 August 23 at 00:11</p>
<div class="toctree-wrapper compound">
<p class="caption" role="heading"><span class="caption-text">Table of Contents</span></p>
<ul class="current">
diff --git a/content/docs/12.0.0/searchindex.js b/content/docs/12.0.0/searchindex.js
index 2bcb6a48..4553e5fd 100644
--- a/content/docs/12.0.0/searchindex.js
+++ b/content/docs/12.0.0/searchindex.js
@@ -1 +1 @@
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\ No newline at end of file
+Search.setIndex({"docnames": ["applications/index", "applications/nsh/builtin", "applications/nsh/commands", "applications/nsh/config", "applications/nsh/customizing", "applications/nsh/index", "applications/nsh/installation", "applications/nsh/login", "applications/nsh/nsh", "components/binfmt", "components/drivers/block/index", "components/drivers/character/analog", "components/drivers/character/can", "components/drivers/character/foc", "components/drivers/character/index", "components [...]
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diff --git a/content/docs/12.1.0/index.html b/content/docs/12.1.0/index.html
index 956243f2..6866aff2 100644
--- a/content/docs/12.1.0/index.html
+++ b/content/docs/12.1.0/index.html
@@ -151,7 +151,7 @@ by following these <a class="reference internal" href="contributing/documentatio
<section id="nuttx-documentation">
<h1>NuttX Documentation<a class="headerlink" href="#nuttx-documentation" title="Permalink to this heading"></a></h1>
<p>NuttX is a real-time operating system (RTOS) with an emphasis on standards compliance and small footprint. Scalable from 8-bit to 64-bit microcontroller environments, the primary governing standards in NuttX are POSIX and ANSI standards. Additional standard APIs from Unix and other common RTOS’s (such as VxWorks) are adopted for functionality not available under these standards, or for functionality that is not appropriate for deeply-embedded environments (such as fork()).</p>
-<p>Last Updated: 24 August 23 at 00:11</p>
+<p>Last Updated: 25 August 23 at 00:11</p>
<div class="toctree-wrapper compound">
<p class="caption" role="heading"><span class="caption-text">Table of Contents</span></p>
<ul class="current">
diff --git a/content/docs/12.1.0/searchindex.js b/content/docs/12.1.0/searchindex.js
index f72795b2..a0ed0e8f 100644
--- a/content/docs/12.1.0/searchindex.js
+++ b/content/docs/12.1.0/searchindex.js
@@ -1 +1 @@
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\ No newline at end of file
+Search.setIndex({"docnames": ["applications/index", "applications/nsh/builtin", "applications/nsh/commands", "applications/nsh/config", "applications/nsh/customizing", "applications/nsh/index", "applications/nsh/installation", "applications/nsh/login", "applications/nsh/nsh", "components/binfmt", "components/drivers/block/index", "components/drivers/character/analog", "components/drivers/character/can", "components/drivers/character/foc", "components/drivers/character/index", "components [...]
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diff --git a/content/docs/12.2.0/index.html b/content/docs/12.2.0/index.html
index 94e08d5f..1e1e48b3 100644
--- a/content/docs/12.2.0/index.html
+++ b/content/docs/12.2.0/index.html
@@ -154,7 +154,7 @@ by following these <a class="reference internal" href="contributing/documentatio
<section id="nuttx-documentation">
<h1>NuttX Documentation<a class="headerlink" href="#nuttx-documentation" title="Permalink to this heading"></a></h1>
<p>NuttX is a real-time operating system (RTOS) with an emphasis on standards compliance and small footprint. Scalable from 8-bit to 64-bit microcontroller environments, the primary governing standards in NuttX are POSIX and ANSI standards. Additional standard APIs from Unix and other common RTOS’s (such as VxWorks) are adopted for functionality not available under these standards, or for functionality that is not appropriate for deeply-embedded environments (such as fork()).</p>
-<p>Last Updated: 24 August 23 at 00:11</p>
+<p>Last Updated: 25 August 23 at 00:11</p>
<div class="toctree-wrapper compound">
<p class="caption" role="heading"><span class="caption-text">Table of Contents</span></p>
<ul class="current">
diff --git a/content/docs/12.2.0/searchindex.js b/content/docs/12.2.0/searchindex.js
index 50810e38..1c0e0978 100644
--- a/content/docs/12.2.0/searchindex.js
+++ b/content/docs/12.2.0/searchindex.js
@@ -1 +1 @@
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\ No newline at end of file
+Search.setIndex({"docnames": ["applications/index", "applications/nsh/builtin", "applications/nsh/commands", "applications/nsh/config", "applications/nsh/customizing", "applications/nsh/index", "applications/nsh/installation", "applications/nsh/login", "applications/nsh/nsh", "applications/nxdiag/config", "applications/nxdiag/index", "applications/wapi/commands", "applications/wapi/index", "applications/wapi/wireless", "components/binfmt", "components/drivers/block/index", "components/dr [...]
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diff --git a/content/docs/12.2.1/index.html b/content/docs/12.2.1/index.html
index 94e08d5f..d9087bce 100644
--- a/content/docs/12.2.1/index.html
+++ b/content/docs/12.2.1/index.html
@@ -154,7 +154,7 @@ by following these <a class="reference internal" href="contributing/documentatio
<section id="nuttx-documentation">
<h1>NuttX Documentation<a class="headerlink" href="#nuttx-documentation" title="Permalink to this heading"></a></h1>
<p>NuttX is a real-time operating system (RTOS) with an emphasis on standards compliance and small footprint. Scalable from 8-bit to 64-bit microcontroller environments, the primary governing standards in NuttX are POSIX and ANSI standards. Additional standard APIs from Unix and other common RTOS’s (such as VxWorks) are adopted for functionality not available under these standards, or for functionality that is not appropriate for deeply-embedded environments (such as fork()).</p>
-<p>Last Updated: 24 August 23 at 00:11</p>
+<p>Last Updated: 25 August 23 at 00:12</p>
<div class="toctree-wrapper compound">
<p class="caption" role="heading"><span class="caption-text">Table of Contents</span></p>
<ul class="current">
diff --git a/content/docs/12.2.1/searchindex.js b/content/docs/12.2.1/searchindex.js
index d303d436..9490cebd 100644
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\ No newline at end of file
+Search.setIndex({"docnames": ["applications/index", "applications/nsh/builtin", "applications/nsh/commands", "applications/nsh/config", "applications/nsh/customizing", "applications/nsh/index", "applications/nsh/installation", "applications/nsh/login", "applications/nsh/nsh", "applications/nxdiag/config", "applications/nxdiag/index", "applications/wapi/commands", "applications/wapi/index", "applications/wapi/wireless", "components/binfmt", "components/drivers/block/index", "components/dr [...]
\ No newline at end of file
diff --git a/content/docs/latest/_sources/platforms/arm/stm32f1/boards/cloudctrl/index.rst.txt b/content/docs/latest/_sources/platforms/arm/stm32f1/boards/cloudctrl/index.rst.txt
new file mode 100644
index 00000000..87a09202
--- /dev/null
+++ b/content/docs/latest/_sources/platforms/arm/stm32f1/boards/cloudctrl/index.rst.txt
@@ -0,0 +1,559 @@
+===============
+CloudController
+===============
+
+This README discusses issues unique to NuttX configurations for the CloudController
+development board featuring the STMicro STM32F107VCT MCU.
+
+Features of the CloudController board include:
+
+- STM32F107VCT
+- 10/100M PHY (DM9161AEP)
+- USB OTG
+- USART connectos (USART1-2)
+- SPI Flash (W25X16)
+- (3) LEDs (LED1-3)
+- (3) Buttons (KEY1-3, USERKEY2, USERKEY, TEMPER, WAKEUP)
+- 5V/3.3V power conversion
+- SWD
+
+STM32F107VCT Pin Usage
+======================
+
+::
+
+ == ==== ============== ===================================================================
+ PN NAME SIGNAL NOTES
+ == ==== ============== ===================================================================
+ **23 PA0 WAKEUP Connected to KEY4. Active low: Closing KEY4 pulls WAKEUP to ground.
+ 24 PA1 MII_RX_CLK
+ RMII_REF_CLK
+ 25 PA2 MII_MDIO
+ 26 PA3 315M_VT
+ 29 PA4 DAC_OUT1 To CON5(CN14)
+ 30 PA5 DAC_OUT2 To CON5(CN14). JP10
+ SPI1_SCK To the SD card, SPI FLASH
+ 31 PA6 SPI1_MISO To the SD card, SPI FLASH
+ 32 PA7 SPI1_MOSI To the SD card, SPI FLASH
+ 67 PA8 MCO To DM9161AEP PHY
+ 68 PA9 USB_VBUS MINI-USB-AB. JP3
+ USART1_TX MAX3232 to CN5
+ 69 PA10 USB_ID MINI-USB-AB. JP5
+ USART1_RX MAX3232 to CN5
+ 70 PA11 USB_DM MINI-USB-AB
+ 71 PA12 USB_DP MINI-USB-AB
+ 72 PA13 TMS/SWDIO
+ 76 PA14 TCK/SWCLK
+ 77 PA15 TDI
+ == ==== ============== ===================================================================
+
+ == ==== ============== ===================================================================
+ PN NAME SIGNAL NOTES
+ == ==== ============== ===================================================================
+ 35 PB0 ADC_IN1 To CON5(CN14)
+ 36 PB1 ADC_IN2 To CON5(CN14)
+ 37 PB2 DATA_LE To TFT LCD (CN13)
+ BOOT1 JP13
+ 89 PB3 TDO/SWO
+ 90 PB4 TRST
+ 91 PB5 CAN2_RX
+ 92 PB6 CAN2_TX JP11
+ I2C1_SCL
+ 93 PB7 I2C1_SDA
+ 95 PB8 USB_PWR Drives USB VBUS
+ 96 PB9 F_CS To both the TFT LCD (CN13) and to the W25X16 SPI FLASH
+ 47 PB10 USERKEY Connected to KEY2
+ 48 PB11 MII_TX_EN Ethernet PHY
+ 51 PB12 I2S_WS Audio DAC
+ MII_TXD0 Ethernet PHY
+ 52 PB13 I2S_CK Audio DAC
+ MII_TXD1 Ethernet PHY
+ 53 PB14 SD_CD There is confusion here. Schematic is wrong LCD_WR is PB14.
+ 54 PB15 I2S_DIN Audio DAC
+ == ==== ============== ===================================================================
+
+ == ==== ============== ===================================================================
+ PN NAME SIGNAL NOTES
+ == ==== ============== ===================================================================
+ 15 PC0 POTENTIO_METER
+ 16 PC1 MII_MDC Ethernet PHY
+ 17 PC2 WIRELESS_INT
+ 18 PC3 WIRELESS_CE To the NRF24L01 2.4G wireless module
+ 33 PC4 USERKEY2 Connected to KEY1
+ 34 PC5 TP_INT JP6. To TFT LCD (CN13) module
+ MII_INT Ethernet PHY
+ 63 PC6 I2S_MCK Audio DAC. Active low: Pulled high
+ 64 PC7 PCM1770_CS Audio DAC. Active low: Pulled high
+ 65 PC8 LCD_CS TFT LCD (CN13). Active low: Pulled high
+ 66 PC9 TP_CS TFT LCD (CN13). Active low: Pulled high
+ 78 PC10 SPI3_SCK To TFT LCD (CN13), the NRF24L01 2.4G wireless module
+ 79 PC11 SPI3_MISO To TFT LCD (CN13), the NRF24L01 2.4G wireless module
+ 80 PC12 SPI3_MOSI To TFT LCD (CN13), the NRF24L01 2.4G wireless module
+ 7 PC13 TAMPER Connected to KEY3
+ 8 PC14 OSC32_IN Y1 32.768Khz XTAL
+ 9 PC15 OSC32_OUT Y1 32.768Khz XTAL
+ == ==== ============== ===================================================================
+
+ == ==== ============== ===================================================================
+ PN NAME SIGNAL NOTES
+ == ==== ============== ===================================================================
+ 81 PD0 CAN1_RX
+ 82 PD1 CAN1_TX
+ 83 PD2 LED1 Active low: Pulled high
+ 84 PD3 LED2 Active low: Pulled high
+ 85 PD4 LED3 Active low: Pulled high
+ 86 PD5 485_TX Same as USART2_TX but goes to SP3485
+ USART2_TX MAX3232 to CN6
+ 87 PD6 485_RX Save as USART2_RX but goes to SP3485 (see JP4)
+ USART2_RX MAX3232 to CN6
+ 88 PD7 LED4 Active low: Pulled high
+ 485_DIR SP3485 read enable (not)
+ 55 PD8 MII_RX_DV Ethernet PHY
+ RMII_CRSDV Ethernet PHY
+ 56 PD9 MII_RXD0 Ethernet PHY
+ 57 PD10 MII_RXD1 Ethernet PHY
+ 58 PD11 SD_CS Active low: Pulled high (See also TFT LCD CN13, pin 32)
+ 59 PD12 WIRELESS_CS To the NRF24L01 2.4G wireless module
+ 60 PD13 LCD_RS To TFT LCD (CN13)
+ 61 PD14 LCD_WR To TFT LCD (CN13). Schematic is wrong LCD_WR is PB14.
+ 62 PD15 LCD_RD To TFT LCD (CN13)
+ == ==== ============== ===================================================================
+
+ == ==== ============== ===================================================================
+ PN NAME SIGNAL NOTES
+ == ==== ============== ===================================================================
+ 97 PE0 DB00 To TFT LCD (CN13)
+ 98 PE1 DB01 To TFT LCD (CN13)
+ 1 PE2 DB02 To TFT LCD (CN13)
+ 2 PE3 DB03 To TFT LCD (CN13)
+ 3 PE4 DB04 To TFT LCD (CN13)
+ 4 PE5 DB05 To TFT LCD (CN13)
+ 5 PE6 DB06 To TFT LCD (CN13)
+ 38 PE7 DB07 To TFT LCD (CN13)
+ 39 PE8 DB08 To TFT LCD (CN13)
+ 40 PE9 DB09 To TFT LCD (CN13)
+ 41 PE10 DB10 To TFT LCD (CN13)
+ 42 PE11 DB11 To TFT LCD (CN13)
+ 43 PE12 DB12 To TFT LCD (CN13)
+ 44 PE13 DB13 To TFT LCD (CN13)
+ 45 PE14 DB14 To TFT LCD (CN13)
+ 46 PE15 DB15 To TFT LCD (CN13)
+ == ==== ============== ===================================================================
+
+ == ==== ============== ===================================================================
+ PN NAME SIGNAL NOTES
+ == ==== ============== ===================================================================
+ 73 N/C
+
+ 12 OSC_IN Y2 25Mhz XTAL
+ 13 OSC_OUT Y2 25Mhz XTAL
+
+ 94 BOOT0 JP15 (3.3V or GND)
+ 14 RESET S5
+ 6 VBAT JP14 (3.3V or battery)
+
+ 49 VSS_1 GND
+ 74 VSS_2 GND
+ 99 VSS_3 GND
+ 27 VSS_4 GND
+ 10 VSS_5 GND
+ 19 VSSA VSSA
+ 20 VREF- VREF-
+ == ==== ============== ===================================================================
+
+LEDs
+====
+
+ The Cloudctrl board has four LEDs labeled LED1, LED2, LED3 and LED4 on the
+ board. These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
+ defined. In that case, the usage by the board port is defined in
+ include/board.h and src/up_leds.c. The LEDs are used to encode OS-related
+ events as follows:
+
+ =================== ======================= ======= ======= ======= ======
+ SYMBOL Meaning LED1[1] LED2 LED3 LED4[4]
+ =================== ======================= ======= ======= ======= ======
+ LED_STARTED NuttX has been started ON OFF OFF OFF
+ LED_HEAPALLOCATE Heap has been allocated OFF ON OFF OFF
+ LED_IRQSENABLED Interrupts enabled ON ON OFF OFF
+ LED_STACKCREATED Idle stack created OFF OFF ON OFF
+ LED_INIRQ In an interrupt[2] ON N/C N/C OFF
+ LED_SIGNAL In a signal handler[3] N/C ON N/C OFF
+ LED_ASSERTION An assertion failed ON ON N/C OFF
+ LED_PANIC The system has crashed N/C N/C N/C ON
+ LED_IDLE STM32 is is sleep mode
+ =================== ======================= ======= ======= ======= ======
+
+ [1] If LED1, LED2, LED3 are statically on, then NuttX probably failed to boot
+ and these LEDs will give you some indication of where the failure was
+ [2] The normal state is LED1 ON and LED1 faintly glowing. This faint glow
+ is because of timer interrupts that result in the LED being illuminated
+ on a small proportion of the time.
+ [3] LED2 may also flicker normally if signals are processed.
+ [4] LED4 may not be available if RS-485 is also used. For RS-485, it will
+ then indicate the RS-485 direction.
+
+Cloudctrl-specific Configuration Options
+============================================
+
+..
+ CONFIG_ARCH - Identifies the arch/ subdirectory. This should be set to:
+
+ CONFIG_ARCH=arm
+
+ CONFIG_ARCH_family - For use in C code:
+
+ CONFIG_ARCH_ARM=y
+
+ CONFIG_ARCH_architecture - For use in C code:
+
+ CONFIG_ARCH_CORTEXM3=y
+
+ CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
+
+ CONFIG_ARCH_CHIP=stm32
+
+ CONFIG_ARCH_CHIP_name - For use in C code to identify the exact chip:
+
+ CONFIG_ARCH_CHIP_STM32F107VC=y
+
+ CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock
+ configuration features.
+
+ CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n
+
+ CONFIG_ARCH_BOARD - Identifies the boards/ subdirectory and
+ hence, the board that supports the particular chip or SoC.
+
+ CONFIG_ARCH_BOARD=shenzhou (for the Cloudctrl development board)
+
+ CONFIG_ARCH_BOARD_name - For use in C code
+
+ CONFIG_ARCH_BOARD_SHENZHOU=y
+
+ CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
+ of delay loops
+
+ CONFIG_ENDIAN_BIG - define if big endian (default is little
+ endian)
+
+ CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case):
+
+ CONFIG_RAM_SIZE=0x00010000 (64Kb)
+
+ CONFIG_RAM_START - The start address of installed DRAM
+
+ CONFIG_RAM_START=0x20000000
+
+ CONFIG_STM32_CCMEXCLUDE - Exclude CCM SRAM from the HEAP
+
+ CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that
+ have LEDs
+
+ CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
+ stack. If defined, this symbol is the size of the interrupt
+ stack in bytes. If not defined, the user task stacks will be
+ used during interrupt handling.
+
+ CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
+
+ CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture.
+
+ Individual subsystems can be enabled:
+
+ AHB
+ ---
+ CONFIG_STM32_DMA1
+ CONFIG_STM32_DMA2
+ CONFIG_STM32_CRC
+ CONFIG_STM32_ETHMAC
+ CONFIG_STM32_OTGFS
+ CONFIG_STM32_IWDG
+ CONFIG_STM32_PWR -- Required for RTC
+
+ APB1 (low speed)
+ ----------------
+ CONFIG_STM32_BKP
+ CONFIG_STM32_TIM2
+ CONFIG_STM32_TIM3
+ CONFIG_STM32_TIM4
+ CONFIG_STM32_TIM5
+ CONFIG_STM32_TIM6
+ CONFIG_STM32_TIM7
+ CONFIG_STM32_USART2
+ CONFIG_STM32_USART3
+ CONFIG_STM32_UART4
+ CONFIG_STM32_UART5
+ CONFIG_STM32_SPI2
+ CONFIG_STM32_SPI3
+ CONFIG_STM32_I2C1
+ CONFIG_STM32_I2C2
+ CONFIG_STM32_CAN1
+ CONFIG_STM32_CAN2
+ CONFIG_STM32_DAC1
+ CONFIG_STM32_DAC2
+ CONFIG_STM32_WWDG
+
+ APB2 (high speed)
+ -----------------
+ CONFIG_STM32_TIM1
+ CONFIG_STM32_SPI1
+ CONFIG_STM32_USART1
+ CONFIG_STM32_ADC1
+ CONFIG_STM32_ADC2
+
+ Timer and I2C devices may need to the following to force power to be applied
+ unconditionally at power up. (Otherwise, the device is powered when it is
+ initialized).
+
+ CONFIG_STM32_FORCEPOWER
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If CONFIG_STM32_TIMn
+ is defined (as above) then the following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation, ADC conversion,
+ or DAC conversion. Note that ADC/DAC require two definition: Not only do you have
+ to assign the timer (n) for used by the ADC or DAC, but then you also have to
+ configure which ADC or DAC (m) it is assigned to.
+
+ CONFIG_STM32_TIMn_PWM Reserve timer n for use by PWM, n=1,..,14
+ CONFIG_STM32_TIMn_ADC Reserve timer n for use by ADC, n=1,..,14
+ CONFIG_STM32_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,14, m=1,..,3
+ CONFIG_STM32_TIMn_DAC Reserve timer n for use by DAC, n=1,..,14
+ CONFIG_STM32_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,14, m=1,..,2
+
+ For each timer that is enabled for PWM usage, we need the following additional
+ configuration settings:
+
+ CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
+
+ NOTE: The STM32 timers are each capable of generating different signals on
+ each of the four channels with different duty cycles. That capability is
+ not supported by this driver: Only one output channel per timer.
+
+ JTAG Enable settings (by default JTAG-DP and SW-DP are disabled):
+
+ CONFIG_STM32_JTAG_FULL_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
+ CONFIG_STM32_JTAG_NOJNTRST_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
+ but without JNTRST.
+ CONFIG_STM32_JTAG_SW_ENABLE - Set JTAG-DP disabled and SW-DP enabled
+
+ STM32107xxx specific device driver settings
+
+ CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=1,2,3) or UART
+ m (m=4,5) for the console and ttys0 (default is the USART1).
+ CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received.
+ This specific the size of the receive buffer
+ CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before
+ being sent. This specific the size of the transmit buffer
+ CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be
+ CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8.
+ CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
+ CONFIG_U[S]ARTn_2STOP - Two stop bits
+
+ CONFIG_STM32_SPI_INTERRUPTS - Select to enable interrupt driven SPI
+ support. Non-interrupt-driven, poll-waiting is recommended if the
+ interrupt rate would be to high in the interrupt driven case.
+ CONFIG_STM32_SPIx_DMA - Use DMA to improve SPIx transfer performance.
+ Cannot be used with CONFIG_STM32_SPI_INTERRUPT.
+
+ CONFIG_STM32_PHYADDR - The 5-bit address of the PHY on the board
+ CONFIG_STM32_MII - Support Ethernet MII interface
+ CONFIG_STM32_MII_MCO - Use MCO to clock the MII interface
+ CONFIG_STM32_RMII - Support Ethernet RMII interface
+ CONFIG_STM32_RMII_MCO - Use MCO to clock the RMII interface
+ CONFIG_STM32_AUTONEG - Use PHY autonegotiation to determine speed and mode
+ CONFIG_STM32_ETHFD - If CONFIG_STM32_AUTONEG is not defined, then this
+ may be defined to select full duplex mode. Default: half-duplex
+ CONFIG_STM32_ETH100MBPS - If CONFIG_STM32_AUTONEG is not defined, then this
+ may be defined to select 100 MBps speed. Default: 10 Mbps
+ CONFIG_STM32_PHYSR - This must be provided if CONFIG_STM32_AUTONEG is
+ defined. The PHY status register address may diff from PHY to PHY. This
+ configuration sets the address of the PHY status register.
+ CONFIG_STM32_PHYSR_SPEED - This must be provided if CONFIG_STM32_AUTONEG is
+ defined. This provides bit mask indicating 10 or 100MBps speed.
+ CONFIG_STM32_PHYSR_100MBPS - This must be provided if CONFIG_STM32_AUTONEG is
+ defined. This provides the value of the speed bit(s) indicating 100MBps speed.
+ CONFIG_STM32_PHYSR_MODE - This must be provided if CONFIG_STM32_AUTONEG is
+ defined. This provide bit mask indicating full or half duplex modes.
+ CONFIG_STM32_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32_AUTONEG is
+ defined. This provides the value of the mode bits indicating full duplex mode.
+ CONFIG_STM32_ETH_PTP - Precision Time Protocol (PTP). Not supported
+ but some hooks are indicated with this condition.
+
+ Cloudctrl CAN Configuration
+
+ CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32_CAN1 or
+ CONFIG_STM32_CAN2 must also be defined)
+ CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages.
+ Default: 8
+ CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests.
+ Default: 4
+ CONFIG_CAN_LOOPBACK - A CAN driver may or may not support a loopback
+ mode for testing. The STM32 CAN driver does support loopback mode.
+ CONFIG_STM32_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN1
+ is defined.
+ CONFIG_STM32_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN2
+ is defined.
+ CONFIG_STM32_CAN_TSEG1 - The number of CAN time quanta in segment 1.
+ Default: 6
+ CONFIG_STM32_CAN_TSEG2 - the number of CAN time quanta in segment 2.
+ Default: 7
+ CONFIG_STM32_CAN_REGDEBUG - If CONFIG_DEBUG_FEATURES is set, this will generate an
+ dump of all CAN registers.
+
+ Cloudctrl LCD Hardware Configuration
+
+ The LCD driver supports the following LCDs on the STM324xG_EVAL board:
+
+ AM-240320L8TNQW00H (LCD_ILI9320 or LCD_ILI9321) OR
+ AM-240320D5TOQW01H (LCD_ILI9325)
+
+ Configuration options.
+
+ CONFIG_LCD_LANDSCAPE - Define for 320x240 display "landscape"
+ support. Default is this 320x240 "landscape" orientation
+ For the Cloudctrl board, the edge opposite from the row of buttons
+ is used as the top of the display in this orientation.
+ CONFIG_LCD_RLANDSCAPE - Define for 320x240 display "reverse
+ landscape" support. Default is this 320x240 "landscape"
+ orientation
+ For the Cloudctrl board, the edge next to the row of buttons
+ is used as the top of the display in this orientation.
+ CONFIG_LCD_PORTRAIT - Define for 240x320 display "portrait"
+ orientation support.
+ CONFIG_LCD_RPORTRAIT - Define for 240x320 display "reverse
+ portrait" orientation support.
+ CONFIG_LCD_RDSHIFT - When reading 16-bit gram data, there appears
+ to be a shift in the returned data. This value fixes the offset.
+ Default 5.
+
+ The LCD driver dynamically selects the LCD based on the reported LCD
+ ID value. However, code size can be reduced by suppressing support for
+ individual LCDs using:
+
+ CONFIG_STM32_ILI9320_DISABLE (includes ILI9321)
+ CONFIG_STM32_ILI9325_DISABLE
+
+ STM32 USB OTG FS Host Driver Support
+
+ Pre-requisites
+
+ CONFIG_USBHOST - Enable USB host support
+ CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block
+ CONFIG_STM32_SYSCFG - Needed
+ CONFIG_SCHED_WORKQUEUE - Worker thread support is required
+
+ Options:
+
+ CONFIG_STM32_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words.
+ Default 128 (512 bytes)
+ CONFIG_STM32_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO
+ in 32-bit words. Default 96 (384 bytes)
+ CONFIG_STM32_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit
+ words. Default 96 (384 bytes)
+ CONFIG_STM32_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: 128
+ CONFIG_STM32_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever
+ want to do that?
+ CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access
+ debug. Depends on CONFIG_DEBUG_FEATURES.
+ CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB
+ packets. Depends on CONFIG_DEBUG_FEATURES.
+
+Configurations
+==============
+
+Each Cloudctrl configuration is maintained in a sub-directory and
+can be selected as follow::
+
+ tools/configure.sh shenzhou:<subdir>
+
+Where <subdir> is one of the following:
+
+nsh
+---
+
+Configures the NuttShell (nsh) located at apps/examples/nsh. The
+Configuration enables both the serial and telnet NSH interfaces.::
+
+ CONFIG_ARM_TOOLCHAIN_GNU_EABI=y : GNU EABI toolchain for Windows
+ CONFIG_NSH_DHCPC=n : DHCP is disabled
+ CONFIG_NSH_IPADDR=0x0a000002 : Target IP address 10.0.0.2
+ CONFIG_NSH_DRIPADDR=0x0a000001 : Host IP address 10.0.0.1
+
+ NOTES:
+ 1. This example assumes that a network is connected. During its
+ initialization, it will try to negotiate the link speed. If you have
+ no network connected when you reset the board, there will be a long
+ delay (maybe 30 seconds?) before anything happens. That is the timeout
+ before the networking finally gives up and decides that no network is
+ available.
+
+ 2. Enabling the ADC example:
+
+ The only internal signal for ADC testing is the potentiometer input:
+
+ ADC1_IN10(PC0) Potentiometer
+
+ External signals are also available on CON5 CN14:
+
+ ADC_IN8 (PB0) CON5 CN14 Pin2
+ ADC_IN9 (PB1) CON5 CN14 Pin1
+
+ The signal selection is hard-coded in boards/shenzhou/src/up_adc.c: The
+ potentiometer input (only) is selected.
+
+ These selections will enable sampling the potentiometer input at 100Hz using
+ Timer 1:
+
+ CONFIG_ANALOG=y : Enable analog device support
+ CONFIG_ADC=y : Enable generic ADC driver support
+ CONFIG_ADC_DMA=n : ADC DMA is not supported
+ CONFIG_STM32_ADC1=y : Enable ADC 1
+ CONFIG_STM32_TIM1=y : Enable Timer 1
+ CONFIG_STM32_TIM1_ADC=y : Use Timer 1 for ADC
+ CONFIG_STM32_TIM1_ADC1=y : Allocate Timer 1 to ADC 1
+ CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=100 : Set sampling frequency to 100Hz
+ CONFIG_STM32_ADC1_TIMTRIG=0 : Trigger on timer output 0
+ CONFIG_STM32_FORCEPOWER=y : Apply power to TIM1 a boot up time
+ CONFIG_EXAMPLES_ADC=y : Enable the apps/examples/adc built-in
+
+nxwm
+----
+
+This is a special configuration setup for the NxWM window manager
+UnitTest. The NxWM window manager can be found here::
+
+ apps/graphics/NxWidgets/nxwm
+
+The NxWM unit test can be found at::
+
+ apps/graphics/NxWidgets/UnitTests/nxwm
+
+NOTE: JP6 selects between the touchscreen interrupt and the MII
+interrupt. It should be positioned 1-2 to enable the touchscreen
+interrupt.
+
+NOTE: Reading from the LCD is not currently supported by this
+configuration. The hardware will support reading from the LCD
+and drivers/lcd/ssd1289.c also supports reading from the LCD.
+This limits some graphics capabilities.
+
+Reading from the LCD is not supported only because it has not
+been test. If you get inspired to test this feature, you can
+turn the LCD read functionality on by setting::
+
+ -CONFIG_LCD_NOGETRUN=y
+ +# CONFIG_LCD_NOGETRUN is not set
+
+ -CONFIG_NX_WRITEONLY=y
+ +# CONFIG_NX_WRITEONLY is not set
+
+thttpd
+------
+
+This builds the THTTPD web server example using the THTTPD and
+the apps/examples/thttpd application.
+
+NOTE: This example can only be built using older GCC toolchains
+due to incompatibilities introduced in later GCC releases.
diff --git a/content/docs/latest/_sources/platforms/arm/stm32f1/boards/et-stm32-stamp/index.rst.txt b/content/docs/latest/_sources/platforms/arm/stm32f1/boards/et-stm32-stamp/index.rst.txt
new file mode 100644
index 00000000..5d680116
--- /dev/null
+++ b/content/docs/latest/_sources/platforms/arm/stm32f1/boards/et-stm32-stamp/index.rst.txt
@@ -0,0 +1,116 @@
+==============
+ET-STM32 Stamp
+==============
+
+This README discusses issues/thoughts unique to NuttX configuration(s) for the
+ET-STM32 Stamp board from Futurlec (https://www.futurlec.com/ET-STM32_Stamp.shtml).
+
+Microprocessor: 32-bit ARM Cortex M3 at 72MHz STM32F103RET6
+Memory: 512 KB Flash and 64 KB SRAM
+I/O Pins Out: 48
+ADCs: 16 (at 12-bit resolution)
+DACs: 2 (at 12-bit resolution)
+Peripherals: RTC, 4 timers, 2 I2Cs, 3 SPI ports, 1 on-board UART (upto 5 channels)
+Other: Sleep, stop, and standby modes; serial wire debug and JTAG interfaces
+
+Please see link below for board specific details:
+
+ https://www.futurlec.com/ET-STM32_Stamp_Technical.shtml
+
+This configuration supports the ET-STM32 Stamp module.
+
+Development Environment
+=======================
+
+Either Linux (recommended), Mac or Cygwin on Windows can be used for the development
+environment. The source has been built only using the GNU (Cortex M) toolchain.
+Other toolchains will likely cause problems.
+
+WSL (Windows Subsystem for Linux) was used to develop, compile and test the NuttX
+build for the ET-STM32 Stamp platform.
+
+Flashing/Programming
+====================
+
+Prerequisites:
+
+1. The ET-STM32 Stamp module from Futurlec.
+
+2. An RS232 connection cable such as the one in this link: (Part code: RS232CONN):
+ https://www.futurlec.com/DevBoardAccessories.shtml
+
+ It has a 4-pin connection header on one end and an RS-232 (DB9) female connector on
+ the other. The 4-pin connector can be directly plugged onto the Stamp module.
+
+3. An RS232 to USB converter cable. Ensure that a suitable driver is installed for
+ the converter cable. When the cable is plugged in (for example), my PC lists the
+ assigned port with this name: "USB-SERIAL CH340 (COM2)".
+
+ Assuming Windows 10, navigate to: This PC -> Manage -> Device Manager -> Ports.
+
+4. ST's Flash loader demonstrator tool. You can download it from here:
+ https://www.st.com/en/development-tools/flasher-stm32.html
+
+ To install the NuttX firmware (nuttx.bin) on the ET-STM32 Stamp:
+
+1. First, power the Stamp module with a 3.3 VDC power supply. I made my own
+ Stamp module fixture using a 3.3 VDC switching regulator, a prototype PCB card
+ and some solder.
+
+2. Insert the RS232CONN into the 4-pin on-board header. The other end should be
+ connected to the USB port of the PC using the RS232-USB converter.
+
+3. Set the BOOT1 jumper on your board to the ISP position.
+
+4. Press the BOOT0 switch. The green "BOOT0=1" LED should light up.
+
+5. Reset the board by pressing on the RESET button.
+
+6. Using the ST Flash loader demonstrator to download the NuttX binary image.
+
+7. Wait until programming is completed and press "Finish". Toggle the
+ BOOT0 switch again. Reset the board.
+
+You will now be presented with the NuttShell (NSH). Enjoy.
+
+Configurations
+==============
+
+Information Common to All Configurations
+----------------------------------------
+
+The ET-STM32 Stamp configuration is maintained in a sub-directory and can be
+selected as follow::
+
+ tools/configure.sh et-stm32-stamp:<subdir>
+
+Before building, make sure the PATH environment variable includes the
+correct path to the directory than holds your toolchain binaries.
+
+And then build NuttX by simply typing the following. At the conclusion of
+the make, the nuttx binary will reside in an ELF file called, simply, nuttx.::
+
+ make
+
+The <subdir> that is provided above as an argument to the tools/configure.sh
+must be in one of the following.
+
+NOTES:
+
+1. These configurations use the mconf-based configuration tool. To
+ change any of these configurations using that tool, you should:
+
+ a. Build and install the kconfig-mconf tool. See nuttx/README.txt
+ see additional README.txt files in the NuttX tools repository.
+
+ b. Execute 'make menuconfig' in nuttx/ in order to start the
+ reconfiguration process.
+
+Configuration Sub-directories
+-----------------------------
+
+nsh:
+----
+
+This configuration directory provide the basic NuttShell (NSH).
+A serial console is provided on USART1.
diff --git a/content/docs/latest/_sources/platforms/arm/stm32f1/boards/fire-stm32v2/index.rst.txt b/content/docs/latest/_sources/platforms/arm/stm32f1/boards/fire-stm32v2/index.rst.txt
new file mode 100644
index 00000000..fce821ad
--- /dev/null
+++ b/content/docs/latest/_sources/platforms/arm/stm32f1/boards/fire-stm32v2/index.rst.txt
@@ -0,0 +1,594 @@
+===========
+fire-stm2v2
+===========
+
+This README discusses issues unique to NuttX configurations for the M3
+Wildfire development board (STM32F103VET6). See http://firestm32.taobao.com
+
+This configuration should support both the version 2 and version 3 of the
+Wildfire board (using NuttX configuration options). However, only version 2
+has been verified.
+
+Pin Configuration
+=================
+
+..
+ === ====== ============== ===================================================================
+ PIN NAME SIGNAL NOTES
+ === ====== ============== ===================================================================
+ 1 PE2 PE2=C=RCLK Camera (P9)
+ 2 PE3 PE3=USB=M USB2.0
+ 3 PE4 PE4=BEEP LS1 Bell (v2)
+ PE4 10Mbps ENC28J60 Interrupt (v3)
+ 4 PE5 (no name) 10Mbps ENC28J60 Interrupt (v2)
+ PE5 KEY1, Low when closed (pulled high if open) (v3)
+ 5 PE6
+ 6 VBAT BT1 Battery (BT1)
+ 7 PC13 Header 7X2
+ 8 PC14 PC14/OSC32=IN Y2 32.768KHz
+ 9 PC15 PC15/OSC32=OUT Y2 32.768KHz
+ 10 VSS_5 DGND
+ 11 VDD_5 3V3
+ 12 OSC_IN Y1 8MHz
+ 13 OSC_OUT Y1 8MHz
+ 14 NRST REST1 Reset switch
+ 15 PC0
+ 16 PC1 PC1/ADC123=IN11 Potentiometer (R16)
+ 17 PC2
+ 18 PC3 PC3=LED1 LED1, Active low (pulled high)
+ 19 VSSA DGND
+ 20 VREF= DGND
+ 21 VREF+ 3V3
+ 22 VDDA 3V3
+ 23 PA0 PA0=C=VSYNC Camera (P9)
+ 24 PA1 PC1/ADC123=IN1
+ 25 PA2 PA2=US2=TX MAX3232, DB9 D7
+ === ====== ============== ===================================================================
+
+ === ====== ============== ===================================================================
+ PIN NAME SIGNAL NOTES
+ === ====== ============== ===================================================================
+ 26 PA3 PA3=US2=RX MAX3232, DB9 D7
+ 27 VSS_4 DGND
+ 28 VDD_4 3V3
+ 29 PA4 PA4=SPI1=NSS 10Mbit ENC28J60, SPI 2M FLASH
+ 30 PA5 PA5=SPI1=SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH
+ 31 PA6 PA6=SPI1=MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH
+ 32 PA7 PA7=SPI1=MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH
+ 33 PC4 PC4=LED2 LED2, Active low (pulled high)
+ 34 PC5 PC5=LED3 LED3, Active low (pulled high)
+ 35 PB0 PB0=KEY1 KEY1, Low when closed (pulled high if open) (v2)
+ PB0 Header P5 (v3)
+ 36 PB1 PB1=KEY2 KEY2, Low when closed (pulled high if open)
+ 37 PB2 BOOT1/DGND
+ 38 PE7 PE7=FSMC_D4 2.4" TFT + Touchscreen
+ 39 PE8 PE8=FSMC_D5 2.4" TFT + Touchscreen
+ 40 PE9 PE9=FSMC_D6 2.4" TFT + Touchscreen
+ 41 PE10 PE10=FSMC_D7 2.4" TFT + Touchscreen
+ 42 PE11 PE11=FSMC_D8 2.4" TFT + Touchscreen
+ 43 PE12 PE12=FSMC_D9 2.4" TFT + Touchscreen
+ 44 PE13 PE13=FSMC_D10 2.4" TFT + Touchscreen
+ 45 PE14 PE14=FSMC_D11 2.4" TFT + Touchscreen
+ 46 PE15 PE15=FSMC_D12 2.4" TFT + Touchscreen
+ 47 PB10 PB10=C=DO_2 Camera (P9)
+ 48 PB11 PB11=MP3=RST MP3
+ PB11=C=DO_3 Camera (P9)
+ 49 VSS_1 DGND
+ 50 VDD_1 3V3
+ === ====== ============== ===================================================================
+
+ === ====== ============== ===================================================================
+ PIN NAME SIGNAL NOTES
+ === ====== ============== ===================================================================
+
+ 51 PB12 PB12=SPI2=NSS MP3
+ PB12=C=DO_4 Camera (P9)
+ 52 PB13 PB13=SPI2=SCK MP3
+ PB13=C=DO_5 Camera (P9)
+ 53 PB14 PB14=SPI2=MISO MP3
+ PB14=C=DO_6 Camera (P9)
+ 54 PB15 PB15=SPI2=MOSI MP3
+ PB15=C=DO_7 Camera (P9)
+ 55 PD8 PD8=FSMC_D13 2.4" TFT + Touchscreen
+ 56 PD9 PD9=FSMC_D14 2.4" TFT + Touchscreen
+ 57 PD10 PD10=FSMC_D15 2.4" TFT + Touchscreen
+ 58 PD11 PD11=FSMC_A16 2.4" TFT + Touchscreen
+ 59 PD12 C=LED_EN Camera (P9)
+ 60 PD13 PD13=LCD/LIGHT 2.4" TFT + Touchscreen
+ 61 PD14 PD14=FSMC_D0 2.4" TFT + Touchscreen
+ 62 PD15 PD15=FSMC_D1 2.4" TFT + Touchscreen
+ 63 PC6 PC6=MP3=XDCS MP3
+ PC6=C=SIO_C Camera (P9)
+ 64 PC7 PC7=MP3=DREQ MP3
+ PC7=C=SIO_D Camera (P9)
+ 65 PC8 PC8=SDIO=D0 SD card, pulled high
+ 66 PC9 PC9=SDIO=D1 SD card, pulled high
+ 67 PA8 PA8=C=XCLK Camera (P9)
+ 68 PA9 PA9=US1=TX MAX3232, DB9 D8
+ 69 PA10 PA10=US1=RX MAX3232, DB9 D8
+ 70 PA11 PA11=USBDM USB2.0
+ 71 PA12 PA12=USBDP USB2.0
+ 72 PA13 PA13=JTMS JTAG
+ 73 N/C
+ 74 VSS_2 DGND
+ 75 VDD_2 3V3
+ === ====== ============== ===================================================================
+
+ === ====== ============== ===================================================================
+ PIN NAME SIGNAL NOTES
+ === ====== ============== ===================================================================
+ 76 PA14 PA14=JTCK JTAG
+ 77 PA15 PA15=JTDI JTAG
+ 78 PC10 PC10=SDIO=D2 SD card, pulled high
+ 79 PC11 PC10=SDIO=D3 SD card, pulled high
+ 80 PC12 PC12=SDIO=CLK SD card
+ 81 PD0 PD0=FSMC_D2 2.4" TFT + Touchscreen
+ 82 PD1 PD1=FSMC_D3 2.4" TFT + Touchscreen
+ 83 PD2 PD2=SDIO=CMD SD card, pulled high
+ 84 PD3 PD3=C=WEN Camera (P9)
+ 85 PD4 PD4=FSMC_NOE 2.4" TFT + Touchscreen
+ 86 PD5 PD5=FSMC_NWE 2.4" TFT + Touchscreen
+ 87 PD6 PD6=C=OE Camera (P9)
+ 88 PD7 PD7=FSMC_NE1 2.4" TFT + Touchscreen
+ 89 PB3 PB3=JTDO JTAG
+ 90 PB4 PB4=NJTRST JTAG
+ 91 PB5 PB5=C=WRST Camera (P9)
+ 92 PB6 PB6=I2C1=SCL 2.4" TFT + Touchscreen, AT24C02
+ 93 PB7 PB7=I2C1=SDA 2.4" TFT + Touchscreen, AT24C02
+ 94 BOOT0 SW3 3V3 or DGND
+ 95 PB8 PB8=CAN=RX CAN transceiver, Header 2H
+ PB8=C=DO_0 Camera (P9)
+ 96 PB9 PB9=CAN=TX CAN transceiver, Header 2H
+ PB9=C=DO_1 Camera (P9)
+ 97 PE0 PE0=C=RRST Camera (P9)
+ 98 PE1 PE1=FSMC_NBL1 2.4" TFT + Touchscreen
+ 99 VSS_3 DGND
+ 100 VDD_3 3V3
+ === ====== ============== ===================================================================
+
+DFU and JTAG
+============
+
+Enbling Support for the DFU Bootloader
+--------------------------------------
+
+The linker files in these projects can be configured to indicate that you
+will be loading code using STMicro built-in USB Device Firmware Upgrade (DFU)
+loader or via some JTAG emulator. You can specify the DFU bootloader by
+adding the following line::
+
+ CONFIG_STM32_DFU=y
+
+to your .config file. Most of the configurations in this directory are set
+up to use the DFU loader.
+
+If CONFIG_STM32_DFU is defined, the code will not be positioned at the beginning
+of FLASH (0x08000000) but will be offset to 0x08003000. This offset is needed
+to make space for the DFU loader and 0x08003000 is where the DFU loader expects
+to find new applications at boot time. If you need to change that origin for some
+other bootloader, you will need to edit the file(s) ld.script.dfu for the
+configuration.
+
+The DFU SE PC-based software is available from the STMicro website,
+http://www.st.com. General usage instructions:
+
+1. Convert the NuttX Intel Hex file (nuttx.hex) into a special DFU
+ file (nuttx.dfu)... see below for details.
+
+2. Connect the M3 Wildfire board to your computer using a USB cable.
+
+3. Start the DFU loader on the M3 Wildfire board. You do this by
+ resetting the board while holding the *Key* button. Windows should
+ recognize that the DFU loader has been installed.
+
+3. Run the DFU SE program to load nuttx.dfu into FLASH.
+
+What if the DFU loader is not in FLASH? The loader code is available
+inside of the Demo directory of the USBLib ZIP file that can be downloaded
+from the STMicro Website. You can build it using RIDE (or other toolchains);
+you will need a JTAG emulator to burn it into FLASH the first time.
+
+In order to use STMicro's built-in DFU loader, you will have to get
+the NuttX binary into a special format with a .dfu extension. The
+DFU SE PC_based software installation includes a file "DFU File Manager"
+conversion program that a file in Intel Hex format to the special DFU
+format. When you successfully build NuttX, you will find a file called
+nutt.hex in the top-level directory. That is the file that you should
+provide to the DFU File Manager. You will end up with a file called
+nuttx.dfu that you can use with the STMicro DFU SE program.
+
+Enabling JTAG
+-------------
+
+If you are not using the DFU, then you will probably also need to enable
+JTAG support. By default, all JTAG support is disabled but there NuttX
+configuration options to enable JTAG in various different ways.
+
+These configurations effect the setting of the SWJ_CFG[2:0] bits in the AFIO
+MAPR register. These bits are used to configure the SWJ and trace alternate
+function I/Os. The SWJ (SerialWire JTAG) supports JTAG or SWD access to the
+Cortex debug port. The default state in this port is for all JTAG support
+to be disabled.::
+
+ CONFIG_STM32_JTAG_FULL_ENABLE - sets SWJ_CFG[2:0] to 000 which enables full
+ SWJ (JTAG-DP + SW-DP)
+
+ CONFIG_STM32_JTAG_NOJNTRST_ENABLE - sets SWJ_CFG[2:0] to 001 which enable
+ full SWJ (JTAG-DP + SW-DP) but without JNTRST.
+
+ CONFIG_STM32_JTAG_SW_ENABLE - sets SWJ_CFG[2:0] to 010 which would set JTAG-DP
+ disabled and SW-DP enabled.
+
+ The default setting (none of the above defined) is SWJ_CFG[2:0] set to 100
+ which disable JTAG-DP and SW-DP.
+
+OpenOCD
+=======
+
+I have also used OpenOCD with the M3 Wildfire. In this case, I used
+the Olimex USB ARM OCD. See the script in boards/arm/stm32/fire-stm32v2/tools/oocd.sh
+for more information. Using the script:
+
+- Start the OpenOCD GDB server::
+
+ cd <nuttx-build-directory>
+ boards/arm/stm32/fire-stm32v2/tools/oocd.sh $PWD
+
+- Load NuttX::
+
+ cd <nuttx-built-directory>
+ arm-none-eabi-gdb nuttx
+ gdb> target remote localhost:3333
+ gdb> mon reset
+ gdb> mon halt
+ gdb> load nuttx
+
+- Running NuttX::
+
+ gdb> mon reset
+ gdb> c
+
+LEDs
+====
+
+The M3 Wildfire has 3 LEDs labeled LED1, LED2 and LED3. These LEDs are not
+used by the NuttX port unless CONFIG_ARCH_LEDS is defined. In that case, the
+usage by the board port is defined in include/board.h and src/up_autoleds.c.
+The LEDs are used to encode OS-related events as follows::
+
+ /* LED1 LED2 LED3 */
+ #define LED_STARTED 0 /* OFF OFF OFF */
+ #define LED_HEAPALLOCATE 1 /* ON OFF OFF */
+ #define LED_IRQSENABLED 2 /* OFF ON OFF */
+ #define LED_STACKCREATED 3 /* OFF OFF OFF */
+
+ #define LED_INIRQ 4 /* NC NC ON (momentary) */
+ #define LED_SIGNAL 5 /* NC NC ON (momentary) */
+ #define LED_ASSERTION 6 /* NC NC ON (momentary) */
+ #define LED_PANIC 7 /* NC NC ON (2Hz flashing) */
+ #undef LED_IDLE /* Sleep mode indication not supported */
+
+RTC
+===
+
+The STM32 RTC may configured using the following settings.::
+
+ CONFIG_RTC - Enables general support for a hardware RTC. Specific
+ architectures may require other specific settings.
+ CONFIG_RTC_HIRES - The typical RTC keeps time to resolution of 1
+ second, usually supporting a 32-bit time_t value. In this case,
+ the RTC is used to "seed" the normal NuttX timer and the
+ NuttX timer provides for higher resolution time. If CONFIG_RTC_HIRES
+ is enabled in the NuttX configuration, then the RTC provides higher
+ resolution time and completely replaces the system timer for purpose of
+ date and time.
+ CONFIG_RTC_FREQUENCY - If CONFIG_RTC_HIRES is defined, then the
+ frequency of the high resolution RTC must be provided. If CONFIG_RTC_HIRES
+ is not defined, CONFIG_RTC_FREQUENCY is assumed to be one.
+ CONFIG_RTC_ALARM - Enable if the RTC hardware supports setting of an alarm.
+ A callback function will be executed when the alarm goes off.
+
+In hi-res mode, the STM32 RTC operates only at 16384Hz. Overflow interrupts
+are handled when the 32-bit RTC counter overflows every 3 days and 43 minutes.
+A BKP register is incremented on each overflow interrupt creating, effectively,
+a 48-bit RTC counter.
+
+In the lo-res mode, the RTC operates at 1Hz. Overflow interrupts are not handled
+(because the next overflow is not expected until the year 2106).
+
+WARNING: Overflow interrupts are lost whenever the STM32 is powered down. The
+overflow interrupt may be lost even if the STM32 is powered down only momentarily.
+Therefore hi-res solution is only useful in systems where the power is always on.
+
+M3 Wildfire-specific Configuration Options
+============================================
+
+..
+ CONFIG_ARCH - Identifies the arch/ subdirectory. This should be set to:
+
+ CONFIG_ARCH=arm
+
+ CONFIG_ARCH_family - For use in C code:
+
+ CONFIG_ARCH_ARM=y
+
+ CONFIG_ARCH_architecture - For use in C code:
+
+ CONFIG_ARCH_CORTEXM3=y
+
+ CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
+
+ CONFIG_ARCH_CHIP=stm32
+
+ CONFIG_ARCH_CHIP_name - For use in C code to identify the exact chip:
+
+ CONFIG_ARCH_CHIP_STM32
+ CONFIG_ARCH_CHIP_STM32F103VE
+
+ CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock
+ configuration features.
+
+ CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n
+
+ CONFIG_ARCH_BOARD - Identifies the boards/ subdirectory and
+ hence, the board that supports the particular chip or SoC.
+
+ CONFIG_ARCH_BOARD=fire-stm32v2 (for the M3 Wildfire development board)
+
+ CONFIG_ARCH_BOARD_name - For use in C code
+
+ CONFIG_ARCH_BOARD_FIRE_STM32V2=y (Version 2)
+ CONFIG_ARCH_BOARD_FIRE_STM32V3=y (Version 3)
+
+ CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operationof delay loops
+
+ CONFIG_ENDIAN_BIG - define if big endian (default is little endian)
+
+ CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case):
+
+ CONFIG_RAM_SIZE=0x00010000 (64Kb)
+
+ CONFIG_RAM_START - The start address of installed DRAM
+
+ CONFIG_RAM_START=0x20000000
+
+ CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that have LEDs
+
+ CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
+ stack. If defined, this symbol is the size of the interrupt
+ stack in bytes. If not defined, the user task stacks will be
+ used during interrupt handling.
+
+ CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
+
+ CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture.
+
+ Individual subsystems can be enabled:
+
+ AHB
+ ---
+ CONFIG_STM32_DMA1
+ CONFIG_STM32_DMA2
+ CONFIG_STM32_CRC
+ CONFIG_STM32_FSMC
+ CONFIG_STM32_SDIO
+
+ APB1
+ ----
+ CONFIG_STM32_TIM2
+ CONFIG_STM32_TIM3
+ CONFIG_STM32_TIM4
+ CONFIG_STM32_TIM5
+ CONFIG_STM32_TIM6
+ CONFIG_STM32_TIM7
+ CONFIG_STM32_WWDG
+ CONFIG_STM32_IWDG
+ CONFIG_STM32_SPI2
+ CONFIG_STM32_SPI4
+ CONFIG_STM32_USART2
+ CONFIG_STM32_USART3
+ CONFIG_STM32_UART4
+ CONFIG_STM32_UART5
+ CONFIG_STM32_I2C1
+ CONFIG_STM32_I2C2
+ CONFIG_STM32_USB
+ CONFIG_STM32_CAN1
+ CONFIG_STM32_BKP
+ CONFIG_STM32_PWR
+ CONFIG_STM32_DAC1
+ CONFIG_STM32_DAC2
+ CONFIG_STM32_USB
+
+ APB2
+ ----
+ CONFIG_STM32_ADC1
+ CONFIG_STM32_ADC2
+ CONFIG_STM32_TIM1
+ CONFIG_STM32_SPI1
+ CONFIG_STM32_TIM8
+ CONFIG_STM32_USART1
+ CONFIG_STM32_ADC3
+
+ Timer and I2C devices may need to the following to force power to be applied
+ unconditionally at power up. (Otherwise, the device is powered when it is
+ initialized).
+
+ CONFIG_STM32_FORCEPOWER
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If CONFIG_STM32_TIMn
+ is defined (as above) then the following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation, ADC conversion,
+ or DAC conversion. Note that ADC/DAC require two definition: Not only do you have
+ to assign the timer (n) for used by the ADC or DAC, but then you also have to
+ configure which ADC or DAC (m) it is assigned to.
+
+ CONFIG_STM32_TIMn_PWM Reserve timer n for use by PWM, n=1,..,8
+ CONFIG_STM32_TIMn_ADC Reserve timer n for use by ADC, n=1,..,8
+ CONFIG_STM32_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,8, m=1,..,3
+ CONFIG_STM32_TIMn_DAC Reserve timer n for use by DAC, n=1,..,8
+ CONFIG_STM32_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,8, m=1,..,2
+
+ For each timer that is enabled for PWM usage, we need the following additional
+ configuration settings:
+
+ CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
+
+ NOTE: The STM32 timers are each capable of generating different signals on
+ each of the four channels with different duty cycles. That capability is
+ not supported by this driver: Only one output channel per timer.
+
+ Alternate pin mappings. The M3 Wildfire board requires only CAN1 remapping
+ On the M3 Wildfire board pin PB9 is wired as TX and pin PB8 is wired as RX.
+ Which then makes the proper connection through the CAN transceiver SN65HVD230
+ out to the CAN D-type 9-pn male connector where pin 2 is CANL and pin 7 is CANH.
+
+ CONFIG_STM32_TIM1_FULL_REMAP
+ CONFIG_STM32_TIM1_PARTIAL_REMAP
+ CONFIG_STM32_TIM2_FULL_REMAP
+ CONFIG_STM32_TIM2_PARTIAL_REMAP_1
+ CONFIG_STM32_TIM2_PARTIAL_REMAP_2
+ CONFIG_STM32_TIM3_FULL_REMAP
+ CONFIG_STM32_TIM3_PARTIAL_REMAP
+ CONFIG_STM32_TIM4_REMAP
+ CONFIG_STM32_USART1_REMAP
+ CONFIG_STM32_USART2_REMAP
+ CONFIG_STM32_USART3_FULL_REMAP
+ CONFIG_STM32_USART3_PARTIAL_REMAP
+ CONFIG_STM32_SPI1_REMAP
+ CONFIG_STM32_SPI3_REMAP
+ CONFIG_STM32_I2C1_REMAP
+ CONFIG_STM32_CAN1_REMAP1
+ CONFIG_STM32_CAN1_REMAP2
+ CONFIG_STM32_CAN2_REMAP
+
+ JTAG Enable settings (by default JTAG-DP and SW-DP are disabled):
+ CONFIG_STM32_JTAG_FULL_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
+ CONFIG_STM32_JTAG_NOJNTRST_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
+ but without JNTRST.
+ CONFIG_STM32_JTAG_SW_ENABLE - Set JTAG-DP disabled and SW-DP enabled
+
+ STM32F103Z specific device driver settings
+
+ CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=1,2,3) or UART
+ m (m=4,5) for the console and ttys0 (default is the USART1).
+ CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received.
+ This specific the size of the receive buffer
+ CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before
+ being sent. This specific the size of the transmit buffer
+ CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be
+ CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8.
+ CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
+ CONFIG_U[S]ARTn_2STOP - Two stop bits
+
+ CONFIG_STM32_SPI_INTERRUPTS - Select to enable interrupt driven SPI
+ support. Non-interrupt-driven, poll-waiting is recommended if the
+ interrupt rate would be to high in the interrupt driven case.
+ CONFIG_STM32_SPIx_DMA - Use DMA to improve SPIx transfer performance.
+ Cannot be used with CONFIG_STM32_SPI_INTERRUPT.
+
+ CONFIG_STM32_SDIO_DMA - Support DMA data transfers. Requires
+ CONFIG_STM32_SDIO and CONFIG_STM32_DMA2.
+ CONFIG_STM32_SDIO_PRI - Select SDIO interrupt priority. Default: 128
+ CONFIG_STM32_SDIO_DMAPRIO - Select SDIO DMA interrupt priority.
+ Default: Medium
+ CONFIG_STM32_SDIO_WIDTH_D1_ONLY - Select 1-bit transfer mode. Default:
+ 4-bit transfer mode.
+
+ M3 Wildfire CAN Configuration
+
+ CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32_CAN1 or
+ CONFIG_STM32_CAN2 must also be defined)
+ CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. Default
+ Standard 11-bit IDs.
+ CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages.
+ Default: 8
+ CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests.
+ Default: 4
+ CONFIG_CAN_LOOPBACK - A CAN driver may or may not support a loopback
+ mode for testing. The STM32 CAN driver does support loopback mode.
+ CONFIG_STM32_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN1
+ is defined.
+ CONFIG_STM32_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN2
+ is defined.
+ CONFIG_STM32_CAN_TSEG1 - The number of CAN time quanta in segment 1.
+ Default: 6
+ CONFIG_STM32_CAN_TSEG2 - the number of CAN time quanta in segment 2.
+ Default: 7
+ CONFIG_STM32_CAN_REGDEBUG - If CONFIG_DEBUG_FEATURES is set, this will generate an
+ dump of all CAN registers.
+
+ M3 Wildfire LCD Hardware Configuration
+
+ CONFIG_LCD_LANDSCAPE - Define for 320x240 display "landscape"
+ support. Default is this 320x240 "landscape" orientation
+ (this setting is informative only... not used).
+ CONFIG_LCD_PORTRAIT - Define for 240x320 display "portrait"
+ orientation support. In this orientation, the M3 Wildfire's
+ LCD ribbon cable is at the bottom of the display. Default is
+ 320x240 "landscape" orientation.
+ CONFIG_LCD_RPORTRAIT - Define for 240x320 display "reverse
+ portrait" orientation support. In this orientation, the
+ M3 Wildfire's LCD ribbon cable is at the top of the display.
+ Default is 320x240 "landscape" orientation.
+ CONFIG_LCD_BACKLIGHT - Define to support a backlight.
+ CONFIG_LCD_PWM - If CONFIG_STM32_TIM1 is also defined, then an
+ adjustable backlight will be provided using timer 1 to generate
+ various pulse widthes. The granularity of the settings is
+ determined by CONFIG_LCD_MAXPOWER. If CONFIG_LCD_PWM (or
+ CONFIG_STM32_TIM1) is not defined, then a simple on/off backlight
+ is provided.
+ CONFIG_LCD_RDSHIFT - When reading 16-bit gram data, there appears
+ to be a shift in the returned data. This value fixes the offset.
+ Default 5.
+
+ The LCD driver dynamically selects the LCD based on the reported LCD
+ ID value. However, code size can be reduced by suppressing support for
+ individual LCDs using:
+
+ CONFIG_STM32_AM240320_DISABLE
+ CONFIG_STM32_SPFD5408B_DISABLE
+
+Configurations
+==============
+
+Each M3 Wildfire configuration is maintained in a sub-directory and
+can be selected as follow::
+
+ tools/configure.sh fire-stm32v2:<subdir>
+
+Where <subdir> is one of the following:
+
+nsh
+---
+
+Configure the NuttShell (nsh) located at examples/nsh. The nsh configuration
+contains support for some built-in applications that can be enabled by making
+some additional minor change to the configuration file.
+
+Reconfiguring: This configuration uses to the kconfig-mconf configuration tool
+to control the configuration. See the section entitled "NuttX Configuration
+Tool" in the top-level README.txt file.
+
+Start Delays: If no SD card is present in the slot, or if the network is not
+connected, then there will be long start-up delays before you get the NSH
+prompt. If I am focused on ENC28J60 debug, I usually disable MMC/SD so that
+I don't have to bother with the SD card::
+
+ CONFIG_STM32_SDIO=n
+ CONFIG_MMCSD=n
+
+STATUS: The board port is basically functional. Not all features have been
+verified. The ENC28J60 network is not yet functional. Networking is
+enabled by default in this configuration for testing purposes. To use this
+configuration, the network must currently be disabled. To do this using
+the kconfig-mconf configuration tool::
+
+ > make menuconfig
+
+Then de-select "Networking Support" -> "Networking Support"
+
+PDATE: The primary problem with the ENC29J60 is a v2 board issue: The
+SPI FLASH and the ENC28J60 shared the same SPI chip select signal (PA4-SPI1-NSS).
+In order to finish the debug of the ENC28J60, it may be necessary to lift
+the SPI FLASH chip select pin from the board.
diff --git a/content/docs/latest/_sources/platforms/arm/stm32f1/boards/hymini-stm32/index.rst.txt b/content/docs/latest/_sources/platforms/arm/stm32f1/boards/hymini-stm32/index.rst.txt
new file mode 100644
index 00000000..3ddafec4
--- /dev/null
+++ b/content/docs/latest/_sources/platforms/arm/stm32f1/boards/hymini-stm32/index.rst.txt
@@ -0,0 +1,514 @@
+=============
+HY-MiniSTM32V
+=============
+
+This README discusses issues unique to NuttX configurations for the
+HY-MiniSTM32V development board.
+
+ST Bootloader
+=============
+
+A bootloader code is available in an internal boot ROM memory (called
+'system memory' in STM documentation) in all STM32 MCUs. For the F103xx
+this bootloader can be used to upload & flash a firmware image through
+the USART1.
+
+Notes:
+
+- The bootloader is activated by the BOOT0 / BOOT1 pins after a MCU reset.
+ See STM application note 2606 for more details.
+- On the hymini-stm32 board the USART1 is connected to a PL2303
+ USB<->serial converter.
+
+To enter bootloader mode in the hymini-stm32 board:
+
+- Press the 'boot0' button (located next to 'reset' button)
+- While boot0 button is pressed, reset the board through the reset button.
+- Once you pressed / released the 'reset' button, the MCU has (re)started
+ in bootloader mode (and you can then release the boot0 button).
+
+A flash utility must be used on your development workstation to upload / flash
+a firmware image. (The 'stm32flash' open source tool, available at
+http://stm32flash.googlecode.com/ has been used successfully).
+
+LEDs
+====
+
+The HY-MiniSTM32 board provides only two controllable LEDs labeled LED1 and LED2.
+Usage of these LEDs is defined in include/board.h and src/up_leds.c.
+They are encoded as follows::
+
+ =================== ======================= ======= =======
+ SYMBOL Meaning LED1* LED2
+ =================== ======================= ======= =======
+ LED_STARTED NuttX has been started OFF OFF
+ LED_HEAPALLOCATE Heap has been allocated ON OFF
+ LED_IRQSENABLED Interrupts enabled OFF ON
+ LED_STACKCREATED Idle stack created ON OFF
+ LED_INIRQ In an interrupt** OFF N/C
+ LED_SIGNAL In a signal handler*** N/C ON
+ LED_ASSERTION An assertion failed ON ON
+ LED_PANIC The system has crashed BLINK BLINK
+ LED_IDLE STM32 is is sleep mode (Optional, not used)
+ =================== ======================= ======= =======
+
+ * If NuttX starts correctly, normal state is to have LED1 on and LED2 off.
+ ** LED1 is turned off during interrupt.
+ *** LED2 is turned on during signal handler.
+
+RTC
+===
+
+The STM32 RTC may configured using the following settings.::
+
+ CONFIG_RTC - Enables general support for a hardware RTC. Specific
+ architectures may require other specific settings.
+ CONFIG_RTC_HIRES - The typical RTC keeps time to resolution of 1
+ second, usually supporting a 32-bit time_t value. In this case,
+ the RTC is used to "seed" the normal NuttX timer and the
+ NuttX timer provides for higher resolution time. If CONFIG_RTC_HIRES
+ is enabled in the NuttX configuration, then the RTC provides higher
+ resolution time and completely replaces the system timer for purpose of
+ date and time.
+ CONFIG_RTC_FREQUENCY - If CONFIG_RTC_HIRES is defined, then the
+ frequency of the high resolution RTC must be provided. If CONFIG_RTC_HIRES
+ is not defined, CONFIG_RTC_FREQUENCY is assumed to be one.
+ CONFIG_RTC_ALARM - Enable if the RTC hardware supports setting of an alarm.
+ A callback function will be executed when the alarm goes off
+
+In hi-res mode, the STM32 RTC operates only at 16384Hz. Overflow interrupts
+are handled when the 32-bit RTC counter overflows every 3 days and 43 minutes.
+A BKP register is incremented on each overflow interrupt creating, effectively,
+a 48-bit RTC counter.
+
+In the lo-res mode, the RTC operates at 1Hz. Overflow interrupts are not handled
+(because the next overflow is not expected until the year 2106.
+
+WARNING: Overflow interrupts are lost whenever the STM32 is powered down. The
+overflow interrupt may be lost even if the STM32 is powered down only momentarily.
+Therefore hi-res solution is only useful in systems where the power is always on.
+
+HY-Mini specific Configuration Options
+======================================
+
+::
+
+ CONFIG_ARCH - Identifies the arch/ subdirectory. This should be set to:
+
+ CONFIG_ARCH=arm
+
+ CONFIG_ARCH_family - For use in C code:
+
+ CONFIG_ARCH_ARM=y
+
+ CONFIG_ARCH_architecture - For use in C code:
+
+ CONFIG_ARCH_CORTEXM3=y
+
+ CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
+
+ CONFIG_ARCH_CHIP=stm32
+
+ CONFIG_ARCH_CHIP_name - For use in C code to identify the exact chip:
+
+ CONFIG_ARCH_CHIP_STM32F103VC
+
+ CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock
+ configuration features.
+
+ CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n
+
+ CONFIG_ARCH_BOARD - Identifies the boards/ subdirectory and
+ hence, the board that supports the particular chip or SoC.
+
+ CONFIG_ARCH_BOARD=hymini-stm32v (for the HY-Mini development board)
+
+ CONFIG_ARCH_BOARD_name - For use in C code
+
+ CONFIG_ARCH_BOARD_HYMINI_STM32V=y
+
+ CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
+ of delay loops
+
+ CONFIG_ENDIAN_BIG - define if big endian (default is little
+ endian)
+
+ CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case):
+
+ CONFIG_RAM_SIZE=0x0000C000 (48Kb)
+
+ CONFIG_RAM_START - The start address of installed DRAM
+
+ CONFIG_RAM_START=0x20000000
+
+ CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that
+ have LEDs
+
+ CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
+ stack. If defined, this symbol is the size of the interrupt
+ stack in bytes. If not defined, the user task stacks will be
+ used during interrupt handling.
+
+ CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
+
+ CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture.
+
+ Individual subsystems can be enabled:
+ AHB
+ ---
+ CONFIG_STM32_DMA1
+ CONFIG_STM32_DMA2
+ CONFIG_STM32_CRC
+ CONFIG_STM32_FSMC
+ CONFIG_STM32_SDIO
+
+ APB1
+ ----
+ CONFIG_STM32_TIM2
+ CONFIG_STM32_TIM3 (required for PWM control of LCD backlight)
+ CONFIG_STM32_TIM4
+ CONFIG_STM32_TIM5
+ CONFIG_STM32_TIM6
+ CONFIG_STM32_TIM7
+ CONFIG_STM32_IWDG
+ CONFIG_STM32_WWDG
+ CONFIG_STM32_IWDG
+ CONFIG_STM32_SPI2
+ CONFIG_STM32_SPI4
+ CONFIG_STM32_USART2
+ CONFIG_STM32_USART3
+ CONFIG_STM32_UART4
+ CONFIG_STM32_UART5
+ CONFIG_STM32_I2C1
+ CONFIG_STM32_I2C2
+ CONFIG_STM32_USB
+ CONFIG_STM32_CAN1
+ CONFIG_STM32_BKP
+ CONFIG_STM32_PWR
+ CONFIG_STM32_DAC
+ CONFIG_STM32_USB
+
+ APB2
+ ----
+ CONFIG_STM32_ADC1
+ CONFIG_STM32_ADC2
+ CONFIG_STM32_TIM1
+ CONFIG_STM32_SPI1
+ CONFIG_STM32_TIM8
+ CONFIG_STM32_USART1
+ CONFIG_STM32_ADC3
+
+ Timer and I2C devices may need to the following to force power to be applied
+ unconditionally at power up. (Otherwise, the device is powered when it is
+ initialized).
+
+ CONFIG_STM32_FORCEPOWER
+
+ The Timer3 alternate mapping is required for PWM control of LCD backlight
+
+ CONFIG_STM32_TIM3_PARTIAL_REMAP=y
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If CONFIG_STM32_TIMn
+ is defined (as above) then the following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation, ADC conversion,
+ or DAC conversion. Note that ADC/DAC require two definition: Not only do you have
+ to assign the timer (n) for used by the ADC or DAC, but then you also have to
+ configure which ADC or DAC (m) it is assigned to.
+
+ CONFIG_STM32_TIMn_PWM Reserve timer n for use by PWM, n=1,..,8
+ CONFIG_STM32_TIMn_ADC Reserve timer n for use by ADC, n=1,..,8
+ CONFIG_STM32_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,8, m=1,..,3
+ CONFIG_STM32_TIMn_DAC Reserve timer n for use by DAC, n=1,..,8
+ CONFIG_STM32_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,8, m=1,..,2
+
+ Others alternate pin mappings available:
+
+ CONFIG_STM32_TIM1_FULL_REMAP
+ CONFIG_STM32_TIM1_PARTIAL_REMAP
+ CONFIG_STM32_TIM2_FULL_REMAP
+ CONFIG_STM32_TIM2_PARTIAL_REMAP_1
+ CONFIG_STM32_TIM2_PARTIAL_REMAP_2
+ CONFIG_STM32_TIM3_FULL_REMAP
+ CONFIG_STM32_TIM3_PARTIAL_REMAP
+ CONFIG_STM32_TIM4_REMAP
+ CONFIG_STM32_USART1_REMAP
+ CONFIG_STM32_USART2_REMAP
+ CONFIG_STM32_USART3_FULL_REMAP
+ CONFIG_STM32_USART3_PARTIAL_REMAP
+ CONFIG_STM32_SPI1_REMAP
+ CONFIG_STM32_SPI3_REMAP
+ CONFIG_STM32_I2C1_REMAP
+ CONFIG_STM32_CAN1_REMAP1
+ CONFIG_STM32_CAN1_REMAP2
+ CONFIG_STM32_CAN2_REMAP
+
+ STM32F103V specific device driver settings
+
+ CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=1,2,3) or UART
+ m (m=4,5) for the console and ttys0 (default is the USART1).
+
+ Note: USART1 is connected to a PL2303 serial to USB converter.
+ So USART1 is available through USB port labeled CN3 on the board.
+
+ CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received.
+ This specific the size of the receive buffer
+ CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before
+ being sent. This specific the size of the transmit buffer
+ CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be
+ CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8.
+ CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
+ CONFIG_U[S]ARTn_2STOP - Two stop bits
+
+ CONFIG_STM32_SPI_INTERRUPTS - Select to enable interrupt driven SPI
+ support. Non-interrupt-driven, poll-waiting is recommended if the
+ interrupt rate would be to high in the interrupt driven case.
+ CONFIG_STM32_SPIx_DMA - Use DMA to improve SPIx transfer performance.
+ Cannot be used with CONFIG_STM32_SPI_INTERRUPT.
+
+ CONFIG_SDIO_DMA - Support DMA data transfers. Requires CONFIG_STM32_SDIO
+ and CONFIG_STM32_DMA2.
+ CONFIG_STM32_SDIO_PRI - Select SDIO interrupt priority. Default: 128
+ CONFIG_STM32_SDIO_DMAPRIO - Select SDIO DMA interrupt priority.
+ Default: Medium
+ CONFIG_STM32_SDIO_WIDTH_D1_ONLY - Select 1-bit transfer mode. Default:
+ 4-bit transfer mode.
+ CONFIG_MMCSD_HAVE_CARDDETECT - Select if SDIO driver card detection
+ is 100% accurate (it is on the HY-MiniSTM32V)
+
+ HY-MiniSTM32V CAN Configuration
+
+ CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32_CAN1 or
+ CONFIG_STM32_CAN2 must also be defined)
+ CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. Default
+ Standard 11-bit IDs.
+ CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages.
+ Default: 8
+ CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests.
+ Default: 4
+ CONFIG_CAN_LOOPBACK - A CAN driver may or may not support a loopback
+ mode for testing. The STM32 CAN driver does support loopback mode.
+ CONFIG_STM32_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN1
+ is defined.
+ CONFIG_STM32_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN2
+ is defined.
+ CONFIG_STM32_CAN_TSEG1 - The number of CAN time quanta in segment 1.
+ Default: 6
+ CONFIG_STM32_CAN_TSEG2 - the number of CAN time quanta in segment 2.
+ Default: 7
+ CONFIG_STM32_CAN_REGDEBUG - If CONFIG_DEBUG_FEATURES is set, this will generate an
+ dump of all CAN registers.
+
+ HY-MiniSTM32V LCD Hardware Configuration. The HY-Mini board may be delivered with
+ either an SSD1289 or an R61505U LCD controller.
+
+ CONFIG_LCD_R61505U - Selects the R61505U LCD controller.
+ CONFIG_LCD_SSD1289 - Selects the SSD1289 LCD controller.
+
+ The following options apply for either LCD controller:
+
+ CONFIG_NX_LCDDRIVER - To be defined to include LCD driver
+ CONFIG_LCD_LANDSCAPE - Define for 320x240 display "landscape"
+ support. In this orientation, the HY-MiniSTM32V's
+ LCD used connector is at the right of the display.
+ Default is this 320x240 "landscape" orientation
+ CONFIG_LCD_PORTRAIT - Define for 240x320 display "portrait"
+ orientation support. In this orientation, the HY-MiniSTM32V's
+ LCD used connector is at the bottom of the display. Default is
+ 320x240 "landscape" orientation.
+ CONFIG_LCD_RPORTRAIT - Define for 240x320 display "reverse
+ portrait" orientation support. In this orientation, the
+ HY-MiniSTM32V's LCD used connector is at the top of the display.
+ Default is 320x240 "landscape" orientation.
+ CONFIG_LCD_BACKLIGHT - Define to support an adjustable backlight
+ using timer 3. The granularity of the settings is determined
+ by CONFIG_LCD_MAXPOWER. Requires CONFIG_STM32_TIM3.
+
+Configurations
+==============
+
+NOTES:
+
+- All configurations described below are using the mconf-based
+ configuration tool. To change their configuration using that tool, you
+ should:
+
+ a. Build and install the kconfig-mconf tool. See nuttx/README.txt
+ see additional README.txt files in the NuttX tools repository.
+
+ b. Execute 'make menuconfig' in nuttx/ in order to start the
+ reconfiguration process.
+
+- All configurations use a generic GNU EABI toolchain for Linux by
+ default.
+
+- They are all configured to generate a binary image that can be flashed
+ through the STM32 internal bootloader.
+
+Each HY-MiniSTM32V configuration is maintained in a sub-directory and
+can be selected as follow::
+
+ tools/configure.sh hymini-stm32v:<subdir>
+
+Where <subdir> is one of the following:
+
+nsh and nsh2
+------------
+
+Configure the NuttShell (nsh) located at examples/nsh.
+
+Differences between the two NSH configurations::
+
+ =========== ======================= ================================
+ nsh nsh2
+ =========== ======================= ================================
+ Serial Debug output: USART1 Debug output: USART1
+ Console: NSH output: USART1 NSH output: USART1 (2)
+ =========== ======================= ================================
+ microSD Yes (5) Yes (5)
+ Support
+ =========== ======================= ================================
+ FAT FS CONFIG_FAT_LCNAMES=y CONFIG_FAT_LCNAMES=y
+ Config CONFIG_FAT_LFN=n CONFIG_FAT_LFN=y (3)
+ =========== ======================= ================================
+ LCD Driver No Yes
+ Support
+ =========== ======================= ================================
+ RTC Support No Yes
+ =========== ======================= ================================
+ Support for No Yes
+ Built=in
+ Apps
+ =========== ======================= ================================
+ Built=in None apps/examples/nx
+ Apps apps/examples/nxhello
+ apps/system/usbmsc (4)
+ apps/examples/nximage
+ =========== ======================= ================================
+
+ (1) You will probably need to the PATH environment variable to set
+ up the correct PATH variable for whichever toolchain you may use.
+ (2) When any other device other than /dev/console is used for a user
+ interface, (1) linefeeds (\n) will not be expanded to carriage return
+ / linefeeds \r\n). You will need to configure your terminal program
+ to account for this. And (2) input is not automatically echoed so
+ you will have to turn local echo on.
+ (3) Microsoft holds several patents related to the design of
+ long file names in the FAT file system. Please refer to the
+ details in the top-level NOTICE file. Please do not use FAT
+ long file name unless you are familiar with these patent issues.
+ (4) When built as an NSH add-on command (CONFIG_NSH_BUILTIN_APPS=y),
+ Caution should be used to assure that the SD drive is not in use when
+ the USB storage device is configured. Specifically, the SD driver
+ should be unmounted like::
+
+ nsh> mount -t vfat /dev/mmcsd0 /mnt/sdcard # Card is mounted in NSH
+ ...
+ nsh> umount /mnd/sdcard # Unmount before connecting USB!!!
+ nsh> msconn # Connect the USB storage device
+ ...
+ nsh> msdis # Disconnect USB storate device
+ nsh> mount -t vfat /dev/mmcsd0 /mnt/sdcard # Restore the mount
+
+ Failure to do this could result in corruption of the SD card format.
+ (5) Option CONFIG_NSH_ARCHINIT must be enabled in order to call the SDIO slot
+ initialization code.
+
+usbmsc
+------
+
+This configuration directory exercises the USB mass storage
+class driver at system/usbmsc. See examples/README.txt for
+more information.
+
+usbnsh
+------
+
+This is another NSH example. If differs from other 'nsh' configurations
+in that this configurations uses a USB serial device for console I/O.
+
+NOTES:
+
+1. This configuration does have UART2 output enabled and set up as
+ the system logging device::
+
+ CONFIG_SYSLOG_CHAR=y : Use a character device for system logging
+ CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" : UART2 will be /dev/ttyS0
+
+ However, there is nothing to generate SYSLOG output in the default
+ configuration so nothing should appear on UART2 unless you enable
+ some debug output or enable the USB monitor.
+
+2. Enabling USB monitor SYSLOG output. If tracing is enabled, the USB
+ device will save encoded trace output in in-memory buffer; if the
+ USB monitor is enabled, that trace buffer will be periodically
+ emptied and dumped to the system logging device (UART2 in this
+ configuration)::
+
+ CONFIG_USBDEV_TRACE=y : Enable USB trace feature
+ CONFIG_USBDEV_TRACE_NRECORDS=128 : Buffer 128 records in memory
+ CONFIG_NSH_USBDEV_TRACE=n : No builtin tracing from NSH
+ CONFIG_NSH_ARCHINIT=y : Automatically start the USB monitor
+ CONFIG_USBMONITOR=y : Enable the USB monitor daemon
+ CONFIG_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size
+ CONFIG_USBMONITOR_PRIORITY=50 : USB monitor daemon priority
+ CONFIG_USBMONITOR_INTERVAL=2 : Dump trace data every 2 seconds
+
+ CONFIG_USBMONITOR_TRACEINIT=y : Enable TRACE output
+ CONFIG_USBMONITOR_TRACECLASS=y
+ CONFIG_USBMONITOR_TRACETRANSFERS=y
+ CONFIG_USBMONITOR_TRACECONTROLLER=y
+ CONFIG_USBMONITOR_TRACEINTERRUPTS=y
+
+ Using the Prolifics PL2303 Emulation
+ ------------------------------------
+ You could also use the non-standard PL2303 serial device instead of
+ the standard CDC/ACM serial device by changing::
+
+ CONFIG_CDCACM=y : Disable the CDC/ACM serial device class
+ CONFIG_CDCACM_CONSOLE=y : The CDC/ACM serial device is NOT the console
+ CONFIG_PL2303=y : The Prolifics PL2303 emulation is enabled
+ CONFIG_PL2303_CONSOLE=y : The PL2303 serial device is the console
+
+usbserial
+---------
+
+This configuration directory exercises the USB serial class
+driver at examples/usbserial. See examples/README.txt for
+more information.::
+
+ CONFIG_HOST_LINUX=y : Linux host
+ CONFIG_ARM_TOOLCHAIN_GNU_EABI=y : GNU EABI toolchain for Linux
+
+USB debug output can be enabled as by changing the following
+settings in the configuration file::
+
+ -CONFIG_DEBUG_FEATURES=n
+ -CONFIG_DEBUG_INFO=n
+ -CONFIG_DEBUG_USB=n
+ +CONFIG_DEBUG_FEATURES=y
+ +CONFIG_DEBUG_INFO=y
+ +CONFIG_DEBUG_USB=y
+
+ -CONFIG_EXAMPLES_USBSERIAL_TRACEINIT=n
+ -CONFIG_EXAMPLES_USBSERIAL_TRACECLASS=n
+ -CONFIG_EXAMPLES_USBSERIAL_TRACETRANSFERS=n
+ -CONFIG_EXAMPLES_USBSERIAL_TRACECONTROLLER=n
+ -CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n
+ +CONFIG_EXAMPLES_USBSERIAL_TRACEINIT=y
+ +CONFIG_EXAMPLES_USBSERIAL_TRACECLASS=y
+ +CONFIG_EXAMPLES_USBSERIAL_TRACETRANSFERS=y
+ +CONFIG_EXAMPLES_USBSERIAL_TRACECONTROLLER=y
+ +CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=y
+
+By default, the usbserial example uses the Prolific PL2303
+serial/USB converter emulation. The example can be modified
+serial/USB converter emulation. The example can be modified
+to use the CDC/ACM serial class by making the following changes
+to the configuration file::
+
+ -CONFIG_PL2303=y
+ +CONFIG_PL2303=n
+
+ -CONFIG_CDCACM=n
+ +CONFIG_CDCACM=y
diff --git a/content/docs/latest/_sources/platforms/arm/stm32f1/boards/maple/index.rst.txt b/content/docs/latest/_sources/platforms/arm/stm32f1/boards/maple/index.rst.txt
new file mode 100644
index 00000000..a06d9c29
--- /dev/null
+++ b/content/docs/latest/_sources/platforms/arm/stm32f1/boards/maple/index.rst.txt
@@ -0,0 +1,214 @@
+=====
+maple
+=====
+
+This README discusses issues unique to NuttX configurations for the
+maple board from LeafLabs (http://leaflabs.com).
+
+Microprocessor: 32-bit ARM Cortex M3 at 72MHz STM32F103RBT6 (STM32F103CBT6 for mini version)
+Memory: 120 KB Flash and 20 KB SRAM
+I/O Pins Out: 43 (34 for mini version)
+ADCs: 9 (at 12-bit resolution)
+Peripherals: 4 timers, 2 I2Cs, 2 SPI ports, 3 USARTs
+Other: Sleep, stop, and standby modes; serial wire debug and JTAG interfaces
+
+Please see below link for a list of maple devices and documentations.
+
+ http://leaflabs.com/devices
+ http://leaflabs.com/docs
+
+This config supports Maple and Maple Mini.
+
+Development Environment
+=======================
+
+Either Linux (recommended), Mac or Cygwin on Windows can be used for the development
+environment. The source has been built only using the GNU toolchain (see below).
+Other toolchains will likely cause problems.
+
+DFU
+===
+
+The linker files in these projects can be configured to indicate that you
+will be loading code using STMicro built-in USB Device Firmware Upgrade (DFU)
+loader or via some JTAG emulator. You can specify the DFU bootloader by
+adding the following line::
+
+ CONFIG_STM32_DFU=y
+
+to your .config file. Most of the configurations in this directory are set
+up to use the DFU loader.
+
+If CONFIG_STM32_DFU is defined, the code will not be positioned at the beginning
+of FLASH (0x08000000) but will be offset to 0x08005000. This offset is needed
+to make space for the DFU loader and 0x08005000 is where the DFU loader expects
+to find new applications at boot time. If you need to change that origin for some
+other bootloader, you will need to edit the file(s) ld.script.dfu for each
+configuration. In LeafLabs case, we are using maple bootloader:
+
+ http://leaflabs.com/docs/bootloader.html
+
+For Linux or Mac
+-----------------
+
+While on Linux or Mac, we can use dfu-util to upload nuttx binary.
+
+1. Make sure we have installed dfu-util. (From yum, apt-get or build from source.)
+2. Start the DFU loader (bootloader) on the maple board. You do this by
+ resetting the board while holding the "Key" button. Windows should
+ recognize that the DFU loader has been installed.
+3. Flash the nuttx.bin to the board use dfu-util. Here's an example::
+
+ $ dfu-util -a1 -d 1eaf:0003 -D nuttx.bin -R
+
+For anything not clear, we can refer to LeafLabs official document:
+
+ http://leaflabs.com/docs/unix-toolchain.html
+
+For Windows
+------------
+
+The DFU SE PC-based software is available from the STMicro website,
+http://www.st.com. General usage instructions:
+
+1. Connect the maple board to your computer using a USB
+ cable.
+2. Start the DFU loader on the maple board. You do this by
+ resetting the board while holding the "Key" button. Windows should
+ recognize that the DFU loader has been installed.
+3. Run the DFU SE program to load nuttx.bin into FLASH.
+
+What if the DFU loader is not in FLASH? The loader code is available
+inside of the Demo directory of the USBLib ZIP file that can be downloaded
+from the STMicro Website. You can build it using RIDE (or other toolchains);
+you will need a JTAG emulator to burn it into FLASH the first time.
+
+In order to use STMicro's built-in DFU loader, you will have to get
+the NuttX binary into a special format with a .dfu extension. The
+DFU SE PC_based software installation includes a file "DFU File Manager"
+conversion program that a file in Intel Hex format to the special DFU
+format. When you successfully build NuttX, you will find a file called
+nutt.hex in the top-level directory. That is the file that you should
+provide to the DFU File Manager. You will end up with a file called
+nuttx.dfu that you can use with the STMicro DFU SE program.
+
+Configurations
+==============
+
+Information Common to All Configurations
+----------------------------------------
+
+Each Maple configuration is maintained in a sub-directory and
+can be selected as follow::
+
+ tools/configure.sh maple:<subdir>
+
+Before building, make sure the PATH environment variable includes the
+correct path to the directory than holds your toolchain binaries.
+
+And then build NuttX by simply typing the following. At the conclusion of
+the make, the nuttx binary will reside in an ELF file called, simply, nuttx.::
+
+ make
+
+The <subdir> that is provided above as an argument to the tools/configure.sh
+must be is one of the following.
+
+NOTES:
+
+1. These configurations use the mconf-based configuration tool. To
+ change any of these configurations using that tool, you should:
+
+ a. Build and install the kconfig-mconf tool. See nuttx/README.txt
+ see additional README.txt files in the NuttX tools repository.
+
+ b. Execute 'make menuconfig' in nuttx/ in order to start the
+ reconfiguration process.
+
+Configuration Sub-directories
+-----------------------------
+
+nsh
+---
+
+This configuration directory provide the basic NuttShell (NSH).
+A serial console is provided on USART1.
+
+NOTES:
+
+1. Currently configured for the STM32F103CB. But this is easily reconfigured::
+
+ CONFIG_ARCH_CHIP_STM32F103RB=n
+ CONFIG_ARCH_CHIP_STM32F103CB=y
+
+2. Support for the I2C tool has been disabled, but can be restored
+ with following configure options::
+
+ System Type -> Peripherals
+ CONFIG_STM32_I2C1=y
+ CONFIG_STM32_I2C2=y
+ CONFIG_STM32_I2CTIMEOSEC=1
+ CONFIG_STM32_I2CTIMEOMS=500
+ CONFIG_STM32_I2CTIMEOTICKS=500
+
+ Drivers
+ CONFIG_I2C=y
+
+ Applications -> System Add-Ons
+ CONFIG_SYSTEM_I2CTOOL=y
+ CONFIG_I2CTOOL_MINBUS=1
+ CONFIG_I2CTOOL_MAXBUS=2
+ CONFIG_I2CTOOL_MINADDR=0x0
+ CONFIG_I2CTOOL_MAXADDR=0xf0
+ CONFIG_I2CTOOL_MAXREGADDR=0xff
+ CONFIG_I2CTOOL_DEFFREQ=100000
+
+nx
+--
+
+This configuration has been used to bring up the Sharp Memory LCD
+on a custom board. This NX configuration was used for testing that
+LCD. Debug output will appear on USART1.
+
+NOTES:
+1. Currently configured for the STM32F103CB. But this is easily reconfigured::
+
+ CONFIG_ARCH_CHIP_STM32F103RB=n
+ CONFIG_ARCH_CHIP_STM32F103CB=y
+
+2. You won't be able to buy a Sharp Memory LCD to use with your
+ Maple. If you want one, you will have to make one yourself.
+
+usbnsh
+------
+
+This is an alternative NuttShell (NSH) configuration that uses a USB
+serial console for interaction.
+
+NOTES:
+1. Currently configured for the STM32F103CB. But this is easily reconfigured::
+
+ CONFIG_ARCH_CHIP_STM32F103RB=n
+ CONFIG_ARCH_CHIP_STM32F103CB=y
+
+2. Support for the I2C tool has been disabled, but can be restored
+ with following configure options::
+
+ System Type -> Peripherals
+ CONFIG_STM32_I2C1=y
+ CONFIG_STM32_I2C2=y
+ CONFIG_STM32_I2CTIMEOSEC=1
+ CONFIG_STM32_I2CTIMEOMS=500
+ CONFIG_STM32_I2CTIMEOTICKS=500
+
+ Drivers
+ CONFIG_I2C=y
+
+ Applications -> System Add-Ons
+ CONFIG_SYSTEM_I2CTOOL=y
+ CONFIG_I2CTOOL_MINBUS=1
+ CONFIG_I2CTOOL_MAXBUS=2
+ CONFIG_I2CTOOL_MINADDR=0x0
+ CONFIG_I2CTOOL_MAXADDR=0xf0
+ CONFIG_I2CTOOL_MAXREGADDR=0xff
+ CONFIG_I2CTOOL_DEFFREQ=100000
diff --git a/content/docs/latest/_sources/platforms/arm/stm32f1/boards/nucleo-f103rb/index.rst.txt b/content/docs/latest/_sources/platforms/arm/stm32f1/boards/nucleo-f103rb/index.rst.txt
new file mode 100644
index 00000000..edff2573
--- /dev/null
+++ b/content/docs/latest/_sources/platforms/arm/stm32f1/boards/nucleo-f103rb/index.rst.txt
@@ -0,0 +1,71 @@
+================
+ST Nucleo F103RB
+================
+
+The Nucleo-F103RB is a member of the Nucleo-64 board family.
+
+Configurations
+==============
+
+ihm07m1_b16:
+------------
+
+These examples are dedicated for the X-NUCLEO-IHM07M1 expansion board
+based on L6230 DMOS driver for three-phase brushless DC motors.
+
+X-NUCLEO-IHM07M1 must be configured to work with FOC and 3-shunt
+resistors. See ST documentation for details.
+
+Pin configuration for the X-NUCLEO-IHM07M1 (TIM1 configuration):
+
+ ============== ================ =================
+ Board Function Chip Function Chip Pin Number
+ ============== ================ =================
+ Phase U high TIM1_CH1 PA8
+ Phase U enable GPIO_PC10 PC10
+ Phase V high TIM1_CH2 PA9
+ Phase V enable GPIO_PC11 PC11
+ Phase W high TIM1_CH3 PA10
+ Phase W enable GPIO_PC12 PC12
+ DIAG/EN GPIO_PA11 PA11
+ Current U ADC1_IN0 PA0
+ Current V ADC1_IN11 PC1
+ Current W ADC1_IN10 PC0
+ Temperature ADC1_IN12 PC2
+ VBUS ADC1_IN1 PA1
+ BEMF1 (NU) PC3
+ BEMF2 (NU) PB0
+ BEMF3 (NU) PA7
+ LED GPIO_PB2 PB2
+ +3V3 (CN7_16)
+ GND (CN7_20)
+ GPIO_BEMF (NU) PC9
+ ENCO_A/HALL_H1 TIM2_CH1 PA15
+ ENCO_B/HALL_H2 TIM2_CH2 PB3
+ ENCO_Z/HALL_H3 TIM2_CH3 PB10
+ GPIO1 (NU) PB13
+ GPIO2 (NU) PB5
+ GPIO3 (NU) PA5
+ CPOUT (NU) PA12
+ BKIN1 (NU) PB14
+ POT ADC1_IN9 PB1
+ CURR_REF (NU) PB4
+ DAC DAC1_CH1 PA4
+ DEBUG0 GPIO PB8
+ DEBUG1 GPIO PB9
+ DEBUG2 GPIO PC6
+ DEBUG3 GPIO PC5
+ DEBUG4 GPIO PC8
+ ============== ================ =================
+
+ Current shunt resistance = 0.33
+ Current sense gain = -1.53 (inverted current)
+ Vbus sense gain = 9.31k/(9.31k+169k) = 0.0522124390107
+ Vbus min = 8V
+ Vbus max = 48V
+ Iout max = 1.4A RMS
+
+ IPHASE_RATIO = 1/(R_shunt*gain) = -1.98
+ VBUS_RATIO = 1/VBUS_gain = 19.152
+
+ For now only 3-shunt resistors configuration is supported.
diff --git a/content/docs/latest/_sources/platforms/arm/stm32f1/boards/olimexino-stm32/index.rst.txt b/content/docs/latest/_sources/platforms/arm/stm32f1/boards/olimexino-stm32/index.rst.txt
new file mode 100644
index 00000000..af7c8112
--- /dev/null
+++ b/content/docs/latest/_sources/platforms/arm/stm32f1/boards/olimexino-stm32/index.rst.txt
@@ -0,0 +1,3 @@
+===============
+olimexino-stm32
+===============
diff --git a/content/docs/latest/_sources/platforms/arm/stm32f1/boards/shenzhou/index.rst.txt b/content/docs/latest/_sources/platforms/arm/stm32f1/boards/shenzhou/index.rst.txt
new file mode 100644
index 00000000..b7c08952
--- /dev/null
+++ b/content/docs/latest/_sources/platforms/arm/stm32f1/boards/shenzhou/index.rst.txt
@@ -0,0 +1,570 @@
+===========
+Shenzhou IV
+===========
+
+This README discusses issues unique to NuttX configurations for the Shenzhou
+IV development board from www.armjishu.com featuring the STMicro STM32F107VCT
+MCU. As of this writing, there are five models of the Shenzhou board:
+
+1. Shenzhou I (STM32F103RB)
+2. Shenzhou II (STM32F103VC)
+3. Shenzhou III (STM32F103ZE)
+4. Shenzhou IV (STM32F107VC)
+5. Shenzhou king ((STM32F103ZG, core board + IO expansion board)).
+
+Support is currently provided for the Shenzhou IV only. Features of the
+Shenzhou IV board include:
+
+- STM32F107VCT
+- 10/100M PHY (DM9161AEP)
+- TFT LCD Connector
+- USB OTG
+- CAN (CAN1=2)
+- USART connectos (USART1-2)
+- RS-485
+- SD card slot
+- Audio DAC (PCM1770)
+- SPI Flash (W25X16)
+- (4) LEDs (LED1-4)
+- 2.4G Wireless (NRF24L01 SPI module)
+- 315MHz Wireless (module)
+- (4) Buttons (KEY1-4, USERKEY2, USERKEY, TEMPER, WAKEUP)
+- VBUS/external +4V select
+- 5V/3.3V power conversion
+- Extension connector
+- JTAG
+
+STM32F107VCT Pin Usage
+======================
+
+..
+ -- ---- -------------- -------------------------------------------------------------------
+ PN NAME SIGNAL NOTES
+ -- ---- -------------- -------------------------------------------------------------------
+ 23 PA0 WAKEUP Connected to KEY4. Active low: Closing KEY4 pulls WAKEUP to ground.
+ 24 PA1 MII_RX_CLK
+ RMII_REF_CLK
+ 25 PA2 MII_MDIO
+ 26 PA3 315M_VT
+ 29 PA4 DAC_OUT1 To CON5(CN14)
+ 30 PA5 DAC_OUT2 To CON5(CN14). JP10
+ SPI1_SCK To the SD card, SPI FLASH
+ 31 PA6 SPI1_MISO To the SD card, SPI FLASH
+ 32 PA7 SPI1_MOSI To the SD card, SPI FLASH
+ 67 PA8 MCO To DM9161AEP PHY
+ 68 PA9 USB_VBUS MINI-USB-AB. JP3
+ USART1_TX MAX3232 to CN5
+ 69 PA10 USB_ID MINI-USB-AB. JP5
+ USART1_RX MAX3232 to CN5
+ 70 PA11 USB_DM MINI-USB-AB
+ 71 PA12 USB_DP MINI-USB-AB
+ 72 PA13 TMS/SWDIO
+ 76 PA14 TCK/SWCLK
+ 77 PA15 TDI
+
+ -- ---- -------------- -------------------------------------------------------------------
+ PN NAME SIGNAL NOTES
+ -- ---- -------------- -------------------------------------------------------------------
+ 35 PB0 ADC_IN1 To CON5(CN14)
+ 36 PB1 ADC_IN2 To CON5(CN14)
+ 37 PB2 DATA_LE To TFT LCD (CN13)
+ BOOT1 JP13
+ 89 PB3 TDO/SWO
+ 90 PB4 TRST
+ 91 PB5 CAN2_RX
+ 92 PB6 CAN2_TX JP11
+ I2C1_SCL
+ 93 PB7 I2C1_SDA
+ 95 PB8 USB_PWR Drives USB VBUS
+ 96 PB9 F_CS To both the TFT LCD (CN13) and to the W25X16 SPI FLASH
+ 47 PB10 USERKEY Connected to KEY2
+ 48 PB11 MII_TX_EN Ethernet PHY
+ 51 PB12 I2S_WS Audio DAC
+ MII_TXD0 Ethernet PHY
+ 52 PB13 I2S_CK Audio DAC
+ MII_TXD1 Ethernet PHY
+ 53 PB14 SD_CD There is confusion here. Schematic is wrong LCD_WR is PB14.
+ 54 PB15 I2S_DIN Audio DAC
+
+ -- ---- -------------- -------------------------------------------------------------------
+ PN NAME SIGNAL NOTES
+ -- ---- -------------- -------------------------------------------------------------------
+ 15 PC0 POTENTIO_METER
+ 16 PC1 MII_MDC Ethernet PHY
+ 17 PC2 WIRELESS_INT
+ 18 PC3 WIRELESS_CE To the NRF24L01 2.4G wireless module
+ 33 PC4 USERKEY2 Connected to KEY1
+ 34 PC5 TP_INT JP6. To TFT LCD (CN13) module
+ MII_INT Ethernet PHY
+ 63 PC6 I2S_MCK Audio DAC. Active low: Pulled high
+ 64 PC7 PCM1770_CS Audio DAC. Active low: Pulled high
+ 65 PC8 LCD_CS TFT LCD (CN13). Active low: Pulled high
+ 66 PC9 TP_CS TFT LCD (CN13). Active low: Pulled high
+ 78 PC10 SPI3_SCK To TFT LCD (CN13), the NRF24L01 2.4G wireless module
+ 79 PC11 SPI3_MISO To TFT LCD (CN13), the NRF24L01 2.4G wireless module
+ 80 PC12 SPI3_MOSI To TFT LCD (CN13), the NRF24L01 2.4G wireless module
+ 7 PC13 TAMPER Connected to KEY3
+ 8 PC14 OSC32_IN Y1 32.768Khz XTAL
+ 9 PC15 OSC32_OUT Y1 32.768Khz XTAL
+
+ -- ---- -------------- -------------------------------------------------------------------
+ PN NAME SIGNAL NOTES
+ -- ---- -------------- -------------------------------------------------------------------
+ 81 PD0 CAN1_RX
+ 82 PD1 CAN1_TX
+ 83 PD2 LED1 Active low: Pulled high
+ 84 PD3 LED2 Active low: Pulled high
+ 85 PD4 LED3 Active low: Pulled high
+ 86 PD5 485_TX Same as USART2_TX but goes to SP3485
+ USART2_TX MAX3232 to CN6
+ 87 PD6 485_RX Save as USART2_RX but goes to SP3485 (see JP4)
+ USART2_RX MAX3232 to CN6
+ 88 PD7 LED4 Active low: Pulled high
+ 485_DIR SP3485 read enable (not)
+ 55 PD8 MII_RX_DV Ethernet PHY
+ RMII_CRSDV Ethernet PHY
+ 56 PD9 MII_RXD0 Ethernet PHY
+ 57 PD10 MII_RXD1 Ethernet PHY
+ 58 PD11 SD_CS Active low: Pulled high (See also TFT LCD CN13, pin 32)
+ 59 PD12 WIRELESS_CS To the NRF24L01 2.4G wireless module
+ 60 PD13 LCD_RS To TFT LCD (CN13)
+ 61 PD14 LCD_WR To TFT LCD (CN13). Schematic is wrong LCD_WR is PB14.
+ 62 PD15 LCD_RD To TFT LCD (CN13)
+
+ -- ---- -------------- -------------------------------------------------------------------
+ PN NAME SIGNAL NOTES
+ -- ---- -------------- -------------------------------------------------------------------
+ 97 PE0 DB00 To TFT LCD (CN13)
+ 98 PE1 DB01 To TFT LCD (CN13)
+ 1 PE2 DB02 To TFT LCD (CN13)
+ 2 PE3 DB03 To TFT LCD (CN13)
+ 3 PE4 DB04 To TFT LCD (CN13)
+ 4 PE5 DB05 To TFT LCD (CN13)
+ 5 PE6 DB06 To TFT LCD (CN13)
+ 38 PE7 DB07 To TFT LCD (CN13)
+ 39 PE8 DB08 To TFT LCD (CN13)
+ 40 PE9 DB09 To TFT LCD (CN13)
+ 41 PE10 DB10 To TFT LCD (CN13)
+ 42 PE11 DB11 To TFT LCD (CN13)
+ 43 PE12 DB12 To TFT LCD (CN13)
+ 44 PE13 DB13 To TFT LCD (CN13)
+ 45 PE14 DB14 To TFT LCD (CN13)
+ 46 PE15 DB15 To TFT LCD (CN13)
+
+ -- ---- -------------- -------------------------------------------------------------------
+ PN NAME SIGNAL NOTES
+ -- ---- -------------- -------------------------------------------------------------------
+ 73 N/C
+
+ 12 OSC_IN Y2 25Mhz XTAL
+ 13 OSC_OUT Y2 25Mhz XTAL
+
+ 94 BOOT0 JP15 (3.3V or GND)
+ 14 RESET S5
+ 6 VBAT JP14 (3.3V or battery)
+
+ 49 VSS_1 GND
+ 74 VSS_2 GND
+ 99 VSS_3 GND
+ 27 VSS_4 GND
+ 10 VSS_5 GND
+ 19 VSSA VSSA
+ 20 VREF- VREF-
+
+LEDs
+====
+
+The Shenzhou board has four LEDs labeled LED1, LED2, LED3 and LED4 on the
+board. These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
+defined. In that case, the usage by the board port is defined in
+include/board.h and src/up_leds.c. The LEDs are used to encode OS-related
+events as follows::
+
+ SYMBOL Meaning LED1* LED2 LED3 LED4****
+ ------------------- ----------------------- ------- ------- ------- ------
+ LED_STARTED NuttX has been started ON OFF OFF OFF
+ LED_HEAPALLOCATE Heap has been allocated OFF ON OFF OFF
+ LED_IRQSENABLED Interrupts enabled ON ON OFF OFF
+ LED_STACKCREATED Idle stack created OFF OFF ON OFF
+ LED_INIRQ In an interrupt** ON N/C N/C OFF
+ LED_SIGNAL In a signal handler*** N/C ON N/C OFF
+ LED_ASSERTION An assertion failed ON ON N/C OFF
+ LED_PANIC The system has crashed N/C N/C N/C ON
+ LED_IDLE STM32 is is sleep mode (Optional, not used)
+
+ * If LED1, LED2, LED3 are statically on, then NuttX probably failed to boot
+ and these LEDs will give you some indication of where the failure was
+ ** The normal state is LED1 ON and LED1 faintly glowing. This faint glow
+ is because of timer interrupts that result in the LED being illuminated
+ on a small proportion of the time.
+ *** LED2 may also flicker normally if signals are processed.
+ **** LED4 may not be available if RS-485 is also used. For RS-485, it will
+ then indicate the RS-485 direction.
+
+Shenzhou-specific Configuration Options
+=======================================
+
+..
+ CONFIG_ARCH - Identifies the arch/ subdirectory. This should
+ be set to:
+
+ CONFIG_ARCH=arm
+
+ CONFIG_ARCH_family - For use in C code:
+
+ CONFIG_ARCH_ARM=y
+
+ CONFIG_ARCH_architecture - For use in C code:
+
+ CONFIG_ARCH_CORTEXM3=y
+
+ CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
+
+ CONFIG_ARCH_CHIP=stm32
+
+ CONFIG_ARCH_CHIP_name - For use in C code to identify the exact
+ chip:
+
+ CONFIG_ARCH_CHIP_STM32F107VC=y
+
+ CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock
+ configuration features.
+
+ CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n
+
+ CONFIG_ARCH_BOARD - Identifies the boards/ subdirectory and
+ hence, the board that supports the particular chip or SoC.
+
+ CONFIG_ARCH_BOARD=shenzhou (for the Shenzhou development board)
+
+ CONFIG_ARCH_BOARD_name - For use in C code
+
+ CONFIG_ARCH_BOARD_SHENZHOU=y
+
+ CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
+ of delay loops
+
+ CONFIG_ENDIAN_BIG - define if big endian (default is little
+ endian)
+
+ CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case):
+
+ CONFIG_RAM_SIZE=0x00010000 (64Kb)
+
+ CONFIG_RAM_START - The start address of installed DRAM
+
+ CONFIG_RAM_START=0x20000000
+
+ CONFIG_STM32_CCMEXCLUDE - Exclude CCM SRAM from the HEAP
+
+ CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that
+ have LEDs
+
+ CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
+ stack. If defined, this symbol is the size of the interrupt
+ stack in bytes. If not defined, the user task stacks will be
+ used during interrupt handling.
+
+ CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
+
+ CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture.
+
+ Individual subsystems can be enabled:
+
+ AHB
+ ---
+ CONFIG_STM32_DMA1
+ CONFIG_STM32_DMA2
+ CONFIG_STM32_CRC
+ CONFIG_STM32_ETHMAC
+ CONFIG_STM32_OTGFS
+ CONFIG_STM32_IWDG
+ CONFIG_STM32_PWR -- Required for RTC
+
+ APB1 (low speed)
+ ----------------
+ CONFIG_STM32_BKP
+ CONFIG_STM32_TIM2
+ CONFIG_STM32_TIM3
+ CONFIG_STM32_TIM4
+ CONFIG_STM32_TIM5
+ CONFIG_STM32_TIM6
+ CONFIG_STM32_TIM7
+ CONFIG_STM32_USART2
+ CONFIG_STM32_USART3
+ CONFIG_STM32_UART4
+ CONFIG_STM32_UART5
+ CONFIG_STM32_SPI2
+ CONFIG_STM32_SPI3
+ CONFIG_STM32_I2C1
+ CONFIG_STM32_I2C2
+ CONFIG_STM32_CAN1
+ CONFIG_STM32_CAN2
+ CONFIG_STM32_DAC1
+ CONFIG_STM32_DAC2
+ CONFIG_STM32_WWDG
+
+ APB2 (high speed)
+ -----------------
+ CONFIG_STM32_TIM1
+ CONFIG_STM32_SPI1
+ CONFIG_STM32_USART1
+ CONFIG_STM32_ADC1
+ CONFIG_STM32_ADC2
+
+ Timer and I2C devices may need to the following to force power to be applied
+ unconditionally at power up. (Otherwise, the device is powered when it is
+ initialized).
+
+ CONFIG_STM32_FORCEPOWER
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If CONFIG_STM32_TIMn
+ is defined (as above) then the following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation, ADC conversion,
+ or DAC conversion. Note that ADC/DAC require two definition: Not only do you have
+ to assign the timer (n) for used by the ADC or DAC, but then you also have to
+ configure which ADC or DAC (m) it is assigned to.
+
+ CONFIG_STM32_TIMn_PWM Reserve timer n for use by PWM, n=1,..,14
+ CONFIG_STM32_TIMn_ADC Reserve timer n for use by ADC, n=1,..,14
+ CONFIG_STM32_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,14, m=1,..,3
+ CONFIG_STM32_TIMn_DAC Reserve timer n for use by DAC, n=1,..,14
+ CONFIG_STM32_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,14, m=1,..,2
+
+ For each timer that is enabled for PWM usage, we need the following additional
+ configuration settings:
+
+ CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
+
+ NOTE: The STM32 timers are each capable of generating different signals on
+ each of the four channels with different duty cycles. That capability is
+ not supported by this driver: Only one output channel per timer.
+
+ JTAG Enable settings (by default JTAG-DP and SW-DP are disabled):
+
+ CONFIG_STM32_JTAG_FULL_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
+ CONFIG_STM32_JTAG_NOJNTRST_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
+ but without JNTRST.
+ CONFIG_STM32_JTAG_SW_ENABLE - Set JTAG-DP disabled and SW-DP enabled
+
+ STM32107xxx specific device driver settings
+
+ CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=1,2,3) or UART
+ m (m=4,5) for the console and ttys0 (default is the USART1).
+ CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received.
+ This specific the size of the receive buffer
+ CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before
+ being sent. This specific the size of the transmit buffer
+ CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be
+ CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8.
+ CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
+ CONFIG_U[S]ARTn_2STOP - Two stop bits
+
+ CONFIG_STM32_SPI_INTERRUPTS - Select to enable interrupt driven SPI
+ support. Non-interrupt-driven, poll-waiting is recommended if the
+ interrupt rate would be to high in the interrupt driven case.
+ CONFIG_STM32_SPIx_DMA - Use DMA to improve SPIx transfer performance.
+ Cannot be used with CONFIG_STM32_SPI_INTERRUPT.
+
+ CONFIG_STM32_PHYADDR - The 5-bit address of the PHY on the board
+ CONFIG_STM32_MII - Support Ethernet MII interface
+ CONFIG_STM32_MII_MCO - Use MCO to clock the MII interface
+ CONFIG_STM32_RMII - Support Ethernet RMII interface
+ CONFIG_STM32_RMII_MCO - Use MCO to clock the RMII interface
+ CONFIG_STM32_AUTONEG - Use PHY autonegotiation to determine speed and mode
+ CONFIG_STM32_ETHFD - If CONFIG_STM32_AUTONEG is not defined, then this
+ may be defined to select full duplex mode. Default: half-duplex
+ CONFIG_STM32_ETH100MBPS - If CONFIG_STM32_AUTONEG is not defined, then this
+ may be defined to select 100 MBps speed. Default: 10 Mbps
+ CONFIG_STM32_PHYSR - This must be provided if CONFIG_STM32_AUTONEG is
+ defined. The PHY status register address may diff from PHY to PHY. This
+ configuration sets the address of the PHY status register.
+ CONFIG_STM32_PHYSR_SPEED - This must be provided if CONFIG_STM32_AUTONEG is
+ defined. This provides bit mask indicating 10 or 100MBps speed.
+ CONFIG_STM32_PHYSR_100MBPS - This must be provided if CONFIG_STM32_AUTONEG is
+ defined. This provides the value of the speed bit(s) indicating 100MBps speed.
+ CONFIG_STM32_PHYSR_MODE - This must be provided if CONFIG_STM32_AUTONEG is
+ defined. This provide bit mask indicating full or half duplex modes.
+ CONFIG_STM32_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32_AUTONEG is
+ defined. This provides the value of the mode bits indicating full duplex mode.
+ CONFIG_STM32_ETH_PTP - Precision Time Protocol (PTP). Not supported
+ but some hooks are indicated with this condition.
+
+ Shenzhou CAN Configuration
+
+ CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32_CAN1 or
+ CONFIG_STM32_CAN2 must also be defined)
+ CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages.
+ Default: 8
+ CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests.
+ Default: 4
+ CONFIG_CAN_LOOPBACK - A CAN driver may or may not support a loopback
+ mode for testing. The STM32 CAN driver does support loopback mode.
+ CONFIG_STM32_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN1
+ is defined.
+ CONFIG_STM32_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN2
+ is defined.
+ CONFIG_STM32_CAN_TSEG1 - The number of CAN time quanta in segment 1.
+ Default: 6
+ CONFIG_STM32_CAN_TSEG2 - the number of CAN time quanta in segment 2.
+ Default: 7
+ CONFIG_STM32_CAN_REGDEBUG - If CONFIG_DEBUG_FEATURES is set, this will generate an
+ dump of all CAN registers.
+
+ Shenzhou LCD Hardware Configuration
+
+ The LCD driver supports the following LCDs on the STM324xG_EVAL board:
+
+ AM-240320L8TNQW00H (LCD_ILI9320 or LCD_ILI9321) OR
+ AM-240320D5TOQW01H (LCD_ILI9325)
+
+ Configuration options.
+
+ CONFIG_LCD_LANDSCAPE - Define for 320x240 display "landscape"
+ support. Default is this 320x240 "landscape" orientation
+ For the Shenzhou board, the edge opposite from the row of buttons
+ is used as the top of the display in this orientation.
+ CONFIG_LCD_RLANDSCAPE - Define for 320x240 display "reverse
+ landscape" support. Default is this 320x240 "landscape"
+ orientation
+ For the Shenzhou board, the edge next to the row of buttons
+ is used as the top of the display in this orientation.
+ CONFIG_LCD_PORTRAIT - Define for 240x320 display "portrait"
+ orientation support.
+ CONFIG_LCD_RPORTRAIT - Define for 240x320 display "reverse
+ portrait" orientation support.
+ CONFIG_LCD_RDSHIFT - When reading 16-bit gram data, there appears
+ to be a shift in the returned data. This value fixes the offset.
+ Default 5.
+
+ The LCD driver dynamically selects the LCD based on the reported LCD
+ ID value. However, code size can be reduced by suppressing support for
+ individual LCDs using:
+
+ CONFIG_STM32_ILI9320_DISABLE (includes ILI9321)
+ CONFIG_STM32_ILI9325_DISABLE
+
+ STM32 USB OTG FS Host Driver Support
+
+ Pre-requisites
+
+ CONFIG_USBHOST - Enable USB host support
+ CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block
+ CONFIG_STM32_SYSCFG - Needed
+ CONFIG_SCHED_WORKQUEUE - Worker thread support is required
+
+ Options:
+
+ CONFIG_STM32_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words.
+ Default 128 (512 bytes)
+ CONFIG_STM32_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO
+ in 32-bit words. Default 96 (384 bytes)
+ CONFIG_STM32_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit
+ words. Default 96 (384 bytes)
+ CONFIG_STM32_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: 128
+ CONFIG_STM32_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever
+ want to do that?
+ CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access
+ debug. Depends on CONFIG_DEBUG_FEATURES.
+ CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB
+ packets. Depends on CONFIG_DEBUG_FEATURES.
+
+Configurations
+==============
+
+Each Shenzhou configuration is maintained in a sub-directory and
+can be selected as follow::
+
+ tools/configure.sh shenzhou:<subdir>
+
+Where <subdir> is one of the following:
+
+nsh
+---
+
+Configures the NuttShell (nsh) located at apps/examples/nsh. The
+Configuration enables both the serial and telnet NSH interfaces.::
+
+ CONFIG_ARM_TOOLCHAIN_GNU_EABI=y : GNU EABI toolchain for Windows
+ CONFIG_NSH_DHCPC=n : DHCP is disabled
+ CONFIG_NSH_IPADDR=0x0a000002 : Target IP address 10.0.0.2
+ CONFIG_NSH_DRIPADDR=0x0a000001 : Host IP address 10.0.0.1
+
+NOTES:
+
+1. This example assumes that a network is connected. During its
+ initialization, it will try to negotiate the link speed. If you have
+ no network connected when you reset the board, there will be a long
+ delay (maybe 30 seconds?) before anything happens. That is the timeout
+ before the networking finally gives up and decides that no network is
+ available.
+
+2. Enabling the ADC example:
+
+ The only internal signal for ADC testing is the potentiometer input::
+
+ ADC1_IN10(PC0) Potentiometer
+
+ External signals are also available on CON5 CN14::
+
+ ADC_IN8 (PB0) CON5 CN14 Pin2
+ ADC_IN9 (PB1) CON5 CN14 Pin1
+
+ The signal selection is hard-coded in boards/arm/stm32/shenzhou/src/up_adc.c: The
+ potentiometer input (only) is selected.
+
+ These selections will enable sampling the potentiometer input at 100Hz using
+ Timer 1::
+
+ CONFIG_ANALOG=y : Enable analog device support
+ CONFIG_ADC=y : Enable generic ADC driver support
+ CONFIG_ADC_DMA=n : ADC DMA is not supported
+ CONFIG_STM32_ADC1=y : Enable ADC 1
+ CONFIG_STM32_TIM1=y : Enable Timer 1
+ CONFIG_STM32_TIM1_ADC=y : Use Timer 1 for ADC
+ CONFIG_STM32_TIM1_ADC1=y : Allocate Timer 1 to ADC 1
+ CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=100 : Set sampling frequency to 100Hz
+ CONFIG_STM32_ADC1_TIMTRIG=0 : Trigger on timer output 0
+ CONFIG_STM32_FORCEPOWER=y : Apply power to TIM1 a boot up time
+ CONFIG_EXAMPLES_ADC=y : Enable the apps/examples/adc built-in
+
+nxwm
+----
+
+This is a special configuration setup for the NxWM window manager
+UnitTest. The NxWM window manager can be found here::
+
+ apps/graphics/NxWidgets/nxwm
+
+The NxWM unit test can be found at::
+
+ apps/graphics/NxWidgets/UnitTests/nxwm
+
+NOTE: JP6 selects between the touchscreen interrupt and the MII
+interrupt. It should be positioned 1-2 to enable the touchscreen
+interrupt.
+
+NOTE: Reading from the LCD is not currently supported by this
+configuration. The hardware will support reading from the LCD
+and drivers/lcd/ssd1289.c also supports reading from the LCD.
+This limits some graphics capabilities.
+
+Reading from the LCD is not supported only because it has not
+been tested. If you get inspired to test this feature, you can
+turn the LCD read functionality on by setting::
+
+ -CONFIG_LCD_NOGETRUN=y
+ +# CONFIG_LCD_NOGETRUN is not set
+
+ -CONFIG_NX_WRITEONLY=y
+ +# CONFIG_NX_WRITEONLY is not set
+
+thttpd
+------
+
+This builds the THTTPD web server example using the THTTPD and
+the apps/examples/thttpd application.
+
+NOTE: This example can only be built using the older toolchains
+due to incompatibilities introduced in later GCC releases.
diff --git a/content/docs/latest/_sources/platforms/arm/stm32f1/boards/stm3210e-eval/index.rst.txt b/content/docs/latest/_sources/platforms/arm/stm32f1/boards/stm3210e-eval/index.rst.txt
new file mode 100644
index 00000000..60f46908
--- /dev/null
+++ b/content/docs/latest/_sources/platforms/arm/stm32f1/boards/stm3210e-eval/index.rst.txt
@@ -0,0 +1,912 @@
+================
+ST STM3210E-EVAL
+================
+
+This README discusses issues unique to NuttX configurations for the
+STMicro STM3210E-EVAL development board.
+
+DFU and JTAG
+============
+
+Enbling Support for the DFU Bootloader
+--------------------------------------
+
+The linker files in these projects can be configured to indicate that you
+will be loading code using STMicro built-in USB Device Firmware Upgrade (DFU)
+loader or via some JTAG emulator. You can specify the DFU bootloader by
+adding the following line::
+
+ CONFIG_STM32_DFU=y
+
+to your .config file. Most of the configurations in this directory are set
+up to use the DFU loader.
+
+If CONFIG_STM32_DFU is defined, the code will not be positioned at the beginning
+of FLASH (0x08000000) but will be offset to 0x08003000. This offset is needed
+to make space for the DFU loader and 0x08003000 is where the DFU loader expects
+to find new applications at boot time. If you need to change that origin for some
+other bootloader, you will need to edit the file(s) ld.script.dfu for the
+configuration.
+
+The DFU SE PC-based software is available from the STMicro website,
+http://www.st.com. General usage instructions:
+
+1. Convert the NuttX Intel Hex file (nuttx.hex) into a special DFU
+ file (nuttx.dfu)... see below for details.
+
+2. Connect the STM3210E-EVAL board to your computer using a USB cable.
+
+3. Start the DFU loader on the STM3210E-EVAL board. You do this by
+ resetting the board while holding the "Key" button. Windows should
+ recognize that the DFU loader has been installed.
+
+4. Run the DFU SE program to load nuttx.dfu into FLASH.
+
+What if the DFU loader is not in FLASH? The loader code is available
+inside of the Demo directory of the USBLib ZIP file that can be downloaded
+from the STMicro Website. You can build it using RIDE (or other toolchains);
+you will need a JTAG emulator to burn it into FLASH the first time.
+
+In order to use STMicro's built-in DFU loader, you will have to get
+the NuttX binary into a special format with a .dfu extension. The
+DFU SE PC_based software installation includes a file "DFU File Manager"
+conversion program that a file in Intel Hex format to the special DFU
+format. When you successfully build NuttX, you will find a file called
+nutt.hex in the top-level directory. That is the file that you should
+provide to the DFU File Manager. You will end up with a file called
+nuttx.dfu that you can use with the STMicro DFU SE program.
+
+Enabling JTAG
+-------------
+
+If you are not using the DFU, then you will probably also need to enable
+JTAG support. By default, all JTAG support is disabled but there NuttX
+configuration options to enable JTAG in various different ways.
+
+These configurations effect the setting of the SWJ_CFG[2:0] bits in the AFIO
+MAPR register. These bits are used to configure the SWJ and trace alternate
+function I/Os. The SWJ (SerialWire JTAG) supports JTAG or SWD access to the
+Cortex debug port. The default state in this port is for all JTAG support
+to be disabled.
+
+CONFIG_STM32_JTAG_FULL_ENABLE - sets SWJ_CFG[2:0] to 000 which enables full
+SWJ (JTAG-DP + SW-DP)
+
+CONFIG_STM32_JTAG_NOJNTRST_ENABLE - sets SWJ_CFG[2:0] to 001 which enable
+full SWJ (JTAG-DP + SW-DP) but without JNTRST.
+
+CONFIG_STM32_JTAG_SW_ENABLE - sets SWJ_CFG[2:0] to 010 which would set JTAG-DP
+disabled and SW-DP enabled.
+
+The default setting (none of the above defined) is SWJ_CFG[2:0] set to 100
+which disable JTAG-DP and SW-DP.
+
+OpenOCD
+=======
+
+I have also used OpenOCD with the STM3210E-EVAL. In this case, I used
+the Olimex USB ARM OCD. See the script in boards/arm/stm32/stm3210e-eval/tools/oocd.sh
+for more information. Using the script:
+
+- Start the OpenOCD GDB server::
+
+ cd <nuttx-build-directory>
+ boards/arm/stm32/stm3210e-eval/tools/oocd.sh $PWD
+
+- Load NuttX::
+
+ cd <nuttx-built-directory>
+ arm-none-eabi-gdb nuttx
+ gdb> target remote localhost:3333
+ gdb> mon reset
+ gdb> mon halt
+ gdb> load nuttx
+
+- Running NuttX::
+
+ gdb> mon reset
+ gdb> c
+
+LEDs
+====
+
+The STM3210E-EVAL board has four LEDs labeled LD1, LD2, LD3 and LD4 on the
+board. These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
+defined. In that case, the usage by the board port is defined in
+include/board.h and src/up_leds.c. The LEDs are used to encode OS-related
+events as follows:
+
+ =================== ======================= ======= ======= ======= ======
+ SYMBOL Meaning LED1[1] LED2 LED3 LED4[4]
+ =================== ======================= ======= ======= ======= ======
+ LED_STARTED NuttX has been started ON OFF OFF OFF
+ LED_HEAPALLOCATE Heap has been allocated OFF ON OFF OFF
+ LED_IRQSENABLED Interrupts enabled ON ON OFF OFF
+ LED_STACKCREATED Idle stack created OFF OFF ON OFF
+ LED_INIRQ In an interrupt[2] ON N/C N/C OFF
+ LED_SIGNAL In a signal handler[3] N/C ON N/C OFF
+ LED_ASSERTION An assertion failed ON ON N/C OFF
+ LED_PANIC The system has crashed N/C N/C N/C ON
+ LED_IDLE STM32 is is sleep mode
+ =================== ======================= ======= ======= ======= ======
+
+ [1] If LED1, LED2, LED3 are statically on, then NuttX probably failed to boot
+ and these LEDs will give you some indication of where the failure was
+ [2] The normal state is LED1 ON and LED1 faintly glowing. This faint glow
+ is because of timer interrupts that result in the LED being illuminated
+ on a small proportion of the time.
+ [3] LED2 may also flicker normally if signals are processed.
+ [4] LED4 may not be available if RS-485 is also used. For RS-485, it will
+ then indicate the RS-485 direction.
+
+Temperature Sensor
+==================
+
+LM-75 Temperature Sensor Driver
+-------------------------------
+
+Support for the on-board LM-75 temperature sensor is available. This
+support has been verified, but has not been included in any of the
+available the configurations. To set up the temperature sensor, add the
+following to the NuttX configuration file::
+
+ Drivers -> Sensors
+ CONFIG_SENSORS_LM75=y
+ CONFIG_LM75_I2C=y
+
+Then you can implement logic like the following to use the temperature
+sensor::
+
+ #include <nuttx/sensors/lm75.h>
+ #include <arch/board/board.h>
+
+ ret = stm32_lm75initialize("/dev/temp"); /* Register the temperature sensor */
+ fd = open("/dev/temp", O_RDONLY); /* Open the temperature sensor device */
+ ret = ioctl(fd, SNIOC_FAHRENHEIT, 0); /* Select Fahrenheit */
+ bytesread = read(fd, buffer, 8*sizeof(b16_t)); /* Read temperature samples */
+
+More complex temperature sensor operations are also available. See the
+IOCTL commands enumerated in include/nuttx/sensors/lm75.h. Also read the
+descriptions of the stm32_lm75initialize() and stm32_lm75attach()
+interfaces in the arch/board/board.h file (sames as
+boards/arm/stm32/stm3210e-eval/include/board.h).
+
+NSH Command Line Application
+----------------------------
+
+There is a tiny NSH command line application at examples/system/lm75 that
+will read the current temperature from an LM75 compatible temperature sensor
+and print the temperature on stdout in either units of degrees Fahrenheit or
+Centigrade. This tiny command line application is enabled with the following
+configuration options::
+
+ Library
+ CONFIG_LIBM=y
+ CONFIG_LIBC_FLOATINGPOINT=y
+
+ Applications -> NSH Library
+ CONFIG_NSH_ARCHINIT=y
+
+ Applications -> System Add-Ons
+ CONFIG_SYSTEM_LM75=y
+ CONFIG_SYSTEM_LM75_DEVNAME="/dev/temp"
+ CONFIG_SYSTEM_LM75_FAHRENHEIT=y (or CENTIGRADE)
+ CONFIG_SYSTEM_LM75_STACKSIZE=1024
+ CONFIG_SYSTEM_LM75_PRIORITY=100
+
+RTC
+===
+
+The STM32 RTC may configured using the following settings.::
+
+ CONFIG_RTC - Enables general support for a hardware RTC. Specific
+ architectures may require other specific settings.
+ CONFIG_RTC_HIRES - The typical RTC keeps time to resolution of 1
+ second, usually supporting a 32-bit time_t value. In this case,
+ the RTC is used to "seed" the normal NuttX timer and the
+ NuttX timer provides for higher resolution time. If CONFIG_RTC_HIRES
+ is enabled in the NuttX configuration, then the RTC provides higher
+ resolution time and completely replaces the system timer for purpose of
+ date and time.
+ CONFIG_RTC_FREQUENCY - If CONFIG_RTC_HIRES is defined, then the
+ frequency of the high resolution RTC must be provided. If CONFIG_RTC_HIRES
+ is not defined, CONFIG_RTC_FREQUENCY is assumed to be one.
+ CONFIG_RTC_ALARM - Enable if the RTC hardware supports setting of an alarm.
+ A callback function will be executed when the alarm goes off.
+
+In hi-res mode, the STM32 RTC operates only at 16384Hz. Overflow interrupts
+are handled when the 32-bit RTC counter overflows every 3 days and 43 minutes.
+A BKP register is incremented on each overflow interrupt creating, effectively,
+a 48-bit RTC counter.
+
+In the lo-res mode, the RTC operates at 1Hz. Overflow interrupts are not handled
+(because the next overflow is not expected until the year 2106).
+
+WARNING: Overflow interrupts are lost whenever the STM32 is powered down. The
+overflow interrupt may be lost even if the STM32 is powered down only momentarily.
+Therefore hi-res solution is only useful in systems where the power is always on.
+
+FSMC SRAM
+=========
+
+The 8-Mbit SRAM is connected to the STM32 at PG10 which will be FSMC_NE3, Bank1
+SRAM3. This memory will appear at address 0x68000000.
+
+The on-board SRAM can be configured by setting::
+
+ CONFIG_STM32_FSMC=y : Enables the FSMC
+ CONFIG_STM32_EXTERNAL_RAM=y : Enable external SRAM support
+ CONFIG_HEAP2_BASE=0x68000000 : SRAM will be located at 0x680000000
+ CONFIG_HEAP2_SIZE=1048576 : The size of the SRAM is 1Mbyte
+ CONFIG_MM_REGIONS=2 : There will be two memory regions
+ : in the heap
+
+STM3210E-EVAL-specific Configuration Options
+============================================
+
+..
+ CONFIG_ARCH - Identifies the arch/ subdirectory. This should
+ be set to:
+
+ CONFIG_ARCH=arm
+
+ CONFIG_ARCH_family - For use in C code:
+
+ CONFIG_ARCH_ARM=y
+
+ CONFIG_ARCH_architecture - For use in C code:
+
+ CONFIG_ARCH_CORTEXM3=y
+
+ CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
+
+ CONFIG_ARCH_CHIP=stm32
+
+ CONFIG_ARCH_CHIP_name - For use in C code to identify the exact
+ chip:
+
+ CONFIG_ARCH_CHIP_STM32F103ZE
+
+ CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock
+ configuration features.
+
+ CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n
+
+ CONFIG_ARCH_BOARD - Identifies the boards/ subdirectory and
+ hence, the board that supports the particular chip or SoC.
+
+ CONFIG_ARCH_BOARD=stm3210e_eval (for the STM3210E-EVAL development board)
+
+ CONFIG_ARCH_BOARD_name - For use in C code
+
+ CONFIG_ARCH_BOARD_STM3210E_EVAL=y
+
+ CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
+ of delay loops
+
+ CONFIG_ENDIAN_BIG - define if big endian (default is little
+ endian)
+
+ CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case):
+
+ CONFIG_RAM_SIZE=0x00010000 (64Kb)
+
+ CONFIG_RAM_START - The start address of installed DRAM
+
+ CONFIG_RAM_START=0x20000000
+
+ CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that
+ have LEDs
+
+ CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
+ stack. If defined, this symbol is the size of the interrupt
+ stack in bytes. If not defined, the user task stacks will be
+ used during interrupt handling.
+
+ CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
+
+ CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture.
+
+ Individual subsystems can be enabled:
+ AHB
+ ---
+ CONFIG_STM32_DMA1
+ CONFIG_STM32_DMA2
+ CONFIG_STM32_CRC
+ CONFIG_STM32_FSMC
+ CONFIG_STM32_SDIO
+
+ APB1
+ ----
+ CONFIG_STM32_TIM2
+ CONFIG_STM32_TIM3
+ CONFIG_STM32_TIM4
+ CONFIG_STM32_TIM5
+ CONFIG_STM32_TIM6
+ CONFIG_STM32_TIM7
+ CONFIG_STM32_WWDG
+ CONFIG_STM32_IWDG
+ CONFIG_STM32_SPI2
+ CONFIG_STM32_SPI4
+ CONFIG_STM32_USART2
+ CONFIG_STM32_USART3
+ CONFIG_STM32_UART4
+ CONFIG_STM32_UART5
+ CONFIG_STM32_I2C1
+ CONFIG_STM32_I2C2
+ CONFIG_STM32_USB
+ CONFIG_STM32_CAN1
+ CONFIG_STM32_BKP
+ CONFIG_STM32_PWR
+ CONFIG_STM32_DAC1
+ CONFIG_STM32_DAC2
+ CONFIG_STM32_USB
+
+ APB2
+ ----
+ CONFIG_STM32_ADC1
+ CONFIG_STM32_ADC2
+ CONFIG_STM32_TIM1
+ CONFIG_STM32_SPI1
+ CONFIG_STM32_TIM8
+ CONFIG_STM32_USART1
+ CONFIG_STM32_ADC3
+
+ Timer and I2C devices may need to the following to force power to be applied
+ unconditionally at power up. (Otherwise, the device is powered when it is
+ initialized).
+
+ CONFIG_STM32_FORCEPOWER
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If CONFIG_STM32_TIMn
+ is defined (as above) then the following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation, ADC conversion,
+ or DAC conversion. Note that ADC/DAC require two definition: Not only do you have
+ to assign the timer (n) for used by the ADC or DAC, but then you also have to
+ configure which ADC or DAC (m) it is assigned to.
+
+ CONFIG_STM32_TIMn_PWM Reserve timer n for use by PWM, n=1,..,8
+ CONFIG_STM32_TIMn_ADC Reserve timer n for use by ADC, n=1,..,8
+ CONFIG_STM32_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,8, m=1,..,3
+ CONFIG_STM32_TIMn_DAC Reserve timer n for use by DAC, n=1,..,8
+ CONFIG_STM32_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,8, m=1,..,2
+
+ For each timer that is enabled for PWM usage, we need the following additional
+ configuration settings:
+
+ CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
+
+ NOTE: The STM32 timers are each capable of generating different signals on
+ each of the four channels with different duty cycles. That capability is
+ not supported by this driver: Only one output channel per timer.
+
+ Alternate pin mappings. The STM3210E-EVAL board requires only CAN1 remapping
+ On the STM3210E-EVAL board pin PB9 is wired as TX and pin PB8 is wired as RX.
+ Which then makes the proper connection through the CAN transceiver SN65HVD230
+ out to the CAN D-type 9-pn male connector where pin 2 is CANL and pin 7 is CANH.
+
+ CONFIG_STM32_TIM1_FULL_REMAP
+ CONFIG_STM32_TIM1_PARTIAL_REMAP
+ CONFIG_STM32_TIM2_FULL_REMAP
+ CONFIG_STM32_TIM2_PARTIAL_REMAP_1
+ CONFIG_STM32_TIM2_PARTIAL_REMAP_2
+ CONFIG_STM32_TIM3_FULL_REMAP
+ CONFIG_STM32_TIM3_PARTIAL_REMAP
+ CONFIG_STM32_TIM4_REMAP
+ CONFIG_STM32_USART1_REMAP
+ CONFIG_STM32_USART2_REMAP
+ CONFIG_STM32_USART3_FULL_REMAP
+ CONFIG_STM32_USART3_PARTIAL_REMAP
+ CONFIG_STM32_SPI1_REMAP
+ CONFIG_STM32_SPI3_REMAP
+ CONFIG_STM32_I2C1_REMAP
+ CONFIG_STM32_CAN1_REMAP1
+ CONFIG_STM32_CAN1_REMAP2
+ CONFIG_STM32_CAN2_REMAP
+
+ JTAG Enable settings (by default JTAG-DP and SW-DP are disabled):
+ CONFIG_STM32_JTAG_FULL_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
+ CONFIG_STM32_JTAG_NOJNTRST_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
+ but without JNTRST.
+ CONFIG_STM32_JTAG_SW_ENABLE - Set JTAG-DP disabled and SW-DP enabled
+
+ STM32F103Z specific device driver settings
+
+ CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=1,2,3) or UART
+ m (m=4,5) for the console and ttys0 (default is the USART1).
+ CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received.
+ This specific the size of the receive buffer
+ CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before
+ being sent. This specific the size of the transmit buffer
+ CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be
+ CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8.
+ CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
+ CONFIG_U[S]ARTn_2STOP - Two stop bits
+
+ CONFIG_STM32_SPI_INTERRUPTS - Select to enable interrupt driven SPI
+ support. Non-interrupt-driven, poll-waiting is recommended if the
+ interrupt rate would be to high in the interrupt driven case.
+ CONFIG_STM32_SPIx_DMA - Use DMA to improve SPIx transfer performance.
+ Cannot be used with CONFIG_STM32_SPI_INTERRUPT.
+
+ CONFIG_SDIO_DMA - Support DMA data transfers. Requires CONFIG_STM32_SDIO
+ and CONFIG_STM32_DMA2.
+ CONFIG_STM32_SDIO_PRI - Select SDIO interrupt priority. Default: 128
+ CONFIG_STM32_SDIO_DMAPRIO - Select SDIO DMA interrupt priority.
+ Default: Medium
+ CONFIG_STM32_SDIO_WIDTH_D1_ONLY - Select 1-bit transfer mode. Default:
+ 4-bit transfer mode.
+
+ STM3210E-EVAL CAN Configuration
+
+ CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32_CAN1 or
+ CONFIG_STM32_CAN2 must also be defined)
+ CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. Default
+ Standard 11-bit IDs.
+ CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages.
+ Default: 8
+ CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests.
+ Default: 4
+ CONFIG_CAN_LOOPBACK - A CAN driver may or may not support a loopback
+ mode for testing. The STM32 CAN driver does support loopback mode.
+ CONFIG_STM32_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN1
+ is defined.
+ CONFIG_STM32_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN2
+ is defined.
+ CONFIG_STM32_CAN_TSEG1 - The number of CAN time quanta in segment 1.
+ Default: 6
+ CONFIG_STM32_CAN_TSEG2 - the number of CAN time quanta in segment 2.
+ Default: 7
+ CONFIG_STM32_CAN_REGDEBUG - If CONFIG_DEBUG_FEATURES is set, this will generate an
+ dump of all CAN registers.
+
+ STM3210E-EVAL LCD Hardware Configuration
+
+ CONFIG_LCD_LANDSCAPE - Define for 320x240 display "landscape"
+ support. Default is this 320x240 "landscape" orientation
+ (this setting is informative only... not used).
+ CONFIG_LCD_PORTRAIT - Define for 240x320 display "portrait"
+ orientation support. In this orientation, the STM3210E-EVAL's
+ LCD ribbon cable is at the bottom of the display. Default is
+ 320x240 "landscape" orientation.
+ CONFIG_LCD_RPORTRAIT - Define for 240x320 display "reverse
+ portrait" orientation support. In this orientation, the
+ STM3210E-EVAL's LCD ribbon cable is at the top of the display.
+ Default is 320x240 "landscape" orientation.
+ CONFIG_STM3210E_LCD_BACKLIGHT - Define to support a backlight.
+ CONFIG_STM3210E_LCD_PWM - If CONFIG_STM32_TIM1 is also defined, then an
+ adjustable backlight will be provided using timer 1 to generate
+ various pulse widthes. The granularity of the settings is
+ determined by CONFIG_LCD_MAXPOWER. If CONFIG_STM3210E_LCD_PWM (or
+ CONFIG_STM32_TIM1) is not defined, then a simple on/off backlight
+ is provided.
+ CONFIG_STM3210E_LCD_RDSHIFT - When reading 16-bit gram data, there appears
+ to be a shift in the returned data. This value fixes the offset.
+ Default 5.
+
+ The LCD driver dynamically selects the LCD based on the reported LCD
+ ID value. However, code size can be reduced by suppressing support for
+ individual LCDs using:
+
+ CONFIG_STM3210E_AM240320_DISABLE
+ CONFIG_STM3210E_SPFD5408B_DISABLE
+ CONFIG_STM3210E_R61580_DISABLE
+
+Configurations
+==============
+
+Each STM3210E-EVAL configuration is maintained in a sub-directory and
+can be selected as follow::
+
+ tools/configure.sh stm3210e-eval:<subdir>
+
+Where <subdir> is one of the following:
+
+composite
+---------
+
+This configuration exercises a composite USB interface consisting
+of a CDC/ACM device and a USB mass storage device. This configuration
+uses apps/system/composite.
+
+nsh and nsh2
+------------
+Configure the NuttShell (nsh) located at examples/nsh.
+
+Differences between the two NSH configurations::
+
+ =========== ======================= ================================
+ nsh nsh2
+ =========== ======================= ================================
+ Platform Windows with Cygwin (2) Windows with Cygwin (2)
+ ----------- ----------------------- --------------------------------
+ Toolchain: NuttX buildroot (1) ARM EABI GCC for Windows (1)
+ ----------- ----------------------- --------------------------------
+ Loader: DfuSe DfuSe
+ ----------- ----------------------- --------------------------------
+ Serial Debug output: USART1 Debug output: USART1
+ Console: NSH output: USART1 NSH output: USART1 (3)
+ ----------- ----------------------- --------------------------------
+ I2C No I2C1
+ ----------- ----------------------- --------------------------------
+ microSD Yes Yes
+ Support
+ ----------- ----------------------- --------------------------------
+ FAT FS CONFIG_FAT_LCNAMES=y CONFIG_FAT_LCNAMES=y
+ Config CONFIG_FAT_LFN=n CONFIG_FAT_LFN=y (4)
+ ----------- ----------------------- --------------------------------
+ Support for No Yes
+ Built-in
+ Apps
+ ----------- ----------------------- --------------------------------
+ Built-in None apps/examples/nx
+ Apps apps/examples/nxhello
+ apps/system/usbmsc (5)
+ apps/system/i2c
+ =========== ======================= ================================
+
+ (1) You will probably need to modify PATH environment variable to
+ to include the correct path to the binaries for whichever
+ toolchain you may use.
+ (2) Since DfuSe is assumed, this configuration may only work under
+ Cygwin without modification.
+ (3) When any other device other than /dev/console is used for a user
+ interface, (1) linefeeds (\n) will not be expanded to carriage return
+ / linefeeds \r\n). You will need to configure your terminal program
+ to account for this. And (2) input is not automatically echoed so
+ you will have to turn local echo on.
+ (4) Microsoft holds several patents related to the design of
+ long file names in the FAT file system. Please refer to the
+ details in the top-level NOTICE file. Please do not use FAT
+ long file name unless you are familiar with these patent issues.
+ (5) When built as an NSH add-on command (CONFIG_NSH_BUILTIN_APPS=y),
+ Caution should be used to assure that the SD drive is not in use when
+ the USB storage device is configured. Specifically, the SD driver
+ should be unmounted like:
+
+ nsh> mount -t vfat /dev/mmcsd0 /mnt/sdcard # Card is mounted in NSH
+ ...
+ nsh> umount /mnd/sdcard # Unmount before connecting USB!!!
+ nsh> msconn # Connect the USB storage device
+ ...
+ nsh> msdis # Disconnect USB storate device
+ nsh> mount -t vfat /dev/mmcsd0 /mnt/sdcard # Restore the mount
+
+ Failure to do this could result in corruption of the SD card format.
+
+ 1. Both configurations use the mconf-based configuration tool. To
+ change these configurations using that tool, you should:
+
+ a. Build and install the kconfig-mconf tool. See nuttx/README.txt
+ see additional README.txt files in the NuttX tools repository.
+
+ b. Execute 'make menuconfig' in nuttx/ in order to start the
+ reconfiguration process.
+
+ 2. The nsh2 contains support for some built-in applications that can be
+ enabled by make some additional minor changes:
+
+ a. examples/can. The CAN test example can be enabled by changing the
+ following settings in nsh2/defconfig:
+
+ CONFIG_CAN=y : Enable CAN "upper-half" driver support
+ CONFIG_STM32_CAN1=y : Enable STM32 CAN1 "lower-half" driver support
+
+ The default CAN settings may need to change in your board board
+ configuration:
+
+ CONFIG_CAN_EXTID=y : Support extended IDs
+ CONFIG_STM32_CAN1_BAUD=250000 : Bit rate: 250 KHz
+ CONFIG_STM32_CAN_TSEG1=12 : 80% sample point
+ CONFIG_STM32_CAN_TSEG2=3
+
+nx
+---
+
+An example using the NuttX graphics system (NX). This example
+focuses on general window controls, movement, mouse and keyboard
+input.::
+
+ CONFIG_ARM_TOOLCHAIN_GNU_EABI=y : GNU EABI toolchain for Windows
+ CONFIG_LCD_RPORTRAIT=y : 240x320 reverse portrait
+
+NOTES:
+
+1. This configuration uses the mconf-based configuration tool. To
+ change this configurations using that tool, you should:
+
+ a. Build and install the kconfig-mconf tool. See nuttx/README.txt
+ see additional README.txt files in the NuttX tools repository.
+
+ b. Execute 'make menuconfig' in nuttx/ in order to start the
+ reconfiguration process.
+
+2. If you configured the multi-used NX server (which is disabled
+ by default), then you would also need::
+
+ CONFIG_EXAMPLES_NX_CLIENTPRIO=80
+ CONFIG_EXAMPLES_NX_SERVERPRIO=120
+ CONFIG_EXAMPLES_NX_STACKSIZE=2048
+
+3. This example provides a framework for a number of other standalone
+ graphics tests.
+
+ a. apps/examples/nxlines: The NXLINES graphic example illustrates
+ drawing of fat lines in various orientations. You can modify
+ this configuration so to support the NXLINES example by making
+ the following modifications to the NuttX configuration file:
+
+ Provide the new start-up entry point:
+
+ CONFIG_INIT_ENTRYPOINT="nxlines_main"
+
+ Disable apps/examples/nx:
+
+ CONFIG_EXAMPLES_NX=n
+
+ Enable and configure apps/nxlines/nxlines:
+
+ CONFIG_EXAMPLES_NXLINES=y
+ CONFIG_EXAMPLES_NXLINES_VPLANE=0
+ CONFIG_EXAMPLES_NXLINES_DEVNO=0
+ CONFIG_EXAMPLES_NXLINES_DEFAULT_COLORS=n
+ CONFIG_EXAMPLES_NXLINES_BGCOLOR=0x0320
+ CONFIG_EXAMPLES_NXLINES_LINEWIDTH=16
+ CONFIG_EXAMPLES_NXLINES_LINECOLOR=0xffe0
+ CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=4
+ CONFIG_EXAMPLES_NXLINES_BORDERCOLOR=0xffe0
+ CONFIG_EXAMPLES_NXLINES_CIRCLECOLOR=0xf7bb
+ CONFIG_EXAMPLES_NXLINES_BPP=16
+ CONFIG_EXAMPLES_NXLINES_EXTERNINIT=n
+
+ b. apps/examples/nxtext: Another example using the NuttX graphics
+ system (NX). This example focuses on placing text on the
+ background while pop-up windows occur. Text should continue to
+ update normally with or without the popup windows present.
+
+ You can modify this configuration so to support the NXLINES
+ example by making the following modifications to the NuttX
+ configuration file:
+
+ Provide the new start-up entry point::
+
+ CONFIG_INIT_ENTRYPOINT="nxtext_main"
+
+ Disable apps/examples/nx::
+
+ CONFIG_EXAMPLES_NX=n
+
+ Enable an NX font::
+
+ CONFIG_NXFONT_SERIF22X28B=y
+
+ Enable and configure apps/nxlines/nxtext::
+
+ CONFIG_EXAMPLES_NXTEXT=y
+ CONFIG_EXAMPLES_NXTEXT_VPLANE=0
+ CONFIG_EXAMPLES_NXTEXT_DEVNO=0
+ CONFIG_EXAMPLES_NXTEXT_BPP=16
+ CONFIG_EXAMPLES_NXTEXT_BMCACHE=512
+ CONFIG_EXAMPLES_NXTEXT_GLCACHE=16
+ CONFIG_EXAMPLES_NXTEXT_DEFAULT_COLORS=n
+ CONFIG_EXAMPLES_NXTEXT_BGCOLOR=0x0011
+ CONFIG_EXAMPLES_NXTEXT_BGFONTCOLOR=0xffdf
+ CONFIG_EXAMPLES_NXTEXT_PUCOLOR=0xfd20
+ CONFIG_EXAMPLES_NXTEXT_PUFONTCOLOR=0x001f
+ CONFIG_EXAMPLES_NXTEXT_DEFAULT_FONT=n
+ CONFIG_EXAMPLES_NXTEXT_BGFONTID=11
+ CONFIG_EXAMPLES_NXTEXT_PUFONTID=1
+ CONFIG_EXAMPLES_NXTEXT_EXTERNINIT=n
+
+ If you configured the multi-used NX server (which is disabled
+ by default), then you would also need::
+
+ CONFIG_EXAMPLES_NXTEXT_STACKSIZE=2048
+ CONFIG_EXAMPLES_NXTEXT_CLIENTPRIO=80
+ CONFIG_EXAMPLES_NXTEXT_SERVERPRIO=120
+
+ c. Others could be similar configured: apps/examples/nxhello,
+ nximage, ...
+
+ 4. The nsh configuration was used to verify the discrete joystick
+ (DJoystick driver). If you would like to duplicate this test, below
+ are the configuration changes needed to setup the DJoystick driver
+ (see nuttx/drivers/input/djoystick.c) and the DJoystick test (see
+ apps/examples/djoystick)::
+
+ Pre-requisites:
+
+ CONFIG_BUILTIN=y # Enable support for built-in applications
+ CONFIG_NSH_BUILTIN_APPS=y # Enable NSH built-in applications
+
+ Enable the DJoystick driver:
+
+ CONFIG_INPUT=y # Enable input driver support
+ CONFIG_INPUT_DJOYSTICK=y # Enable the joystick drivers
+ # (default parameters should be okay)
+ Enable the DJoystick Example:
+
+ CONFIG_EXAMPLES_DJOYSTICK=y # Enable the DJoystick example
+ CONFIG_EXAMPLES_DJOYSTICK_DEVNAME="/dev/djoy0"
+
+ When running the configuration, you should see the built-in
+ application 'djoy'. Just type 'djoy' at the NSH command prompt.
+
+nxterm
+------
+
+This is yet another NSH configuration. This NSH configuration differs
+from the other, however, in that it uses the NxTerm driver to host
+the NSH shell.
+
+NOTES:
+
+1. This configuration uses the mconf-based configuration tool. To
+ change this configurations using that tool, you should:
+
+ a. Build and install the kconfig-mconf tool. See nuttx/README.txt
+ see additional README.txt files in the NuttX tools repository.
+
+ b. Execute 'make menuconfig' in nuttx/ in order to start the
+ reconfiguration process.
+
+2. Some of the differences in this configuration include these settings
+ in the defconfig file:
+
+ These select NX Multi-User mode::
+
+ CONFG_NX_MULTIUSER=y
+ CONFIG_DISABLE_MQUEUE=n
+
+ The following definition in the defconfig file to enables the NxTerm
+ driver::
+
+ CONFIG_NXTERM=y
+
+ And this selects apps/examples/nxterm instead of apps/examples/nsh::
+
+ CONFIG_EXAMPLES_NXTERM=y
+
+ Other configuration settings of interest::
+
+ CONFIG_HOST_WINDOWS=y : Windows
+ CONFIG_WINDOWS_CYGWIN=y : with Cygwin
+ CONFIG_ARM_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin
+ CONFIG_LCD_LANDSCAPE=y : 320x240 landscape
+
+pm
+--
+
+This is a configuration that is used to test STM32 power management, i.e.,
+to test that the board can go into lower and lower states of power usage
+as a result of inactivity. This configuration is based on the nsh2
+configuration with modifications for testing power management. This
+configuration should provide some guideline for power management in your
+STM32 application.
+
+NOTES:
+
+1. This configuration uses the mconf-based configuration tool. To
+ change this configurations using that tool, you should:
+
+ a. Build and install the kconfig-mconf tool. See nuttx/README.txt
+ see additional README.txt files in the NuttX tools repository.
+
+ b. Execute 'make menuconfig' in nuttx/ in order to start the
+ reconfiguration process.
+
+2. Default configuration is Cygwin under windows using the ARM EABI
+ toolchain::
+
+ CONFIG_HOST_WINDOWS=y : Windows
+ CONFIG_WINDOWS_CYGWIN=y : Cygwin
+ CONFIG_ARM_TOOLCHAIN_GNU_EABI=y : GNU EABI toolchain for Windows
+
+3. CONFIG_ARCH_CUSTOM_PMINIT and CONFIG_ARCH_IDLE_CUSTOM are necessary
+ parts of the PM configuration::
+
+ CONFIG_ARCH_CUSTOM_PMINIT=y
+
+ CONFIG_ARCH_CUSTOM_PMINIT moves the PM initialization from
+ arch/arm/src/stm32/stm32_pminitialiaze.c to boards/arm/stm32/stm3210-eval/src/stm32_pm.c.
+ This allows us to support board-specific PM initialization.::
+
+ CONFIG_ARCH_IDLE_CUSTOM=y
+
+ The bulk of the PM activities occur in the IDLE loop. The IDLE loop
+ is special because it is what runs when there is no other task running.
+ Therefore when the IDLE executes, we can be assure that nothing else
+ is going on; this is the ideal condition for doing reduced power
+ management.
+
+ The configuration CONFIG_ARCH_IDLE_CUSTOM allows us to "steal" the
+ normal STM32 IDLE loop (of arch/arm/src/stm32/stm32_idle.c) and replace
+ this with our own custom IDLE loop (at boards/arm/stm32/stm3210-eval/src/up_idle.c).
+
+4. Here are some additional things to note in the configuration::
+
+ CONFIG_PM_BUTTONS=y
+
+ CONFIG_PM_BUTTONS enables button support for PM testing. Buttons can
+ drive EXTI interrupts and EXTI interrupts can be used to wakeup for
+ certain reduced power modes (STOP mode). The use of the buttons here
+ is for PM testing purposes only; buttons would normally be part the
+ application code and CONFIG_PM_BUTTONS would not be defined.::
+
+ CONFIG_RTC_ALARM=y
+
+ The RTC alarm is used to wake up from STOP mode and to transition to
+ STANDBY mode. This used of the RTC alarm could conflict with other
+ uses of the RTC alarm in your application.
+
+usbserial
+---------
+
+This configuration directory exercises the USB serial class
+driver at examples/usbserial. See examples/README.txt for
+more information.::
+
+ CONFIG_ARM_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin
+
+USB debug output can be enabled as by changing the following
+settings in the configuration file::
+
+ -CONFIG_DEBUG_FEATURES=n
+ -CONFIG_DEBUG_INFO=n
+ -CONFIG_DEBUG_USB=n
+ +CONFIG_DEBUG_FEATURES=y
+ +CONFIG_DEBUG_INFO=y
+ +CONFIG_DEBUG_USB=y
+
+ -CONFIG_EXAMPLES_USBSERIAL_TRACEINIT=n
+ -CONFIG_EXAMPLES_USBSERIAL_TRACECLASS=n
+ -CONFIG_EXAMPLES_USBSERIAL_TRACETRANSFERS=n
+ -CONFIG_EXAMPLES_USBSERIAL_TRACECONTROLLER=n
+ -CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n
+ +CONFIG_EXAMPLES_USBSERIAL_TRACEINIT=y
+ +CONFIG_EXAMPLES_USBSERIAL_TRACECLASS=y
+ +CONFIG_EXAMPLES_USBSERIAL_TRACETRANSFERS=y
+ +CONFIG_EXAMPLES_USBSERIAL_TRACECONTROLLER=y
+ +CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=y
+
+By default, the usbserial example uses the Prolific PL2303
+serial/USB converter emulation. The example can be modified
+to use the CDC/ACM serial class by making the following changes
+to the configuration file::
+
+ -CONFIG_PL2303=y
+ +CONFIG_PL2303=n
+
+ -CONFIG_CDCACM=n
+ +CONFIG_CDCACM=y
+
+The example can also be converted to use the alternative
+USB serial example at apps/examples/usbterm by changing the
+following::
+
+ -CONFIG_EXAMPLES_USBSERIAL=y
+ +CONFIG_EXAMPLES_USBSERIAL=n
+
+usbmsc
+------
+
+This configuration directory exercises the USB mass storage
+class driver at system/usbmsc. See examples/README.txt for
+more information.
+
+NOTES:
+
+1. This configuration uses the mconf-based configuration tool. To
+ change this configurations using that tool, you should:
+
+ a. Build and install the kconfig-mconf tool. See nuttx/README.txt
+ see additional README.txt files in the NuttX tools repository.
+
+ b. Execute 'make menuconfig' in nuttx/ in order to start the
+ reconfiguration process.
+
+2. Build environment (can be easily reconfigured)::
+
+ CONFIG_HOST_LINUX=y : Linux (or Cygwin)
+ CONFIG_ARM_TOOLCHAIN_BUILDROOT=y : NuttX buildroot under Linux or Cygwin
diff --git a/content/docs/latest/_sources/platforms/arm/stm32f1/boards/stm32_tiny/index.rst.txt b/content/docs/latest/_sources/platforms/arm/stm32f1/boards/stm32_tiny/index.rst.txt
new file mode 100644
index 00000000..6f3f251b
--- /dev/null
+++ b/content/docs/latest/_sources/platforms/arm/stm32f1/boards/stm32_tiny/index.rst.txt
@@ -0,0 +1,456 @@
+==========
+STM32 Tiny
+==========
+
+This README discusses issues unique to NuttX configurations for the
+STM32 Tiny development board.
+
+This board is available from several vendors on the net, and may
+be sold under different names. It is based on a STM32 F103C8T6 MCU, and
+is (always ?) bundled with a nRF24L01 wireless communication module.
+
+Contents
+========
+
+ - LEDs
+ - PWM
+ - UARTs
+ - Timer Inputs/Outputs
+ - STM32 Tiny -specific Configuration Options
+ - Configurations
+
+LEDs
+====
+
+The STM32Tiny board has only one software controllable LED.
+This LED can be used by the board port when CONFIG_ARCH_LEDS option is
+enabled.
+
+If enabled the LED is simply turned on when the board boots
+successfully, and is blinking on panic / assertion failed.
+
+PWM
+===
+
+The STM32 Tiny has no real on-board PWM devices, but the board can be
+configured to output a pulse train using TIM3 CH2 on the GPIO line B.5
+(connected to the LED).
+Please note that the CONFIG_STM32_TIM3_PARTIAL_REMAP option must be enabled
+in this case.
+
+UARTs
+=====
+
+UART/USART PINS
+---------------
+
+::
+
+ USART1
+ RX PA10
+ TX PA9
+ USART2
+ CK PA4
+ CTS PA0*
+ RTS PA1
+ RX PA3
+ TX PA2
+ USART3
+ CK PB12*
+ CTS PB13*
+ RTS PB14*
+ RX PB11
+ TX PB10
+
+* these IO lines are intended to be used by the wireless module on the board.
+
+Default USART/UART Configuration
+--------------------------------
+
+USART1 (RX & TX only) is available through the RS-232 port on the board. A MAX232 chip converts
+voltage to RS-232 level. This serial port can be used to flash a firmware using the boot loader
+integrated in the MCU.
+
+Timer Inputs/Outputs
+====================
+
+TIM1
+ CH1 PA8
+ CH2 PA9*
+ CH3 PA10*
+ CH4 PA11*
+TIM2
+ CH1 PA0*, PA15, PA5
+ CH2 PA1, PB3
+ CH3 PA2, PB10*
+ CH4 PA3, PB11
+TIM3
+ CH1 PA6, PB4
+ CH2 PA7, PB5*
+ CH3 PB0
+ CH4 PB1*
+TIM4
+ CH1 PB6*
+ CH2 PB7
+ CH3 PB8
+ CH4 PB9*
+
+ * Indicates pins that have other on-board functions and should be used only
+ with care (See board datasheet).
+
+STM32 Tiny - specific Configuration Options
+===============================================
+
+
+ ..
+ CONFIG_ARCH - Identifies the arch/ subdirectory. This should
+ be set to:
+
+ CONFIG_ARCH=arm
+
+ CONFIG_ARCH_family - For use in C code:
+
+ CONFIG_ARCH_ARM=y
+
+ CONFIG_ARCH_architecture - For use in C code:
+
+ CONFIG_ARCH_CORTEXM3=y
+
+ CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
+
+ CONFIG_ARCH_CHIP=stm32
+
+ CONFIG_ARCH_CHIP_name - For use in C code to identify the exact
+ chip:
+
+ CONFIG_ARCH_CHIP_STM32F103C8=y
+
+ CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock
+ configuration features.
+
+ CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n
+
+ CONFIG_ARCH_BOARD - Identifies the boards/ subdirectory and
+ hence, the board that supports the particular chip or SoC.
+
+ CONFIG_ARCH_BOARD=stm32_tiny
+
+ CONFIG_ARCH_BOARD_name - For use in C code
+
+ CONFIG_ARCH_BOARD_STM32_TINY=y
+
+ CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
+ of delay loops
+
+ CONFIG_ENDIAN_BIG - define if big endian (default is little
+ endian)
+
+ CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case):
+
+ CONFIG_RAM_SIZE=20480 (20Kb)
+
+ CONFIG_RAM_START - The start address of installed DRAM
+
+ CONFIG_RAM_START=0x20000000
+
+ CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that
+ have LEDs
+
+ CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
+ stack. If defined, this symbol is the size of the interrupt
+ stack in bytes. If not defined, the user task stacks will be
+ used during interrupt handling.
+
+ CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
+
+ ..
+ Individual subsystems can be enabled:
+
+ AHB
+ ---
+ CONFIG_STM32_CRC
+ CONFIG_STM32_BKPSRAM
+
+ APB1
+ ----
+ CONFIG_STM32_TIM2
+ CONFIG_STM32_TIM3
+ CONFIG_STM32_TIM4
+ CONFIG_STM32_WWDG
+ CONFIG_STM32_IWDG
+ CONFIG_STM32_SPI2
+ CONFIG_STM32_USART2
+ CONFIG_STM32_USART3
+ CONFIG_STM32_I2C1
+ CONFIG_STM32_I2C2
+ CONFIG_STM32_CAN1
+ CONFIG_STM32_PWR -- Required for RTC
+
+ APB2
+ ----
+ CONFIG_STM32_TIM1
+ CONFIG_STM32_USART1
+ CONFIG_STM32_ADC1
+ CONFIG_STM32_ADC2
+ CONFIG_STM32_SPI1
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If CONFIG_STM32_TIMn
+ is defined (as above) then the following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation or ADC conversion.
+ Note that ADC require two definitions: Not only do you have
+ to assign the timer (n) for used by the ADC, but then you also have to
+ configure which ADC (m) it is assigned to.
+
+ CONFIG_STM32_TIMn_PWM Reserve timer n for use by PWM, n=1,..,14
+ CONFIG_STM32_TIMn_ADC Reserve timer n for use by ADC, n=1,..,14
+ CONFIG_STM32_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,14, m=1,..,3
+
+ For each timer that is enabled for PWM usage, we need the following additional
+ configuration settings:
+
+ CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
+
+ NOTE: The STM32 timers are each capable of generating different signals on
+ each of the four channels with different duty cycles. That capability is
+ not supported by this driver: Only one output channel per timer.
+
+ JTAG Enable settings (by default only SW-DP is enabled):
+
+ CONFIG_STM32_JTAG_FULL_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
+ CONFIG_STM32_JTAG_NOJNTRST_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
+ but without JNTRST.
+ CONFIG_STM32_JTAG_SW_ENABLE - Set JTAG-DP disabled and SW-DP enabled
+
+ STM32Tiny specific device driver settings
+
+ CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=1,2,3)
+ for the console and ttys0 (default is the USART1).
+ CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received.
+ This specific the size of the receive buffer
+ CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before
+ being sent. This specific the size of the transmit buffer
+ CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be
+ CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8.
+ CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
+ CONFIG_U[S]ARTn_2STOP - Two stop bits
+
+ STM32Tiny CAN Configuration
+
+ CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32_CAN1 or
+ CONFIG_STM32_CAN2 must also be defined)
+ CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. Default
+ Standard 11-bit IDs.
+ CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages.
+ Default: 8
+ CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests.
+ Default: 4
+ CONFIG_CAN_LOOPBACK - A CAN driver may or may not support a loopback
+ mode for testing. The STM32 CAN driver does support loopback mode.
+ CONFIG_STM32_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN1
+ is defined.
+ CONFIG_STM32_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN2
+ is defined.
+ CONFIG_STM32_CAN_TSEG1 - The number of CAN time quanta in segment 1.
+ Default: 6
+ CONFIG_STM32_CAN_TSEG2 - the number of CAN time quanta in segment 2.
+ Default: 7
+ CONFIG_STM32_CAN_REGDEBUG - If CONFIG_DEBUG_FEATURES is set, this will generate an
+ dump of all CAN registers.
+
+ STM32Tiny SPI Configuration
+
+ CONFIG_STM32_SPI_INTERRUPTS - Select to enable interrupt driven SPI
+ support. Non-interrupt-driven, poll-waiting is recommended if the
+ interrupt rate would be to high in the interrupt driven case.
+ CONFIG_STM32_SPIx_DMA - Use DMA to improve SPIx transfer performance.
+ Cannot be used with CONFIG_STM32_SPI_INTERRUPT.
+
+Configurations
+==============
+
+Each STM32Tiny configuration is maintained in a sub-directory and
+can be selected as follow:
+
+ tools/configure.sh STM32Tiny:<subdir>
+
+Where <subdir> is one of the following:
+
+nsh
+---
+
+Configures the NuttShell (nsh) located at apps/examples/nsh. This
+configuration enables a console on UART1. Support for
+builtin applications is enabled, but in the base configuration no
+builtin applications are selected (see NOTES below).
+
+NOTES:
+
+ ..
+ 1. This configuration uses the mconf-based configuration tool. To
+ change this configuration using that tool, you should:
+
+ a. Build and install the kconfig-mconf tool. See nuttx/README.txt
+ see additional README.txt files in the NuttX tools repository.
+
+ b. Execute 'make menuconfig' in nuttx/ in order to start the
+ reconfiguration process.
+
+ 2. By default, this configuration uses the ARM EABI toolchain
+ for Windows and builds under Cygwin (or probably MSYS). That
+ can easily be reconfigured, of course.
+
+ CONFIG_HOST_WINDOWS=y : Builds under Windows
+ CONFIG_WINDOWS_CYGWIN=y : Using Cygwin
+ CONFIG_ARM_TOOLCHAIN_GNU_EABI=y : GNU EABI toolchain for Windows
+
+ 3. This example supports the PWM test (apps/examples/pwm) but this must
+ be manually enabled by selecting:
+
+ CONFIG_PWM=y : Enable the generic PWM infrastructure
+ CONFIG_STM32_TIM3=y : Enable TIM3
+ CONFIG_STM32_TIM3_PWM=y : Use TIM3 to generate PWM output
+ CONFIG_STM32_TIM3_PARTIAL_REMAP=y : Required to have the port B5 as timer PWM output (channel 2)
+ CONFIG_STM32_TIM3_CHANNEL=2
+
+ See also apps/examples/README.txt
+
+ Note that the only supported board configuration uses the board LED as PWM output.
+
+ Special PWM-only debug options:
+
+ CONFIG_DEBUG_PWM_INFO
+
+ 7. USB Support (CDC/ACM device)
+
+ CONFIG_STM32_OTGFS=y : STM32 OTG FS support
+ CONFIG_USBDEV=y : USB device support must be enabled
+ CONFIG_CDCACM=y : The CDC/ACM driver must be built
+ CONFIG_NSH_BUILTIN_APPS=y : NSH built-in application support must be enabled
+ CONFIG_NSH_ARCHINIT=y : To perform USB initialization
+
+ 8. Using the USB console.
+
+ The STM32Tiny NSH configuration can be set up to use a USB CDC/ACM
+ (or PL2303) USB console. The normal way that you would configure the
+ the USB console would be to change the .config file like this:
+
+ CONFIG_STM32_OTGFS=y : STM32 OTG FS support
+ CONFIG_USART2_SERIAL_CONSOLE=n : Disable the USART2 console
+ CONFIG_DEV_CONSOLE=n : Inhibit use of /dev/console by other logic
+ CONFIG_USBDEV=y : USB device support must be enabled
+ CONFIG_CDCACM=y : The CDC/ACM driver must be built
+ CONFIG_CDCACM_CONSOLE=y : Enable the CDC/ACM USB console.
+
+ NOTE: When you first start the USB console, you have hit ENTER a few
+ times before NSH starts. The logic does this to prevent sending USB data
+ before there is anything on the host side listening for USB serial input.
+
+ 9. Here is an alternative USB console configuration. The following
+ configuration will also create a NSH USB console but this version
+ will use /dev/console. Instead, it will use the normal /dev/ttyACM0
+ USB serial device for the console:
+
+ CONFIG_STM32_OTGFS=y : STM32 OTG FS support
+ CONFIG_USART2_SERIAL_CONSOLE=y : Keep the USART2 console
+ CONFIG_DEV_CONSOLE=y : /dev/console exists (but NSH won't use it)
+ CONFIG_USBDEV=y : USB device support must be enabled
+ CONFIG_CDCACM=y : The CDC/ACM driver must be built
+ CONFIG_CDCACM_CONSOLE=n : Don't use the CDC/ACM USB console.
+ CONFIG_NSH_USBCONSOLE=y : Instead use some other USB device for the console
+
+ The particular USB device that is used is:
+
+ CONFIG_NSH_USBCONDEV="/dev/ttyACM0"
+
+ The advantage of this configuration is only that it is easier to
+ bet working. This alternative does has some side effects:
+
+ - When any other device other than /dev/console is used for a user
+ interface, linefeeds (\n) will not be expanded to carriage return /
+ linefeeds (\r\n). You will need to set your terminal program to account
+ for this.
+
+ - /dev/console still exists and still refers to the serial port. So
+ you can still use certain kinds of debug output (see include/debug.h, all
+ of the debug output from interrupt handlers will be lost.
+
+ - But don't enable USB debug output! Since USB is console is used for
+ USB debug output and you are using a USB console, there will be
+ infinite loops and deadlocks: Debug output generates USB debug
+ output which generatates USB debug output, etc. If you want USB
+ debug output, you should consider enabling USB trace
+ (CONFIG_USBDEV_TRACE) and perhaps the USB monitor (CONFIG_USBMONITOR).
+
+ See the usbnsh configuration below for more information on configuring
+ USB trace output and the USB monitor.
+
+usbnsh
+------
+
+This is another NSH example. If differs from other 'nsh' configurations
+in that this configurations uses a USB serial device for console I/O.
+
+NOTES:
+
+ ..
+ 1. This configuration uses the mconf-based configuration tool. To
+ change this configuration using that tool, you should:
+
+ a. Build and install the kconfig-mconf tool. See nuttx/README.txt
+ see additional README.txt files in the NuttX tools repository.
+
+ b. Execute 'make menuconfig' in nuttx/ in order to start the
+ reconfiguration process.
+
+ 2. By default, this configuration uses the ARM EABI toolchain
+ for Windows and builds under Cygwin (or probably MSYS). That
+ can easily be reconfigured, of course.
+
+ CONFIG_HOST_WINDOWS=y : Builds under Windows
+ CONFIG_WINDOWS_CYGWIN=y : Using Cygwin
+ CONFIG_ARM_TOOLCHAIN_GNU_EABI=y : GNU EABI toolchain for Windows
+
+ 3. This configuration does have UART2 output enabled and set up as
+ the system logging device:
+
+ CONFIG_SYSLOG_CHAR=y : Use a character device for system logging
+ CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" : UART2 will be /dev/ttyS0
+
+ However, there is nothing to generate SYSLOG output in the default
+ configuration so nothing should appear on UART2 unless you enable
+ some debug output or enable the USB monitor.
+
+ 4. Enabling USB monitor SYSLOG output. If tracing is enabled, the USB
+ device will save encoded trace output in in-memory buffer; if the
+ USB monitor is enabled, that trace buffer will be periodically
+ emptied and dumped to the system logging device (UART2 in this
+ configuration):
+
+ CONFIG_USBDEV_TRACE=y : Enable USB trace feature
+ CONFIG_USBDEV_TRACE_NRECORDS=128 : Buffer 128 records in memory
+ CONFIG_NSH_USBDEV_TRACE=n : No builtin tracing from NSH
+ CONFIG_NSH_ARCHINIT=y : Automatically start the USB monitor
+ CONFIG_USBMONITOR=y : Enable the USB monitor daemon
+ CONFIG_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size
+ CONFIG_USBMONITOR_PRIORITY=50 : USB monitor daemon priority
+ CONFIG_USBMONITOR_INTERVAL=2 : Dump trace data every 2 seconds
+
+ CONFIG_USBMONITOR_TRACEINIT=y : Enable TRACE output
+ CONFIG_USBMONITOR_TRACECLASS=y
+ CONFIG_USBMONITOR_TRACETRANSFERS=y
+ CONFIG_USBMONITOR_TRACECONTROLLER=y
+ CONFIG_USBMONITOR_TRACEINTERRUPTS=y
+
+ 5. By default, this project assumes that you are *NOT* using the DFU
+ bootloader.
+
+ Using the Prolifics PL2303 Emulation
+ ------------------------------------
+ You could also use the non-standard PL2303 serial device instead of
+ the standard CDC/ACM serial device by changing:
+
+ CONFIG_CDCACM=y : Disable the CDC/ACM serial device class
+ CONFIG_CDCACM_CONSOLE=y : The CDC/ACM serial device is NOT the console
+ CONFIG_PL2303=y : The Prolifics PL2303 emulation is enabled
+ CONFIG_PL2303_CONSOLE=y : The PL2303 serial device is the console
diff --git a/content/docs/latest/_sources/platforms/arm/stm32f1/boards/stm32butterfly2/index.rst.txt b/content/docs/latest/_sources/platforms/arm/stm32f1/boards/stm32butterfly2/index.rst.txt
new file mode 100644
index 00000000..07b0291f
--- /dev/null
+++ b/content/docs/latest/_sources/platforms/arm/stm32f1/boards/stm32butterfly2/index.rst.txt
@@ -0,0 +1,3 @@
+===============
+STM32BUTTERFLY2
+===============
diff --git a/content/docs/latest/_sources/platforms/arm/stm32f1/boards/stm32f103-minimum/index.rst.txt b/content/docs/latest/_sources/platforms/arm/stm32f1/boards/stm32f103-minimum/index.rst.txt
new file mode 100644
index 00000000..b9bec1a8
--- /dev/null
+++ b/content/docs/latest/_sources/platforms/arm/stm32f1/boards/stm32f103-minimum/index.rst.txt
@@ -0,0 +1,882 @@
+=================
+stm32f103-minimum
+=================
+
+This README discusses issues unique to NuttX configurations for the
+STM32F103C8T6 Minimum System Development Board for ARM Microcontroller.
+
+STM32F103C8T6 Minimum System Development Boards:
+================================================
+
+This STM32F103C8T6 minimum system development board is available from
+several vendors on the net, and may be sold under different names or
+no name at all. It is based on a STM32F103C8T6 and has a DIP-40 form-
+factor.
+
+There are four versions of very similar boards: Red, Blue, RoboDyn Black and
+Black.
+See: https://wiki.stm32duino.com/index.php?title=Blue_Pill
+https://wiki.stm32duino.com/index.php?title=Red_Pill
+https://wiki.stm32duino.com/index.php?title=RobotDyn_Black_Pill
+https://wiki.stm32duino.com/index.php?title=Black_Pill
+
+The Red Board:
+
+Good things about the red board:
+
+- 1.5k pull up resistor on the PA12 pin (USB D+) which you can
+ programmatically drag down for automated USB reset.
+- large power capacitors and LDO power.
+- User LED on PC13
+
+Problems with the red board:
+
+- Silk screen is barely readable, the text is chopped off on some of
+ the pins
+- USB connector only has two anchor points and it is directly soldered
+ on the surface
+- Small reset button with hardly any resistance
+
+The Blue Board:
+
+Good things about the blue board:
+
+- Four soldered anchor point on the USB connector. What you can't tell
+ from this picture is that there is a notch in the PCB board and the USB
+ connector sits down inside it some. This provides some lateral stability
+ that takes some of the stress off the solder points.
+- It has nice clear readable silkscreen printing.
+- It also a larger reset button.
+- User LED on PC13
+
+Problems with the blue board:
+
+- Probably won't work as a USB device if it has a 10k pull-up on PA12. You
+ have to check the pull up on PA12 (USB D+). If it has a 10k pull-up
+ resistor, you will need to replace it with a 1.5k one to use the native
+ USB.
+- Puny voltage regulator probably 100mA.
+
+A schematic for the blue board is available here:
+http://www.stm32duino.com/download/file.php?id=276
+
+The Black Board:
+
+- User LED is on PB12.
+- Mounting holes.
+
+Both Boards:
+
+Nice features common to both:
+
+- SWD pins broken out and easily connected (VCC, GND, SWDIO, SWCLK)
+- USB 5V is broken out with easy access.
+- Power LED
+- You can probably use more flash (128k) than officially documented for
+ the chip (stm32f103c8t6 64k), I was able to load 115k of flash on mine
+ and it seemed to work.
+
+Problems with both boards:
+
+- No preloaded bootloader (this isn't really a problem as the
+ entire 64k of flash is available for use)
+- No user button
+
+This is the board pinout based on its form-factor for the Blue board:
+
+..
+ USB
+ ___
+ -----/ _ \-----
+ |B12 GND|
+ |B13 GND|
+ |B14 3.3V|
+ |B15 RST|
+ |A8 B11|
+ |A9 B10|
+ |A10 B1|
+ |A11 B0|
+ |A12 A7|
+ |A15 A6|
+ |B3 A5|
+ |B4 A4|
+ |B5 A3|
+ |B6 A2|
+ |B7 A1|
+ |B8 A0|
+ |B9 C15|
+ |5V C14|
+ |GND C13|
+ |3.3V VB|
+ |_____________|
+
+LEDs
+====
+
+The STM32F103 Minimum board has only one software controllable LED.
+This LED can be used by the board port when CONFIG_ARCH_LEDS option is
+enabled.
+
+If enabled the LED is simply turned on when the board boots
+successfully, and is blinking on panic / assertion failed.
+
+UARTs
+=====
+
+UART/USART PINS
+---------------
+
+ ..
+ USART1
+ RX PA10
+ TX PA9
+ USART2
+ CK PA4
+ CTS PA0
+ RTS PA1
+ RX PA3
+ TX PA2
+ USART3
+ CK PB12
+ CTS PB13
+ RTS PB14
+ RX PB11
+ TX PB10
+
+Default USART/UART Configuration
+--------------------------------
+
+USART1 (RX & TX only) is available through pins PA9 (TX) and PA10 (RX).
+
+Timer Inputs/Outputs
+====================
+
+ ..
+ TIM1
+ CH1 PA8
+ CH2 PA9*
+ CH3 PA10*
+ CH4 PA11*
+ TIM2
+ CH1 PA0*, PA15, PA5
+ CH2 PA1, PB3
+ CH3 PA2, PB10*
+ CH4 PA3, PB11
+ TIM3
+ CH1 PA6, PB4
+ CH2 PA7, PB5*
+ CH3 PB0
+ CH4 PB1*
+ TIM4
+ CH1 PB6*
+ CH2 PB7
+ CH3 PB8
+ CH4 PB9*
+
+ * Indicates pins that have other on-board functions and should be used only
+ with care (See board datasheet).
+
+Using 128KiB of Flash instead of 64KiB
+======================================
+
+Some people figured out that the STM32F103C8T6 has 128KiB of internal memory
+instead of 64KiB as documented in the datasheet and reported by its internal
+register.
+
+In order to enable 128KiB you need modify the linker script to reflect this
+new size. Open the boards/arm/stm32/stm32f103-minimum/scripts/ld.script and replace::
+
+ flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K
+
+with::
+
+ flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K
+
+Enable many NuttX features (ie. many filesystems and applications) to get a
+large binary image with more than 64K.
+
+We will use OpenOCD to write the firmware in the STM32F103C8T6 Flash. Use a
+up to dated OpenOCD version (ie. openocd-0.9).
+
+You will need to create a copy of original openocd/scripts/target/stm32f1x.cfg
+to openocd/scripts/target/stm32f103c8t6.cfg and edit the later file replacing::
+
+ flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
+
+with::
+
+ flash bank $_FLASHNAME stm32f1x 0x08000000 0x20000 0 0 $_TARGETNAME
+
+We will use OpenOCD with STLink-V2 programmer, but it will work with other
+programmers (JLink, Versaloon, or some based on FTDI FT232, etc).
+
+Open a terminal and execute::
+
+ $ sudo openocd -f interface/stlink-v2.cfg -f target/stm32f103c8t6.cfg
+
+Now in other terminal execute::
+
+ $ telnet localhost 4444
+
+ Trying 127.0.0.1...
+ Connected to localhost.
+ Escape character is '^]'.
+ Open On-Chip Debugger
+
+ > reset halt
+ stm32f1x.cpu: target state: halted
+ target halted due to debug-request, current mode: Thread
+ xPSR: 0x01000000 pc: 0x080003ac msp: 0x20000d78
+
+ > flash write_image erase nuttx.bin 0x08000000
+ auto erase enabled
+ device id = 0x20036410
+ ignoring flash probed value, using configured bank size
+ flash size = 128kbytes
+ stm32f1x.cpu: target state: halted
+ target halted due to breakpoint, current mode: Thread
+ xPSR: 0x61000000 pc: 0x2000003a msp: 0x20000d78
+ wrote 92160 bytes from file nuttx.bin in 4.942194s (18.211 KiB/s)
+
+ > reset run
+ > exit
+
+Now NuttX should start normally.
+
+Nintendo Wii Nunchuck:
+======================
+
+There is a driver on NuttX to support Nintendo Wii Nunchuck Joystick. If you
+want to use it please select these options:
+
+- Enable the I2C1 at System Type -> STM32 Peripheral Support, it will enable:
+
+ CONFIG_STM32_I2C1=y
+
+- Enable to Custom board/driver initialization at RTOS Features -> RTOS hooks
+
+ CONFIG_BOARD_LATE_INITIALIZE=y
+
+- Enable the I2C Driver Support at Device Drivers, it will enable this symbol:
+
+ CONFIG_I2C=y
+
+- Nintendo Wii Nunchuck Joystick at Device Drivers -> [*] Input Device Support
+
+ CONFIG_INPUT=y
+ CONFIG_INPUT_NUNCHUCK=y
+
+- Enable the Nunchuck joystick example at Application Configuration -> Examples
+
+ CONFIG_EXAMPLES_NUNCHUCK=y
+ CONFIG_EXAMPLES_NUNCHUCK_DEVNAME="/dev/nunchuck0"
+
+You need to connect GND and +3.3V pins from Nunchuck connector to GND and 3.3V
+of stm32f103-minimum respectively (Nunchuck also can work connected to 5V, but
+I don't recommend it). Connect I2C Clock from Nunchuck to SCK (PB6) and the
+I2C Data to SDA (PB7).
+
+Quadrature Encoder:
+===================
+
+The nsh configuration has been used to test the Quadrature Encoder
+(QEncoder, QE) with the following modifications to the configuration
+file:
+
+- These setting enable support for the common QEncode upper half driver:
+
+ CONFIG_SENSORS=y
+ CONFIG_SENSORS_QENCODER=y
+
+- This is a board setting that selected timer 4 for use with the
+ quadrature encode:
+
+ CONFIG_STM32F103MINIMUM_QETIMER=4
+
+- These settings enable the STM32 Quadrature encoder on timer 4:
+
+ CONFIG_STM32_TIM4_CAP=y
+ CONFIG_STM32_TIM4_QE=y
+ CONFIG_STM32_TIM4_QECLKOUT=2800000
+ CONFIG_STM32_QENCODER_FILTER=y
+ CONFIG_STM32_QENCODER_SAMPLE_EVENT_6=y
+ CONFIG_STM32_QENCODER_SAMPLE_FDTS_4=y
+
+- These settings enable the test case at apps/examples/qencoder:
+
+ CONFIG_EXAMPLES_QENCODER=y
+ CONFIG_EXAMPLES_QENCODER_DELAY=100
+ CONFIG_EXAMPLES_QENCODER_DEVPATH="/dev/qe0"
+
+In this configuration, the QEncoder inputs will be on the TIM4 inputs of
+PB6 and PB7.
+
+SPI NOR Flash support:
+======================
+
+We can use an extern SPI NOR Flash with STM32F103-Minimum board. In this case
+we tested the Winboard W25Q32FV (32Mbit = 4MiB).
+
+You can connect the W25Q32FV module in the STM32F103 Minimum board this way:
+connect PA5 (SPI1 CLK) to CLK; PA7 (SPI1 MOSI) to DI; PA6 (SPI MISO) to DO;
+PA4 to /CS; Also connect 3.3V to VCC and GND to GND.
+
+You can start with default "stm32f103-minimum/nsh" configuration option and
+enable/disable these options using "make menuconfig" ::
+
+ System Type --->
+ STM32 Peripheral Support --->
+ [*] SPI1
+
+ Board Selection --->
+ [*] MTD driver for external 4Mbyte W25Q32FV FLASH on SPI1
+ (0) Minor number for the FLASH /dev/smart entry
+ [*] Enable partition support on FLASH
+ (1024,1024,1024,1024) Flash partition size list
+
+ RTOS Features --->
+ Stack and heap information --->
+ (512) Idle thread stack size
+ (1024) Main thread stack size
+ (256) Minimum pthread stack size
+ (1024) Default pthread stack size
+
+ Device Drivers --->
+ -*- Memory Technology Device (MTD) Support --->
+ [*] Support MTD partitions
+ -*- SPI-based W25 FLASH
+ (0) W25 SPI Mode
+ (20000000) W25 SPI Frequency
+
+ File Systems --->
+ [ ] Disable pseudo-filesystem operations
+ -*- SMART file system
+ (0xff) FLASH erased state
+ (16) Maximum file name length
+
+ Memory Management --->
+ [*] Small memory model
+
+ Also change the boards/arm/stm32/stm32f103-minimum/scripts/ld.script file to use 128KB
+ of Flash instead 64KB (since this board has a hidden 64KB flash) :
+
+ MEMORY
+ {
+ flash (rx) : ORIGIN = 0x08000000, LENGTH = 128K
+ sram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K
+ }
+
+ Then after compiling and flashing the file nuttx.bin you can format and mount
+ the flash this way:
+
+ nsh> mksmartfs /dev/smart0p0
+ nsh> mksmartfs /dev/smart0p1
+ nsh> mksmartfs /dev/smart0p2
+ nsh> mksmartfs /dev/smart0p3
+
+ nsh> mount -t smartfs /dev/smart0p0 /mnt
+ nsh> ls /mnt
+ /mnt:
+
+ nsh> echo "Testing" > /mnt/file.txt
+
+ nsh> ls /mnt
+ /mnt:
+ file.txt
+
+ nsh> cat /mnt/file.txt
+ Testing
+
+ nsh>
+
+SDCard support:
+===============
+
+Only STM32F103xx High-density devices has SDIO controller. STM32F103C8T6 is a
+Medium-density device, but we can use SDCard over SPI.
+
+You can do that enabling these options::
+
+ CONFIG_FS_FAT=y
+
+ CONFIG_MMCSD=y
+ CONFIG_MMCSD_NSLOTS=1
+ CONFIG_MMCSD_SPI=y
+ CONFIG_MMCSD_SPICLOCK=20000000
+ CONFIG_MMCSD_SPIMODE=0
+
+ CONFIG_STM32_SPI=y
+ CONFIG_STM32_SPI1=y
+
+ CONFIG_SPI=y
+ CONFIG_SPI_CALLBACK=y
+ CONFIG_SPI_EXCHANGE=y
+
+And connect a SDCard/SPI board on SPI1. Connect the CS pin to PA4, SCK to
+PA5, MOSI to PA7 and MISO to PA6. Note: some chinese boards use MOSO instead
+of MISO.
+
+Nokia 5110 LCD Display support:
+===============================
+
+You can connect a low cost Nokia 5110 LCD display in the STM32F103 Minimum
+board this way: connect PA5 (SPI1 CLK) to CLK; PA7 (SPI1 MOSI) to DIN; PA4
+to CE; PA3 to RST; PA2 to DC. Also connect 3.3V to VCC and GND to GND.
+
+You can start with default "stm32f103-minimum/nsh" configuration option and
+enable these options using "make menuconfig" ::
+
+ System Type --->
+ STM32 Peripheral Support --->
+ [*] SPI1
+
+ Device Drivers --->
+ -*- SPI Driver Support --->
+ [*] SPI exchange
+ [*] SPI CMD/DATA
+
+ Device Drivers --->
+ LCD Driver Support --->
+ [*] Graphic LCD Driver Support --->
+ [*] Nokia 5110 LCD Display (Phillips PCD8544)
+ (1) Number of PCD8544 Devices
+ (84) PCD8544 X Resolution
+ (48) PCD8544 Y Resolution
+
+ Graphics Support --->
+ [*] NX Graphics
+ (1) Number of Color Planes
+
+ (0x0) Initial background color
+ Supported Pixel Depths --->
+ [ ] Disable 1 BPP
+ [*] Packed MS First
+
+ Font Selections --->
+ (7) Bits in Character Set
+ [*] Mono 5x8
+
+ Application Configuration --->
+ Examples --->
+ [*] NX graphics "Hello, World!" example
+ (1) Bits-Per-Pixel
+
+ After compiling and flashing the nuttx.bin inside the board, reset it.
+ You should see it:
+
+ NuttShell (NSH)
+ nsh> ?
+ help usage: help [-v] [<cmd>]
+
+ [ dd free mb source usleep
+ ? echo help mh sleep xd
+ cat exec hexdump mw test
+ cd exit kill pwd true
+ cp false ls set unset
+
+ Builtin Apps:
+ nxhello
+
+ Now just run nxhello and you should see "Hello World" in the display:
+
+ nsh> nxhello
+
+HYT271 sensor support
+=====================
+
+The existing sensor configuration allows connecting several sensors of type
+hyt271 on i2c bus number 2. For full feature support, be able to change the
+i2c address of the sensor, the following hardware setup is necessary.::
+
+ ---------- -----------
+ | |------ GND ------------------------ GND ----| |
+ | | | |
+ | | | |
+ | | | |
+ | |---- POWIN A00 ------. | |
+ | | | | |
+ | | 4.7k | |
+ | | | | |
+ | STM32 |--- POWOUT A01 ------.------.------ VDD ----| HYT271 |
+ | | | | | |
+ | | 2.2k | | |
+ | | | | | |
+ | |----- SDA2 B11 ------.---- | ----- SDA ----| |
+ | | | | |
+ | | 2.2k | |
+ | | | | |
+ | |----- SCL2 B10 -------------.------ SCL ----| |
+ | | | |
+ --------- -----------
+
+DS18B20 sensor support
+======================
+
+The existing sensor configuration allows connecting several sensors of type
+ds18b20 on 1wire bus number 2. The following hardware setup is necessary.::
+
+ --------- -----------
+ | |------ GND ----------.------------- GND ----| |
+ | | | |
+ | | | |
+ | | | |
+ | |------ VDD ----------.------------- VDD ----| |
+ | STM32 | | | DS18B20 |
+ | | 4.7k | |
+ | | | | |
+ | |----- TX2 A02 -------.------.------- DQ ----| |
+ | | | |
+ -------- -----------
+
+USB Console support
+===================
+
+The STM32F103C8 has a USB Device controller, then we can use NuttX support
+to USB Device. We can the console over USB enabling these options:
+
+::
+
+ System Type --->
+ STM32 Peripheral Support --->
+ [*] USB Device
+
+ It will enable: CONFIG_STM32_USB=y
+
+ Board Selection --->
+ -*- Enable boardctl() interface
+ [*] Enable USB device controls
+
+ It will enable: CONFIG_BOARDCTL_USBDEVCTRL=y
+
+ Device Drivers --->
+ -*- USB Device Driver Support --->
+ [*] USB Modem (CDC/ACM) support --->
+
+ It will enable: CONFIG_CDCACM=y and many default options.
+
+ Device Drivers --->
+ -*- USB Device Driver Support --->
+ [*] USB Modem (CDC/ACM) support --->
+ [*] CDC/ACM console device
+
+ It will enable: CONFIG_CDCACM_CONSOLE=y
+
+ Device Drivers --->
+ [*] Serial Driver Support --->
+ Serial console (No serial console) --->
+ (X) No serial console
+
+It will enable: CONFIG_NO_SERIAL_CONSOLE=y
+
+After flashing the firmware in the board, unplug and plug it in the computer
+and it will create a /dev/ttyACM0 device in the Linux. Use minicom with this
+device to get access to NuttX NSH console (press Enter three times to start)
+
+MCP2515 External Module
+=======================
+
+You can use an external MCP2515 (tested with NiRen MCP2515_CAN module) to
+get CAN Bus working on STM32F103C8 chip (remember the internal CAN cannot
+work with USB at same time because they share the SRAM buffer).
+
+You can connect the MCP2515 module in the STM32F103 Minimum board this way:
+connect PA5 (SPI1 CLK) to SCK; PA7 (SPI1 MOSI) to SI; PA6 (SPI MISO) to SO;
+PA4 to CS; B0 to INT. Also connect 5V to VCC and GND to GND.
+
+Note: Although MCP2515 can work with 2.7V-5.5V it is more stable when using
+it on BluePill board on 5V.
+
+Testing: you will need at least 2 boards each one with a MCP2515 module
+connected to it. Connect CAN High from the first module to the CAN High of
+the second module, and the CAN Low from the first module to the CAN Low of
+the second module.
+
+You need to modify the "CAN example" application on menuconfig and create
+two firmware versions: the first firmware will be Read-only and the second
+one Write-only. Flash the first firmware in the first board and the second
+firmware in the second board. Now you can start the both boards, run the
+"can" command in the Write-only board and then run the "can" command in the
+Read-only board. You should see the data coming.
+
+STM32F103 Minimum - specific Configuration Options
+==================================================
+
+ ..
+ CONFIG_ARCH - Identifies the arch/ subdirectory. This should
+ be set to:
+
+ CONFIG_ARCH=arm
+
+ CONFIG_ARCH_family - For use in C code:
+
+ CONFIG_ARCH_ARM=y
+
+ CONFIG_ARCH_architecture - For use in C code:
+
+ CONFIG_ARCH_CORTEXM3=y
+
+ CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
+
+ CONFIG_ARCH_CHIP=stm32
+
+ CONFIG_ARCH_CHIP_name - For use in C code to identify the exact
+ chip:
+
+ CONFIG_ARCH_CHIP_STM32F103C8=y
+
+ CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock
+ configuration features.
+
+ CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n
+
+ CONFIG_ARCH_BOARD - Identifies the boards/ subdirectory and
+ hence, the board that supports the particular chip or SoC.
+
+ CONFIG_ARCH_BOARD=stm32f103-minimum
+
+ CONFIG_ARCH_BOARD_name - For use in C code
+
+ CONFIG_ARCH_BOARD_STM32_MINIMUM=y
+
+ CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
+ of delay loops
+
+ CONFIG_ENDIAN_BIG - define if big endian (default is little
+ endian)
+
+ CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case):
+
+ CONFIG_RAM_SIZE=20480 (20Kb)
+
+ CONFIG_RAM_START - The start address of installed DRAM
+
+ CONFIG_RAM_START=0x20000000
+
+ CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that
+ have LEDs
+
+ CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
+ stack. If defined, this symbol is the size of the interrupt
+ stack in bytes. If not defined, the user task stacks will be
+ used during interrupt handling.
+
+ CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
+
+ ..
+ Individual subsystems can be enabled:
+
+ AHB
+ ---
+ CONFIG_STM32_CRC
+ CONFIG_STM32_BKPSRAM
+
+ APB1
+ ----
+ CONFIG_STM32_TIM2
+ CONFIG_STM32_TIM3
+ CONFIG_STM32_TIM4
+ CONFIG_STM32_WWDG
+ CONFIG_STM32_IWDG
+ CONFIG_STM32_SPI2
+ CONFIG_STM32_USART2
+ CONFIG_STM32_USART3
+ CONFIG_STM32_I2C1
+ CONFIG_STM32_I2C2
+ CONFIG_STM32_CAN1
+ CONFIG_STM32_PWR -- Required for RTC
+
+ APB2
+ ----
+ CONFIG_STM32_TIM1
+ CONFIG_STM32_USART1
+ CONFIG_STM32_ADC1
+ CONFIG_STM32_ADC2
+ CONFIG_STM32_SPI1
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If CONFIG_STM32_TIMn
+ is defined (as above) then the following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation or ADC conversion.
+ Note that ADC require two definitions: Not only do you have
+ to assign the timer (n) for used by the ADC, but then you also have to
+ configure which ADC (m) it is assigned to.
+
+ CONFIG_STM32_TIMn_PWM Reserve timer n for use by PWM, n=1,..,14
+ CONFIG_STM32_TIMn_ADC Reserve timer n for use by ADC, n=1,..,14
+ CONFIG_STM32_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,14, m=1,..,3
+
+ For each timer that is enabled for PWM usage, we need the following additional
+ configuration settings:
+
+ CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
+
+ NOTE: The STM32 timers are each capable of generating different signals on
+ each of the four channels with different duty cycles. That capability is
+ not supported by this driver: Only one output channel per timer.
+
+ JTAG Enable settings (by default only SW-DP is enabled):
+
+ CONFIG_STM32_JTAG_FULL_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
+ CONFIG_STM32_JTAG_NOJNTRST_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
+ but without JNTRST.
+ CONFIG_STM32_JTAG_SW_ENABLE - Set JTAG-DP disabled and SW-DP enabled
+
+ STM32F103 Minimum specific device driver settings
+
+ CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=1,2,3)
+ for the console and ttys0 (default is the USART1).
+ CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received.
+ This specific the size of the receive buffer
+ CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before
+ being sent. This specific the size of the transmit buffer
+ CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be
+ CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8.
+ CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
+ CONFIG_U[S]ARTn_2STOP - Two stop bits
+
+ STM32F103 Minimum CAN Configuration
+
+ CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32_CAN1 or
+ CONFIG_STM32_CAN2 must also be defined)
+ CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. Default
+ Standard 11-bit IDs.
+ CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages.
+ Default: 8
+ CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests.
+ Default: 4
+ CONFIG_CAN_LOOPBACK - A CAN driver may or may not support a loopback
+ mode for testing. The STM32 CAN driver does support loopback mode.
+ CONFIG_STM32_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN1
+ is defined.
+ CONFIG_STM32_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN2
+ is defined.
+ CONFIG_STM32_CAN_TSEG1 - The number of CAN time quanta in segment 1.
+ Default: 6
+ CONFIG_STM32_CAN_TSEG2 - the number of CAN time quanta in segment 2.
+ Default: 7
+ CONFIG_STM32_CAN_REGDEBUG - If CONFIG_DEBUG_FEATURES is set, this will generate an
+ dump of all CAN registers.
+
+ STM32F103 Minimum SPI Configuration
+
+ CONFIG_STM32_SPI_INTERRUPTS - Select to enable interrupt driven SPI
+ support. Non-interrupt-driven, poll-waiting is recommended if the
+ interrupt rate would be to high in the interrupt driven case.
+ CONFIG_STM32_SPIx_DMA - Use DMA to improve SPIx transfer performance.
+ Cannot be used with CONFIG_STM32_SPI_INTERRUPT.
+
+Configurations
+==============
+
+Instantiating Configurations
+----------------------------
+
+Each STM32F103 Minimum configuration is maintained in a sub-directory and
+can be selected as follow::
+
+ tools/configure.sh STM32F103 Minimum:<subdir>
+
+Where <subdir> is one of the following:
+
+Configuration Directories
+-------------------------
+
+nsh
+---
+
+Configures the NuttShell (nsh) located at apps/examples/nsh. This
+configuration enables a console on UART1. Support for
+builtin applications is enabled, but in the base configuration no
+builtin applications are selected.
+
+jlx12864g
+---------
+
+This is a config example to use the JLX12864G-086 LCD module. To use this
+LCD you need to connect PA5 (SPI1 CLK) to SCK; PA7 (SPI1 MOSI) to SDA; PA4
+to CS; PA3 to RST; PA2 to RS.
+
+nrf24
+-----
+
+This is a config example to test the nrf24 terminal example. You will need
+two stm32f103-minimum board each one with a nRF24L01 module connected this
+way: connect PB1 to nRF24 CE pin; PA4 to CSN; PA5 (SPI1 CLK) to SCK; PA7
+(SPI1 MOSI) to MOSI; PA6 (SPI1 MISO) to MISO; PA0 to IRQ.
+
+usbnsh
+------
+
+This is another NSH example. If differs from other 'nsh' configurations
+in that this configurations uses a USB serial device for console I/O.
+
+NOTES:
+
+1. This configuration uses the mconf-based configuration tool. To
+ change this configuration using that tool, you should:
+
+ a. Build and install the kconfig-mconf tool. See nuttx/README.txt
+ see additional README.txt files in the NuttX tools repository.
+
+ b. Execute 'make menuconfig' in nuttx/ in order to start the
+ reconfiguration process.
+
+2. By default, this configuration uses the ARM EABI toolchain
+ for Windows and builds under Cygwin (or probably MSYS). That
+ can easily be reconfigured, of course.
+
+ CONFIG_HOST_WINDOWS=y : Builds under Windows
+ CONFIG_WINDOWS_CYGWIN=y : Using Cygwin
+ CONFIG_ARM_TOOLCHAIN_GNU_EABI=y : GNU EABI toolchain for Windows
+
+3. This configuration does have UART2 output enabled and set up as
+ the system logging device:
+
+ CONFIG_SYSLOG_CHAR=y : Use a character device for system logging
+ CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" : UART2 will be /dev/ttyS0
+
+ However, there is nothing to generate SYSLOG output in the default
+ configuration so nothing should appear on UART2 unless you enable
+ some debug output or enable the USB monitor.
+
+4. Enabling USB monitor SYSLOG output. If tracing is enabled, the USB
+ device will save encoded trace output in in-memory buffer; if the
+ USB monitor is enabled, that trace buffer will be periodically
+ emptied and dumped to the system logging device (UART2 in this
+ configuration)::
+
+ CONFIG_USBDEV_TRACE=y : Enable USB trace feature
+ CONFIG_USBDEV_TRACE_NRECORDS=128 : Buffer 128 records in memory
+ CONFIG_NSH_USBDEV_TRACE=n : No builtin tracing from NSH
+ CONFIG_NSH_ARCHINIT=y : Automatically start the USB monitor
+ CONFIG_USBMONITOR=y : Enable the USB monitor daemon
+ CONFIG_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size
+ CONFIG_USBMONITOR_PRIORITY=50 : USB monitor daemon priority
+ CONFIG_USBMONITOR_INTERVAL=2 : Dump trace data every 2 seconds
+
+ CONFIG_USBMONITOR_TRACEINIT=y : Enable TRACE output
+ CONFIG_USBMONITOR_TRACECLASS=y
+ CONFIG_USBMONITOR_TRACETRANSFERS=y
+ CONFIG_USBMONITOR_TRACECONTROLLER=y
+ CONFIG_USBMONITOR_TRACEINTERRUPTS=y
+
+5. By default, this project assumes that you are *NOT* using the DFU
+ bootloader.
+
+Using the Prolifics PL2303 Emulation
+------------------------------------
+
+You could also use the non-standard PL2303 serial device instead of
+the standard CDC/ACM serial device by changing::
+
+ CONFIG_CDCACM=y : Disable the CDC/ACM serial device class
+ CONFIG_CDCACM_CONSOLE=y : The CDC/ACM serial device is NOT the console
+ CONFIG_PL2303=y : The Prolifics PL2303 emulation is enabled
+ CONFIG_PL2303_CONSOLE=y : The PL2303 serial device is the console
+
+veml6070
+--------
+
+This is a config example to use the Vishay VEML6070 UV-A sensor. To use this
+sensor you need to connect PB6 (I2C1 CLK) to SCL; PB7 (I2C1 SDA) to SDA of
+sensor module. I used a GY-VEML6070 module to test this driver.
diff --git a/content/docs/latest/_sources/platforms/arm/stm32f1/boards/stm32vldiscovery/index.rst.txt b/content/docs/latest/_sources/platforms/arm/stm32f1/boards/stm32vldiscovery/index.rst.txt
new file mode 100644
index 00000000..91b2f212
--- /dev/null
+++ b/content/docs/latest/_sources/platforms/arm/stm32f1/boards/stm32vldiscovery/index.rst.txt
@@ -0,0 +1,215 @@
+===================
+ST STM32VLDiscovery
+===================
+
+This README discusses issues unique to NuttX configurations for the STMicro
+STM32VLDiscovery (Value Line Discovery) board.
+
+
+LEDs
+====
+
+It is assumed that STMicro STM32F100RB generic board board has one LED on PA0.
+You should configure the port and pin number in
+boards/arm/stm32/stm32vldiscovery/src/stm32vldiscovery.h. This LED is not used by
+the board port unless CONFIG_ARCH_LEDS is defined. In that case, the usage by
+the board port is defined in include/board.h and src/up_leds.c. The LED is used
+to encode OS-related events as follows::
+
+ SYMBOL Meaning LED1*
+ green
+ ------------------- ----------------------- -------
+ LED_STARTED NuttX has been started ON
+ LED_HEAPALLOCATE Heap has been allocated ON
+ LED_IRQSENABLED Interrupts enabled ON
+ LED_STACKCREATED Idle stack created ON
+ LED_INIRQ In an interrupt ON
+ LED_SIGNAL In a signal handler ON
+ LED_ASSERTION An assertion failed OFF
+ LED_PANIC The system has crashed OFF
+
+So basically if the LED is off it means that there is a problem.
+
+UART
+====
+
+Default USART/UART Configuration
+--------------------------------
+
+USART1 is enabled in all configurations (see \*/defconfig). RX and TX are
+configured on pins PA10 and PA9, respectively. Then connect the RX pin of
+your USB/Serial adapter to TX pin (PA9) and the TX pin of your adapter to
+RX pin (PA10) of your board besides, of course, the GND pin.
+
+"STMicro STM32F100RB generic" specific Configuration Options
+============================================================
+
+::
+
+ CONFIG_ARCH - Identifies the arch/ subdirectory. This should
+ be set to:
+
+ CONFIG_ARCH=arm
+
+ CONFIG_ARCH_family - For use in C code:
+
+ CONFIG_ARCH_ARM=y
+
+ CONFIG_ARCH_architecture - For use in C code:
+
+ CONFIG_ARCH_CORTEXM3=y
+
+ CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
+
+ CONFIG_ARCH_CHIP=stm32
+
+ CONFIG_ARCH_CHIP_name - For use in C code to identify the exact
+ chip:
+
+ CONFIG_ARCH_CHIP_STM32F100RB=y
+
+ CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock
+ configuration features.
+
+ CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n
+
+ CONFIG_ARCH_BOARD - Identifies the boards/ subdirectory and
+ hence, the board that supports the particular chip or SoC.
+
+ CONFIG_ARCH_BOARD=stm32vldiscovery
+
+ CONFIG_ARCH_BOARD_name - For use in C code
+
+ CONFIG_ARCH_BOARD_STM32VL_DISCOVERY=y
+
+ CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
+ of delay loops
+
+ CONFIG_ENDIAN_BIG - define if big endian (default is little
+ endian)
+
+ CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case):
+
+ CONFIG_RAM_SIZE=8192 (8kB)
+
+ CONFIG_RAM_START - The start address of installed DRAM
+
+ CONFIG_RAM_START=0x20000000
+
+ CONFIG_ARCH_LEDS - Use LED to show state. Unique to boards that have LED(s)
+
+ CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
+ stack. If defined, this symbol is the size of the interrupt
+ stack in bytes. If not defined, the user task stacks will be
+ used during interrupt handling.
+
+ CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
+
+ Individual subsystems can be enabled::
+
+ AHB
+ ----
+ CONFIG_STM32_CRC
+ CONFIG_STM32_DMA1
+ CONFIG_STM32_DMA2
+
+ APB1
+ ----
+ CONFIG_STM32_TIM2
+ CONFIG_STM32_TIM3
+ CONFIG_STM32_TIM4
+ CONFIG_STM32_TIM5
+ CONFIG_STM32_TIM6
+ CONFIG_STM32_TIM7
+ CONFIG_STM32_TIM12
+ CONFIG_STM32_TIM13
+ CONFIG_STM32_TIM14
+ CONFIG_STM32_RTC
+ CONFIG_STM32_WWDG
+ CONFIG_STM32_IWDG
+ CONFIG_STM32_SPI2
+ CONFIG_STM32_SPI3
+ CONFIG_STM32_USART2
+ CONFIG_STM32_USART3
+ CONFIG_STM32_UART4
+ CONFIG_STM32_UART5
+ CONFIG_STM32_I2C1
+ CONFIG_STM32_I2C2
+ CONFIG_STM32_PWR -- Required for RTC
+ CONFIG_STM32_BKP -- Required for RTC
+ CONFIG_STM32_DAC1
+ CONFIG_STM32_DAC2
+ CONFIG_STM32_CEC
+
+ APB2
+ ----
+ CONFIG_STM32_ADC1
+ CONFIG_STM32_TIM1
+ CONFIG_STM32_SPI1
+ CONFIG_STM32_USART1
+ CONFIG_STM32_TIM15
+ CONFIG_STM32_TIM16
+ CONFIG_STM32_TIM17
+
+ Timer devices may be used for different purposes. One special purpose is
+ to generate modulated outputs for such things as motor control. If CONFIG_STM32_TIMn
+ is defined (as above) then the following may also be defined to indicate that
+ the timer is intended to be used for pulsed output modulation, ADC conversion,
+ or DAC conversion. Note that ADC/DAC require two definition: Not only do you have
+ to assign the timer (n) for used by the ADC or DAC, but then you also have to
+ configure which ADC or DAC (m) it is assigned to.
+
+ CONFIG_STM32_TIMn_PWM Reserve timer n for use by PWM, n=1,..,17
+ CONFIG_STM32_TIMn_ADC Reserve timer n for use by ADC, n=1,..,17
+ CONFIG_STM32_TIMn_ADC1 Reserve timer n to trigger ADCm, n=1,..,17
+ CONFIG_STM32_TIMn_DAC Reserve timer n for use by DAC, n=1,..,17
+ CONFIG_STM32_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,17, m=1,..,2
+
+ For each timer that is enabled for PWM usage, we need the following additional
+ configuration settings:
+
+ CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
+
+ NOTE: The STM32 timers are each capable of generating different signals on
+ each of the four channels with different duty cycles. That capability is
+ not supported by this driver: Only one output channel per timer.
+
+ JTAG Enable settings (by default full SWJ is enabled):
+
+ CONFIG_STM32_JTAG_FULL_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
+ CONFIG_STM32_JTAG_NOJNTRST_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
+ but without JNTRST.
+ CONFIG_STM32_JTAG_SW_ENABLE - Set JTAG-DP disabled and SW-DP enabled
+
+ STMicro STM32F100RB generic specific device driver settings
+
+ CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=1,2,3) or UART
+ m (m=4,5) for the console and ttys0 (default is the USART1).
+ CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received.
+ This specific the size of the receive buffer
+ CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before
+ being sent. This specific the size of the transmit buffer
+ CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be
+ CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8.
+ CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
+ CONFIG_U[S]ARTn_2STOP - Two stop bits
+
+Configurations
+==============
+
+Each STMicro STM32F100RB generic configuration is maintained in a sub-directory
+and can be selected as follow::
+
+ tools/configure.sh stm32vldiscovery:<subdir>
+
+Where <subdir> is one of the following:
+
+nsh
+---
+
+Configures the NuttShell (nsh) located at apps/examples/nsh. The
+Configuration enables only the serial NSH interfaces.
+
+Default toolchain::
+
+ CONFIG_ARM_TOOLCHAIN_GNU_EABI=y : GNU EABI toolchain for Linux
diff --git a/content/docs/latest/_sources/platforms/arm/stm32f1/boards/viewtool-stm32f107/index.rst.txt b/content/docs/latest/_sources/platforms/arm/stm32f1/boards/viewtool-stm32f107/index.rst.txt
new file mode 100644
index 00000000..2fb2cdd7
--- /dev/null
+++ b/content/docs/latest/_sources/platforms/arm/stm32f1/boards/viewtool-stm32f107/index.rst.txt
@@ -0,0 +1,1116 @@
+=======================
+ViewTool STM32F103/F107
+=======================
+
+This README discusses issues unique to NuttX configurations for the
+ViewTool STM32F103/F107 V1.2 board. This board may be fitted with either
+
+- STM32F107VCT6, or
+- STM32F103VCT6
+
+The board is very modular with connectors for a variety of peripherals.
+Features on the base board include:
+
+- User and Wake-Up Keys
+- LEDs
+
+See http://www.viewtool.com/ for further information.
+
+User and Wake-Up keys
+=====================
+
+All pulled high and will be sensed low when depressed.::
+
+ SW2 PC11 Needs J42 closed
+ SW3 PC12 Needs J43 closed
+ SW4 PA0 Needs J44 closed
+
+LEDs
+====
+
+There are four LEDs on the ViewTool STM32F103/F107 board that can be controlled
+by software: LED1 through LED4. All pulled high and can be illuminated by
+driving the output to low::
+
+ LED1 PA6
+ LED2 PA7
+ LED3 PB12
+ LED4 PB13
+
+These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
+defined. In that case, the usage by the board port is defined in
+include/board.h and src/stm32_leds.c. The LEDs are used to encode OS-related
+events as follows::
+
+ SYMBOL Meaning LED state
+ LED1 LED2 LED3 LED4
+ ----------------- ----------------------- ---- ---- ---- ----
+ LED_STARTED NuttX has been started ON OFF OFF OFF
+ LED_HEAPALLOCATE Heap has been allocated OFF ON OFF OFF
+ LED_IRQSENABLED Interrupts enabled ON ON OFF OFF
+ LED_STACKCREATED Idle stack created OFF OFF ON OFF
+ LED_INIRQ In an interrupt N/C N/C N/C Soft glow
+ LED_SIGNAL In a signal handler N/C N/C N/C Soft glow
+ LED_ASSERTION An assertion failed N/C N/C N/C Soft glow
+ LED_PANIC The system has crashed N/C N/C N/C 2Hz Flashing
+ LED_IDLE MCU is is sleep mode Not used
+
+After booting, LED1-3 are not longer used by the system and can be used for
+other purposes by the application (Of course, all LEDs are available to the
+application if CONFIG_ARCH_LEDS is not defined.
+
+Serial Console
+==============
+
+Console Configuration
+---------------------
+
+The NuttX console is configured by default on USART1 at 115200 BAUD 8N1
+(8-bits, not parity, one stop bit). These setting can, of course, easily
+be changed by reconfiguring NuttX.
+
+J5 - USART1
+-----------
+
+The boards come with a PL-2303 based USB-to-serial board. Also available
+as an option is an RS-232 board. Both have the same pin out on a 6-pin
+connector that mates with the upper row of J5.::
+
+ PIN MODULE BOARD J5
+ --- ------ ---------------------------
+ 1 5V 1 POWER Power jumper
+ 2 GND 3 GND Ground
+ 3 TXD 5 RXD1 PA10 USART1_RXD
+ 4 RXD 7 TXD1 PA9 USART1_TXD
+ 5 RTS? 9 CTS? PA12 USART1_RTS
+ 6 CTS? 11 RTS? PA11 USART1_CTS
+
+PL-2013 USB-to-Serial Interface
+-------------------------------
+
+J37 - CON4. Jumper Settings::
+
+ 1 <-> 3 : Connects PA9 to the RXD1 output pin
+ 2 <-> 4 : Connects PA10 to the TXD1 input pin
+
+J35 - CON2. Jumper Setting::
+
+ Open. the PL2303 adapter receives its power from the USB host.
+
+RS-232 Module
+-------------
+
+J37 - CON4. Jumper Settings::
+
+ 1 <-> 3 : Connects PA9 to the RXD1 output pin
+ 2 <-> 4 : Connects PA10 to the TXD1 input pin
+
+J35 - CON2. Jumper Setting::
+
+ 1 <-> 2 : Proves 3.3V to the RS-232 module.
+
+USB Interface
+=============
+
+USB Connector
+-------------
+
+The Viewtool base board has a USB Mini-B connector. Only USB device can
+be supported with this connector.::
+
+ ------------------------- ------------------------------------
+ USB Connector
+ J10 mini-USB GPIO CONFIGURATION(s)
+ --- --------- ----------- ------------------------------------
+ Pin Signal
+ --- --------- ----------- ------------------------------------
+ 1 USB_VBUS VDD_USB (No sensing available)
+ 2 OTG_DM PA11 GPIO_OTGFS_DM (F107) GPIO_USB_DM (F103)
+ 3 OTG_DP PA12 GPIO_OTGFS_DP (F107) GPIO_USB_DP (F103)
+ 4 OTG_ID PA10 GPIO_OTGFS_ID (F107)
+ 5 Shield N/A N/A
+ 6 Shield N/A N/A
+ 7 Shield N/A N/A
+ 8 Shield N/A N/A
+ 9 Shield N/A N/A
+ PE11 USB_EN GPIO controlled soft pull-up (if J51 closed)
+
+ NOTES:
+ 1. GPIO_OTGFS_VBUS (F107) should not be configured. No VBUS sensing
+ 2. GPIO_OTGFS_SOF (F107) is not used
+ 3. The OTG FS module has is own, internal soft pull-up logic. J51 should
+ be open so that PE11 activity does effect USB.
+
+STM32F103 Configuration
+-----------------------
+
+System Type -> STM32 Peripheral Support::
+
+ CONFIG_STM32_USB=y : Enable USB FS device
+
+Device Drivers::
+
+ CONFIG_USBDEV : USB device support
+
+STATUS: All of the code is in place, but no testing has been performed.
+
+STM32F107 Configuration
+-----------------------
+
+System Type -> STM32 Peripheral Support::
+
+ CONFIG_STM32_OTGFS=y : Enable OTG FS
+
+Device Drivers::
+
+ CONFIG_USBDEV : USB device support
+
+STATUS: All of the code is in place, but USB is not yet functional.
+
+CDC/ACM Configuration
+---------------------
+
+This will select the CDC/ACM serial device. Defaults for the other
+options should be okay.::
+
+ Device Drivers -> USB Device Driver Support
+ CONFIG_CDCACM=y : Enable the CDC/ACM device
+
+The following setting enables an example that can can be used to control
+the CDC/ACM device. It will add two new NSH commands:
+
+a. sercon will connect the USB serial device (creating /dev/ttyACM0), and
+b. serdis which will disconnect the USB serial device (destroying
+ /dev/ttyACM0).
+
+Application Configuration -> Examples::
+
+ CONFIG_SYSTEM_CDCACM=y : Enable an CDC/ACM example
+
+USB MSC Configuration
+---------------------
+
+[WARNING: This configuration has not yet been verified]
+
+The Mass Storage Class (MSC) class driver can be selected in order to
+export the microSD card to the host computer. MSC support is selected:::
+
+ Device Drivers -> USB Device Driver Support
+ CONFIG_USBMSC=y : Enable the USB MSC class driver
+ CONFIG_USBMSC_EPBULKOUT=1 : Use EP1 for the BULK OUT endpoint
+ CONFIG_USBMSC_EPBULKIN=2 : Use EP2 for the BULK IN endpoint
+
+The following setting enables an add-on that can can be used to control
+the USB MSC device. It will add two new NSH commands:
+
+a. msconn will connect the USB serial device and export the microSD
+ card to the host, and
+b. msdis which will disconnect the USB serial device.
+
+Application Configuration -> System Add-Ons::
+
+ CONFIG_SYSTEM_USBMSC=y : Enable the USBMSC add-on
+ CONFIG_SYSTEM_USBMSC_NLUNS=1 : One LUN
+ CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 : Minor device zero
+ CONFIG_SYSTEM_USBMSC_DEVPATH1="/dev/mmcsd0"
+ : Use a single, LUN: The microSD
+ : block driver.
+
+NOTES:
+
+a. To prevent file system corruption, make sure that the microSD is un-
+ mounted *before* exporting the mass storage device to the host::
+
+ nsh> umount /mnt/sdcard
+ nsh> mscon
+
+ The microSD can be re-mounted after the mass storage class is disconnected::
+
+ nsh> msdis
+ nsh> mount -t vfat /dev/mtdblock0 /mnt/at25
+
+microSD Card Interface
+======================
+
+microSD Connector
+-----------------
+
+::
+
+ ----------------------------- ------------------------- --------------------------------
+ Connector J17 GPIO CONFIGURATION(s)
+ PIN SIGNAL LEGEND (no remapping) DP83848C Board
+ --- ------------- ----------- ------------------------- --------------------------------
+ 1 VDD 3.3 N/A N/A 3.3
+ 2 GND N/A N/A GND
+ 3 PC8 SDIO_D0 GPIO_SDIO_D0 D0
+ 4 PD2 SDIO_CMD GPIO_SDIO_CMD CMD
+ 5 PC12 SDIO_CLK GPIO_SDIO_CK CLK
+ 6 PC11 SDIO_D3 GPIO_SDIO_D3 D3
+ 7 PC10 SDIO_D2 GPIO_SDIO_D2 D2
+ 8 PC9 SDIO_D1 GPIO_SDIO_D1 D1
+ 9 PA8 CD Board-specific GPIO input CD
+ --- ------------- ----------- ------------------------- --------------------------------
+
+ NOTES:
+ 1. The STM32F107 does not support the SDIO/memory card interface. So the SD card
+ cannot be used with the STM32F107 (unless the pin-out just happens to match up
+ with an SPI-based card interface???)
+
+Configuration (STM32F103 only)
+------------------------------
+
+ [WARNING: This configuration has not yet been verified]
+
+ Enabling SDIO-based MMC/SD support::
+
+ System Type->STM32 Peripheral Support
+ CONFIG_STM32_SDIO=y : Enable SDIO support
+ CONFIG_STM32_DMA2=y : DMA2 is needed by the driver
+
+ Device Drivers -> MMC/SD Driver Support
+ CONFIG_MMCSD=y : Enable MMC/SD support
+ CONFIG_MMSCD_NSLOTS=1 : One slot per driver instance
+ CONFIG_MMCSD_HAVE_CARDDETECT=y : Supports card-detect PIOs
+ CONFIG_MMCSD_MMCSUPPORT=n : Interferes with some SD cards
+ CONFIG_MMCSD_SPI=n : No SPI-based MMC/SD support
+ CONFIG_MMCSD_SDIO=y : SDIO-based MMC/SD support
+ CONFIG_SDIO_DMA=y : Use SDIO DMA
+ CONFIG_SDIO_BLOCKSETUP=y : Needs to know block sizes
+
+ Library Routines
+ CONFIG_SCHED_WORKQUEUE=y : Driver needs work queue support
+
+ Application Configuration -> NSH Library
+ CONFIG_NSH_ARCHINIT=y : NSH board-initialization
+
+ Using the SD card
+ -----------------
+
+ 1) After booting, an SDIO device will appear as /dev/mmcsd0
+
+ 2) If you try mounting an SD card with nothing in the slot, the
+ mount will fail:
+
+ nsh> mount -t vfat /dev/mmcsd1 /mnt/sd1
+ nsh: mount: mount failed: 19
+
+ STATUS: All of the code is in place, but no testing has been performed.
+
+ViewTool DP83848 Ethernet Module
+================================
+
+Ethernet Connector
+------------------
+
+..
+ ----------------------------- ------------------------ --------------------------------
+ Connector J2 GPIO CONFIGURATION(s)
+ PIN SIGNAL LEGEND (no remapping) DP83848C Board
+ --- ------------- ----------- ------------------------ --------------------------------
+ 1 PA0 MII_CRS N/A N/C
+ 2 PB11/SDA2 COM_TX_EN GPIO_ETH_RMII_TX_EN TX_EN
+ 3 PA3/LED_G2 MII_COL N/A N/C
+ 4 PB12/NSS2 COM_TXD0 GPIO_ETH_RMII_TXD0 TXD0
+ 5 PA1 MII_RX_CLK GPIO_ETH_RMII_REF_CLK OSCIN
+ 6 PB13/SCK2 COM_TXD1 GPIO_ETH_RMII_TXD1 TXD1
+ 7 PB1/CD_RESET MII_RXD3 N/A N/C
+ 8 PC4/LCDTP COM_RXD0 GPIO_ETH_RMII_RXD0 RXD0
+ 9 PB0/BL_PWM MII_RXD2 N/A N/C
+ 10 PC5 COM_RXD1 GPIO_ETH_RMII_RXD1 RXD1
+ 11 PB8/CAN1_RX MII_TXD3 N/A N/C
+ 12 PC1/LED_R1 COM_MDC GPIO_ETH_MDC MDC
+ 13 PC2/LED_R2 MII_TXD2 N/A N/C
+ 14 PA2/LED_G1 COM_MDIO GPIO_ETH_MDIO MDIO
+ 15 PC3/ONEW MII_TX_CLK N/A N/C
+ 16 PB10/SCL2 RX_ER N/A N/C
+ 17 PD2 GPIO1 N/A N/C
+ 18 PA7/MOSI1 COM_RX_DV GPIO_ETH_RMII_CRS_DV CRS_DIV
+ 19 PD3 GPIO2 N/A N/C
+ 20 PB5 COM_PPS_OUT N/A N/C
+ 21 VDD 3.3 VDD_3.3 N/A 3.3V
+ 22 VDD 3.3 VDD_3.3 N/A 3.3V
+ 23 GND GND N/A GND
+ 24 GND GND N/A GND
+ --- ------------- ----------- ------------------------ --------------------------------
+
+ NOTES:
+ 1. RMII interface is used
+ 2. There is a 50MHz clock on board the DP83848. No MCO clock need be provided.
+
+Configuration
+-------------
+
+System Type -> STM32 Peripheral Support::
+
+ CONFIG_STM32_ETHMAC=y : Enable Ethernet driver
+
+System Type -> Ethernet MAC Configuration::
+
+ CONFIG_STM32_RMII=y : Configuration RM-II DP83848C PHY
+ CONFIG_STM32_AUTONEG=y
+ CONFIG_STM32_PHYADDR=1
+ CONFIG_STM32_PHYSR=16
+ CONFIG_STM32_PHYSR_SPEED=0x0002
+ CONFIG_STM32_PHYSR_100MBPS=0x0000
+ CONFIG_STM32_PHYSR_MODE=0x0004
+ CONFIG_STM32_PHYSR_FULLDUPLEX=0x0004
+ CONFIG_STM32_RMII_EXTCLK=y
+
+Device Drivers -> Networking Devices::
+
+ CONFIG_NETDEVICES=y : More PHY stuff
+ CONFIG_ETH0_PHY_DP83848C=y
+
+Networking (required)::
+
+ CONFIG_NET=y : Enabled networking support
+ CONFIG_NSH_NOMAC=y
+
+Networking (recommended/typical)::
+
+ CONFIG_NET_SOCKOPTS=y
+
+ CONFIG_NET_ETH_PKTSIZE=650 : Maximum packet size
+
+ CONFIG_NET_TCP=y : TCP support
+ CONFIG_NET_NTCP_READAHEAD_BUFFERS=8
+
+ CONFIG_NET_UDP=y : UDP support
+ CONFIG_NET_UDP_PREALLOC_CONNS=8
+
+ CONFIG_NET_ICMP=y : ICMP support
+ CONFIG_NET_ICMP_SOCKET=y
+
+ CONFIG_NSH_DRIPADDR=0x0a000001 : Network identity
+ CONFIG_NSH_IPADDR=0x0a000002
+ CONFIG_NSH_NETMASK=0xffffff00
+
+Network Utilities (basic)::
+
+ CONFIG_NETUTILS_TFTPC=y : Needed by NSH unless to disable TFTP commands
+ CONFIG_NETUTILS_DHCPC=y : Fun stuff
+ CONFIG_NETUTILS_TELNETD=y : Support for a Telnet NSH console
+ CONFIG_NSH_TELNET=y
+
+ (also FTP, TFTP, WGET, NFS, etc. if you also have a mass storage
+ device).
+
+Freescale MPL115A barometer sensor
+==================================
+
+This board support package includes hooks that can be used to enable
+testing of a Freescale MPL115A barometer sensor connected via SPI3 with
+chip select on PB6,
+
+Here are the configuration settings that would have to be included to
+enabled support for the barometer::
+
+ System Type -> Peripherals
+ CONFIG_STM32_SPI3=y
+
+ Drivers -> SPI
+ CONFIG_SPI=y
+ CONFIG_SPI_EXCHANGE=y
+
+ Drivers -> Sensors
+ CONFIG_SENSORS=y
+ CONFIG_SENSORS_MPL115A=y
+ CONFIG_NSH_ARCHINIT=y
+
+Note: this driver uses SPI3 then since PB3 pin is also use to JTAG TDO you
+need to disable JTAG support to get this driver working::
+
+ System Type
+ CONFIG_STM32_JTAG_DISABLE=y
+
+LCD/Touchscreen Interface
+=========================
+
+An LCD may be connected via J11. Only the STM32F103 supports the FSMC signals
+needed to drive the LCD.
+
+The LCD features an (1) HY32D module with built-in SSD1289 LCD controller, and (a)
+a XPT2046 touch screen controller.
+
+LCD Connector
+-------------
+
+todo::
+
+ ----------------------------- ------------------------ --------------------------------
+ Connector J11 GPIO CONFIGURATION(s)
+ PIN SIGNAL LEGEND (F103 only) LCD Module
+ --- ------------- ----------- ------------------------ --------------------------------
+ 1 VDD_5 NC N/A 5V ---
+ 2 GND GND N/A GND ---
+ 3 PD14 DATA0 GPIO_NPS_D0 D0 HY32D
+ 4 PD15 DATA1 GPIO_NPS_D1 D1 HY32D
+ 5 PD0 DATA2 GPIO_NPS_D2 D2 HY32D
+ 6 PD1 DATA3 GPIO_NPS_D3 D3 HY32D
+ 7 PE7 DATA4 GPIO_NPS_D4 D4 HY32D
+ 8 PE8 DATA5 GPIO_NPS_D5 D5 HY32D
+ 9 PE9 DATA6 GPIO_NPS_D6 D6 HY32D
+ 10 PE10 DATA7 GPIO_NPS_D7 D7 HY32D
+ 11 PE11 DATA8 GPIO_NPS_D8 D8 HY32D
+ 12 PE12 DATA9 GPIO_NPS_D9 D9 HY32D
+ 13 PE13 DATA10 GPIO_NPS_D10 D10 HY32D
+ 14 PE14 DATA11 GPIO_NPS_D11 D11 HY32D
+ 15 PE15 DATA12 GPIO_NPS_D12 D12 HY32D
+ 16 PD8 DATA13 GPIO_NPS_D13 D13 HY32D
+ 17 PD9 DATA14 GPIO_NPS_D14 D14 HY32D
+ 18 PD10 DATA15 GPIO_NPS_D15 D15 HY32D
+ 19 (3) LCD_CS GPIO_NPS_NE1 CS HY32D
+ 20 PD11 LCD_RS GPIO_NPS_A16 RS HY32D
+ 21 PD5 LCD_R/W GPIO_NPS_NWE WR HY32D
+ 22 PD4 LCD_RD GPIO_NPS_NOE RD HY32D
+ 23 PB1 LCD_RESET (GPIO) RESET HY32D
+ 24 N/C NC N/A TE (unused?)
+ 25 VDD_3.3 BL_VCC N/A BLVDD CA6219 (Drives LCD backlight)
+ 26 GND BL_GND N/A BLGND CA6219
+ 27 PB0 BL_PWM GPIO_TIM3_CH3OUT(2) BL_CNT CA6219
+ 28 PC5 LCDTP_IRQ (GPIO) TP_IRQ XPT2046
+ 29 PC4 LCDTP_CS (GPIO) TP_CS XPT2046
+ 30 PB13 LCDTP_CLK GPIO_SPI2_SCK TP_SCK XPT2046
+ 31 PB15 LCDTP_DIN GPIO_SPI2_MOSI TP_SI XPT2046
+ 32 PB14 LCDTP_DOUT GPIO_SPI2_MISO TP_SO XPT2046
+ 33 VDD_3.3 VDD_3.3 N/A 3.3V ---
+ 34 GND GND N/A GND ---
+ --- ------------- ----------- ------------------------ --------------------------------
+
+ NOTES:
+ 1) Only the F103 version of the board supports the FSMC
+ 2) No remap
+ 3) LCD_CS is controlled by J13 JUMPER4 (under the LCD unfortunately):
+
+ 1->2 : PD7 (GPIO_NPS_NE1) enables the multiplexor : 1E\ enable input (active LOW)
+ 3->4 : PD13 provides 1A0 input (1A1 is grounded). : 1A0 address input
+ So will chip enable to either LCD_CS or
+ Flash_CS.
+ 5->6 : 1Y0 output to LCD_CS : 1Y0 address output
+ 7->8 : 1Y1 output to Flash_CE : 1Y1 address output
+
+ Truth Table:
+ 1E\ 1A0 1A1 1Y0 1Y1
+ --- --- --- --- ---
+ HI N/A N/A HI HI
+ LO LO LO LO HI
+ LO HI LO HI LO
+
+FT80x Integration
+=================
+
+I have used the ViewTool F107 for initial testing of the three displays
+based on FTDI/BridgeTek FT80x GUIs:
+
+Haoyu 5"
+--------
+
+I purchased a Haoyu 5" FT800 display on eBay. Pin out and board
+connectivity is as follows::
+
+ 2x5 Connector J2 using SPI1:
+ PIN NAME VIEWTOOL STM32 PIN NAME VIEWTOOL STM32
+ 1 5V J18 Pin 2 2 GND J8 Pin 8
+ 3 SCK J8 Pin 11 PA5/SCK1 4 MISO J8 Pin 9 PA6/MISO1
+ 5 MOSI J8 Pin 10 PA7/MOSI1 6 CS J8 Pin 12 PA4/NSS1
+ 7 INT J18 Pin 8 PA1 8 PD J18 Pin 6 PC5
+ 9 AUDIO-L 10 GND
+
+ 2x5 Connector J2 using SPI2:
+ PIN NAME VIEWTOOL STM32 PIN NAME VIEWTOOL STM32
+ 1 5V J18 Pin 2 2 GND J8 Pin 2
+ 3 SCK J8 Pin 5 PB13/SCK2 4 MISO J8 Pin 3 PB14/MISO2
+ 5 MOSI J8 Pin 4 PB15/MOSI2 6 CS J8 Pin 6 PB12/NSS2
+ 7 INT J18 Pin 8 PA1 8 PD J18 Pin 6 PC5
+ 9 AUDIO-L 10 GND J18 Pin 4
+
+ The Haoyu display has no audio amplifier on board; Output is raw PWM
+ audio.
+
+ GPIO0 and MODE are pulled low meaning that SPI is the default interface
+ with slave address bit 0 = 0. GPIO1 is not connected.
+
+ This display should have:
+
+ CONFIG_LCD_FT800=y
+ CONFIG_LCD_FT80X_SPI=y
+ CONFIG_LCD_FT80X_WQVGA=y
+ CONFIG_LCD_FT80X_AUDIO_NOSHUTDOWN=y
+ CONFIG_EXAMPLES_FT80X_DEVPATH="/dev/ft800"
+
+MikroElektronkia ConnectEVE FT800
+---------------------------------
+
+todo::
+
+ 2x5 Connector CN2 using SPI1:
+ ---- ------ ----------- ---------- ---- ------ ---------- ----------
+ PIN NAME VIEWTOOL STM32 PIN NAME VIEWTOOL STM32
+ ---- ------ ----------- ---------- ---- ------ ---------- ----------
+ 1 PD# J18 Pin 6 PC5 2 INT# J18 Pin 8 PA1
+ 3 CS# J8 Pin 12 PA4/NSS1 4 SCK 8 Pin 11 PA5/SCK1
+ 5 MISO J8 Pin 9 PA6/MISO1 6 MOSI J8 Pin 10 PA7/MOSI1
+ 7 N/C 8 N/C
+ 9 3.3V J8 Pin 7 10 GND J8 Pin 8
+
+ 2x5 Connector CN2 using SPI2:
+ ---- ------ ----------- ---------- ---- ------ ---------- ----------
+ PIN NAME VIEWTOOL STM32 PIN NAME VIEWTOOL STM32
+ ---- ------ ----------- ---------- ---- ------ ---------- ----------
+ 1 PD# J18 Pin 6 PC5 2 INT# J18 Pin 8 PA1
+ 3 CS# J8 Pin 6 PB12/NSS2 4 SCK J8 Pin 5 PB13/SCK2
+ 5 MISO J8 Pin 3 PB14/MISO2 6 MOSI J8 Pin 4 PB15/MOSI2
+ 7 N/C 8 N/C
+ 9 3.3V J8 Pin 1 10 GND J8 Pin 2
+
+ 1x10 Connector CN3 using SPI1:
+ ---- ------ ----------- -----------
+ PIN NAME VIEWTOOL STM32
+ ---- ------ ----------- -----------
+ 1 CS# J8 Pin 12 PA4/NSS1
+ 2 SCK J8 Pin 11 PA5/SCK1
+ 3 MISO J8 Pin 9 PA6/MISO1
+ 4 MOSI J8 Pin 10 PA7/MOSI1
+ 5 INT# J18 Pin 8 PA1
+ 6 PD# J18 Pin 6 PC5
+ 7 AUDIO+
+ 8 AUDIO-
+ 9 3.3V J8 Pin 7
+ 10 GND J8 Pin 8
+
+ 1x10 Connector CN3 using SPI2:
+ ---- ------ ----------- -----------
+ PIN NAME VIEWTOOL STM32
+ ---- ------ ----------- -----------
+ 1 CS# J8 Pin 6 PB12/NSS2
+ 2 SCK J8 Pin 5 PB13/SCK2
+ 3 MISO J8 Pin 3 PB14/MISO2
+ 4 MOSI J8 Pin 4 PB15/MOSI2
+ 5 INT# J18 Pin 8 PA1
+ 6 PD# J18 Pin 6 PC5
+ 7 AUDIO+
+ 8 AUDIO-
+ 9 3.3V J8 Pin 1
+ 10 GND J8 Pin 2
+
+ Configurations using FT80x should not enable Ethernet, CAN2 or LED
+ support. The LCD connector, J28 pin 9, and the upper row of J18 are
+ also assumed to be unused:
+
+ J8 upper row (SPI2) conflicts:
+
+ Pin 2 PB14 also used by LCD
+ Pin 4 PB15 also used by LCD
+ Pin 5 PB13 also used by Ethernet, CAN2, LCD and LED4
+ Pin 6 PB12 also used by Ethernet, CAN2, J28 pin 9, and LED3
+
+ J8 lower row (SPI1) conflicts:
+
+ Pin 9 PA6 also used by J8 pin 9 and LED1
+ Pin 10 PA7 also used Ethernet
+ Pin 11 PA5 also used by J8 pin 7
+ Pin 12 PA4 also used by J8 pin 5 (J8 pin 5 not used)
+
+ J18 upper row is not used in this configuration. Cannot be used with
+ SPI1. Not used with SPI2 because SPI2 has the same conflicts as the
+ lower row so why bother?
+
+ Pin 5 PA4 also used by SPI1/NSS1
+ Pin 7 PA5 also used by SPI1/SCK1
+ Pin 9 PA6 also used by SPI1/MOSI1 and LED1
+
+ J18 lower row conflicts:
+
+ Pin 6 PC5 also used by Ethernet and the LCD interface
+ Pin 8 PA1 also used by Ethernet
+ Pin 10 PA0 also used by Ethernet and Wake-up button (not used)
+
+ Remapped SPI1 pins are not supported, but that would permit these options:
+
+ PA15/NSS1 also used by LCD
+ PB3/SCK1 also used by USART1 and JTAG
+ PB4/MISO1 also used by JTAG
+ PB5/MOSI1 also used by USART1, Ethernet, and J28 pin 10
+
+ There is a LM4864 audio amplifier on board so audio outputs are ready for
+ use with a small 1W 8Ohm speaker. GPIO0 should be configured as an
+ output because it is used to control the shutdown pin of the LM4864 audio
+ output.
+
+ GPIO0 is not connected.
+
+ This display should have:
+
+ CONFIG_LCD_FT800=y
+ CONFIG_LCD_FT80X_SPI=y
+ CONFIG_LCD_FT80X_WQVGA=y
+ CONFIG_LCD_FT80X_AUDIO_GPIOSHUTDOWN=y
+ CONFIG_LCD_FT80X_AUDIO_GPIO=0
+ CONFIG_EXAMPLES_FT80X_DEVPATH="/dev/ft800"
+
+ Reverdi RVT43ULFNWC01
+ ---------------------
+
+ I used this FT801 board with a 20 pin breakout module.
+
+ 2x10 Connector CN2 using SPI1:
+ ---- --------- ----------- ----------- ---- --------- ----------- -----------
+ PIN NAME VIEWTOOL STM32 PIN NAME VIEWTOOL STM32
+ ---- --------- ----------- ----------- ---- --------- ----------- -----------
+ 1 VDD J8 Pin 7 * 2 GND J8 Pin 8
+ 3 SPI_CLK J8 Pin 11 PA5/SCK1 4 MISO J8 Pin 9 PA6/MISO1
+ 5 MOSI/IO1 J8 Pin 10 PA7/MOSI1 6 CS J8 Pin 12 PA4/NSS1
+ 7 INT J18 Pin 8 PA1 8 PD J18 Pin 6 PC5
+ 9 NC N/C 10 AUDIO OUT N/C
+ 11 GPIO0/IO2 N/C 12 GPIO0/IO3 N/C
+ 13 GPIO2 N/C 14 GPIO3 N/C
+ 15 NC N/C 16 NC N/C
+ 17 BLVDD N/C ** 18 BLVDD N/C **
+ 19 BLGND N/C ** 20 BLGND N/C **
+
+ 2x10 Connector CN2 using SPI2:
+ ---- --------- ----------- ----------- ---- --------- ----------- -----------
+ PIN NAME VIEWTOOL STM32 PIN NAME VIEWTOOL STM32
+ ---- --------- ----------- ---------- ---- --------- ----------- ------------
+ 1 VDD J8 Pin 1 * 2 GND J8 Pin 2
+ 3 SPI_CLK J8 Pin 5 PB13/SCK2 4 MISO J8 Pin 3 PB14/MISO2
+ 5 MOSI/IO1 J8 Pin 4 PB15/MOSI2 6 CS J8 Pin 6 PB12/NSS2
+ 7 INT J18 Pin 8 PA1 8 PD J18 Pin 6 PC5
+ 9 NC N/C 10 AUDIO OUT N/C
+ 11 GPIO0/IO2 N/C 12 GPIO0/IO3 N/C
+ 13 GPIO2 N/C 14 GPIO3 N/C
+ 15 NC N/C 16 NC N/C
+ 17 BLVDD N/C ** 18 BLVDD N/C **
+ 19 BLGND N/C ** 20 BLGND N/C **
+
+ * 0.0-4.0V
+ ** May be connected to VDD, 0.0-7.0V
+
+ I did not see a backlight without BLVDD or BLGND connected. Possibly
+ this depends on the 3.3V current provided by the board? Obvious
+ connections would be J18 pins 2 and 4.
+
+ This display should have:
+
+ CONFIG_LCD_FT801=y
+ CONFIG_LCD_FT80X_SPI=y
+ CONFIG_LCD_FT80X_WQVGA=y
+ CONFIG_LCD_FT80X_AUDIO_NOSHUTDOWN=y
+ CONFIG_EXAMPLES_FT80X_DEVPATH="/dev/ft801"
+
+MAX3421E Integration
+====================
+
+Board Connections
+-----------------
+
+todo::
+
+ USBHostShield-v13 (See schematic).
+
+ DuinoFun UHS mini v2.0. No schematics available. This is how the pins
+ are labeled:
+
+ INT MAX_RST
+ o o o o o o o o o o o o
+ o o o o o
+ V_BUS INT GPX MAX_RST SS
+
+ o o o o o o o o o o o o
+ SS CLK* MISO MOSI* VCC GND**
+
+ * NOTE: There is a error in the silkscreen: The pin labeled CLK is
+ actually MOSI; the pin labeled MOSI is the clock
+ ** Not labeled
+
+ Using SPI1 on J8 pins 7-12, discretes on J18
+
+ ------ ----------- ----------- ------------------ ----------------------
+ NAME VIEWTOOL STM32 USBHostShield-v13 DuinoFun UHS mini v2.0
+ ------ ----------- ----------- ------------------ ----------------------
+ CS# J8 Pin 12 PA4/NSS1 D10 SS
+ SCK J8 Pin 11 PA5/SCK1 D13 CLK (label MOSI)
+ MISO J8 Pin 9 PA6/MISO1 D12 MISO
+ MOSI J8 Pin 10 PA7/MOSI1 D11 MOSI (label CLK)
+ INT# J18 Pin 10 PA0 D9 INT
+ RST# J18 Pin 8 PA1 D7 MAX_RST
+ GPX J18 Pin 6 PC5 D8 GPX (not used)
+ VBUS J18 Pin 2 5V VIN V_BUS
+ 3.3V J8 Pin 7 N/C VCC
+ GND J8 Pin 8 GND GND (no label)
+
+ Using SPI2 on J8 pins 1-6, discretes on J18
+
+ ------ ----------- ----------- ------------------ ----------------------
+ NAME VIEWTOOL STM32 USBHostShield-v13 DuinoFun UHS mini v2.0
+ ------ ----------- ----------- ------------------ ----------------------
+ CS# J8 Pin 6 PB12/NSS2 D10 SS
+ SCK J8 Pin 5 PB13/SCK2 D13 CLK (label MOSI)
+ MISO J8 Pin 3 PB14/MISO2 D12 MISO
+ MOSI J8 Pin 4 PB15/MOSI2 D11 MOSI (label CLK)
+ INT# J18 Pin 10 PA0 D9 INT
+ RST# J18 Pin 8 PA1 D7 MAX_RST
+ GPX J18 Pin 6 PC5 D8 GPX (not used)
+ VBUS J18 Pin 2 5V VIN V_BUS
+ 3.3V J8 Pin 1 N/C VCC
+ GND J8 Pin 2 GND GND (no label)
+
+ 5V VBUS power is also needed. This might be directly connected to the USB
+ host connector (as assumed here), or switched via additional logic. Then
+ GPX pin might also be necessary if VBUS detect is used with self-powered
+ devices.
+
+ Configuration Options
+ ---------------------
+ These options have to be added to the basic NSH configuration in order to
+ support the MAX3421E:
+
+ CONFIG_EXPERIMENTAL=y # EXPERIMENTAL required for now (might change)
+ CONFIG_NSH_ARCHINIT=y # Board level initialization required
+ CONFIG_STM32_SPI1=y # SPI for the MAX3421E (could use SPI2)
+ CONFIG_USBHOST=y # General USB host support
+ CONFIG_USBHOST_ISOC_DISABLE=y # Does not support Isochronous endpoints
+ CONFIG_USBHOST_MAX3421E=y # MAX3421E support
+ CONFIG_USBHOST_MSC=y # USB MSC class
+
+ Using SPI1:
+
+ CONFIG_VIEWTOOL_MAX3421E_SPI1=y
+ CONFIG_VIEWTOOL_MAX3421E_FREQUENCY=20000000
+ CONFIG_VIEWTOOL_MAX3421E_RST=y
+ # CONFIG_VIEWTOOL_MAX3421E_PWR is not set
+ CONFIG_VIEWTOOL_MAX3421E_CONNMON_STACKSIZE=2048
+ CONFIG_VIEWTOOL_MAX3421E_CONNMON_PRIORITY=100
+
+ Settings not listed above can be left at their default values.
+
+Toolchains
+==========
+
+NOTE about Windows native toolchains
+------------------------------------
+
+There are several limitations to using a Windows based toolchain in a
+Cygwin environment. The three biggest are:
+
+1. The Windows toolchain cannot follow Cygwin paths. Path conversions are
+ performed automatically in the Cygwin makefiles using the 'cygpath'
+ utility but you might easily find some new path problems. If so, check
+ out 'cygpath -w'
+
+2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic
+ links are used in NuttX (e.g., include/arch). The make system works
+ around these problems for the Windows tools by copying directories
+ instead of linking them. But this can also cause some confusion for
+ you: For example, you may edit a file in a "linked" directory and find
+ that your changes had no effect. That is because you are building the
+ copy of the file in the "fake" symbolic directory. If you use a\
+ Windows toolchain, you should get in the habit of making like this::
+
+ make clean_context all
+
+ An alias in your .bashrc file might make that less painful.
+
+Configurations
+==============
+
+Information Common to All Configurations
+----------------------------------------
+
+Each SAM3U-EK configuration is maintained in a sub-directory and
+can be selected as follow::
+
+ tools/configure.sh viewtool-stm32f107:<subdir>
+
+Before starting the build, make sure that your PATH environment variable
+includes the correct path to your toolchain.
+
+And then build NuttX by simply typing the following. At the conclusion of
+the make, the nuttx binary will reside in an ELF file called, simply, nuttx.::
+
+ make
+
+The <subdir> that is provided above as an argument to the tools/configure.sh
+must be is one of the following.
+
+NOTES::
+
+ 1. These configurations use the mconf-based configuration tool. To
+ change any of these configurations using that tool, you should:
+
+ a. Build and install the kconfig-mconf tool. See nuttx/README.txt
+ see additional README.txt files in the NuttX tools repository.
+
+ b. Execute 'make menuconfig' in nuttx/ in order to start the
+ reconfiguration process.
+
+ 2. Unless stated otherwise, all configurations generate console
+ output on USART1.
+
+ 3. Unless otherwise stated, the configurations are setup for
+ Cygwin under Windows:
+
+ Build Setup:
+ CONFIG_HOST_WINDOWS=y : Windows operating system
+ CONFIG_WINDOWS_CYGWIN=y : POSIX environment under windows
+
+ 4. All of these configurations use the ARM EABI GCC toolchain for Windows
+ (unless stated otherwise in the description of the configuration). That
+ toolchain selection can easily be reconfigured using 'make menuconfig'.
+ Here are the relevant current settings:
+
+ System Type -> Toolchain:
+ CONFIG_ARM_TOOLCHAIN_GNU_EABI=y : GNU EABI toolchain for Windows
+
+ See also the "NOTE about Windows native toolchains" in the section call
+ "GNU Toolchain Options" above.
+
+ 4. These configurations all assume that the STM32F107VCT6 is mounted on
+ board. This is configurable; you can select the STM32F103VCT6 as an
+ alternative.
+
+ 5. These configurations all assume that you are loading code using
+ something like the ST-Link v2 JTAG. None of these configurations are
+ setup to use the DFU bootloader but should be easily reconfigured to
+ use that bootloader if so desired.
+
+Configuration Sub-directories
+-----------------------------
+
+f80x
+-----
+
+This configuration was added in order to verify the FTDI/Bridgetick
+Ft80x driver using apps/examples/ft80x with apps/graphics/ft80x. It
+is very similar to the NSH configuration with support for the FTDI
+FT80x LCD enabled on SPI1.
+
+This configuration is properly setup for the MikroElektronika
+ConnectEVE LCD. To use the Reverdi FT801 LCD, the following changes
+would be required to the configuration::
+
+ -CONFIG_LCD_FT800=y
+ +CONFIG_LCD_FT801=y
+
+ -CONFIG_LCD_FT80X_AUDIO_GPIOSHUTDOWN=y
+ -CONFIG_LCD_FT80X_AUDIO_GPIO=0
+ +CONFIG_LCD_FT80X_AUDIO_NOSHUTDOWN=y
+
+ -CONFIG_EXAMPLES_FT80X_DEVPATH="/dev/ft800"
+ +CONFIG_EXAMPLES_FT80X_DEVPATH="/dev/ft801"
+
+STATUS::
+ 2018-03-09: The ConnectEVE display is basically working. There are
+ some specific issues with some of the demos in apps/examples/ft80x
+ that still need to be addressed. I have the Riverdi display FT801
+ display in hand as well, but have not tested with the display yet.
+
+ I have seen issues also where the board does not recover after a
+ reset. It required a full power cycle to get functionality back.
+ This is not too surprising since there is no reset signal to the
+ FT80x (there is power down/up). It might be necessary to perform
+ a software reset of the FT80x during initialization.
+
+ 1028-03-10: Most of issues have been worked out in the FT80x demos
+ and the driver appears 100% functional.
+
+netnsh
+------
+
+This configuration directory provide the NuttShell (NSH) with
+networking support.
+
+NOTES::
+ 1. This configuration will work only on the version the viewtool
+ board with the STM32F107VCT6 installed. If you have a board
+ with the STM32F103VCT6 installed, please use the nsh configuration
+ described below.
+
+ 2. There is no PHY on the base viewtool stm32f107 board. You must
+ also have the "ViewTool DP83848 Ethernet Module" installed on J2
+ in order to support networking.
+
+ 3. Since networking is enabled, you will see some boot-up delays when
+ the network connection is established. These delays can be quite
+ large if no network is attached (A production design to bring up the
+ network asynchronously to avoid these start up delays).
+
+ 4. This configuration uses the default USART1 serial console. That
+ is easily changed by reconfiguring to (1) enable a different
+ serial peripheral, and (2) selecting that serial peripheral as
+ the console device.
+
+ 5. By default, this configuration is set up to build on Windows
+ under either a Cygwin or MSYS environment using a recent, Windows-
+ native, generic ARM EABI GCC toolchain (such as the CodeSourcery
+ toolchain). Both the build environment and the toolchain
+ selection can easily be changed by reconfiguring:
+
+ CONFIG_HOST_WINDOWS=y : Windows operating system
+ CONFIG_WINDOWS_CYGWIN=y : POSIX environment under Windows
+ CONFIG_ARM_TOOLCHAIN_GNU_EABI=y : GNU EABI toolchain for Windows
+
+ 6. USB support is disabled by default. See the section above entitled,
+ "USB Interface"
+
+nsh
+----
+
+This configuration directory provide the basic NuttShell (NSH).
+
+NOTES::
+
+ 1. This configuration will work with either the version of the board
+ with STM32F107VCT6 or STM32F103VCT6 installed. The default
+ configuration is for the STM32F107VCT6. To use this configuration
+ with a STM32F103VCT6, it would have to be modified as follows:
+
+ System Type -> STM32 Configuration Options
+ CONFIG_ARCH_CHIP_STM32F103VC=y
+ CONFIG_ARCH_CHIP_STM32F107VC=n
+
+ 2. This configuration uses the default USART1 serial console. That
+ is easily changed by reconfiguring to (1) enable a different
+ serial peripheral, and (2) selecting that serial peripheral as
+ the console device.
+
+ 3. By default, this configuration is set up to build on Windows
+ under either a Cygwin or MSYS environment using a recent, Windows-
+ native, generic ARM EABI GCC toolchain (such as the CodeSourcery
+ toolchain). Both the build environment and the toolchain
+ selection can easily be changed by reconfiguring:
+
+ CONFIG_HOST_WINDOWS=y : Windows operating system
+ CONFIG_WINDOWS_CYGWIN=y : POSIX environment under Windows
+ CONFIG_ARM_TOOLCHAIN_GNU_EABI=y : GNU EABI toolchain for Windows
+
+ 4. USB support is disabled by default. See the section above entitled,
+ "USB Interface"
+
+ 3. This configured can be re-configured to use either the Viewtool LCD
+ module. NOTE: The LCD module can only be used on the STM32F103 version
+ of the board. The LCD requires FSMC support.
+
+ System Type -> STM32 Chip Selection:
+ CONFIG_ARCH_CHIP_STM32F103VC=y : Select STM32F103VCT6
+
+ System Type -> Peripherals:
+ CONFIG_STM32_FSMC=y : Enable FSMC LCD interface
+
+ Device Drivers -> LCD Driver Support
+ CONFIG_LCD=y : Enable LCD support
+ CONFIG_NX_LCDDRIVER=y : LCD graphics device
+ CONFIG_LCD_MAXCONTRAST=1
+ CONFIG_LCD_MAXPOWER=255
+ CONFIG_LCD_LANDSCAPE=y : Landscape orientation
+ CONFIG_LCD_SSD1289=y : Select the SSD1289
+ CONFIG_SSD1289_PROFILE1=y
+
+ Graphics Support
+ CONFIG_NX=y
+
+ Graphics Support -> Supported Pixel Depths
+ CONFIG_NX_DISABLE_1BPP=y : Only 16BPP supported
+ CONFIG_NX_DISABLE_2BPP=y
+ CONFIG_NX_DISABLE_4BPP=y
+ CONFIG_NX_DISABLE_8BPP=y
+ CONFIG_NX_DISABLE_24BPP=y
+ CONFIG_NX_DISABLE_32BPP=y
+
+ Graphics Support -> Font Selections
+ CONFIG_NXFONTS_CHARBITS=7
+ CONFIG_NXFONT_SANS22X29B=y
+ CONFIG_NXFONT_SANS23X27=y
+
+ Application Configuration -> Examples
+ CONFIG_EXAMPLES_NXLINES=y
+ CONFIG_EXAMPLES_NXLINES_BGCOLOR=0x0320
+ CONFIG_EXAMPLES_NXLINES_LINEWIDTH=16
+ CONFIG_EXAMPLES_NXLINES_LINECOLOR=0xffe0
+ CONFIG_EXAMPLES_NXLINES_BORDERWIDTH=4
+ CONFIG_EXAMPLES_NXLINES_BORDERCOLOR=0xffe0
+ CONFIG_EXAMPLES_NXLINES_CIRCLECOLOR=0xf7bb
+ CONFIG_EXAMPLES_NXLINES_BPP=16
+
+ STATUS: Not working; reads 0x8999 as device ID. This may perhaps
+ be due to incorrect jumper settings
+
+ 6. This configuration has been used for verifying the touchscreen on
+ on the Viewtool LCD module. NOTE: The LCD module can really only
+ be used on the STM32F103 version of the board. The LCD requires
+ FSMC support (the touchscreen, however, does not but the touchscreen
+ is not very meaningful with no LCD).
+
+ System Type -> STM32 Chip Selection:
+ CONFIG_ARCH_CHIP_STM32F103VC=y : Select STM32F103VCT6
+
+ With the following modifications, you can include the touchscreen
+ test program at apps/examples/touchscreen as an NSH built-in
+ application. You can enable the touchscreen and test by modifying
+ the default configuration in the following ways:
+
+ Device Drivers
+ CONFIG_SPI=y : Enable SPI support
+ CONFIG_SPI_EXCHANGE=y : The exchange() method is supported
+
+ CONFIG_INPUT=y : Enable support for input devices
+ CONFIG_INPUT_ADS7843E=y : Enable support for the XPT2046
+ CONFIG_ADS7843E_SPIDEV=2 : Use SPI2 for communication
+ CONFIG_ADS7843E_SPIMODE=0 : Use SPI mode 0
+ CONFIG_ADS7843E_FREQUENCY=1000000 : SPI BAUD 1MHz
+ CONFIG_ADS7843E_SWAPXY=y : If landscape orientation
+ CONFIG_ADS7843E_THRESHX=51 : These will probably need to be tuned
+ CONFIG_ADS7843E_THRESHY=39
+
+ System Type -> Peripherals:
+ CONFIG_STM32_SPI2=y : Enable support for SPI2
+
+ Library Support:
+ CONFIG_SCHED_WORKQUEUE=y : Work queue support required
+
+ Application Configuration:
+ CONFIG_EXAMPLES_TOUCHSCREEN=y : Enable the touchscreen built-int test
+
+ Defaults should be okay for related touchscreen settings. Touchscreen
+ debug output on USART1 can be enabled with:
+
+ Build Setup:
+ CONFIG_DEBUG_FEATURES=y : Enable debug features
+ CONFIG_DEBUG_INFO=y : Enable verbose debug output
+ CONFIG_DEBUG_INPUT=y : Enable debug output from input devices
+
+ STATUS: Working
+
+highpri
+-------
+
+This configuration was used to verify the NuttX high priority, nested
+interrupt feature. This is a board-specific test and probably not
+of much interest now other than for reference.
+
+This configuration targets the viewtool board with the STM32F103VCT6
+
+tcpblaster
+----------
+
+The tcpblaster example derives from the nettest example and basically
+duplicates that application when the nettest PERFORMANCE option is selected.
+tcpblaster has a little better reporting of performance stats, however.
+
+This configuration derives directly from the netnsh configuration and most
+of the notes there should apply equally here.
+
+General usage instructions:
+1. On the host:
+
+ a. cd to apps/examples/tcpblaster
+
+ b. Run the host tcpserver[.exe] program that was built in that directory
+
+2. On the target:
+
+ a. Run the tcpclient built in application.
+
+3. When you get tire of watch the numbers scroll by, just kill the tcpserver
+ on the host.
diff --git a/content/docs/latest/_sources/platforms/arm/stm32f1/index.rst.txt b/content/docs/latest/_sources/platforms/arm/stm32f1/index.rst.txt
new file mode 100644
index 00000000..a9b645bf
--- /dev/null
+++ b/content/docs/latest/_sources/platforms/arm/stm32f1/index.rst.txt
@@ -0,0 +1,22 @@
+==========
+ST STM32F1
+==========
+
+Supported MCUs
+==============
+
+TODO
+
+Peripheral Support
+==================
+
+TODO
+
+Supported Boards
+================
+
+.. toctree::
+ :glob:
+ :maxdepth: 1
+
+ boards/*/*
diff --git a/content/docs/latest/_sources/platforms/arm/stm32f4/boards/axoloti/index.rst.txt b/content/docs/latest/_sources/platforms/arm/stm32f4/boards/axoloti/index.rst.txt
new file mode 100644
index 00000000..07df510e
--- /dev/null
+++ b/content/docs/latest/_sources/platforms/arm/stm32f4/boards/axoloti/index.rst.txt
@@ -0,0 +1,21 @@
+=======
+Axoloti
+=======
+
+This README discusses issues unique to NuttX configurations for the
+Axoloti open source synthesizer board featuring the STM32F427IGH6
+MCU. The STM32F427IGH6 has a 180MHz Cortex-M4 core with 1MiB Flash
+memory and 256KiB of SRAM. The board features:
+
+ - ADAU1961 24-bit 96 kHz stereo CODEC
+ - 1/4" in/out jacks for analog audio signals
+ - 3.5 mm jack for analog audio signals
+ - 8 MiB of SDRAM (Alliance Memory AS4C4M16SA)
+ - Serial MIDI in/out ports
+ - SD Card slot
+ - Two user LEDs and one (GPIO) push-button
+ - USB OTG FS with Micro-AB connector (USB device mode operation)
+ - USB OTG HS with Type-A connector (USB host mode operation)
+ - Easy access to most IO pins
+
+Refer to http://www.axoloti.com/ for further information about this board.
diff --git a/content/docs/latest/_sources/platforms/arm/stm32f4/boards/clicker2-stm32/index.rst.txt b/content/docs/latest/_sources/platforms/arm/stm32f4/boards/clicker2-stm32/index.rst.txt
new file mode 100644
index 00000000..507687ca
--- /dev/null
+++ b/content/docs/latest/_sources/platforms/arm/stm32f4/boards/clicker2-stm32/index.rst.txt
@@ -0,0 +1,798 @@
+=====================
+Mikroe Clicker2 STM32
+=====================
+
+This is the README file for the port of NuttX to the Mikroe Clicker2 STM32
+board based on the STMicro STM32F407VGT6 MCU.
+
+Reference: https://shop.mikroe.com/development-boards/starter/clicker-2/stm32f4
+
+Contents
+========
+
+- Serial Console
+- LEDs
+- Buttons
+- Using JTAG
+- Configurations
+
+Serial Console
+==============
+
+The are no RS-232 drivers on-board. An RS-232 Click board is available:
+https://shop.mikroe.com/click/interface/rs232 or you can cannot an off-
+board TTL-to-RS-232 converter as follows::
+
+ USART2: mikroBUS1 PD6/RX and PD5/TX
+ USART3: mikroBUS2 PD9/RX and PD8TX
+
+ GND, 3.3V, and 5V. Are also available
+
+By default, USART3 on mikroBUS2 is used as the serial console in each
+configuration unless stated otherwise in the description of the
+configuration.
+
+LEDs
+====
+
+The Mikroe Clicker2 STM32 has two user controllable LEDs::
+
+ LD1/PE12, Active high output illuminates
+ LD2/PE15, Active high output illuminates
+
+If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any
+way. If CONFIG_ARCH_LEDs is defined, then NuttX will control the 2 LEDs on
+board the Clicker2 for STM32. The following definitions describe how NuttX
+controls the LEDs:
+
+ =================== ======================= ======== ========
+ SYMBOL Meaning LD1 LD2
+ =================== ======================= ======== ========
+ LED_STARTED NuttX has been started OFF OFF
+ LED_HEAPALLOCATE Heap has been allocated OFF OFF
+ LED_IRQSENABLED Interrupts enabled OFF OFF
+ LED_STACKCREATED Idle stack created ON OFF
+ LED_INIRQ In an interrupt N/C ON
+ LED_SIGNAL In a signal handler N/C N/C
+ LED_ASSERTION An assertion failed N/C N/C
+ LED_PANIC The system has crashed OFF Blinking
+ LED_IDLE STM32 is is sleep mode N/U N/U
+ =================== ======================= ======== ========
+
+Thus is LD1 is illuminated, the Clicker2 has completed boot-up. IF LD2
+is glowly softly, then interrupts are being taken; the level of illumination
+depends amount of time processing interrupts. If LD1 is off and LD2 is
+blinking at about 2Hz, then the system has crashed.
+
+Buttons
+=======
+
+The Mikroe Clicker2 STM32 has two buttons available to software::
+
+ T2/E0, Low sensed when pressed
+ T3/PA10, Low sensed when pressed
+
+Using JTAG
+==========
+
+The Clicker2 comes with the mikroBootloader installed. That bootloader
+has not been used and is possibly incompatible with the Clicker2-STM32
+linker script at boards/arm/stm32/clicker2-stm32/scripts/flash.ld. Often code must
+be built to execute at an offset in to FLASH when a bootloader is used.
+Certainly that is the case for the ST-Micro DFU bootloader but I am not
+aware of the requirements for use with the mikroBootloader.
+
+JTAG has been used in the development of this board support. The
+Clicker2-STM32 board offers a 2x5 JTAG connector. You may use Dupont
+jumpers to connect this port to JTAG as described here:
+
+ https://www.mikroe.com/how-to-use-st-link-v2-with-clicker-2-for-stm32-a-detailed-walkthrough/
+ http://www.playembedded.org/blog/en/2016/02/06/mikroe-clicker-2-for-stm32-and-stlink-v2/
+
+NOTE that the FLASH probably has read protection enabled locked. You may
+need to follow the instructions at the second link to unlock it. You can
+also use the STM32 ST-Link CLI tool on Windows to remove the read protection
+using the -OB command::
+
+ $ ./ST-LINK_CLI.exe -c SN=53FF6F064966545035320387 SWD LPM
+ STM32 ST-LINK CLI v2.3.0
+ STM32 ST-LINK Command Line Interface
+
+ ST-LINK SN : 53FF6F064966545035320387
+ ST-LINK Firmware version : V2J24S4
+ Connected via SWD.
+ SWD Frequency = 4000K.
+ Target voltage = 3.2 V.
+ Connection mode : Normal.
+ Debug in Low Power mode enabled.
+ Device ID:0x413
+ Device family :STM32F40xx/F41xx
+
+ $ ./ST-LINK_CLI.exe -OB RDP=0
+ STM32 ST-LINK CLI v2.3.0
+ STM32 ST-LINK Command Line Interface
+
+ ST-LINK SN : 53FF6F064966545035320387
+ ST-LINK Firmware version : V2J24S4
+ Connected via SWD.
+ SWD Frequency = 4000K.
+ Target voltage = 3.2 V.
+ Connection mode : Normal.
+ Device ID:0x413
+ Device family :STM32F40xx/F41xx
+ Updating option bytes...
+ Option bytes updated successfully.
+
+NOTE:
+
+1. You can get the ST-Link Utilities here:
+ http://www.st.com/en/embedded-software/stsw-link004.html
+
+2. The ST-LINK Utility command line interface is located at:
+ [Install_Directory]\STM32 ST-LINK Utility\ST-LINK Utility\ST-LINK_CLI.exe
+
+3. You can get a summary of all of the command options by running
+ ST-LINK_CLI.exe with no arguments.
+
+4. You can get the serial number of the ST-Link when from the information
+ window if you connect via the ST-Link Utility::
+
+ 11:04:28 : ST-LINK SN : 53FF6F064966545035320387
+ 11:04:28 : ST-LINK Firmware version : V2J24S4
+ 11:04:28 : Connected via SWD.
+ 11:04:28 : SWD Frequency = 100 KHz.
+ 11:04:28 : Connection mode : Normal.
+ 11:04:28 : Debug in Low Power mode enabled.
+ 11:04:30 : Device ID:0x413
+ 11:04:30 : Device family :STM32F40xx/F41xx
+ 11:04:30 : Can not read memory!
+ Disable Read Out Protection and retry.
+
+You can avoid the mess of jumpers using the mikroProg to ST-Link v2 adapter
+along with a 2x5, 10-wire ribbon cable connector:
+
+ https://shop.mikroe.com/add-on-boards/adapter/mikroprog-st-link-v2-adapter
+
+Then you can use the ST-Link Utility or other debugger software to write
+the NuttX binary to FLASH. OpenOCD can be used with the ST-Link to provide
+a debug environment. The debug adaptor is NOT compatible with other JTAG
+debuggers such as the Segger J-Link.
+
+Configurations
+==============
+
+Information Common to All Configurations
+----------------------------------------
+
+Each Clicker2 configuration is maintained in a sub-directory and can be
+selected as follow::
+
+ tools/configure.sh clicker2-stm32:<subdir>
+
+Before building, make sure the PATH environment variable includes the
+correct path to the directory than holds your toolchain binaries.
+
+And then build NuttX by simply typing the following. At the conclusion of
+the make, the nuttx binary will reside in an ELF file called, simply, nuttx.::
+
+ make oldconfig
+ make
+
+The <subdir> that is provided above as an argument to the tools/configure.sh
+must be is one of the following.
+
+NOTES:
+
+1. These configurations use the mconf-based configuration tool. To
+ change any of these configurations using that tool, you should:
+
+ a. Build and install the kconfig-mconf tool. See nuttx/README.txt
+ see additional README.txt files in the NuttX tools repository.
+
+ b. Execute 'make menuconfig' in nuttx/ in order to start the
+ reconfiguration process.
+
+2. Unless stated otherwise, all configurations generate console
+ output on USART3, channel 0) as described above under "Serial
+ Console". The relevant configuration settings are listed below::
+
+ CONFIG_STM32_USART3=y
+ CONFIG_STM32_USART3_SERIALDRIVER=y
+ CONFIG_STM32_USART=y
+
+ CONFIG_USART3_SERIALDRIVER=y
+ CONFIG_USART3_SERIAL_CONSOLE=y
+
+ CONFIG_USART3_RXBUFSIZE=256
+ CONFIG_USART3_TXBUFSIZE=256
+ CONFIG_USART3_BAUD=115200
+ CONFIG_USART3_BITS=8
+ CONFIG_USART3_PARITY=0
+ CONFIG_USART3_2STOP=0
+
+3. All of these configurations are set up to build under Linux using the
+ "GNU Tools for ARM Embedded Processors" that is maintained by ARM
+ (unless stated otherwise in the description of the configuration).
+
+ https://developer.arm.com/open-source/gnu-toolchain/gnu-rm
+
+ That toolchain selection can easily be reconfigured using
+ 'make menuconfig'. Here are the relevant current settings:
+
+ Build Setup::
+
+ CONFIG_HOST_LINUX =y : Linux environment
+
+ System Type -> Toolchain::
+ CONFIG_ARM_TOOLCHAIN_GNU_EABI=y : GNU ARM EABI toolchain
+
+Configuration sub-directories
+-----------------------------
+
+
+knsh
+----
+
+This is identical to the nsh configuration below except that NuttX
+is built as a protected mode, monolithic module and the user applications
+are built separately.
+
+It is recommends to use a special make command; not just 'make' but make
+with the following two arguments::
+
+ make pass1 pass2
+
+In the normal case (just 'make'), make will attempt to build both user-
+and kernel-mode blobs more or less interleaved. This actual works!
+However, for me it is very confusing so I prefer the above make command:
+Make the user-space binaries first (pass1), then make the kernel-space
+binaries (pass2)
+
+NOTES:
+
+1. At the end of the build, there will be several files in the top-level
+ NuttX build directory:
+
+ PASS1::
+
+ nuttx_user.elf - The pass1 user-space ELF file
+ nuttx_user.hex - The pass1 Intel HEX format file (selected in defconfig)
+ User.map - Symbols in the user-space ELF file
+
+ PASS2::
+
+ nuttx - The pass2 kernel-space ELF file
+ nuttx.hex - The pass2 Intel HEX file (selected in defconfig)
+ System.map - Symbols in the kernel-space ELF file
+
+ The J-Link programmer will accept files in .hex, .mot, .srec, and .bin
+ formats. The St-Link programmer will accept files in hex and .bin
+ formats.
+
+2. Combining .hex files. If you plan to use the .hex files with your
+ debugger or FLASH utility, then you may need to combine the two hex
+ files into a single .hex file. Here is how you can do that.
+
+ a. The 'tail' of the nuttx.hex file should look something like this
+ (with my comments added)::
+
+ $ tail nuttx.hex
+ # 00, data records
+ ...
+ :10 9DC0 00 01000000000800006400020100001F0004
+ :10 9DD0 00 3B005A0078009700B500D400F300110151
+ :08 9DE0 00 30014E016D0100008D
+ # 05, Start Linear Address Record
+ :04 0000 05 0800 0419 D2
+ # 01, End Of File record
+ :00 0000 01 FF
+
+ Use an editor such as vi to remove the 05 and 01 records.
+
+ b. The 'head' of the nuttx_user.hex file should look something like
+ this (again with my comments added)::
+
+ $ head nuttx_user.hex
+ # 04, Extended Linear Address Record
+ :02 0000 04 0801 F1
+ # 00, data records
+ :10 8000 00 BD89 01084C800108C8110208D01102087E
+ :10 8010 00 0010 00201C1000201C1000203C16002026
+ :10 8020 00 4D80 01085D80010869800108ED83010829
+ ...
+
+ Nothing needs to be done here. The nuttx_user.hex file should
+ be fine.
+
+ c. Combine the edited nuttx.hex and un-edited nuttx_user.hex
+ file to produce a single combined hex file::
+
+ $ cat nuttx.hex nuttx_user.hex >combined.hex
+
+ Then use the combined.hex file with the to write the FLASH image.
+ If you do this a lot, you will probably want to invest a little time
+ to develop a tool to automate these steps.
+
+mrf24j40-mac
+------------
+
+This is a version of nsh that was used for testing the MRF24J40 MAC be
+as a character device. The most important configuration differences are
+summarized below:
+
+1. Support for the BEE click and SPI are in enabled in the mikroBUS1 slot:
+
+ CONFIG_CLICKER2_STM32_MB1_BEE=y
+ CONFIG_CLICKER2_STM32_MB1_SPI=y
+
+2. SPI support and STM32 SPI3, in particular, are enabled:
+
+ CONFIG_SPI=y
+ CONFIG_SPI_EXCHANGE=y
+
+ CONFIG_STM32_SPI=y
+ CONFIG_STM32_SPI3=y
+
+4. Support for the IEEE802.15.4 "upper half" character driver is enabled:
+
+ CONFIG_WIRELESS=y
+ CONFIG_WIRELESS_IEEE802154=y
+ CONFIG_IEEE802154_MAC_DEV=y
+ CONFIG_IEEE802154_NTXDESC=3
+ CONFIG_IEEE802154_IND_PREALLOC=20
+ CONFIG_IEEE802154_IND_IRQRESERVE=10
+ CONFIG_IEEE802154_DEFAULT_EADDR=0x00fade00deadbeef
+
+5. Support for the lower half MRF24J40 character driver is enabled
+
+ CONFIG_DRIVERS_WIRELESS=y
+ CONFIG_DRIVERS_IEEE802154=y
+ CONFIG_IEEE802154_MRF24J40=y
+
+6. Support for the i8sak test program at apps/ieee802154 is enabled:
+
+ CONFIG_IEEE802154_LIBMAC=y
+ CONFIG_IEEE802154_LIBUTILS=y
+ CONFIG_IEEE802154_I8SAK=y
+ CONFIG_IEEE802154_I8SAK_PRIORITY=100
+ CONFIG_IEEE802154_I8SAK_STACKSIZE=2048
+
+7. Initialization hooks are provided to enable the MRF24J40 and to
+ register the radio character driver.
+
+ CONFIG_NSH_ARCHINIT=y
+
+8. Configuration instructions: WPAN configuration must be performed
+ using the i8sak program. Detailed instructions are provided in a
+ README.txt file at apps/wireless/ieee802154/i8sak. You should make
+ sure that you are familiar with the content of that README.txt file.
+
+ Here is a quick "cheat sheet" for associated to setting up a
+ coordinator and associating with the WPAN:
+
+ 1. Configure the Coordinator. On coordinator device do:
+
+ nsh> i8 /dev/ieee0 startpan cd:ab
+ nsh> i8 acceptassoc
+
+ 2. Associate an endpoint device with the WPAN. On the endpoint
+ device:
+
+ nsh> i8 /dev/ieee0 assoc
+
+mrf24j40-6lowpan
+----------------
+
+This is another version of nsh that is very similar to the mrf24j40-mac
+configuration but is focused on testing the IEEE 802.15.4 MAC
+integration with the 6LoWPAN network stack. It derives directly from the
+mrf24j40-mac and all NOTES provided there apply. Additional differences
+are summarized below:
+
+NOTES:
+
+1. You must have two clicker2-stm32 boards each with an MRF24J40 click
+ board in order to run these tests.
+
+2. This configuration differs from the mrf24j40-mac configuration in
+ that this configuration, like the usbnsh configuration, uses a USB
+ serial device for console I/O. Such a configuration is useful on the
+ Clicker2 STM32 which has no builtin RS-232 drivers and eliminates the
+ tangle of cables and jumpers needed to debug multi-board setups.
+
+ Most other NOTES for the usbnsh configuration should apply. Specific
+ differences between the usbnsh or mrf24j40-mac configurations and this
+ configuration are listed in these NOTES.
+
+3. On most serial terminal programs that I have used, the USB
+ connection will be lost when the target board is reset. When that
+ happens, you may have to reset your serial terminal program to adapt
+ to the new USB connection. Using TeraTerm, I actually have to exit
+ the serial program and restart it in order to detect and select the
+ re-established USB serial connection.
+
+4. This configuration does NOT have USART3 output enabled. This
+ configuration supports logging of debug output to a circular
+ buffer in RAM. This feature is discussed fully in this Wiki page:
+ https://cwiki.apache.org/confluence/display/NUTTX/SYSLOG . Relevant
+ configuration settings are summarized below::
+
+ Device Drivers:
+ CONFIG_RAMLOG=y : Enable the RAM-based logging feature.
+ CONFIG_RAMLOG_SYSLOG=y : This enables the RAM-based logger as the
+ system logger.
+ CONFIG_RAMLOG_NONBLOCKING=y : Needs to be non-blocking for dmesg
+ CONFIG_RAMLOG_BUFSIZE=8192 : Buffer size is 8KiB
+
+ NOTE: This RAMLOG feature is really only of value if debug output
+ is enabled. But, by default, no debug output is disabled in this
+ configuration. Therefore, there is no logic that will add anything
+ to the RAM buffer. This feature is configured and in place only
+ to support any future debugging needs that you may have.
+
+ If you don't plan on using the debug features, then by all means
+ disable this feature and save 8KiB of RAM!
+
+ NOTE: There is an issue with capturing data in the RAMLOG: If
+ the system crashes, all of the crash dump information will go into
+ the RAMLOG and you will be unable to access it! You can tell that
+ the system has crashed because (a) it will be unresponsive and (b)
+ the LD2 will be blinking at about 2Hz.
+
+5. IPv6 networking is enabled with TCP/IP, UDP, 6LoWPAN, and NSH
+ Telnet support.
+
+6. Configuration instructions: Basic PAN configuration is similar to the
+ mrf24j40-mac configuration with the exception that you use the network
+ interface name 'wpan0'. This tells the i8sak app to use a socket
+ instead of a character device to perform the IOCTL operations with the
+ MAC. Additionally, after the PAN has been configured with the i8sak
+ utility, you must explicitly bring the network up on each node::
+
+ nsh> ifup wpan0
+
+7. examples/udp is enabled. This will allow two MRF24J40 nodes to
+ exchange UDP packets. Basic instructions:
+
+ On the server node::
+
+ nsh> ifconfig
+ nsh> udpserver &
+
+ The ifconfig command will show the IP address of the server. Then on
+ the client node use this IP address to start the client::
+
+ nsh> udpclient <server-ip> &
+
+ Where <server-ip> is the IP address of the server that you got above.
+ NOTE: There is no way to stop the UDP test once it has been started
+ other than by resetting the board.
+
+ Cheat Sheet. Here is a concise summary of all all the steps needed to
+ run the UDP test (C=Coordinator; E=Endpoint)::
+
+ C: nsh> i8 wpan0 startpan cd:ab
+ C: nsh> i8 acceptassoc
+ E: nsh> i8 wpan0 assoc
+ C: nsh> ifup wpan0
+ C: nsh> ifconfig <-- To get the <server-ip>
+ E: nsh> ifup wpan0
+ C: nsh> udpserver &
+ E: nsh> udpclient <server-ip> &
+
+ The nsh> dmesg command can be use at any time on any node to see
+ any debug output that you have selected.
+
+8. examples/nettest is enabled. This will allow two MRF24J40 nodes to
+ exchange TCP packets. Basic instructions:
+
+ On the server node::
+
+ nsh> ifconfig
+ nsh> tcpserver &
+
+ The ifconfig command will show the IP address of the server. Then on
+ the client node use this IP address to start the client::
+
+ nsh> tcpclient <server-ip> &
+
+ Where <server-ip> is the IP address of the server that you got above.
+ NOTE: Unlike the UDP test, there the TCP test will terminate
+ automatically when the packet exchange is complete.
+
+ Cheat Sheet. Here is a concise summary of all all the steps needed to
+ run the TCP test (C=Coordinator; E=Endpoint)::
+
+ C: nsh> i8 wpan0 startpan cd:ab
+ C: nsh> i8 acceptassoc
+ E: nsh> i8 wpan0 assoc
+ C: nsh> ifup wpan0
+ C: nsh> ifconfig <-- To get the <server-ip>
+ E: nsh> ifup wpan0
+ C: nsh> tcpserver &
+ E: nsh> tcpclient <server-ip> &
+
+ The nsh> dmesg command can be use at any time on any node to see
+ any debug output that you have selected.
+
+9. The NSH Telnet daemon (server) is enabled. However, it cannot be
+ started automatically. Rather, it must be started AFTER the network
+ has been brought up using the NSH 'telnetd' command. You would want
+ to start the Telent daemon only if you want the node to serve Telent
+ connections to an NSH shell on the node.::
+
+ nsh> ifconfig
+ nsh> telnetd
+
+ Note the 'ifconfig' is executed to get the IP address of the node.
+ This is necessary because the IP address is assigned by the the
+ Coordinator and may not be known a priori.
+
+10. This configuration also includes the Telnet client program. This
+ will allow you to execute a NSH one a node from the command line on
+ a different node. Like::
+
+ nsh> telnet <server-ip>
+
+ Where <server-ip> is the IP address of the server that you got for
+ the ifconfig comma on the remote node. Once the telnet session
+ has been started, you can end the session with::
+
+ nsh> exit
+
+ Cheat Sheet. Here is a concise summary of all all the steps needed to
+ run the TCP test (C=Coordinator; E=Endpoint)::
+
+ C: nsh> i8 wpan0 startpan
+ C: nsh> i8 acceptassoc
+ E: nsh> i8 wpan0 assoc
+ C: nsh> ifup wpan0
+ C: nsh> ifconfig <-- To get the <server-ip>
+ E: nsh> ifup wpan0
+ C: nsh> telnetd <-- Starts the Telnet daemon
+ E: nsh> telnet <server-ip> <-- Runs the Telnet client
+
+ STATUS:
+
+ 2017-06-21: Basic UDP functionality has been achieved with HC06
+ compression and short address. Additional testing is required for
+ other configurations (see text matrix below).
+
+ 2017-06-23: Added test for TCP functionality. As of yet unverified.
+
+ 2017-06-24: There are significant problems with the 6LoWPAN TCP send
+ logic. A major redesign was done to better handle ACKs and
+ retransmissions, and to work with TCP dynamic windowing.
+
+ 2017-05-25: After some rather extensive debug, the TCP test was made
+ to with (HC06 and short addressing).
+
+ 2017-06-26: Verified with HC06 and extended addressing and HC1 with
+ both addressing modes.
+
+ 2017-06-27: Added the Telnet client application to the configuration.
+ Initial testing reveal a problem that required re-design of the
+ Telnet daemon: It did not yet support IPv6! But after adding this
+ support, Telnet worked just fine.
+
+ Test Matrix:
+ The following configurations have been tested::
+
+ =========== ========== ==== ====
+ COMPRESSION ADDRESSING UDP TCP
+ =========== ========== ==== ====
+ hc06 short 6/21 6/25
+ extended 6/22 6/26
+ hc1 short 6/23 6/26
+ extended 6/23 6/26
+ ipv6 short --- ---
+ extended --- ---
+ telnet short N/A 6/27 (hc06)
+ extended N/A ---
+ =========== ========== ==== ====
+
+ Other configuration options have not been specifically addressed
+ (such non-compressable ports, non-MAC based IPv6 addresses, etc.)
+
+ One limitation of this test is that it only tests NuttX 6LoWPAN
+ against NuttX 6LoWPAN. It does not prove that NuttX 6LoWPAN is
+ compatible with other implementations of 6LoWPAN. The tests could
+ potentially be verifying only that the design is implemented
+ incorrectly in compatible way on both the client and server sides.
+
+mrf24j40-starhub and mrf24j40-starpoint
+----------------------------------------
+
+These two configurations implement hub and and star endpoint in a
+star topology. Both configurations derive from the mrf24j40-6lowpan
+configuration and most of the notes there apply here as well.
+
+1. You must have three clicker2-stm32 boards each with an MRF24J40
+ click board in order to run these tests: One that serves as the
+ star hub and at least two star endpoints.
+
+2. The star point configuration differs from the primarily in the
+ mrf24j40-6lowpan in following is also set:
+
+ CONFIG_NET_STAR=y
+ CONFIG_NET_STARPOINT=y
+
+ The CONFIG_NET_STARPOINT selection informs the endpoint that it
+ must send all frames to the hub of the star, rather than directly
+ to the recipient.
+
+ The star hub configuration, on the other hand, differs from the
+ mrf24j40-6lowpan in these fundamental ways:
+
+ CONFIG_NET_STAR=y
+ CONFIG_NET_STARHUB=y
+ CONFIG_NET_IPFORWARD=y
+
+ The CONFIG_NET_IPFORWARD selection informs the hub that if it
+ receives any packets that are not destined for the hub, it should
+ forward those packets appropriately.
+
+3. Telnet: The star point configuration supports the Telnet daemon,
+ but not the Telnet client; the star hub configuration supports
+ the Telnet client, but not the Telnet daemon. Therefore, the
+ star hub can Telnet to any point in the star, the star endpoints
+ cannot initiate telnet sessions.
+
+4. TCP and UDP Tests: The same TCP and UDP tests as described for
+ the mrf24j40-6lowpan coniguration are supported on the star
+ endpoints, but NOT on the star hub. Therefore, all network testing
+ is between endpoints with the hub acting, well, only like a hub.
+
+ The modified usage of the TCP test is show below with E1 E2
+ representing the two star endpoints and C: representing the
+ coordinator/hub.::
+
+ C: nsh> i8 wpan0 startpan cd:ab
+ C: nsh> i8 acceptassoc
+ E1: nsh> i8 wpan0 assoc
+ E2: nsh> i8 wpan0 assoc
+ C: nsh> ifup wpan0
+ E1: nsh> ifup wpan0
+ E1: nsh> ifconfig <-- To get the IP address of E1 endpoint
+ E1: nsh> telnetd <-- Starts the Telnet daemon
+ E2: nsh> ifup wpan0
+ E2: nsh> ifconfig <-- To get the IP address of E2 endpoint
+ E2: nsh> telnetd <-- Starts the Telnet daemon
+ E1: nsh> tcpserver &
+ E2: nsh> tcpclient <server-ip> &
+
+ Where <server-ip> is the IP address of the E1 endpoint.
+
+ Similarly for the UDP test:::
+
+ E1: nsh> udpserver &
+ E2: nsh> udpclient <server-ip> &
+
+ The nsh> dmesg command can be use at any time on any node to see
+ any debug output that you have selected.
+
+ Telenet sessions may be initiated only from the hub to a star
+ endpoint::
+
+ C: nsh> telnet <server-ip> <-- Runs the Telnet client
+
+ Where <server-ip> is the IP address of either the E1 or E2 endpoints.
+
+ STATUS:
+ 2017-06-29: Configurations added. Initial testing indicates that
+ the TCP Telnet client can successfully establish sessions with
+ the two star endpoints. When testing communications between the
+ two star endpoints via the hub, the frames are correctly directed
+ to the hub. However, they are not being forwarded to the other
+ endpoint.
+
+ 2017-06-30: The failure to forward is understood: When the star
+ endpoint sent the IPv6 destination address, the HC06 compression
+ logic elided the address -- meaning that it could be reconstructed
+ based on the receiver's assigned short address. However, when
+ intercepted by the hub, the uncompressed address does not know
+ the short address of the recipient and instead uses the short
+ address of the hub. This means two things: (1) it looks like
+ the hub address is the destination address, and (2) the
+ uncompressed UDP packet has a bad checksum.
+
+ This required a change to assure that the destination IPv6 address
+ is not elided in the case of the star endpoint configuration. After
+ some additional fixes for byte ordering in 16-bit and 64-bit
+ compressed IPv6 addresses, then all tests are working as expected:
+ TCP, UDP, Telnet.
+
+ 2017-08-05: It looks like I have lost one of my Clicker2-STM32 boards.
+ This means that I will not be able to do any regression testing as
+ changes are made to the radio interfaces and 6LoWPAN :(
+
+ 2017-08-26: There was only a single buffer for reassemblying larger
+ packets. This could be a problem issue for the hub configuration
+ which really needs the capability concurrently reassemble multiple
+ incoming streams. The design was extended to support multiple
+ reassembly buffers but have not yet been verified on this platform.
+
+nsh
+----
+
+Configures the NuttShell (nsh) located at examples/nsh. This
+configuration is focused on low level, command-line driver testing. It
+has no network.
+
+NOTES:
+
+1. Support for NSH built-in applications is provided:
+
+ Binary Formats::
+
+ CONFIG_BUILTIN=y : Enable support for built-in programs
+
+ Application Configuration::
+
+ CONFIG_NSH_BUILTIN_APPS=y : Enable starting apps from NSH command line
+
+ No built applications are enabled in the base configuration, however.
+
+2. C++ support for applications is enabled::
+
+ CONFIG_HAVE_CXX=y
+ CONFIG_HAVE_CXXINITIALIZE=y
+
+usbnsh
+------
+
+This is another NSH example. If differs from other 'nsh' configurations
+n that this configurations uses a USB serial device for console I/O.
+Such a configuration is useful on the Clicker2 STM32 which has no
+builtin RS-232 drivers.
+
+NOTES:
+
+1. One most serial terminal programs that I have used, the USB
+ connection will be lost when the target board is reset. When that
+ happens, you may have to reset your serial terminal program to adapt
+ to the new USB connection. Using TeraTerm, I actually have to exit
+ the serial program and restart it in order to detect and select the
+ re-established USB serial connection.
+
+2. This configuration does have USART3 output enabled and set up as
+ the system logging device::
+
+ CONFIG_SYSLOG_CHAR=y : Use a character device for system logging
+ CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" : USART3 will be /dev/ttyS0
+
+ However, there is nothing to generate SYSLOG output in the default
+ configuration so nothing should appear on USART3 unless you enable
+ some debug output or enable the USB monitor.
+
+3. Enabling USB monitor SYSLOG output. If tracing is enabled, the USB
+ device will save encoded trace output in in-memory buffer; if the
+ USB monitor is enabled, that trace buffer will be periodically
+ emptied and dumped to the system logging device (USART3 in this
+ configuration)::
+
+ CONFIG_USBDEV_TRACE=y : Enable USB trace feature
+ CONFIG_USBDEV_TRACE_NRECORDS=128 : Buffer 128 records in memory
+ CONFIG_NSH_USBDEV_TRACE=n : No builtin tracing from NSH
+ CONFIG_NSH_ARCHINIT=y : Automatically start the USB monitor
+ CONFIG_USBMONITOR=y : Enable the USB monitor daemon
+ CONFIG_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size
+ CONFIG_USBMONITOR_PRIORITY=50 : USB monitor daemon priority
+ CONFIG_USBMONITOR_INTERVAL=2 : Dump trace data every 2 seconds
+
+ CONFIG_USBMONITOR_TRACEINIT=y : Enable TRACE output
+ CONFIG_USBMONITOR_TRACECLASS=y
+ CONFIG_USBMONITOR_TRACETRANSFERS=y
+ CONFIG_USBMONITOR_TRACECONTROLLER=y
+ CONFIG_USBMONITOR_TRACEINTERRUPTS=y
+
+Using the Prolifics PL2303 Emulation
+------------------------------------
+
+You could also use the non-standard PL2303 serial device instead of
+the standard CDC/ACM serial device by changing::
+
+ CONFIG_CDCACM=n : Disable the CDC/ACM serial device class
+ CONFIG_CDCACM_CONSOLE=n : The CDC/ACM serial device is NOT the console
+ CONFIG_PL2303=y : The Prolifics PL2303 emulation is enabled
+ CONFIG_PL2303_CONSOLE=y : The PL2303 serial device is the console
diff --git a/content/docs/latest/_sources/platforms/arm/stm32f4/boards/mikroe-stm32f4/index.rst.txt b/content/docs/latest/_sources/platforms/arm/stm32f4/boards/mikroe-stm32f4/index.rst.txt
new file mode 100644
index 00000000..6686c6b3
--- /dev/null
+++ b/content/docs/latest/_sources/platforms/arm/stm32f4/boards/mikroe-stm32f4/index.rst.txt
@@ -0,0 +1,372 @@
+==============
+mikroe-stm32f4
+==============
+
+This README discusses issues unique to NuttX configurations for the
+MikroElektronika Mikromedia for STM32F4 development board. This is
+another board support by NuttX that uses the same STM32F407VGT6 MCU
+as does the STM32F4-Discovery board. This board, however, has very
+different on-board peripherals than does the STM32F4-Discovery:
+
+- TFT display with touch panel,
+- VS1053 stereo audio codec with headphone jack,
+- SD card slot,
+- Serial FLASH memory,
+- USB OTG FS with micro-AB connector, and
+- Battery connect and batter charger circuit.
+
+See the http://www.mikroe.com/mikromedia/stm32-m4/ for more information
+about this board.
+
+LEDs
+====
+
+The Mikroe-STM32F4 board has no user accessible LEDs onboard, only a power
+and "charging" LED. All visual user output must be performed through the TFT
+display.
+
+External LEDs could be added via the expansion headers on the side of the
+board, but as this would be a custom configuration, LEDs are not supported
+in this port.
+
+PWM
+===
+
+The Mikroe-STM32F4 has no real on-board PWM devices, but it does have PWM
+pins routed to the expansion I/O headers on the side of the board.
+
+UARTs
+=====
+
+The Mikroe-STM32F4 board has no onboard RS-232 line driver, however the
+expansion I/O header provides access to USART2 on pins PD5/PD6. The port
+includes support for USART2 configured as /dev/ttyS0.
+
+USART2
+------
+
+========== =====
+UART/USART PINS
+========== =====
+RX PD6
+TX PD5
+========== =====
+
+Default USART/UART Configuration
+--------------------------------
+
+USART2 is enabled in all configurations (see \*/defconfig). RX and TX are
+configured on pins PD6 and PD5, respectively (see include/board.h).
+
+Timer Inputs/Outputs
+====================
+
+::
+ TIM1
+ CH1 PA8, PE9
+ CH2 PA9[1], PE11
+ CH3 PA10[1], PE13
+ CH4 PA11[1], PE14
+ TIM2
+ CH1 PA0[1], PA15, PA5[1]
+ CH2 PA1, PB3[1]
+ CH3 PA2, PB10[1]
+ CH4 PA3, PB11
+ TIM3
+ CH1 PA6[1], PB4, PC6
+ CH2 PA7[1], PB5, PC7[1]
+ CH3 PB0, PC8
+ CH4 PB1, PC9
+ TIM4
+ CH1 PB6[1], PD12[1]
+ CH2 PB7, PD13[1]
+ CH3 PB8, PD14[1]
+ CH4 PB9[1], PD15[1]
+ TIM5
+ CH1 PA0[1], PH10[2]
+ CH2 PA1, PH11[2]
+ CH3 PA2, PH12[2]
+ CH4 PA3, PI0
+ TIM8
+ CH1 PC6, PI5
+ CH2 PC7[1], PI6
+ CH3 PC8, PI7
+ CH4 PC9, PI2
+ TIM9
+ CH1 PA2, PE5
+ CH2 PA3, PE6
+ TIM10
+ CH1 PB8, PF6
+ TIM11
+ CH1 PB9[1], PF7
+ TIM12
+ CH1 PH6[2], PB14
+ CH2 PC15, PH9[2]
+ TIM13
+ CH1 PA6[1], PF8
+ TIM14
+ CH1 PA7[1], PF9
+
+ [1] Indicates pins that have other on-board functions and should be used only
+ with care (See table 5 in the Mikroe-STM32F4 User Guide). The rest are
+ free I/O pins.
+ [2] Port H pins are not supported by the MCU
+
+MIO283QT-2/MIO283QT-9A
+======================
+
+The original Mikroe-SMT32F4 board as an on-board MIO283QT-2 TFT LCD that can
+be configured and used. This is a 320x240 resolution display with color
+capability to 262K colors, though the mio283qt-2 driver in NuttX only
+supports 16-bit color depth, or 65K colors. Changes to both the
+mio283qt-2 driver and the driver interface layer would need to be made
+to support 24 BPP mode.
+
+UPDATE: New boards now support a MIO283QT-9A TFT LCD that is not compatible
+with the MIO283QT-2. It uses a different LCD controller. The default in
+all of these configurations is the MIO283QT-2. But MIO283QT-9A is also
+supported and you can switch from the MIO283QT-2 to the MIO283QT-9A by simply
+modifying the NuttX configuration
+
+Configurations
+==============
+
+Each Mikroe-STM32F4 configuration is maintained in a sub-directory and
+can be selected as follow::
+
+ tools/configure.sh mikroe-stm32f4:<subdir>
+
+If this is a Windows native build, then configure.bat should be used
+instead of configure.sh::
+
+ configure.bat Mikroe-STM32F4\<subdir>
+
+Where <subdir> is one of the following:
+
+fulldemo
+--------
+
+This is an example that includes an NSH shell over USB that also
+enables all features of the Mikroe-STM32F4 board including the LCD,
+on-board 1M Flash with SMART filesystem, Aux RS-232 serial port on the
+expansion header, etc. A couple of the NX graphics commands are made
+available via the NSH prompt for performing LCD demonstrations, and the
+nximage example is used as a splash-screen at startup.
+
+kostest
+-------
+
+NOTE: This configuration compiles, but has not been fully tested
+on the hardware yet.
+
+This configuration directory, performs a simple OS test using
+apps/examples/ostest with NuttX build as a kernel-mode monolithic
+module and the user applications are built separately. Is
+is recommended to use a special make command; not just 'make' but
+make with the following two arguments::
+
+ make pass1 pass2
+
+In the normal case (just 'make'), make will attempt to build both user-
+and kernel-mode blobs more or less interleaved. This actual works!
+However, for me it is very confusing so I prefer the above make command:
+Make the user-space binaries first (pass1), then make the kernel-space
+binaries (pass2)
+
+NOTES:
+
+1. This configuration uses the mconf-based configuration tool. To
+ change this configuration using that tool, you should:
+
+ a. Build and install the kconfig-mconf tool. See nuttx/README.txt
+ see additional README.txt files in the NuttX tools repository.
+
+ b. Execute 'make menuconfig' in nuttx/ in order to start the
+ reconfiguration process.
+
+2. This is the default platform/toolchain in the configuration::
+
+ CONFIG_HOST_WINDOWS=y : Windows
+ CONFIG_WINDOWS_CYGWIN=y : Cygwin environment on Windows
+ CONFIG_ARM_TOOLCHAIN_GNU_EABI=y : GNU EABI toolchain for Windows
+
+ This is easily changed by modifying the configuration.
+
+3. At the end of the build, there will be several files in the top-level
+ NuttX build directory::
+
+ PASS1:
+ nuttx_user.elf - The pass1 user-space ELF file
+ nuttx_user.hex - The pass1 Intel HEX format file (selected in defconfig)
+ User.map - Symbols in the user-space ELF file
+
+ PASS2:
+ nuttx - The pass2 kernel-space ELF file
+ nuttx.hex - The pass2 Intel HEX file (selected in defconfig)
+ System.map - Symbols in the kernel-space ELF file
+
+4. Combining .hex files. If you plan to use the STM32 ST-Link Utility to
+ load the .hex files into FLASH, then you need to combine the two hex
+ files into a single .hex file. Here is how you can do that.
+
+ a. The 'tail' of the nuttx.hex file should look something like this
+ (with my comments added)::
+
+ $ tail nuttx.hex
+ # 00, data records
+ ...
+ :10 9DC0 00 01000000000800006400020100001F0004
+ :10 9DD0 00 3B005A0078009700B500D400F300110151
+ :08 9DE0 00 30014E016D0100008D
+ # 05, Start Linear Address Record
+ :04 0000 05 0800 0419 D2
+ # 01, End Of File record
+ :00 0000 01 FF
+
+ Use an editor such as vi to remove the 05 and 01 records.
+
+ b. The 'head' of the nuttx_user.hex file should look something like
+ this (again with my comments added)::
+
+ $ head nuttx_user.hex
+ # 04, Extended Linear Address Record
+ :02 0000 04 0801 F1
+ # 00, data records
+ :10 8000 00 BD89 01084C800108C8110208D01102087E
+ :10 8010 00 0010 00201C1000201C1000203C16002026
+ :10 8020 00 4D80 01085D80010869800108ED83010829
+ ...
+
+ Nothing needs to be done here. The nuttx_user.hex file should
+ be fine.
+
+ c. Combine the edited nuttx.hex and un-edited nuttx_user.hex
+ file to produce a single combined hex file::
+
+ $ cat nuttx.hex nuttx_user.hex >combined.hex
+
+ Then use the combined.hex file with the STM32 ST-Link tool. If
+ you do this a lot, you will probably want to invest a little time
+ to develop a tool to automate these steps.
+
+nsh
+---
+
+This is an NSH example that uses USART2 as the console. Note that
+the Mikroe-STM32F4 board doesn't actually have onboard line drivers
+or a connector for USART2, but it does route the USART2 signals to
+the expansion header. To use this demo, you would need to connect
+an external 3.3V RS-232 line driver to the USART's I/O lines on the
+expansion header.
+
+NOTE: This demo doesn't quite work yet. I can get output to the
+USART, but so far, I have not gotten nsh to actually come up.
+
+nx
+--
+
+An example using the NuttX graphics system (NX). This example
+focuses on general window controls, movement, mouse and keyboard
+input.::
+
+ CONFIG_LCD_LANDSCAPE=y : 320x240 landscape orientation
+ CONFIG_LCD_MIO283QT2=y : MIO283QT-2 is the default
+
+You can the newer MIO283QT-9A by enabling it in the configuration.::
+
+ CONFIG_LCD_MIO283QT2=n : Disable the MIO283QT-2
+ CONFIG_LCD_MIO283QT9A=y : Enable the MIO283QT-9A
+
+nxlines
+-------
+
+An example using the NuttX graphics system (NX). This example focuses on
+placing lines on the background in various orientations using the
+on-board TFT LCD.::
+
+ CONFIG_LCD_LANDSCAPE=y : 320x240 landscape orientation
+ CONFIG_LCD_MIO283QT2=y : MIO283QT-2 is the default
+
+You can the newer MIO283QT-9A by enabling it in the configuration.::
+
+ CONFIG_LCD_MIO283QT2=n : Disable the MIO283QT-2
+ CONFIG_LCD_MIO283QT9A=y : Enable the MIO283QT-9A
+
+nxtext
+------
+
+Another example using the NuttX graphics system (NX). This
+example focuses on placing text on the background while pop-up
+windows occur. Text should continue to update normally with
+or without the popup windows present.
+
+usbnsh
+-------
+
+This is another NSH example. If differs from other 'nsh' configurations
+in that this configurations uses a USB serial device for console I/O.
+Such a configuration is useful on the stm32f4discovery which has no
+builtin RS-232 drivers.
+
+NOTES:
+
+1. This configuration uses the mconf-based configuration tool. To
+ change this configuration using that tool, you should:
+
+ a. Build and install the kconfig-mconf tool. See nuttx/README.txt
+ see additional README.txt files in the NuttX tools repository.
+
+ b. Execute 'make menuconfig' in nuttx/ in order to start the
+ reconfiguration process.
+
+2. By default, this configuration uses the ARM EABI toolchain
+ for Windows and builds under Cygwin (or probably MSYS). That
+ can easily be reconfigured, of course.::
+
+ CONFIG_HOST_WINDOWS=y : Builds under Windows
+ CONFIG_WINDOWS_CYGWIN=y : Using Cygwin
+ CONFIG_ARM_TOOLCHAIN_GNU_EABI=y : GNU EABI toolchain for Windows
+
+3. This configuration does have UART2 output enabled and set up as
+ the system logging device::
+
+ CONFIG_SYSLOG_CHAR=y : Use a character device for system logging
+ CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" : UART2 will be /dev/ttyS0
+
+ However, there is nothing to generate SYSLOG output in the default
+ configuration so nothing should appear on UART2 unless you enable
+ some debug output or enable the USB monitor.
+
+4. Enabling USB monitor SYSLOG output. If tracing is enabled, the USB
+ device will save encoded trace output in in-memory buffer; if the
+ USB monitor is enabled, that trace buffer will be periodically
+ emptied and dumped to the system logging device (UART2 in this
+ configuration)::
+
+ CONFIG_USBDEV_TRACE=y : Enable USB trace feature
+ CONFIG_USBDEV_TRACE_NRECORDS=128 : Buffer 128 records in memory
+ CONFIG_NSH_USBDEV_TRACE=n : No builtin tracing from NSH
+ CONFIG_NSH_ARCHINIT=y : Automatically start the USB monitor
+ CONFIG_USBMONITOR=y : Enable the USB monitor daemon
+ CONFIG_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size
+ CONFIG_USBMONITOR_PRIORITY=50 : USB monitor daemon priority
+ CONFIG_USBMONITOR_INTERVAL=2 : Dump trace data every 2 seconds
+
+ CONFIG_USBMONITOR_TRACEINIT=y : Enable TRACE output
+ CONFIG_USBMONITOR_TRACECLASS=y
+ CONFIG_USBMONITOR_TRACETRANSFERS=y
+ CONFIG_USBMONITOR_TRACECONTROLLER=y
+ CONFIG_USBMONITOR_TRACEINTERRUPTS=y
+
+5. By default, this project assumes that you are *NOT* using the DFU bootloader.
+
+Using the Prolifics PL2303 Emulation
+------------------------------------
+
+You could also use the non-standard PL2303 serial device instead of
+the standard CDC/ACM serial device by changing::
+
+ CONFIG_CDCACM=y : Disable the CDC/ACM serial device class
+ CONFIG_CDCACM_CONSOLE=y : The CDC/ACM serial device is NOT the console
+ CONFIG_PL2303=y : The Prolifics PL2303 emulation is enabled
+ CONFIG_PL2303_CONSOLE=y : The PL2303 serial device is the console
diff --git a/content/docs/latest/_sources/platforms/arm/stm32f4/boards/nucleo-f401re/index.rst.txt b/content/docs/latest/_sources/platforms/arm/stm32f4/boards/nucleo-f401re/index.rst.txt
new file mode 100644
index 00000000..9bfbbdc5
--- /dev/null
+++ b/content/docs/latest/_sources/platforms/arm/stm32f4/boards/nucleo-f401re/index.rst.txt
@@ -0,0 +1,394 @@
+================
+ST Nucleo F401RE
+================
+
+This page discusses issues unique to NuttX configurations for the ST
+NucleoF401RE and NucleoF411RE boards from ST Micro. See
+
+ http://www.st.com/web/catalog/mmc/FM141/SC1169/SS1577/LN1810/PF258797
+ http://www.st.com/web/catalog/mmc/FM141/SC1169/SS1577/LN1877/PF260049
+
+These two boards are very similar, both supporting STM32 "Dynamic Efficiency
+Line" parts but differing in the specific STM32 chip mounted on board. The
+chips themselves are also very similar with the STM32F411RE having some
+additional capability:
+
+NucleoF401RE:
+
+- Microprocessor: 32-bit ARM Cortex M4 at 84MHz STM32F104RE
+- Memory: 512 KB Flash and 96 KB SRAM
+- ADC: 1×12-bit, 2.4 MSPS A/D converter: up to 10 channels
+- DMA: 16-stream DMA controllers with FIFOs and burst support
+- Timers: Up to 11 timers: up to six 16-bit, two 32-bit timers, two
+ watchdog timers, and a SysTick timer
+- GPIO: Up to 81 I/O ports with interrupt capability
+- I2C: Up to 3 × I2C interfaces
+- USARTs: Up to 3 USARTs
+- SPIs: Up to 4 SPIs (2 I2S)
+- SDIO interface
+- USB: USB 2.0 full-speed device/host/OTG controller with on-chip PHY
+- CRC calculation unit
+- RTC
+
+The NucleoF411RE also has additional DMA and SPI peripheral capabilities.
+
+Board features, however, are identical:
+
+- Peripherals: 1 led, 1 push button
+- Debug: Serial wire debug and JTAG interfaces
+- Expansion I/F Ardino and Morpho Headers
+
+Uses a STM32F103 to provide a ST-Link for programming, debug similar to the
+OpenOcd FTDI function - USB to JTAG front-end.
+
+See http://mbed.org/platforms/ST-Nucleo-F401RE and
+http://developer.mbed.org/platforms/ST-Nucleo-F411RE for more
+information about these boards.
+
+mbed
+====
+
+The Nucleo-F401RE includes boot loader from mbed:
+
+ https://mbed.org/platforms/ST-Nucleo-F401RE/
+ https://mbed.org/handbook/Homepage
+
+Using the mbed loader:
+
+1. Connect the Nucleo-F4x1RE to the host PC using the USB connector.
+2. A new file system will appear called NUCLEO; open it with Windows
+ Explorer (assuming that you are using Windows).
+3. Drag and drop nuttx.bin into the MBED window. This will load the
+ nuttx.bin binary into the Nucleo-F4x1RE. The NUCLEO window will
+ close then re-open and the Nucleo-F4x1RE will be running the new code.
+
+Hardware
+========
+
+GPIO
+----
+
+::
+
+ SERIAL_TX=PA_2 USER_BUTTON=PC_13
+ SERIAL_RX=PA_3 LED1 =PA_5
+
+ A0=PA_0 USART2RX D0=PA_3 D8 =PA_9
+ A1=PA_1 USART2TX D1=PA_2 D9 =PC_7
+ A2=PA_4 D2=PA_10 WIFI_CS=D10=PB_6 SPI_CS
+ A3=PB_0 WIFI_INT=D3=PB_3 D11=PA_7 SPI_MOSI
+ A4=PC_1 SDCS=D4=PB_5 D12=PA_6 SPI_MISO
+ A5=PC_0 WIFI_EN=D5=PB_4 LED1=D13=PA_5 SPI_SCK
+ LED2=D6=PB_10 I2C1_SDA=D14=PB_9 Probe
+ D7=PA_8 I2C1_SCL=D15=PB_8 Probe
+
+ From: https://mbed.org/platforms/ST-Nucleo-F401RE/
+
+Buttons
+-------
+
+B1 USER: the user button is connected to the I/O PC13 (pin 2) of the STM32
+microcontroller.
+
+LEDs
+----
+
+The Nucleo F401RE and Nucleo F411RE provide a single user LED, LD2. LD2
+is the green LED connected to Arduino signal D13 corresponding to MCU I/O
+PA5 (pin 21) or PB13 (pin 34) depending on the STM32target.
+
+- When the I/O is HIGH value, the LED is on.
+- When the I/O is LOW, the LED is off.
+
+These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
+defined. In that case, the usage by the board port is defined in
+include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related
+events as follows when the red LED (PE24) is available:
+
+ =================== ======================= ===========
+ SYMBOL Meaning LD2
+ =================== ======================= ===========
+ LED_STARTED NuttX has been started OFF
+ LED_HEAPALLOCATE Heap has been allocated OFF
+ LED_IRQSENABLED Interrupts enabled OFF
+ LED_STACKCREATED Idle stack created ON
+ LED_INIRQ In an interrupt No change
+ LED_SIGNAL In a signal handler No change
+ LED_ASSERTION An assertion failed No change
+ LED_PANIC The system has crashed Blinking
+ LED_IDLE MCU is is sleep mode Not used
+ =================== ======================= ===========
+
+Thus if LD2, NuttX has successfully booted and is, apparently, running
+normally. If LD2 is flashing at approximately 2Hz, then a fatal error
+has been detected and the system has halted.
+
+Serial Consoles
+===============
+
+USART1
+------
+
+Pins and Connectors::
+
+ RXD: PA11 CN10 pin 14
+ PB7 CN7 pin 21
+ TXD: PA10 CN9 pin 3, CN10 pin 33
+ PB6 CN5 pin 3, CN10 pin 17
+
+NOTE: You may need to edit the include/board.h to select different USART1
+pin selections.
+
+TTL to RS-232 converter connection::
+
+ Nucleo CN10 STM32F4x1RE
+ ----------- ------------
+ Pin 21 PA9 USART1_RX *Warning you make need to reverse RX/TX on
+ Pin 33 PA10 USART1_TX some RS-232 converters
+ Pin 20 GND
+ Pin 8 U5V
+
+To configure USART1 as the console::
+
+ CONFIG_STM32_USART1=y
+ CONFIG_USART1_SERIALDRIVER=y
+ CONFIG_USART1_SERIAL_CONSOLE=y
+ CONFIG_USART1_RXBUFSIZE=256
+ CONFIG_USART1_TXBUFSIZE=256
+ CONFIG_USART1_BAUD=115200
+ CONFIG_USART1_BITS=8
+ CONFIG_USART1_PARITY=0
+ CONFIG_USART1_2STOP=0
+
+USART2
+------
+
+Pins and Connectors::
+
+ RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37
+ PD6
+ TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35
+ PD5
+
+ UART2 is the default in all of these configurations.
+
+TTL to RS-232 converter connection::
+
+ Nucleo CN9 STM32F4x1RE
+ ----------- ------------
+ Pin 1 PA3 USART2_RX *Warning you make need to reverse RX/TX on
+ Pin 2 PA2 USART2_TX some RS-232 converters
+
+Solder Bridges. This configuration requires:
+
+- SB62 and SB63 Closed: PA2 and PA3 on STM32 MCU are connected to D1 and D0
+ (pin 7 and pin 8) on Arduino connector CN9 and ST Morpho connector CN10
+ as USART signals. Thus SB13 and SB14 should be OFF.
+
+- SB13 and SB14 Open: PA2 and PA3 on STM32F103C8T6 (ST-LINK MCU) are
+ disconnected to PA3 and PA2 on STM32 MCU.
+
+To configure USART2 as the console::
+
+ CONFIG_STM32_USART2=y
+ CONFIG_USART2_SERIALDRIVER=y
+ CONFIG_USART2_SERIAL_CONSOLE=y
+ CONFIG_USART2_RXBUFSIZE=256
+ CONFIG_USART2_TXBUFSIZE=256
+ CONFIG_USART2_BAUD=115200
+ CONFIG_USART2_BITS=8
+ CONFIG_USART2_PARITY=0
+ CONFIG_USART2_2STOP=0
+
+USART6
+------
+
+Pins and Connectors::
+
+ RXD: PC7 CN5 pin2, CN10 pin 19
+ PA12 CN10, pin 12
+ TXD: PC6 CN10, pin 4
+ PA11 CN10, pin 14
+
+To configure USART6 as the console::
+
+ CONFIG_STM32_USART6=y
+ CONFIG_USART6_SERIALDRIVER=y
+ CONFIG_USART6_SERIAL_CONSOLE=y
+ CONFIG_USART6_RXBUFSIZE=256
+ CONFIG_USART6_TXBUFSIZE=256
+ CONFIG_USART6_BAUD=115200
+ CONFIG_USART6_BITS=8
+ CONFIG_USART6_PARITY=0
+ CONFIG_USART6_2STOP=0
+
+Virtual COM Port
+----------------
+
+Yet another option is to use UART2 and the USB virtual COM port. This
+option may be more convenient for long term development, but is painful
+to use during board bring-up.
+
+Solder Bridges. This configuration requires:
+
+- SB62 and SB63 Open: PA2 and PA3 on STM32 MCU are disconnected to D1
+ and D0 (pin 7 and pin 8) on Arduino connector CN9 and ST Morpho
+ connector CN10.
+
+- SB13 and SB14 Closed: PA2 and PA3 on STM32F103C8T6 (ST-LINK MCU) are
+ connected to PA3 and PA2 on STM32 MCU to have USART communication
+ between them. Thus SB61, SB62 and SB63 should be OFF.
+
+Configuring USART2 is the same as given above.
+
+Question: What BAUD should be configure to interface with the Virtual
+COM port? 115200 8N1?
+
+Default
+-------
+
+As shipped, SB62 and SB63 are open and SB13 and SB14 closed, so the
+virtual COM port is enabled.
+
+Shields
+=======
+
+RS-232 from Cutedigi.com
+------------------------
+
+Supports a single RS-232 connected via::
+
+ Nucleo CN9 STM32F4x1RE Cutedigi
+ ----------- ------------ --------
+ Pin 1 PA3 USART2_RX RXD
+ Pin 2 PA2 USART2_TX TXD
+
+Support for this shield is enabled by selecting USART2 and configuring
+SB13, 14, 62, and 63 as described above under "Serial Consoles"
+
+Itead Joystick Shield
+---------------------
+
+See http://imall.iteadstudio.com/im120417014.html for more information
+about this joystick.
+
+Itead Joystick Connection::
+
+ --------- ----------------- ---------------------------------
+ ARDUINO ITEAD NUCLEO-F4x1
+ PIN NAME SIGNAL SIGNAL
+ --------- ----------------- ---------------------------------
+ D3 Button E Output PB3
+ D4 Button D Output PB5
+ D5 Button C Output PB4
+ D6 Button B Output PB10
+ D7 Button A Output PA8
+ D8 Button F Output PA9
+ D9 Button G Output PC7
+ A0 Joystick Y Output PA0 ADC1_0
+ A1 Joystick X Output PA1 ADC1_1
+ --------- ----------------- ---------------------------------
+
+ All buttons are pulled on the shield. A sensed low value indicates
+ when the button is pressed.
+
+ NOTE: Button F cannot be used with the default USART1 configuration
+ because PA9 is configured for USART1_RX by default. Use select
+ different USART1 pins in the board.h file or select a different
+ USART or select CONFIG_NUCLEO_F401RE_AJOY_MINBUTTONS which will
+ eliminate all but buttons A, B, and C.
+
+Itead Joystick Signal interpretation::
+
+ --------- ----------------------- ---------------------------
+ BUTTON TYPE NUTTX ALIAS
+ --------- ----------------------- ---------------------------
+ Button A Large button A JUMP/BUTTON 3
+ Button B Large button B FIRE/BUTTON 2
+ Button C Joystick select button SELECT/BUTTON 1
+ Button D Tiny Button D BUTTON 6
+ Button E Tiny Button E BUTTON 7
+ Button F Large Button F BUTTON 4
+ Button G Large Button G BUTTON 5
+ --------- ----------------------- ---------------------------
+
+Itead Joystick configuration settings::
+
+ System Type -> STM32 Peripheral Support
+ CONFIG_STM32_ADC1=y : Enable ADC1 driver support
+
+ Drivers
+ CONFIG_ANALOG=y : Should be automatically selected
+ CONFIG_ADC=y : Should be automatically selected
+ CONFIG_INPUT=y : Select input device support
+ CONFIG_INPUT_AJOYSTICK=y : Select analog joystick support
+
+There is nothing in the configuration that currently uses the joystick.
+For testing, you can add the following configuration options to enable the
+analog joystick example at apps/examples/ajoystick::
+
+ CONFIG_NSH_ARCHINIT=y
+ CONFIG_EXAMPLES_AJOYSTICK=y
+ CONFIG_EXAMPLES_AJOYSTICK_DEVNAME="/dev/ajoy0"
+
+STATUS:
+
+2014-12-04:
+
+- Without ADC DMA support, it is not possible to sample both X and Y
+ with a single ADC. Right now, only one axis is being converted.
+
+- There is conflicts with some of the Arduino data pins and the
+ default USART1 configuration. I am currently running with USART1
+ but with CONFIG_NUCLEO_F401RE_AJOY_MINBUTTONS to eliminate the
+ conflict.
+
+- Current showstopper: I appear to be getting infinite interrupts as
+ soon as joystick button interrupts are enabled.
+
+Configurations
+==============
+
+f401-nsh:
+---------
+
+Configures the NuttShell (nsh) located at apps/examples/nsh for the
+Nucleo-F401RE board. The Configuration enables the serial interfaces
+on UART2. Support for builtin applications is enabled, but in the base
+configuration no builtin applications are selected (see NOTES below).
+
+NOTES:
+
+1. This configuration uses the mconf-based configuration tool. To
+ change this configuration using that tool, you should:
+
+ a. Build and install the kconfig-mconf tool. See nuttx/README.txt
+ see additional README.txt files in the NuttX tools repository.
+
+ b. Execute 'make menuconfig' in nuttx/ in order to start the
+ reconfiguration process.
+
+2. By default, this configuration uses the ARM EABI toolchain
+ for Linux. That can easily be reconfigured, of course.:
+
+ CONFIG_HOST_LINUX=y : Builds under Linux
+ CONFIG_ARM_TOOLCHAIN_GNU_EABI=y : GNU EABI toolchain for Linux
+
+3. Although the default console is USART2 (which would correspond to
+ the Virtual COM port) I have done all testing with the console
+ device configured for USART1 (see instruction above under "Serial
+ Consoles). I have been using a TTL-to-RS-232 converter connected
+ as shown below::
+
+ Nucleo CN10 STM32F4x1RE
+ ----------- ------------
+ Pin 21 PA9 USART1_RX *Warning you make need to reverse RX/TX on
+ Pin 33 PA10 USART1_TX some RS-232 converters
+ Pin 20 GND
+ Pin 8 U5V
+
+f411-nsh
+--------
+
+This configuration is the same as the f401-nsh configuration, except
+that it is configured to support the Nucleo-F411RE.
diff --git a/content/docs/latest/_sources/platforms/arm/stm32f4/boards/nucleo-f410rb/index.rst.txt b/content/docs/latest/_sources/platforms/arm/stm32f4/boards/nucleo-f410rb/index.rst.txt
new file mode 100644
index 00000000..29db291d
--- /dev/null
+++ b/content/docs/latest/_sources/platforms/arm/stm32f4/boards/nucleo-f410rb/index.rst.txt
@@ -0,0 +1,223 @@
+================
+ST Nucleo F410RB
+================
+
+This page discusses issues unique to NuttX configurations for the ST
+Nucleo F410RB board from ST Micro. See
+
+ http://www.st.com/en/evaluation-tools/nucleo-f410rb.html
+
+NucleoF410RB:
+
+- Microprocessor: 32-bit ARM Cortex M4 at 100MHz STM32F410RB
+- Memory: 128 KB Flash and 32 KB SRAM
+- ADC: 1x12-bit, 2.4 MSPS A/D converter: up to 16 channels
+- DAC: 1x12-bit, 2.4 MSPS A/D converter: up to 1 channels
+- DMA: 16-stream DMA controllers with FIFOs and burst support
+- Timers: Up to 11 timers: up to 5 16-bit, 1 32-bit timers, two
+ watchdog timers, and a SysTick timer
+- GPIO: Up to 81 I/O ports with interrupt capability
+- I2C: Up to 3 I2C interfaces
+- USARTs: Up to 3 USARTs
+- SPIs: Up to 4 SPIs (2 I2S)
+- CRC calculation unit
+- RTC
+
+- Peripherals: 1 led, 1 push button
+- Debug: Serial wire debug and JTAG interfaces
+- Expansion I/F Ardino and Morpho Headers
+
+Uses a STM32F103 to provide a ST-Link for programming, debug similar to the
+OpenOcd FTDI function - USB to JTAG front-end.
+
+See https://os.mbed.com/platforms/ST-Nucleo-F410RB for more
+information about this board.
+
+Hardware
+========
+
+Buttons
+-------
+
+B1 USER: the user button is connected to the I/O PC13 (pin 2) of the STM32
+microcontroller.
+
+LEDs
+----
+
+The Nucleo F410RB provide a single user LED, LD2. LD2
+is the green LED connected to Arduino signal D13 corresponding to MCU I/O
+PA5 (pin 21) or PB13 (pin 34) depending on the STM32target.
+
+- When the I/O is HIGH value, the LED is on.
+- When the I/O is LOW, the LED is off.
+
+These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
+defined. In that case, the usage by the board port is defined in
+include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related
+events as follows when the red LED (PE24) is available::
+
+ SYMBOL Meaning LD2
+ ------------------- ----------------------- -----------
+ LED_STARTED NuttX has been started OFF
+ LED_HEAPALLOCATE Heap has been allocated OFF
+ LED_IRQSENABLED Interrupts enabled OFF
+ LED_STACKCREATED Idle stack created ON
+ LED_INIRQ In an interrupt No change
+ LED_SIGNAL In a signal handler No change
+ LED_ASSERTION An assertion failed No change
+ LED_PANIC The system has crashed Blinking
+ LED_IDLE MCU is is sleep mode Not used
+
+ Thus if LD2, NuttX has successfully booted and is, apparently, running
+ normally. If LD2 is flashing at approximately 2Hz, then a fatal error
+ has been detected and the system has halted.
+
+Serial Consoles
+===============
+
+USART1
+------
+
+Pins and Connectors::
+
+ RXD: PA11 CN10 pin 14
+ PB7 CN7 pin 21
+ TXD: PA10 CN9 pin 3, CN10 pin 33
+ PB6 CN5 pin 3, CN10 pin 17
+
+ NOTE: You may need to edit the include/board.h to select different USART1
+ pin selections.
+
+TTL to RS-232 converter connection::
+
+ Nucleo CN10 STM32F410RB
+ ----------- ------------
+ Pin 21 PA9 USART1_RX *Warning you make need to reverse RX/TX on
+ Pin 33 PA10 USART1_TX some RS-232 converters
+ Pin 20 GND
+ Pin 8 U5V
+
+To configure USART1 as the console::
+
+ CONFIG_STM32_USART1=y
+ CONFIG_USART1_SERIALDRIVER=y
+ CONFIG_USART1_SERIAL_CONSOLE=y
+ CONFIG_USART1_RXBUFSIZE=256
+ CONFIG_USART1_TXBUFSIZE=256
+ CONFIG_USART1_BAUD=115200
+ CONFIG_USART1_BITS=8
+ CONFIG_USART1_PARITY=0
+ CONFIG_USART1_2STOP=0
+
+USART2
+------
+
+Pins and Connectors::
+
+ RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37
+ PD6
+ TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35
+ PD5
+
+ UART2 is the default in all of these configurations.
+
+TTL to RS-232 converter connection::
+
+ Nucleo CN9 STM32F410RB
+ ----------- ------------
+ Pin 1 PA3 USART2_RX *Warning you make need to reverse RX/TX on
+ Pin 2 PA2 USART2_TX some RS-232 converters
+
+Solder Bridges. This configuration requires:
+
+- SB62 and SB63 Closed: PA2 and PA3 on STM32 MCU are connected to D1 and D0
+ (pin 7 and pin 8) on Arduino connector CN9 and ST Morpho connector CN10
+ as USART signals. Thus SB13 and SB14 should be OFF.
+
+- SB13 and SB14 Open: PA2 and PA3 on STM32F103C8T6 (ST-LINK MCU) are
+ disconnected to PA3 and PA2 on STM32 MCU.
+
+To configure USART2 as the console::
+
+ CONFIG_STM32_USART2=y
+ CONFIG_USART2_SERIALDRIVER=y
+ CONFIG_USART2_SERIAL_CONSOLE=y
+ CONFIG_USART2_RXBUFSIZE=256
+ CONFIG_USART2_TXBUFSIZE=256
+ CONFIG_USART2_BAUD=115200
+ CONFIG_USART2_BITS=8
+ CONFIG_USART2_PARITY=0
+ CONFIG_USART2_2STOP=0
+
+USART6
+------
+
+Pins and Connectors::
+
+ RXD: PC7 CN5 pin2, CN10 pin 19
+ PA12 CN10, pin 12
+ TXD: PC6 CN10, pin 4
+ PA11 CN10, pin 14
+
+To configure USART6 as the console::
+
+ CONFIG_STM32_USART6=y
+ CONFIG_USART6_SERIALDRIVER=y
+ CONFIG_USART6_SERIAL_CONSOLE=y
+ CONFIG_USART6_RXBUFSIZE=256
+ CONFIG_USART6_TXBUFSIZE=256
+ CONFIG_USART6_BAUD=115200
+ CONFIG_USART6_BITS=8
+ CONFIG_USART6_PARITY=0
+ CONFIG_USART6_2STOP=0
+
+Virtual COM Port
+----------------
+
+Yet another option is to use UART2 and the USB virtual COM port. This
+option may be more convenient for long term development, but is painful
+to use during board bring-up.
+
+ Solder Bridges. This configuration requires:
+
+ - SB62 and SB63 Open: PA2 and PA3 on STM32 MCU are disconnected to D1
+ and D0 (pin 7 and pin 8) on Arduino connector CN9 and ST Morpho
+ connector CN10.
+
+ - SB13 and SB14 Closed: PA2 and PA3 on STM32F103C8T6 (ST-LINK MCU) are
+ connected to PA3 and PA2 on STM32 MCU to have USART communication
+ between them. Thus SB61, SB62 and SB63 should be OFF.
+
+ Configuring USART2 is the same as given above.
+
+ Question: What BAUD should be configure to interface with the Virtual
+ COM port? 115200 8N1?
+
+Default
+-------
+
+As shipped, SB62 and SB63 are open and SB13 and SB14 closed, so the
+virtual COM port is enabled.
+
+Configurations
+==============
+
+nsh
+---
+
+Configures the NuttShell (nsh) located at apps/examples/nsh for the
+Nucleo-F410RB board. The Configuration enables the serial interfaces
+on UART2. Support for builtin applications is enabled, but in the base
+configuration no builtin applications are selected (see NOTES below).
+
+NOTES:
+
+1. This configuration uses the mconf-based configuration tool. To
+ change this configuration using that tool, you should:
+
+ a. Build and install the kconfig-mconf tool. See nuttx/README.txt
+ see additional README.txt files in the NuttX tools repository.
+
+ b. Execute 'make menuconfig' in nuttx/ in order to start the
+ reconfiguration process.
diff --git a/content/docs/latest/_sources/platforms/arm/stm32f4/boards/nucleo-f411re/index.rst.txt b/content/docs/latest/_sources/platforms/arm/stm32f4/boards/nucleo-f411re/index.rst.txt
new file mode 100644
index 00000000..f428a1ae
--- /dev/null
+++ b/content/docs/latest/_sources/platforms/arm/stm32f4/boards/nucleo-f411re/index.rst.txt
@@ -0,0 +1,394 @@
+================
+ST Nucleo F401RE
+================
+
+This README discusses issues unique to NuttX configurations for the ST
+NucleoF401RE and NucleoF411RE boards from ST Micro. See
+
+ http://www.st.com/web/catalog/mmc/FM141/SC1169/SS1577/LN1810/PF258797
+ http://www.st.com/web/catalog/mmc/FM141/SC1169/SS1577/LN1877/PF260049
+
+These two boards are very similar, both supporting STM32 "Dynamic Efficiency
+Line" parts but differing in the specific STM32 chip mounted on board. The
+chips themselves are also very similar with the STM32F411RE having some
+additional capability:
+
+NucleoF411RE:
+
+- Microprocessor: 32-bit ARM Cortex M4 at 100MHz STM32F411RE
+- Memory: 512 KB Flash and 128 KB SRAM
+- ADC: 1×12-bit, 2.4 MSPS A/D converter: up to 10 channels
+- DMA: 16-stream DMA controllers with FIFOs and burst support
+- Timers: Up to 11 timers: up to six 16-bit, two 32-bit timers, two
+ watchdog timers, and a SysTick timer
+- GPIO: Up to 81 I/O ports with interrupt capability
+- I2C: Up to 3 × I2C interfaces
+- USARTs: Up to 3 USARTs
+- SPIs: Up to 4 SPIs (2 I2S)
+- SDIO interface
+- USB: USB 2.0 full-speed device/host/OTG controller with on-chip PHY
+- CRC calculation unit
+- RTC
+
+The NucleoF411RE also has additional DMA and SPI peripheral capabilities.
+
+Board features, however, are identical:
+
+- Peripherals: 1 led, 1 push button
+- Debug: Serial wire debug and JTAG interfaces
+- Expansion I/F Ardino and Morpho Headers
+
+Uses a STM32F103 to provide a ST-Link for programming, debug similar to the
+OpenOcd FTDI function - USB to JTAG front-end.
+
+See http://mbed.org/platforms/ST-Nucleo-F401RE and
+http://developer.mbed.org/platforms/ST-Nucleo-F411RE for more
+information about these boards.
+
+mbed
+====
+
+The Nucleo-F411RE includes boot loader from mbed:
+
+ https://mbed.org/platforms/ST-Nucleo-F401RE/
+ https://mbed.org/handbook/Homepage
+
+Using the mbed loader:
+
+1. Connect the Nucleo-F4x1RE to the host PC using the USB connector.
+2. A new file system will appear called NUCLEO; open it with Windows
+ Explorer (assuming that you are using Windows).
+3. Drag and drop nuttx.bin into the MBED window. This will load the
+ nuttx.bin binary into the Nucleo-F4x1RE. The NUCLEO window will
+ close then re-open and the Nucleo-F4x1RE will be running the new code.
+
+Hardware
+========
+
+GPIO
+----
+
+::
+
+ SERIAL_TX=PA_2 USER_BUTTON=PC_13
+ SERIAL_RX=PA_3 LED1 =PA_5
+
+ A0=PA_0 USART2RX D0=PA_3 D8 =PA_9
+ A1=PA_1 USART2TX D1=PA_2 D9 =PC_7
+ A2=PA_4 D2=PA_10 WIFI_CS=D10=PB_6 SPI_CS
+ A3=PB_0 WIFI_INT=D3=PB_3 D11=PA_7 SPI_MOSI
+ A4=PC_1 SDCS=D4=PB_5 D12=PA_6 SPI_MISO
+ A5=PC_0 WIFI_EN=D5=PB_4 LED1=D13=PA_5 SPI_SCK
+ LED2=D6=PB_10 I2C1_SDA=D14=PB_9 Probe
+ D7=PA_8 I2C1_SCL=D15=PB_8 Probe
+
+ From: https://mbed.org/platforms/ST-Nucleo-F401RE/
+
+Buttons
+-------
+
+B1 USER: the user button is connected to the I/O PC13 (pin 2) of the STM32
+microcontroller.
+
+LEDs
+----
+
+The Nucleo F401RE and Nucleo F411RE provide a single user LED, LD2. LD2
+is the green LED connected to Arduino signal D13 corresponding to MCU I/O
+PA5 (pin 21) or PB13 (pin 34) depending on the STM32target.
+
+- When the I/O is HIGH value, the LED is on.
+- When the I/O is LOW, the LED is off.
+
+These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
+defined. In that case, the usage by the board port is defined in
+include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related
+events as follows when the red LED (PE24) is available:
+
+ =================== ======================= ===========
+ SYMBOL Meaning LD2
+ =================== ======================= ===========
+ LED_STARTED NuttX has been started OFF
+ LED_HEAPALLOCATE Heap has been allocated OFF
+ LED_IRQSENABLED Interrupts enabled OFF
+ LED_STACKCREATED Idle stack created ON
+ LED_INIRQ In an interrupt No change
+ LED_SIGNAL In a signal handler No change
+ LED_ASSERTION An assertion failed No change
+ LED_PANIC The system has crashed Blinking
+ LED_IDLE MCU is is sleep mode Not used
+ =================== ======================= ===========
+
+Thus if LD2, NuttX has successfully booted and is, apparently, running
+normally. If LD2 is flashing at approximately 2Hz, then a fatal error
+has been detected and the system has halted.
+
+Serial Consoles
+===============
+
+USART1
+------
+
+Pins and Connectors::
+
+ RXD: PA11 CN10 pin 14
+ PB7 CN7 pin 21
+ TXD: PA10 CN9 pin 3, CN10 pin 33
+ PB6 CN5 pin 3, CN10 pin 17
+
+NOTE: You may need to edit the include/board.h to select different USART1
+pin selections.
+
+TTL to RS-232 converter connection::
+
+ Nucleo CN10 STM32F4x1RE
+ ----------- ------------
+ Pin 21 PA9 USART1_RX *Warning you make need to reverse RX/TX on
+ Pin 33 PA10 USART1_TX some RS-232 converters
+ Pin 20 GND
+ Pin 8 U5V
+
+To configure USART1 as the console::
+
+ CONFIG_STM32_USART1=y
+ CONFIG_USART1_SERIALDRIVER=y
+ CONFIG_USART1_SERIAL_CONSOLE=y
+ CONFIG_USART1_RXBUFSIZE=256
+ CONFIG_USART1_TXBUFSIZE=256
+ CONFIG_USART1_BAUD=115200
+ CONFIG_USART1_BITS=8
+ CONFIG_USART1_PARITY=0
+ CONFIG_USART1_2STOP=0
+
+USART2
+------
+
+Pins and Connectors::
+
+ RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37
+ PD6
+ TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35
+ PD5
+
+ UART2 is the default in all of these configurations.
+
+TTL to RS-232 converter connection::
+
+ Nucleo CN9 STM32F4x1RE
+ ----------- ------------
+ Pin 1 PA3 USART2_RX *Warning you make need to reverse RX/TX on
+ Pin 2 PA2 USART2_TX some RS-232 converters
+
+Solder Bridges. This configuration requires:
+
+- SB62 and SB63 Closed: PA2 and PA3 on STM32 MCU are connected to D1 and D0
+ (pin 7 and pin 8) on Arduino connector CN9 and ST Morpho connector CN10
+ as USART signals. Thus SB13 and SB14 should be OFF.
+
+- SB13 and SB14 Open: PA2 and PA3 on STM32F103C8T6 (ST-LINK MCU) are
+ disconnected to PA3 and PA2 on STM32 MCU.
+
+To configure USART2 as the console::
+
+ CONFIG_STM32_USART2=y
+ CONFIG_USART2_SERIALDRIVER=y
+ CONFIG_USART2_SERIAL_CONSOLE=y
+ CONFIG_USART2_RXBUFSIZE=256
+ CONFIG_USART2_TXBUFSIZE=256
+ CONFIG_USART2_BAUD=115200
+ CONFIG_USART2_BITS=8
+ CONFIG_USART2_PARITY=0
+ CONFIG_USART2_2STOP=0
+
+USART6
+------
+
+Pins and Connectors::
+
+ RXD: PC7 CN5 pin2, CN10 pin 19
+ PA12 CN10, pin 12
+ TXD: PC6 CN10, pin 4
+ PA11 CN10, pin 14
+
+To configure USART6 as the console::
+
+ CONFIG_STM32_USART6=y
+ CONFIG_USART6_SERIALDRIVER=y
+ CONFIG_USART6_SERIAL_CONSOLE=y
+ CONFIG_USART6_RXBUFSIZE=256
+ CONFIG_USART6_TXBUFSIZE=256
+ CONFIG_USART6_BAUD=115200
+ CONFIG_USART6_BITS=8
+ CONFIG_USART6_PARITY=0
+ CONFIG_USART6_2STOP=0
+
+Virtual COM Port
+----------------
+
+Yet another option is to use UART2 and the USB virtual COM port. This
+option may be more convenient for long term development, but is painful
+to use during board bring-up.
+
+Solder Bridges. This configuration requires:
+
+- SB62 and SB63 Open: PA2 and PA3 on STM32 MCU are disconnected to D1
+ and D0 (pin 7 and pin 8) on Arduino connector CN9 and ST Morpho
+ connector CN10.
+
+- SB13 and SB14 Closed: PA2 and PA3 on STM32F103C8T6 (ST-LINK MCU) are
+ connected to PA3 and PA2 on STM32 MCU to have USART communication
+ between them. Thus SB61, SB62 and SB63 should be OFF.
+
+Configuring USART2 is the same as given above.
+
+Question: What BAUD should be configure to interface with the Virtual
+COM port? 115200 8N1?
+
+Default
+-------
+
+As shipped, SB62 and SB63 are open and SB13 and SB14 closed, so the
+virtual COM port is enabled.
+
+Shields
+=======
+
+RS-232 from Cutedigi.com
+------------------------
+
+Supports a single RS-232 connected via::
+
+ Nucleo CN9 STM32F4x1RE Cutedigi
+ ----------- ------------ --------
+ Pin 1 PA3 USART2_RX RXD
+ Pin 2 PA2 USART2_TX TXD
+
+Support for this shield is enabled by selecting USART2 and configuring
+SB13, 14, 62, and 63 as described above under "Serial Consoles"
+
+Itead Joystick Shield
+---------------------
+
+See http://imall.iteadstudio.com/im120417014.html for more information
+about this joystick.
+
+Itead Joystick Connection::
+
+ --------- ----------------- ---------------------------------
+ ARDUINO ITEAD NUCLEO-F4x1
+ PIN NAME SIGNAL SIGNAL
+ --------- ----------------- ---------------------------------
+ D3 Button E Output PB3
+ D4 Button D Output PB5
+ D5 Button C Output PB4
+ D6 Button B Output PB10
+ D7 Button A Output PA8
+ D8 Button F Output PA9
+ D9 Button G Output PC7
+ A0 Joystick Y Output PA0 ADC1_0
+ A1 Joystick X Output PA1 ADC1_1
+ --------- ----------------- ---------------------------------
+
+ All buttons are pulled on the shield. A sensed low value indicates
+ when the button is pressed.
+
+ NOTE: Button F cannot be used with the default USART1 configuration
+ because PA9 is configured for USART1_RX by default. Use select
+ different USART1 pins in the board.h file or select a different
+ USART or select CONFIG_NUCLEO_F401RE_AJOY_MINBUTTONS which will
+ eliminate all but buttons A, B, and C.
+
+Itead Joystick Signal interpretation::
+
+ --------- ----------------------- ---------------------------
+ BUTTON TYPE NUTTX ALIAS
+ --------- ----------------------- ---------------------------
+ Button A Large button A JUMP/BUTTON 3
+ Button B Large button B FIRE/BUTTON 2
+ Button C Joystick select button SELECT/BUTTON 1
+ Button D Tiny Button D BUTTON 6
+ Button E Tiny Button E BUTTON 7
+ Button F Large Button F BUTTON 4
+ Button G Large Button G BUTTON 5
+ --------- ----------------------- ---------------------------
+
+Itead Joystick configuration settings::
+
+ System Type -> STM32 Peripheral Support
+ CONFIG_STM32_ADC1=y : Enable ADC1 driver support
+
+ Drivers
+ CONFIG_ANALOG=y : Should be automatically selected
+ CONFIG_ADC=y : Should be automatically selected
+ CONFIG_INPUT=y : Select input device support
+ CONFIG_INPUT_AJOYSTICK=y : Select analog joystick support
+
+There is nothing in the configuration that currently uses the joystick.
+For testing, you can add the following configuration options to enable the
+analog joystick example at apps/examples/ajoystick::
+
+ CONFIG_NSH_ARCHINIT=y
+ CONFIG_EXAMPLES_AJOYSTICK=y
+ CONFIG_EXAMPLES_AJOYSTICK_DEVNAME="/dev/ajoy0"
+
+STATUS:
+
+2014-12-04:
+
+- Without ADC DMA support, it is not possible to sample both X and Y
+ with a single ADC. Right now, only one axis is being converted.
+
+- There is conflicts with some of the Arduino data pins and the
+ default USART1 configuration. I am currently running with USART1
+ but with CONFIG_NUCLEO_F401RE_AJOY_MINBUTTONS to eliminate the
+ conflict.
+
+- Current showstopper: I appear to be getting infinite interrupts as
+ soon as joystick button interrupts are enabled.
+
+Configurations
+==============
+
+f401-nsh:
+---------
+
+Configures the NuttShell (nsh) located at apps/examples/nsh for the
+Nucleo-F401RE board. The Configuration enables the serial interfaces
+on UART2. Support for builtin applications is enabled, but in the base
+configuration no builtin applications are selected (see NOTES below).
+
+NOTES:
+
+1. This configuration uses the mconf-based configuration tool. To
+ change this configuration using that tool, you should:
+
+ a. Build and install the kconfig-mconf tool. See nuttx/README.txt
+ see additional README.txt files in the NuttX tools repository.
+
+ b. Execute 'make menuconfig' in nuttx/ in order to start the
+ reconfiguration process.
+
+2. By default, this configuration uses the ARM EABI toolchain
+ for Linux. That can easily be reconfigured, of course.:
+
+ CONFIG_HOST_LINUX=y : Builds under Linux
+ CONFIG_ARM_TOOLCHAIN_GNU_EABI=y : GNU EABI toolchain for Linux
+
+3. Although the default console is USART2 (which would correspond to
+ the Virtual COM port) I have done all testing with the console
+ device configured for USART1 (see instruction above under "Serial
+ Consoles). I have been using a TTL-to-RS-232 converter connected
+ as shown below::
+
+ Nucleo CN10 STM32F4x1RE
+ ----------- ------------
+ Pin 21 PA9 USART1_RX *Warning you make need to reverse RX/TX on
+ Pin 33 PA10 USART1_TX some RS-232 converters
+ Pin 20 GND
+ Pin 8 U5V
+
+f411-nsh
+--------
+
+This configuration is the same as the f401-nsh configuration, except
+that it is configured to support the Nucleo-F411RE.
diff --git a/content/docs/latest/_sources/platforms/arm/stm32f4/boards/nucleo-f412zg/index.rst.txt b/content/docs/latest/_sources/platforms/arm/stm32f4/boards/nucleo-f412zg/index.rst.txt
new file mode 100644
index 00000000..cbad2e3d
--- /dev/null
+++ b/content/docs/latest/_sources/platforms/arm/stm32f4/boards/nucleo-f412zg/index.rst.txt
@@ -0,0 +1,222 @@
+================
+ST Nucleo F410RB
+================
+
+This page discusses issues unique to NuttX configurations for the ST
+Nucleo F410RB board from ST Micro. See
+
+ http://www.st.com/en/evaluation-tools/nucleo-f412zg.html
+
+NucleoF412ZG:
+
+- Microprocessor: 32-bit ARM Cortex M4 at 100MHz STM32F412ZG
+- Memory: 1 MB Flash and 256 KB SRAM
+- ADC: 1x12-bit, 2.4 MSPS A/D converter: up to 16 channels
+- DMA: 2x8-stream DMA controllers with FIFOs and burst support
+- Timers: Up to 17 timers: up to 12 16-bit, 2 32-bit timers, two
+ watchdog timers, and a SysTick timer
+- GPIO: Up to 114 I/O ports with interrupt capability
+- I2C: Up to 4 I2C interfaces
+- USARTs: Up to 4 USARTs
+- SPIs: Up to 5 SPIs (5 I2S)
+- SDIO interface (SD/MMC/eMMC)
+- Advanced connectivity: USB 2.0 full-speed device/host/OTG controller with PHY
+- 2x CAN (2.0B Active)
+- True random number generator
+- CRC calculation unit
+- 96-bit unique ID
+- RTC
+
+See:
+https://www.st.com/content/ccc/resource/technical/document/user_manual/group0/26/49/90/2e/33/0d/4a/da/DM00244518/files/DM00244518.pdf/jcr:content/translations/en.DM00244518.pdf
+
+- Peripherals: 3 led, 2 push button
+- Debug: Serial wire debug and JTAG interfaces
+- Expansion I/F Ardino and Morpho Headers
+
+Hardware
+========
+
+Buttons
+-------
+
+B1 USER: the user button is connected to the I/O PC13 (pin 2) of the STM32
+microcontroller.
+
+LEDs
+----
+
+The Nucleo F410RB provide a single user LED, LD2. LD2
+is the green LED connected to Arduino signal D13 corresponding to MCU I/O
+PA5 (pin 21) or PB13 (pin 34) depending on the STM32target.
+
+- When the I/O is HIGH value, the LED is on.
+- When the I/O is LOW, the LED is off.
+
+These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
+defined. In that case, the usage by the board port is defined in
+include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related
+events as follows when the red LED (PE24) is available::
+
+ SYMBOL Meaning LD2
+ ------------------- ----------------------- -----------
+ LED_STARTED NuttX has been started OFF
+ LED_HEAPALLOCATE Heap has been allocated OFF
+ LED_IRQSENABLED Interrupts enabled OFF
+ LED_STACKCREATED Idle stack created ON
+ LED_INIRQ In an interrupt No change
+ LED_SIGNAL In a signal handler No change
+ LED_ASSERTION An assertion failed No change
+ LED_PANIC The system has crashed Blinking
+ LED_IDLE MCU is is sleep mode Not used
+
+Thus if LD2, NuttX has successfully booted and is, apparently, running
+normally. If LD2 is flashing at approximately 2Hz, then a fatal error
+has been detected and the system has halted.
+
+Serial Consoles
+===============
+
+USART1
+------
+
+Pins and Connectors::
+
+ RXD: PA11 CN10 pin 14
+ PB7 CN7 pin 21
+ TXD: PA10 CN9 pin 3, CN10 pin 33
+ PB6 CN5 pin 3, CN10 pin 17
+
+ NOTE: You may need to edit the include/board.h to select different USART1
+ pin selections.
+
+TTL to RS-232 converter connection::
+
+ Nucleo CN10 STM32F410RB
+ ----------- ------------
+ Pin 21 PA9 USART1_RX *Warning you make need to reverse RX/TX on
+ Pin 33 PA10 USART1_TX some RS-232 converters
+ Pin 20 GND
+ Pin 8 U5V
+
+To configure USART1 as the console::
+
+ CONFIG_STM32_USART1=y
+ CONFIG_USART1_SERIALDRIVER=y
+ CONFIG_USART1_SERIAL_CONSOLE=y
+ CONFIG_USART1_RXBUFSIZE=256
+ CONFIG_USART1_TXBUFSIZE=256
+ CONFIG_USART1_BAUD=115200
+ CONFIG_USART1_BITS=8
+ CONFIG_USART1_PARITY=0
+ CONFIG_USART1_2STOP=0
+
+USART2
+------
+
+Pins and Connectors::
+
+ RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37
+ PD6
+ TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35
+ PD5
+
+ UART2 is the default in all of these configurations.
+
+TTL to RS-232 converter connection::
+
+ Nucleo CN9 STM32F410RB
+ ----------- ------------
+ Pin 1 PA3 USART2_RX *Warning you make need to reverse RX/TX on
+ Pin 2 PA2 USART2_TX some RS-232 converters
+
+Solder Bridges. This configuration requires:
+
+- SB62 and SB63 Closed: PA2 and PA3 on STM32 MCU are connected to D1 and D0
+ (pin 7 and pin 8) on Arduino connector CN9 and ST Morpho connector CN10
+ as USART signals. Thus SB13 and SB14 should be OFF.
+
+- SB13 and SB14 Open: PA2 and PA3 on STM32F103C8T6 (ST-LINK MCU) are
+ disconnected to PA3 and PA2 on STM32 MCU.
+
+To configure USART2 as the console::
+
+ CONFIG_STM32_USART2=y
+ CONFIG_USART2_SERIALDRIVER=y
+ CONFIG_USART2_SERIAL_CONSOLE=y
+ CONFIG_USART2_RXBUFSIZE=256
+ CONFIG_USART2_TXBUFSIZE=256
+ CONFIG_USART2_BAUD=115200
+ CONFIG_USART2_BITS=8
+ CONFIG_USART2_PARITY=0
+ CONFIG_USART2_2STOP=0
+
+USART6
+------
+
+Pins and Connectors::
+
+ RXD: PC7 CN5 pin2, CN10 pin 19
+ PA12 CN10, pin 12
+ TXD: PC6 CN10, pin 4
+ PA11 CN10, pin 14
+
+To configure USART6 as the console::
+
+ CONFIG_STM32_USART6=y
+ CONFIG_USART6_SERIALDRIVER=y
+ CONFIG_USART6_SERIAL_CONSOLE=y
+ CONFIG_USART6_RXBUFSIZE=256
+ CONFIG_USART6_TXBUFSIZE=256
+ CONFIG_USART6_BAUD=115200
+ CONFIG_USART6_BITS=8
+ CONFIG_USART6_PARITY=0
+ CONFIG_USART6_2STOP=0
+
+Virtual COM Port
+----------------
+
+Yet another option is to use UART2 and the USB virtual COM port. This
+option may be more convenient for long term development, but is painful
+to use during board bring-up.
+
+Solder Bridges. This configuration requires:
+
+- SB62 and SB63 Open: PA2 and PA3 on STM32 MCU are disconnected to D1
+ and D0 (pin 7 and pin 8) on Arduino connector CN9 and ST Morpho
+ connector CN10.
+
+- SB13 and SB14 Closed: PA2 and PA3 on STM32F103C8T6 (ST-LINK MCU) are
+ connected to PA3 and PA2 on STM32 MCU to have USART communication
+ between them. Thus SB61, SB62 and SB63 should be OFF.
+
+Configuring USART2 is the same as given above.
+
+Question: What BAUD should be configure to interface with the Virtual
+COM port? 115200 8N1?
+
+Default:
+As shipped, SB62 and SB63 are open and SB13 and SB14 closed, so the
+virtual COM port is enabled.
+
+Configurations
+==============
+
+nsh
+---
+
+Configures the NuttShell (nsh) located at apps/examples/nsh for the
+Nucleo-F410RB board. The Configuration enables the serial interfaces
+on UART2. Support for builtin applications is enabled, but in the base
+configuration no builtin applications are selected (see NOTES below).
+
+NOTES:
+
+1. This configuration uses the mconf-based configuration tool. To
+ change this configuration using that tool, you should:
+
+ a. Build and install the kconfig-mconf tool. See nuttx/README.txt
+ see additional README.txt files in the NuttX tools repository.
+
+ b. Execute 'make menuconfig' in nuttx/ in order to start the
+ reconfiguration process.
diff --git a/content/docs/latest/_sources/platforms/arm/stm32f4/boards/nucleo-f429zi/index.rst.txt b/content/docs/latest/_sources/platforms/arm/stm32f4/boards/nucleo-f429zi/index.rst.txt
new file mode 100644
index 00000000..1f9d5069
--- /dev/null
+++ b/content/docs/latest/_sources/platforms/arm/stm32f4/boards/nucleo-f429zi/index.rst.txt
@@ -0,0 +1,3 @@
+================
+ST Nucleo F429ZI
+================
diff --git a/content/docs/latest/_sources/platforms/arm/stm32f4/boards/nucleo-f446re/index.rst.txt b/content/docs/latest/_sources/platforms/arm/stm32f4/boards/nucleo-f446re/index.rst.txt
new file mode 100644
index 00000000..bc9a19bd
--- /dev/null
+++ b/content/docs/latest/_sources/platforms/arm/stm32f4/boards/nucleo-f446re/index.rst.txt
@@ -0,0 +1,494 @@
+================
+ST Nucleo F446RE
+================
+
+This page discusses issues unique to NuttX configurations for the ST
+NucleoF446RE boards from ST Micro. See
+
+ https://www.st.com/en/evaluation-tools/nucleo-f446re.html
+
+NucleoF446RE:
+
+- Microprocessor: 32-bit ARM Cortex M4 at 180MHz STM32F446RE
+- Memory: 512 KB Flash and 128 KB SRAM
+- ADC: 1×12-bit, 2.4 MSPS A/D converter: up to 10 channels
+- DMA: 16-stream DMA controllers with FIFOs and burst support
+- Timers: Up to 11 timers: up to six 16-bit, two 32-bit timers, two
+ watchdog timers, and a SysTick timer
+- GPIO: Up to 81 I/O ports with interrupt capability
+- I2C: Up to 3 × I2C interfaces
+- USARTs: Up to 3 USARTs
+- USARTs: Up to 3 USARTs
+- SPIs: Up to 4 SPIs (2 I2S)
+- SDIO interface
+- USB: USB 2.0 full-speed device/host/OTG controller with on-chip PHY
+- CRC calculation unit
+- RTC
+
+The NucleoF446RE also has additional DMA and SPI peripheral capabilities.
+
+Board features, however, are identical:
+
+- Peripherals: 1 led, 1 push button
+- Debug: Serial wire debug and JTAG interfaces
+- Expansion I/F Ardino and Morpho Headers
+
+Uses a STM32F103 to provide a ST-Link for programming, debug similar to the
+OpenOcd FTDI function - USB to JTAG front-end.
+
+See https://os.mbed.com/platforms/ST-Nucleo-F446RE/ for more
+information about this board.
+
+mbed
+====
+
+The Nucleo-F401RE includes boot loader from mbed:
+
+ https://mbed.org/platforms/ST-Nucleo-F401RE/
+ https://mbed.org/handbook/Homepage
+
+Using the mbed loader:
+
+1. Connect the Nucleo-F4x1RE to the host PC using the USB connector.
+2. A new file system will appear called NUCLEO; open it with Windows
+ Explorer (assuming that you are using Windows).
+3. Drag and drop nuttx.bin into the MBED window. This will load the
+ nuttx.bin binary into the Nucleo-F4x1RE. The NUCLEO window will
+ close then re-open and the Nucleo-F4x1RE will be running the new code.
+
+Hardware
+========
+
+ ..
+ GPIO
+ ----
+ SERIAL_TX=PA_2 USER_BUTTON=PC_13
+ SERIAL_RX=PA_3 LED1 =PA_5
+
+ A0=PA_0 USART2RX D0=PA_3 D8 =PA_9
+ A1=PA_1 USART2TX D1=PA_2 D9 =PC_7
+ A2=PA_4 D2=PA_10 WIFI_CS=D10=PB_6 SPI_CS
+ A3=PB_0 WIFI_INT=D3=PB_3 D11=PA_7 SPI_MOSI
+ A4=PC_1 SDCS=D4=PB_5 D12=PA_6 SPI_MISO
+ A5=PC_0 WIFI_EN=D5=PB_4 LED1=D13=PA_5 SPI_SCK
+ LED2=D6=PB_10 I2C1_SDA=D14=PB_9 Probe
+ D7=PA_8 I2C1_SCL=D15=PB_8 Probe
+
+ From: https://mbed.org/platforms/ST-Nucleo-F401RE/
+
+Buttons
+-------
+
+B1 USER: the user button is connected to the I/O PC13 (pin 2) of the STM32
+microcontroller.
+
+LEDs
+----
+
+The Nucleo F446RE provides a single user LED, LD2. LD2
+is the green LED connected to Arduino signal D13 corresponding to MCU I/O
+PA5 (pin 21) or PB13 (pin 34) depending on the STM32target.
+
+- When the I/O is HIGH value, the LED is on.
+- When the I/O is LOW, the LED is off.
+
+These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
+defined. In that case, the usage by the board port is defined in
+include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related
+events as follows when the red LED (PE24) is available::
+
+ SYMBOL Meaning LD2
+ ------------------- ----------------------- -----------
+ LED_STARTED NuttX has been started OFF
+ LED_HEAPALLOCATE Heap has been allocated OFF
+ LED_IRQSENABLED Interrupts enabled OFF
+ LED_STACKCREATED Idle stack created ON
+ LED_INIRQ In an interrupt No change
+ LED_SIGNAL In a signal handler No change
+ LED_ASSERTION An assertion failed No change
+ LED_PANIC The system has crashed Blinking
+ LED_IDLE MCU is is sleep mode Not used
+
+Thus if LD2, NuttX has successfully booted and is, apparently, running
+normally. If LD2 is flashing at approximately 2Hz, then a fatal error
+has been detected and the system has halted.
+
+Serial Consoles
+===============
+
+USART1
+------
+
+Pins and Connectors::
+
+ RXD: PA11 CN10 pin 14
+ PB7 CN7 pin 21
+ TXD: PA10 CN9 pin 3, CN10 pin 33
+ PB6 CN5 pin 3, CN10 pin 17
+
+ NOTE: You may need to edit the include/board.h to select different USART1
+ pin selections.
+
+TTL to RS-232 converter connection::
+
+ Nucleo CN10 STM32F4x1RE
+ ----------- ------------
+ Pin 21 PA9 USART1_RX *Warning you make need to reverse RX/TX on
+ Pin 33 PA10 USART1_TX some RS-232 converters
+ Pin 20 GND
+ Pin 8 U5V
+
+To configure USART1 as the console::
+
+ CONFIG_STM32_USART1=y
+ CONFIG_USART1_SERIALDRIVER=y
+ CONFIG_USART1_SERIAL_CONSOLE=y
+ CONFIG_USART1_RXBUFSIZE=256
+ CONFIG_USART1_TXBUFSIZE=256
+ CONFIG_USART1_BAUD=115200
+ CONFIG_USART1_BITS=8
+ CONFIG_USART1_PARITY=0
+ CONFIG_USART1_2STOP=0
+
+USART2
+------
+
+Pins and Connectors::
+
+ RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37
+ PD6
+ TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35
+ PD5
+
+ UART2 is the default in all of these configurations.
+
+TTL to RS-232 converter connection::
+
+ Nucleo CN9 STM32F4x1RE
+ ----------- ------------
+ Pin 1 PA3 USART2_RX *Warning you make need to reverse RX/TX on
+ Pin 2 PA2 USART2_TX some RS-232 converters
+
+Solder Bridges. This configuration requires:
+
+- SB62 and SB63 Closed: PA2 and PA3 on STM32 MCU are connected to D1 and D0
+ (pin 7 and pin 8) on Arduino connector CN9 and ST Morpho connector CN10
+ as USART signals. Thus SB13 and SB14 should be OFF.
+
+- SB13 and SB14 Open: PA2 and PA3 on STM32F103C8T6 (ST-LINK MCU) are
+ disconnected to PA3 and PA2 on STM32 MCU.
+
+To configure USART2 as the console::
+
+ CONFIG_STM32_USART2=y
+ CONFIG_USART2_SERIALDRIVER=y
+ CONFIG_USART2_SERIAL_CONSOLE=y
+ CONFIG_USART2_RXBUFSIZE=256
+ CONFIG_USART2_TXBUFSIZE=256
+ CONFIG_USART2_BAUD=115200
+ CONFIG_USART2_BITS=8
+ CONFIG_USART2_PARITY=0
+ CONFIG_USART2_2STOP=0
+
+USART6
+------
+
+Pins and Connectors::
+
+ RXD: PC7 CN5 pin2, CN10 pin 19
+ PA12 CN10, pin 12
+ TXD: PC6 CN10, pin 4
+ PA11 CN10, pin 14
+
+To configure USART6 as the console::
+
+ CONFIG_STM32_USART6=y
+ CONFIG_USART6_SERIALDRIVER=y
+ CONFIG_USART6_SERIAL_CONSOLE=y
+ CONFIG_USART6_RXBUFSIZE=256
+ CONFIG_USART6_TXBUFSIZE=256
+ CONFIG_USART6_BAUD=115200
+ CONFIG_USART6_BITS=8
+ CONFIG_USART6_PARITY=0
+ CONFIG_USART6_2STOP=0
+
+Virtual COM Port
+----------------
+
+Yet another option is to use UART2 and the USB virtual COM port. This
+option may be more convenient for long term development, but is painful
+to use during board bring-up.
+
+Solder Bridges. This configuration requires:
+
+- SB62 and SB63 Open: PA2 and PA3 on STM32 MCU are disconnected to D1
+ and D0 (pin 7 and pin 8) on Arduino connector CN9 and ST Morpho
+ connector CN10.
+
+- SB13 and SB14 Closed: PA2 and PA3 on STM32F103C8T6 (ST-LINK MCU) are
+ connected to PA3 and PA2 on STM32 MCU to have USART communication
+ between them. Thus SB61, SB62 and SB63 should be OFF.
+
+Configuring USART2 is the same as given above.
+
+Question: What BAUD should be configure to interface with the Virtual
+COM port? 115200 8N1?
+
+Default
+-------
+
+As shipped, SB62 and SB63 are open and SB13 and SB14 closed, so the
+virtual COM port is enabled.
+
+Shields
+=======
+
+RS-232 from Cutedigi.com
+------------------------
+
+Supports a single RS-232 connected via::
+
+ Nucleo CN9 STM32F4x1RE Cutedigi
+ ----------- ------------ --------
+ Pin 1 PA3 USART2_RX RXD
+ Pin 2 PA2 USART2_TX TXD
+
+Support for this shield is enabled by selecting USART2 and configuring
+SB13, 14, 62, and 63 as described above under "Serial Consoles"
+
+Itead Joystick Shield
+---------------------
+
+See http://imall.iteadstudio.com/im120417014.html for more information
+about this joystick.
+
+Itead Joystick Connection::
+
+ --------- ----------------- ---------------------------------
+ ARDUINO ITEAD NUCLEO-F4x1
+ PIN NAME SIGNAL SIGNAL
+ --------- ----------------- ---------------------------------
+ D3 Button E Output PB3
+ D4 Button D Output PB5
+ D5 Button C Output PB4
+ D6 Button B Output PB10
+ D7 Button A Output PA8
+ D8 Button F Output PA9
+ D9 Button G Output PC7
+ A0 Joystick Y Output PA0 ADC1_0
+ A1 Joystick X Output PA1 ADC1_1
+ --------- ----------------- ---------------------------------
+
+ All buttons are pulled on the shield. A sensed low value indicates
+ when the button is pressed.
+
+ NOTE: Button F cannot be used with the default USART1 configuration
+ because PA9 is configured for USART1_RX by default. Use select
+ different USART1 pins in the board.h file or select a different
+ USART or select CONFIG_NUCLEO_F401RE_AJOY_MINBUTTONS which will
+ eliminate all but buttons A, B, and C.
+
+Itead Joystick Signal interpretation::
+
+ --------- ----------------------- ---------------------------
+ BUTTON TYPE NUTTX ALIAS
+ --------- ----------------------- ---------------------------
+ Button A Large button A JUMP/BUTTON 3
+ Button B Large button B FIRE/BUTTON 2
+ Button C Joystick select button SELECT/BUTTON 1
+ Button D Tiny Button D BUTTON 6
+ Button E Tiny Button E BUTTON 7
+ Button F Large Button F BUTTON 4
+ Button G Large Button G BUTTON 5
+ --------- ----------------------- ---------------------------
+
+Itead Joystick configuration settings::
+
+ System Type -> STM32 Peripheral Support
+ CONFIG_STM32_ADC1=y : Enable ADC1 driver support
+
+ Drivers
+ CONFIG_ANALOG=y : Should be automatically selected
+ CONFIG_ADC=y : Should be automatically selected
+ CONFIG_INPUT=y : Select input device support
+ CONFIG_INPUT_AJOYSTICK=y : Select analog joystick support
+
+There is nothing in the configuration that currently uses the joystick.
+For testing, you can add the following configuration options to enable the
+analog joystick example at apps/examples/ajoystick::
+
+ CONFIG_NSH_ARCHINIT=y
+ CONFIG_EXAMPLES_AJOYSTICK=y
+ CONFIG_EXAMPLES_AJOYSTICK_DEVNAME="/dev/ajoy0"
+
+STATUS:
+2014-12-04:
+
+- Without ADC DMA support, it is not possible to sample both X and Y
+ with a single ADC. Right now, only one axis is being converted.
+
+- There is conflicts with some of the Arduino data pins and the
+ default USART1 configuration. I am currently running with USART1
+ but with CONFIG_NUCLEO_F401RE_AJOY_MINBUTTONS to eliminate the
+ conflict.
+
+- Current showstopper: I appear to be getting infinite interrupts as
+ soon as joystick button interrupts are enabled.
+
+Configurations
+==============
+
+nsh:
+----
+
+Configures the NuttShell (nsh) located at apps/examples/nsh for the
+Nucleo-F446RE board. The Configuration enables the serial interfaces
+on UART2. Support for builtin applications is enabled, but in the base
+configuration no builtin applications are selected (see NOTES below).
+
+NOTES:
+
+1. This configuration uses the mconf-based configuration tool. To
+ change this configuration using that tool, you should:
+
+ a. Build and install the kconfig-mconf tool. See nuttx/README.txt
+ see additional README.txt files in the NuttX tools repository.
+
+ b. Execute 'make menuconfig' in nuttx/ in order to start the
+ reconfiguration process.
+
+2. By default, this configuration uses the ARM EABI toolchain
+ for Linux. That can easily be reconfigured, of course.::
+
+ CONFIG_HOST_LINUX=y : Builds under Linux
+ CONFIG_ARM_TOOLCHAIN_GNU_EABI=y : GNU EABI toolchain for Linux
+
+3. Although the default console is USART2 (which would correspond to
+ the Virtual COM port) I have done all testing with the console
+ device configured for USART1 (see instruction above under "Serial
+ Consoles). I have been using a TTL-to-RS-232 converter connected
+ as shown below::
+
+ Nucleo CN10 STM32F446RE
+ ----------- ------------
+ Pin 21 PA9 USART1_RX *Warning you make need to reverse RX/TX on
+ Pin 33 PA10 USART1_TX some RS-232 converters
+ Pin 20 GND
+ Pin 8 U5V
+
+can
+---
+
+This is basically an nsh configuration (see above) with added support
+for CAN driver. Both CAN 1 (RX: PB_8, TX: PB_9) and CAN 2 (RX: PB_5, TX: PB_6)
+are turn on.
+
+Functionality of CAN driver can be tested by calling application
+"can" in NuttShell. This application sends 100 messages over CAN 1.
+
+dac
+---
+
+This is an nsh configuration (see above) with added support
+for digital analog converter driver.
+
+Functionality of DAC driver can be tested by calling application
+"dac" in NuttShell. GPIO_DAC1_OUT1 pin is set on PA_4.
+
+gpio
+----
+
+This is an nsh configuration (see above) with added support for GPIO
+driver and GPIO test application "gpio". Three pins are configured for
+testing purposes::
+
+ PA_7 - GPIO_INPUT
+ PB_6 - GPIO_OUTPUT
+ PC_7 - GPIO_INPUT_INTERRUPT
+
+ihm08m1_f32 and ihm08m1_b16
+---------------------------
+
+These examples are dedicated for the X-NUCLEO-IHM08M1 expansion board with
+L6398 gate drivers and discrete transistors.
+
+WARNING: L6398 gate drivers require channel 2 negative polarisation and
+negative sign for the deadtime. Make sure that your gate drivers logic
+is compatible with this configuration.
+
+X-NUCLEO-IHM08M1 must be configured to work with FOC and 3-shunt
+resistors. See ST documentation for details.
+
+Pin configuration for the X-NUCLEO-IHM08M1 (TIM1 configuration)::
+
+ Board Function Chip Function Chip Pin Number
+ ------------- ---------------- -----------------
+ Phase U high TIM1_CH1 PA8
+ Phase U low TIM1_CH1N PA7
+ Phase V high TIM1_CH2 PA9
+ Phase V low TIM1_CH2N PB0
+ Phase W high TIM1_CH3 PA10
+ Phase W low TIM1_CH3N PB1
+ Current U ADC1_IN0 PA0
+ Current V ADC1_IN11 PC1
+ Current W ADC1_IN10 PC0
+ Temperature ADC1_IN12 PC2
+ VBUS ADC1_IN1 PA1
+ BEMF1 (NU) PC3
+ BEMF2 (NU) PC4
+ BEMF3 (NU) PC5
+ LED GPIO_PB2 PB2
+ +3V3 (CN7_16)
+ GND (CN7_20)
+ GPIO_BEMF (NU) PC9
+ ENCO_A/HALL_H1 TIM2_CH1 PA15
+ ENCO_B/HALL_H2 TIM2_CH2 PB3
+ ENCO_Z/HALL_H3 TIM2_CH3 PB10
+ DAC (NU) PA5
+ GPIO3 (NU) PB13
+ CPOUT (NU) PA12
+ BKIN1 (NU) PA6
+ BKIN2 (NU) PA11
+ BKIN3 (NU) PB14
+ POT/DAC DAC1_CH1/ADC1_IN4 PA4
+ CURR_REF (NU) PB4
+ DEBUG0 GPIO PB12
+ DEBUG1 GPIO PB9
+ DEBUG2 GPIO PC6
+ DEBUG3 GPIO PB5
+ DEBUG4 GPIO PC8
+
+ Current shunt resistance = 0.01
+ Current sense gain = -5.18 (inverted current)
+ Vbus sense gain = 9.31k/(9.31k+169k) = 0.0522
+ Vbus min = 10V
+ Vbus max = 48V
+ Iout max = 15A RMS
+
+ IPHASE_RATIO = 1/(R_shunt*gain) = -19.3
+ VBUS_RATIO = 1/VBUS_gain = 19.152
+
+ For now only 3-shunt resistors configuration is supported.
+
+lcd
+---
+
+This is basically an nsh configuration (see above) with added support
+of ILI9225 176x220 TFT display and test framebuffer application.
+
+Display connection is set to SPI 3 and pinout is following::
+
+ CS D8
+ RST D6
+ RS D7
+ SDA D4
+ CLK D3
+
+Framebuffer application can be started from terminal by typing "fb".
+
+pwm
+---
+
+This is an nsh configuration (see above) with added capability of pulse width
+modulation. PWM output is on Timer 3 channel 1, which is pin PA_6 (D12) on
+Nucleo board. Example program can be stared by "pwm" command.
diff --git a/content/docs/latest/_sources/platforms/arm/stm32f4/boards/olimex-stm32-e407/index.rst.txt b/content/docs/latest/_sources/platforms/arm/stm32f4/boards/olimex-stm32-e407/index.rst.txt
new file mode 100644
index 00000000..90a52315
--- /dev/null
+++ b/content/docs/latest/_sources/platforms/arm/stm32f4/boards/olimex-stm32-e407/index.rst.txt
@@ -0,0 +1,210 @@
+=================
+Olimex STM32-E407
+=================
+
+The Olimex STM32-E407 configuration is based on the configuration
+olimex-stm32-h407 and stm32f4discovery.
+
+Configurations
+==============
+
+Instantiating Configurations
+----------------------------
+
+Each Olimex-STM32-E407 configuration is maintained in a sub-directory and
+can be selected as follow::
+
+ tools/configure.sh [OPTIONS] olimex-stm32-e407:<subdir>
+
+Typical options include -l for a Linux host platform or -c for Cygwin
+host platform. See 'tools/configure.sh -h' for other options. And
+<subdir> is one of the sub-directories listed below.
+
+Compile Firmware
+----------------
+
+Once you've set the proper configuration, you just need to execute the next
+command::
+
+ make
+
+If everything goes find, it should return the next two files::
+
+ nuttx.hex
+ nuttx.bin
+
+You can return more kinds of files by setting on menuconfig.
+
+Flashing the Board
+------------------
+
+You can flash this board in different ways, but the easiest way is using
+ARM-USB-TINY-H JTAG flasher device.
+Connect this device to the JTAG connector and type the next command::
+
+ openocd -f interface/ftdi/olimex-arm-usb-tiny-h.cfg -f target/stm32f4x.cfg -c init -c "reset halt" -c "flash write_image erase nuttx.bin 0x08000000"
+
+Configuration Directories
+-------------------------
+
+nsh
+---
+
+Configures the NuttShell (nsh) located at apps/examples/nsh. This
+configuration enables a console on UART2. Support for
+builtin applications is enabled, but in the base configuration no
+builtin applications are selected.
+
+usbnsh
+------
+
+Configures the NuttShell (nsh) located at apps/examples/nsh. This
+configuration enables a console on USB_OTG1. Support for
+builtin applications is enabled, but in the base configuration no
+builtin applications are selected.
+
+netnsh
+------
+
+Configures the NuttShell (nsh) located at examples/nsh. This
+configuration is focused on network testing.
+
+bmp180
+------
+
+This is a configuration example for the BMP180 barometer sensor. This
+sensor works with I2C, you need to do the next connections::
+
+ BMP180 VIN -> Board 3.3V
+ BMP180 GND -> Board GND
+ BMP180 SCL -> Board PB6 (Arduino header D1)
+ BMP180 SDA -> Board PB7 (Arduino header D0)
+
+This example is configured to work with the USBNSH instead of UART NSH, so
+the console will be shown over the USB_OTG1 connector.
+
+On the console, type "ls /dev " and if the registration process goes fine,
+you should see a device called "press0". Now execute the app
+BMP180 to see the ambient pressure value.
+
+dac
+---
+
+This is a configuration example to use the DAC1 of the board. The DAC1
+is attached to the PA4 pin (Arduino header D10).
+
+This example is configured to work with the USBNSH instead of UART NSH, so
+the console will be shown over the USB_OTG1 connector.
+
+On the console, type "ls /dev " and if the registration process goes fine,
+you should see a device called "dac0". Now execute the app
+dac put a value at the output.
+
+ina219
+------
+
+This is a configuration example for the INA219 DC current sensor. This
+sensor works with I2C, you need to do the next connections::
+
+ INA219 VIN -> Board 3.3V
+ INA219 GND -> Board GND
+ INA219 SCL -> Board PB6 (Arduino header D1)
+ INA219 SDA -> Board PB7 (Arduino header D0)
+
+This example is configured to work with the USBNSH instead of UART NSH, so
+the console will be shown over the USB_OTG1 connector.
+
+On the console, type "ls /dev " and if the registration process goes fine,
+you should see a device called "ina219". Now execute the app
+ina219 to see the ambient pressure value.
+
+timer
+-----
+
+This configuration set the proper configuration to use the timer1 of the
+board. This example is configured to work with the USBNSH instead of
+UART NSH, so the console will be shown over the USB_OTG1 connector.
+
+On the console, type "ls /dev " and if the registration process goes fine,
+you should see a device called "timer1".
+
+mrf24j40-mac
+------------
+
+This configuration set the proper configuration to set the 802.15.4
+communication layer with the MRF24J40 radio. This radio works with
+SPI, you need to do the next connections::
+
+ MRF24J40 VCC -> Board 3.3V
+ MRF24J40 GND -> Board GND
+ MRF24J40 SCLK -> Board PA5 (Arduino header D13)
+ MRF24J40 MISO -> Board PA6 (Arduino header D12)
+ MRF24J40 MOSI -> Board PB5 (Arduino header D11)
+ MRF24J40 CS -> Board PA4 (Arduino header D10)
+ MRF24J40 INT -> Board PG12 (Arduino header D8)
+
+This example is configured to work with the USBNSH instead of UART NSH,
+so the console will be shown over the USB_OTG1 connector.
+
+Once you're on the console, you need to check if the initialization
+process was fine. To do so, you need to type "ls /dev" and you should
+see a device call "ieee0". At this point we need to set-up the network,
+follow the next steps::
+
+ This is an example of how to configure a coordinator:
+ i8sak /dev/ieee0 startpan cd:ab
+ i8sak set chan 11
+ i8sak set saddr 42:01
+ i8sak acceptassoc
+
+ This is an example of how to configure the endpoint:
+ i8sak /dev/ieee0
+ i8sak set chan 11
+ i8sak set panid cd:ab
+ i8sak set saddr 42:02
+ i8sak set ep_saddr 42:01
+ i8sak assoc
+
+mrf24j40-6lowpan
+----------------
+
+This configuration set the proper configuration to use 6lowpan protocol with the MRF24J40
+radio. This radio works with SPI, you need to do the next connections::
+
+ MRF24J40 VCC -> Board 3.3V
+ MRF24J40 GND -> Board GND
+ MRF24J40 SCLK -> Board PA5 (Arduino header D13)
+ MRF24J40 MISO -> Board PA6 (Arduino header D12)
+ MRF24J40 MOSI -> Board PB5 (Arduino header D11)
+ MRF24J40 CS -> Board PA4 (Arduino header D10)
+ MRF24J40 INT -> Board PG12 (Arduino header D8)
+
+This example is configured to work with the USBNSH instead of UART NSH, so
+the console will be shown over the USB_OTG1 connector.
+
+Once you're on the console, you need to check if the initialization process
+was fine. To do so, you need to type "ls /dev" and you should see a device
+call "ieee0". At this point we need to set-up the network, follow the next steps::
+
+ This is an example of how to configure a coordinator:
+ i8sak wpan0 startpan cd:ab
+ i8sak set chan 11
+ i8sak set saddr 42:01
+ i8sak acceptassoc
+
+ When the association was complete, you need to bring-up the network:
+ ifup wpan0
+
+ This is an example of how to configure the endpoint:
+ i8sak wpan0
+ i8sak set chan 11
+ i8sak set panid cd:ab
+ i8sak set saddr 42:02
+ i8sak set ep_saddr 42:01
+ i8sak assoc
+
+ When the association was complete, you need to bring-up the network:
+ ifup wpan0
+
+If you execute the command "ifconfig", you will be able to see the info of the WPAN0 interface
+and see the assigned IP. This interface can be use with an UDP or TCP server/client application.
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