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Posted to commits@tvm.apache.org by GitBox <gi...@apache.org> on 2022/01/18 01:57:31 UTC

[GitHub] [tvm] lyxcliang edited a comment on pull request #3010: [RFC] [VTA] [TSIM] Enabling Cycle-Accurate Hardware Simulation for VTA #3009

lyxcliang edited a comment on pull request #3010:
URL: https://github.com/apache/tvm/pull/3010#issuecomment-1014526809


   use https://github.com/apache/tvm-vta/tree/87ce9acfae550d1a487746e9d06c2e250076e54c/apps/tsim_example was OK. but when run "python3 tests/python/verilog_accel.py", it reported: libhw.so: undefined symbol : VTASimDPI
   ![image](https://user-images.githubusercontent.com/87418712/149775311-18afbfec-ea0d-49cb-832d-ce3519e11d54.png)
   
   the generated code is:
   ![image](https://user-images.githubusercontent.com/87418712/149857452-206f740a-95bc-4c8b-bb3f-56b2bb23acd7.png)
   
   why?


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