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Posted to commits@mynewt.apache.org by we...@apache.org on 2016/09/23 21:55:01 UTC
[1/2] incubator-mynewt-core git commit: Add hal_flash_init to the nrf
bsps. Finised the conversion of the other nrf bsps to our new config method.
Repository: incubator-mynewt-core
Updated Branches:
refs/heads/develop a5e646a0f -> e351784a1
Add hal_flash_init to the nrf bsps. Finised the conversion of the other nrf bsps
to our new config method.
Project: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/repo
Commit: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/commit/e351784a
Tree: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/tree/e351784a
Diff: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/diff/e351784a
Branch: refs/heads/develop
Commit: e351784a1c251584ed95f3c46ed7d19a0fb1ff9a
Parents: a52ff17
Author: William San Filippo <wi...@runtime.io>
Authored: Fri Sep 23 14:50:34 2016 -0700
Committer: William San Filippo <wi...@runtime.io>
Committed: Fri Sep 23 14:54:53 2016 -0700
----------------------------------------------------------------------
hw/bsp/arduino_primo_nrf52/src/os_bsp.c | 7 +-
hw/bsp/bmd300eval/src/os_bsp.c | 3 -
.../include/bsp/nrf_drv_config.h | 466 +++++++++++++++++++
hw/bsp/nrf51-arduino_101/pkg.yml | 30 +-
hw/bsp/nrf51-arduino_101/src/hal_bsp.c | 12 -
hw/bsp/nrf51-arduino_101/src/os_bsp.c | 35 +-
hw/bsp/nrf51-blenano/include/bsp/bsp.h | 5 +-
.../nrf51-blenano/include/bsp/nrf_drv_config.h | 464 ++++++++++++++++++
hw/bsp/nrf51-blenano/src/os_bsp.c | 8 +-
hw/bsp/nrf51dk-16kbram/src/os_bsp.c | 6 +-
hw/bsp/nrf51dk/src/os_bsp.c | 7 +-
hw/bsp/nrf52dk/src/os_bsp.c | 3 -
12 files changed, 997 insertions(+), 49 deletions(-)
----------------------------------------------------------------------
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/e351784a/hw/bsp/arduino_primo_nrf52/src/os_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/arduino_primo_nrf52/src/os_bsp.c b/hw/bsp/arduino_primo_nrf52/src/os_bsp.c
index 6c2c2c4..d5acadf 100644
--- a/hw/bsp/arduino_primo_nrf52/src/os_bsp.c
+++ b/hw/bsp/arduino_primo_nrf52/src/os_bsp.c
@@ -20,6 +20,7 @@
#include <assert.h>
#include "hal/flash_map.h"
#include "hal/hal_bsp.h"
+#include "hal/hal_flash.h"
#include "hal/hal_cputime.h"
#include "mcu/nrf52_hal.h"
#include "uart/uart.h"
@@ -104,8 +105,6 @@ static nrf_drv_saadc_config_t os_bsp_adc0_config = {
};
#endif
-void _close(int fd);
-
/*
* Returns the flash map slot where the currently active image is located.
* If executing from internal flash from fixed location, that slot would
@@ -141,11 +140,13 @@ bsp_init(void)
* XXX this reference is here to keep this function in.
*/
_sbrk(0);
- _close(0);
flash_area_init(bsp_flash_areas,
sizeof(bsp_flash_areas) / sizeof(bsp_flash_areas[0]));
+ rc = hal_flash_init();
+ assert(rc == 0);
+
/*
* Need to initialize cputime here, because bitbanger uart uses it.
*/
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/e351784a/hw/bsp/bmd300eval/src/os_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/bmd300eval/src/os_bsp.c b/hw/bsp/bmd300eval/src/os_bsp.c
index 259701d..a3d12eb 100644
--- a/hw/bsp/bmd300eval/src/os_bsp.c
+++ b/hw/bsp/bmd300eval/src/os_bsp.c
@@ -104,8 +104,6 @@ static nrf_drv_saadc_config_t os_bsp_adc0_config = {
};
#endif
-void _close(int fd);
-
/*
* Returns the flash map slot where the currently active image is located.
* If executing from internal flash from fixed location, that slot would
@@ -146,7 +144,6 @@ bsp_init(void)
* XXX this reference is here to keep this function in.
*/
(void)_sbrk;
- //(void)_close;
/* Set cputime to count at 1 usec increments */
rc = cputime_init(MYNEWT_VAL(CLOCK_FREQ));
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/e351784a/hw/bsp/nrf51-arduino_101/include/bsp/nrf_drv_config.h
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf51-arduino_101/include/bsp/nrf_drv_config.h b/hw/bsp/nrf51-arduino_101/include/bsp/nrf_drv_config.h
new file mode 100644
index 0000000..f97fb5c
--- /dev/null
+++ b/hw/bsp/nrf51-arduino_101/include/bsp/nrf_drv_config.h
@@ -0,0 +1,466 @@
+/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+#ifndef NRF_DRV_CONFIG_H
+#define NRF_DRV_CONFIG_H
+
+/**
+ * Provide a non-zero value here in applications that need to use several
+ * peripherals with the same ID that are sharing certain resources
+ * (for example, SPI0 and TWI0). Obviously, such peripherals cannot be used
+ * simultaneously. Therefore, this definition allows to initialize the driver
+ * for another peripheral from a given group only after the previously used one
+ * is uninitialized. Normally, this is not possible, because interrupt handlers
+ * are implemented in individual drivers.
+ * This functionality requires a more complicated interrupt handling and driver
+ * initialization, hence it is not always desirable to use it.
+ */
+#define PERIPHERAL_RESOURCE_SHARING_ENABLED 1
+
+/* CLOCK */
+#define CLOCK_ENABLED 1
+
+#if (CLOCK_ENABLED == 1)
+#define CLOCK_CONFIG_XTAL_FREQ NRF_CLOCK_XTALFREQ_Default
+#define CLOCK_CONFIG_LF_SRC NRF_CLOCK_LFCLK_Xtal
+#define CLOCK_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+/* GPIOTE */
+#define GPIOTE_ENABLED 1
+
+#if (GPIOTE_ENABLED == 1)
+#define GPIOTE_CONFIG_USE_SWI_EGU false
+#define GPIOTE_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1
+#endif
+
+/* TIMER */
+#define TIMER0_ENABLED 1
+
+#if (TIMER0_ENABLED == 1)
+#define TIMER0_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
+#define TIMER0_CONFIG_MODE TIMER_MODE_MODE_Timer
+#define TIMER0_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_32Bit
+#define TIMER0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER0_INSTANCE_INDEX 0
+#endif
+
+#define TIMER1_ENABLED 0
+
+#if (TIMER1_ENABLED == 1)
+#define TIMER1_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
+#define TIMER1_CONFIG_MODE TIMER_MODE_MODE_Timer
+#define TIMER1_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
+#define TIMER1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER1_INSTANCE_INDEX (TIMER0_ENABLED)
+#endif
+
+#define TIMER2_ENABLED 0
+
+#if (TIMER2_ENABLED == 1)
+#define TIMER2_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
+#define TIMER2_CONFIG_MODE TIMER_MODE_MODE_Timer
+#define TIMER2_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
+#define TIMER2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER2_INSTANCE_INDEX (TIMER1_ENABLED+TIMER0_ENABLED)
+#endif
+
+#define TIMER3_ENABLED 0
+
+#if (TIMER3_ENABLED == 1)
+#define TIMER3_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
+#define TIMER3_CONFIG_MODE TIMER_MODE_MODE_Timer
+#define TIMER3_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
+#define TIMER3_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER3_INSTANCE_INDEX (TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
+#endif
+
+#define TIMER4_ENABLED 0
+
+#if (TIMER4_ENABLED == 1)
+#define TIMER4_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
+#define TIMER4_CONFIG_MODE TIMER_MODE_MODE_Timer
+#define TIMER4_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
+#define TIMER4_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER4_INSTANCE_INDEX (TIMER3_ENABLED+TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
+#endif
+
+
+#define TIMER_COUNT (TIMER0_ENABLED + TIMER1_ENABLED + TIMER2_ENABLED + TIMER3_ENABLED + TIMER4_ENABLED)
+
+/* RTC */
+#define RTC0_ENABLED 0
+
+#if (RTC0_ENABLED == 1)
+#define RTC0_CONFIG_FREQUENCY 32678
+#define RTC0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define RTC0_CONFIG_RELIABLE false
+
+#define RTC0_INSTANCE_INDEX 0
+#endif
+
+#define RTC1_ENABLED 0
+
+#if (RTC1_ENABLED == 1)
+#define RTC1_CONFIG_FREQUENCY 32768
+#define RTC1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define RTC1_CONFIG_RELIABLE false
+
+#define RTC1_INSTANCE_INDEX (RTC0_ENABLED)
+#endif
+
+#define RTC2_ENABLED 0
+
+#if (RTC2_ENABLED == 1)
+#define RTC2_CONFIG_FREQUENCY 32768
+#define RTC2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define RTC2_CONFIG_RELIABLE false
+
+#define RTC2_INSTANCE_INDEX (RTC0_ENABLED+RTC1_ENABLED)
+#endif
+
+
+#define RTC_COUNT (RTC0_ENABLED+RTC1_ENABLED+RTC2_ENABLED)
+
+#define NRF_MAXIMUM_LATENCY_US 2000
+
+/* RNG */
+#define RNG_ENABLED 1
+
+#if (RNG_ENABLED == 1)
+#define RNG_CONFIG_ERROR_CORRECTION true
+#define RNG_CONFIG_POOL_SIZE 8
+#define RNG_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+/* PWM */
+
+#define PWM0_ENABLED 1
+
+#if (PWM0_ENABLED == 1)
+#define PWM0_CONFIG_OUT0_PIN 2
+#define PWM0_CONFIG_OUT1_PIN 3
+#define PWM0_CONFIG_OUT2_PIN 4
+#define PWM0_CONFIG_OUT3_PIN 5
+#define PWM0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define PWM0_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
+#define PWM0_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
+#define PWM0_CONFIG_TOP_VALUE 1000
+#define PWM0_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
+#define PWM0_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
+
+#define PWM0_INSTANCE_INDEX 0
+#endif
+
+#define PWM1_ENABLED 0
+
+#if (PWM1_ENABLED == 1)
+#define PWM1_CONFIG_OUT0_PIN 2
+#define PWM1_CONFIG_OUT1_PIN 3
+#define PWM1_CONFIG_OUT2_PIN 4
+#define PWM1_CONFIG_OUT3_PIN 5
+#define PWM1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define PWM1_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
+#define PWM1_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
+#define PWM1_CONFIG_TOP_VALUE 1000
+#define PWM1_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
+#define PWM1_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
+
+#define PWM1_INSTANCE_INDEX (PWM0_ENABLED)
+#endif
+
+#define PWM2_ENABLED 0
+
+#if (PWM2_ENABLED == 1)
+#define PWM2_CONFIG_OUT0_PIN 2
+#define PWM2_CONFIG_OUT1_PIN 3
+#define PWM2_CONFIG_OUT2_PIN 4
+#define PWM2_CONFIG_OUT3_PIN 5
+#define PWM2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define PWM2_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
+#define PWM2_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
+#define PWM2_CONFIG_TOP_VALUE 1000
+#define PWM2_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
+#define PWM2_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
+
+#define PWM2_INSTANCE_INDEX (PWM0_ENABLED + PWM1_ENABLED)
+#endif
+
+#define PWM_COUNT (PWM0_ENABLED + PWM1_ENABLED + PWM2_ENABLED)
+
+/* SPI */
+#define SPI0_ENABLED 1
+
+#if (SPI0_ENABLED == 1)
+#define SPI0_USE_EASY_DMA 0
+/* NOTE: SCK definitions match NRF51 DK product brief */
+#define SPI0_CONFIG_CSN_PIN 24 /* Note: not defined by SDK */
+#define SPI0_CONFIG_SCK_PIN 29
+#define SPI0_CONFIG_MOSI_PIN 25
+#define SPI0_CONFIG_MISO_PIN 28
+#define SPI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPI0_INSTANCE_INDEX 0
+#endif
+
+#define SPI1_ENABLED 0
+
+#if (SPI1_ENABLED == 1)
+#define SPI1_USE_EASY_DMA 0
+
+#define SPI1_CONFIG_SCK_PIN 2
+#define SPI1_CONFIG_MOSI_PIN 3
+#define SPI1_CONFIG_MISO_PIN 4
+#define SPI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPI1_INSTANCE_INDEX (SPI0_ENABLED)
+#endif
+
+#define SPI2_ENABLED 0
+
+#if (SPI2_ENABLED == 1)
+#define SPI2_USE_EASY_DMA 0
+
+#define SPI2_CONFIG_SCK_PIN 2
+#define SPI2_CONFIG_MOSI_PIN 3
+#define SPI2_CONFIG_MISO_PIN 4
+#define SPI2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPI2_INSTANCE_INDEX (SPI0_ENABLED + SPI1_ENABLED)
+#endif
+
+#define SPI_COUNT (SPI0_ENABLED + SPI1_ENABLED + SPI2_ENABLED)
+
+/* SPIS */
+#define SPIS0_ENABLED 0
+
+#if (SPIS0_ENABLED == 1)
+#define SPIS0_CONFIG_SCK_PIN 2
+#define SPIS0_CONFIG_MOSI_PIN 3
+#define SPIS0_CONFIG_MISO_PIN 4
+#define SPIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPIS0_INSTANCE_INDEX 0
+#endif
+
+#define SPIS1_ENABLED 1
+
+#if (SPIS1_ENABLED == 1)
+#define SPIS1_CONFIG_CSN_PIN 24 /* Note: not defined by SDK */
+#define SPIS1_CONFIG_SCK_PIN 29
+#define SPIS1_CONFIG_MOSI_PIN 25
+#define SPIS1_CONFIG_MISO_PIN 28
+#define SPIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPIS1_INSTANCE_INDEX SPIS0_ENABLED
+#endif
+
+#define SPIS2_ENABLED 0
+
+#if (SPIS2_ENABLED == 1)
+#define SPIS2_CONFIG_SCK_PIN 2
+#define SPIS2_CONFIG_MOSI_PIN 3
+#define SPIS2_CONFIG_MISO_PIN 4
+#define SPIS2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPIS2_INSTANCE_INDEX (SPIS0_ENABLED + SPIS1_ENABLED)
+#endif
+
+#define SPIS_COUNT (SPIS0_ENABLED + SPIS1_ENABLED + SPIS2_ENABLED)
+
+/* UART */
+#define UART0_ENABLED 1
+
+#if (UART0_ENABLED == 1)
+#define UART0_CONFIG_HWFC NRF_UART_HWFC_DISABLED
+#define UART0_CONFIG_PARITY NRF_UART_PARITY_EXCLUDED
+#define UART0_CONFIG_BAUDRATE NRF_UART_BAUDRATE_115200
+#define UART0_CONFIG_PSEL_TXD 0
+#define UART0_CONFIG_PSEL_RXD 0
+#define UART0_CONFIG_PSEL_CTS 0
+#define UART0_CONFIG_PSEL_RTS 0
+#define UART0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#ifdef NRF52
+#define UART0_CONFIG_USE_EASY_DMA false
+//Compile time flag
+#define UART_EASY_DMA_SUPPORT 1
+#define UART_LEGACY_SUPPORT 1
+#endif //NRF52
+#endif
+
+#define TWI0_ENABLED 1
+
+#if (TWI0_ENABLED == 1)
+#define TWI0_USE_EASY_DMA 0
+
+#define TWI0_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
+#define TWI0_CONFIG_SCL 0
+#define TWI0_CONFIG_SDA 1
+#define TWI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TWI0_INSTANCE_INDEX 0
+#endif
+
+#define TWI1_ENABLED 0
+
+#if (TWI1_ENABLED == 1)
+#define TWI1_USE_EASY_DMA 0
+
+#define TWI1_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
+#define TWI1_CONFIG_SCL 0
+#define TWI1_CONFIG_SDA 1
+#define TWI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TWI1_INSTANCE_INDEX (TWI0_ENABLED)
+#endif
+
+#define TWI_COUNT (TWI0_ENABLED + TWI1_ENABLED)
+
+/* TWIS */
+#define TWIS0_ENABLED 0
+
+#if (TWIS0_ENABLED == 1)
+ #define TWIS0_CONFIG_ADDR0 0
+ #define TWIS0_CONFIG_ADDR1 0 /* 0: Disabled */
+ #define TWIS0_CONFIG_SCL 0
+ #define TWIS0_CONFIG_SDA 1
+ #define TWIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+ #define TWIS0_INSTANCE_INDEX 0
+#endif
+
+#define TWIS1_ENABLED 0
+
+#if (TWIS1_ENABLED == 1)
+ #define TWIS1_CONFIG_ADDR0 0
+ #define TWIS1_CONFIG_ADDR1 0 /* 0: Disabled */
+ #define TWIS1_CONFIG_SCL 0
+ #define TWIS1_CONFIG_SDA 1
+ #define TWIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+ #define TWIS1_INSTANCE_INDEX (TWIS0_ENABLED)
+#endif
+
+#define TWIS_COUNT (TWIS0_ENABLED + TWIS1_ENABLED)
+/* For more documentation see nrf_drv_twis.h file */
+#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
+/* For more documentation see nrf_drv_twis.h file */
+#define TWIS_NO_SYNC_MODE 0
+
+/* QDEC */
+#define QDEC_ENABLED 1
+
+#if (QDEC_ENABLED == 1)
+#define QDEC_CONFIG_REPORTPER NRF_QDEC_REPORTPER_10
+#define QDEC_CONFIG_SAMPLEPER NRF_QDEC_SAMPLEPER_16384us
+#define QDEC_CONFIG_PIO_A 1
+#define QDEC_CONFIG_PIO_B 2
+#define QDEC_CONFIG_PIO_LED 3
+#define QDEC_CONFIG_LEDPRE 511
+#define QDEC_CONFIG_LEDPOL NRF_QDEC_LEPOL_ACTIVE_HIGH
+#define QDEC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define QDEC_CONFIG_DBFEN false
+#define QDEC_CONFIG_SAMPLE_INTEN false
+#endif
+
+/* ADC */
+#define ADC_ENABLED 1
+
+#if (ADC_ENABLED == 1)
+#define ADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+
+/* SAADC */
+#define SAADC_ENABLED 0
+
+#if (SAADC_ENABLED == 1)
+#define SAADC_CONFIG_RESOLUTION NRF_SAADC_RESOLUTION_10BIT
+#define SAADC_CONFIG_OVERSAMPLE NRF_SAADC_OVERSAMPLE_DISABLED
+#define SAADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+/* PDM */
+#define PDM_ENABLED 0
+
+#if (PDM_ENABLED == 1)
+#define PDM_CONFIG_MODE NRF_PDM_MODE_MONO
+#define PDM_CONFIG_EDGE NRF_PDM_EDGE_LEFTFALLING
+#define PDM_CONFIG_CLOCK_FREQ NRF_PDM_FREQ_1032K
+#define PDM_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+/* COMP */
+#define COMP_ENABLED 0
+
+#if (COMP_ENABLED == 1)
+#define COMP_CONFIG_REF NRF_COMP_REF_Int1V8
+#define COMP_CONFIG_MAIN_MODE NRF_COMP_MAIN_MODE_SE
+#define COMP_CONFIG_SPEED_MODE NRF_COMP_SP_MODE_High
+#define COMP_CONFIG_HYST NRF_COMP_HYST_NoHyst
+#define COMP_CONFIG_ISOURCE NRF_COMP_ISOURCE_Off
+#define COMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define COMP_CONFIG_INPUT NRF_COMP_INPUT_0
+#endif
+
+/* LPCOMP */
+#define LPCOMP_ENABLED 1
+
+#if (LPCOMP_ENABLED == 1)
+#define LPCOMP_CONFIG_REFERENCE NRF_LPCOMP_REF_SUPPLY_4_8
+#define LPCOMP_CONFIG_DETECTION NRF_LPCOMP_DETECT_DOWN
+#define LPCOMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define LPCOMP_CONFIG_INPUT NRF_LPCOMP_INPUT_0
+#endif
+
+/* WDT */
+#define WDT_ENABLED 1
+
+#if (WDT_ENABLED == 1)
+#define WDT_CONFIG_BEHAVIOUR NRF_WDT_BEHAVIOUR_RUN_SLEEP
+#define WDT_CONFIG_RELOAD_VALUE 2000
+#define WDT_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
+#endif
+
+/* SWI EGU */
+#ifdef NRF52
+ #define EGU_ENABLED 0
+#endif
+
+/* I2S */
+#define I2S_ENABLED 0
+
+#if (I2S_ENABLED == 1)
+#define I2S_CONFIG_SCK_PIN 22
+#define I2S_CONFIG_LRCK_PIN 23
+#define I2S_CONFIG_MCK_PIN NRF_DRV_I2S_PIN_NOT_USED
+#define I2S_CONFIG_SDOUT_PIN 24
+#define I2S_CONFIG_SDIN_PIN 25
+#define I2S_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
+#define I2S_CONFIG_MASTER NRF_I2S_MODE_MASTER
+#define I2S_CONFIG_FORMAT NRF_I2S_FORMAT_I2S
+#define I2S_CONFIG_ALIGN NRF_I2S_ALIGN_LEFT
+#define I2S_CONFIG_SWIDTH NRF_I2S_SWIDTH_16BIT
+#define I2S_CONFIG_CHANNELS NRF_I2S_CHANNELS_STEREO
+#define I2S_CONFIG_MCK_SETUP NRF_I2S_MCK_32MDIV8
+#define I2S_CONFIG_RATIO NRF_I2S_RATIO_256X
+#endif
+
+#include "nrf_drv_config_validation.h"
+
+#endif // NRF_DRV_CONFIG_H
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/e351784a/hw/bsp/nrf51-arduino_101/pkg.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf51-arduino_101/pkg.yml b/hw/bsp/nrf51-arduino_101/pkg.yml
index e451a2e..b674f31 100644
--- a/hw/bsp/nrf51-arduino_101/pkg.yml
+++ b/hw/bsp/nrf51-arduino_101/pkg.yml
@@ -34,7 +34,7 @@ pkg.downloadscript: nrf51dk-16kbram_download.sh
pkg.debugscript: nrf51dk-16kbram_debug.sh
pkg.cflags:
# Nordic SDK files require these defines.
- - '-DNRF52'
+ - '-DNRF51'
pkg.deps:
- hw/mcu/nordic/nrf51xxx
@@ -59,7 +59,7 @@ pkg.syscfg_defs:
CLOCK_FREQ:
description: 'TBD'
- value: 1000000
+ value: 1000000
XTAL_32768:
description: 'TBD'
@@ -68,26 +68,32 @@ pkg.syscfg_defs:
ADC_0:
description: 'TBD'
value: 0
- ADC_0_RESOLUTION:
- description: 'TBD'
- value: 'SAADC_CONFIG_RESOLUTION'
- ADC_0_OVERSAMPLE:
- description: 'TBD'
- value: 'SAADC_CONFIG_OVERSAMPLE'
ADC_0_INTERRUPT_PRIORITY:
description: 'TBD'
- value: 'SAADC_CONFIG_IRQ_PRIORITY'
+ value: 'ADC_CONFIG_IRQ_PRIORITY'
UART_0:
description: 'TBD'
- value: 1
+ value: 1
+ UART_0_PIN_TX:
+ description: 'TBD'
+ value: 9
+ UART_0_PIN_RX:
+ description: 'TBD'
+ value: 11
+ UART_0_PIN_RTS:
+ description: 'TBD'
+ value: 12
+ UART_0_PIN_CTS:
+ description: 'TBD'
+ value: 10
UART_1:
description: 'TBD'
value: 0
SPI_MASTER:
description: 'TBD'
- value: 0
+ value: 0
SPI_SLAVE:
description: 'TBD'
- value: 0
+ value: 0
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/e351784a/hw/bsp/nrf51-arduino_101/src/hal_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf51-arduino_101/src/hal_bsp.c b/hw/bsp/nrf51-arduino_101/src/hal_bsp.c
index f6af3f6..43ed472 100644
--- a/hw/bsp/nrf51-arduino_101/src/hal_bsp.c
+++ b/hw/bsp/nrf51-arduino_101/src/hal_bsp.c
@@ -24,13 +24,6 @@
#include <hal/hal_bsp.h>
#include "bsp/bsp.h"
-static const struct nrf51_uart_cfg uart_cfg = {
- .suc_pin_tx = 9,
- .suc_pin_rx = 11,
- .suc_pin_rts = 12,
- .suc_pin_cts = 10
-};
-
/*
* What memory to include in coredump.
*/
@@ -41,11 +34,6 @@ static const struct bsp_mem_dump dump_cfg[] = {
}
};
-const struct nrf51_uart_cfg *bsp_uart_config(void)
-{
- return &uart_cfg;
-}
-
const struct hal_flash *
bsp_flash_dev(uint8_t id)
{
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/e351784a/hw/bsp/nrf51-arduino_101/src/os_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf51-arduino_101/src/os_bsp.c b/hw/bsp/nrf51-arduino_101/src/os_bsp.c
index 4ae480e..7b89fbc 100644
--- a/hw/bsp/nrf51-arduino_101/src/os_bsp.c
+++ b/hw/bsp/nrf51-arduino_101/src/os_bsp.c
@@ -16,12 +16,18 @@
* specific language governing permissions and limitations
* under the License.
*/
-#include <hal/flash_map.h>
-#include <hal/hal_bsp.h>
+#include <assert.h>
+#include "syscfg/syscfg.h"
+#include "hal/flash_map.h"
+#include "hal/hal_flash.h"
+#include "hal/hal_bsp.h"
#include "bsp/cmsis_nvic.h"
#include "nrf51.h"
#include "nrf51_bitfields.h"
#include "mcu/nrf51_hal.h"
+#include "os/os_dev.h"
+#include "uart/uart.h"
+#include "uart_hal/uart_hal.h"
#define BSP_LOWEST_PRIO ((1 << __NVIC_PRIO_BITS) - 1)
@@ -53,7 +59,15 @@ static struct flash_area bsp_flash_areas[] = {
}
};
-void _close(int fd);
+#if MYNEWT_VAL(UART_0)
+static struct uart_dev os_bsp_uart0;
+static const struct nrf51_uart_cfg os_bsp_uart0_cfg = {
+ .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS),
+};
+#endif
/*
* Returns the flash map slot where the currently active image is located.
@@ -72,15 +86,24 @@ bsp_imgr_current_slot(void)
void
bsp_init(void)
{
+ int rc;
+
+#if MYNEWT_VAL(UART_0)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart0, "uart0",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&os_bsp_uart0_cfg);
+ assert(rc == 0);
+#endif
+
/*
* XXX this reference is here to keep this function in.
*/
_sbrk(0);
- _close(0);
flash_area_init(bsp_flash_areas,
sizeof(bsp_flash_areas) / sizeof(bsp_flash_areas[0]));
+ rc = hal_flash_init();
+ assert(rc == 0);
}
extern void timer_handler(void);
@@ -94,7 +117,7 @@ rtc0_timer_handler(void)
}
void
-os_bsp_systick_init(uint32_t os_ticks_per_sec)
+os_bsp_systick_init(uint32_t os_ticks_per_sec, int prio)
{
uint32_t ctx;
uint32_t mask;
@@ -130,7 +153,7 @@ os_bsp_systick_init(uint32_t os_ticks_per_sec)
NRF_RTC0->TASKS_CLEAR = 1;
/* Set isr in vector table and enable interrupt */
- NVIC_SetPriority(RTC0_IRQn, BSP_LOWEST_PRIO - 1);
+ NVIC_SetPriority(RTC0_IRQn, prio);
NVIC_SetVector(RTC0_IRQn, (uint32_t)rtc0_timer_handler);
NVIC_EnableIRQ(RTC0_IRQn);
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/e351784a/hw/bsp/nrf51-blenano/include/bsp/bsp.h
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf51-blenano/include/bsp/bsp.h b/hw/bsp/nrf51-blenano/include/bsp/bsp.h
index 520dd67..65caf62 100644
--- a/hw/bsp/nrf51-blenano/include/bsp/bsp.h
+++ b/hw/bsp/nrf51-blenano/include/bsp/bsp.h
@@ -6,7 +6,7 @@
* to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
- *
+ *
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
@@ -35,7 +35,8 @@ extern "C" {
#define LED_BLINK_PIN (19)
/* UART info */
-#define CONSOLE_UART 0
+#define CONSOLE_UART "uart0"
+#define CONSOLE_UART_SPEED 115200
int bsp_imgr_current_slot(void);
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/e351784a/hw/bsp/nrf51-blenano/include/bsp/nrf_drv_config.h
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf51-blenano/include/bsp/nrf_drv_config.h b/hw/bsp/nrf51-blenano/include/bsp/nrf_drv_config.h
new file mode 100644
index 0000000..feac50b
--- /dev/null
+++ b/hw/bsp/nrf51-blenano/include/bsp/nrf_drv_config.h
@@ -0,0 +1,464 @@
+/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+#ifndef NRF_DRV_CONFIG_H
+#define NRF_DRV_CONFIG_H
+
+/**
+ * Provide a non-zero value here in applications that need to use several
+ * peripherals with the same ID that are sharing certain resources
+ * (for example, SPI0 and TWI0). Obviously, such peripherals cannot be used
+ * simultaneously. Therefore, this definition allows to initialize the driver
+ * for another peripheral from a given group only after the previously used one
+ * is uninitialized. Normally, this is not possible, because interrupt handlers
+ * are implemented in individual drivers.
+ * This functionality requires a more complicated interrupt handling and driver
+ * initialization, hence it is not always desirable to use it.
+ */
+#define PERIPHERAL_RESOURCE_SHARING_ENABLED 1
+
+/* CLOCK */
+#define CLOCK_ENABLED 1
+
+#if (CLOCK_ENABLED == 1)
+#define CLOCK_CONFIG_XTAL_FREQ NRF_CLOCK_XTALFREQ_Default
+#define CLOCK_CONFIG_LF_SRC NRF_CLOCK_LFCLK_Xtal
+#define CLOCK_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+/* GPIOTE */
+#define GPIOTE_ENABLED 1
+
+#if (GPIOTE_ENABLED == 1)
+#define GPIOTE_CONFIG_USE_SWI_EGU false
+#define GPIOTE_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 1
+#endif
+
+/* TIMER */
+#define TIMER0_ENABLED 1
+
+#if (TIMER0_ENABLED == 1)
+#define TIMER0_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
+#define TIMER0_CONFIG_MODE TIMER_MODE_MODE_Timer
+#define TIMER0_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_32Bit
+#define TIMER0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER0_INSTANCE_INDEX 0
+#endif
+
+#define TIMER1_ENABLED 0
+
+#if (TIMER1_ENABLED == 1)
+#define TIMER1_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
+#define TIMER1_CONFIG_MODE TIMER_MODE_MODE_Timer
+#define TIMER1_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
+#define TIMER1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER1_INSTANCE_INDEX (TIMER0_ENABLED)
+#endif
+
+#define TIMER2_ENABLED 0
+
+#if (TIMER2_ENABLED == 1)
+#define TIMER2_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
+#define TIMER2_CONFIG_MODE TIMER_MODE_MODE_Timer
+#define TIMER2_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
+#define TIMER2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER2_INSTANCE_INDEX (TIMER1_ENABLED+TIMER0_ENABLED)
+#endif
+
+#define TIMER3_ENABLED 0
+
+#if (TIMER3_ENABLED == 1)
+#define TIMER3_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
+#define TIMER3_CONFIG_MODE TIMER_MODE_MODE_Timer
+#define TIMER3_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
+#define TIMER3_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER3_INSTANCE_INDEX (TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
+#endif
+
+#define TIMER4_ENABLED 0
+
+#if (TIMER4_ENABLED == 1)
+#define TIMER4_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz
+#define TIMER4_CONFIG_MODE TIMER_MODE_MODE_Timer
+#define TIMER4_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit
+#define TIMER4_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER4_INSTANCE_INDEX (TIMER3_ENABLED+TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
+#endif
+
+
+#define TIMER_COUNT (TIMER0_ENABLED + TIMER1_ENABLED + TIMER2_ENABLED + TIMER3_ENABLED + TIMER4_ENABLED)
+
+/* RTC */
+#define RTC0_ENABLED 0
+
+#if (RTC0_ENABLED == 1)
+#define RTC0_CONFIG_FREQUENCY 32678
+#define RTC0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define RTC0_CONFIG_RELIABLE false
+
+#define RTC0_INSTANCE_INDEX 0
+#endif
+
+#define RTC1_ENABLED 0
+
+#if (RTC1_ENABLED == 1)
+#define RTC1_CONFIG_FREQUENCY 32768
+#define RTC1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define RTC1_CONFIG_RELIABLE false
+
+#define RTC1_INSTANCE_INDEX (RTC0_ENABLED)
+#endif
+
+#define RTC2_ENABLED 0
+
+#if (RTC2_ENABLED == 1)
+#define RTC2_CONFIG_FREQUENCY 32768
+#define RTC2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define RTC2_CONFIG_RELIABLE false
+
+#define RTC2_INSTANCE_INDEX (RTC0_ENABLED+RTC1_ENABLED)
+#endif
+
+
+#define RTC_COUNT (RTC0_ENABLED+RTC1_ENABLED+RTC2_ENABLED)
+
+#define NRF_MAXIMUM_LATENCY_US 2000
+
+/* RNG */
+#define RNG_ENABLED 1
+
+#if (RNG_ENABLED == 1)
+#define RNG_CONFIG_ERROR_CORRECTION true
+#define RNG_CONFIG_POOL_SIZE 8
+#define RNG_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+/* PWM */
+
+#define PWM0_ENABLED 1
+
+#if (PWM0_ENABLED == 1)
+#define PWM0_CONFIG_OUT0_PIN 2
+#define PWM0_CONFIG_OUT1_PIN 3
+#define PWM0_CONFIG_OUT2_PIN 4
+#define PWM0_CONFIG_OUT3_PIN 5
+#define PWM0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define PWM0_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
+#define PWM0_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
+#define PWM0_CONFIG_TOP_VALUE 1000
+#define PWM0_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
+#define PWM0_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
+
+#define PWM0_INSTANCE_INDEX 0
+#endif
+
+#define PWM1_ENABLED 0
+
+#if (PWM1_ENABLED == 1)
+#define PWM1_CONFIG_OUT0_PIN 2
+#define PWM1_CONFIG_OUT1_PIN 3
+#define PWM1_CONFIG_OUT2_PIN 4
+#define PWM1_CONFIG_OUT3_PIN 5
+#define PWM1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define PWM1_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
+#define PWM1_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
+#define PWM1_CONFIG_TOP_VALUE 1000
+#define PWM1_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
+#define PWM1_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
+
+#define PWM1_INSTANCE_INDEX (PWM0_ENABLED)
+#endif
+
+#define PWM2_ENABLED 0
+
+#if (PWM2_ENABLED == 1)
+#define PWM2_CONFIG_OUT0_PIN 2
+#define PWM2_CONFIG_OUT1_PIN 3
+#define PWM2_CONFIG_OUT2_PIN 4
+#define PWM2_CONFIG_OUT3_PIN 5
+#define PWM2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define PWM2_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz
+#define PWM2_CONFIG_COUNT_MODE NRF_PWM_MODE_UP
+#define PWM2_CONFIG_TOP_VALUE 1000
+#define PWM2_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON
+#define PWM2_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO
+
+#define PWM2_INSTANCE_INDEX (PWM0_ENABLED + PWM1_ENABLED)
+#endif
+
+#define PWM_COUNT (PWM0_ENABLED + PWM1_ENABLED + PWM2_ENABLED)
+
+/* SPI */
+#define SPI0_ENABLED 1
+
+#if (SPI0_ENABLED == 1)
+#define SPI0_USE_EASY_DMA 0
+/* NOTE: SCK definitions match NRF51 DK product brief */
+#define SPI0_CONFIG_SCK_PIN 29
+#define SPI0_CONFIG_MOSI_PIN 25
+#define SPI0_CONFIG_MISO_PIN 28
+#define SPI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPI0_INSTANCE_INDEX 0
+#endif
+
+#define SPI1_ENABLED 0
+
+#if (SPI1_ENABLED == 1)
+#define SPI1_USE_EASY_DMA 0
+
+#define SPI1_CONFIG_SCK_PIN 2
+#define SPI1_CONFIG_MOSI_PIN 3
+#define SPI1_CONFIG_MISO_PIN 4
+#define SPI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPI1_INSTANCE_INDEX (SPI0_ENABLED)
+#endif
+
+#define SPI2_ENABLED 0
+
+#if (SPI2_ENABLED == 1)
+#define SPI2_USE_EASY_DMA 0
+
+#define SPI2_CONFIG_SCK_PIN 2
+#define SPI2_CONFIG_MOSI_PIN 3
+#define SPI2_CONFIG_MISO_PIN 4
+#define SPI2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPI2_INSTANCE_INDEX (SPI0_ENABLED + SPI1_ENABLED)
+#endif
+
+#define SPI_COUNT (SPI0_ENABLED + SPI1_ENABLED + SPI2_ENABLED)
+
+/* SPIS */
+#define SPIS0_ENABLED 0
+
+#if (SPIS0_ENABLED == 1)
+#define SPIS0_CONFIG_SCK_PIN 2
+#define SPIS0_CONFIG_MOSI_PIN 3
+#define SPIS0_CONFIG_MISO_PIN 4
+#define SPIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPIS0_INSTANCE_INDEX 0
+#endif
+
+#define SPIS1_ENABLED 1
+
+#if (SPIS1_ENABLED == 1)
+#define SPIS1_CONFIG_SCK_PIN 29
+#define SPIS1_CONFIG_MOSI_PIN 25
+#define SPIS1_CONFIG_MISO_PIN 28
+#define SPIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPIS1_INSTANCE_INDEX SPIS0_ENABLED
+#endif
+
+#define SPIS2_ENABLED 0
+
+#if (SPIS2_ENABLED == 1)
+#define SPIS2_CONFIG_SCK_PIN 2
+#define SPIS2_CONFIG_MOSI_PIN 3
+#define SPIS2_CONFIG_MISO_PIN 4
+#define SPIS2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define SPIS2_INSTANCE_INDEX (SPIS0_ENABLED + SPIS1_ENABLED)
+#endif
+
+#define SPIS_COUNT (SPIS0_ENABLED + SPIS1_ENABLED + SPIS2_ENABLED)
+
+/* UART */
+#define UART0_ENABLED 1
+
+#if (UART0_ENABLED == 1)
+#define UART0_CONFIG_HWFC NRF_UART_HWFC_DISABLED
+#define UART0_CONFIG_PARITY NRF_UART_PARITY_EXCLUDED
+#define UART0_CONFIG_BAUDRATE NRF_UART_BAUDRATE_115200
+#define UART0_CONFIG_PSEL_TXD 0
+#define UART0_CONFIG_PSEL_RXD 0
+#define UART0_CONFIG_PSEL_CTS 0
+#define UART0_CONFIG_PSEL_RTS 0
+#define UART0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#ifdef NRF52
+#define UART0_CONFIG_USE_EASY_DMA false
+//Compile time flag
+#define UART_EASY_DMA_SUPPORT 1
+#define UART_LEGACY_SUPPORT 1
+#endif //NRF52
+#endif
+
+#define TWI0_ENABLED 1
+
+#if (TWI0_ENABLED == 1)
+#define TWI0_USE_EASY_DMA 0
+
+#define TWI0_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
+#define TWI0_CONFIG_SCL 0
+#define TWI0_CONFIG_SDA 1
+#define TWI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TWI0_INSTANCE_INDEX 0
+#endif
+
+#define TWI1_ENABLED 0
+
+#if (TWI1_ENABLED == 1)
+#define TWI1_USE_EASY_DMA 0
+
+#define TWI1_CONFIG_FREQUENCY NRF_TWI_FREQ_100K
+#define TWI1_CONFIG_SCL 0
+#define TWI1_CONFIG_SDA 1
+#define TWI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TWI1_INSTANCE_INDEX (TWI0_ENABLED)
+#endif
+
+#define TWI_COUNT (TWI0_ENABLED + TWI1_ENABLED)
+
+/* TWIS */
+#define TWIS0_ENABLED 0
+
+#if (TWIS0_ENABLED == 1)
+ #define TWIS0_CONFIG_ADDR0 0
+ #define TWIS0_CONFIG_ADDR1 0 /* 0: Disabled */
+ #define TWIS0_CONFIG_SCL 0
+ #define TWIS0_CONFIG_SDA 1
+ #define TWIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+ #define TWIS0_INSTANCE_INDEX 0
+#endif
+
+#define TWIS1_ENABLED 0
+
+#if (TWIS1_ENABLED == 1)
+ #define TWIS1_CONFIG_ADDR0 0
+ #define TWIS1_CONFIG_ADDR1 0 /* 0: Disabled */
+ #define TWIS1_CONFIG_SCL 0
+ #define TWIS1_CONFIG_SDA 1
+ #define TWIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+ #define TWIS1_INSTANCE_INDEX (TWIS0_ENABLED)
+#endif
+
+#define TWIS_COUNT (TWIS0_ENABLED + TWIS1_ENABLED)
+/* For more documentation see nrf_drv_twis.h file */
+#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
+/* For more documentation see nrf_drv_twis.h file */
+#define TWIS_NO_SYNC_MODE 0
+
+/* QDEC */
+#define QDEC_ENABLED 1
+
+#if (QDEC_ENABLED == 1)
+#define QDEC_CONFIG_REPORTPER NRF_QDEC_REPORTPER_10
+#define QDEC_CONFIG_SAMPLEPER NRF_QDEC_SAMPLEPER_16384us
+#define QDEC_CONFIG_PIO_A 1
+#define QDEC_CONFIG_PIO_B 2
+#define QDEC_CONFIG_PIO_LED 3
+#define QDEC_CONFIG_LEDPRE 511
+#define QDEC_CONFIG_LEDPOL NRF_QDEC_LEPOL_ACTIVE_HIGH
+#define QDEC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define QDEC_CONFIG_DBFEN false
+#define QDEC_CONFIG_SAMPLE_INTEN false
+#endif
+
+/* ADC */
+#define ADC_ENABLED 1
+
+#if (ADC_ENABLED == 1)
+#define ADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+
+/* SAADC */
+#define SAADC_ENABLED 0
+
+#if (SAADC_ENABLED == 1)
+#define SAADC_CONFIG_RESOLUTION NRF_SAADC_RESOLUTION_10BIT
+#define SAADC_CONFIG_OVERSAMPLE NRF_SAADC_OVERSAMPLE_DISABLED
+#define SAADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+/* PDM */
+#define PDM_ENABLED 0
+
+#if (PDM_ENABLED == 1)
+#define PDM_CONFIG_MODE NRF_PDM_MODE_MONO
+#define PDM_CONFIG_EDGE NRF_PDM_EDGE_LEFTFALLING
+#define PDM_CONFIG_CLOCK_FREQ NRF_PDM_FREQ_1032K
+#define PDM_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+/* COMP */
+#define COMP_ENABLED 0
+
+#if (COMP_ENABLED == 1)
+#define COMP_CONFIG_REF NRF_COMP_REF_Int1V8
+#define COMP_CONFIG_MAIN_MODE NRF_COMP_MAIN_MODE_SE
+#define COMP_CONFIG_SPEED_MODE NRF_COMP_SP_MODE_High
+#define COMP_CONFIG_HYST NRF_COMP_HYST_NoHyst
+#define COMP_CONFIG_ISOURCE NRF_COMP_ISOURCE_Off
+#define COMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define COMP_CONFIG_INPUT NRF_COMP_INPUT_0
+#endif
+
+/* LPCOMP */
+#define LPCOMP_ENABLED 1
+
+#if (LPCOMP_ENABLED == 1)
+#define LPCOMP_CONFIG_REFERENCE NRF_LPCOMP_REF_SUPPLY_4_8
+#define LPCOMP_CONFIG_DETECTION NRF_LPCOMP_DETECT_DOWN
+#define LPCOMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define LPCOMP_CONFIG_INPUT NRF_LPCOMP_INPUT_0
+#endif
+
+/* WDT */
+#define WDT_ENABLED 1
+
+#if (WDT_ENABLED == 1)
+#define WDT_CONFIG_BEHAVIOUR NRF_WDT_BEHAVIOUR_RUN_SLEEP
+#define WDT_CONFIG_RELOAD_VALUE 2000
+#define WDT_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
+#endif
+
+/* SWI EGU */
+#ifdef NRF52
+ #define EGU_ENABLED 0
+#endif
+
+/* I2S */
+#define I2S_ENABLED 0
+
+#if (I2S_ENABLED == 1)
+#define I2S_CONFIG_SCK_PIN 22
+#define I2S_CONFIG_LRCK_PIN 23
+#define I2S_CONFIG_MCK_PIN NRF_DRV_I2S_PIN_NOT_USED
+#define I2S_CONFIG_SDOUT_PIN 24
+#define I2S_CONFIG_SDIN_PIN 25
+#define I2S_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
+#define I2S_CONFIG_MASTER NRF_I2S_MODE_MASTER
+#define I2S_CONFIG_FORMAT NRF_I2S_FORMAT_I2S
+#define I2S_CONFIG_ALIGN NRF_I2S_ALIGN_LEFT
+#define I2S_CONFIG_SWIDTH NRF_I2S_SWIDTH_16BIT
+#define I2S_CONFIG_CHANNELS NRF_I2S_CHANNELS_STEREO
+#define I2S_CONFIG_MCK_SETUP NRF_I2S_MCK_32MDIV8
+#define I2S_CONFIG_RATIO NRF_I2S_RATIO_256X
+#endif
+
+#include "nrf_drv_config_validation.h"
+
+#endif // NRF_DRV_CONFIG_H
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/e351784a/hw/bsp/nrf51-blenano/src/os_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf51-blenano/src/os_bsp.c b/hw/bsp/nrf51-blenano/src/os_bsp.c
index b17be8f..19becb2 100644
--- a/hw/bsp/nrf51-blenano/src/os_bsp.c
+++ b/hw/bsp/nrf51-blenano/src/os_bsp.c
@@ -6,7 +6,7 @@
* to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
- *
+ *
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
@@ -20,6 +20,7 @@
#include <assert.h>
#include "syscfg/syscfg.h"
#include "hal/flash_map.h"
+#include "hal/hal_flash.h"
#if MYNEWT_VAL(UART_0)
#include "mcu/nrf51_hal.h"
#include "uart/uart.h"
@@ -67,7 +68,6 @@ static const struct nrf51_uart_cfg os_bsp_uart0_cfg = {
#endif
void *_sbrk(int incr);
-void _close(int fd);
/*
* Returns the flash map slot where the currently active image is located.
@@ -100,11 +100,13 @@ bsp_init(void)
* XXX this reference is here to keep this function in.
*/
_sbrk(0);
- _close(0);
flash_area_init(bsp_flash_areas,
sizeof(bsp_flash_areas) / sizeof(bsp_flash_areas[0]));
+ rc = hal_flash_init();
+ assert(rc == 0);
+
#if MYNEWT_VAL(UART_0)
rc = os_dev_create((struct os_dev *) &os_bsp_uart0, "uart0",
OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&os_bsp_uart0_cfg);
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/e351784a/hw/bsp/nrf51dk-16kbram/src/os_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf51dk-16kbram/src/os_bsp.c b/hw/bsp/nrf51dk-16kbram/src/os_bsp.c
index 4fc35e0..95115a6 100644
--- a/hw/bsp/nrf51dk-16kbram/src/os_bsp.c
+++ b/hw/bsp/nrf51dk-16kbram/src/os_bsp.c
@@ -20,6 +20,7 @@
#include "syscfg/syscfg.h"
#include "bsp.h"
#include "hal/flash_map.h"
+#include "hal/hal_flash.h"
#include "hal/hal_bsp.h"
#include "hal/hal_spi.h"
#include "mcu/nrf51_hal.h"
@@ -73,7 +74,6 @@ static const struct nrf51_uart_cfg os_bsp_uart0_cfg = {
};
#endif
-void _close(int fd);
void bsp_hal_init(void);
/*
@@ -120,11 +120,13 @@ bsp_init(void)
* XXX this reference is here to keep this function in.
*/
_sbrk(0);
- _close(0);
flash_area_init(bsp_flash_areas,
sizeof(bsp_flash_areas) / sizeof(bsp_flash_areas[0]));
+ rc = hal_flash_init();
+ assert(rc == 0);
+
#if MYNEWT_VAL(SPI_MASTER)
rc = hal_spi_init(0, &spi_cfg, HAL_SPI_TYPE_MASTER);
assert(rc == 0);
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/e351784a/hw/bsp/nrf51dk/src/os_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf51dk/src/os_bsp.c b/hw/bsp/nrf51dk/src/os_bsp.c
index dfdc22c..8c5a07c 100644
--- a/hw/bsp/nrf51dk/src/os_bsp.c
+++ b/hw/bsp/nrf51dk/src/os_bsp.c
@@ -20,6 +20,7 @@
#include "syscfg/syscfg.h"
#include "bsp.h"
#include "hal/flash_map.h"
+#include "hal/hal_flash.h"
#include "hal/hal_bsp.h"
#include "hal/hal_spi.h"
#include "mcu/nrf51_hal.h"
@@ -73,8 +74,6 @@ static const struct nrf51_uart_cfg os_bsp_uart0_cfg = {
};
#endif
-void _close(int fd);
-
/*
* Returns the flash map slot where the currently active image is located.
* If executing from internal flash from fixed location, that slot would
@@ -119,11 +118,13 @@ bsp_init(void)
* XXX this reference is here to keep this function in.
*/
_sbrk(0);
- _close(0);
flash_area_init(bsp_flash_areas,
sizeof(bsp_flash_areas) / sizeof(bsp_flash_areas[0]));
+ rc = hal_flash_init();
+ assert(rc == 0);
+
#if MYNEWT_VAL(SPI_MASTER)
rc = hal_spi_init(0, &spi_cfg, HAL_SPI_TYPE_MASTER);
assert(rc == 0);
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/e351784a/hw/bsp/nrf52dk/src/os_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf52dk/src/os_bsp.c b/hw/bsp/nrf52dk/src/os_bsp.c
index 396ef82..4f90473 100644
--- a/hw/bsp/nrf52dk/src/os_bsp.c
+++ b/hw/bsp/nrf52dk/src/os_bsp.c
@@ -105,8 +105,6 @@ static nrf_drv_saadc_config_t os_bsp_adc0_config = {
};
#endif
-//void _close(int fd);
-
/*
* Returns the flash map slot where the currently active image is located.
* If executing from internal flash from fixed location, that slot would
@@ -147,7 +145,6 @@ bsp_init(void)
* XXX this reference is here to keep this function in.
*/
(void)_sbrk;
- //(void)_close;
/* Set cputime to count at 1 usec increments */
rc = cputime_init(MYNEWT_VAL(CLOCK_FREQ));
[2/2] incubator-mynewt-core git commit: Sys reboot needs to depend on
sys/config
Posted by we...@apache.org.
Sys reboot needs to depend on sys/config
Project: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/repo
Commit: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/commit/a52ff170
Tree: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/tree/a52ff170
Diff: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/diff/a52ff170
Branch: refs/heads/develop
Commit: a52ff1706ae110a6f6618288a48c2e1b8a2afa80
Parents: a5e646a
Author: William San Filippo <wi...@runtime.io>
Authored: Fri Sep 23 13:21:19 2016 -0700
Committer: William San Filippo <wi...@runtime.io>
Committed: Fri Sep 23 14:54:53 2016 -0700
----------------------------------------------------------------------
sys/reboot/pkg.yml | 1 +
1 file changed, 1 insertion(+)
----------------------------------------------------------------------
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/a52ff170/sys/reboot/pkg.yml
----------------------------------------------------------------------
diff --git a/sys/reboot/pkg.yml b/sys/reboot/pkg.yml
index a34d45c..c2c2bf7 100644
--- a/sys/reboot/pkg.yml
+++ b/sys/reboot/pkg.yml
@@ -30,6 +30,7 @@ pkg.deps:
- libs/util
- sys/log
- libs/imgmgr
+ - sys/config
pkg.deps.REBOOT_LOG_FCB:
- sys/fcb
pkg.req_apis: