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Posted to commits@nuttx.apache.org by "hujun260 (via GitHub)" <gi...@apache.org> on 2024/09/16 06:09:05 UTC
[PR] Accelerate access to interrupt status [nuttx]
hujun260 opened a new pull request, #13486:
URL: https://github.com/apache/nuttx/pull/13486
## Summary
using percpu storage for g_current_regs or leveraging interrupt status
registers to determine if code is running within an interrupt context can enhance performance.
## Impact
none
## Testing
ostest
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Re: [PR] Accelerate access to interrupt status [nuttx]
Posted by "anchao (via GitHub)" <gi...@apache.org>.
anchao commented on code in PR #13486:
URL: https://github.com/apache/nuttx/pull/13486#discussion_r1764728402
##########
arch/arm/include/armv7-a/irq.h:
##########
@@ -490,13 +484,36 @@ static inline_function uint32_t up_getsp(void)
return sp;
}
-#endif /* __ASSEMBLY__ */
+static inline_function uint32_t *up_current_regs(void)
+{
+ uint32_t *regs;
+ __asm__ __volatile__
+ (
+ "mrc " "p15, " "0" ", %0, " "c13" ", " "c0" ", " "4" "\n"
Review Comment:
let us move cp15.h to arch public, same level as armv*/
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Re: [PR] Accelerate access to interrupt status [nuttx]
Posted by "anchao (via GitHub)" <gi...@apache.org>.
anchao commented on PR #13486:
URL: https://github.com/apache/nuttx/pull/13486#issuecomment-2357410844
> The current implementation need at least 3 executions of msr/mrs instructions plus 4 normal instructions, making this optimization evident. After optimization, only a single mrs instruction is needed, with no additional overhead.
Have you checked the assembly code? The previous implementation only reads the Affinity ID through MRC (1 cycle) and does not call MCR. Now your implementation uses MCR instruction to save the current regs with higher overhead than before.
>Unfortunately, we haven't conducted tests specifically for this single optimization point alone.
Instead, we've tested the entire message sending/receiving process, and each test incorporates multiple optimization points.
Could you provide performance diagram before and after adding this commit? Or API level test? Why you conclude that the performance is better than before without any test?
My concern is that MCR may perform worse than it currently does, but I'm not sure, could you help confirm this?
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Re: [PR] Accelerate access to interrupt status [nuttx]
Posted by "yf13 (via GitHub)" <gi...@apache.org>.
yf13 commented on PR #13486:
URL: https://github.com/apache/nuttx/pull/13486#issuecomment-2354210862
@hujun260, Can you enrich the `testing` section of PR description with checked targets (with configs) and observed performance changes?
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Re: [PR] Accelerate access to interrupt status [nuttx]
Posted by "xiaoxiang781216 (via GitHub)" <gi...@apache.org>.
xiaoxiang781216 commented on code in PR #13486:
URL: https://github.com/apache/nuttx/pull/13486#discussion_r1762232235
##########
arch/arm64/src/common/arm64_arch.h:
##########
@@ -466,7 +465,7 @@ static inline int arch_get_exception_depth(void)
static inline uint64_t arch_get_current_tcb(void)
{
- return read_sysreg(tpidr_el1);
+ return read_sysreg(tpidr_el0);
Review Comment:
@pussuw kernel space use tpidr_el1 here:
https://github.com/apache/nuttx/pull/13486/files#diff-a696b8576fe26629d886f8b4d2d3224143dc83018435ec1787300b2ba9fa6b73R404
tpidr_el0 will be used as userspace tls later.
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Re: [PR] Accelerate access to interrupt status [nuttx]
Posted by "xiaoxiang781216 (via GitHub)" <gi...@apache.org>.
xiaoxiang781216 commented on code in PR #13486:
URL: https://github.com/apache/nuttx/pull/13486#discussion_r1762905897
##########
arch/arm64/src/common/arm64_arch.h:
##########
@@ -466,7 +465,7 @@ static inline int arch_get_exception_depth(void)
static inline uint64_t arch_get_current_tcb(void)
{
- return read_sysreg(tpidr_el1);
+ return read_sysreg(tpidr_el0);
Review Comment:
@hujun260 it's better to remove arch_get_current_tcb in this patch and bring back later when we really use it.
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Re: [PR] Accelerate access to interrupt status [nuttx]
Posted by "anchao (via GitHub)" <gi...@apache.org>.
anchao commented on code in PR #13486:
URL: https://github.com/apache/nuttx/pull/13486#discussion_r1764354675
##########
arch/arm/include/armv7-a/irq.h:
##########
@@ -490,13 +484,36 @@ static inline_function uint32_t up_getsp(void)
return sp;
}
-#endif /* __ASSEMBLY__ */
+static inline_function uint32_t *up_current_regs(void)
+{
+ uint32_t *regs;
+ __asm__ __volatile__
+ (
+ "mrc " "p15, " "0" ", %0, " "c13" ", " "c0" ", " "4" "\n"
Review Comment:
CP15_TPIDRPRW
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Re: [PR] Accelerate access to interrupt status [nuttx]
Posted by "xiaoxiang781216 (via GitHub)" <gi...@apache.org>.
xiaoxiang781216 commented on code in PR #13486:
URL: https://github.com/apache/nuttx/pull/13486#discussion_r1761682683
##########
arch/arm/include/tlsr82/irq.h:
##########
@@ -294,6 +294,22 @@ static inline_function void up_set_current_regs(uint32_t *regs)
g_current_regs[up_cpu_index()] = regs;
}
+noinstrument_function
+static inline_function bool up_interrupt_context(void)
+{
+#ifdef CONFIG_SMP
Review Comment:
change to `return up_current_regs() != NULL;`
##########
arch/arm/include/armv8-m/irq.h:
##########
@@ -567,6 +567,21 @@ static inline_function void up_set_current_regs(uint32_t *regs)
g_current_regs[up_cpu_index()] = regs;
}
+noinstrument_function
+static inline_function bool up_interrupt_context(void)
+{
+#ifdef CONFIG_SMP
+ irqstate_t flags = up_irq_save();
+#endif
Review Comment:
call up_current_regs
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Re: [PR] Accelerate access to interrupt status [nuttx]
Posted by "pussuw (via GitHub)" <gi...@apache.org>.
pussuw commented on code in PR #13486:
URL: https://github.com/apache/nuttx/pull/13486#discussion_r1762545393
##########
arch/arm64/src/common/arm64_arch.h:
##########
@@ -466,7 +465,7 @@ static inline int arch_get_exception_depth(void)
static inline uint64_t arch_get_current_tcb(void)
{
- return read_sysreg(tpidr_el1);
+ return read_sysreg(tpidr_el0);
Review Comment:
Ok, will you handle arch_get_current_tcb differently then? Using tpidr_el0 inside the kernel is dangerous as tpidr_el0 is in fact writable from el0 / user-space
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Re: [PR] Accelerate access to interrupt status [nuttx]
Posted by "xiaoxiang781216 (via GitHub)" <gi...@apache.org>.
xiaoxiang781216 commented on code in PR #13486:
URL: https://github.com/apache/nuttx/pull/13486#discussion_r1762232235
##########
arch/arm64/src/common/arm64_arch.h:
##########
@@ -466,7 +465,7 @@ static inline int arch_get_exception_depth(void)
static inline uint64_t arch_get_current_tcb(void)
{
- return read_sysreg(tpidr_el1);
+ return read_sysreg(tpidr_el0);
Review Comment:
kernel space use tpidr_el1 here:
https://github.com/apache/nuttx/pull/13486/files#diff-a696b8576fe26629d886f8b4d2d3224143dc83018435ec1787300b2ba9fa6b73R404
tpidr_el0 will be used as userspace tls later.
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Re: [PR] Accelerate access to interrupt status [nuttx]
Posted by "hujun260 (via GitHub)" <gi...@apache.org>.
hujun260 commented on PR #13486:
URL: https://github.com/apache/nuttx/pull/13486#issuecomment-2357299404
> @hujun260, Can you enrich the `testing` section of PR description with checked targets (with configs) and observed performance changes?
The benefits are very significant.
Before the modification, if we needed to obtain the interrupt status, it required three steps:
1 Obtain the CPU index
2 Access the global variable
4 Disable/Enable interrupts
This process involved at least 6 CPU instructions.
However, now it only requires a single CPU instruction.
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Re: [PR] Accelerate access to interrupt status [nuttx]
Posted by "hujun260 (via GitHub)" <gi...@apache.org>.
hujun260 commented on code in PR #13486:
URL: https://github.com/apache/nuttx/pull/13486#discussion_r1764704054
##########
arch/arm/include/armv7-a/irq.h:
##########
@@ -490,13 +484,36 @@ static inline_function uint32_t up_getsp(void)
return sp;
}
-#endif /* __ASSEMBLY__ */
+static inline_function uint32_t *up_current_regs(void)
+{
+ uint32_t *regs;
+ __asm__ __volatile__
+ (
+ "mrc " "p15, " "0" ", %0, " "c13" ", " "c0" ", " "4" "\n"
Review Comment:
cp15.h is internal head file
we can't include cp15.h into irq.h
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Re: [PR] Accelerate access to interrupt status [nuttx]
Posted by "xiaoxiang781216 (via GitHub)" <gi...@apache.org>.
xiaoxiang781216 commented on code in PR #13486:
URL: https://github.com/apache/nuttx/pull/13486#discussion_r1764777263
##########
arch/arm/include/armv7-a/irq.h:
##########
@@ -490,13 +484,36 @@ static inline_function uint32_t up_getsp(void)
return sp;
}
-#endif /* __ASSEMBLY__ */
+static inline_function uint32_t *up_current_regs(void)
+{
+ uint32_t *regs;
+ __asm__ __volatile__
+ (
+ "mrc " "p15, " "0" ", %0, " "c13" ", " "c0" ", " "4" "\n"
Review Comment:
let's add a comment
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Re: [PR] Accelerate access to interrupt status [nuttx]
Posted by "pussuw (via GitHub)" <gi...@apache.org>.
pussuw commented on code in PR #13486:
URL: https://github.com/apache/nuttx/pull/13486#discussion_r1761760405
##########
arch/arm64/src/common/arm64_arch.h:
##########
@@ -466,7 +465,7 @@ static inline int arch_get_exception_depth(void)
static inline uint64_t arch_get_current_tcb(void)
{
- return read_sysreg(tpidr_el1);
+ return read_sysreg(tpidr_el0);
Review Comment:
You cannot rely on this as the user has access to tpidr_el0 and can corrupt the contents at any point. This can be considered a security risk as well.
Edit: I did not verify if el0 has _write_ access to tpidr_el0, but it has read access. It is typically used to hold thread local storage.
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Re: [PR] Accelerate access to interrupt status [nuttx]
Posted by "hujun260 (via GitHub)" <gi...@apache.org>.
hujun260 commented on PR #13486:
URL: https://github.com/apache/nuttx/pull/13486#issuecomment-2357375331
> > The benefits are very significant. Before the modification, if we needed to obtain the interrupt status, it required three steps:
> > 1 Obtain the CPU index 2 Access the global variable 4 Disable/Enable interrupts This process involved at least 6 CPU instructions.
> > However, now it only requires a single CPU instruction.
>
> 1. The switch irq enable/disable in `up_interrupt_context()` could be removed actually, as 32-bit is atomic type on arm32 CPU core
> 2. The instructions cycle timings of MCR may bring more overhead, requiring **6 cycles in the worst case**
>
> 
>
> https://developer.arm.com/documentation/100026/0104/smr1465219161191
>
> Do we have relevant performance test? For example, how many cycles does it take to call up_set_current_regs()/up_current_regs() 10,000 times with/out this PR?
Firstly, irq masking cannot be removed here due to the crucial reason that we must ensure no scheduling occurs for the current task
after the cpuindex is acquired. Otherwise, the cpuindex will not correspond to the CPU where the current task resides, leading to logical errors.
The implementation of this_task follows a similar principle.
The current implementation need at least 3 executions of msr/mrs instructions plus 4 normal instructions, making this optimization evident. After optimization, only a single msr instruction is needed, with no additional overhead.
Unfortunately, we haven't conducted tests specifically for this single optimization point alone.
Instead, we've tested the entire message sending/receiving process, and each test incorporates multiple optimization points.
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Re: [PR] Accelerate access to interrupt status [nuttx]
Posted by "anchao (via GitHub)" <gi...@apache.org>.
anchao merged PR #13486:
URL: https://github.com/apache/nuttx/pull/13486
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Re: [PR] Accelerate access to interrupt status [nuttx]
Posted by "anchao (via GitHub)" <gi...@apache.org>.
anchao commented on PR #13486:
URL: https://github.com/apache/nuttx/pull/13486#issuecomment-2357416138
> Firstly, irq masking cannot be removed here due to the crucial reason that we must ensure no scheduling occurs for the current task after the cpuindex is acquired. Otherwise, the cpuindex will not correspond to the CPU where the current task resides, leading to logical errors. The implementation of this_task follows a similar principle.
Yes, you are right, I forgot SMP mode, which does require disabling interrupts. I am currently using AMP/BMP mode, the performance is much higher than SMP
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Re: [PR] Accelerate access to interrupt status [nuttx]
Posted by "xiaoxiang781216 (via GitHub)" <gi...@apache.org>.
xiaoxiang781216 commented on code in PR #13486:
URL: https://github.com/apache/nuttx/pull/13486#discussion_r1764766955
##########
arch/arm/include/armv7-a/irq.h:
##########
@@ -490,13 +484,36 @@ static inline_function uint32_t up_getsp(void)
return sp;
}
-#endif /* __ASSEMBLY__ */
+static inline_function uint32_t *up_current_regs(void)
+{
+ uint32_t *regs;
+ __asm__ __volatile__
+ (
+ "mrc " "p15, " "0" ", %0, " "c13" ", " "c0" ", " "4" "\n"
Review Comment:
but cp15 is only useable for R and A profile, it isn't good to bring the whole file to public folder.
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Re: [PR] Accelerate access to interrupt status [nuttx]
Posted by "hujun260 (via GitHub)" <gi...@apache.org>.
hujun260 commented on PR #13486:
URL: https://github.com/apache/nuttx/pull/13486#issuecomment-2357926857
> > The current implementation need at least 3 executions of msr/mrs instructions plus 4 normal instructions, making this optimization evident. After optimization, only a single mrs instruction is needed, with no additional overhead.
>
> Have you checked the assembly code? The previous implementation only reads the Affinity ID through MRC (1 cycle) and does not call MCR. Now your implementation uses MCR instruction to save the current regs with higher overhead than before.
>
> > Unfortunately, we haven't conducted tests specifically for this single optimization point alone.
> > Instead, we've tested the entire message sending/receiving process, and each test incorporates multiple optimization points.
>
> Could you provide performance diagram before and after adding this commit? Or API level test? Why you conclude that the performance is better than before without any test?
>
> My concern is that MCR may perform worse than it currently does, but I'm not sure, could you help confirm this?
I did a test, 200 million cycles
before:
up_current_regs + irq enable/disable
2884 ms
up_set_current_regs
1358 ms
------------------------------------------
after:
up_current_regs + irq enable/disable
1017 ms
up_set_current_regs
339 ms
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Re: [PR] Accelerate access to interrupt status [nuttx]
Posted by "anchao (via GitHub)" <gi...@apache.org>.
anchao commented on code in PR #13486:
URL: https://github.com/apache/nuttx/pull/13486#discussion_r1764344179
##########
arch/arm/include/armv6-m/irq.h:
##########
@@ -366,17 +379,26 @@ static inline_function uint32_t up_getsp(void)
return sp;
}
-#endif /* __ASSEMBLY__ */
+static inline_function uint32_t *up_current_regs(void)
+{
+ return (uint32_t *)g_current_regs[up_cpu_index()];
+}
-/****************************************************************************
- * Public Data
- ****************************************************************************/
+static inline_function void up_set_current_regs(uint32_t *regs)
Review Comment:
```suggestion
noinstrument_function
static inline_function void up_set_current_regs(uint32_t *regs)
```
##########
arch/arm/include/armv7-a/irq.h:
##########
@@ -490,13 +484,36 @@ static inline_function uint32_t up_getsp(void)
return sp;
}
-#endif /* __ASSEMBLY__ */
+static inline_function uint32_t *up_current_regs(void)
Review Comment:
```suggestion
noinstrument_function
static inline_function uint32_t *up_current_regs(void)
```
##########
arch/arm/include/armv6-m/irq.h:
##########
@@ -366,17 +379,26 @@ static inline_function uint32_t up_getsp(void)
return sp;
}
-#endif /* __ASSEMBLY__ */
+static inline_function uint32_t *up_current_regs(void)
Review Comment:
```suggestion
noinstrument_function
static inline_function uint32_t *up_current_regs(void)
```
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Re: [PR] Accelerate access to interrupt status [nuttx]
Posted by "hujun260 (via GitHub)" <gi...@apache.org>.
hujun260 commented on code in PR #13486:
URL: https://github.com/apache/nuttx/pull/13486#discussion_r1764262619
##########
arch/arm64/src/common/arm64_arch.h:
##########
@@ -466,7 +465,7 @@ static inline int arch_get_exception_depth(void)
static inline uint64_t arch_get_current_tcb(void)
{
- return read_sysreg(tpidr_el1);
+ return read_sysreg(tpidr_el0);
Review Comment:
ok
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Re: [PR] Accelerate access to interrupt status [nuttx]
Posted by "anchao (via GitHub)" <gi...@apache.org>.
anchao commented on PR #13486:
URL: https://github.com/apache/nuttx/pull/13486#issuecomment-2357343295
> The benefits are very significant. Before the modification, if we needed to obtain the interrupt status, it required three steps:
>
> 1 Obtain the CPU index 2 Access the global variable 4 Disable/Enable interrupts This process involved at least 6 CPU instructions.
>
> However, now it only requires a single CPU instruction.
1. The switch interrupt in `up_interrupt_context()` could be deleted actually, as 32-bit is atomic type on arm32 CPU core
2. The instructions cycle timings of MCR may bring more overhead, requiring **6 cycles in the worst case**
https://developer.arm.com/documentation/100026/0104/smr1465219161191
Do we have relevant performance test? For example, how many cycles does it take to call up_set_current_regs()/up_current_regs() 10,000 times with/out this PR?
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Re: [PR] Accelerate access to interrupt status [nuttx]
Posted by "pussuw (via GitHub)" <gi...@apache.org>.
pussuw commented on code in PR #13486:
URL: https://github.com/apache/nuttx/pull/13486#discussion_r1761760405
##########
arch/arm64/src/common/arm64_arch.h:
##########
@@ -466,7 +465,7 @@ static inline int arch_get_exception_depth(void)
static inline uint64_t arch_get_current_tcb(void)
{
- return read_sysreg(tpidr_el1);
+ return read_sysreg(tpidr_el0);
Review Comment:
You cannot rely on this as the user has access to tpidr_el0 and can corrupt the contents at any point. This can be considered a security risk as well.
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Re: [PR] Accelerate access to interrupt status [nuttx]
Posted by "pussuw (via GitHub)" <gi...@apache.org>.
pussuw commented on code in PR #13486:
URL: https://github.com/apache/nuttx/pull/13486#discussion_r1761760405
##########
arch/arm64/src/common/arm64_arch.h:
##########
@@ -466,7 +465,7 @@ static inline int arch_get_exception_depth(void)
static inline uint64_t arch_get_current_tcb(void)
{
- return read_sysreg(tpidr_el1);
+ return read_sysreg(tpidr_el0);
Review Comment:
You cannot rely on this as the user has access to tpidr_el0 and can corrupt the contents at any point. This can be considered a security risk as well.
Edit: I did not verify if el0 has _write_ access to el0, but it has read access. It is typically used to hold thread local storage.
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