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Posted to commits@mynewt.apache.org by an...@apache.org on 2018/11/23 16:16:38 UTC
[mynewt-core] 06/26: hw/bus: Add SPI bus driver
This is an automated email from the ASF dual-hosted git repository.
andk pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit b1366267ddc917c26b3f763ea386adf44425a9f8
Author: Andrzej Kaczmarek <an...@codecoup.pl>
AuthorDate: Thu Nov 8 16:01:50 2018 +0100
hw/bus: Add SPI bus driver
---
hw/bus/spi/include/bus/spi.h | 116 ++++++++++++++++++++++
hw/bus/spi/pkg.yml | 28 ++++++
hw/bus/spi/src/spi.c | 224 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 368 insertions(+)
diff --git a/hw/bus/spi/include/bus/spi.h b/hw/bus/spi/include/bus/spi.h
new file mode 100644
index 0000000..e2a332c
--- /dev/null
+++ b/hw/bus/spi/include/bus/spi.h
@@ -0,0 +1,116 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef HW_BUS_SPI_H_
+#define HW_BUS_SPI_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include "bus/bus.h"
+#include "bus/bus_driver.h"
+#include "bus/bus_debug.h"
+#include "hal/hal_spi.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct bus_spi_dev_cfg {
+ int spi_num;
+ int pin_sck;
+ int pin_mosi;
+ int pin_miso;
+};
+
+struct bus_spi_dev {
+ struct bus_dev bdev;
+ struct bus_spi_dev_cfg cfg;
+
+#if MYNEWT_VAL(BUS_DEBUG)
+ uint32_t devmagic;
+#endif
+};
+
+#define BUS_SPI_MODE_0 (HAL_SPI_MODE0)
+#define BUS_SPI_MODE_1 (HAL_SPI_MODE1)
+#define BUS_SPI_MODE_2 (HAL_SPI_MODE2)
+#define BUS_SPI_MODE_3 (HAL_SPI_MODE3)
+
+#define BUS_SPI_DATA_ORDER_LSB (HAL_SPI_LSB_FIRST)
+#define BUS_SPI_DATA_ORDER_MSB (HAL_SPI_MSB_FIRST)
+
+struct bus_spi_node_cfg {
+ /** General node configuration */
+ struct bus_node_cfg node_cfg;
+ /** */
+ uint8_t pin_cs;
+ /** Data mode */
+ uint8_t mode;
+ /** Data order */
+ uint8_t data_order;
+ /** SCK frequency to be used for node */
+ uint16_t freq;
+ /** Quirks to be applied for device */
+ uint16_t quirks;
+};
+
+struct bus_spi_node {
+ struct bus_node bnode;
+ uint8_t pin_cs;
+ uint8_t mode;
+ uint8_t data_order;
+ uint16_t freq;
+ uint16_t quirks;
+
+#if MYNEWT_VAL(BUS_DEBUG)
+ uint32_t nodemagic;
+#endif
+};
+
+int
+bus_spi_dev_init_func(struct os_dev *odev, void *arg);
+
+static inline int
+bus_spi_dev_create(const char *name, struct bus_spi_dev *dev,
+ struct bus_spi_dev_cfg *cfg)
+{
+ struct os_dev *odev = (struct os_dev *)dev;
+
+ return os_dev_create(odev, name, OS_DEV_INIT_PRIMARY, 0,
+ bus_spi_dev_init_func, cfg);
+}
+
+int
+bus_spi_node_init_func(struct os_dev *odev, void *arg);
+
+static inline int
+bus_spi_node_create(const char *name, struct bus_spi_node *node,
+ const struct bus_spi_node_cfg *cfg)
+{
+ struct os_dev *odev = (struct os_dev *)node;
+
+ return os_dev_create(odev, name, OS_DEV_INIT_PRIMARY, 1,
+ bus_spi_node_init_func, (void *)cfg);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HW_BUS_SPI_H_ */
diff --git a/hw/bus/spi/pkg.yml b/hw/bus/spi/pkg.yml
new file mode 100644
index 0000000..9c82432
--- /dev/null
+++ b/hw/bus/spi/pkg.yml
@@ -0,0 +1,28 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: hw/bus/spi
+pkg.description: SPI bus implementation
+pkg.author: "Apache Mynewt <de...@mynewt.apache.org>"
+pkg.homepage: "http://mynewt.apache.org/"
+pkg.keywords:
+pkg.deps:
+
+pkg.deps:
+ - "@apache-mynewt-core/hw/bus"
diff --git a/hw/bus/spi/src/spi.c b/hw/bus/spi/src/spi.c
new file mode 100644
index 0000000..7aca7c4
--- /dev/null
+++ b/hw/bus/spi/src/spi.c
@@ -0,0 +1,224 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include "defs/error.h"
+#include "hal/hal_gpio.h"
+#include "hal/hal_spi.h"
+#include "bus/bus.h"
+#include "bus/bus_debug.h"
+#include "bus/spi.h"
+
+static int
+bus_spi_enable(struct bus_dev *bdev)
+{
+ struct bus_spi_dev *dev = (struct bus_spi_dev *)bdev;
+ int rc;
+
+ BUS_DEBUG_VERIFY_DEV(dev);
+
+ rc = hal_spi_enable(dev->cfg.spi_num);
+ if (rc) {
+ return SYS_EINVAL;
+ }
+
+ return 0;
+}
+
+static int
+bus_spi_configure(struct bus_dev *bdev, struct bus_node *bnode)
+{
+ struct bus_spi_dev *dev = (struct bus_spi_dev *)bdev;
+ struct bus_spi_node *node = (struct bus_spi_node *)bnode;
+ struct bus_spi_node *current_node = (struct bus_spi_node *)bdev->configured_for;
+ struct hal_spi_settings spi_cfg;
+ int rc;
+
+ BUS_DEBUG_VERIFY_DEV(dev);
+ BUS_DEBUG_VERIFY_NODE(node);
+
+ /* No need to reconfigure if already configured with the same settings */
+ if (current_node && (current_node->mode == node->mode) &&
+ (current_node->data_order == node->data_order) &&
+ (current_node->freq == node->freq)) {
+ return 0;
+ }
+
+ rc = hal_spi_disable(dev->cfg.spi_num);
+ if (rc) {
+ goto done;
+ }
+
+ spi_cfg.data_mode = node->mode;
+ spi_cfg.data_order = node->data_order;
+ spi_cfg.baudrate = node->freq;
+ /* XXX add support for other word sizes */
+ spi_cfg.word_size = HAL_SPI_WORD_SIZE_8BIT;
+
+ rc = hal_spi_config(dev->cfg.spi_num, &spi_cfg);
+ if (rc) {
+ goto done;
+ }
+
+ rc = hal_spi_enable(dev->cfg.spi_num);
+
+done:
+ if (rc) {
+ rc = SYS_EIO;
+ }
+
+ return rc;
+}
+
+static int
+bus_spi_read(struct bus_dev *bdev, struct bus_node *bnode, uint8_t *buf,
+ uint16_t length, os_time_t timeout, uint16_t flags)
+{
+ struct bus_spi_dev *dev = (struct bus_spi_dev *)bdev;
+ struct bus_spi_node *node = (struct bus_spi_node *)bnode;
+ uint8_t val;
+ int i;
+ int rc;
+
+ BUS_DEBUG_VERIFY_DEV(dev);
+ BUS_DEBUG_VERIFY_NODE(node);
+
+ rc = 0;
+
+ hal_gpio_write(node->pin_cs, 0);
+
+ for (i = 0; i < length; i++) {
+ val = hal_spi_tx_val(dev->cfg.spi_num, 0xAA);
+ if (val == 0xFFFF) {
+ rc = SYS_EINVAL;
+ break;
+ }
+
+ buf[i] = val;
+ }
+
+ if (rc || !(flags & BUS_F_NOSTOP)) {
+ hal_gpio_write(node->pin_cs, 1);
+ }
+
+ return rc;
+}
+
+static int
+bus_spi_write(struct bus_dev *bdev, struct bus_node *bnode, uint8_t *buf,
+ uint16_t length, os_time_t timeout, uint16_t flags)
+{
+ struct bus_spi_dev *dev = (struct bus_spi_dev *)bdev;
+ struct bus_spi_node *node = (struct bus_spi_node *)bnode;
+ int rc;
+
+ BUS_DEBUG_VERIFY_DEV(dev);
+ BUS_DEBUG_VERIFY_NODE(node);
+
+ hal_gpio_write(node->pin_cs, 0);
+
+ rc = hal_spi_txrx(dev->cfg.spi_num, buf, NULL, length);
+
+ if (!(flags & BUS_F_NOSTOP)) {
+ hal_gpio_write(node->pin_cs, 1);
+ }
+
+ return rc;
+}
+
+static int bus_spi_disable(struct bus_dev *bdev)
+{
+ struct bus_spi_dev *dev = (struct bus_spi_dev *)bdev;
+ int rc;
+
+ BUS_DEBUG_VERIFY_DEV(dev);
+
+ rc = hal_spi_disable(dev->cfg.spi_num);
+ if (rc) {
+ return SYS_EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct bus_dev_ops bus_spi_ops = {
+ .enable = bus_spi_enable,
+ .configure = bus_spi_configure,
+ .read = bus_spi_read,
+ .write = bus_spi_write,
+ .disable = bus_spi_disable,
+};
+
+int
+bus_spi_dev_init_func(struct os_dev *odev, void *arg)
+{
+ struct bus_spi_dev *dev = (struct bus_spi_dev *)odev;
+ struct bus_spi_dev_cfg *cfg = arg;
+ struct hal_spi_hw_settings hal_cfg;
+ int rc;
+
+ hal_cfg.pin_sck = cfg->pin_sck;
+ hal_cfg.pin_mosi = cfg->pin_mosi;
+ hal_cfg.pin_miso = cfg->pin_miso;
+ hal_cfg.pin_ss = 0;
+
+ /* XXX we support master only! */
+ rc = hal_spi_init_hw(cfg->spi_num, HAL_SPI_TYPE_MASTER, &hal_cfg);
+ if (rc) {
+ return SYS_EINVAL;
+ }
+
+ rc = bus_dev_init_func(odev, (void*)&bus_spi_ops);
+ assert(rc == 0);
+
+ BUS_DEBUG_POISON_DEV(dev);
+
+ dev->cfg = *cfg;
+
+ rc = hal_spi_enable(dev->cfg.spi_num);
+ assert(rc == 0);
+
+ return 0;
+}
+
+int
+bus_spi_node_init_func(struct os_dev *odev, void *arg)
+{
+ struct bus_spi_node *node = (struct bus_spi_node *)odev;
+ struct bus_spi_node_cfg *cfg = arg;
+ struct bus_node_cfg *node_cfg = &cfg->node_cfg;
+ int rc;
+
+ rc = bus_node_init_func(odev, node_cfg);
+ if (rc) {
+ return rc;
+ }
+
+ BUS_DEBUG_POISON_NODE(node);
+
+ node->pin_cs = cfg->pin_cs;
+ node->mode = cfg->mode;
+ node->data_order = cfg->data_order;
+ node->freq = cfg->freq;
+ node->quirks = cfg->quirks;
+
+ hal_gpio_init_out(node->pin_cs, 1);
+
+ return 0;
+}