[GitHub] [incubator-nuttx] Ouss4 commented on issue #1274: RISC-V: Using MIPS configuration in multiple functions

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Ouss4 commented on issue #1274:
URL: https://github.com/apache/incubator-nuttx/issues/1274#issuecomment-646968363


   I'm glad you created this.  I noticed the issue before and fixed a few that were on my way but apparently there are more.
   One more thing is in the following lines of the RISC-V up_idle function:
   https://github.com/apache/incubator-nuttx/blob/b64060f717866c77338a032be4287b5ee097835d/arch/risc-v/src/common/riscv_idle.c#L77-L89
   
   That comment and "kludge" was also taken from the MIPS port.  The problem in the MIPS port was in a bad interrupt configuration which is now fixed.  Could you (or anyone using RISC-V) verify that there is no need for that kludge?
   
   Similarly for `xtensa_idle.c` `lm32_idle.c` and `minerva_idle.c`.
   I can take a look at the xtensa one. (Maybe after we cut RC0 :) )


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