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Posted to commits@harmony.apache.org by "Ivashin Sergey (JIRA)" <ji...@apache.org> on 2006/12/15 14:44:22 UTC
[jira] Updated: (HARMONY-2747) [drlvm][jit] Jitrino SpillGen
improvements
[ http://issues.apache.org/jira/browse/HARMONY-2747?page=all ]
Ivashin Sergey updated HARMONY-2747:
------------------------------------
Attachment: H-2747.patch
> [drlvm][jit] Jitrino SpillGen improvements
> ------------------------------------------
>
> Key: HARMONY-2747
> URL: http://issues.apache.org/jira/browse/HARMONY-2747
> Project: Harmony
> Issue Type: Improvement
> Components: DRLVM
> Reporter: Ivashin Sergey
> Attachments: H-2747.patch
>
>
> In general, SpillGen cannot assign registers for all operands that require it. For all known tests and benchmarks SpillGen assign registers successfully, but it is possible to generate a control flow graph on which Spillgen will fail, i.e. will not assign register for instruction which requires it. In fact, such programs are often generated by experimental versions of IA32 codegen stages.
> The proposed patch significantly reduces chances of SpillGen failures. It was tested and used in experiments with IA32 codegen. Currently it is impossible to create a test for this patch or demonstrate its effect.
> The patch also contains some code cleanup (dead code removed).
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