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Posted to commits@nuttx.apache.org by ac...@apache.org on 2026/10/16 12:22:19 UTC
(nuttx) 03/03: arch/arm/stm32: Move the GPDMA driver to common
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 41aedbe38a1bbb78ad29ba252fff77baf427af55
Author: raiden00pl <ra...@railab.me>
AuthorDate: Wed Aug 26 12:46:38 2026 +0200
arch/arm/stm32: Move the GPDMA driver to common
Move the STM32H5 GPDMA driver, its interface header, and the GPDMA
register map into common/stm32, built for STM32_HAVE_IP_DMA_GPDMA
families when STM32_DMA is enabled.
Generate the channel table from STM32_DMAx_NCHAN and
STM32_DMAx_IRQ_FIRST provided by the family chip.h, and take the DMA
request signal map from the family hardware/stm32_dmasigmap.h.
Signed-off-by: raiden00pl <ra...@railab.me>
Assisted-by: Claude Code
---
arch/arm/src/common/stm32/CMakeLists.txt | 4 +
arch/arm/src/common/stm32/Make.defs | 4 +
.../stm32}/hardware/stm32_gpdma.h | 17 ++-
.../stm32_dma.c => common/stm32/stm32_dma_gpdma.c} | 129 +++++++++++++++++----
.../{stm32h5 => common/stm32}/stm32_dma_gpdma.h | 10 +-
arch/arm/src/common/stm32/stm32_serial_m33_v3.c | 4 +
arch/arm/src/stm32h5/CMakeLists.txt | 4 -
arch/arm/src/stm32h5/Make.defs | 4 -
arch/arm/src/stm32h5/chip.h | 7 ++
.../stm32h5/{chip.h => hardware/stm32_dmasigmap.h} | 42 ++-----
10 files changed, 146 insertions(+), 79 deletions(-)
diff --git a/arch/arm/src/common/stm32/CMakeLists.txt b/arch/arm/src/common/stm32/CMakeLists.txt
index 758928452c3..356807f6f96 100644
--- a/arch/arm/src/common/stm32/CMakeLists.txt
+++ b/arch/arm/src/common/stm32/CMakeLists.txt
@@ -48,6 +48,10 @@ if(CONFIG_STM32_HAVE_IP_GPIO_M33_V1)
list(APPEND SRCS stm32_gpio_m33_v1.c)
endif()
+if(CONFIG_STM32_HAVE_IP_DMA_GPDMA AND CONFIG_STM32_DMA)
+ list(APPEND SRCS stm32_dma_gpdma.c)
+endif()
+
if(CONFIG_STM32_HAVE_IP_EXTI_M33_V1)
list(APPEND SRCS stm32_exti_gpio_m33_v1.c)
endif()
diff --git a/arch/arm/src/common/stm32/Make.defs b/arch/arm/src/common/stm32/Make.defs
index 4e646e1ab6f..271212da7ba 100644
--- a/arch/arm/src/common/stm32/Make.defs
+++ b/arch/arm/src/common/stm32/Make.defs
@@ -59,6 +59,10 @@ ifeq ($(CONFIG_STM32_HAVE_IP_GPIO_M33_V1),y)
CHIP_CSRCS += stm32_gpio_m33_v1.c
endif
+ifeq ($(CONFIG_STM32_HAVE_IP_DMA_GPDMA)$(CONFIG_STM32_DMA),yy)
+CHIP_CSRCS += stm32_dma_gpdma.c
+endif
+
ifeq ($(CONFIG_STM32_HAVE_IP_EXTI_M33_V1),y)
CHIP_CSRCS += stm32_exti_gpio_m33_v1.c
endif
diff --git a/arch/arm/src/stm32h5/hardware/stm32_gpdma.h b/arch/arm/src/common/stm32/hardware/stm32_gpdma.h
similarity index 98%
rename from arch/arm/src/stm32h5/hardware/stm32_gpdma.h
rename to arch/arm/src/common/stm32/hardware/stm32_gpdma.h
index 52ce92f6f81..795a9462e63 100644
--- a/arch/arm/src/stm32h5/hardware/stm32_gpdma.h
+++ b/arch/arm/src/common/stm32/hardware/stm32_gpdma.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/stm32h5/hardware/stm32_gpdma.h
+ * arch/arm/src/common/stm32/hardware/stm32_gpdma.h
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -20,8 +20,8 @@
*
****************************************************************************/
-#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_GPDMA_H
-#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_GPDMA_H
+#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPDMA_H
+#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPDMA_H
/****************************************************************************
* Included Files
@@ -30,12 +30,9 @@
#include <nuttx/config.h>
#include "chip.h"
-#if defined(CONFIG_STM32_STM32H50XXX) || defined(CONFIG_STM32_STM32H53XXX) || \
- defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX)
-# include "stm32h56x_dmasigmap.h"
-#else
-# error "Unsupported STM32 H5 DMA map"
-#endif
+/* Each family provides its DMA request signal map */
+
+#include "hardware/stm32_dmasigmap.h"
/****************************************************************************
* Pre-processor Definitions
@@ -559,4 +556,4 @@
#define GPDMA_CXLLR_UT2 (1 << 30) /* Update CxTR2 register from memory */
#define GPDMA_CXLLR_UT1 (1 << 31) /* Update CxTR1 register from memory */
-#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_GPDMA_H */
\ No newline at end of file
+#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPDMA_H */
\ No newline at end of file
diff --git a/arch/arm/src/stm32h5/stm32_dma.c b/arch/arm/src/common/stm32/stm32_dma_gpdma.c
similarity index 90%
rename from arch/arm/src/stm32h5/stm32_dma.c
rename to arch/arm/src/common/stm32/stm32_dma_gpdma.c
index c9cb1d76036..f4512dfc032 100644
--- a/arch/arm/src/stm32h5/stm32_dma.c
+++ b/arch/arm/src/common/stm32/stm32_dma_gpdma.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/stm32h5/stm32_dma.c
+ * arch/arm/src/common/stm32/stm32_dma_gpdma.c
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -118,13 +118,15 @@ static int gpdma_dmainterrupt(int irq, void *context, void *arg);
* Private Data
****************************************************************************/
-/* One entry per implemented GPDMA channel */
+/* One entry per implemented GPDMA channel. Each family provides
+ * STM32_DMAx_NCHAN and STM32_DMAx_IRQ_FIRST for its instances.
+ */
-#define GPDMA_CHAN(inst, ch, irqno) \
+#define GPDMA_CHAN(inst, ch) \
{ \
.dma_instance = (inst), \
.channel = (ch), \
- .irq = (irqno), \
+ .irq = STM32_DMA##inst##_IRQ_FIRST + (ch), \
.free = true, \
.base = STM32_DMA##inst##_BASE + CH_BASE_OFFSET(ch) \
}
@@ -132,24 +134,104 @@ static int gpdma_dmainterrupt(int irq, void *context, void *arg);
static struct gpdma_ch_s g_chan[] =
{
#ifdef CONFIG_STM32_DMA1
- GPDMA_CHAN(1, 0, STM32_IRQ_GPDMA1_CH0),
- GPDMA_CHAN(1, 1, STM32_IRQ_GPDMA1_CH1),
- GPDMA_CHAN(1, 2, STM32_IRQ_GPDMA1_CH2),
- GPDMA_CHAN(1, 3, STM32_IRQ_GPDMA1_CH3),
- GPDMA_CHAN(1, 4, STM32_IRQ_GPDMA1_CH4),
- GPDMA_CHAN(1, 5, STM32_IRQ_GPDMA1_CH5),
- GPDMA_CHAN(1, 6, STM32_IRQ_GPDMA1_CH6),
- GPDMA_CHAN(1, 7, STM32_IRQ_GPDMA1_CH7),
+# if STM32_DMA1_NCHAN > 0
+ GPDMA_CHAN(1, 0),
+# endif
+# if STM32_DMA1_NCHAN > 1
+ GPDMA_CHAN(1, 1),
+# endif
+# if STM32_DMA1_NCHAN > 2
+ GPDMA_CHAN(1, 2),
+# endif
+# if STM32_DMA1_NCHAN > 3
+ GPDMA_CHAN(1, 3),
+# endif
+# if STM32_DMA1_NCHAN > 4
+ GPDMA_CHAN(1, 4),
+# endif
+# if STM32_DMA1_NCHAN > 5
+ GPDMA_CHAN(1, 5),
+# endif
+# if STM32_DMA1_NCHAN > 6
+ GPDMA_CHAN(1, 6),
+# endif
+# if STM32_DMA1_NCHAN > 7
+ GPDMA_CHAN(1, 7),
+# endif
+# if STM32_DMA1_NCHAN > 8
+ GPDMA_CHAN(1, 8),
+# endif
+# if STM32_DMA1_NCHAN > 9
+ GPDMA_CHAN(1, 9),
+# endif
+# if STM32_DMA1_NCHAN > 10
+ GPDMA_CHAN(1, 10),
+# endif
+# if STM32_DMA1_NCHAN > 11
+ GPDMA_CHAN(1, 11),
+# endif
+# if STM32_DMA1_NCHAN > 12
+ GPDMA_CHAN(1, 12),
+# endif
+# if STM32_DMA1_NCHAN > 13
+ GPDMA_CHAN(1, 13),
+# endif
+# if STM32_DMA1_NCHAN > 14
+ GPDMA_CHAN(1, 14),
+# endif
+# if STM32_DMA1_NCHAN > 15
+ GPDMA_CHAN(1, 15),
+# endif
#endif
#ifdef CONFIG_STM32_DMA2
- GPDMA_CHAN(2, 0, STM32_IRQ_GPDMA2_CH0),
- GPDMA_CHAN(2, 1, STM32_IRQ_GPDMA2_CH1),
- GPDMA_CHAN(2, 2, STM32_IRQ_GPDMA2_CH2),
- GPDMA_CHAN(2, 3, STM32_IRQ_GPDMA2_CH3),
- GPDMA_CHAN(2, 4, STM32_IRQ_GPDMA2_CH4),
- GPDMA_CHAN(2, 5, STM32_IRQ_GPDMA2_CH5),
- GPDMA_CHAN(2, 6, STM32_IRQ_GPDMA2_CH6),
- GPDMA_CHAN(2, 7, STM32_IRQ_GPDMA2_CH7),
+# if STM32_DMA2_NCHAN > 0
+ GPDMA_CHAN(2, 0),
+# endif
+# if STM32_DMA2_NCHAN > 1
+ GPDMA_CHAN(2, 1),
+# endif
+# if STM32_DMA2_NCHAN > 2
+ GPDMA_CHAN(2, 2),
+# endif
+# if STM32_DMA2_NCHAN > 3
+ GPDMA_CHAN(2, 3),
+# endif
+# if STM32_DMA2_NCHAN > 4
+ GPDMA_CHAN(2, 4),
+# endif
+# if STM32_DMA2_NCHAN > 5
+ GPDMA_CHAN(2, 5),
+# endif
+# if STM32_DMA2_NCHAN > 6
+ GPDMA_CHAN(2, 6),
+# endif
+# if STM32_DMA2_NCHAN > 7
+ GPDMA_CHAN(2, 7),
+# endif
+# if STM32_DMA2_NCHAN > 8
+ GPDMA_CHAN(2, 8),
+# endif
+# if STM32_DMA2_NCHAN > 9
+ GPDMA_CHAN(2, 9),
+# endif
+# if STM32_DMA2_NCHAN > 10
+ GPDMA_CHAN(2, 10),
+# endif
+# if STM32_DMA2_NCHAN > 11
+ GPDMA_CHAN(2, 11),
+# endif
+# if STM32_DMA2_NCHAN > 12
+ GPDMA_CHAN(2, 12),
+# endif
+# if STM32_DMA2_NCHAN > 13
+ GPDMA_CHAN(2, 13),
+# endif
+# if STM32_DMA2_NCHAN > 14
+ GPDMA_CHAN(2, 14),
+# endif
+# if STM32_DMA2_NCHAN > 15
+ GPDMA_CHAN(2, 15),
+# endif
#endif
};
@@ -429,8 +511,7 @@ void weak_function arm_dma_initialize(void)
DMA_HANDLE stm32_dmachannel(enum gpdma_ttype_e type)
{
- /* On the H5, peripherals can kind of be mapped to any number of different
- * channels.
+ /* Peripherals can be mapped to any number of different channels.
*
* P2M and M2P should be on channels with 8 byte FIFOs. GPDMA1/2 CH[0-3]
*
@@ -658,13 +739,13 @@ void stm32_dmastop(DMA_HANDLE handle)
*
* Description:
* Returns the number of data beats remaining to transfer in the current
- * STM32H5 GPDMA block. This reads the BNDT[15:0] field from the
+ * GPDMA block. This reads the BNDT[15:0] field from the
* GPDMA_CxBR1 register, which indicates how many beats are left in the
* programmed transfer.
*
* Assumptions:
* - DMA handle was allocated by stm32_dmachannel().
- * - The handle refers to a valid STM32H5 GPDMA channel.
+ * - The handle refers to a valid GPDMA channel.
*
****************************************************************************/
diff --git a/arch/arm/src/stm32h5/stm32_dma_gpdma.h b/arch/arm/src/common/stm32/stm32_dma_gpdma.h
similarity index 97%
rename from arch/arm/src/stm32h5/stm32_dma_gpdma.h
rename to arch/arm/src/common/stm32/stm32_dma_gpdma.h
index deff54995bb..0d6acde63ec 100644
--- a/arch/arm/src/stm32h5/stm32_dma_gpdma.h
+++ b/arch/arm/src/common/stm32/stm32_dma_gpdma.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/stm32h5/stm32_dma_gpdma.h
+ * arch/arm/src/common/stm32/stm32_dma_gpdma.h
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -20,8 +20,8 @@
*
****************************************************************************/
-#ifndef __ARCH_ARM_SRC_STM32H5_STM32_DMA_GPDMA_H
-#define __ARCH_ARM_SRC_STM32H5_STM32_DMA_GPDMA_H
+#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA_GPDMA_H
+#define __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA_GPDMA_H
/****************************************************************************
* Included Files
@@ -132,7 +132,7 @@ struct stm32_gpdma_cfg_s
/* request: Accepts GPDMA_CXTR2_SWREQ, GPDMA_CXTR2_DREQ, and
* GPDMA_CXTR2_REQSEL(r) for r given by GPDMA_REQ_x
- * macros defined in hardware/stm32h56x_dmasigmap.h
+ * macros defined in the family hardware/stm32_dmasigmap.h
*/
uint16_t request;
@@ -368,4 +368,4 @@ void stm32_dmadump(DMA_HANDLE handle, const char *msg);
#endif
#endif /* !__ASSEMBLY__*/
-#endif /* __ARCH_ARM_SRC_STM32H5_STM32_DMA_GPDMA_H*/
+#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA_GPDMA_H*/
diff --git a/arch/arm/src/common/stm32/stm32_serial_m33_v3.c b/arch/arm/src/common/stm32/stm32_serial_m33_v3.c
index 7aaa25ab7b6..c17b35a9d16 100644
--- a/arch/arm/src/common/stm32/stm32_serial_m33_v3.c
+++ b/arch/arm/src/common/stm32/stm32_serial_m33_v3.c
@@ -57,6 +57,10 @@
#include "stm32_rcc.h"
#include "arm_internal.h"
+#ifdef SERIAL_HAVE_DMA
+# include "stm32_dma.h"
+#endif
+
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
diff --git a/arch/arm/src/stm32h5/CMakeLists.txt b/arch/arm/src/stm32h5/CMakeLists.txt
index 096576b89f6..01cd1a86831 100644
--- a/arch/arm/src/stm32h5/CMakeLists.txt
+++ b/arch/arm/src/stm32h5/CMakeLists.txt
@@ -92,10 +92,6 @@ if(CONFIG_MDIO_BUS)
list(APPEND SRCS stm32_mdio.c)
endif()
-if(CONFIG_STM32_DMA)
- list(APPEND SRCS stm32_dma.c)
-endif()
-
if(CONFIG_STM32_DTS)
list(APPEND SRCS stm32_dts.c)
endif()
diff --git a/arch/arm/src/stm32h5/Make.defs b/arch/arm/src/stm32h5/Make.defs
index 6c8db51439f..d35f7c4fb7c 100644
--- a/arch/arm/src/stm32h5/Make.defs
+++ b/arch/arm/src/stm32h5/Make.defs
@@ -100,10 +100,6 @@ ifeq ($(CONFIG_MDIO_BUS),y)
CHIP_CSRCS += stm32_mdio.c
endif
-ifeq ($(CONFIG_STM32_DMA),y)
-CHIP_CSRCS += stm32_dma.c
-endif
-
ifeq ($(CONFIG_STM32_DTS),y)
CHIP_CSRCS += stm32_dts.c
endif
diff --git a/arch/arm/src/stm32h5/chip.h b/arch/arm/src/stm32h5/chip.h
index 7cdcc950e3d..099478bdb3d 100644
--- a/arch/arm/src/stm32h5/chip.h
+++ b/arch/arm/src/stm32h5/chip.h
@@ -50,6 +50,13 @@
#define ARMV8M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS
+/* GPDMA instance parameters */
+
+#define STM32_DMA1_NCHAN 8
+#define STM32_DMA1_IRQ_FIRST STM32_IRQ_GPDMA1_CH0
+#define STM32_DMA2_NCHAN 8
+#define STM32_DMA2_IRQ_FIRST STM32_IRQ_GPDMA2_CH0
+
/* Cache line sizes set in line with ST document RM0481 Rev 2.
* DCACHE implementation, pg 284, Table 93
* ICACHE implementation, pg 367, Table 85.
diff --git a/arch/arm/src/stm32h5/chip.h b/arch/arm/src/stm32h5/hardware/stm32_dmasigmap.h
similarity index 50%
copy from arch/arm/src/stm32h5/chip.h
copy to arch/arm/src/stm32h5/hardware/stm32_dmasigmap.h
index 7cdcc950e3d..af2f51cb0cb 100644
--- a/arch/arm/src/stm32h5/chip.h
+++ b/arch/arm/src/stm32h5/hardware/stm32_dmasigmap.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/stm32h5/chip.h
+ * arch/arm/src/stm32h5/hardware/stm32_dmasigmap.h
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -20,8 +20,8 @@
*
****************************************************************************/
-#ifndef __ARCH_ARM_SRC_STM32H5_CHIP_H
-#define __ARCH_ARM_SRC_STM32H5_CHIP_H
+#ifndef __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_DMASIGMAP_H
+#define __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_DMASIGMAP_H
/****************************************************************************
* Included Files
@@ -29,33 +29,11 @@
#include <nuttx/config.h>
-/* Include the memory map and the chip definitions file. Other chip hardware
- * files should then include this file for the proper setup.
- */
+#if defined(CONFIG_STM32_STM32H50XXX) || defined(CONFIG_STM32_STM32H53XXX) || \
+ defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32_STM32H57XXX)
+# include "hardware/stm32h56x_dmasigmap.h"
+#else
+# error "Unsupported STM32H5 DMA signal map"
+#endif
-#include <arch/irq.h>
-#include <arch/stm32h5/chip.h>
-#include "hardware/stm32_pinmap.h"
-#include "hardware/stm32_memorymap.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* If the common ARMv8-M vector handling logic is used, then it expects the
- * following definition in this file that provides the number of supported
- * external interrupts which, for this architecture, is provided in the
- * arch/stm32h5/chip.h header file.
- */
-
-#define ARMV8M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS
-
-/* Cache line sizes set in line with ST document RM0481 Rev 2.
- * DCACHE implementation, pg 284, Table 93
- * ICACHE implementation, pg 367, Table 85.
- */
-
-#define ARMV8M_ICACHE_LINESIZE 16 /* 16 bytes */
-#define ARMV8M_DCACHE_LINESIZE 16 /* 16 bytes */
-
-#endif /* __ARCH_ARM_SRC_STM32H5_CHIP_H */
+#endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_DMASIGMAP_H */