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Posted to commits@nuttx.apache.org by xi...@apache.org on 2020/12/02 17:21:20 UTC

[incubator-nuttx] branch master updated: arch/stm32: Fix a wrong bitfield definition

This is an automated email from the ASF dual-hosted git repository.

xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git


The following commit(s) were added to refs/heads/master by this push:
     new 32b49e6  arch/stm32: Fix a wrong bitfield definition
32b49e6 is described below

commit 32b49e6db881ab59014f36bccd88f2597c36eaee
Author: Nathan Hartman <59...@users.noreply.github.com>
AuthorDate: Tue Dec 1 19:53:09 2020 -0500

    arch/stm32: Fix a wrong bitfield definition
    
    arch/arm/src/stm32/hardware/stm32_adc_v2.h:
    
        * ADC_CFGR1_JAWD1EN: Change from (1 << 22) to (1 << 24)
          and update comment.
---
 arch/arm/src/stm32/hardware/stm32_adc_v2.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/src/stm32/hardware/stm32_adc_v2.h b/arch/arm/src/stm32/hardware/stm32_adc_v2.h
index 5b52c8a..4deae87 100644
--- a/arch/arm/src/stm32/hardware/stm32_adc_v2.h
+++ b/arch/arm/src/stm32/hardware/stm32_adc_v2.h
@@ -465,7 +465,7 @@
 #define ADC_CFGR1_JQM                 (1 << 21)                    /* Bit 21: JSQR queue mode */
 #define ADC_CFGR1_AWD1SGL             (1 << 22)                    /* Bit 22: Enable watchdog on single/all channels */
 #define ADC_CFGR1_AWD1EN              (1 << 23)                    /* Bit 23: Analog watchdog enable 1 regular channels */
-#define ADC_CFGR1_JAWD1EN             (1 << 22)                    /* Bit 22: Analog watchdog enable 1 injected channels */
+#define ADC_CFGR1_JAWD1EN             (1 << 24)                    /* Bit 24: Analog watchdog enable 1 injected channels */
 #define ADC_CFGR1_JAUTO               (1 << 25)                    /* Bit 25: Automatic Injected Group conversion */
 #define ADC_CFGR1_AWD1CH_SHIFT        (26)                         /* Bits 26-30: Analog watchdog 1 channel select bits */
 #define ADC_CFGR1_AWD1CH_MASK         (31 << ADC_CFGR1_AWD1CH_SHIFT)