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Posted to dev@nuttx.apache.org by Michael Jung <mi...@gmx.net> on 2022/03/25 16:06:46 UTC
STM32U585: Can't enable peripheral clock for IO port I (GPIOIEN in RCC_AHB2ENR1)
Hello,
This is more about STM32 than it is about NuttX, but I know there are
experts here: STM32U585 does have 8 GPIOs on Port I. However, setting bit
8 (GPIOIEN) in RCC_AHB2ENR1 seems to be ignored (i.e. GPIOIEN remains at
0). For the other eight IO ports (GPIO[A-H]EN) it works just fine. Any
ideas anyone?
Thanks!
Michael
Re: STM32U585: Can't enable peripheral clock for IO port I (GPIOIEN in RCC_AHB2ENR1)
Posted by Alan Carvalho de Assis <ac...@gmail.com>.
On 3/25/22, Michael Jung <mi...@gmx.net> wrote:
> Hi David,
>
> I think I figured it out: I am running in the non-secure world of
> TrustZone. Turns out ST missed configuring the IO Port I as non-secure in
> their STM32U5 port of TrustedFirmware-M (all other IO ports are configured
> as non-secure). I am compiling right now.
>
> Security sucks :-)
Hahaha, I hope the NuttX Security Team don't read it! :-D
BR,
Alan
Re: STM32U585: Can't enable peripheral clock for IO port I (GPIOIEN in RCC_AHB2ENR1)
Posted by Michael Jung <mi...@gmx.net>.
Hi David,
I think I figured it out: I am running in the non-secure world of
TrustZone. Turns out ST missed configuring the IO Port I as non-secure in
their STM32U5 port of TrustedFirmware-M (all other IO ports are configured
as non-secure). I am compiling right now.
Security sucks :-)
Thanks for your help
Michael
Am Fr., 25. März 2022 um 17:50 Uhr schrieb David Sidrane <
david.sidrane@nscdg.com>:
> Does the CPU busfault if write the GPIOI MODER? Do the values stick when
> written?
>
> -----Original Message-----
> From: Michael Jung <mi...@gmx.net>
> Sent: Friday, March 25, 2022 9:36 AM
> To: dev <de...@nuttx.apache.org>
> Subject: Re: STM32U585: Can't enable peripheral clock for IO port I
> (GPIOIEN
> in RCC_AHB2ENR1)
>
> Hi David,
>
> Thanks for your reply. Actually, I am trying to get the B-U585I-IOT02A's
> NOR flash chip running, which is connected via OCTOSPI. I can issue a
> single command (READID) to the NOR flash and I get a sane reply, but any
> follow-on command will just return nonsense (more specifically, the READID
> reply will be returned over and over again). This seemed to point to
> problems with the nCS signal, which turned out to be on PI5. I then
> realized
> via JTAG/SVD that GPIOIEN is not set. Single stepping through the code I
> see
> that the value 0x802001ff is written to RCC_AHB2ENR1, but reading back the
> register returns 0x802000ff.
>
> The stm32l5, which I based the stm32u5 code on, did not have an IO port I.
> I must have missed a piece of logic during porting I guess.
>
> Bye,
> Michael
>
> Am Fr., 25. März 2022 um 17:22 Uhr schrieb David Sidrane <
> david.sidrane@nscdg.com>:
>
> > Hi Michael,
> >
> > Odd. Did you check the defines? How are you verifying it? Have you
> > JTAG-ed it, could it be bad SVD? Have you just printed the value to be
> > set and the result ?
> >
> > David
> >
> > -----Original Message-----
> > From: Michael Jung <mi...@gmx.net>
> > Sent: Friday, March 25, 2022 9:07 AM
> > To: dev <de...@nuttx.apache.org>
> > Subject: STM32U585: Can't enable peripheral clock for IO port I
> > (GPIOIEN in
> > RCC_AHB2ENR1)
> >
> > Hello,
> >
> > This is more about STM32 than it is about NuttX, but I know there are
> > experts here: STM32U585 does have 8 GPIOs on Port I. However,
> > setting bit
> > 8 (GPIOIEN) in RCC_AHB2ENR1 seems to be ignored (i.e. GPIOIEN remains
> > at 0).
> > For the other eight IO ports (GPIO[A-H]EN) it works just fine. Any
> > ideas anyone?
> >
> > Thanks!
> > Michael
> >
>
RE: STM32U585: Can't enable peripheral clock for IO port I (GPIOIEN in RCC_AHB2ENR1)
Posted by David Sidrane <da...@nscdg.com>.
Does the CPU busfault if write the GPIOI MODER? Do the values stick when
written?
-----Original Message-----
From: Michael Jung <mi...@gmx.net>
Sent: Friday, March 25, 2022 9:36 AM
To: dev <de...@nuttx.apache.org>
Subject: Re: STM32U585: Can't enable peripheral clock for IO port I (GPIOIEN
in RCC_AHB2ENR1)
Hi David,
Thanks for your reply. Actually, I am trying to get the B-U585I-IOT02A's
NOR flash chip running, which is connected via OCTOSPI. I can issue a
single command (READID) to the NOR flash and I get a sane reply, but any
follow-on command will just return nonsense (more specifically, the READID
reply will be returned over and over again). This seemed to point to
problems with the nCS signal, which turned out to be on PI5. I then realized
via JTAG/SVD that GPIOIEN is not set. Single stepping through the code I see
that the value 0x802001ff is written to RCC_AHB2ENR1, but reading back the
register returns 0x802000ff.
The stm32l5, which I based the stm32u5 code on, did not have an IO port I.
I must have missed a piece of logic during porting I guess.
Bye,
Michael
Am Fr., 25. März 2022 um 17:22 Uhr schrieb David Sidrane <
david.sidrane@nscdg.com>:
> Hi Michael,
>
> Odd. Did you check the defines? How are you verifying it? Have you
> JTAG-ed it, could it be bad SVD? Have you just printed the value to be
> set and the result ?
>
> David
>
> -----Original Message-----
> From: Michael Jung <mi...@gmx.net>
> Sent: Friday, March 25, 2022 9:07 AM
> To: dev <de...@nuttx.apache.org>
> Subject: STM32U585: Can't enable peripheral clock for IO port I
> (GPIOIEN in
> RCC_AHB2ENR1)
>
> Hello,
>
> This is more about STM32 than it is about NuttX, but I know there are
> experts here: STM32U585 does have 8 GPIOs on Port I. However,
> setting bit
> 8 (GPIOIEN) in RCC_AHB2ENR1 seems to be ignored (i.e. GPIOIEN remains
> at 0).
> For the other eight IO ports (GPIO[A-H]EN) it works just fine. Any
> ideas anyone?
>
> Thanks!
> Michael
>
Re: STM32U585: Can't enable peripheral clock for IO port I (GPIOIEN in RCC_AHB2ENR1)
Posted by Michael Jung <mi...@gmx.net>.
Hi David,
Thanks for your reply. Actually, I am trying to get the B-U585I-IOT02A's
NOR flash chip running, which is connected via OCTOSPI. I can issue a
single command (READID) to the NOR flash and I get a sane reply, but any
follow-on command will just return nonsense (more specifically, the READID
reply will be returned over and over again). This seemed to point to
problems with the nCS signal, which turned out to be on PI5. I then
realized via JTAG/SVD that GPIOIEN is not set. Single stepping through the
code I see that the value 0x802001ff is written to RCC_AHB2ENR1, but
reading back the register returns 0x802000ff.
The stm32l5, which I based the stm32u5 code on, did not have an IO port I.
I must have missed a piece of logic during porting I guess.
Bye,
Michael
Am Fr., 25. März 2022 um 17:22 Uhr schrieb David Sidrane <
david.sidrane@nscdg.com>:
> Hi Michael,
>
> Odd. Did you check the defines? How are you verifying it? Have you JTAG-ed
> it, could it be bad SVD? Have you just printed the value to be set and the
> result ?
>
> David
>
> -----Original Message-----
> From: Michael Jung <mi...@gmx.net>
> Sent: Friday, March 25, 2022 9:07 AM
> To: dev <de...@nuttx.apache.org>
> Subject: STM32U585: Can't enable peripheral clock for IO port I (GPIOIEN in
> RCC_AHB2ENR1)
>
> Hello,
>
> This is more about STM32 than it is about NuttX, but I know there are
> experts here: STM32U585 does have 8 GPIOs on Port I. However, setting bit
> 8 (GPIOIEN) in RCC_AHB2ENR1 seems to be ignored (i.e. GPIOIEN remains at
> 0).
> For the other eight IO ports (GPIO[A-H]EN) it works just fine. Any ideas
> anyone?
>
> Thanks!
> Michael
>
RE: STM32U585: Can't enable peripheral clock for IO port I (GPIOIEN in RCC_AHB2ENR1)
Posted by David Sidrane <da...@nscdg.com>.
Hi Michael,
Odd. Did you check the defines? How are you verifying it? Have you JTAG-ed
it, could it be bad SVD? Have you just printed the value to be set and the
result ?
David
-----Original Message-----
From: Michael Jung <mi...@gmx.net>
Sent: Friday, March 25, 2022 9:07 AM
To: dev <de...@nuttx.apache.org>
Subject: STM32U585: Can't enable peripheral clock for IO port I (GPIOIEN in
RCC_AHB2ENR1)
Hello,
This is more about STM32 than it is about NuttX, but I know there are
experts here: STM32U585 does have 8 GPIOs on Port I. However, setting bit
8 (GPIOIEN) in RCC_AHB2ENR1 seems to be ignored (i.e. GPIOIEN remains at 0).
For the other eight IO ports (GPIO[A-H]EN) it works just fine. Any ideas
anyone?
Thanks!
Michael