[Apache TVM Discuss] [Questions] Cache coherency on ZCU102

[XiaoXuanwen via Apache TVM Discuss <no...@discuss.tvm.ai>]

Hello all:

First of all, please forgive me for my poor English.

We try to test VTA on ZCU102, a problem was found. 

When HPC on PL reads or writes data, the hardware cache coherency can not work.

Modify function VTAMemAlloc:
   void * VTAMemAlloc(size_t size, int cached) {
      ......
      // return cma_alloc(size, cached);
      return cma_alloc( size, 0 );
   }

The VTA can work normally, but the speed is more than ten times slower.


I found hardware cache coherency support by CCI, need to confirm two register values for CCI:
   Snoop Control Register
   Control Override Register

Because the BSP is downloaded from Xilinx's official website, so I think values of these two registers should be correct, and it's hard to confirm its value.

Who knows the reason, can you tell me?

XiaoXuanwen





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