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Posted to commits@tvm.apache.org by GitBox <gi...@apache.org> on 2022/07/15 21:46:12 UTC
[GitHub] [tvm] vinx13 opened a new pull request, #12113: [MetaSchedule] Allow MultiLevelTilingTensorCore rule to specify multiple tensor intrin groups
vinx13 opened a new pull request, #12113:
URL: https://github.com/apache/tvm/pull/12113
This PR made it possible to specify multiple tensor core intrinsics (for different dtype) at the same time.
cc @masahi @spectrometerHBH @junrushao1994
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[GitHub] [tvm] vinx13 commented on a diff in pull request #12113: [MetaSchedule] Allow MultiLevelTilingTensorCore rule to specify multiple tensor intrin groups
Posted by GitBox <gi...@apache.org>.
vinx13 commented on code in PR #12113:
URL: https://github.com/apache/tvm/pull/12113#discussion_r922610270
##########
python/tvm/meta_schedule/testing/schedule_rule.py:
##########
@@ -114,18 +115,29 @@ def multi_level_tiling(target: Target) -> ScheduleRule:
def multi_level_tiling_tensor_core(
target: Target,
- write_reuse_scope="shared",
- in_dtype="float16",
- out_dtype="float32",
- trans_b=False,
+ write_reuse_scope: str = "shared",
+ in_dtype: Union[str, List[str]] = "float16",
+ out_dtype: Union[str, List[str]] = "float32",
+ trans_b: Union[bool, List[bool]] = False,
) -> ScheduleRule:
"""Default schedule rules for with multi-level tiling reuse for tensor core"""
assert write_reuse_scope in ["shared", "global"]
+ if not isinstance(in_dtype, list):
+ in_dtype = [in_dtype]
+ if not isinstance(out_dtype, list):
+ out_dtype = [out_dtype]
+ if not isinstance(trans_b, list):
+ trans_b = [trans_b]
+
if target.kind.name == "cuda":
+ intrin_groups = [
+ tensor_intrin.get_wmma_intrin_group(write_reuse_scope, _in_dtype, _out_dtype, _trans_b)
+ for _in_dtype in in_dtype
+ for _out_dtype in out_dtype
+ for _trans_b in trans_b
Review Comment:
yes, this is to allow one single rule to apply to different workloads (different dtypes).
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[GitHub] [tvm] masahi merged pull request #12113: [MetaSchedule] Allow MultiLevelTilingTensorCore rule to specify multiple tensor intrin groups
Posted by GitBox <gi...@apache.org>.
masahi merged PR #12113:
URL: https://github.com/apache/tvm/pull/12113
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[GitHub] [tvm] masahi commented on a diff in pull request #12113: [MetaSchedule] Allow MultiLevelTilingTensorCore rule to specify multiple tensor intrin groups
Posted by GitBox <gi...@apache.org>.
masahi commented on code in PR #12113:
URL: https://github.com/apache/tvm/pull/12113#discussion_r922605734
##########
python/tvm/meta_schedule/testing/schedule_rule.py:
##########
@@ -114,18 +115,29 @@ def multi_level_tiling(target: Target) -> ScheduleRule:
def multi_level_tiling_tensor_core(
target: Target,
- write_reuse_scope="shared",
- in_dtype="float16",
- out_dtype="float32",
- trans_b=False,
+ write_reuse_scope: str = "shared",
+ in_dtype: Union[str, List[str]] = "float16",
+ out_dtype: Union[str, List[str]] = "float32",
+ trans_b: Union[bool, List[bool]] = False,
) -> ScheduleRule:
"""Default schedule rules for with multi-level tiling reuse for tensor core"""
assert write_reuse_scope in ["shared", "global"]
+ if not isinstance(in_dtype, list):
+ in_dtype = [in_dtype]
+ if not isinstance(out_dtype, list):
+ out_dtype = [out_dtype]
+ if not isinstance(trans_b, list):
+ trans_b = [trans_b]
+
if target.kind.name == "cuda":
+ intrin_groups = [
+ tensor_intrin.get_wmma_intrin_group(write_reuse_scope, _in_dtype, _out_dtype, _trans_b)
+ for _in_dtype in in_dtype
+ for _out_dtype in out_dtype
+ for _trans_b in trans_b
Review Comment:
Given a compute, isn't there only one group that's valid?
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