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Posted to commits@nuttx.apache.org by da...@apache.org on 2020/02/07 12:53:46 UTC
[incubator-nuttx] branch master updated: S32K add support for Nxp
drone boards (#224)
This is an automated email from the ASF dual-hosted git repository.
davids5 pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new 499607d S32K add support for Nxp drone boards (#224)
499607d is described below
commit 499607d68f609aa83e617d132cb36090c0fcca00
Author: Peter van der Perk <57...@users.noreply.github.com>
AuthorDate: Fri Feb 7 13:53:40 2020 +0100
S32K add support for Nxp drone boards (#224)
* S32K add support for Nxp drone boards
* Update arch/arm/src/s32k1xx/hardware/s32k1xx_rtc.h codestyle
Co-Authored-By: David Sidrane <Da...@Nscdg.com>
Co-authored-by: Jari van Ewijk <ja...@nxp.com>
Co-authored-by: David Sidrane <Da...@Nscdg.com>
---
arch/arm/include/s32k1xx/irq.h | 6 +-
arch/arm/src/s32k1xx/Kconfig | 15 +-
arch/arm/src/s32k1xx/Make.defs | 4 +
arch/arm/src/s32k1xx/chip.h | 7 +-
arch/arm/src/s32k1xx/hardware/s32k148_pinmux.h | 16 +-
arch/arm/src/s32k1xx/hardware/s32k1xx_rtc.h | 94 ++++++++
arch/arm/src/s32k1xx/s32k14x/Make.defs | 1 +
arch/arm/src/s32k1xx/s32k1xx_clockconfig.c | 85 ++++---
arch/arm/src/s32k1xx/s32k1xx_clockconfig.h | 16 +-
arch/arm/src/s32k1xx/s32k1xx_enet.c | 181 +++++++++-----
arch/arm/src/s32k1xx/s32k1xx_lpi2c.c | 45 +++-
arch/arm/src/s32k1xx/s32k1xx_lpspi.c | 45 ++--
arch/arm/src/s32k1xx/s32k1xx_pin.h | 11 +-
arch/arm/src/s32k1xx/s32k1xx_pinirq.c | 53 ++--
arch/arm/src/s32k1xx/s32k1xx_rtc.c | 267 +++++++++++++++++++++
arch/arm/src/s32k1xx/{chip.h => s32k1xx_rtc.h} | 110 ++++++---
arch/arm/src/s32k1xx/s32k1xx_start.c | 15 +-
boards/Kconfig | 42 ++++
boards/arm/s32k1xx/rddrone-uavcan144/Kconfig | 8 +
boards/arm/s32k1xx/rddrone-uavcan144/README.txt | 15 ++
.../configs/nsh/defconfig | 31 ++-
.../configs/nshdebug}/defconfig | 33 ++-
.../include/board.h | 39 ++-
.../s32k1xx/rddrone-uavcan144/scripts/Make.defs | 131 ++++++++++
.../scripts/flash.ld | 14 +-
.../s32k1xx/rddrone-uavcan144/scripts/s32k144.cfg | 58 +++++
.../scripts/sram.ld | 14 +-
.../arm/s32k1xx/rddrone-uavcan144/src/.gitignore | 2 +
.../{s32k146evb => rddrone-uavcan144}/src/Makefile | 18 +-
.../src/rddrone-uavcan144.h} | 37 +--
.../rddrone-uavcan144/src/s32k1xx_appinit.c | 83 ++++---
.../src/s32k1xx_autoleds.c} | 167 +++++++------
.../s32k1xx/rddrone-uavcan144/src/s32k1xx_boot.c | 82 ++++---
.../src/s32k1xx_bringup.c} | 153 ++++++------
.../src/s32k1xx_buttons.c} | 165 +++++++------
.../rddrone-uavcan144/src/s32k1xx_clockconfig.c | 227 ++++++++++++++++++
.../rddrone-uavcan144/src/s32k1xx_periphclocks.c | 187 +++++++++++++++
.../s32k1xx/rddrone-uavcan144/src/s32k1xx_spi.c | 199 +++++++++++++++
.../rddrone-uavcan144/src/s32k1xx_userleds.c | 105 +++++---
boards/arm/s32k1xx/rddrone-uavcan146/Kconfig | 8 +
boards/arm/s32k1xx/rddrone-uavcan146/README.txt | 15 ++
.../configs/nsh/defconfig | 29 ++-
.../configs/nshdebug}/defconfig | 31 ++-
.../include/board.h | 37 ++-
.../s32k1xx/rddrone-uavcan146/scripts/Make.defs | 131 ++++++++++
.../scripts/flash.ld | 14 +-
.../s32k1xx/rddrone-uavcan146/scripts/s32k146.cfg | 58 +++++
.../scripts/sram.ld | 14 +-
.../arm/s32k1xx/rddrone-uavcan146/src/.gitignore | 2 +
.../{s32k146evb => rddrone-uavcan146}/src/Makefile | 18 +-
.../src/rddrone-uavcan146.h} | 37 +--
.../rddrone-uavcan146/src/s32k1xx_appinit.c | 83 ++++---
.../src/s32k1xx_autoleds.c} | 167 +++++++------
.../s32k1xx/rddrone-uavcan146/src/s32k1xx_boot.c | 82 ++++---
.../src/s32k1xx_bringup.c} | 150 ++++++------
.../src/s32k1xx_buttons.c} | 165 +++++++------
.../rddrone-uavcan146/src/s32k1xx_clockconfig.c | 227 ++++++++++++++++++
.../rddrone-uavcan146/src/s32k1xx_periphclocks.c | 187 +++++++++++++++
.../s32k1xx/rddrone-uavcan146/src/s32k1xx_spi.c | 199 +++++++++++++++
.../rddrone-uavcan146/src/s32k1xx_userleds.c | 105 +++++---
boards/arm/s32k1xx/s32k118evb/README.txt | 4 +-
boards/arm/s32k1xx/s32k118evb/include/board.h | 14 +-
boards/arm/s32k1xx/s32k118evb/src/Makefile | 12 +-
boards/arm/s32k1xx/s32k118evb/src/s32k118evb.h | 15 +-
.../arm/s32k1xx/s32k118evb/src/s32k1xx_appinit.c | 83 ++++---
.../src/{s32k118evb.h => s32k1xx_autoleds.c} | 167 +++++++------
.../arm/s32k1xx/s32k118evb/src/s32k1xx_boot.c | 90 ++++---
.../arm/s32k1xx/s32k118evb/src/s32k1xx_bringup.c | 98 +++++---
.../src/{s32k118evb.h => s32k1xx_buttons.c} | 165 +++++++------
.../s32k1xx/s32k118evb/src/s32k1xx_clockconfig.c | 208 ++++++++++++++++
.../s32k1xx/s32k118evb/src/s32k1xx_periphclocks.c | 152 ++++++++++++
.../arm/s32k1xx/s32k118evb/src/s32k1xx_userleds.c | 105 +++++---
boards/arm/s32k1xx/s32k144evb/Kconfig | 8 +
boards/arm/s32k1xx/s32k144evb/README.txt | 15 ++
.../configs/nsh/defconfig | 12 +-
.../{s32k146evb => s32k144evb}/include/board.h | 48 +++-
boards/arm/s32k1xx/s32k144evb/scripts/Make.defs | 131 ++++++++++
.../{s32k148evb => s32k144evb}/scripts/flash.ld | 14 +-
boards/arm/s32k1xx/s32k144evb/scripts/s32k144.cfg | 58 +++++
.../{s32k148evb => s32k144evb}/scripts/sram.ld | 14 +-
boards/arm/s32k1xx/s32k144evb/src/.gitignore | 2 +
.../{s32k146evb => s32k144evb}/src/Makefile | 18 +-
.../s32k146evb.h => s32k144evb/src/s32k144evb.h} | 35 ++-
.../arm/s32k1xx/s32k144evb/src/s32k1xx_appinit.c | 83 ++++---
.../src/s32k1xx_autoleds.c} | 167 +++++++------
.../arm/s32k1xx/s32k144evb/src/s32k1xx_boot.c | 82 ++++---
.../src/s32k1xx_bringup.c} | 147 ++++++------
.../src/s32k1xx_buttons.c} | 165 +++++++------
.../s32k1xx/s32k144evb/src/s32k1xx_clockconfig.c | 227 ++++++++++++++++++
.../s32k1xx/s32k144evb/src/s32k1xx_periphclocks.c | 187 +++++++++++++++
boards/arm/s32k1xx/s32k144evb/src/s32k1xx_spi.c | 198 +++++++++++++++
.../arm/s32k1xx/s32k144evb/src/s32k1xx_userleds.c | 105 +++++---
boards/arm/s32k1xx/s32k146evb/README.txt | 4 +-
.../arm/s32k1xx/s32k146evb/configs/nsh/defconfig | 6 +-
boards/arm/s32k1xx/s32k146evb/include/board.h | 38 ++-
boards/arm/s32k1xx/s32k146evb/src/Makefile | 16 +-
boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h | 17 +-
.../arm/s32k1xx/s32k146evb/src/s32k1xx_appinit.c | 83 ++++---
.../src/{s32k146evb.h => s32k1xx_autoleds.c} | 167 +++++++------
.../arm/s32k1xx/s32k146evb/src/s32k1xx_boot.c | 82 ++++---
.../src/s32k1xx_bringup.c} | 147 ++++++------
.../src/{s32k146evb.h => s32k1xx_buttons.c} | 165 +++++++------
.../s32k1xx/s32k146evb/src/s32k1xx_clockconfig.c | 227 ++++++++++++++++++
.../s32k1xx/s32k146evb/src/s32k1xx_periphclocks.c | 187 +++++++++++++++
boards/arm/s32k1xx/s32k146evb/src/s32k1xx_spi.c | 198 +++++++++++++++
.../arm/s32k1xx/s32k146evb/src/s32k1xx_userleds.c | 105 +++++---
boards/arm/s32k1xx/s32k148evb/README.txt | 4 +-
.../arm/s32k1xx/s32k148evb/configs/nsh/defconfig | 4 +-
boards/arm/s32k1xx/s32k148evb/include/board.h | 14 +-
boards/arm/s32k1xx/s32k148evb/scripts/flash.ld | 2 +-
boards/arm/s32k1xx/s32k148evb/scripts/sram.ld | 2 +-
boards/arm/s32k1xx/s32k148evb/src/Makefile | 12 +-
boards/arm/s32k1xx/s32k148evb/src/s32k148evb.h | 17 +-
.../arm/s32k1xx/s32k148evb/src/s32k1xx_appinit.c | 83 ++++---
.../src/{s32k148evb.h => s32k1xx_autoleds.c} | 167 +++++++------
.../arm/s32k1xx/s32k148evb/src/s32k1xx_boot.c | 90 ++++---
.../arm/s32k1xx/s32k148evb/src/s32k1xx_bringup.c | 98 +++++---
.../src/{s32k148evb.h => s32k1xx_buttons.c} | 165 +++++++------
.../s32k1xx/s32k148evb/src/s32k1xx_clockconfig.c | 227 ++++++++++++++++++
.../s32k1xx/s32k148evb/src/s32k1xx_periphclocks.c | 178 ++++++++++++++
.../arm/s32k1xx/s32k148evb/src/s32k1xx_userleds.c | 105 +++++---
drivers/spi/spi_bitbang.c | 38 +--
122 files changed, 7762 insertions(+), 2255 deletions(-)
diff --git a/arch/arm/include/s32k1xx/irq.h b/arch/arm/include/s32k1xx/irq.h
index b18bef7..ddef8ea 100644
--- a/arch/arm/include/s32k1xx/irq.h
+++ b/arch/arm/include/s32k1xx/irq.h
@@ -46,10 +46,10 @@
#include <nuttx/config.h>
-#if defined(CONFIG_ARCH_CHIP_S32K11X)
-# include <arch/chip/s32k11x_irq.h>
-#elif defined(CONFIG_ARCH_CHIP_S32K14X)
+#if defined(CONFIG_ARCH_CHIP_S32K14X)
# include <arch/chip/s32k14x_irq.h>
+#elif defined(CONFIG_ARCH_CHIP_S32K11X)
+# include <arch/chip/s32k11x_irq.h>
#else
# error Unrecognized S32K1XX part
#endif
diff --git a/arch/arm/src/s32k1xx/Kconfig b/arch/arm/src/s32k1xx/Kconfig
index ff480fb..63e0cd9 100644
--- a/arch/arm/src/s32k1xx/Kconfig
+++ b/arch/arm/src/s32k1xx/Kconfig
@@ -79,6 +79,9 @@ config ARCH_CHIP_S32K14X
config S32K1XX_HAVE_ENET
bool
default n
+ select ARCH_HAVE_PHY
+ select ARCH_PHY_INTERRUPT
+ select ARCH_HAVE_NETDEV_STATISTICS
config S32K1XX_HAVE_EWM
bool
@@ -183,18 +186,26 @@ config S32K1XX_LPUART0
default n
select S32K1XX_LPUART
select LPUART0_SERIALDRIVER
+ select ARCH_HAVE_SERIAL_TERMIOS
config S32K1XX_LPUART1
bool "LPUART1"
default n
select S32K1XX_LPUART
select LPUART1_SERIALDRIVER
+ select ARCH_HAVE_SERIAL_TERMIOS
config S32K1XX_LPUART2
bool "LPUART2"
default n
select S32K1XX_LPUART
select LPUART2_SERIALDRIVER
+ select ARCH_HAVE_SERIAL_TERMIOS
+
+config S32K1XX_RTC
+ bool "RTC"
+ default n
+
endmenu # S32K1XX Peripheral Selection
@@ -267,14 +278,14 @@ config S32K1XX_FLASHCFG_FPROT
config S32K1XX_FLASHCFG_FSEC
hex "Flash security byte"
- default 0xff
+ default 0xfe
---help---
Refer to the S32K1xx reference manual or to hardware/s32k1xx_flashcfg.h
for a description of the FSEC bitfields.
config S32K1XX_FLASHCFG_FOPT
hex "Flash nonvolatile option byte"
- default 0xff
+ default 0x7f
---help---
Refer to the S32K1xx reference manual or to hardware/s32k1xx_flashcfg.h
for a description of the FOPT bitfields.
diff --git a/arch/arm/src/s32k1xx/Make.defs b/arch/arm/src/s32k1xx/Make.defs
index 880f575..3f69fb0 100644
--- a/arch/arm/src/s32k1xx/Make.defs
+++ b/arch/arm/src/s32k1xx/Make.defs
@@ -90,6 +90,10 @@ ifeq ($(CONFIG_S32K1XX_ENET),y)
CHIP_CSRCS += s32k1xx_enet.c
endif
+ifeq ($(CONFIG_S32K1XX_RTC),y)
+CHIP_CSRCS += s32k1xx_rtc.c
+endif
+
# Source files specific to the ARM CPU family and to the S32K1xx chip family
ifeq ($(CONFIG_ARCH_CHIP_S32K11X),y)
diff --git a/arch/arm/src/s32k1xx/chip.h b/arch/arm/src/s32k1xx/chip.h
index f3f9b9c..73b5882 100644
--- a/arch/arm/src/s32k1xx/chip.h
+++ b/arch/arm/src/s32k1xx/chip.h
@@ -58,6 +58,11 @@
#define ARMV6M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT
#define ARMV7M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT
+/* Cache line sizes (in bytes)for the S32K14X */
+
+#define ARMV7M_DCACHE_LINESIZE 16 /* 16 bytes (4 words) */
+#define ARMV7M_ICACHE_LINESIZE 16 /* 16 bytes (4 words) */
+
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
@@ -71,7 +76,7 @@
************************************************************************************/
/************************************************************************************
- * Public Functions
+ * Public Function Prototypes
************************************************************************************/
#endif /* __ARCH_ARM_SRC_S32K1XX_CHIP_H */
diff --git a/arch/arm/src/s32k1xx/hardware/s32k148_pinmux.h b/arch/arm/src/s32k1xx/hardware/s32k148_pinmux.h
index 06afa60..bb6aaef 100644
--- a/arch/arm/src/s32k1xx/hardware/s32k148_pinmux.h
+++ b/arch/arm/src/s32k1xx/hardware/s32k148_pinmux.h
@@ -642,14 +642,18 @@
#define PIN_RMII_MDIO (PIN_ALT5 | PIN_PORTB | PIN4)
#define PIN_RMII_RX_DV (PIN_ALT5 | PIN_PORTC | PIN17)
#define PIN_RMII_RX_ER (PIN_ALT5 | PIN_PORTC | PIN16)
-#define PIN_RMII_RXD_1 (PIN_ALT5 | PIN_PORTC | PIN0)
-#define PIN_RMII_RXD_2 (PIN_ALT5 | PIN_PORTC | PIN1)
-#define PIN_RMII_RXD_3 (PIN_ALT4 | PIN_PORTC | PIN0)
-#define PIN_RMII_RXD_4 (PIN_ALT4 | PIN_PORTC | PIN1)
+#define PIN_RMII_RXD0_1 (PIN_ALT5 | PIN_PORTC | PIN1)
+#define PIN_RMII_RXD1_1 (PIN_ALT4 | PIN_PORTC | PIN0)
+#define PIN_RMII_RXD0_2 (PIN_ALT5 | PIN_PORTC | PIN0)
+#define PIN_RMII_RXD1_2 (PIN_ALT4 | PIN_PORTC | PIN1)
#define PIN_RMII_TX_CLK (PIN_ALT5 | PIN_PORTD | PIN11)
#define PIN_RMII_TX_EN (PIN_ALT5 | PIN_PORTD | PIN12)
-#define PIN_RMII_TXD_1 (PIN_ALT5 | PIN_PORTC | PIN2)
-#define PIN_RMII_TXD_2 (PIN_ALT5 | PIN_PORTD | PIN7)
+#define PIN_RMII_TXD0 (PIN_ALT5 | PIN_PORTC | PIN2)
+#define PIN_RMII_TXD1 (PIN_ALT5 | PIN_PORTD | PIN7)
+
+#define PIN_RMII_MDC PIN_RMII_MDC_2
+#define PIN_RMII_RXD0 PIN_RMII_RXD0_1
+#define PIN_RMII_RXD1 PIN_RMII_RXD1_1
/* NMI */
diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_rtc.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_rtc.h
new file mode 100644
index 0000000..b09914e
--- /dev/null
+++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_rtc.h
@@ -0,0 +1,94 @@
+/****************************************************************************************************
+ * arch/arm/src/s32k1xx/chip/s32k1xx_rtc.h
+ *
+ * Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_RTC_H
+#define __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_RTC_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+#include <hardware/s32k1xx_memorymap.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* RTC Register Offsets *****************************************************************************/
+
+#define S32K1XX_RTC_TSR_OFFSET 0x0000 /* Time Seconds register */
+#define S32K1XX_RTC_TPR_OFFSET 0x0004 /* Time Prescaler Register */
+#define S32K1XX_RTC_TAR_OFFSET 0x0008 /* Time Alarm Register */
+#define S32K1XX_RTC_TCR_OFFSET 0x000C /* Time Compensation Register */
+#define S32K1XX_RTC_CR_OFFSET 0x0010 /* Control Register */
+#define S32K1XX_RTC_SR_OFFSET 0x0014 /* Status Register */
+#define S32K1XX_RTC_LR_OFFSET 0x0018 /* Lock Register */
+#define S32K1XX_RTC_IER_OFFSET 0x001C /* Interrupt Enable Register */
+
+/* RTC Register Addresses ***************************************************************************/
+
+#define S32K1XX_RTC_TSR (S32K1XX_RTC_BASE + S32K1XX_RTC_TSR_OFFSET)
+#define S32K1XX_RTC_TPR (S32K1XX_RTC_BASE + S32K1XX_RTC_TPR_OFFSET)
+#define S32K1XX_RTC_TAR (S32K1XX_RTC_BASE + S32K1XX_RTC_TAR_OFFSET)
+#define S32K1XX_RTC_TCR (S32K1XX_RTC_BASE + S32K1XX_RTC_TCR_OFFSET)
+#define S32K1XX_RTC_CR (S32K1XX_RTC_BASE + S32K1XX_RTC_CR_OFFSET)
+#define S32K1XX_RTC_SR (S32K1XX_RTC_BASE + S32K1XX_RTC_SR_OFFSET)
+#define S32K1XX_RTC_LR (S32K1XX_RTC_BASE + S32K1XX_RTC_LR_OFFSET)
+#define S32K1XX_RTC_IER (S32K1XX_RTC_BASE + S32K1XX_RTC_IER_OFFSET)
+
+/* RTC Register Bitfield Definitions ****************************************************************/
+
+/* TSR Bit Fields */
+
+#define RTC_TSR_SHIFT (0)
+#define RTC_TSR_MASK (0xffffffff << RTC_TSR_SHIFT)
+
+/* CR Bit Fields */
+
+#define RTC_CR_SWR (1 << 0)
+#define RTC_CR_SUP (1 << 2)
+#define RTC_CR_UM (1 << 3)
+#define RTC_CR_CPS (1 << 5)
+#define RTC_CR_LPOS (1 << 7)
+#define RTC_CR_CPE (1 << 24)
+
+/* SR Bit Fields */
+
+#define RTC_SR_TIF (1 << 0)
+#define RTC_SR_TOF (1 << 1)
+#define RTC_SR_TAF (1 << 2)
+#define RTC_SR_TCE (1 << 4)
+#endif /* __ARCH_ARM_SRC_S32K1XX_HARDWARE_S32K1XX_RTC_H */
diff --git a/arch/arm/src/s32k1xx/s32k14x/Make.defs b/arch/arm/src/s32k1xx/s32k14x/Make.defs
index 9fe8cd7..a0c67d5 100644
--- a/arch/arm/src/s32k1xx/s32k14x/Make.defs
+++ b/arch/arm/src/s32k1xx/s32k14x/Make.defs
@@ -48,6 +48,7 @@ CMN_CSRCS += up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c
CMN_CSRCS += up_doirq.c up_hardfault.c up_initialstate.c up_memfault.c
CMN_CSRCS += up_releasepending.c up_reprioritizertr.c up_schedulesigaction.c
CMN_CSRCS += up_sigdeliver.c up_svcall.c up_trigger_irq.c up_unblocktask.c
+CMN_CSRCS += up_systemreset.c
ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
CMN_ASRCS += up_lazyexception.S
diff --git a/arch/arm/src/s32k1xx/s32k1xx_clockconfig.c b/arch/arm/src/s32k1xx/s32k1xx_clockconfig.c
index 574446b..492b32c 100644
--- a/arch/arm/src/s32k1xx/s32k1xx_clockconfig.c
+++ b/arch/arm/src/s32k1xx/s32k1xx_clockconfig.c
@@ -113,8 +113,8 @@
#define SOSC_STABILIZATION_TIMEOUT 3205000
#define SPLL_STABILIZATION_TIMEOUT 1000
-/* System PLL reference clock after SCG_SPLLCFG[PREDIV] should be in the range of
- * SCG_SPLL_REF_MIN to SCG_SPLL_REF_MAX.
+/* System PLL reference clock after SCG_SPLLCFG[PREDIV] should be in the
+ * range of SCG_SPLL_REF_MIN to SCG_SPLL_REF_MAX.
*/
#define SCG_SPLL_REF_MIN 8000000
@@ -221,7 +221,7 @@ static uint32_t g_tclkfreq[NUMBER_OF_TCLK_INPUTS]; /* TCLKx clocks */
* Returned Value:
* The current system clock source.
*
- *****************************************************************************/
+ ****************************************************************************/
static inline uint32_t s32k1xx_get_scgclk_source(void)
{
@@ -240,7 +240,7 @@ static inline uint32_t s32k1xx_get_scgclk_source(void)
* Returned Value:
* The current running mode.
*
- *****************************************************************************/
+ ****************************************************************************/
static enum scg_system_clock_mode_e s32k1xx_get_runmode(void)
{
@@ -293,7 +293,7 @@ static enum scg_system_clock_mode_e s32k1xx_get_runmode(void)
* Returned Value:
* The SOSC frequency. Zero is returned if the SOSC is invalid.
*
- *****************************************************************************/
+ ****************************************************************************/
static uint32_t s32k1xx_get_soscfreq(void)
{
@@ -321,7 +321,7 @@ static uint32_t s32k1xx_get_soscfreq(void)
* Returned Value:
* The SIRC frequency. Zero is returned if the SIRC is invalid.
*
- *****************************************************************************/
+ ****************************************************************************/
static uint32_t s32k1xx_get_sircfreq(void)
{
@@ -333,7 +333,7 @@ static uint32_t s32k1xx_get_sircfreq(void)
if ((getreg32(S32K1XX_SCG_SIRCCFG) & SCG_SIRCCFG_RANGE) != 0)
{
- return SCG_SIRQ_HIGHRANGE_FREQUENCY;
+ return SCG_SIRC_HIGHRANGE_FREQUENCY;
}
}
@@ -352,7 +352,7 @@ static uint32_t s32k1xx_get_sircfreq(void)
* Returned Value:
* The FIRC frequency. Zero is returned if the FIRC is invalid.
*
- *****************************************************************************/
+ ****************************************************************************/
static uint32_t s32k1xx_get_fircfreq(void)
{
@@ -360,7 +360,7 @@ static uint32_t s32k1xx_get_fircfreq(void)
if ((getreg32(S32K1XX_SCG_FIRCCSR) & SCG_FIRCCSR_FIRCVLD) != 0)
{
- return SCG_FIRQ_FREQUENCY0;
+ return SCG_FIRC_FREQUENCY0;
}
else
{
@@ -380,7 +380,7 @@ static uint32_t s32k1xx_get_fircfreq(void)
* Returned Value:
* The SPLL frequency. Zero is returned if the SPLL is invalid.
*
- *****************************************************************************/
+ ****************************************************************************/
#ifdef CONFIG_S32K1XX_HAVE_SPLL
static uint32_t s32k1xx_get_spllfreq(void)
@@ -429,7 +429,7 @@ static uint32_t s32k1xx_get_spllfreq(void)
* Returned Values:
* The requested clock source frequency. Zero is returned on any error.
*
- *****************************************************************************/
+ ****************************************************************************/
static uint32_t s32k1xx_get_srcfreq(enum scg_system_clock_src_e src)
{
@@ -476,7 +476,7 @@ static uint32_t s32k1xx_get_srcfreq(enum scg_system_clock_src_e src)
* Zero (OK) is returned a success; A negated errno value is returned on
* any failure.
*
- *****************************************************************************/
+ ****************************************************************************/
static int
s32k1xx_set_sysclk_configuration(enum scg_system_clock_mode_e mode,
@@ -546,7 +546,7 @@ s32k1xx_set_sysclk_configuration(enum scg_system_clock_mode_e mode,
break;
#ifdef CONFIG_S32K1XX_HAVE_HSRUN
- case SCG_SYSTEM_CLOCK_MODE_HSRUN: /*!< High Speed Run mode. */
+ case SCG_SYSTEM_CLOCK_MODE_HSRUN: /* High Speed Run mode. */
DEBUGASSERT(SCG_SYSTEM_CLOCK_SRC_FIRC == config->src ||
SCG_SYSTEM_CLOCK_SRC_SYS_PLL == config->src);
@@ -574,6 +574,7 @@ s32k1xx_set_sysclk_configuration(enum scg_system_clock_mode_e mode,
break;
#endif
default:
+
/* Invalid mode */
DEBUGPANIC();
@@ -596,7 +597,7 @@ s32k1xx_set_sysclk_configuration(enum scg_system_clock_mode_e mode,
* Zero (OK) is returned a success; A negated errno value is returned on
* any failure.
*
- *****************************************************************************/
+ ****************************************************************************/
static int
s32k1xx_transition_systemclock(const struct scg_system_clock_config_s *cfg)
@@ -621,7 +622,7 @@ s32k1xx_transition_systemclock(const struct scg_system_clock_config_s *cfg)
if (ret == OK)
{
/* Wait for system clock to transition.
- *
+ *
* e10777: The SCG_RCCR[SCS] and SCG_HCCR[SCS] may have a corrupted
* status during the interval when the system clock is switching.
* Workaround: The SCS field should be read twice by the software to
@@ -662,7 +663,7 @@ s32k1xx_transition_systemclock(const struct scg_system_clock_config_s *cfg)
* Zero (OK) is returned a success; A negated errno value is returned on
* any failure.
*
- *****************************************************************************/
+ ****************************************************************************/
static int s32k1xx_firc_config(bool enable,
const struct scg_firc_config_s *firccfg)
@@ -690,7 +691,7 @@ static int s32k1xx_firc_config(bool enable,
regval &= ~SCG_FIRCCSR_LK;
putreg32(regval, S32K1XX_SCG_FIRCCSR);
- /* Disable monitor, disable clock and clear error. */
+ /* Disable monitor, disable clock and clear error. */
putreg32(SCG_FIRCCSR_FIRCERR, S32K1XX_SCG_FIRCCSR);
}
@@ -766,7 +767,7 @@ static int s32k1xx_firc_config(bool enable,
* Zero (OK) is returned a success; A negated errno value is returned on
* any failure.
*
- *****************************************************************************/
+ ****************************************************************************/
static int s32k11_firc_clocksource(void)
{
@@ -817,7 +818,7 @@ static int s32k11_firc_clocksource(void)
* Zero (OK) is returned a success; A negated errno value is returned on
* any failure.
*
- *****************************************************************************/
+ ****************************************************************************/
static int s32k1xx_sirc_config(bool enable,
const struct scg_sirc_config_s *sirccfg)
@@ -928,7 +929,7 @@ static int s32k1xx_sirc_config(bool enable,
* Zero (OK) is returned a success; A negated errno value is returned on
* any failure.
*
- *****************************************************************************/
+ ****************************************************************************/
static int s32k1xx_sosc_config(bool enable,
const struct scg_sosc_config_s *sosccfg)
@@ -1058,7 +1059,7 @@ static int s32k1xx_sosc_config(bool enable,
* Zero (OK) is returned a success; A negated errno value is returned on
* any failure.
*
- *****************************************************************************/
+ ****************************************************************************/
#ifdef CONFIG_S32K1XX_HAVE_SPLL
static int s32k1xx_spll_config(bool enable,
@@ -1151,6 +1152,7 @@ static int s32k1xx_spll_config(bool enable,
break;
default:
+
/* Invalid monitor mode */
DEBUGPANIC();
@@ -1188,7 +1190,7 @@ static int s32k1xx_spll_config(bool enable,
* Zero (OK) is returned a success; A negated errno value is returned on
* any failure.
*
- *****************************************************************************/
+ ****************************************************************************/
static int s32k1xx_configure_scgmodules(const struct scg_config_s *scgcfg)
{
@@ -1203,12 +1205,12 @@ static int s32k1xx_configure_scgmodules(const struct scg_config_s *scgcfg)
ret = s32k1xx_sirc_config(scgcfg->sirc.initialize, &scgcfg->sirc);
if (ret == OK)
{
- ret = s32k1xx_sosc_config(scgcfg->sosc.initialize, &scgcfg->sosc);
+ ret = s32k1xx_sosc_config(scgcfg->sosc.initialize, &scgcfg->sosc);
#ifdef CONFIG_S32K1XX_HAVE_SPLL
- if (ret == OK)
- {
- ret = s32k1xx_spll_config(scgcfg->spll.initialize, &scgcfg->spll);
- }
+ if (ret == OK)
+ {
+ ret = s32k1xx_spll_config(scgcfg->spll.initialize, &scgcfg->spll);
+ }
#endif
}
@@ -1298,7 +1300,8 @@ static int s32k1xx_configure_scgmodules(const struct scg_config_s *scgcfg)
{
/* Configure the remaining clock source (FIRC). */
- ret = s32k1xx_firc_config(scgcfg->firc.initialize, &scgcfg->firc);
+ ret = s32k1xx_firc_config(scgcfg->firc.initialize,
+ &scgcfg->firc);
if (ret == OK)
{
/* Transition to the next system clock source. */
@@ -1325,7 +1328,8 @@ static int s32k1xx_configure_scgmodules(const struct scg_config_s *scgcfg)
{
/* Configure the remaining clock source (FIRC) */
- ret = s32k1xx_firc_config(scgcfg->firc.initialize, &scgcfg->firc);
+ ret = s32k1xx_firc_config(scgcfg->firc.initialize,
+ &scgcfg->firc);
}
}
}
@@ -1346,7 +1350,7 @@ static int s32k1xx_configure_scgmodules(const struct scg_config_s *scgcfg)
* Zero (OK) is returned a success; A negated errno value is returned on
* any failure.
*
- *****************************************************************************/
+ ****************************************************************************/
static int s32k1xx_scg_config(const struct scg_config_s *scgcfg)
{
@@ -1414,7 +1418,7 @@ static int s32k1xx_scg_config(const struct scg_config_s *scgcfg)
}
}
- return ret;
+ return ret;
}
/****************************************************************************
@@ -1429,7 +1433,7 @@ static int s32k1xx_scg_config(const struct scg_config_s *scgcfg)
* Returned Value:
* None.
*
- *****************************************************************************/
+ ****************************************************************************/
static void s32k1xx_sim_config(const struct sim_clock_config_s *simcfg)
{
@@ -1590,7 +1594,7 @@ static void s32k1xx_sim_config(const struct sim_clock_config_s *simcfg)
* Returned Value:
* None.
*
- *****************************************************************************/
+ ****************************************************************************/
static void s32k1xx_pmc_config(const struct pmc_config_s *pmccfg)
{
@@ -1643,7 +1647,7 @@ static void s32k1xx_pmc_config(const struct pmc_config_s *pmccfg)
* Zero (OK) is returned a success; A negated errno value is returned on
* any failure.
*
- *****************************************************************************/
+ ****************************************************************************/
int s32k1xx_clockconfig(const struct clock_configuration_s *clkcfg)
{
@@ -1685,7 +1689,7 @@ int s32k1xx_clockconfig(const struct clock_configuration_s *clkcfg)
* The current value of the CORE clock frequency. Zero is returned on any
* failure.
*
- *****************************************************************************/
+ ****************************************************************************/
uint32_t s32k1xx_get_coreclk(void)
{
@@ -1722,7 +1726,7 @@ uint32_t s32k1xx_get_coreclk(void)
/* Slow IRC high range clock (8 MHz ) */
- coreclk = SCG_SIRQ_HIGHRANGE_FREQUENCY;
+ coreclk = SCG_SIRC_HIGHRANGE_FREQUENCY;
break;
case SCG_CSR_SCS_FIRC: /* Fast IRC */
@@ -1734,7 +1738,7 @@ uint32_t s32k1xx_get_coreclk(void)
/* Fast IRC is trimmed to 48 MHz */
- coreclk = SCG_FIRQ_FREQUENCY0;
+ coreclk = SCG_FIRC_FREQUENCY0;
break;
#ifdef CONFIG_S32K1XX_HAVE_SPLL
@@ -1767,10 +1771,10 @@ uint32_t s32k1xx_get_coreclk(void)
* type - Identifies the system clock of interest
*
* Returned Values:
- * The current value of the system clock frequency. Zero is returned on any
- * failure.
+ * The current value of the system clock frequency. Zero is returned on
+ * any failure.
*
- *****************************************************************************/
+ ****************************************************************************/
uint32_t s32k1xx_get_sysclk(enum scg_system_clock_type_e type)
{
@@ -1937,6 +1941,7 @@ uint32_t s32k1xx_get_asnchfreq(enum clock_names_e clksrc,
break;
default:
+
/* Invalid async clock source */
freq = 0;
diff --git a/arch/arm/src/s32k1xx/s32k1xx_clockconfig.h b/arch/arm/src/s32k1xx/s32k1xx_clockconfig.h
index cfbbe26..dc2c7c8 100644
--- a/arch/arm/src/s32k1xx/s32k1xx_clockconfig.h
+++ b/arch/arm/src/s32k1xx/s32k1xx_clockconfig.h
@@ -76,9 +76,9 @@
/* Nomial frequencies of internal clocks */
-#define SCG_SIRQ_LOWRANGE_FREQUENCY 2000000 /* 2MHz */
-#define SCG_SIRQ_HIGHRANGE_FREQUENCY 8000000 /* 8MHz */
-#define SCG_FIRQ_FREQUENCY0 48000000 /* 48MHz */
+#define SCG_SIRC_LOWRANGE_FREQUENCY 2000000 /* 2MHz */
+#define SCG_SIRC_HIGHRANGE_FREQUENCY 8000000 /* 8MHz */
+#define SCG_FIRC_FREQUENCY0 48000000 /* 48MHz */
#define NUMBER_OF_TCLK_INPUTS 3
@@ -479,7 +479,7 @@ extern "C"
* Zero (OK) is returned a success; A negated errno value is returned on
* any failure.
*
- *****************************************************************************/
+ ****************************************************************************/
int s32k1xx_clockconfig(FAR const struct clock_configuration_s *clkcfg);
@@ -496,7 +496,7 @@ int s32k1xx_clockconfig(FAR const struct clock_configuration_s *clkcfg);
* The current value of the CORE clock frequency. Zero is returned on any
* failure.
*
- *****************************************************************************/
+ ****************************************************************************/
uint32_t s32k1xx_get_coreclk(void);
@@ -511,10 +511,10 @@ uint32_t s32k1xx_get_coreclk(void);
* type - Identifies the system clock of interest
*
* Returned Values:
- * The current value of the system clock frequency. Zero is returned on any
- * failure.
+ * The current value of the system clock frequency. Zero is returned on
+ * any failure.
*
- *****************************************************************************/
+ ****************************************************************************/
uint32_t s32k1xx_get_sysclk(enum scg_system_clock_type_e type);
diff --git a/arch/arm/src/s32k1xx/s32k1xx_enet.c b/arch/arm/src/s32k1xx/s32k1xx_enet.c
index 2f5e719..682cd4f 100644
--- a/arch/arm/src/s32k1xx/s32k1xx_enet.c
+++ b/arch/arm/src/s32k1xx/s32k1xx_enet.c
@@ -207,6 +207,15 @@
# define BOARD_PHY_10BASET(s) (((s)&MII_LAN8720_SPSCR_10MBPS) != 0)
# define BOARD_PHY_100BASET(s) (((s)&MII_LAN8720_SPSCR_100MBPS) != 0)
# define BOARD_PHY_ISDUPLEX(s) (((s)&MII_LAN8720_SPSCR_DUPLEX) != 0)
+#elif defined(CONFIG_ETH0_PHY_TJA1101)
+# define BOARD_PHY_NAME "TJA1101"
+# define BOARD_PHYID1 MII_PHYID1_TJA1101
+# define BOARD_PHYID2 MII_PHYID2_TJA1101
+# define BOARD_PHY_STATUS MII_TJA110X_BSR
+# define BOARD_PHY_ADDR (0)
+# define BOARD_PHY_10BASET(s) 0 /* PHY only supports 100BASE-T1 */
+# define BOARD_PHY_100BASET(s) 1 /* PHY only supports 100BASE-T1 */
+# define BOARD_PHY_ISDUPLEX(s) 1 /* PHY only supports fullduplex */
#else
# error "Unrecognized or missing PHY selection"
#endif
@@ -222,7 +231,7 @@
* = 23
*/
-#define S32K1XX_MII_SPEED 0x38 /* 100Mbs. Revisit and remove hardcoded value */
+#define S32K1XX_MII_SPEED 0x0f /* 100Mbs. Revisit and remove hardcoded value */
#if S32K1XX_MII_SPEED > 63
# error "S32K1XX_MII_SPEED is out-of-range"
#endif
@@ -251,8 +260,8 @@
* Private Types
****************************************************************************/
-/* The s32k1xx_driver_s encapsulates all state information for a single hardware
- * interface
+/* The s32k1xx_driver_s encapsulates all state information for a single
+ * hardware interface
*/
struct s32k1xx_driver_s
@@ -328,7 +337,8 @@ static void s32k1xx_receive(FAR struct s32k1xx_driver_s *priv);
static void s32k1xx_txdone(FAR struct s32k1xx_driver_s *priv);
static void s32k1xx_enet_interrupt_work(FAR void *arg);
-static int s32k1xx_enet_interrupt(int irq, FAR void *context, FAR void *arg);
+static int s32k1xx_enet_interrupt(int irq, FAR void *context,
+ FAR void *arg);
/* Watchdog timer expirations */
@@ -537,13 +547,13 @@ static int s32k1xx_transmit(FAR struct s32k1xx_driver_s *priv)
buf = (uint8_t *)s32k1xx_swap32((uint32_t)priv->dev.d_buf);
if (priv->rxdesc[priv->rxtail].data == buf)
{
- struct enet_desc_s *rxdesc = &priv->rxdesc[priv->rxtail];
+ struct enet_desc_s *rxdesc = &priv->rxdesc[priv->rxtail];
- /* Data was written into the RX buffer, so swap the TX and RX buffers */
+ /* Data was written into the RX buffer, so swap the TX and RX buffers */
- DEBUGASSERT((rxdesc->status1 & RXDESC_E) == 0);
- rxdesc->data = txdesc->data;
- txdesc->data = buf;
+ DEBUGASSERT((rxdesc->status1 & RXDESC_E) == 0);
+ rxdesc->data = txdesc->data;
+ txdesc->data = buf;
}
else
{
@@ -647,11 +657,11 @@ static int s32k1xx_txpoll(struct net_driver_s *dev)
{
return -EBUSY;
}
- }
+ }
}
- /* If zero is returned, the polling will continue until all connections have
- * been examined.
+ /* If zero is returned, the polling will continue until all connections
+ * have been examined.
*/
return 0;
@@ -684,7 +694,7 @@ static inline void s32k1xx_dispatch(FAR struct s32k1xx_driver_s *priv)
#ifdef CONFIG_NET_PKT
/* When packet sockets are enabled, feed the frame into the packet tap */
- pkt_input(&priv->dev);
+ pkt_input(&priv->dev);
#endif
#ifdef CONFIG_NET_IPv4
@@ -842,7 +852,8 @@ static void s32k1xx_receive(FAR struct s32k1xx_driver_s *priv)
*/
priv->dev.d_len = s32k1xx_swap16(rxdesc->length);
- priv->dev.d_buf = (uint8_t *)s32k1xx_swap32((uint32_t)rxdesc->data);
+ priv->dev.d_buf =
+ (uint8_t *)s32k1xx_swap32((uint32_t)rxdesc->data);
/* Invalidate the buffer so that the correct packet will be re-read
* from memory when the packet content is accessed.
@@ -1080,7 +1091,8 @@ static void s32k1xx_enet_interrupt_work(FAR void *arg)
#if 0
up_enable_irq(S32K1XX_IRQ_EMACTMR);
#endif
- up_enable_irq(S32K1XX_IRQ_ENET);
+ up_enable_irq(S32K1XX_IRQ_ENET_TXDONE);
+ up_enable_irq(S32K1XX_IRQ_ENET_RXDONE);
}
/****************************************************************************
@@ -1112,7 +1124,8 @@ static int s32k1xx_enet_interrupt(int irq, FAR void *context, FAR void *arg)
* condition here.
*/
- up_disable_irq(S32K1XX_IRQ_ENET);
+ up_disable_irq(S32K1XX_IRQ_ENET_TXDONE);
+ up_disable_irq(S32K1XX_IRQ_ENET_RXDONE);
/* Schedule to perform the interrupt processing on the worker thread. */
@@ -1188,7 +1201,8 @@ static void s32k1xx_txtimeout_expiry(int argc, uint32_t arg, ...)
* condition with interrupt work that is already queued and in progress.
*/
- up_disable_irq(S32K1XX_IRQ_ENET);
+ up_disable_irq(S32K1XX_IRQ_ENET_TXDONE);
+ up_disable_irq(S32K1XX_IRQ_ENET_RXDONE);
/* Schedule to perform the TX timeout processing on the worker thread,
* canceling any pending interrupt work.
@@ -1218,8 +1232,9 @@ static void s32k1xx_poll_work(FAR void *arg)
{
FAR struct s32k1xx_driver_s *priv = (FAR struct s32k1xx_driver_s *)arg;
- /* Check if there is there is a transmission in progress. We cannot perform
- * the TX poll if he are unable to accept another packet for transmission.
+ /* Check if there is there is a transmission in progress. We cannot
+ * perform the TX poll if he are unable to accept another packet for
+ * transmission.
*/
net_lock();
@@ -1372,7 +1387,8 @@ static int s32k1xx_ifup_action(struct net_driver_s *dev, bool resetphy)
/* Clear all pending ENET interrupt */
- putreg32(RX_INTERRUPTS | ERROR_INTERRUPTS | TX_INTERRUPTS, S32K1XX_ENET_EIR);
+ putreg32(RX_INTERRUPTS | ERROR_INTERRUPTS | TX_INTERRUPTS,
+ S32K1XX_ENET_EIR);
/* Enable RX and error interrupts at the controller (TX interrupts are
* still disabled).
@@ -1388,7 +1404,8 @@ static int s32k1xx_ifup_action(struct net_driver_s *dev, bool resetphy)
#if 0
up_enable_irq(S32K1XX_IRQ_EMACTMR);
#endif
- up_enable_irq(S32K1XX_IRQ_ENET);
+ up_enable_irq(S32K1XX_IRQ_ENET_TXDONE);
+ up_enable_irq(S32K1XX_IRQ_ENET_RXDONE);
return OK;
}
@@ -1447,7 +1464,8 @@ static int s32k1xx_ifdown(struct net_driver_s *dev)
flags = enter_critical_section();
- up_disable_irq(S32K1XX_IRQ_ENET);
+ up_disable_irq(S32K1XX_IRQ_ENET_TXDONE);
+ up_disable_irq(S32K1XX_IRQ_ENET_RXDONE);
putreg32(0, S32K1XX_ENET_EIMR);
/* Cancel the TX poll timer and TX timeout timers */
@@ -1550,6 +1568,7 @@ static int s32k1xx_txavail(struct net_driver_s *dev)
return OK;
}
+
/****************************************************************************
* Function: s32k1xx_calcethcrc
*
@@ -1597,7 +1616,7 @@ static uint32_t s32k1xx_calcethcrc(const uint8_t *data, size_t length)
}
return crc;
- }
+}
#endif
/****************************************************************************
@@ -1747,7 +1766,8 @@ static int s32k1xx_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac)
****************************************************************************/
#ifdef CONFIG_NETDEV_IOCTL
-static int s32k1xx_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
+static int s32k1xx_ioctl(struct net_driver_s *dev, int cmd,
+ unsigned long arg)
{
#ifdef CONFIG_NETDEV_PHY_IOCTL
FAR struct s32k1xx_driver_s *priv =
@@ -1788,7 +1808,8 @@ static int s32k1xx_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
{
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
- ret = s32k1xx_readmii(priv, req->phy_id, req->reg_num, &req->val_out);
+ ret =
+ s32k1xx_readmii(priv, req->phy_id, req->reg_num, &req->val_out);
}
break;
@@ -1796,7 +1817,8 @@ static int s32k1xx_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg)
{
struct mii_ioctl_data_s *req =
(struct mii_ioctl_data_s *)((uintptr_t)arg);
- ret = s32k1xx_writemii(priv, req->phy_id, req->reg_num, req->val_in);
+ ret =
+ s32k1xx_writemii(priv, req->phy_id, req->reg_num, req->val_in);
}
break;
#endif /* CONFIG_NETDEV_PHY_IOCTL */
@@ -1880,8 +1902,7 @@ static void s32k1xx_initmii(struct s32k1xx_driver_s *priv)
* clock. This hold time value may need to be increased on some platforms
*/
- putreg32(ENET_MSCR_HOLDTIME_2CYCLES |
- S32K1XX_MII_SPEED << ENET_MSCR_MII_SPEED_SHIFT,
+ putreg32(S32K1XX_MII_SPEED << ENET_MSCR_MII_SPEED_SHIFT,
S32K1XX_ENET_MSCR);
}
@@ -2025,7 +2046,8 @@ static int s32k1xx_readmii(struct s32k1xx_driver_s *priv, uint8_t phyaddr,
*
****************************************************************************/
-static inline int s32k1xx_initphy(struct s32k1xx_driver_s *priv, bool renogphy)
+static inline int s32k1xx_initphy(struct s32k1xx_driver_s *priv,
+ bool renogphy)
{
uint32_t rcr;
uint32_t tcr;
@@ -2037,9 +2059,10 @@ static inline int s32k1xx_initphy(struct s32k1xx_driver_s *priv, bool renogphy)
if (renogphy)
{
- /* Loop (potentially infinitely?) until we successfully communicate with
- * the PHY. This is 'standard stuff' that should work for any PHY - we
- * are not communicating with it's 'special' registers at this point.
+ /* Loop (potentially infinitely?) until we successfully communicate
+ * with the PHY. This is 'standard stuff' that should work for any PHY
+ * - we are not communicating with it's 'special' registers at this
+ * point.
*/
ninfo("%s: Try phyaddr: %u\n", BOARD_PHY_NAME, phyaddr);
@@ -2061,7 +2084,8 @@ static inline int s32k1xx_initphy(struct s32k1xx_driver_s *priv, bool renogphy)
if (retries >= 3)
{
- nerr("ERROR: Failed to read %s PHYID1 at address %d\n", BOARD_PHY_NAME, phyaddr);
+ nerr("ERROR: Failed to read %s PHYID1 at address %d\n",
+ BOARD_PHY_NAME, phyaddr);
return -ENOENT;
}
@@ -2145,15 +2169,15 @@ static inline int s32k1xx_initphy(struct s32k1xx_driver_s *priv, bool renogphy)
#elif defined (CONFIG_ETH0_PHY_LAN8720)
- /* Make sure that PHY comes up in correct mode when it's reset */
+ /* Make sure that PHY comes up in correct mode when it's reset */
- s32k1xx_writemii(priv, phyaddr, MII_LAN8720_MODES,
- MII_LAN8720_MODES_RESV | MII_LAN8720_MODES_ALL |
- MII_LAN8720_MODES_PHYAD(BOARD_PHY_ADDR));
+ s32k1xx_writemii(priv, phyaddr, MII_LAN8720_MODES,
+ MII_LAN8720_MODES_RESV | MII_LAN8720_MODES_ALL |
+ MII_LAN8720_MODES_PHYAD(BOARD_PHY_ADDR));
- /* ...and reset PHY */
+ /* ...and reset PHY */
- s32k1xx_writemii(priv, phyaddr, MII_MCR, MII_MCR_RESET);
+ s32k1xx_writemii(priv, phyaddr, MII_MCR, MII_MCR_RESET);
#endif
/* Start auto negotiation */
@@ -2227,17 +2251,17 @@ static inline int s32k1xx_initphy(struct s32k1xx_driver_s *priv, bool renogphy)
{
if (renogphy == false)
{
- /* Give things one more chance with renegociation turned on */
+ /* Give things one more chance with renegociation turned on */
return s32k1xx_initphy(priv, true);
}
else
{
- /* That didn't end well, just give up */
+ /* That didn't end well, just give up */
- nerr("ERROR: Failed to read %s BOARD_PHY_STATUS[%02x]: %d\n",
- BOARD_PHY_NAME, BOARD_PHY_STATUS, ret);
- return ret;
+ nerr("ERROR: Failed to read %s BOARD_PHY_STATUS[%02x]: %d\n",
+ BOARD_PHY_NAME, BOARD_PHY_STATUS, ret);
+ return ret;
}
}
@@ -2261,12 +2285,12 @@ static inline int s32k1xx_initphy(struct s32k1xx_driver_s *priv, bool renogphy)
putreg32(rcr, S32K1XX_ENET_RCR);
putreg32(tcr, S32K1XX_ENET_TCR);
- /* Enable Discard Of Frames With MAC Layer Errors.
+ /* Do not Discard Of Frames With MAC Layer Errors.
* Enable Discard Of Frames With Wrong Protocol Checksum.
* Bit 1: Enable discard of frames with wrong IPv4 header checksum.
*/
- racc = ENET_RACC_PRODIS | ENET_RACC_LINEDIS | ENET_RACC_IPDIS;
+ racc = ENET_RACC_PRODIS | ENET_RACC_IPDIS;
putreg32(racc, S32K1XX_ENET_RACC);
/* Setup half or full duplex */
@@ -2308,6 +2332,45 @@ static inline int s32k1xx_initphy(struct s32k1xx_driver_s *priv, bool renogphy)
return -EIO;
}
+#if defined(CONFIG_ETH0_PHY_TJA1101)
+/* The NXP TJA110X PHY is an automotive 100BASE-T1 PHY
+ * Which requires additional initialization
+ */
+
+ /* select mode TJA110X */
+
+ s32k1xx_writemii(priv, phyaddr, MII_TJA110X_EXT_CNTRL,
+ (MII_EXT_CNTRL_NORMAL | MII_EXT_CNTRL_CONFIG_EN |
+ MII_EXT_CNTRL_CONFIG_INH));
+
+# if defined(CONFIG_PHY_100BASE_T1_MASTER)
+ /* Set TJA110X in master mode */
+
+ s32k1xx_writemii(priv, phyaddr, MII_TJA110X_CONFIG1,
+ (MII_CONFIG1_MASTER | MII_CONFIG1_TX_1250MV |
+ MII_CONFIG1_RMII_25MHZ | MII_CONFIG1_LED_EN));
+# else
+ /* Set TJA110X in slave mode */
+
+ s32k1xx_writemii(priv, phyaddr, MII_TJA110X_CONFIG1,
+ (MII_CONFIG1_TX_1250MV | MII_CONFIG1_RMII_25MHZ |
+ MII_CONFIG1_LED_EN));
+# endif
+
+ s32k1xx_writemii(priv, phyaddr, MII_TJA110X_CONFIG2,
+ (MII_CONFIG2_SNR_AV64 | MII_CONFIG2_WLIM_D |
+ MII_CONFIG2_SNR_F_NL | MII_CONFIG2_SLP_T_1));
+
+ /* Select normal mode TJA110X */
+
+ s32k1xx_writemii(priv, phyaddr, MII_TJA110X_EXT_CNTRL,
+ (MII_EXT_CNTRL_NORMAL | MII_EXT_CNTRL_CONFIG_INH));
+
+ s32k1xx_writemii(priv, phyaddr, MII_TJA110X_EXT_CNTRL,
+ (MII_EXT_CNTRL_LINK_CNTRL | MII_EXT_CNTRL_NORMAL |
+ MII_EXT_CNTRL_CONFIG_INH));
+#endif
+
putreg32(rcr, S32K1XX_ENET_RCR);
putreg32(tcr, S32K1XX_ENET_TCR);
return OK;
@@ -2453,7 +2516,6 @@ int s32k1xx_netinitialize(int intf)
uint32_t uidml;
uint8_t *mac;
#endif
- uint32_t regval;
int ret;
/* Get the interface structure associated with this interface number. */
@@ -2471,11 +2533,12 @@ int s32k1xx_netinitialize(int intf)
s32k1xx_pinconfig(PIN_RMII_MDIO);
s32k1xx_pinconfig(PIN_RMII_RX_DV);
s32k1xx_pinconfig(PIN_RMII_RX_ER);
- s32k1xx_pinconfig(PIN_RMII_RX_EN);
- s32k1xx_pinconfig(PIN_RMII_RXD);
+ s32k1xx_pinconfig(PIN_RMII_RXD0);
+ s32k1xx_pinconfig(PIN_RMII_RXD1);
s32k1xx_pinconfig(PIN_RMII_TX_CLK);
s32k1xx_pinconfig(PIN_RMII_TX_EN);
- s32k1xx_pinconfig(PIN_RMII_TXD);
+ s32k1xx_pinconfig(PIN_RMII_TXD0);
+ s32k1xx_pinconfig(PIN_RMII_TXD1);
#if 0
/* Configure all ENET/MII pins */
@@ -2512,7 +2575,7 @@ int s32k1xx_netinitialize(int intf)
/* Attach the Ethernet interrupt handler */
- if (irq_attach(S32K1XX_IRQ_ENET, s32k1xx_enet_interrupt, NULL))
+ if (irq_attach(S32K1XX_IRQ_ENET_TXDONE, s32k1xx_enet_interrupt, NULL))
{
/* We could not attach the ISR to the interrupt */
@@ -2520,6 +2583,14 @@ int s32k1xx_netinitialize(int intf)
return -EAGAIN;
}
+ if (irq_attach(S32K1XX_IRQ_ENET_RXDONE, s32k1xx_enet_interrupt, NULL))
+ {
+ /* We could not attach the ISR to the interrupt */
+
+ nerr("ERROR: Failed to attach EMACRX IRQ\n");
+ return -EAGAIN;
+ }
+
/* Initialize the driver structure */
memset(priv, 0, sizeof(struct s32k1xx_driver_s));
@@ -2543,14 +2614,14 @@ int s32k1xx_netinitialize(int intf)
#ifdef CONFIG_NET_ETHERNET
/* Determine a semi-unique MAC address from MCU UID
* We use UID Low and Mid Low registers to get 64 bits, from which we keep
- * 48 bits. We then force unicast and locally administered bits (b0 and b1,
- * 1st octet)
+ * 48 bits. We then force unicast and locally administered bits (b0 and
+ * b1, 1st octet)
*/
/* hardcoded offset: todo: need proper header file */
- uidl = getreg32(S32K1XX_OCOTP_BASE + 0x410);
- uidml = getreg32(S32K1XX_OCOTP_BASE + 0x420);
+ uidl = getreg32(S32K1XX_SIM_BASE + 0x60);
+ uidml = getreg32(S32K1XX_SIM_BASE + 0x5c);
mac = priv->dev.d_mac.ether.ether_addr_octet;
uidml |= 0x00000200;
diff --git a/arch/arm/src/s32k1xx/s32k1xx_lpi2c.c b/arch/arm/src/s32k1xx/s32k1xx_lpi2c.c
index 1356972..d7fca33 100644
--- a/arch/arm/src/s32k1xx/s32k1xx_lpi2c.c
+++ b/arch/arm/src/s32k1xx/s32k1xx_lpi2c.c
@@ -893,7 +893,7 @@ static void s32k1xx_lpi2c_tracedump(FAR struct s32k1xx_lpi2c_priv_s *priv)
}
#endif /* CONFIG_I2C_TRACE */
-/************************************************************************************
+/****************************************************************************
* Name: s32k1xx_lpi2c_pckfreq
*
* Description:
@@ -903,9 +903,10 @@ static void s32k1xx_lpi2c_tracedump(FAR struct s32k1xx_lpi2c_priv_s *priv)
* base - The base address of the LPI2C peripheral registers
*
* Returned Value:
- * The frequency of the LPI2C functional input frequency (or zero on a failure)
+ * The frequency of the LPI2C functional input frequency (or zero on a
+ * failure)
*
- ************************************************************************************/
+ ****************************************************************************/
static uint32_t s32k1xx_lpi2c_pckfreq(uintptr_t base)
{
@@ -1062,7 +1063,8 @@ static void s32k1xx_lpi2c_setclock(FAR struct s32k1xx_lpi2c_priv_s *priv,
}
}
- s32k1xx_lpi2c_modifyreg(priv, S32K1XX_LPI2C_MCFGR1_OFFSET, 0,
+ s32k1xx_lpi2c_modifyreg(priv, S32K1XX_LPI2C_MCFGR1_OFFSET,
+ LPI2C_MCFGR1_PRESCALE_MASK,
LPI2C_MCFGR1_PRESCALE(best_prescale));
/* Re-enable LPI2C if it was enabled previously */
@@ -1173,11 +1175,17 @@ static int s32k1xx_lpi2c_isr_process(struct s32k1xx_lpi2c_priv_s *priv)
s32k1xx_lpi2c_tracenew(priv, status);
- /* Continue with either sending or reading data */
+ /* After an error we can get an SDF */
+
+ if (priv->intstate == INTSTATE_DONE && (status & LPI2C_MSR_SDF) != 0)
+ {
+ s32k1xx_lpi2c_traceevent(priv, I2CEVENT_STOP, 0);
+ s32k1xx_lpi2c_putreg(priv, S32K1XX_LPI2C_MSR_OFFSET, LPI2C_MSR_SDF);
+ }
/* Check if there is more bytes to send */
- if (((priv->flags & I2C_M_READ) == 0) && (status & LPI2C_MSR_TDF) != 0)
+ else if (((priv->flags & I2C_M_READ) == 0) && (status & LPI2C_MSR_TDF) != 0)
{
if (priv->dcnt > 0)
{
@@ -1242,7 +1250,8 @@ static int s32k1xx_lpi2c_isr_process(struct s32k1xx_lpi2c_priv_s *priv)
if ((priv->msgv->flags & I2C_M_NOSTART) == 0)
{
- s32k1xx_lpi2c_traceevent(priv, I2CEVENT_STARTRESTART, priv->msgc);
+ s32k1xx_lpi2c_traceevent(priv, I2CEVENT_STARTRESTART,
+ priv->msgc);
s32k1xx_lpi2c_sendstart(priv, priv->msgv->addr);
}
else
@@ -1285,13 +1294,18 @@ static int s32k1xx_lpi2c_isr_process(struct s32k1xx_lpi2c_priv_s *priv)
else if (priv->msgv && ((status & LPI2C_MSR_SDF) != 0))
{
s32k1xx_lpi2c_traceevent(priv, I2CEVENT_STOP, 0);
- s32k1xx_lpi2c_putreg(priv, S32K1XX_LPI2C_MSR_OFFSET, LPI2C_MSR_SDF);
+ s32k1xx_lpi2c_putreg(priv, S32K1XX_LPI2C_MSR_OFFSET,
+ LPI2C_MSR_SDF);
/* Check is there thread waiting for this event (there should be) */
#ifndef CONFIG_I2C_POLLED
if (priv->intstate == INTSTATE_WAITING)
{
+ /* Update Status once at the end */
+
+ priv->status = status;
+
/* inform the thread that transfer is complete
* and wake it up
*/
@@ -1300,6 +1314,7 @@ static int s32k1xx_lpi2c_isr_process(struct s32k1xx_lpi2c_priv_s *priv)
priv->intstate = INTSTATE_DONE;
}
#else
+ priv->status = status;
priv->intstate = INTSTATE_DONE;
#endif
/* Mark that this transaction stopped */
@@ -1340,6 +1355,10 @@ static int s32k1xx_lpi2c_isr_process(struct s32k1xx_lpi2c_priv_s *priv)
#ifndef CONFIG_I2C_POLLED
if (priv->intstate == INTSTATE_WAITING)
{
+ /* Update Status once at the end */
+
+ priv->status = status;
+
/* inform the thread that transfer is complete
* and wake it up
*/
@@ -1348,11 +1367,11 @@ static int s32k1xx_lpi2c_isr_process(struct s32k1xx_lpi2c_priv_s *priv)
priv->intstate = INTSTATE_DONE;
}
#else
+ priv->status = status;
priv->intstate = INTSTATE_DONE;
#endif
}
- priv->status = status;
return OK;
}
@@ -1386,8 +1405,8 @@ static int s32k1xx_lpi2c_init(FAR struct s32k1xx_lpi2c_priv_s *priv)
{
/* Power-up and configure GPIOs .
*
- * NOTE: Clocking to the LPSPI peripheral must be provided by board-specific logic
- * as part of the clock configuration logic.
+ * NOTE: Clocking to the LPSPI peripheral must be provided by
+ * board-specific logic as part of the clock configuration logic.
*/
/* Configure pins */
@@ -1746,13 +1765,13 @@ FAR struct i2c_master_s *s32k1xx_i2cbus_initialize(int port)
switch (port)
{
#ifdef CONFIG_S32K1XX_LPI2C0
- case 1:
+ case 0:
priv = (struct s32k1xx_lpi2c_priv_s *)&s32k1xx_lpi2c0_priv;
break;
#endif
#ifdef CONFIG_S32K1XX_LPI2C1
- case 2:
+ case 1:
priv = (struct s32k1xx_lpi2c_priv_s *)&s32k1xx_lpi2c1_priv;
break;
#endif
diff --git a/arch/arm/src/s32k1xx/s32k1xx_lpspi.c b/arch/arm/src/s32k1xx/s32k1xx_lpspi.c
index f9e7d1e..5fad2a6 100644
--- a/arch/arm/src/s32k1xx/s32k1xx_lpspi.c
+++ b/arch/arm/src/s32k1xx/s32k1xx_lpspi.c
@@ -35,23 +35,23 @@
************************************************************************************/
/************************************************************************************
- * The external functions, s32k1xx_lpspi1/2/3/4select and s32k1xx_lpspi1/2/3/4status
+ * The external functions, s32k1xx_lpspi0/1/2select and s32k1xx_lpspi0/1/2status
* must be provided by board-specific logic. They are implementations of the select
* and status methods of the SPI interface defined by struct s32k1xx_lpspi_ops_s (see
- * include/nuttx/spi/spi.h). All other methods (including s32k1xx_lpspibus_initialize())
- * are provided by common S32K1XX logic. To use this common SPI logic on your
- * board:
+ * include/nuttx/spi/spi.h). All other methods (including
+ * s32k1xx_lpspibus_initialize()) are provided by common S32K1XX logic. To use this
+ * common SPI logic on your board:
*
* 1. Provide logic in s32k1xx_boardinitialize() to configure SPI chip select
* pins.
- * 2. Provide s32k1xx_lpspi1/2/3/4select() and s32k1xx_lpspi1/2/3/4status()
+ * 2. Provide s32k1xx_lpspi0/1/2select() and s32k1xx_lpspi0/1/2status()
* functions in your board-specific logic. These functions will perform chip
* selection and status operations using GPIOs in the way your board is
* configured.
* 3. Add a calls to s32k1xx_lpspibus_initialize() in your low level application
* initialization logic
- * 4. The handle returned by s32k1xx_lpspibus_initialize() may then be used to bind the
- * SPI driver to higher level logic (e.g., calling
+ * 4. The handle returned by s32k1xx_lpspibus_initialize() may then be used to bind
+ * the SPI driver to higher level logic (e.g., calling
* mmcsd_lpspislotinitialize(), for example, will bind the SPI driver to
* the SPI MMC/SD driver).
*
@@ -89,7 +89,8 @@
#include <arch/board/board.h>
-#ifdef CONFIG_S32K1XX_LPSPI
+#if defined(CONFIG_S32K1XX_LPSPI0) || defined(CONFIG_S32K1XX_LPSPI1) || \
+ defined(CONFIG_S32K1XX_LPSPI2)
/************************************************************************************
* Pre-processor Definitions
@@ -952,8 +953,7 @@ static uint32_t s32k1xx_lpspi_setfrequency(FAR struct spi_dev_s *dev,
s32k1xx_lpspi_putreg32(priv, S32K1XX_LPSPI_CCR_OFFSET, regval);
s32k1xx_lpspi_modifyreg32(priv, S32K1XX_LPSPI_TCR_OFFSET,
- LPSPI_TCR_PRESCALE_MASK, 0);
- s32k1xx_lpspi_modifyreg32(priv, S32K1XX_LPSPI_TCR_OFFSET, 0,
+ LPSPI_TCR_PRESCALE_MASK,
LPSPI_TCR_PRESCALE(best_prescaler));
priv->frequency = frequency;
@@ -970,7 +970,8 @@ static uint32_t s32k1xx_lpspi_setfrequency(FAR struct spi_dev_s *dev,
if (men)
{
- s32k1xx_lpspi_modifyreg32(priv, S32K1XX_LPSPI_CR_OFFSET, 0, LPSPI_CR_MEN);
+ s32k1xx_lpspi_modifyreg32(priv, S32K1XX_LPSPI_CR_OFFSET, 0,
+ LPSPI_CR_MEN);
}
}
@@ -1090,7 +1091,6 @@ static void s32k1xx_lpspi_setbits(FAR struct spi_dev_s *dev, int nbits)
if (nbits != priv->nbits)
{
-
if (nbits < 2 || nbits > 4096)
{
return;
@@ -1124,7 +1124,7 @@ static void s32k1xx_lpspi_setbits(FAR struct spi_dev_s *dev, int nbits)
}
}
-/****************************************************************************
+/************************************************************************************
* Name: s32k1xx_lpspi_hwfeatures
*
* Description:
@@ -1138,7 +1138,7 @@ static void s32k1xx_lpspi_setbits(FAR struct spi_dev_s *dev, int nbits)
* Zero (OK) if the selected H/W features are enabled; A negated errno
* value if any H/W feature is not supportable.
*
- ****************************************************************************/
+ ************************************************************************************/
#ifdef CONFIG_SPI_HWFEATURES
static int s32k1xx_lpspi_hwfeatures(FAR struct spi_dev_s *dev,
@@ -1232,7 +1232,8 @@ static uint16_t s32k1xx_lpspi_send(FAR struct spi_dev_s *dev, uint16_t wd)
* nwords - the length of data to be exchaned in units of words.
* The wordsize is determined by the number of bits-per-word
* selected for the SPI interface. If nbits <= 8, the data is
- * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
+ * packed into uint8_t's; if nbits >8, the data is packed into
+ * uint16_t's
*
* Returned Value:
* None
@@ -1326,7 +1327,7 @@ static void s32k1xx_lpspi_exchange_nodma(FAR struct spi_dev_s *dev,
}
#endif /* !CONFIG_S32K1XX_LPSPI_DMA || CONFIG_S32K1XX_DMACAPABLE */
-/****************************************************************************
+/************************************************************************************
* Name: s32k1xx_lpspi_sndblock
*
* Description:
@@ -1338,7 +1339,8 @@ static void s32k1xx_lpspi_exchange_nodma(FAR struct spi_dev_s *dev,
* nwords - the length of data to send from the buffer in number of words.
* The wordsize is determined by the number of bits-per-word
* selected for the SPI interface. If nbits <= 8, the data is
- * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
+ * packed into uint8_t's; if nbits >8, the data is packed into
+ * uint16_t's
*
* Returned Value:
* None
@@ -1366,7 +1368,8 @@ static void s32k1xx_lpspi_sndblock(FAR struct spi_dev_s *dev,
* nwords - the length of data that can be received in the buffer in number
* of words. The wordsize is determined by the number of bits-per-word
* selected for the SPI interface. If nbits <= 8, the data is
- * packed into uint8_t's; if nbits >8, the data is packed into uint16_t's
+ * packed into uint8_t's; if nbits >8, the data is packed into
+ * uint16_t's
*
* Returned Value:
* None
@@ -1386,7 +1389,8 @@ static void s32k1xx_lpspi_recvblock(FAR struct spi_dev_s *dev, FAR void *rxbuffe
* Name: s32k1xx_lpspi_bus_initialize
*
* Description:
- * Initialize the selected SPI bus in its default state (Master, 8-bit, mode 0, etc.)
+ * Initialize the selected SPI bus in its default state (Master, 8-bit, mode 0,
+ * etc.)
*
* Input Parameters:
* priv - private SPI device structure
@@ -1417,6 +1421,7 @@ static void s32k1xx_lpspi_bus_initialize(struct s32k1xx_lpspidev_s *priv)
LPSPI_CFGR1_MASTER);
/* Set specific PCS to active high or low */
+
/* TODO: Not needed for now */
/* Set Configuration Register 1 related setting. */
@@ -1556,4 +1561,4 @@ FAR struct spi_dev_s *s32k1xx_lpspibus_initialize(int bus)
return (FAR struct spi_dev_s *)priv;
}
-#endif /* CONFIG_S32K1XX_LPSPI */
+#endif /* CONFIG_S32K1XX_LPSPI0 || CONFIG_S32K1XX_LPSPI1 || CONFIG_S32K1XX_LPSPI2 */
diff --git a/arch/arm/src/s32k1xx/s32k1xx_pin.h b/arch/arm/src/s32k1xx/s32k1xx_pin.h
index 4971363..ac41b13 100644
--- a/arch/arm/src/s32k1xx/s32k1xx_pin.h
+++ b/arch/arm/src/s32k1xx/s32k1xx_pin.h
@@ -1,5 +1,5 @@
/************************************************************************************
- * arch/arm/src/s32k1xx/s32k1xx.h
+ * arch/arm/src/s32k1xx/s32k1xx_pin.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gn...@nuttx.org>
@@ -57,6 +57,7 @@
************************************************************************************/
/* Bit-encoded input to s32k1xx_pinconfig() *****************************************/
+
/* General form (32-bits, only 22 bits are unused in the encoding):
*
* oooo mmmv iiii ifd- ---- -ppp ---b bbbb
@@ -75,7 +76,9 @@
#define _PIN_OPTIONS_MASK (15 << _PIN_OPTIONS_SHIFT)
/* Port Modes */
- /* Unshifted versions: */
+
+/* Unshifted versions: */
+
#define PIN_MODE_ANALOG (0) /* 000 Pin Disabled (Analog) */
#define PIN_MODE_ALT1 (1) /* 001 Alternative 1 */
#define PIN_MODE_GPIO PIN_MODE_ALT1 /* 001 Alternative 1 (GPIO) */
@@ -85,7 +88,9 @@
#define PIN_MODE_ALT5 (5) /* 101 Alternative 5 */
#define PIN_MODE_ALT6 (6) /* 110 Alternative 6 */
#define PIN_MODE_ALT7 (7) /* 111 Alternative 7 */
- /* Shifted versions: */
+
+/* Shifted versions: */
+
#define _PIN_MODE_ANALOG (0 << _PIN_MODE_SHIFT) /* 000 Pin Disabled (Analog) */
#define _PIN_MODE_ALT1 (1 << _PIN_MODE_SHIFT) /* 001 Alternative 1 */
#define _PIN_MODE_GPIO (1 << _PIN_MODE_SHIFT) /* 001 Alternative 1 (GPIO) */
diff --git a/arch/arm/src/s32k1xx/s32k1xx_pinirq.c b/arch/arm/src/s32k1xx/s32k1xx_pinirq.c
index db990bd..74b3ef7 100644
--- a/arch/arm/src/s32k1xx/s32k1xx_pinirq.c
+++ b/arch/arm/src/s32k1xx/s32k1xx_pinirq.c
@@ -50,7 +50,7 @@
#include "up_arch.h"
#include "up_internal.h"
-#include "s32k1xx.h"
+#include "s32k1xx_pin.h"
#include "hardware/s32k1xx_port.h"
#ifdef CONFIG_S32K1XX_GPIOIRQ
@@ -86,6 +86,7 @@ struct s32k1xx_pinirq_s
/****************************************************************************
* Private Data
****************************************************************************/
+
/* Per pin port interrupt vectors. NOTE: Not all pins in each port
* correspond to externally available GPIOs. However, I believe that the
* Kinesis will support interrupts even if the pin is not available as
@@ -123,7 +124,8 @@ static struct s32k1xx_pinirq_s g_porteisrs[32];
#ifdef HAVE_PORTINTS
static int s32k1xx_portinterrupt(int irq, FAR void *context,
- uintptr_t addr, struct s32k1xx_pinirq_s *isrtab)
+ uintptr_t addr,
+ struct s32k1xx_pinirq_s *isrtab)
{
uint32_t isfr = getreg32(addr);
int i;
@@ -184,31 +186,40 @@ static int s32k1xx_portinterrupt(int irq, FAR void *context,
#ifdef CONFIG_S32K1XX_PORTAINTS
static int s32k1xx_portainterrupt(int irq, FAR void *context, FAR void *arg)
{
- return s32k1xx_portinterrupt(irq, context, S32K1XX_PORTA_ISFR, g_portaisrs);
+ return s32k1xx_portinterrupt(irq, context, S32K1XX_PORTA_ISFR,
+ g_portaisrs);
}
#endif
+
#ifdef CONFIG_S32K1XX_PORTBINTS
static int s32k1xx_portbinterrupt(int irq, FAR void *context, FAR void *arg)
{
- return s32k1xx_portinterrupt(irq, context, S32K1XX_PORTB_ISFR, g_portbisrs);
+ return s32k1xx_portinterrupt(irq, context, S32K1XX_PORTB_ISFR,
+ g_portbisrs);
}
#endif
+
#ifdef CONFIG_S32K1XX_PORTCINTS
static int s32k1xx_portcinterrupt(int irq, FAR void *context, FAR void *arg)
{
- return s32k1xx_portinterrupt(irq, context, S32K1XX_PORTC_ISFR, g_portcisrs);
+ return s32k1xx_portinterrupt(irq, context, S32K1XX_PORTC_ISFR,
+ g_portcisrs);
}
#endif
+
#ifdef CONFIG_S32K1XX_PORTDINTS
static int s32k1xx_portdinterrupt(int irq, FAR void *context, FAR void *arg)
{
- return s32k1xx_portinterrupt(irq, context, S32K1XX_PORTD_ISFR, g_portdisrs);
+ return s32k1xx_portinterrupt(irq, context, S32K1XX_PORTD_ISFR,
+ g_portdisrs);
}
#endif
+
#ifdef CONFIG_S32K1XX_PORTEINTS
static int s32k1xx_porteinterrupt(int irq, FAR void *context, FAR void *arg)
{
- return s32k1xx_portinterrupt(irq, context, S32K1XX_PORTE_ISFR, g_porteisrs);
+ return s32k1xx_portinterrupt(irq, context, S32K1XX_PORTE_ISFR,
+ g_porteisrs);
}
#endif
@@ -276,7 +287,7 @@ void s32k1xx_pinirq_initialize(void)
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure to indicate the nature of the failure.
*
- *******************************************************************************/
+ ****************************************************************************/
int s32k1xx_pinirqattach(uint32_t pinset, xcpt_t pinisr, void *arg)
{
@@ -286,8 +297,8 @@ int s32k1xx_pinirqattach(uint32_t pinset, xcpt_t pinisr, void *arg)
unsigned int port;
unsigned int pin;
- /* It only makes sense to call this function for input pins that are configured
- * as interrupts.
+ /* It only makes sense to call this function for input pins that are
+ * configured as interrupts.
*/
DEBUGASSERT((pinset & _PIN_INTDMA_MASK) == _PIN_INTERRUPT);
@@ -334,27 +345,27 @@ int s32k1xx_pinirqattach(uint32_t pinset, xcpt_t pinisr, void *arg)
return -EINVAL;
}
- /* Get the old PIN ISR and set the new PIN ISR */
+ /* Get the old PIN ISR and set the new PIN ISR */
- isrtab[pin].handler = pinisr;
- isrtab[pin].arg = arg;
+ isrtab[pin].handler = pinisr;
+ isrtab[pin].arg = arg;
- /* And return the old PIN isr address */
+ /* And return the old PIN isr address */
- leave_critical_section(flags);
- return OK;
+ leave_critical_section(flags);
+ return OK;
#else
- return -ENOSYS;
+ return -ENOSYS;
#endif /* HAVE_PORTINTS */
}
-/************************************************************************************
+/****************************************************************************
* Name: s32k1xx_pinirqenable
*
* Description:
* Enable the interrupt for specified pin IRQ
*
- ************************************************************************************/
+ ****************************************************************************/
void s32k1xx_pinirqenable(uint32_t pinset)
{
@@ -426,13 +437,13 @@ void s32k1xx_pinirqenable(uint32_t pinset)
#endif /* HAVE_PORTINTS */
}
-/************************************************************************************
+/****************************************************************************
* Name: s32k1xx_pinirqdisable
*
* Description:
* Disable the interrupt for specified pin
*
- ************************************************************************************/
+ ****************************************************************************/
void s32k1xx_pinirqdisable(uint32_t pinset)
{
diff --git a/arch/arm/src/s32k1xx/s32k1xx_rtc.c b/arch/arm/src/s32k1xx/s32k1xx_rtc.c
new file mode 100644
index 0000000..1bc1dc99
--- /dev/null
+++ b/arch/arm/src/s32k1xx/s32k1xx_rtc.c
@@ -0,0 +1,267 @@
+/****************************************************************************
+ * arch/arm/src/s32k1xx/s32k1xx_rtc.c
+ *
+ * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/timers/rtc.h>
+
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+
+#include "hardware/s32k1xx_rtc.h"
+#include "s32k1xx_periphclocks.h"
+#include "s32k1xx_rtc.h"
+
+#ifdef CONFIG_S32K1XX_RTC
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* Variable determines the state of the RTC module.
+ *
+ * After initialization value is set to 'true' if RTC starts successfully.
+ * The value can be changed to false also during operation if RTC for
+ * some reason fails.
+ */
+
+volatile bool g_rtc_enabled = false;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: s32k1xx_rtc_enable
+ *
+ * Description:
+ * Enable/start the LPRTC time counter.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void s32k1xx_rtc_enable(void)
+{
+ uint32_t regval;
+
+ /* Enable the rtc */
+
+ regval = getreg32(S32K1XX_RTC_SR);
+ regval |= RTC_SR_TCE;
+ putreg32(regval, S32K1XX_RTC_SR);
+}
+
+/****************************************************************************
+ * Name: s32k1xx_rtc_disable
+ *
+ * Description:
+ * disable the LPRTC time counter.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void s32k1xx_rtc_disable(void)
+{
+ uint32_t regval;
+
+ /* Enable the rtc */
+
+ regval = getreg32(S32K1XX_RTC_SR);
+ regval &= ~RTC_SR_TCE;
+ putreg32(regval, S32K1XX_RTC_SR);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_rtc_initialize
+ *
+ * Description:
+ * Initialize the rtc per the selected configuration.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * Zero (OK) on success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+int up_rtc_initialize(void)
+{
+ uint32_t regval;
+
+ /* Disable the clock out pin */
+
+ regval = getreg32(S32K1XX_RTC_CR);
+
+ regval &= ~RTC_CR_CPE;
+
+ putreg32(regval, S32K1XX_RTC_CR);
+
+ /* Set LPO_1KHZ clock source */
+
+ regval = getreg32(S32K1XX_RTC_CR);
+
+ regval |= RTC_CR_LPOS;
+
+ putreg32(regval, S32K1XX_RTC_CR);
+
+ /* Set Update mode */
+
+ regval = getreg32(S32K1XX_RTC_CR);
+
+ regval &= ~(RTC_CR_UM);
+
+ putreg32(regval, S32K1XX_RTC_CR);
+
+ /* Set Non-Supervisor access mode */
+
+ regval = getreg32(S32K1XX_RTC_CR);
+
+ regval &= ~(RTC_CR_SUP);
+
+ putreg32(regval, S32K1XX_RTC_CR);
+
+ /* Enable the rtc */
+
+ s32k1xx_rtc_enable();
+
+ g_rtc_enabled = true;
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: up_rtc_time
+ *
+ * Description:
+ * Get the current time in seconds. This is similar to the standard time()
+ * function. This interface is only required if the low-resolution
+ * RTC/counter hardware implementation selected. It is only used by the
+ * RTOS during initialization to set up the system time when CONFIG_RTC is
+ * set but neither CONFIG_RTC_HIRES nor CONFIG_RTC_DATETIME are set.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * The current time in seconds
+ *
+ ****************************************************************************/
+
+time_t up_rtc_time(void)
+{
+ uint32_t regval;
+
+ regval = getreg32(S32K1XX_RTC_TSR);
+ regval &= RTC_TSR_MASK;
+
+ return (uint32_t) (regval);
+}
+
+/****************************************************************************
+ * Name: up_rtc_settime
+ *
+ * Description:
+ * Set the RTC to the provided time. All RTC implementations must be able
+ * to set their time based on a standard timespec.
+ *
+ * Input Parameters:
+ * tp - the time to use
+ *
+ * Returned Value:
+ * Zero (OK) on success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+int up_rtc_settime(FAR const struct timespec *ts)
+{
+ DEBUGASSERT(ts != NULL);
+
+ s32k1xx_rtc_disable();
+
+ putreg32((uint32_t)ts->tv_sec, S32K1XX_RTC_TSR);
+
+ s32k1xx_rtc_enable();
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: s32k1xx_rtc_havesettime
+ *
+ * Description:
+ * Check if the rtc time has been set
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * Returns true if RTC date-time have been previously set.
+ *
+ ****************************************************************************/
+
+bool s32k1xx_rtc_havesettime(void)
+{
+ return 1; /* TODO */
+}
+#endif /* CONFIG_s32k1xx_SNVS_rtc */
diff --git a/arch/arm/src/s32k1xx/chip.h b/arch/arm/src/s32k1xx/s32k1xx_rtc.h
similarity index 58%
copy from arch/arm/src/s32k1xx/chip.h
copy to arch/arm/src/s32k1xx/s32k1xx_rtc.h
index f3f9b9c..b00c3d3 100644
--- a/arch/arm/src/s32k1xx/chip.h
+++ b/arch/arm/src/s32k1xx/s32k1xx_rtc.h
@@ -1,7 +1,7 @@
-/************************************************************************************
- * arch/arm/src/s32k1xx/chip.h
+/****************************************************************************
+ * arch/arm/src/s32k1xx/s32k1xx_rtc.h
*
- * Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -31,47 +31,91 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ************************************************************************************/
+ ****************************************************************************/
-#ifndef __ARCH_ARM_SRC_S32K1XX_CHIP_H
-#define __ARCH_ARM_SRC_S32K1XX_CHIP_H
-
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_s32k1xx_s32k1xx_rtc_H
+#define __ARCH_ARM_SRC_s32k1xx_s32k1xx_rtc_H
#include <nuttx/config.h>
-/* Include the memory map and the chip definitions file. Other chip hardware files
- * should then include this file for the proper setup.
- */
+#include "chip.h"
+
+#ifdef CONFIG_S32K1XX_RTC
-#include <arch/irq.h>
-#include "hardware/s32k1xx_memorymap.h"
+/****************************************************************************
+ * Preprocessor Definitions
+ ****************************************************************************/
-/* The common ARMv6/7-M vector handling logic expects the following definitions in
- * this file. ARMV6/7M_PERIPHERAL_INTERRUPTS provides the number of supported
- * external interrupts which, for this architecture, is provided in the
- * arch/s32k1xx/irq.h header file.
+# ifdef CONFIG_RTC_DATETIME
+# error CONFIG_RTC_DATETIME should not be selected with this driver
+# endif
+
+# ifdef CONFIG_RTC_PERIODIC
+# error CONFIG_RTC_PERIODIC should not be selected with this driver
+# endif
+
+/* REVISIT: This is probably supportable. The 47 bit timer does have
+ * accuracy greater than 1 second.
*/
-#define ARMV6M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT
-#define ARMV7M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT
+# ifdef CONFIG_RTC_HIRES
+# error CONFIG_RTC_PERIODIC should not be selected with this driver
+# endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
-/************************************************************************************
- * Public Types
- ************************************************************************************/
+/****************************************************************************
+ * Name: up_rtc_initialize
+ *
+ * Description:
+ * Initialize the rtc per the selected configuration.
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * Zero (OK) on success; a negated errno on failure
+ *
+ ****************************************************************************/
+
+int up_rtc_initialize(void);
-/************************************************************************************
- * Public Data
- ************************************************************************************/
+/****************************************************************************
+ * Name: s32k1xx_rtc_havesettime
+ *
+ * Description:
+ * Check if the rtc time has been set
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * Returns true if RTC date-time have been previously set.
+ *
+ ****************************************************************************/
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
+bool s32k1xx_rtc_havesettime(void);
-#endif /* __ARCH_ARM_SRC_S32K1XX_CHIP_H */
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_S32K1XX_RTC */
+#endif /* __ARCH_ARM_SRC_s32k1xx_s32k1xx_rtc_H */
diff --git a/arch/arm/src/s32k1xx/s32k1xx_start.c b/arch/arm/src/s32k1xx/s32k1xx_start.c
index 709b7b3..4ac0720 100644
--- a/arch/arm/src/s32k1xx/s32k1xx_start.c
+++ b/arch/arm/src/s32k1xx/s32k1xx_start.c
@@ -33,6 +33,10 @@
*
****************************************************************************/
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
#include <nuttx/config.h>
#include <stdint.h>
@@ -57,6 +61,9 @@
#include "s32k1xx_serial.h"
#include "s32k1xx_wdog.h"
#include "s32k1xx_start.h"
+#if defined(CONFIG_ARCH_USE_MPU) && defined(CONFIG_S32K1XX_ENET)
+#include "hardware/s32k1xx_mpu.h"
+#endif
/****************************************************************************
* Pre-processor Definitions
@@ -143,7 +150,8 @@ const uintptr_t g_idle_topstack = HEAP_BASE;
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
- * Software must not change the value of the ASPEN bit or LSPEN bit while either:
+ * Software must not change the value of the ASPEN bit or LSPEN bit while
+ * either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
@@ -253,7 +261,8 @@ static inline void s32k1xx_mpu_config(void)
*/
regval = (MPU_RGDAAC_M3UM_XACCESS | MPU_RGDAAC_M3UM_WACCESS |
- MPU_RGDAAC_M3UM_RACCESS | MPU_RGDAAC_M3SM_M3UM;
+ MPU_RGDAAC_M3UM_RACCESS | MPU_RGDAAC_M3SM_M3UM);
+
putreg32(regval, S32K1XX_MPU_RGDAAC(0));
}
#endif
@@ -330,11 +339,11 @@ void __start(void)
showprogress('C');
#if defined(CONFIG_ARCH_USE_MPU) && defined(CONFIG_S32K1XX_ENET)
+
/* Enable all MPU bus masters */
s32k1xx_mpu_config();
showprogress('D');
-}
#endif
/* Perform early serial initialization */
diff --git a/boards/Kconfig b/boards/Kconfig
index 552641e..b622863 100644
--- a/boards/Kconfig
+++ b/boards/Kconfig
@@ -1245,6 +1245,36 @@ config ARCH_BOARD_S32K118EVB
This options selects support for NuttX on the NXP S32K118EVB board
featuring the S32K118 Cortex-M0+.
+config ARCH_BOARD_S32K144EVB
+ bool "NXP S32K144EVB"
+ depends on ARCH_CHIP_S32K144
+ select ARCH_HAVE_LEDS
+ select ARCH_HAVE_BUTTONS
+ select ARCH_HAVE_IRQBUTTONS
+ ---help---
+ This options selects support for NuttX on the NXP S32K144EVB board
+ featuring the S32K144 Cortex-M4F.
+
+config ARCH_BOARD_RDDRONE_UAVCAN144
+ bool "NXP RDDRONE-UAVCAN144"
+ depends on ARCH_CHIP_S32K144
+ select ARCH_HAVE_LEDS
+ select ARCH_HAVE_BUTTONS
+ select ARCH_HAVE_IRQBUTTONS
+ ---help---
+ This options selects support for NuttX on the NXP RDDRONE-UAVCAN board
+ featuring the S32K144 Cortex-M4F.
+
+config ARCH_BOARD_RDDRONE_UAVCAN146
+ bool "NXP RDDRONE-UAVCAN146"
+ depends on ARCH_CHIP_S32K146
+ select ARCH_HAVE_LEDS
+ select ARCH_HAVE_BUTTONS
+ select ARCH_HAVE_IRQBUTTONS
+ ---help---
+ This options selects support for NuttX on the NXP RDDRONE-UAVCAN board
+ featuring the S32K146 Cortex-M4F.
+
config ARCH_BOARD_S32K146EVB
bool "NXP S32K146EVB"
depends on ARCH_CHIP_S32K146
@@ -2129,6 +2159,9 @@ config ARCH_BOARD
default "rx65n-rsk2mb" if ARCH_BOARD_RX65N_RSK2MB
default "rx65n-grrose" if ARCH_BOARD_RX65N_GRROSE
default "s32k118evb" if ARCH_BOARD_S32K118EVB
+ default "s32k144evb" if ARCH_BOARD_S32K144EVB
+ default "rddrone-uavcan144" if ARCH_BOARD_RDDRONE_UAVCAN144
+ default "rddrone-uavcan146" if ARCH_BOARD_RDDRONE_UAVCAN146
default "s32k146evb" if ARCH_BOARD_S32K146EVB
default "s32k148evb" if ARCH_BOARD_S32K148EVB
default "sabre-6quad" if ARCH_BOARD_SABRE_6QUAD
@@ -2263,6 +2296,15 @@ endif
if ARCH_BOARD_S32K118EVB
source "boards/arm/s32k1xx/s32k118evb/Kconfig"
endif
+if ARCH_BOARD_S32K144EVB
+source "boards/arm/s32k1xx/s32k144evb/Kconfig"
+endif
+if ARCH_BOARD_RDDRONE_UAVCAN144
+source "boards/arm/s32k1xx/rddrone-uavcan144/Kconfig"
+endif
+if ARCH_BOARD_RDDRONE_UAVCAN146
+source "boards/arm/s32k1xx/rddrone-uavcan146/Kconfig"
+endif
if ARCH_BOARD_S32K146EVB
source "boards/arm/s32k1xx/s32k146evb/Kconfig"
endif
diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/Kconfig b/boards/arm/s32k1xx/rddrone-uavcan144/Kconfig
new file mode 100644
index 0000000..c61362c
--- /dev/null
+++ b/boards/arm/s32k1xx/rddrone-uavcan144/Kconfig
@@ -0,0 +1,8 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_BOARD_RDDRONE_UAVCAN144
+
+endif # ARCH_BOARD_RDDRONE_UAVCAN144
diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/README.txt b/boards/arm/s32k1xx/rddrone-uavcan144/README.txt
new file mode 100644
index 0000000..d79bc82
--- /dev/null
+++ b/boards/arm/s32k1xx/rddrone-uavcan144/README.txt
@@ -0,0 +1,15 @@
+README
+======
+
+This directory holds the port to the NXP RDDRONE-UAVCAN board with S32K144 MCU.
+
+Contents
+========
+
+ o Status
+
+Status
+======
+
+ 2020-01-23: Configuration created (copy-paste from S32K146EVB).
+ Tested: Serial console, I2C, SPI
\ No newline at end of file
diff --git a/boards/arm/s32k1xx/s32k148evb/configs/nsh/defconfig b/boards/arm/s32k1xx/rddrone-uavcan144/configs/nsh/defconfig
similarity index 66%
copy from boards/arm/s32k1xx/s32k148evb/configs/nsh/defconfig
copy to boards/arm/s32k1xx/rddrone-uavcan144/configs/nsh/defconfig
index bdbf7d3..a7abcbe 100644
--- a/boards/arm/s32k1xx/s32k148evb/configs/nsh/defconfig
+++ b/boards/arm/s32k1xx/rddrone-uavcan144/configs/nsh/defconfig
@@ -10,19 +10,27 @@
# CONFIG_NSH_CMDOPT_HEXDUMP is not set
# CONFIG_NSH_CMDPARMS is not set
CONFIG_ARCH="arm"
-CONFIG_ARCH_BOARD="s32k148evb"
-CONFIG_ARCH_BOARD_S32K148EVB=y
+CONFIG_ARCH_BOARD="rddrone-uavcan144"
+CONFIG_ARCH_BOARD_RDDRONE_UAVCAN144=y
CONFIG_ARCH_CHIP="s32k1xx"
-CONFIG_ARCH_CHIP_S32K148=y
+CONFIG_ARCH_CHIP_S32K144=y
CONFIG_ARCH_CHIP_S32K14X=y
CONFIG_ARCH_CHIP_S32K1XX=y
CONFIG_ARCH_STACKDUMP=y
-CONFIG_BOARD_LOOPSPERMSEC=2988
+CONFIG_BOARD_LOOPSPERMSEC=3997
CONFIG_BUILTIN=y
CONFIG_EXAMPLES_HELLO=y
CONFIG_FS_PROCFS=y
CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_I2C=y
+CONFIG_I2CTOOL_DEFFREQ=100000
+CONFIG_I2CTOOL_MAXADDR=0x7f
+CONFIG_I2CTOOL_MAXBUS=0
+CONFIG_I2CTOOL_MINADDR=0x00
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LPUART0_RXBUFSIZE=64
+CONFIG_LPUART0_TXBUFSIZE=64
CONFIG_LPUART1_RXBUFSIZE=64
CONFIG_LPUART1_SERIAL_CONSOLE=y
CONFIG_LPUART1_TXBUFSIZE=64
@@ -38,17 +46,26 @@ CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_MQ_MSGS=4
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=16
-CONFIG_RAM_SIZE=23552
-CONFIG_RAM_START=0x1ffffc00
+CONFIG_RAM_SIZE=61440
+CONFIG_RAM_START=0x1fff8000
+CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
+CONFIG_S32K1XX_LPI2C0=y
+CONFIG_S32K1XX_LPSPI0=y
+CONFIG_S32K1XX_LPUART0=y
CONFIG_S32K1XX_LPUART1=y
CONFIG_SCHED_WAITPID=y
CONFIG_SDCLONE_DISABLE=y
+CONFIG_SPITOOL_DEFFREQ=400000
+CONFIG_SPITOOL_MAXBUS=0
+CONFIG_SPITOOL_PROGNAME="spi"
CONFIG_START_DAY=18
CONFIG_START_MONTH=8
CONFIG_START_YEAR=2019
CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_SYMTAB_ORDEREDBYNAME=y
+CONFIG_SYSTEM_I2CTOOL=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_NSH_CXXINITIALIZE=y
-CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_SYSTEM_SPITOOL=y
+CONFIG_USER_ENTRYPOINT="nsh_main"
\ No newline at end of file
diff --git a/boards/arm/s32k1xx/s32k148evb/configs/nsh/defconfig b/boards/arm/s32k1xx/rddrone-uavcan144/configs/nshdebug/defconfig
similarity index 64%
copy from boards/arm/s32k1xx/s32k148evb/configs/nsh/defconfig
copy to boards/arm/s32k1xx/rddrone-uavcan144/configs/nshdebug/defconfig
index bdbf7d3..c48d50d 100644
--- a/boards/arm/s32k1xx/s32k148evb/configs/nsh/defconfig
+++ b/boards/arm/s32k1xx/rddrone-uavcan144/configs/nshdebug/defconfig
@@ -10,19 +10,29 @@
# CONFIG_NSH_CMDOPT_HEXDUMP is not set
# CONFIG_NSH_CMDPARMS is not set
CONFIG_ARCH="arm"
-CONFIG_ARCH_BOARD="s32k148evb"
-CONFIG_ARCH_BOARD_S32K148EVB=y
+CONFIG_ARCH_BOARD="rddrone-uavcan144"
+CONFIG_ARCH_BOARD_RDDRONE_UAVCAN144=y
CONFIG_ARCH_CHIP="s32k1xx"
-CONFIG_ARCH_CHIP_S32K148=y
+CONFIG_ARCH_CHIP_S32K144=y
CONFIG_ARCH_CHIP_S32K14X=y
CONFIG_ARCH_CHIP_S32K1XX=y
CONFIG_ARCH_STACKDUMP=y
-CONFIG_BOARD_LOOPSPERMSEC=2988
+CONFIG_BOARD_LOOPSPERMSEC=3997
CONFIG_BUILTIN=y
+CONFIG_DEBUG_FEATURES=y
+CONFIG_DEBUG_SYMBOLS=y
CONFIG_EXAMPLES_HELLO=y
CONFIG_FS_PROCFS=y
CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_I2C=y
+CONFIG_I2CTOOL_DEFFREQ=100000
+CONFIG_I2CTOOL_MAXADDR=0x7f
+CONFIG_I2CTOOL_MAXBUS=0
+CONFIG_I2CTOOL_MINADDR=0x00
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LPUART0_RXBUFSIZE=64
+CONFIG_LPUART0_TXBUFSIZE=64
CONFIG_LPUART1_RXBUFSIZE=64
CONFIG_LPUART1_SERIAL_CONSOLE=y
CONFIG_LPUART1_TXBUFSIZE=64
@@ -38,17 +48,26 @@ CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_MQ_MSGS=4
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=16
-CONFIG_RAM_SIZE=23552
-CONFIG_RAM_START=0x1ffffc00
+CONFIG_RAM_SIZE=61440
+CONFIG_RAM_START=0x1fff8000
+CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
+CONFIG_S32K1XX_LPI2C0=y
+CONFIG_S32K1XX_LPSPI0=y
+CONFIG_S32K1XX_LPUART0=y
CONFIG_S32K1XX_LPUART1=y
CONFIG_SCHED_WAITPID=y
CONFIG_SDCLONE_DISABLE=y
+CONFIG_SPITOOL_DEFFREQ=400000
+CONFIG_SPITOOL_MAXBUS=0
+CONFIG_SPITOOL_PROGNAME="spi"
CONFIG_START_DAY=18
CONFIG_START_MONTH=8
CONFIG_START_YEAR=2019
CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_SYMTAB_ORDEREDBYNAME=y
+CONFIG_SYSTEM_I2CTOOL=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_NSH_CXXINITIALIZE=y
-CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_SYSTEM_SPITOOL=y
+CONFIG_USER_ENTRYPOINT="nsh_main"
\ No newline at end of file
diff --git a/boards/arm/s32k1xx/s32k146evb/include/board.h b/boards/arm/s32k1xx/rddrone-uavcan144/include/board.h
similarity index 78%
copy from boards/arm/s32k1xx/s32k146evb/include/board.h
copy to boards/arm/s32k1xx/rddrone-uavcan144/include/board.h
index da991a1..6f5966e 100644
--- a/boards/arm/s32k1xx/s32k146evb/include/board.h
+++ b/boards/arm/s32k1xx/rddrone-uavcan144/include/board.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/arm/s32k1xx/s32k146evb/include/board.h
+ * boards/arm/s32k1xx/rddrone-uavcan144/include/board.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -33,8 +33,8 @@
*
****************************************************************************/
-#ifndef __BOARDS_ARM_STM32F4DISCOVERY_INCLUDE_BOARD_H
-#define __BOARDS_ARM_STM32F4DISCOVERY_INCLUDE_BOARD_H
+#ifndef __BOARDS_ARM_RDDRONE_UAVCAN144_INCLUDE_BOARD_H
+#define __BOARDS_ARM_RDDRONE_UAVCAN144_INCLUDE_BOARD_H
/****************************************************************************
* Included Files
@@ -53,15 +53,15 @@
/* Clocking *****************************************************************/
-/* The S32K146EVB is fitted with a 8MHz Crystal */
+/* The RDDRONE-UAVCAN144 is fitted with a 8MHz Crystal */
#define BOARD_XTAL_FREQUENCY 8000000
-/* The S32K146 will run at 112MHz */
+/* The S32K144 will run at 112MHz */
/* LED definitions **********************************************************/
-/* The S32K146EVB has one RGB LED:
+/* The RDDRONE-UAVCAN144 has one RGB LED:
*
* RedLED PTD15 (FTM0 CH0)
* GreenLED PTD16 (FTM0 CH1)
@@ -89,9 +89,8 @@
#define BOARD_LED_B_BIT (1 << BOARD_LED_B)
/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LEDs on board
- * the s32k146evb. The following definitions describe how NuttX controls the
- * LEDs:
- *
+ * the RDDRONE-UAVCAN144. The following definitions describe how NuttX
+ * controls the LEDs:
*
* SYMBOL Meaning LED state
* RED GREEN BLUE
@@ -106,11 +105,11 @@
#define LED_SIGNAL 0 /* In a signal handler (no change) */
#define LED_ASSERTION 0 /* An assertion failed (no change) */
#define LED_PANIC 4 /* The system has crashed FLASH OFF OFF */
-#undef LED_IDLE /* S32K146EVN in sleep mode (Not used) */
+#undef LED_IDLE /* RDDRONE-UAVCAN144 in sleep mode (Not used) */
/* Button definitions *******************************************************/
-/* The S32K146EVB supports two buttons:
+/* The RDDRONE-UAVCAN144 supports two buttons:
*
* SW2 PTC12
* SW3 PTC13
@@ -131,10 +130,24 @@
* OpenSDA UART RX PTC6 (LPUART1_RX)
*/
+#define PIN_LPUART0_CTS PIN_LPUART0_CTS_2 /* PTC8 */
+#define PIN_LPUART0_RTS PIN_LPUART0_RTS_2 /* PTC9 */
+#define PIN_LPUART0_RX PIN_LPUART0_RX_1 /* PTB0 */
+#define PIN_LPUART0_TX PIN_LPUART0_TX_1 /* PTB1 */
+
#define PIN_LPUART1_RX PIN_LPUART1_RX_1 /* PTC6 */
#define PIN_LPUART1_TX PIN_LPUART1_TX_1 /* PTC7 */
-/* DMA Channel/Stream Selections ********************************************/
+/* SPI selections ***********************************************************/
+
+#define PIN_LPSPI0_SCK PIN_LPSPI0_SCK_2 /* PTB2 */
+#define PIN_LPSPI0_MISO PIN_LPSPI0_SIN_2 /* PTB3 */
+#define PIN_LPSPI0_MOSI PIN_LPSPI0_SOUT_3 /* PTB4 */
+#define PIN_LPSPI0_PCS PIN_LPSPI0_PCS0_2 /* PTB5 */
+
+/* I2C selections ***********************************************************/
+#define PIN_LPI2C0_SCL PIN_LPI2C0_SCL_2 /* PTA3 */
+#define PIN_LPI2C0_SDA PIN_LPI2C0_SDA_2 /* PTA2 */
-#endif /* __BOARDS_ARM_STM32F4DISCOVERY_INCLUDE_BOARD_H */
+#endif /* __BOARDS_ARM_RDDRONE_UAVCAN144_INCLUDE_BOARD_H */
diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/scripts/Make.defs b/boards/arm/s32k1xx/rddrone-uavcan144/scripts/Make.defs
new file mode 100644
index 0000000..e8cfa94
--- /dev/null
+++ b/boards/arm/s32k1xx/rddrone-uavcan144/scripts/Make.defs
@@ -0,0 +1,131 @@
+############################################################################
+# boards/arm/s32k1xx/rddrone-uavcan144/scripts/Make.defs
+#
+# Copyright (C) 2018 Gregory Nutt. All rights reserved.
+# Author: Gregory Nutt <gn...@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+# used to endorse or promote products derived from this software
+# without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+include ${TOPDIR}/.config
+include ${TOPDIR}/tools/Config.mk
+include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs
+
+ifeq ($(CONFIG_BOOT_RUNFROMFLASH),y)
+ LDSCRIPT = flash.ld
+else ifeq ($(CONFIG_BOOT_RUNFROMISRAM),y)
+ LDSCRIPT = sram.ld
+endif
+
+$(warning, LDSCRIPT is $(LDSCRIPT))
+ifeq ($(WINTOOL),y)
+ # Windows-native toolchains
+ ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
+ ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
+ ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
+else
+ # Linux/Cygwin-native toolchain
+ ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
+ ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
+ ARCHSCRIPT = -T$(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
+endif
+$(warning, LDSCRIPT is $(LDSCRIPT))
+$(warning, ARCHSCRIPT is $(ARCHSCRIPT))
+
+CC = $(CROSSDEV)gcc
+CXX = $(CROSSDEV)g++
+CPP = $(CROSSDEV)gcc -E
+LD = $(CROSSDEV)ld
+STRIP = $(CROSSDEV)strip --strip-unneeded
+AR = $(ARCROSSDEV)ar rcs
+NM = $(ARCROSSDEV)nm
+OBJCOPY = $(CROSSDEV)objcopy
+OBJDUMP = $(CROSSDEV)objdump
+
+ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
+ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
+
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+ ARCHOPTIMIZATION = -g
+endif
+
+ifneq ($(CONFIG_DEBUG_NOOPT),y)
+ ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
+endif
+
+ARCHCFLAGS = -fno-builtin
+ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
+ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
+ARCHWARNINGSXX = -Wall -Wshadow -Wundef
+ARCHDEFINES =
+ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
+
+CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
+AFLAGS = $(CFLAGS) -D__ASSEMBLY__
+
+NXFLATLDFLAGS1 = -r -d -warn-common
+NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
+LDNXFLATFLAGS = -e main -s 2048
+
+ASMEXT = .S
+OBJEXT = .o
+LIBEXT = .a
+EXEEXT =
+
+ifneq ($(CROSSDEV),arm-nuttx-elf-)
+ LDFLAGS += -nostartfiles -nodefaultlibs
+endif
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+ LDFLAGS += -g
+endif
+
+
+HOSTCC = gcc
+HOSTINCLUDES = -I.
+HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
+HOSTLDFLAGS =
+ifeq ($(CONFIG_HOST_WINDOWS),y)
+ HOSTEXEEXT = .exe
+else
+ HOSTEXEEXT =
+endif
+
+ifeq ($(WINTOOL),y)
+ # Windows-native host tools
+ DIRLINK = $(TOPDIR)/tools/copydir.sh
+ DIRUNLINK = $(TOPDIR)/tools/unlink.sh
+ MKDEP = $(TOPDIR)/tools/mkwindeps.sh
+else
+ # Linux/Cygwin-native host tools
+ MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
+endif
diff --git a/boards/arm/s32k1xx/s32k148evb/scripts/flash.ld b/boards/arm/s32k1xx/rddrone-uavcan144/scripts/flash.ld
similarity index 91%
copy from boards/arm/s32k1xx/s32k148evb/scripts/flash.ld
copy to boards/arm/s32k1xx/rddrone-uavcan144/scripts/flash.ld
index b59ab9b..ac75100 100644
--- a/boards/arm/s32k1xx/s32k148evb/scripts/flash.ld
+++ b/boards/arm/s32k1xx/rddrone-uavcan144/scripts/flash.ld
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/arm/s32k1xx/s32k148evb/scripts/flash.ld
+ * boards/arm/s32k1xx/rddrone-uavcan144/scripts/flash.ld
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -33,23 +33,23 @@
*
****************************************************************************/
-/* The S32K148 has 2Mb of FLASH beginning at address 0x0000:0000 and
- * 252Kb of SRAM beginning at address 0x1ffe:0000 (plus 4Kb of FlexRAM)
+/* The S32K144 has 512Kb of FLASH beginning at address 0x0000:0000 and
+ * 60Kb of SRAM beginning at address 0x1fff:8000 (plus 4Kb of FlexRAM)
*
* The on-chip RAM is split in two regions: SRAM_L and SRAM_U. The RAM is
* implemented such that the SRAM_L and SRAM_U ranges form a contiguous
* block in the memory map
*
- * SRAM_L 1ffe0000 - 1fffffff 128Kb
- * SRAM_U 20000000 - 2001efff 124Kb
+ * SRAM_L 1fff8000 - 1fffffff 32Kb
+ * SRAM_U 20000000 - 20006fff 28Kb
*/
MEMORY
{
vflash (rx) : ORIGIN = 0x00000000, LENGTH = 1K
pflash (rx) : ORIGIN = 0x00000400, LENGTH = 16
- dflash (rx) : ORIGIN = 0x00000410, LENGTH = 2047K-16
- sram (rwx) : ORIGIN = 0x1fff0000, LENGTH = 252K
+ dflash (rx) : ORIGIN = 0x00000410, LENGTH = 511K-16
+ sram (rwx) : ORIGIN = 0x1fff8000, LENGTH = 60K
}
OUTPUT_ARCH(arm)
diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/scripts/s32k144.cfg b/boards/arm/s32k1xx/rddrone-uavcan144/scripts/s32k144.cfg
new file mode 100644
index 0000000..7d30a9f
--- /dev/null
+++ b/boards/arm/s32k1xx/rddrone-uavcan144/scripts/s32k144.cfg
@@ -0,0 +1,58 @@
+#
+# NXP S32K144 - 1x ARM Cortex-M4 @ up to 112 MHz
+#
+
+adapter_khz 4000
+transport select swd
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME s32k144
+}
+
+#
+# M4 JTAG mode TAP
+#
+if { [info exists M4_JTAG_TAPID] } {
+ set _M4_JTAG_TAPID $M4_JTAG_TAPID
+} else {
+ set _M4_JTAG_TAPID 0x4ba00477
+}
+
+#
+# M4 SWD mode TAP
+#
+if { [info exists M4_SWD_TAPID] } {
+ set _M4_SWD_TAPID $M4_SWD_TAPID
+} else {
+ set _M4_SWD_TAPID 0x2ba01477
+}
+
+source [find target/swj-dp.tcl]
+
+if { [using_jtag] } {
+ set _M4_TAPID $_M4_JTAG_TAPID
+} else {
+ set _M4_TAPID $_M4_SWD_TAPID
+}
+
+swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
+ -expected-id $_M4_TAPID
+
+target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4
+
+# S32K144 has 32+28 KB contiguous SRAM
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ set _WORKAREASIZE 0xF000
+}
+$_CHIPNAME.m4 configure -work-area-phys 0x1FFF8000 \
+ -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+$_CHIPNAME.m4 configure -rtos nuttx
+
+if { ![using_hla] } {
+ cortex_m reset_config vectreset
+}
diff --git a/boards/arm/s32k1xx/s32k148evb/scripts/sram.ld b/boards/arm/s32k1xx/rddrone-uavcan144/scripts/sram.ld
similarity index 90%
copy from boards/arm/s32k1xx/s32k148evb/scripts/sram.ld
copy to boards/arm/s32k1xx/rddrone-uavcan144/scripts/sram.ld
index c5819bf..1b992ec 100644
--- a/boards/arm/s32k1xx/s32k148evb/scripts/sram.ld
+++ b/boards/arm/s32k1xx/rddrone-uavcan144/scripts/sram.ld
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/arm/s32k1xx/s32k148evb/scripts/sram.ld
+ * boards/arm/s32k1xx/rddrone-uavcan144/scripts/sram.ld
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -33,21 +33,21 @@
*
****************************************************************************/
-/* The S32K148 has 2Mb of FLASH beginning at address 0x0000:0000 and
- * 252Kb of SRAM beginning at address 0x1ffe:0000 (plus 4Kb of FlexRAM)
+/* The S32K144 has 512Kb of FLASH beginning at address 0x0000:0000 and
+ * 60Kb of SRAM beginning at address 0x1fff:8000 (plus 4Kb of FlexRAM)
*
* The on-chip RAM is split in two regions: SRAM_L and SRAM_U. The RAM is
* implemented such that the SRAM_L and SRAM_U ranges form a contiguous
* block in the memory map
*
- * SRAM_L 1ffe0000 - 1fffffff 128Kb
- * SRAM_U 20000000 - 2001efff 124Kb
+ * SRAM_L 1fff8000 - 1fffffff 32Kb
+ * SRAM_U 20000000 - 20006fff 28Kb
*/
MEMORY
{
- flash (rx) : ORIGIN = 0x00000000, LENGTH = 2M
- sram (rwx) : ORIGIN = 0x1fff0000, LENGTH = 252K
+ flash (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+ sram (rwx) : ORIGIN = 0x1fff8000, LENGTH = 60K
}
OUTPUT_ARCH(arm)
diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/src/.gitignore b/boards/arm/s32k1xx/rddrone-uavcan144/src/.gitignore
new file mode 100644
index 0000000..726d936
--- /dev/null
+++ b/boards/arm/s32k1xx/rddrone-uavcan144/src/.gitignore
@@ -0,0 +1,2 @@
+/.depend
+/Make.dep
diff --git a/boards/arm/s32k1xx/s32k146evb/src/Makefile b/boards/arm/s32k1xx/rddrone-uavcan144/src/Makefile
similarity index 85%
copy from boards/arm/s32k1xx/s32k146evb/src/Makefile
copy to boards/arm/s32k1xx/rddrone-uavcan144/src/Makefile
index 5237a26..56fd270 100644
--- a/boards/arm/s32k1xx/s32k146evb/src/Makefile
+++ b/boards/arm/s32k1xx/rddrone-uavcan144/src/Makefile
@@ -1,5 +1,5 @@
############################################################################
-# boards/arm/s32k1xx/s32k146evb/src/Makefile
+# boards/arm/s32k1xx/rddrone-uavcan144/src/Makefile
#
# Copyright (C) 2019 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gn...@nuttx.org>
@@ -36,21 +36,25 @@
-include $(TOPDIR)/Make.defs
ASRCS =
-CSRCS = s32k146_boot.c s32k146_bringup.c s32k146_clockconfig.c
-CSRCS += s32k146_periphclocks.c
+CSRCS = s32k1xx_boot.c s32k1xx_bringup.c s32k1xx_clockconfig.c
+CSRCS += s32k1xx_periphclocks.c
ifeq ($(CONFIG_ARCH_LEDS),y)
-CSRCS += s32k146_autoleds.c
+CSRCS += s32k1xx_autoleds.c
else
-CSRCS += s32k146_userleds.c
+CSRCS += s32k1xx_userleds.c
endif
ifeq ($(CONFIG_ARCH_BUTTONS),y)
-CSRCS += s32k146_buttons.c
+CSRCS += s32k1xx_buttons.c
endif
ifeq ($(CONFIG_LIB_BOARDCTL),y)
-CSRCS += s32k146_appinit.c
+CSRCS += s32k1xx_appinit.c
+endif
+
+ifeq ($(CONFIG_S32K1XX_LPSPI),y)
+CSRCS += s32k1xx_spi.c
endif
include $(TOPDIR)/boards/Board.mk
diff --git a/boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h b/boards/arm/s32k1xx/rddrone-uavcan144/src/rddrone-uavcan144.h
similarity index 82%
copy from boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h
copy to boards/arm/s32k1xx/rddrone-uavcan144/src/rddrone-uavcan144.h
index 13cfc0c..62697cd 100644
--- a/boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h
+++ b/boards/arm/s32k1xx/rddrone-uavcan144/src/rddrone-uavcan144.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h
+ * boards/arm/s32k1xx/rddrone-uavcan144/src/rddrone-uavcan144.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -33,8 +33,8 @@
*
****************************************************************************/
-#ifndef __BOARDS_ARM_S32K1XX_S32K146EVB_SRC_S32K146EVB_H
-#define __BOARDS_ARM_S32K1XX_S32K146EVB_SRC_S32K146EVB_H
+#ifndef __BOARDS_ARM_S32K1XX_RDDRONE_UAVCAN144_SRC_RDDRONE_UAVCAN144_H
+#define __BOARDS_ARM_S32K1XX_RDDRONE_UAVCAN144_SRC_RDDRONE_UAVCAN144_H
/****************************************************************************
* Included Files
@@ -54,9 +54,9 @@
/* Configuration ************************************************************/
-/* S32K146EVB GPIOs *********************************************************/
+/* RDDRONE-UAVCAN144 GPIOs **************************************************/
-/* LEDs. The S32K146EVB has one RGB LED:
+/* LEDs. The RDDRONE-UAVCAN144 has one RGB LED:
*
* RedLED PTD15 (FTM0 CH0)
* GreenLED PTD16 (FTM0 CH1)
@@ -67,9 +67,9 @@
#define GPIO_LED_R (PIN_PTD15 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
#define GPIO_LED_G (PIN_PTD16 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
-#define GPIO_LED_B (PIN_PTE8 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
+#define GPIO_LED_B (PIN_PTD0 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
-/* Buttons. The S32K146EVB supports two buttons:
+/* Buttons. The RDDRONE-UAVCAN144 supports two buttons:
*
* SW2 PTC12
* SW3 PTC13
@@ -80,17 +80,20 @@
/* SPI chip selects */
+/* A71CH Reset */
+
+#define GPIO_A71CH_RST (PIN_PTA6 | GPIO_LOWDRIVE)
/* Count of peripheral clock user configurations */
-#define NUM_OF_PERIPHERAL_CLOCKS_0 11
+#define NUM_OF_PERIPHERAL_CLOCKS_0 15
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
- * Public data
+ * Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
@@ -100,11 +103,11 @@
extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[];
/****************************************************************************
- * Public Functions
+ * Public Function Prototypes
****************************************************************************/
/****************************************************************************
- * Name: s32k146_bringup
+ * Name: s32k1xx_bringup
*
* Description:
* Perform architecture-specific initialization
@@ -117,20 +120,20 @@ extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[];
*
****************************************************************************/
-int s32k146_bringup(void);
+int s32k1xx_bringup(void);
/****************************************************************************
- * Name: s32k146_spidev_initialize
+ * Name: s32k1xx_spidev_initialize
*
* Description:
- * Called to configure SPI chip select GPIO pins for the s32k146evb
+ * Called to configure SPI chip select GPIO pins for the RDDRONE-UAVCAN144
* board.
*
****************************************************************************/
-#ifdef CONFIG_S32K1XX_SPI
-void s32k146_spidev_initialize(void);
+#ifdef CONFIG_S32K1XX_LPSPI
+void s32k1xx_spidev_initialize(void);
#endif
#endif /* __ASSEMBLY__ */
-#endif /* __BOARDS_ARM_S32K1XX_S32K146EVB_SRC_S32K146EVB_H */
+#endif /* __BOARDS_ARM_S32K1XX_RDDRONE_UAVCAN144_SRC_RDDRONE_UAVCAN144_H */
diff --git a/arch/arm/src/s32k1xx/chip.h b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_appinit.c
similarity index 58%
copy from arch/arm/src/s32k1xx/chip.h
copy to boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_appinit.c
index f3f9b9c..5168f36 100644
--- a/arch/arm/src/s32k1xx/chip.h
+++ b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_appinit.c
@@ -1,5 +1,5 @@
-/************************************************************************************
- * arch/arm/src/s32k1xx/chip.h
+/****************************************************************************
+ * boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_appinit.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -31,47 +31,64 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ************************************************************************************/
+ ****************************************************************************/
-#ifndef __ARCH_ARM_SRC_S32K1XX_CHIP_H
-#define __ARCH_ARM_SRC_S32K1XX_CHIP_H
-
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
-/* Include the memory map and the chip definitions file. Other chip hardware files
- * should then include this file for the proper setup.
- */
+#include <nuttx/board.h>
-#include <arch/irq.h>
-#include "hardware/s32k1xx_memorymap.h"
+#include "rddrone-uavcan144.h"
-/* The common ARMv6/7-M vector handling logic expects the following definitions in
- * this file. ARMV6/7M_PERIPHERAL_INTERRUPTS provides the number of supported
- * external interrupts which, for this architecture, is provided in the
- * arch/s32k1xx/irq.h header file.
- */
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
-#define ARMV6M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT
-#define ARMV7M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT
+#ifndef OK
+# define OK 0
+#endif
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
-/************************************************************************************
- * Public Types
- ************************************************************************************/
+/****************************************************************************
+ * Name: board_app_initialize
+ *
+ * Description:
+ * Perform application specific initialization. This function is never
+ * called directly from application code, but only indirectly via the
+ * (non-standard) boardctl() interface using the command BOARDIOC_INIT.
+ *
+ * Input Parameters:
+ * arg - The boardctl() argument is passed to the board_app_initialize()
+ * implementation without modification. The argument has no
+ * meaning to NuttX; the meaning of the argument is a contract
+ * between the board-specific initialization logic and the
+ * matching application logic. The value cold be such things as a
+ * mode enumeration value, a set of DIP switch switch settings, a
+ * pointer to configuration data read from a file or serial FLASH,
+ * or whatever you would like to do with it. Every implementation
+ * should accept zero/NULL as a default configuration.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned on
+ * any failure to indicate the nature of the failure.
+ *
+ ****************************************************************************/
-/************************************************************************************
- * Public Data
- ************************************************************************************/
+int board_app_initialize(uintptr_t arg)
+{
+#ifdef CONFIG_BOARD_LATE_INITIALIZE
+ /* Board initialization already performed by board_late_initialize() */
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
+ return OK;
+#else
+ /* Perform board-specific initialization */
-#endif /* __ARCH_ARM_SRC_S32K1XX_CHIP_H */
+ return s32k1xx_bringup();
+#endif
+}
diff --git a/boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_autoleds.c
similarity index 52%
copy from boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h
copy to boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_autoleds.c
index 13cfc0c..6a63a9b 100644
--- a/boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h
+++ b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_autoleds.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h
+ * boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_autoleds.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -33,104 +33,133 @@
*
****************************************************************************/
-#ifndef __BOARDS_ARM_S32K1XX_S32K146EVB_SRC_S32K146EVB_H
-#define __BOARDS_ARM_S32K1XX_S32K146EVB_SRC_S32K146EVB_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-#include <nuttx/compiler.h>
-
-#include <stdint.h>
-
-#include "hardware/s32k1xx_pinmux.h"
-#include "s32k1xx_periphclocks.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* Configuration ************************************************************/
-
-/* S32K146EVB GPIOs *********************************************************/
-
-/* LEDs. The S32K146EVB has one RGB LED:
+/* The RDDRONE-UAVCAN144 has one RGB LED:
*
* RedLED PTD15 (FTM0 CH0)
* GreenLED PTD16 (FTM0 CH1)
* BlueLED PTD0 (FTM0 CH2)
*
* An output of '1' illuminates the LED.
+ *
+ * If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board
+ * the Freedom K66F. The following definitions describe how NuttX controls
+ * the LEDs:
+ *
+ * SYMBOL Meaning LED state
+ * RED GREEN BLUE
+ * ------------------- ----------------------- -----------------
+ * LED_STARTED NuttX has been started OFF OFF OFF
+ * LED_HEAPALLOCATE Heap has been allocated OFF OFF ON
+ * LED_IRQSENABLED Interrupts enabled OFF OFF ON
+ * LED_STACKCREATED Idle stack created OFF ON OFF
+ * LED_INIRQ In an interrupt (no change)
+ * LED_SIGNAL In a signal handler (no change)
+ * LED_ASSERTION An assertion failed (no change)
+ * LED_PANIC The system has crashed FLASH OFF OFF
+ * LED_IDLE K66 is in sleep mode (Optional, not used)
*/
-#define GPIO_LED_R (PIN_PTD15 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
-#define GPIO_LED_G (PIN_PTD16 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
-#define GPIO_LED_B (PIN_PTE8 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
-/* Buttons. The S32K146EVB supports two buttons:
- *
- * SW2 PTC12
- * SW3 PTC13
- */
+#include <nuttx/config.h>
-#define GPIO_SW2 (PIN_PTC12 | PIN_INT_BOTH)
-#define GPIO_SW3 (PIN_PTC13 | PIN_INT_BOTH)
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
-/* SPI chip selects */
+#include <nuttx/board.h>
+#include <arch/board/board.h>
+#include "up_arch.h"
+#include "up_internal.h"
-/* Count of peripheral clock user configurations */
+#include "s32k1xx_pin.h"
+#include "rddrone-uavcan144.h"
-#define NUM_OF_PERIPHERAL_CLOCKS_0 11
+#include <arch/board/board.h>
-/****************************************************************************
- * Public Types
- ****************************************************************************/
+#ifdef CONFIG_ARCH_LEDS
/****************************************************************************
- * Public data
+ * Pre-processor Definitions
****************************************************************************/
-#ifndef __ASSEMBLY__
+/* Summary of all possible settings */
-/* User peripheral configuration structure 0 */
-
-extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[];
+#define LED_NOCHANGE 0 /* LED_IRQSENABLED, LED_INIRQ, LED_SIGNAL, LED_ASSERTION */
+#define LED_OFF_OFF_OFF 1 /* LED_STARTED */
+#define LED_OFF_OFF_ON 2 /* LED_HEAPALLOCATE */
+#define LED_OFF_ON_OFF 3 /* LED_STACKCREATED */
+#define LED_ON_OFF_OFF 4 /* LED_PANIC */
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
- * Name: s32k146_bringup
- *
- * Description:
- * Perform architecture-specific initialization
- *
- * CONFIG_BOARD_LATE_INITIALIZE=y :
- * Called from board_late_initialize().
- *
- * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y :
- * Called from the NSH library
- *
+ * Name: board_autoled_initialize
****************************************************************************/
-int s32k146_bringup(void);
+void board_autoled_initialize(void)
+{
+ /* Configure LED GPIOs for output */
+
+ s32k1xx_pinconfig(GPIO_LED_R);
+ s32k1xx_pinconfig(GPIO_LED_G);
+ s32k1xx_pinconfig(GPIO_LED_B);
+}
/****************************************************************************
- * Name: s32k146_spidev_initialize
- *
- * Description:
- * Called to configure SPI chip select GPIO pins for the s32k146evb
- * board.
- *
+ * Name: board_autoled_on
****************************************************************************/
-#ifdef CONFIG_S32K1XX_SPI
-void s32k146_spidev_initialize(void);
-#endif
+void board_autoled_on(int led)
+{
+ if (led != LED_NOCHANGE)
+ {
+ bool redon = false;
+ bool greenon = false;
+ bool blueon = false;
+
+ switch (led)
+ {
+ default:
+ case LED_OFF_OFF_OFF:
+ break;
+
+ case LED_OFF_OFF_ON:
+ blueon = true;
+ break;
+
+ case LED_OFF_ON_OFF:
+ greenon = true;
+ break;
+
+ case LED_ON_OFF_OFF:
+ redon = true;
+ break;
+ }
+
+ s32k1xx_gpiowrite(GPIO_LED_R, redon);
+ s32k1xx_gpiowrite(GPIO_LED_G, greenon);
+ s32k1xx_gpiowrite(GPIO_LED_B, blueon);
+ }
+}
+
+/****************************************************************************
+ * Name: board_autoled_off
+ ****************************************************************************/
-#endif /* __ASSEMBLY__ */
-#endif /* __BOARDS_ARM_S32K1XX_S32K146EVB_SRC_S32K146EVB_H */
+void board_autoled_off(int led)
+{
+ if (led == LED_ON_OFF_OFF)
+ {
+ s32k1xx_gpiowrite(GPIO_LED_R, true);
+ s32k1xx_gpiowrite(GPIO_LED_G, false);
+ s32k1xx_gpiowrite(GPIO_LED_B, false);
+ }
+}
+
+#endif /* CONFIG_ARCH_LEDS */
diff --git a/arch/arm/src/s32k1xx/chip.h b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_boot.c
similarity index 62%
copy from arch/arm/src/s32k1xx/chip.h
copy to boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_boot.c
index f3f9b9c..3fcaa13 100644
--- a/arch/arm/src/s32k1xx/chip.h
+++ b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_boot.c
@@ -1,5 +1,5 @@
-/************************************************************************************
- * arch/arm/src/s32k1xx/chip.h
+/****************************************************************************
+ * boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_boot.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -31,47 +31,63 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ************************************************************************************/
+ ****************************************************************************/
-#ifndef __ARCH_ARM_SRC_S32K1XX_CHIP_H
-#define __ARCH_ARM_SRC_S32K1XX_CHIP_H
-
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
-/* Include the memory map and the chip definitions file. Other chip hardware files
- * should then include this file for the proper setup.
- */
+#include <debug.h>
+
+#include <nuttx/board.h>
-#include <arch/irq.h>
-#include "hardware/s32k1xx_memorymap.h"
+#include "rddrone-uavcan144.h"
-/* The common ARMv6/7-M vector handling logic expects the following definitions in
- * this file. ARMV6/7M_PERIPHERAL_INTERRUPTS provides the number of supported
- * external interrupts which, for this architecture, is provided in the
- * arch/s32k1xx/irq.h header file.
- */
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
-#define ARMV6M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT
-#define ARMV7M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT
+/****************************************************************************
+ * Name: s32k1xx_board_initialize
+ *
+ * Description:
+ * All S32K1XX architectures must provide the following entry point. This
+ * entry point is called early in the initialization -- after all memory
+ * has been configured and mapped but before any devices have been
+ * initialized.
+ *
+ ****************************************************************************/
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
+void s32k1xx_board_initialize(void)
+{
+#ifdef CONFIG_ARCH_LEDS
+ /* Configure on-board LEDs if LED support has been selected. */
-/************************************************************************************
- * Public Types
- ************************************************************************************/
+ board_autoled_initialize();
+#endif
+}
-/************************************************************************************
- * Public Data
- ************************************************************************************/
+/****************************************************************************
+ * Name: board_late_initialize
+ *
+ * Description:
+ * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
+ * initialization call will be performed in the boot-up sequence to a
+ * function called board_late_initialize(). board_late_initialize() will
+ * be called immediately after up_initialize() is called and just before
+ * the initial application is started. This additional initialization
+ * phase may be used, for example, to initialize board-specific device
+ * drivers.
+ *
+ ****************************************************************************/
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
+#ifdef CONFIG_BOARD_LATE_INITIALIZE
+void board_late_initialize(void)
+{
+ /* Perform board-specific initialization */
-#endif /* __ARCH_ARM_SRC_S32K1XX_CHIP_H */
+ s32k1xx_bringup();
+}
+#endif
diff --git a/boards/arm/s32k1xx/s32k148evb/src/s32k148evb.h b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_bringup.c
similarity index 51%
copy from boards/arm/s32k1xx/s32k148evb/src/s32k148evb.h
copy to boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_bringup.c
index ba85f50..bc0abbf 100644
--- a/boards/arm/s32k1xx/s32k148evb/src/s32k148evb.h
+++ b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_bringup.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/arm/s32k1xx/s32k148evb/src/s32k148evb.h
+ * boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_bringup.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -33,78 +33,38 @@
*
****************************************************************************/
-#ifndef __BOARDS_ARM_S32K1XX_S32K148EVB_SRC_S32K148EVB_H
-#define __BOARDS_ARM_S32K1XX_S32K148EVB_SRC_S32K148EVB_H
-
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
-#include <nuttx/compiler.h>
-
-#include <stdint.h>
-
-#include "hardware/s32k1xx_pinmux.h"
-#include "s32k1xx_periphclocks.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* Configuration ************************************************************/
-
-/* S32K148EVB GPIOs *********************************************************/
-
-/* LEDs. The S32K148EVB has one RGB LED:
- *
- * RedLED PTE21
- * GreenLED PTE22
- * BlueLED PTE23
- *
- * An output of '1' illuminates the LED.
- */
-#define GPIO_LED_R (PIN_PTE21 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
-#define GPIO_LED_G (PIN_PTE22 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
-#define GPIO_LED_B (PIN_PTE23 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
+#include <sys/types.h>
+#include <sys/mount.h>
+#include <syslog.h>
-/* Buttons. The S32K148EVB supports two buttons:
- *
- * SW3 PTC12
- * SW4 PTC13
- */
-
-#define GPIO_SW3 (PIN_PTC12 | PIN_INT_BOTH)
-#define GPIO_SW4 (PIN_PTC13 | PIN_INT_BOTH)
-
-/* SPI chip selects */
-
-
-/* Count of peripheral clock user configurations */
-
-#define NUM_OF_PERIPHERAL_CLOCKS_0 11
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-/****************************************************************************
- * Public data
- ****************************************************************************/
+#ifdef CONFIG_BUTTONS
+# include <nuttx/input/buttons.h>
+#endif
-#ifndef __ASSEMBLY__
+#ifdef CONFIG_USERLED
+# include <nuttx/leds/userled.h>
+#endif
-/* User peripheral configuration structure 0 */
+#ifdef CONFIG_I2C_DRIVER
+# include "s32k1xx_pin.h"
+# include <nuttx/i2c/i2c_master.h>
+# include "s32k1xx_lpi2c.h"
+#endif
-extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[];
+#include "rddrone-uavcan144.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
- * Name: s32k148_bringup
+ * Name: s32k1xx_bringup
*
* Description:
* Perform architecture-specific initialization
@@ -112,25 +72,76 @@ extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[];
* CONFIG_BOARD_LATE_INITIALIZE=y :
* Called from board_late_initialize().
*
- * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y :
+ * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y :
* Called from the NSH library
*
****************************************************************************/
-int s32k148_bringup(void);
+int s32k1xx_bringup(void)
+{
+ int ret = OK;
-/****************************************************************************
- * Name: s32k148_spidev_initialize
- *
- * Description:
- * Called to configure SPI chip select GPIO pins for the s32k148evb
- * board.
- *
- ****************************************************************************/
+#ifdef CONFIG_BUTTONS
+ /* Register the BUTTON driver */
+
+ ret = btn_lower_initialize("/dev/buttons");
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret);
+ }
+#endif
-#ifdef CONFIG_S32K1XX_SPI
-void s32k148_spidev_initialize(void);
+#ifdef CONFIG_USERLED
+ /* Register the LED driver */
+
+ ret = userled_lower_initialize("/dev/userleds");
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret);
+ }
+#endif
+
+#ifdef CONFIG_FS_PROCFS
+ /* Mount the procfs file system */
+
+ ret = mount(NULL, "/proc", "procfs", 0, NULL);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret);
+ }
+#endif
+
+#ifdef CONFIG_S32K1XX_LPSPI
+ /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak
+ * function s32k1xx_spidev_initialize() has been brought into the link.
+ */
+
+ s32k1xx_spidev_initialize();
+#endif
+
+#if defined(CONFIG_S32K1XX_LPI2C0)
+ s32k1xx_pinconfig(GPIO_HIGHDRIVE | GPIO_OUTPUT_ONE | PIN_PORTA | PIN10); /* Set A71CH IF0 HIGH */
+ s32k1xx_pinconfig(GPIO_HIGHDRIVE | GPIO_OUTPUT_ZERO | PIN_PORTA | PIN7); /* Set A71CH IF1 LOW */
+
+#if defined(CONFIG_I2C_DRIVER)
+ FAR struct i2c_master_s *i2c;
+ i2c = s32k1xx_i2cbus_initialize(0);
+
+ if (i2c == NULL)
+ {
+ serr("ERROR: Failed to get I2C%d interface\n", bus);
+ }
+ else
+ {
+ ret = i2c_register(i2c, 0);
+ if (ret < 0)
+ {
+ serr("ERROR: Failed to register I2C%d driver: %d\n", bus, ret);
+ s32k1xx_i2cbus_uninitialize(i2c);
+ }
+ }
+#endif
#endif
-#endif /* __ASSEMBLY__ */
-#endif /* __BOARDS_ARM_S32K1XX_S32K148EVB_SRC_S32K148EVB_H */
+ return ret;
+}
diff --git a/boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_buttons.c
similarity index 51%
copy from boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h
copy to boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_buttons.c
index 13cfc0c..f5cf6e2 100644
--- a/boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h
+++ b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_buttons.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h
+ * boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_buttons.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -33,104 +33,133 @@
*
****************************************************************************/
-#ifndef __BOARDS_ARM_S32K1XX_S32K146EVB_SRC_S32K146EVB_H
-#define __BOARDS_ARM_S32K1XX_S32K146EVB_SRC_S32K146EVB_H
+/* The RDDRONE-UAVCAN144 supports two buttons:
+ *
+ * SW2 PTC12
+ * SW3 PTC13
+ */
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
-#include <nuttx/compiler.h>
#include <stdint.h>
+#include <errno.h>
-#include "hardware/s32k1xx_pinmux.h"
-#include "s32k1xx_periphclocks.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
-/* Configuration ************************************************************/
+#include "s32k1xx_pin.h"
+#include "rddrone-uavcan144.h"
-/* S32K146EVB GPIOs *********************************************************/
+#include <arch/board/board.h>
-/* LEDs. The S32K146EVB has one RGB LED:
- *
- * RedLED PTD15 (FTM0 CH0)
- * GreenLED PTD16 (FTM0 CH1)
- * BlueLED PTD0 (FTM0 CH2)
- *
- * An output of '1' illuminates the LED.
- */
+#ifdef CONFIG_ARCH_BUTTONS
-#define GPIO_LED_R (PIN_PTD15 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
-#define GPIO_LED_G (PIN_PTD16 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
-#define GPIO_LED_B (PIN_PTE8 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
-/* Buttons. The S32K146EVB supports two buttons:
+/****************************************************************************
+ * Name: board_button_initialize
*
- * SW2 PTC12
- * SW3 PTC13
- */
-
-#define GPIO_SW2 (PIN_PTC12 | PIN_INT_BOTH)
-#define GPIO_SW3 (PIN_PTC13 | PIN_INT_BOTH)
-
-/* SPI chip selects */
-
+ * Description:
+ * board_button_initialize() must be called to initialize button resources.
+ * After that, board_buttons() may be called to collect the current state
+ * of all buttons or board_button_irq() may be called to register button
+ * interrupt handlers.
+ *
+ ****************************************************************************/
-/* Count of peripheral clock user configurations */
+void board_button_initialize(void)
+{
+ /* Configure the GPIO pins as interrupting inputs. */
-#define NUM_OF_PERIPHERAL_CLOCKS_0 11
+ s32k1xx_pinconfig(GPIO_SW2);
+ s32k1xx_pinconfig(GPIO_SW3);
+}
/****************************************************************************
- * Public Types
+ * Name: board_buttons
****************************************************************************/
-/****************************************************************************
- * Public data
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
+uint32_t board_buttons(void)
+{
+ uint32_t ret = 0;
-/* User peripheral configuration structure 0 */
+ if (s32k1xx_gpioread(GPIO_SW2))
+ {
+ ret |= BUTTON_SW2_BIT;
+ }
-extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[];
+ if (s32k1xx_gpioread(GPIO_SW3))
+ {
+ ret |= BUTTON_SW3_BIT;
+ }
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
+ return ret;
+}
/****************************************************************************
- * Name: s32k146_bringup
+ * Button support.
*
* Description:
- * Perform architecture-specific initialization
+ * board_button_initialize() must be called to initialize button resources.
+ * After that, board_buttons() may be called to collect the current state
+ * of all buttons or board_button_irq() may be called to register button
+ * interrupt handlers.
*
- * CONFIG_BOARD_LATE_INITIALIZE=y :
- * Called from board_late_initialize().
+ * After board_button_initialize() has been called, board_buttons() may be
+ * called to collect the state of all buttons. board_buttons() returns a
+ * 32-bit bit set with each bit associated with a button. See the
+ * BUTTON_*_BIT definitions in board.h for the meaning of each bit.
*
- * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y :
- * Called from the NSH library
+ * board_button_irq() may be called to register an interrupt handler that
+ * will be called when a button is depressed or released. The ID value is
+ * a button enumeration value that uniquely identifies a button resource.
+ * See the BUTTON_* definitions in board.h for the meaning of enumeration
+ * value.
*
****************************************************************************/
-int s32k146_bringup(void);
-
-/****************************************************************************
- * Name: s32k146_spidev_initialize
- *
- * Description:
- * Called to configure SPI chip select GPIO pins for the s32k146evb
- * board.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_S32K1XX_SPI
-void s32k146_spidev_initialize(void);
+#ifdef CONFIG_ARCH_IRQBUTTONS
+int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg)
+{
+ uint32_t pinset;
+ int ret;
+
+ /* Map the button id to the GPIO bit set. */
+
+ if (id == BUTTON_SW2)
+ {
+ pinset = GPIO_SW2;
+ }
+ else if (id == BUTTON_SW3)
+ {
+ pinset = GPIO_SW3;
+ }
+ else
+ {
+ return -EINVAL;
+ }
+
+ /* The button has already been configured as an interrupting input (by
+ * board_button_initialize() above).
+ *
+ * Attach the new button handler.
+ */
+
+ ret = s32k1xx_pinirqattach(pinset, irqhandler, NULL);
+ if (ret >= 0)
+ {
+ /* Then make sure that interrupts are enabled on the pin */
+
+ s32k1xx_pinirqenable(pinset);
+ }
+
+ return ret;
+}
#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __BOARDS_ARM_S32K1XX_S32K146EVB_SRC_S32K146EVB_H */
+#endif /* CONFIG_ARCH_BUTTONS */
diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_clockconfig.c b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_clockconfig.c
new file mode 100644
index 0000000..3ad5f31
--- /dev/null
+++ b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_clockconfig.c
@@ -0,0 +1,227 @@
+/****************************************************************************
+ * boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_clockconfig.c
+ *
+ * Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Most of the settings within this file derives from NXP sample code for
+ * the S32K1XX MCUs. That sample code has this licensing information:
+ *
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "s32k1xx_clockconfig.h"
+#include "s32k1xx_start.h"
+#include "rddrone-uavcan144.h"
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* Each S32K1XX board must provide the following initialized structure.
+ * This is needed to establish the initial board clocking.
+ */
+
+const struct clock_configuration_s g_initial_clkconfig =
+{
+ .scg =
+ {
+ .sirc =
+ {
+ .range = SCG_SIRC_RANGE_HIGH, /* RANGE - High range (8 MHz) */
+ .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV1 */
+ .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV2 */
+ .initialize = true, /* Initialize */
+ .stopmode = true, /* SIRCSTEN */
+ .lowpower = true, /* SIRCLPEN */
+ .locked = false, /* LK */
+ },
+ .firc =
+ {
+ .range = SCG_FIRC_RANGE_48M, /* RANGE */
+ .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV1 */
+ .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV2 */
+ .initialize = true, /* Initialize */
+ .stopmode = false, /* */
+ .lowpower = false, /* */
+ .regulator = true, /* FIRCREGOFF */
+ .locked = false, /* LK */
+ },
+ .sosc =
+ {
+ .mode = SCG_SOSC_MONITOR_DISABLE, /* SOSCCM */
+ .gain = SCG_SOSC_GAIN_LOW, /* HGO */
+ .range = SCG_SOSC_RANGE_MID, /* RANGE */
+ .extref = SCG_SOSC_REF_OSC, /* EREFS */
+ .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV1 */
+ .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV2 */
+ .initialize = true, /* Initialize */
+ .stopmode = false, /* */
+ .lowpower = false, /* */
+ .locked = false, /* LK */
+ },
+ .spll =
+ {
+ .mode = SCG_SPLL_MONITOR_DISABLE, /* SPLLCM */
+ .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV1 */
+ .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV2 */
+ .prediv = 1, /* PREDIV */
+ .mult = 40, /* MULT */
+ .src = 0, /* SOURCE */
+ .initialize = true, /* Initialize */
+ .stopmode = false, /* */
+ .locked = false, /* LK */
+ },
+ .rtc =
+ {
+ .initialize = true, /* Initialize */
+ .clkin = 0 /* RTC_CLKIN */
+ },
+ .clockout =
+ {
+ .source = SCG_CLOCKOUT_SRC_FIRC, /* SCG CLKOUTSEL */
+ .initialize = true, /* Initialize */
+ },
+ .clockmode =
+ {
+ .rccr = /* RCCR - Run Clock Control Register */
+ {
+ .src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL, /* SCS */
+ .divslow = 3, /* DIVSLOW, range 1..16 */
+ .divbus = 2, /* DIVBUS, range 1..16 */
+ .divcore = 2 /* DIVCORE, range 1..16 */
+ },
+ .vccr = /* VCCR - VLPR Clock Control Register */
+ {
+ .src = SCG_SYSTEM_CLOCK_SRC_SIRC, /* SCS */
+ .divslow = 4, /* DIVSLOW, range 1..16 */
+ .divbus = 1, /* DIVBUS, range 1..16 */
+ .divcore = 2 /* DIVCORE, range 1..16 */
+ },
+ .hccr =
+ {
+ .src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL, /* SCS */
+ .divslow = 3, /* DIVSLOW, range 1..16 */
+ .divbus = 2, /* DIVBUS, range 1..16 */
+ .divcore = 2 /* DIVCORE, range 1..16 */
+ },
+
+ /* .altclk */
+
+ .initialize = true, /* Initialize */
+ },
+ },
+ .sim =
+ {
+ .clockout = /* Clock Out configuration. */
+ {
+ .source = SIM_CLKOUT_SEL_SYSTEM_SCG_CLKOUT, /* CLKOUTSEL */
+ .divider = 1, /* CLKOUTDIV, range 1..8 */
+ .initialize = true, /* Initialize */
+ .enable = false, /* CLKOUTEN */
+ },
+ .lpoclk = /* Low Power Clock configuration. */
+ {
+ .rtc_source = SIM_RTCCLK_SEL_SOSCDIV1_CLK, /* RTCCLKSEL */
+ .lpo_source = SIM_LPO_CLK_SEL_LPO_128K, /* LPOCLKSEL */
+ .initialize = true, /* Initialize */
+ .lpo32k = true, /* LPO32KCLKEN */
+ .lpo1k = true, /* LPO1KCLKEN */
+ },
+ .tclk = /* TCLK CLOCK configuration. */
+ {
+ .tclkfreq[0] = 0, /* TCLK0 */
+ .tclkfreq[1] = 0, /* TCLK1 */
+ .tclkfreq[2] = 0, /* TCLK2 */
+ .initialize = true, /* Initialize */
+ },
+ .platgate = /* Platform Gate Clock configuration. */
+ {
+ .initialize = true, /* Initialize */
+ .mscm = true, /* CGCMSCM */
+ .mpu = true, /* CGCMPU */
+ .dma = true, /* CGCDMA */
+ .erm = true, /* CGCERM */
+ .eim = true, /* CGCEIM */
+ },
+ .traceclk = /* Debug trace Clock Configuration. */
+ {
+ .source = CLOCK_TRACE_SRC_CORE_CLK, /* TRACECLK_SEL */
+ .divider = 1, /* TRACEDIV, range 1..8 */
+ .initialize = true, /* Initialize */
+ .enable = true, /* TRACEDIVEN */
+ .fraction = false, /* TRACEFRAC */
+ },
+#ifdef CONFIG_S32K1XX_HAVE_QSPI
+ .qspirefclk = /* Quad Spi Internal Reference Clock Gating. */
+ {
+ .refclk = false, /* Qspi reference clock gating */
+ },
+#endif
+ },
+ .pcc =
+ {
+ .count = NUM_OF_PERIPHERAL_CLOCKS_0, /* Number peripheral clock configurations */
+ .pclks = g_peripheral_clockconfig0 /* Peripheral clock configurations */
+ },
+ .pmc =
+ {
+ .lpoclk = /* Low Power Clock configuration. */
+ {
+ .trim = 0, /* Trimming value for LPO */
+ .initialize = true, /* Initialize */
+ .enable = true, /* Enable/disable LPO */
+ },
+ }
+};
diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_periphclocks.c b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_periphclocks.c
new file mode 100644
index 0000000..22be892
--- /dev/null
+++ b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_periphclocks.c
@@ -0,0 +1,187 @@
+/****************************************************************************
+ * boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_periphclks.c
+ *
+ * Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Most of the settings within this file derives from NXP sample code for
+ * the S32K1XX MCUs. That sample code has this licensing information:
+ *
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "s32k1xx_periphclocks.h"
+#include "rddrone-uavcan144.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* Each S32K1XX board must provide the following initialized structure.
+ * This is needed to establish the initial peripheral clocking.
+ */
+
+const struct peripheral_clock_config_s g_peripheral_clockconfig0[] =
+{
+ {
+ .clkname = ADC0_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_FIRC,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = ADC1_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_FIRC,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = LPI2C0_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_SIRC,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = LPSPI0_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_SIRC,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = LPSPI1_CLK,
+ .clkgate = false,
+ .clksrc = CLK_SRC_FIRC,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = LPSPI2_CLK,
+ .clkgate = false,
+ .clksrc = CLK_SRC_FIRC,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = LPTMR0_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_SIRC,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = LPUART0_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_SIRC,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = LPUART1_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_SIRC,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = LPUART2_CLK,
+ .clkgate = false,
+ .clksrc = CLK_SRC_SIRC,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = PORTA_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_OFF,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = PORTB_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_OFF,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = PORTC_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_OFF,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = PORTD_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_OFF,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = PORTE_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_OFF,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ }
+};
diff --git a/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_spi.c b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_spi.c
new file mode 100644
index 0000000..1c0588c
--- /dev/null
+++ b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_spi.c
@@ -0,0 +1,199 @@
+/****************************************************************************
+ * boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_spi.c
+ *
+ * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Author: Ivan Ucherdzhiev <iv...@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/spi/spi.h>
+#include <nuttx/spi/spi_transfer.h>
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+
+#include "s32k1xx_config.h"
+#include "s32k1xx_lpspi.h"
+#include "s32k1xx_pin.h"
+#include "rddrone-uavcan144.h"
+
+#if defined(CONFIG_S32K1XX_LPSPI0) || defined(CONFIG_S32K1XX_LPSPI1) || \
+ defined(CONFIG_S32K1XX_LPSPI2)
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: s32k1xx_spidev_initialize
+ *
+ * Description:
+ * Called to configure SPI chip select GPIO pins for the RDDRONE-UAVCAN144
+ * board.
+ *
+ ****************************************************************************/
+
+void weak_function s32k1xx_spidev_initialize(void)
+{
+#ifdef CONFIG_S32K1XX_LPSPI0
+ s32k1xx_pinconfig(PIN_LPSPI0_PCS);
+
+#ifdef CONFIG_SPI_DRIVER
+ struct spi_dev_s *g_lpspi0;
+ g_lpspi0 = s32k1xx_lpspibus_initialize(0);
+
+ if (!g_lpspi0)
+ {
+ spierr("ERROR: [boot] FAILED to initialize LPSPI0\n");
+ }
+
+ spi_register(g_lpspi0, 0);
+#endif
+#endif
+
+#ifdef CONFIG_S32K1XX_LPSPI1
+ s32k1xx_pinconfig(PIN_LPSPI1_PCS);
+
+#ifdef CONFIG_SPI_DRIVER
+ struct spi_dev_s *g_lpspi1;
+ g_lpspi1 = s32k1xx_lpspibus_initialize(1);
+
+ if (!g_lpspi1)
+ {
+ spierr("ERROR: [boot] FAILED to initialize LPSPI1\n");
+ }
+
+ spi_register(g_lpspi1, 1);
+#endif
+#endif
+
+#ifdef CONFIG_S32K1XX_LPSPI2
+ s32k1xx_pinconfig(PIN_LPSPI2_PCS);
+
+#ifdef CONFIG_SPI_DRIVER
+ struct spi_dev_s *g_lpspi2;
+ g_lpspi2 = s32k1xx_lpspibus_initialize(2);
+
+ if (!g_lpspi2)
+ {
+ spierr("ERROR: [boot] FAILED to initialize LPSPI2\n");
+ }
+
+ spi_register(g_lpspi2, 2);
+#endif
+#endif
+}
+
+/****************************************************************************
+ * Name: s32k1xx_lpspi0/1/2select and s32k1xx_lpspi0/1/2status
+ *
+ * Description:
+ * The external functions, s32k1xx_lpspi0/1/2select and
+ * s32k1xx_lpspi0/1/2status must be provided by board-specific logic.
+ * They are implementations of the select and status methods of the SPI
+ * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h).
+ * All other methods (including s32k1xx_lpspibus_initialize()) are provided
+ * by common logic. To use this common SPI logic on your board:
+ *
+ * 1. Provide logic in s32k1xx_boardinitialize() to configure SPI chip
+ * select pins.
+ * 2. Provide s32k1xx_lpspi0/1/2select() and s32k1xx_lpspi0/1/2status()
+ * functions in your board-specific logic. These functions will perform
+ * chip selection and status operations using GPIOs in the way your
+ * board is configured.
+ * 3. Add a calls to s32k1xx_lpspibus_initialize() in your low level
+ * application initialization logic
+ * 4. The handle returned by s32k1xx_lpspibus_initialize() may then be used
+ * to bind the SPI driver to higher level logic (e.g., calling
+ * mmcsd_spislotinitialize(), for example, will bind the SPI driver to
+ * the SPI MMC/SD driver).
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_S32K1XX_LPSPI0
+void s32k1xx_lpspi0select(FAR struct spi_dev_s *dev, uint32_t devid,
+ bool selected)
+{
+ spiinfo("devid: %d CS: %s\n", (int)devid,
+ selected ? "assert" : "de-assert");
+
+ s32k1xx_gpiowrite(PIN_LPSPI0_PCS, !selected);
+}
+
+uint8_t s32k1xx_lpspi0status(FAR struct spi_dev_s *dev, uint32_t devid)
+{
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_S32K1XX_LPSPI1
+void s32k1xx_lpspi1select(FAR struct spi_dev_s *dev,
+ uint32_t devid, bool selected)
+{
+ spiinfo("devid: %d CS: %s\n", (int)devid,
+ selected ? "assert" : "de-assert");
+
+ s32k1xx_gpiowrite(PIN_LPSPI1_PCS, !selected);
+}
+
+uint8_t s32k1xx_lpspi1status(FAR struct spi_dev_s *dev, uint32_t devid)
+{
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_S32K1XX_LPSPI2
+void s32k1xx_lpspi2select(FAR struct spi_dev_s *dev,
+ uint32_t devid, bool selected)
+{
+ spiinfo("devid: %d CS: %s\n", (int)devid,
+ selected ? "assert" : "de-assert");
+
+ s32k1xx_gpiowrite(PIN_LPSPI2_PCS, !selected);
+}
+
+uint8_t s32k1xx_lpspi2status(FAR struct spi_dev_s *dev, uint32_t devid)
+{
+ return 0;
+}
+#endif
+
+#endif /* CONFIG_S32K1XX_LPSPI0 || CONFIG_S32K1XX_LPSPI01 || CONFIG_S32K1XX_LPSPI2 */
diff --git a/arch/arm/src/s32k1xx/chip.h b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_userleds.c
similarity index 63%
copy from arch/arm/src/s32k1xx/chip.h
copy to boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_userleds.c
index f3f9b9c..de3e419 100644
--- a/arch/arm/src/s32k1xx/chip.h
+++ b/boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_userleds.c
@@ -1,5 +1,5 @@
-/************************************************************************************
- * arch/arm/src/s32k1xx/chip.h
+/****************************************************************************
+ * boards/arm/s32k1xx/rddrone-uavcan144/src/s32k1xx_userleds.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -31,47 +31,86 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ************************************************************************************/
+ ****************************************************************************/
-#ifndef __ARCH_ARM_SRC_S32K1XX_CHIP_H
-#define __ARCH_ARM_SRC_S32K1XX_CHIP_H
-
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
-/* Include the memory map and the chip definitions file. Other chip hardware files
- * should then include this file for the proper setup.
- */
-
-#include <arch/irq.h>
-#include "hardware/s32k1xx_memorymap.h"
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
-/* The common ARMv6/7-M vector handling logic expects the following definitions in
- * this file. ARMV6/7M_PERIPHERAL_INTERRUPTS provides the number of supported
- * external interrupts which, for this architecture, is provided in the
- * arch/s32k1xx/irq.h header file.
- */
+#include <nuttx/board.h>
-#define ARMV6M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT
-#define ARMV7M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT
+#include "up_arch.h"
+#include "up_internal.h"
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
+#include "s32k1xx_pin.h"
+#include "rddrone-uavcan144.h"
-/************************************************************************************
- * Public Types
- ************************************************************************************/
+#include <arch/board/board.h>
-/************************************************************************************
- * Public Data
- ************************************************************************************/
+#ifndef CONFIG_ARCH_LEDS
-/************************************************************************************
+/****************************************************************************
* Public Functions
- ************************************************************************************/
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_userled_initialize
+ ****************************************************************************/
+
+void board_userled_initialize(void)
+{
+ /* Configure LED GPIOs for output */
+
+ s32k1xx_pinconfig(GPIO_LED_R);
+ s32k1xx_pinconfig(GPIO_LED_G);
+ s32k1xx_pinconfig(GPIO_LED_B);
+}
+
+/****************************************************************************
+ * Name: board_userled
+ ****************************************************************************/
+
+void board_userled(int led, bool ledon)
+{
+ uint32_t ledcfg;
+
+ if (led == BOARD_LED_R)
+ {
+ ledcfg = GPIO_LED_R;
+ }
+ else if (led == BOARD_LED_G)
+ {
+ ledcfg = GPIO_LED_G;
+ }
+ else if (led == BOARD_LED_B)
+ {
+ ledcfg = GPIO_LED_B;
+ }
+ else
+ {
+ return;
+ }
+
+ s32k1xx_gpiowrite(ledcfg, ledon); /* High illuminates */
+}
+
+/****************************************************************************
+ * Name: board_userled_all
+ ****************************************************************************/
+
+void board_userled_all(uint8_t ledset)
+{
+ /* Low illuminates */
+
+ s32k1xx_gpiowrite(GPIO_LED_R, (ledset & BOARD_LED_R_BIT) != 0);
+ s32k1xx_gpiowrite(GPIO_LED_G, (ledset & BOARD_LED_G_BIT) != 0);
+ s32k1xx_gpiowrite(GPIO_LED_B, (ledset & BOARD_LED_B_BIT) != 0);
+}
-#endif /* __ARCH_ARM_SRC_S32K1XX_CHIP_H */
+#endif /* !CONFIG_ARCH_LEDS */
diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/Kconfig b/boards/arm/s32k1xx/rddrone-uavcan146/Kconfig
new file mode 100644
index 0000000..77a4ee5
--- /dev/null
+++ b/boards/arm/s32k1xx/rddrone-uavcan146/Kconfig
@@ -0,0 +1,8 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_BOARD_RDDRONE_UAVCAN146
+
+endif # ARCH_BOARD_RDDRONE_UAVCAN146
diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/README.txt b/boards/arm/s32k1xx/rddrone-uavcan146/README.txt
new file mode 100644
index 0000000..86cb1a8
--- /dev/null
+++ b/boards/arm/s32k1xx/rddrone-uavcan146/README.txt
@@ -0,0 +1,15 @@
+README
+======
+
+This directory holds the port to the NXP RDDRONE-UAVCAN board with S32K146 MCU.
+
+Contents
+========
+
+ o Status
+
+Status
+======
+
+ 2020-01-23: Configuration created (copy-paste from S32K146EVB).
+ Tested: Serial console
\ No newline at end of file
diff --git a/boards/arm/s32k1xx/s32k146evb/configs/nsh/defconfig b/boards/arm/s32k1xx/rddrone-uavcan146/configs/nsh/defconfig
similarity index 67%
copy from boards/arm/s32k1xx/s32k146evb/configs/nsh/defconfig
copy to boards/arm/s32k1xx/rddrone-uavcan146/configs/nsh/defconfig
index e409d5a..80bed11 100644
--- a/boards/arm/s32k1xx/s32k146evb/configs/nsh/defconfig
+++ b/boards/arm/s32k1xx/rddrone-uavcan146/configs/nsh/defconfig
@@ -10,19 +10,27 @@
# CONFIG_NSH_CMDOPT_HEXDUMP is not set
# CONFIG_NSH_CMDPARMS is not set
CONFIG_ARCH="arm"
-CONFIG_ARCH_BOARD="s32k146evb"
-CONFIG_ARCH_BOARD_S32K146EVB=y
+CONFIG_ARCH_BOARD="rddrone-uavcan146"
+CONFIG_ARCH_BOARD_RDDRONE_UAVCAN146=y
CONFIG_ARCH_CHIP="s32k1xx"
CONFIG_ARCH_CHIP_S32K146=y
CONFIG_ARCH_CHIP_S32K14X=y
CONFIG_ARCH_CHIP_S32K1XX=y
CONFIG_ARCH_STACKDUMP=y
-CONFIG_BOARD_LOOPSPERMSEC=2988
+CONFIG_BOARD_LOOPSPERMSEC=3997
CONFIG_BUILTIN=y
CONFIG_EXAMPLES_HELLO=y
CONFIG_FS_PROCFS=y
CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_I2C=y
+CONFIG_I2CTOOL_DEFFREQ=100000
+CONFIG_I2CTOOL_MAXADDR=0x7f
+CONFIG_I2CTOOL_MAXBUS=0
+CONFIG_I2CTOOL_MINADDR=0x00
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LPUART0_RXBUFSIZE=64
+CONFIG_LPUART0_TXBUFSIZE=64
CONFIG_LPUART1_RXBUFSIZE=64
CONFIG_LPUART1_SERIAL_CONSOLE=y
CONFIG_LPUART1_TXBUFSIZE=64
@@ -38,17 +46,26 @@ CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_MQ_MSGS=4
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=16
-CONFIG_RAM_SIZE=23552
-CONFIG_RAM_START=0x1ffffc00
+CONFIG_RAM_SIZE=126976
+CONFIG_RAM_START=0x1fff0000
+CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
+CONFIG_S32K1XX_LPI2C0=y
+CONFIG_S32K1XX_LPSPI0=y
+CONFIG_S32K1XX_LPUART0=y
CONFIG_S32K1XX_LPUART1=y
CONFIG_SCHED_WAITPID=y
CONFIG_SDCLONE_DISABLE=y
+CONFIG_SPITOOL_DEFFREQ=400000
+CONFIG_SPITOOL_MAXBUS=0
+CONFIG_SPITOOL_PROGNAME="spi"
CONFIG_START_DAY=18
CONFIG_START_MONTH=8
CONFIG_START_YEAR=2019
CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_SYMTAB_ORDEREDBYNAME=y
+CONFIG_SYSTEM_I2CTOOL=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_NSH_CXXINITIALIZE=y
-CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_SYSTEM_SPITOOL=y
+CONFIG_USER_ENTRYPOINT="nsh_main"
\ No newline at end of file
diff --git a/boards/arm/s32k1xx/s32k146evb/configs/nsh/defconfig b/boards/arm/s32k1xx/rddrone-uavcan146/configs/nshdebug/defconfig
similarity index 66%
copy from boards/arm/s32k1xx/s32k146evb/configs/nsh/defconfig
copy to boards/arm/s32k1xx/rddrone-uavcan146/configs/nshdebug/defconfig
index e409d5a..a7a81e4 100644
--- a/boards/arm/s32k1xx/s32k146evb/configs/nsh/defconfig
+++ b/boards/arm/s32k1xx/rddrone-uavcan146/configs/nshdebug/defconfig
@@ -10,19 +10,29 @@
# CONFIG_NSH_CMDOPT_HEXDUMP is not set
# CONFIG_NSH_CMDPARMS is not set
CONFIG_ARCH="arm"
-CONFIG_ARCH_BOARD="s32k146evb"
-CONFIG_ARCH_BOARD_S32K146EVB=y
+CONFIG_ARCH_BOARD="rddrone-uavcan146"
+CONFIG_ARCH_BOARD_RDDRONE_UAVCAN146=y
CONFIG_ARCH_CHIP="s32k1xx"
CONFIG_ARCH_CHIP_S32K146=y
CONFIG_ARCH_CHIP_S32K14X=y
CONFIG_ARCH_CHIP_S32K1XX=y
CONFIG_ARCH_STACKDUMP=y
-CONFIG_BOARD_LOOPSPERMSEC=2988
+CONFIG_BOARD_LOOPSPERMSEC=3997
CONFIG_BUILTIN=y
+CONFIG_DEBUG_FEATURES=y
+CONFIG_DEBUG_SYMBOLS=y
CONFIG_EXAMPLES_HELLO=y
CONFIG_FS_PROCFS=y
CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_I2C=y
+CONFIG_I2CTOOL_DEFFREQ=100000
+CONFIG_I2CTOOL_MAXADDR=0x7f
+CONFIG_I2CTOOL_MAXBUS=0
+CONFIG_I2CTOOL_MINADDR=0x00
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LPUART0_RXBUFSIZE=64
+CONFIG_LPUART0_TXBUFSIZE=64
CONFIG_LPUART1_RXBUFSIZE=64
CONFIG_LPUART1_SERIAL_CONSOLE=y
CONFIG_LPUART1_TXBUFSIZE=64
@@ -38,17 +48,26 @@ CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_MQ_MSGS=4
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=16
-CONFIG_RAM_SIZE=23552
-CONFIG_RAM_START=0x1ffffc00
+CONFIG_RAM_SIZE=126976
+CONFIG_RAM_START=0x1fff0000
+CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
+CONFIG_S32K1XX_LPI2C0=y
+CONFIG_S32K1XX_LPSPI0=y
+CONFIG_S32K1XX_LPUART0=y
CONFIG_S32K1XX_LPUART1=y
CONFIG_SCHED_WAITPID=y
CONFIG_SDCLONE_DISABLE=y
+CONFIG_SPITOOL_DEFFREQ=400000
+CONFIG_SPITOOL_MAXBUS=0
+CONFIG_SPITOOL_PROGNAME="spi"
CONFIG_START_DAY=18
CONFIG_START_MONTH=8
CONFIG_START_YEAR=2019
CONFIG_STDIO_DISABLE_BUFFERING=y
CONFIG_SYMTAB_ORDEREDBYNAME=y
+CONFIG_SYSTEM_I2CTOOL=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_NSH_CXXINITIALIZE=y
-CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_SYSTEM_SPITOOL=y
+CONFIG_USER_ENTRYPOINT="nsh_main"
\ No newline at end of file
diff --git a/boards/arm/s32k1xx/s32k146evb/include/board.h b/boards/arm/s32k1xx/rddrone-uavcan146/include/board.h
similarity index 79%
copy from boards/arm/s32k1xx/s32k146evb/include/board.h
copy to boards/arm/s32k1xx/rddrone-uavcan146/include/board.h
index da991a1..c0ab9d1 100644
--- a/boards/arm/s32k1xx/s32k146evb/include/board.h
+++ b/boards/arm/s32k1xx/rddrone-uavcan146/include/board.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/arm/s32k1xx/s32k146evb/include/board.h
+ * boards/arm/s32k1xx/rddrone-uavcan146/include/board.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -33,8 +33,8 @@
*
****************************************************************************/
-#ifndef __BOARDS_ARM_STM32F4DISCOVERY_INCLUDE_BOARD_H
-#define __BOARDS_ARM_STM32F4DISCOVERY_INCLUDE_BOARD_H
+#ifndef __BOARDS_ARM_RDDRONE_UAVCAN146_INCLUDE_BOARD_H
+#define __BOARDS_ARM_RDDRONE_UAVCAN146_INCLUDE_BOARD_H
/****************************************************************************
* Included Files
@@ -53,7 +53,7 @@
/* Clocking *****************************************************************/
-/* The S32K146EVB is fitted with a 8MHz Crystal */
+/* The RDDRONE-UAVCAN146 is fitted with a 8MHz Crystal */
#define BOARD_XTAL_FREQUENCY 8000000
@@ -61,7 +61,7 @@
/* LED definitions **********************************************************/
-/* The S32K146EVB has one RGB LED:
+/* The RDDRONE-UAVCAN146 has one RGB LED:
*
* RedLED PTD15 (FTM0 CH0)
* GreenLED PTD16 (FTM0 CH1)
@@ -89,9 +89,8 @@
#define BOARD_LED_B_BIT (1 << BOARD_LED_B)
/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LEDs on board
- * the s32k146evb. The following definitions describe how NuttX controls the
- * LEDs:
- *
+ * the RDDRONE-UAVCAN146. The following definitions describe how NuttX
+ * controls the LEDs:
*
* SYMBOL Meaning LED state
* RED GREEN BLUE
@@ -106,11 +105,11 @@
#define LED_SIGNAL 0 /* In a signal handler (no change) */
#define LED_ASSERTION 0 /* An assertion failed (no change) */
#define LED_PANIC 4 /* The system has crashed FLASH OFF OFF */
-#undef LED_IDLE /* S32K146EVN in sleep mode (Not used) */
+#undef LED_IDLE /* RDDRONE-UAVCAN146 in sleep mode (Not used) */
/* Button definitions *******************************************************/
-/* The S32K146EVB supports two buttons:
+/* The RDDRONE-UAVCAN146 supports two buttons:
*
* SW2 PTC12
* SW3 PTC13
@@ -131,10 +130,24 @@
* OpenSDA UART RX PTC6 (LPUART1_RX)
*/
+#define PIN_LPUART0_CTS PIN_LPUART0_CTS_2 /* PTC8 */
+#define PIN_LPUART0_RTS PIN_LPUART0_RTS_2 /* PTC9 */
+#define PIN_LPUART0_RX PIN_LPUART0_RX_1 /* PTB0 */
+#define PIN_LPUART0_TX PIN_LPUART0_TX_1 /* PTB1 */
+
#define PIN_LPUART1_RX PIN_LPUART1_RX_1 /* PTC6 */
#define PIN_LPUART1_TX PIN_LPUART1_TX_1 /* PTC7 */
-/* DMA Channel/Stream Selections ********************************************/
+/* SPI selections ***********************************************************/
+
+#define PIN_LPSPI0_SCK PIN_LPSPI0_SCK_2 /* PTB2 */
+#define PIN_LPSPI0_MISO PIN_LPSPI0_SIN_2 /* PTB3 */
+#define PIN_LPSPI0_MOSI PIN_LPSPI0_SOUT_3 /* PTB4 */
+#define PIN_LPSPI0_PCS PIN_LPSPI0_PCS0_2 /* PTB5 */
+
+/* I2C selections ***********************************************************/
+#define PIN_LPI2C0_SCL PIN_LPI2C0_SCL_2 /* PTA3 */
+#define PIN_LPI2C0_SDA PIN_LPI2C0_SDA_2 /* PTA2 */
-#endif /* __BOARDS_ARM_STM32F4DISCOVERY_INCLUDE_BOARD_H */
+#endif /* __BOARDS_ARM_RDDRONE_UAVCAN146_INCLUDE_BOARD_H */
diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/scripts/Make.defs b/boards/arm/s32k1xx/rddrone-uavcan146/scripts/Make.defs
new file mode 100644
index 0000000..6f0e0a6
--- /dev/null
+++ b/boards/arm/s32k1xx/rddrone-uavcan146/scripts/Make.defs
@@ -0,0 +1,131 @@
+############################################################################
+# boards/arm/s32k1xx/rddrone-uavcan146/scripts/Make.defs
+#
+# Copyright (C) 2018 Gregory Nutt. All rights reserved.
+# Author: Gregory Nutt <gn...@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+# used to endorse or promote products derived from this software
+# without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+include ${TOPDIR}/.config
+include ${TOPDIR}/tools/Config.mk
+include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs
+
+ifeq ($(CONFIG_BOOT_RUNFROMFLASH),y)
+ LDSCRIPT = flash.ld
+else ifeq ($(CONFIG_BOOT_RUNFROMISRAM),y)
+ LDSCRIPT = sram.ld
+endif
+
+$(warning, LDSCRIPT is $(LDSCRIPT))
+ifeq ($(WINTOOL),y)
+ # Windows-native toolchains
+ ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
+ ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
+ ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
+else
+ # Linux/Cygwin-native toolchain
+ ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
+ ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
+ ARCHSCRIPT = -T$(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
+endif
+$(warning, LDSCRIPT is $(LDSCRIPT))
+$(warning, ARCHSCRIPT is $(ARCHSCRIPT))
+
+CC = $(CROSSDEV)gcc
+CXX = $(CROSSDEV)g++
+CPP = $(CROSSDEV)gcc -E
+LD = $(CROSSDEV)ld
+STRIP = $(CROSSDEV)strip --strip-unneeded
+AR = $(ARCROSSDEV)ar rcs
+NM = $(ARCROSSDEV)nm
+OBJCOPY = $(CROSSDEV)objcopy
+OBJDUMP = $(CROSSDEV)objdump
+
+ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
+ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
+
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+ ARCHOPTIMIZATION = -g
+endif
+
+ifneq ($(CONFIG_DEBUG_NOOPT),y)
+ ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
+endif
+
+ARCHCFLAGS = -fno-builtin
+ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
+ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
+ARCHWARNINGSXX = -Wall -Wshadow -Wundef
+ARCHDEFINES =
+ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
+
+CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
+AFLAGS = $(CFLAGS) -D__ASSEMBLY__
+
+NXFLATLDFLAGS1 = -r -d -warn-common
+NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
+LDNXFLATFLAGS = -e main -s 2048
+
+ASMEXT = .S
+OBJEXT = .o
+LIBEXT = .a
+EXEEXT =
+
+ifneq ($(CROSSDEV),arm-nuttx-elf-)
+ LDFLAGS += -nostartfiles -nodefaultlibs
+endif
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+ LDFLAGS += -g
+endif
+
+
+HOSTCC = gcc
+HOSTINCLUDES = -I.
+HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
+HOSTLDFLAGS =
+ifeq ($(CONFIG_HOST_WINDOWS),y)
+ HOSTEXEEXT = .exe
+else
+ HOSTEXEEXT =
+endif
+
+ifeq ($(WINTOOL),y)
+ # Windows-native host tools
+ DIRLINK = $(TOPDIR)/tools/copydir.sh
+ DIRUNLINK = $(TOPDIR)/tools/unlink.sh
+ MKDEP = $(TOPDIR)/tools/mkwindeps.sh
+else
+ # Linux/Cygwin-native host tools
+ MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
+endif
diff --git a/boards/arm/s32k1xx/s32k148evb/scripts/flash.ld b/boards/arm/s32k1xx/rddrone-uavcan146/scripts/flash.ld
similarity index 91%
copy from boards/arm/s32k1xx/s32k148evb/scripts/flash.ld
copy to boards/arm/s32k1xx/rddrone-uavcan146/scripts/flash.ld
index b59ab9b..8d08125 100644
--- a/boards/arm/s32k1xx/s32k148evb/scripts/flash.ld
+++ b/boards/arm/s32k1xx/rddrone-uavcan146/scripts/flash.ld
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/arm/s32k1xx/s32k148evb/scripts/flash.ld
+ * boards/arm/s32k1xx/rddrone-uavcan146/scripts/flash.ld
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -33,23 +33,23 @@
*
****************************************************************************/
-/* The S32K148 has 2Mb of FLASH beginning at address 0x0000:0000 and
- * 252Kb of SRAM beginning at address 0x1ffe:0000 (plus 4Kb of FlexRAM)
+/* The S32K146 has 1Mb of FLASH beginning at address 0x0000:0000 and
+ * 124Kb of SRAM beginning at address 0x1fff:0000 (plus 4Kb of FlexRAM)
*
* The on-chip RAM is split in two regions: SRAM_L and SRAM_U. The RAM is
* implemented such that the SRAM_L and SRAM_U ranges form a contiguous
* block in the memory map
*
- * SRAM_L 1ffe0000 - 1fffffff 128Kb
- * SRAM_U 20000000 - 2001efff 124Kb
+ * SRAM_L 1fff0000 - 1fffffff 64Kb
+ * SRAM_U 20000000 - 2000efff 60Kb
*/
MEMORY
{
vflash (rx) : ORIGIN = 0x00000000, LENGTH = 1K
pflash (rx) : ORIGIN = 0x00000400, LENGTH = 16
- dflash (rx) : ORIGIN = 0x00000410, LENGTH = 2047K-16
- sram (rwx) : ORIGIN = 0x1fff0000, LENGTH = 252K
+ dflash (rx) : ORIGIN = 0x00000410, LENGTH = 1023K-16
+ sram (rwx) : ORIGIN = 0x1fff0000, LENGTH = 124K
}
OUTPUT_ARCH(arm)
diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/scripts/s32k146.cfg b/boards/arm/s32k1xx/rddrone-uavcan146/scripts/s32k146.cfg
new file mode 100644
index 0000000..749facc
--- /dev/null
+++ b/boards/arm/s32k1xx/rddrone-uavcan146/scripts/s32k146.cfg
@@ -0,0 +1,58 @@
+#
+# NXP S32K146 - 1x ARM Cortex-M4 @ up to 180 MHz
+#
+
+adapter_khz 4000
+transport select swd
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME s32k146
+}
+
+#
+# M4 JTAG mode TAP
+#
+if { [info exists M4_JTAG_TAPID] } {
+ set _M4_JTAG_TAPID $M4_JTAG_TAPID
+} else {
+ set _M4_JTAG_TAPID 0x4ba00477
+}
+
+#
+# M4 SWD mode TAP
+#
+if { [info exists M4_SWD_TAPID] } {
+ set _M4_SWD_TAPID $M4_SWD_TAPID
+} else {
+ set _M4_SWD_TAPID 0x2ba01477
+}
+
+source [find target/swj-dp.tcl]
+
+if { [using_jtag] } {
+ set _M4_TAPID $_M4_JTAG_TAPID
+} else {
+ set _M4_TAPID $_M4_SWD_TAPID
+}
+
+swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
+ -expected-id $_M4_TAPID
+
+target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4
+
+# S32K146 has 64+60 KB contiguous SRAM
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ set _WORKAREASIZE 0x1F000
+}
+$_CHIPNAME.m4 configure -work-area-phys 0x1FFF0000 \
+ -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+$_CHIPNAME.m4 configure -rtos nuttx
+
+if { ![using_hla] } {
+ cortex_m reset_config vectreset
+}
diff --git a/boards/arm/s32k1xx/s32k148evb/scripts/sram.ld b/boards/arm/s32k1xx/rddrone-uavcan146/scripts/sram.ld
similarity index 90%
copy from boards/arm/s32k1xx/s32k148evb/scripts/sram.ld
copy to boards/arm/s32k1xx/rddrone-uavcan146/scripts/sram.ld
index c5819bf..ff18d0e 100644
--- a/boards/arm/s32k1xx/s32k148evb/scripts/sram.ld
+++ b/boards/arm/s32k1xx/rddrone-uavcan146/scripts/sram.ld
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/arm/s32k1xx/s32k148evb/scripts/sram.ld
+ * boards/arm/s32k1xx/rddrone-uavcan146/scripts/sram.ld
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -33,21 +33,21 @@
*
****************************************************************************/
-/* The S32K148 has 2Mb of FLASH beginning at address 0x0000:0000 and
- * 252Kb of SRAM beginning at address 0x1ffe:0000 (plus 4Kb of FlexRAM)
+/* The S32K146 has 1Mb of FLASH beginning at address 0x0000:0000 and
+ * 124Kb of SRAM beginning at address 0x1fff:0000 (plus 4Kb of FlexRAM)
*
* The on-chip RAM is split in two regions: SRAM_L and SRAM_U. The RAM is
* implemented such that the SRAM_L and SRAM_U ranges form a contiguous
* block in the memory map
*
- * SRAM_L 1ffe0000 - 1fffffff 128Kb
- * SRAM_U 20000000 - 2001efff 124Kb
+ * SRAM_L 1fff0000 - 1fffffff 64Kb
+ * SRAM_U 20000000 - 2000efff 60Kb
*/
MEMORY
{
- flash (rx) : ORIGIN = 0x00000000, LENGTH = 2M
- sram (rwx) : ORIGIN = 0x1fff0000, LENGTH = 252K
+ flash (rx) : ORIGIN = 0x00000000, LENGTH = 1M
+ sram (rwx) : ORIGIN = 0x1fff0000, LENGTH = 124K
}
OUTPUT_ARCH(arm)
diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/src/.gitignore b/boards/arm/s32k1xx/rddrone-uavcan146/src/.gitignore
new file mode 100644
index 0000000..726d936
--- /dev/null
+++ b/boards/arm/s32k1xx/rddrone-uavcan146/src/.gitignore
@@ -0,0 +1,2 @@
+/.depend
+/Make.dep
diff --git a/boards/arm/s32k1xx/s32k146evb/src/Makefile b/boards/arm/s32k1xx/rddrone-uavcan146/src/Makefile
similarity index 85%
copy from boards/arm/s32k1xx/s32k146evb/src/Makefile
copy to boards/arm/s32k1xx/rddrone-uavcan146/src/Makefile
index 5237a26..bbae865 100644
--- a/boards/arm/s32k1xx/s32k146evb/src/Makefile
+++ b/boards/arm/s32k1xx/rddrone-uavcan146/src/Makefile
@@ -1,5 +1,5 @@
############################################################################
-# boards/arm/s32k1xx/s32k146evb/src/Makefile
+# boards/arm/s32k1xx/rddrone-uavcan146/src/Makefile
#
# Copyright (C) 2019 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gn...@nuttx.org>
@@ -36,21 +36,25 @@
-include $(TOPDIR)/Make.defs
ASRCS =
-CSRCS = s32k146_boot.c s32k146_bringup.c s32k146_clockconfig.c
-CSRCS += s32k146_periphclocks.c
+CSRCS = s32k1xx_boot.c s32k1xx_bringup.c s32k1xx_clockconfig.c
+CSRCS += s32k1xx_periphclocks.c
ifeq ($(CONFIG_ARCH_LEDS),y)
-CSRCS += s32k146_autoleds.c
+CSRCS += s32k1xx_autoleds.c
else
-CSRCS += s32k146_userleds.c
+CSRCS += s32k1xx_userleds.c
endif
ifeq ($(CONFIG_ARCH_BUTTONS),y)
-CSRCS += s32k146_buttons.c
+CSRCS += s32k1xx_buttons.c
endif
ifeq ($(CONFIG_LIB_BOARDCTL),y)
-CSRCS += s32k146_appinit.c
+CSRCS += s32k1xx_appinit.c
+endif
+
+ifeq ($(CONFIG_S32K1XX_LPSPI),y)
+CSRCS += s32k1xx_spi.c
endif
include $(TOPDIR)/boards/Board.mk
diff --git a/boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h b/boards/arm/s32k1xx/rddrone-uavcan146/src/rddrone-uavcan146.h
similarity index 82%
copy from boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h
copy to boards/arm/s32k1xx/rddrone-uavcan146/src/rddrone-uavcan146.h
index 13cfc0c..a4f2764 100644
--- a/boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h
+++ b/boards/arm/s32k1xx/rddrone-uavcan146/src/rddrone-uavcan146.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h
+ * boards/arm/s32k1xx/rddrone-uavcan146/src/rddrone-uavcan146.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -33,8 +33,8 @@
*
****************************************************************************/
-#ifndef __BOARDS_ARM_S32K1XX_S32K146EVB_SRC_S32K146EVB_H
-#define __BOARDS_ARM_S32K1XX_S32K146EVB_SRC_S32K146EVB_H
+#ifndef __BOARDS_ARM_S32K1XX_RDDRONE_UAVCAN146_SRC_RDDRONE_UAVCAN146_H
+#define __BOARDS_ARM_S32K1XX_RDDRONE_UAVCAN146_SRC_RDDRONE_UAVCAN146_H
/****************************************************************************
* Included Files
@@ -54,9 +54,9 @@
/* Configuration ************************************************************/
-/* S32K146EVB GPIOs *********************************************************/
+/* RDDRONE-UAVCAN146 GPIOs **************************************************/
-/* LEDs. The S32K146EVB has one RGB LED:
+/* LEDs. The RDDRONE-UAVCAN146 has one RGB LED:
*
* RedLED PTD15 (FTM0 CH0)
* GreenLED PTD16 (FTM0 CH1)
@@ -67,9 +67,9 @@
#define GPIO_LED_R (PIN_PTD15 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
#define GPIO_LED_G (PIN_PTD16 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
-#define GPIO_LED_B (PIN_PTE8 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
+#define GPIO_LED_B (PIN_PTD0 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
-/* Buttons. The S32K146EVB supports two buttons:
+/* Buttons. The RDDRONE-UAVCAN146 supports two buttons:
*
* SW2 PTC12
* SW3 PTC13
@@ -80,17 +80,20 @@
/* SPI chip selects */
+/* SE050 Enable */
+
+#define GPIO_SE050_EN (PIN_PTA6 | GPIO_LOWDRIVE)
/* Count of peripheral clock user configurations */
-#define NUM_OF_PERIPHERAL_CLOCKS_0 11
+#define NUM_OF_PERIPHERAL_CLOCKS_0 15
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
- * Public data
+ * Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
@@ -100,11 +103,11 @@
extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[];
/****************************************************************************
- * Public Functions
+ * Public Function Prototypes
****************************************************************************/
/****************************************************************************
- * Name: s32k146_bringup
+ * Name: s32k1xx_bringup
*
* Description:
* Perform architecture-specific initialization
@@ -117,20 +120,20 @@ extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[];
*
****************************************************************************/
-int s32k146_bringup(void);
+int s32k1xx_bringup(void);
/****************************************************************************
- * Name: s32k146_spidev_initialize
+ * Name: s32k1xx_spidev_initialize
*
* Description:
- * Called to configure SPI chip select GPIO pins for the s32k146evb
+ * Called to configure SPI chip select GPIO pins for the RDDRONE-UAVCAN146
* board.
*
****************************************************************************/
-#ifdef CONFIG_S32K1XX_SPI
-void s32k146_spidev_initialize(void);
+#ifdef CONFIG_S32K1XX_LPSPI
+void s32k1xx_spidev_initialize(void);
#endif
#endif /* __ASSEMBLY__ */
-#endif /* __BOARDS_ARM_S32K1XX_S32K146EVB_SRC_S32K146EVB_H */
+#endif /* __BOARDS_ARM_S32K1XX_RDDRONE_UAVCAN146_SRC_RDDRONE_UAVCAN146_H */
diff --git a/arch/arm/src/s32k1xx/chip.h b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_appinit.c
similarity index 58%
copy from arch/arm/src/s32k1xx/chip.h
copy to boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_appinit.c
index f3f9b9c..54e98d5 100644
--- a/arch/arm/src/s32k1xx/chip.h
+++ b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_appinit.c
@@ -1,5 +1,5 @@
-/************************************************************************************
- * arch/arm/src/s32k1xx/chip.h
+/****************************************************************************
+ * boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_appinit.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -31,47 +31,64 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ************************************************************************************/
+ ****************************************************************************/
-#ifndef __ARCH_ARM_SRC_S32K1XX_CHIP_H
-#define __ARCH_ARM_SRC_S32K1XX_CHIP_H
-
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
-/* Include the memory map and the chip definitions file. Other chip hardware files
- * should then include this file for the proper setup.
- */
+#include <nuttx/board.h>
-#include <arch/irq.h>
-#include "hardware/s32k1xx_memorymap.h"
+#include "rddrone-uavcan146.h"
-/* The common ARMv6/7-M vector handling logic expects the following definitions in
- * this file. ARMV6/7M_PERIPHERAL_INTERRUPTS provides the number of supported
- * external interrupts which, for this architecture, is provided in the
- * arch/s32k1xx/irq.h header file.
- */
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
-#define ARMV6M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT
-#define ARMV7M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT
+#ifndef OK
+# define OK 0
+#endif
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
-/************************************************************************************
- * Public Types
- ************************************************************************************/
+/****************************************************************************
+ * Name: board_app_initialize
+ *
+ * Description:
+ * Perform application specific initialization. This function is never
+ * called directly from application code, but only indirectly via the
+ * (non-standard) boardctl() interface using the command BOARDIOC_INIT.
+ *
+ * Input Parameters:
+ * arg - The boardctl() argument is passed to the board_app_initialize()
+ * implementation without modification. The argument has no
+ * meaning to NuttX; the meaning of the argument is a contract
+ * between the board-specific initialization logic and the
+ * matching application logic. The value cold be such things as a
+ * mode enumeration value, a set of DIP switch switch settings, a
+ * pointer to configuration data read from a file or serial FLASH,
+ * or whatever you would like to do with it. Every implementation
+ * should accept zero/NULL as a default configuration.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned on
+ * any failure to indicate the nature of the failure.
+ *
+ ****************************************************************************/
-/************************************************************************************
- * Public Data
- ************************************************************************************/
+int board_app_initialize(uintptr_t arg)
+{
+#ifdef CONFIG_BOARD_LATE_INITIALIZE
+ /* Board initialization already performed by board_late_initialize() */
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
+ return OK;
+#else
+ /* Perform board-specific initialization */
-#endif /* __ARCH_ARM_SRC_S32K1XX_CHIP_H */
+ return s32k1xx_bringup();
+#endif
+}
diff --git a/boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_autoleds.c
similarity index 52%
copy from boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h
copy to boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_autoleds.c
index 13cfc0c..a766850 100644
--- a/boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h
+++ b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_autoleds.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h
+ * boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_autoleds.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -33,104 +33,133 @@
*
****************************************************************************/
-#ifndef __BOARDS_ARM_S32K1XX_S32K146EVB_SRC_S32K146EVB_H
-#define __BOARDS_ARM_S32K1XX_S32K146EVB_SRC_S32K146EVB_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-#include <nuttx/compiler.h>
-
-#include <stdint.h>
-
-#include "hardware/s32k1xx_pinmux.h"
-#include "s32k1xx_periphclocks.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* Configuration ************************************************************/
-
-/* S32K146EVB GPIOs *********************************************************/
-
-/* LEDs. The S32K146EVB has one RGB LED:
+/* The RDDRONE-UAVCAN146 has one RGB LED:
*
* RedLED PTD15 (FTM0 CH0)
* GreenLED PTD16 (FTM0 CH1)
* BlueLED PTD0 (FTM0 CH2)
*
* An output of '1' illuminates the LED.
+ *
+ * If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board
+ * the Freedom K66F. The following definitions describe how NuttX controls
+ * the LEDs:
+ *
+ * SYMBOL Meaning LED state
+ * RED GREEN BLUE
+ * ------------------- ----------------------- -----------------
+ * LED_STARTED NuttX has been started OFF OFF OFF
+ * LED_HEAPALLOCATE Heap has been allocated OFF OFF ON
+ * LED_IRQSENABLED Interrupts enabled OFF OFF ON
+ * LED_STACKCREATED Idle stack created OFF ON OFF
+ * LED_INIRQ In an interrupt (no change)
+ * LED_SIGNAL In a signal handler (no change)
+ * LED_ASSERTION An assertion failed (no change)
+ * LED_PANIC The system has crashed FLASH OFF OFF
+ * LED_IDLE K66 is in sleep mode (Optional, not used)
*/
-#define GPIO_LED_R (PIN_PTD15 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
-#define GPIO_LED_G (PIN_PTD16 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
-#define GPIO_LED_B (PIN_PTE8 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
-/* Buttons. The S32K146EVB supports two buttons:
- *
- * SW2 PTC12
- * SW3 PTC13
- */
+#include <nuttx/config.h>
-#define GPIO_SW2 (PIN_PTC12 | PIN_INT_BOTH)
-#define GPIO_SW3 (PIN_PTC13 | PIN_INT_BOTH)
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
-/* SPI chip selects */
+#include <nuttx/board.h>
+#include <arch/board/board.h>
+#include "up_arch.h"
+#include "up_internal.h"
-/* Count of peripheral clock user configurations */
+#include "s32k1xx_pin.h"
+#include "rddrone-uavcan146.h"
-#define NUM_OF_PERIPHERAL_CLOCKS_0 11
+#include <arch/board/board.h>
-/****************************************************************************
- * Public Types
- ****************************************************************************/
+#ifdef CONFIG_ARCH_LEDS
/****************************************************************************
- * Public data
+ * Pre-processor Definitions
****************************************************************************/
-#ifndef __ASSEMBLY__
+/* Summary of all possible settings */
-/* User peripheral configuration structure 0 */
-
-extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[];
+#define LED_NOCHANGE 0 /* LED_IRQSENABLED, LED_INIRQ, LED_SIGNAL, LED_ASSERTION */
+#define LED_OFF_OFF_OFF 1 /* LED_STARTED */
+#define LED_OFF_OFF_ON 2 /* LED_HEAPALLOCATE */
+#define LED_OFF_ON_OFF 3 /* LED_STACKCREATED */
+#define LED_ON_OFF_OFF 4 /* LED_PANIC */
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
- * Name: s32k146_bringup
- *
- * Description:
- * Perform architecture-specific initialization
- *
- * CONFIG_BOARD_LATE_INITIALIZE=y :
- * Called from board_late_initialize().
- *
- * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y :
- * Called from the NSH library
- *
+ * Name: board_autoled_initialize
****************************************************************************/
-int s32k146_bringup(void);
+void board_autoled_initialize(void)
+{
+ /* Configure LED GPIOs for output */
+
+ s32k1xx_pinconfig(GPIO_LED_R);
+ s32k1xx_pinconfig(GPIO_LED_G);
+ s32k1xx_pinconfig(GPIO_LED_B);
+}
/****************************************************************************
- * Name: s32k146_spidev_initialize
- *
- * Description:
- * Called to configure SPI chip select GPIO pins for the s32k146evb
- * board.
- *
+ * Name: board_autoled_on
****************************************************************************/
-#ifdef CONFIG_S32K1XX_SPI
-void s32k146_spidev_initialize(void);
-#endif
+void board_autoled_on(int led)
+{
+ if (led != LED_NOCHANGE)
+ {
+ bool redon = false;
+ bool greenon = false;
+ bool blueon = false;
+
+ switch (led)
+ {
+ default:
+ case LED_OFF_OFF_OFF:
+ break;
+
+ case LED_OFF_OFF_ON:
+ blueon = true;
+ break;
+
+ case LED_OFF_ON_OFF:
+ greenon = true;
+ break;
+
+ case LED_ON_OFF_OFF:
+ redon = true;
+ break;
+ }
+
+ s32k1xx_gpiowrite(GPIO_LED_R, redon);
+ s32k1xx_gpiowrite(GPIO_LED_G, greenon);
+ s32k1xx_gpiowrite(GPIO_LED_B, blueon);
+ }
+}
+
+/****************************************************************************
+ * Name: board_autoled_off
+ ****************************************************************************/
-#endif /* __ASSEMBLY__ */
-#endif /* __BOARDS_ARM_S32K1XX_S32K146EVB_SRC_S32K146EVB_H */
+void board_autoled_off(int led)
+{
+ if (led == LED_ON_OFF_OFF)
+ {
+ s32k1xx_gpiowrite(GPIO_LED_R, true);
+ s32k1xx_gpiowrite(GPIO_LED_G, false);
+ s32k1xx_gpiowrite(GPIO_LED_B, false);
+ }
+}
+
+#endif /* CONFIG_ARCH_LEDS */
diff --git a/arch/arm/src/s32k1xx/chip.h b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_boot.c
similarity index 62%
copy from arch/arm/src/s32k1xx/chip.h
copy to boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_boot.c
index f3f9b9c..59a6fdc 100644
--- a/arch/arm/src/s32k1xx/chip.h
+++ b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_boot.c
@@ -1,5 +1,5 @@
-/************************************************************************************
- * arch/arm/src/s32k1xx/chip.h
+/****************************************************************************
+ * boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_boot.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -31,47 +31,63 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ************************************************************************************/
+ ****************************************************************************/
-#ifndef __ARCH_ARM_SRC_S32K1XX_CHIP_H
-#define __ARCH_ARM_SRC_S32K1XX_CHIP_H
-
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
-/* Include the memory map and the chip definitions file. Other chip hardware files
- * should then include this file for the proper setup.
- */
+#include <debug.h>
+
+#include <nuttx/board.h>
-#include <arch/irq.h>
-#include "hardware/s32k1xx_memorymap.h"
+#include "rddrone-uavcan146.h"
-/* The common ARMv6/7-M vector handling logic expects the following definitions in
- * this file. ARMV6/7M_PERIPHERAL_INTERRUPTS provides the number of supported
- * external interrupts which, for this architecture, is provided in the
- * arch/s32k1xx/irq.h header file.
- */
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
-#define ARMV6M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT
-#define ARMV7M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT
+/****************************************************************************
+ * Name: s32k1xx_board_initialize
+ *
+ * Description:
+ * All S32K1XX architectures must provide the following entry point. This
+ * entry point is called early in the initialization -- after all memory
+ * has been configured and mapped but before any devices have been
+ * initialized.
+ *
+ ****************************************************************************/
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
+void s32k1xx_board_initialize(void)
+{
+#ifdef CONFIG_ARCH_LEDS
+ /* Configure on-board LEDs if LED support has been selected. */
-/************************************************************************************
- * Public Types
- ************************************************************************************/
+ board_autoled_initialize();
+#endif
+}
-/************************************************************************************
- * Public Data
- ************************************************************************************/
+/****************************************************************************
+ * Name: board_late_initialize
+ *
+ * Description:
+ * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
+ * initialization call will be performed in the boot-up sequence to a
+ * function called board_late_initialize(). board_late_initialize() will
+ * be called immediately after up_initialize() is called and just before
+ * the initial application is started. This additional initialization
+ * phase may be used, for example, to initialize board-specific device
+ * drivers.
+ *
+ ****************************************************************************/
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
+#ifdef CONFIG_BOARD_LATE_INITIALIZE
+void board_late_initialize(void)
+{
+ /* Perform board-specific initialization */
-#endif /* __ARCH_ARM_SRC_S32K1XX_CHIP_H */
+ s32k1xx_bringup();
+}
+#endif
diff --git a/boards/arm/s32k1xx/s32k148evb/src/s32k148evb.h b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_bringup.c
similarity index 51%
copy from boards/arm/s32k1xx/s32k148evb/src/s32k148evb.h
copy to boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_bringup.c
index ba85f50..300f08e 100644
--- a/boards/arm/s32k1xx/s32k148evb/src/s32k148evb.h
+++ b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_bringup.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/arm/s32k1xx/s32k148evb/src/s32k148evb.h
+ * boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_bringup.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -33,78 +33,38 @@
*
****************************************************************************/
-#ifndef __BOARDS_ARM_S32K1XX_S32K148EVB_SRC_S32K148EVB_H
-#define __BOARDS_ARM_S32K1XX_S32K148EVB_SRC_S32K148EVB_H
-
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
-#include <nuttx/compiler.h>
-
-#include <stdint.h>
-
-#include "hardware/s32k1xx_pinmux.h"
-#include "s32k1xx_periphclocks.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* Configuration ************************************************************/
-
-/* S32K148EVB GPIOs *********************************************************/
-
-/* LEDs. The S32K148EVB has one RGB LED:
- *
- * RedLED PTE21
- * GreenLED PTE22
- * BlueLED PTE23
- *
- * An output of '1' illuminates the LED.
- */
-#define GPIO_LED_R (PIN_PTE21 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
-#define GPIO_LED_G (PIN_PTE22 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
-#define GPIO_LED_B (PIN_PTE23 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
+#include <sys/types.h>
+#include <sys/mount.h>
+#include <syslog.h>
-/* Buttons. The S32K148EVB supports two buttons:
- *
- * SW3 PTC12
- * SW4 PTC13
- */
-
-#define GPIO_SW3 (PIN_PTC12 | PIN_INT_BOTH)
-#define GPIO_SW4 (PIN_PTC13 | PIN_INT_BOTH)
-
-/* SPI chip selects */
-
-
-/* Count of peripheral clock user configurations */
-
-#define NUM_OF_PERIPHERAL_CLOCKS_0 11
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-/****************************************************************************
- * Public data
- ****************************************************************************/
+#ifdef CONFIG_BUTTONS
+# include <nuttx/input/buttons.h>
+#endif
-#ifndef __ASSEMBLY__
+#ifdef CONFIG_USERLED
+# include <nuttx/leds/userled.h>
+#endif
-/* User peripheral configuration structure 0 */
+#ifdef CONFIG_I2C_DRIVER
+# include "s32k1xx_pin.h"
+# include <nuttx/i2c/i2c_master.h>
+# include "s32k1xx_lpi2c.h"
+#endif
-extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[];
+#include "rddrone-uavcan146.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
- * Name: s32k148_bringup
+ * Name: s32k1xx_bringup
*
* Description:
* Perform architecture-specific initialization
@@ -112,25 +72,73 @@ extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[];
* CONFIG_BOARD_LATE_INITIALIZE=y :
* Called from board_late_initialize().
*
- * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y :
+ * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y :
* Called from the NSH library
*
****************************************************************************/
-int s32k148_bringup(void);
+int s32k1xx_bringup(void)
+{
+ int ret = OK;
-/****************************************************************************
- * Name: s32k148_spidev_initialize
- *
- * Description:
- * Called to configure SPI chip select GPIO pins for the s32k148evb
- * board.
- *
- ****************************************************************************/
+#ifdef CONFIG_BUTTONS
+ /* Register the BUTTON driver */
+
+ ret = btn_lower_initialize("/dev/buttons");
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret);
+ }
+#endif
-#ifdef CONFIG_S32K1XX_SPI
-void s32k148_spidev_initialize(void);
+#ifdef CONFIG_USERLED
+ /* Register the LED driver */
+
+ ret = userled_lower_initialize("/dev/userleds");
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret);
+ }
+#endif
+
+#ifdef CONFIG_FS_PROCFS
+ /* Mount the procfs file system */
+
+ ret = mount(NULL, "/proc", "procfs", 0, NULL);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret);
+ }
+#endif
+
+#ifdef CONFIG_S32K1XX_LPSPI
+ /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak
+ * function s32k1xx_spidev_initialize() has been brought into the link.
+ */
+
+ s32k1xx_spidev_initialize();
+#endif
+
+#if defined(CONFIG_S32K1XX_LPI2C0)
+#if defined(CONFIG_I2C_DRIVER)
+ FAR struct i2c_master_s *i2c;
+ i2c = s32k1xx_i2cbus_initialize(0);
+
+ if (i2c == NULL)
+ {
+ serr("ERROR: Failed to get I2C%d interface\n", bus);
+ }
+ else
+ {
+ ret = i2c_register(i2c, 0);
+ if (ret < 0)
+ {
+ serr("ERROR: Failed to register I2C%d driver: %d\n", bus, ret);
+ s32k1xx_i2cbus_uninitialize(i2c);
+ }
+ }
+#endif
#endif
-#endif /* __ASSEMBLY__ */
-#endif /* __BOARDS_ARM_S32K1XX_S32K148EVB_SRC_S32K148EVB_H */
+ return ret;
+}
diff --git a/boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_buttons.c
similarity index 51%
copy from boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h
copy to boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_buttons.c
index 13cfc0c..81fc968 100644
--- a/boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h
+++ b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_buttons.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h
+ * boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_buttons.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -33,104 +33,133 @@
*
****************************************************************************/
-#ifndef __BOARDS_ARM_S32K1XX_S32K146EVB_SRC_S32K146EVB_H
-#define __BOARDS_ARM_S32K1XX_S32K146EVB_SRC_S32K146EVB_H
+/* The RDDRONE-UAVCAN146 supports two buttons:
+ *
+ * SW2 PTC12
+ * SW3 PTC13
+ */
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
-#include <nuttx/compiler.h>
#include <stdint.h>
+#include <errno.h>
-#include "hardware/s32k1xx_pinmux.h"
-#include "s32k1xx_periphclocks.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
-/* Configuration ************************************************************/
+#include "s32k1xx_pin.h"
+#include "rddrone-uavcan146.h"
-/* S32K146EVB GPIOs *********************************************************/
+#include <arch/board/board.h>
-/* LEDs. The S32K146EVB has one RGB LED:
- *
- * RedLED PTD15 (FTM0 CH0)
- * GreenLED PTD16 (FTM0 CH1)
- * BlueLED PTD0 (FTM0 CH2)
- *
- * An output of '1' illuminates the LED.
- */
+#ifdef CONFIG_ARCH_BUTTONS
-#define GPIO_LED_R (PIN_PTD15 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
-#define GPIO_LED_G (PIN_PTD16 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
-#define GPIO_LED_B (PIN_PTE8 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
-/* Buttons. The S32K146EVB supports two buttons:
+/****************************************************************************
+ * Name: board_button_initialize
*
- * SW2 PTC12
- * SW3 PTC13
- */
-
-#define GPIO_SW2 (PIN_PTC12 | PIN_INT_BOTH)
-#define GPIO_SW3 (PIN_PTC13 | PIN_INT_BOTH)
-
-/* SPI chip selects */
-
+ * Description:
+ * board_button_initialize() must be called to initialize button resources.
+ * After that, board_buttons() may be called to collect the current state
+ * of all buttons or board_button_irq() may be called to register button
+ * interrupt handlers.
+ *
+ ****************************************************************************/
-/* Count of peripheral clock user configurations */
+void board_button_initialize(void)
+{
+ /* Configure the GPIO pins as interrupting inputs. */
-#define NUM_OF_PERIPHERAL_CLOCKS_0 11
+ s32k1xx_pinconfig(GPIO_SW2);
+ s32k1xx_pinconfig(GPIO_SW3);
+}
/****************************************************************************
- * Public Types
+ * Name: board_buttons
****************************************************************************/
-/****************************************************************************
- * Public data
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
+uint32_t board_buttons(void)
+{
+ uint32_t ret = 0;
-/* User peripheral configuration structure 0 */
+ if (s32k1xx_gpioread(GPIO_SW2))
+ {
+ ret |= BUTTON_SW2_BIT;
+ }
-extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[];
+ if (s32k1xx_gpioread(GPIO_SW3))
+ {
+ ret |= BUTTON_SW3_BIT;
+ }
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
+ return ret;
+}
/****************************************************************************
- * Name: s32k146_bringup
+ * Button support.
*
* Description:
- * Perform architecture-specific initialization
+ * board_button_initialize() must be called to initialize button resources.
+ * After that, board_buttons() may be called to collect the current state
+ * of all buttons or board_button_irq() may be called to register button
+ * interrupt handlers.
*
- * CONFIG_BOARD_LATE_INITIALIZE=y :
- * Called from board_late_initialize().
+ * After board_button_initialize() has been called, board_buttons() may be
+ * called to collect the state of all buttons. board_buttons() returns a
+ * 32-bit bit set with each bit associated with a button. See the
+ * BUTTON_*_BIT definitions in board.h for the meaning of each bit.
*
- * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y :
- * Called from the NSH library
+ * board_button_irq() may be called to register an interrupt handler that
+ * will be called when a button is depressed or released. The ID value is
+ * a button enumeration value that uniquely identifies a button resource.
+ * See the BUTTON_* definitions in board.h for the meaning of enumeration
+ * value.
*
****************************************************************************/
-int s32k146_bringup(void);
-
-/****************************************************************************
- * Name: s32k146_spidev_initialize
- *
- * Description:
- * Called to configure SPI chip select GPIO pins for the s32k146evb
- * board.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_S32K1XX_SPI
-void s32k146_spidev_initialize(void);
+#ifdef CONFIG_ARCH_IRQBUTTONS
+int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg)
+{
+ uint32_t pinset;
+ int ret;
+
+ /* Map the button id to the GPIO bit set. */
+
+ if (id == BUTTON_SW2)
+ {
+ pinset = GPIO_SW2;
+ }
+ else if (id == BUTTON_SW3)
+ {
+ pinset = GPIO_SW3;
+ }
+ else
+ {
+ return -EINVAL;
+ }
+
+ /* The button has already been configured as an interrupting input (by
+ * board_button_initialize() above).
+ *
+ * Attach the new button handler.
+ */
+
+ ret = s32k1xx_pinirqattach(pinset, irqhandler, NULL);
+ if (ret >= 0)
+ {
+ /* Then make sure that interrupts are enabled on the pin */
+
+ s32k1xx_pinirqenable(pinset);
+ }
+
+ return ret;
+}
#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __BOARDS_ARM_S32K1XX_S32K146EVB_SRC_S32K146EVB_H */
+#endif /* CONFIG_ARCH_BUTTONS */
diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_clockconfig.c b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_clockconfig.c
new file mode 100644
index 0000000..5f31c4c
--- /dev/null
+++ b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_clockconfig.c
@@ -0,0 +1,227 @@
+/****************************************************************************
+ * boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_clockconfig.c
+ *
+ * Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Most of the settings within this file derives from NXP sample code for
+ * the S32K1XX MCUs. That sample code has this licensing information:
+ *
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "s32k1xx_clockconfig.h"
+#include "s32k1xx_start.h"
+#include "rddrone-uavcan146.h"
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* Each S32K1XX board must provide the following initialized structure.
+ * This is needed to establish the initial board clocking.
+ */
+
+const struct clock_configuration_s g_initial_clkconfig =
+{
+ .scg =
+ {
+ .sirc =
+ {
+ .range = SCG_SIRC_RANGE_HIGH, /* RANGE - High range (8 MHz) */
+ .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV1 */
+ .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV2 */
+ .initialize = true, /* Initialize */
+ .stopmode = true, /* SIRCSTEN */
+ .lowpower = true, /* SIRCLPEN */
+ .locked = false, /* LK */
+ },
+ .firc =
+ {
+ .range = SCG_FIRC_RANGE_48M, /* RANGE */
+ .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV1 */
+ .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV2 */
+ .initialize = true, /* Initialize */
+ .stopmode = false, /* */
+ .lowpower = false, /* */
+ .regulator = true, /* FIRCREGOFF */
+ .locked = false, /* LK */
+ },
+ .sosc =
+ {
+ .mode = SCG_SOSC_MONITOR_DISABLE, /* SOSCCM */
+ .gain = SCG_SOSC_GAIN_LOW, /* HGO */
+ .range = SCG_SOSC_RANGE_MID, /* RANGE */
+ .extref = SCG_SOSC_REF_OSC, /* EREFS */
+ .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV1 */
+ .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV2 */
+ .initialize = true, /* Initialize */
+ .stopmode = false, /* */
+ .lowpower = false, /* */
+ .locked = false, /* LK */
+ },
+ .spll =
+ {
+ .mode = SCG_SPLL_MONITOR_DISABLE, /* SPLLCM */
+ .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV1 */
+ .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV2 */
+ .prediv = 1, /* PREDIV */
+ .mult = 40, /* MULT */
+ .src = 0, /* SOURCE */
+ .initialize = true, /* Initialize */
+ .stopmode = false, /* */
+ .locked = false, /* LK */
+ },
+ .rtc =
+ {
+ .initialize = true, /* Initialize */
+ .clkin = 0 /* RTC_CLKIN */
+ },
+ .clockout =
+ {
+ .source = SCG_CLOCKOUT_SRC_FIRC, /* SCG CLKOUTSEL */
+ .initialize = true, /* Initialize */
+ },
+ .clockmode =
+ {
+ .rccr = /* RCCR - Run Clock Control Register */
+ {
+ .src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL, /* SCS */
+ .divslow = 3, /* DIVSLOW, range 1..16 */
+ .divbus = 2, /* DIVBUS, range 1..16 */
+ .divcore = 2 /* DIVCORE, range 1..16 */
+ },
+ .vccr = /* VCCR - VLPR Clock Control Register */
+ {
+ .src = SCG_SYSTEM_CLOCK_SRC_SIRC, /* SCS */
+ .divslow = 4, /* DIVSLOW, range 1..16 */
+ .divbus = 1, /* DIVBUS, range 1..16 */
+ .divcore = 2 /* DIVCORE, range 1..16 */
+ },
+ .hccr =
+ {
+ .src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL, /* SCS */
+ .divslow = 3, /* DIVSLOW, range 1..16 */
+ .divbus = 2, /* DIVBUS, range 1..16 */
+ .divcore = 2 /* DIVCORE, range 1..16 */
+ },
+
+ /* .altclk */
+
+ .initialize = true, /* Initialize */
+ },
+ },
+ .sim =
+ {
+ .clockout = /* Clock Out configuration. */
+ {
+ .source = SIM_CLKOUT_SEL_SYSTEM_SCG_CLKOUT, /* CLKOUTSEL */
+ .divider = 1, /* CLKOUTDIV, range 1..8 */
+ .initialize = true, /* Initialize */
+ .enable = false, /* CLKOUTEN */
+ },
+ .lpoclk = /* Low Power Clock configuration. */
+ {
+ .rtc_source = SIM_RTCCLK_SEL_SOSCDIV1_CLK, /* RTCCLKSEL */
+ .lpo_source = SIM_LPO_CLK_SEL_LPO_128K, /* LPOCLKSEL */
+ .initialize = true, /* Initialize */
+ .lpo32k = true, /* LPO32KCLKEN */
+ .lpo1k = true, /* LPO1KCLKEN */
+ },
+ .tclk = /* TCLK CLOCK configuration. */
+ {
+ .tclkfreq[0] = 0, /* TCLK0 */
+ .tclkfreq[1] = 0, /* TCLK1 */
+ .tclkfreq[2] = 0, /* TCLK2 */
+ .initialize = true, /* Initialize */
+ },
+ .platgate = /* Platform Gate Clock configuration. */
+ {
+ .initialize = true, /* Initialize */
+ .mscm = true, /* CGCMSCM */
+ .mpu = true, /* CGCMPU */
+ .dma = true, /* CGCDMA */
+ .erm = true, /* CGCERM */
+ .eim = true, /* CGCEIM */
+ },
+ .traceclk = /* Debug trace Clock Configuration. */
+ {
+ .source = CLOCK_TRACE_SRC_CORE_CLK, /* TRACECLK_SEL */
+ .divider = 1, /* TRACEDIV, range 1..8 */
+ .initialize = true, /* Initialize */
+ .enable = true, /* TRACEDIVEN */
+ .fraction = false, /* TRACEFRAC */
+ },
+#ifdef CONFIG_S32K1XX_HAVE_QSPI
+ .qspirefclk = /* Quad Spi Internal Reference Clock Gating. */
+ {
+ .refclk = false, /* Qspi reference clock gating */
+ },
+#endif
+ },
+ .pcc =
+ {
+ .count = NUM_OF_PERIPHERAL_CLOCKS_0, /* Number peripheral clock configurations */
+ .pclks = g_peripheral_clockconfig0 /* Peripheral clock configurations */
+ },
+ .pmc =
+ {
+ .lpoclk = /* Low Power Clock configuration. */
+ {
+ .trim = 0, /* Trimming value for LPO */
+ .initialize = true, /* Initialize */
+ .enable = true, /* Enable/disable LPO */
+ },
+ }
+};
diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_periphclocks.c b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_periphclocks.c
new file mode 100644
index 0000000..d2dc57f
--- /dev/null
+++ b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_periphclocks.c
@@ -0,0 +1,187 @@
+/****************************************************************************
+ * boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_periphclks.c
+ *
+ * Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Most of the settings within this file derives from NXP sample code for
+ * the S32K1XX MCUs. That sample code has this licensing information:
+ *
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "s32k1xx_periphclocks.h"
+#include "rddrone-uavcan146.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* Each S32K1XX board must provide the following initialized structure.
+ * This is needed to establish the initial peripheral clocking.
+ */
+
+const struct peripheral_clock_config_s g_peripheral_clockconfig0[] =
+{
+ {
+ .clkname = ADC0_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_FIRC,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = ADC1_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_FIRC,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = LPI2C0_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_SIRC,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = LPSPI0_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_SIRC,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = LPSPI1_CLK,
+ .clkgate = false,
+ .clksrc = CLK_SRC_FIRC,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = LPSPI2_CLK,
+ .clkgate = false,
+ .clksrc = CLK_SRC_FIRC,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = LPTMR0_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_SIRC,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = LPUART0_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_SIRC,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = LPUART1_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_SIRC,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = LPUART2_CLK,
+ .clkgate = false,
+ .clksrc = CLK_SRC_SIRC,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = PORTA_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_OFF,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = PORTB_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_OFF,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = PORTC_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_OFF,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = PORTD_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_OFF,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = PORTE_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_OFF,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ }
+};
diff --git a/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_spi.c b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_spi.c
new file mode 100644
index 0000000..d9ca69a
--- /dev/null
+++ b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_spi.c
@@ -0,0 +1,199 @@
+/****************************************************************************
+ * boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_spi.c
+ *
+ * Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ * Author: Ivan Ucherdzhiev <iv...@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/spi/spi.h>
+#include <nuttx/spi/spi_transfer.h>
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+
+#include "s32k1xx_config.h"
+#include "s32k1xx_lpspi.h"
+#include "s32k1xx_pin.h"
+#include "rddrone-uavcan146.h"
+
+#if defined(CONFIG_S32K1XX_LPSPI0) || defined(CONFIG_S32K1XX_LPSPI1) || \
+ defined(CONFIG_S32K1XX_LPSPI2)
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: s32k1xx_spidev_initialize
+ *
+ * Description:
+ * Called to configure SPI chip select GPIO pins for the RDDRONE-UAVCAN146
+ * board.
+ *
+ ****************************************************************************/
+
+void weak_function s32k1xx_spidev_initialize(void)
+{
+#ifdef CONFIG_S32K1XX_LPSPI0
+ s32k1xx_pinconfig(PIN_LPSPI0_PCS);
+
+#ifdef CONFIG_SPI_DRIVER
+ struct spi_dev_s *g_lpspi0;
+ g_lpspi0 = s32k1xx_lpspibus_initialize(0);
+
+ if (!g_lpspi0)
+ {
+ spierr("ERROR: [boot] FAILED to initialize LPSPI0\n");
+ }
+
+ spi_register(g_lpspi0, 0);
+#endif
+#endif
+
+#ifdef CONFIG_S32K1XX_LPSPI1
+ s32k1xx_pinconfig(PIN_LPSPI1_PCS);
+
+#ifdef CONFIG_SPI_DRIVER
+ struct spi_dev_s *g_lpspi1;
+ g_lpspi1 = s32k1xx_lpspibus_initialize(1);
+
+ if (!g_lpspi1)
+ {
+ spierr("ERROR: [boot] FAILED to initialize LPSPI1\n");
+ }
+
+ spi_register(g_lpspi1, 1);
+#endif
+#endif
+
+#ifdef CONFIG_S32K1XX_LPSPI2
+ s32k1xx_pinconfig(PIN_LPSPI2_PCS);
+
+#ifdef CONFIG_SPI_DRIVER
+ struct spi_dev_s *g_lpspi2;
+ g_lpspi2 = s32k1xx_lpspibus_initialize(2);
+
+ if (!g_lpspi2)
+ {
+ spierr("ERROR: [boot] FAILED to initialize LPSPI2\n");
+ }
+
+ spi_register(g_lpspi2, 2);
+#endif
+#endif
+}
+
+/****************************************************************************
+ * Name: s32k1xx_lpspi0/1/2select and s32k1xx_lpspi0/1/2status
+ *
+ * Description:
+ * The external functions, s32k1xx_lpspi0/1/2select and
+ * s32k1xx_lpspi0/1/2status must be provided by board-specific logic.
+ * They are implementations of the select and status methods of the SPI
+ * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h).
+ * All other methods (including s32k1xx_lpspibus_initialize()) are provided
+ * by common logic. To use this common SPI logic on your board:
+ *
+ * 1. Provide logic in s32k1xx_boardinitialize() to configure SPI chip
+ * select pins.
+ * 2. Provide s32k1xx_lpspi0/1/2select() and s32k1xx_lpspi0/1/2status()
+ * functions in your board-specific logic. These functions will perform
+ * chip selection and status operations using GPIOs in the way your
+ * board is configured.
+ * 3. Add a calls to s32k1xx_lpspibus_initialize() in your low level
+ * application initialization logic
+ * 4. The handle returned by s32k1xx_lpspibus_initialize() may then be used
+ * to bind the SPI driver to higher level logic (e.g., calling
+ * mmcsd_spislotinitialize(), for example, will bind the SPI driver to
+ * the SPI MMC/SD driver).
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_S32K1XX_LPSPI0
+void s32k1xx_lpspi0select(FAR struct spi_dev_s *dev, uint32_t devid,
+ bool selected)
+{
+ spiinfo("devid: %d CS: %s\n", (int)devid,
+ selected ? "assert" : "de-assert");
+
+ s32k1xx_gpiowrite(PIN_LPSPI0_PCS, !selected);
+}
+
+uint8_t s32k1xx_lpspi0status(FAR struct spi_dev_s *dev, uint32_t devid)
+{
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_S32K1XX_LPSPI1
+void s32k1xx_lpspi1select(FAR struct spi_dev_s *dev,
+ uint32_t devid, bool selected)
+{
+ spiinfo("devid: %d CS: %s\n", (int)devid,
+ selected ? "assert" : "de-assert");
+
+ s32k1xx_gpiowrite(PIN_LPSPI1_PCS, !selected);
+}
+
+uint8_t s32k1xx_lpspi1status(FAR struct spi_dev_s *dev, uint32_t devid)
+{
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_S32K1XX_LPSPI2
+void s32k1xx_lpspi2select(FAR struct spi_dev_s *dev,
+ uint32_t devid, bool selected)
+{
+ spiinfo("devid: %d CS: %s\n", (int)devid,
+ selected ? "assert" : "de-assert");
+
+ s32k1xx_gpiowrite(PIN_LPSPI2_PCS, !selected);
+}
+
+uint8_t s32k1xx_lpspi2status(FAR struct spi_dev_s *dev, uint32_t devid)
+{
+ return 0;
+}
+#endif
+
+#endif /* CONFIG_S32K1XX_LPSPI0 || CONFIG_S32K1XX_LPSPI01 || CONFIG_S32K1XX_LPSPI2 */
diff --git a/arch/arm/src/s32k1xx/chip.h b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_userleds.c
similarity index 63%
copy from arch/arm/src/s32k1xx/chip.h
copy to boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_userleds.c
index f3f9b9c..3b66e0d 100644
--- a/arch/arm/src/s32k1xx/chip.h
+++ b/boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_userleds.c
@@ -1,5 +1,5 @@
-/************************************************************************************
- * arch/arm/src/s32k1xx/chip.h
+/****************************************************************************
+ * boards/arm/s32k1xx/rddrone-uavcan146/src/s32k1xx_userleds.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -31,47 +31,86 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ************************************************************************************/
+ ****************************************************************************/
-#ifndef __ARCH_ARM_SRC_S32K1XX_CHIP_H
-#define __ARCH_ARM_SRC_S32K1XX_CHIP_H
-
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
-/* Include the memory map and the chip definitions file. Other chip hardware files
- * should then include this file for the proper setup.
- */
-
-#include <arch/irq.h>
-#include "hardware/s32k1xx_memorymap.h"
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
-/* The common ARMv6/7-M vector handling logic expects the following definitions in
- * this file. ARMV6/7M_PERIPHERAL_INTERRUPTS provides the number of supported
- * external interrupts which, for this architecture, is provided in the
- * arch/s32k1xx/irq.h header file.
- */
+#include <nuttx/board.h>
-#define ARMV6M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT
-#define ARMV7M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT
+#include "up_arch.h"
+#include "up_internal.h"
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
+#include "s32k1xx_pin.h"
+#include "rddrone-uavcan146.h"
-/************************************************************************************
- * Public Types
- ************************************************************************************/
+#include <arch/board/board.h>
-/************************************************************************************
- * Public Data
- ************************************************************************************/
+#ifndef CONFIG_ARCH_LEDS
-/************************************************************************************
+/****************************************************************************
* Public Functions
- ************************************************************************************/
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_userled_initialize
+ ****************************************************************************/
+
+void board_userled_initialize(void)
+{
+ /* Configure LED GPIOs for output */
+
+ s32k1xx_pinconfig(GPIO_LED_R);
+ s32k1xx_pinconfig(GPIO_LED_G);
+ s32k1xx_pinconfig(GPIO_LED_B);
+}
+
+/****************************************************************************
+ * Name: board_userled
+ ****************************************************************************/
+
+void board_userled(int led, bool ledon)
+{
+ uint32_t ledcfg;
+
+ if (led == BOARD_LED_R)
+ {
+ ledcfg = GPIO_LED_R;
+ }
+ else if (led == BOARD_LED_G)
+ {
+ ledcfg = GPIO_LED_G;
+ }
+ else if (led == BOARD_LED_B)
+ {
+ ledcfg = GPIO_LED_B;
+ }
+ else
+ {
+ return;
+ }
+
+ s32k1xx_gpiowrite(ledcfg, ledon); /* High illuminates */
+}
+
+/****************************************************************************
+ * Name: board_userled_all
+ ****************************************************************************/
+
+void board_userled_all(uint8_t ledset)
+{
+ /* Low illuminates */
+
+ s32k1xx_gpiowrite(GPIO_LED_R, (ledset & BOARD_LED_R_BIT) != 0);
+ s32k1xx_gpiowrite(GPIO_LED_G, (ledset & BOARD_LED_G_BIT) != 0);
+ s32k1xx_gpiowrite(GPIO_LED_B, (ledset & BOARD_LED_B_BIT) != 0);
+}
-#endif /* __ARCH_ARM_SRC_S32K1XX_CHIP_H */
+#endif /* !CONFIG_ARCH_LEDS */
diff --git a/boards/arm/s32k1xx/s32k118evb/README.txt b/boards/arm/s32k1xx/s32k118evb/README.txt
index 1e9c468..37aa327 100644
--- a/boards/arm/s32k1xx/s32k118evb/README.txt
+++ b/boards/arm/s32k1xx/s32k118evb/README.txt
@@ -65,7 +65,7 @@ LEDs and Buttons
the common RGB LED driver.
If CONFIG_ARCH_LEDs is defined, then NuttX will control the LEDs on board
- the s32k118evb. The following definitions describe how NuttX controls the
+ the S32K118EVB. The following definitions describe how NuttX controls the
LEDs:
==========================================+========+========+=========
@@ -80,7 +80,7 @@ LEDs and Buttons
LED_SIGNAL In a signal handler (no change)
LED_ASSERTION An assertion failed (no change)
LED_PANIC The system has crashed FLASH OFF OFF
- LED_IDLE S32K118EVN in sleep mode (no change)
+ LED_IDLE S32K118EVB in sleep mode (no change)
==========================================+========+========+=========
Buttons
diff --git a/boards/arm/s32k1xx/s32k118evb/include/board.h b/boards/arm/s32k1xx/s32k118evb/include/board.h
index 065edba..23f0cd0 100644
--- a/boards/arm/s32k1xx/s32k118evb/include/board.h
+++ b/boards/arm/s32k1xx/s32k118evb/include/board.h
@@ -33,8 +33,8 @@
*
****************************************************************************/
-#ifndef __BOARDS_ARM_STM32F4DISCOVERY_INCLUDE_BOARD_H
-#define __BOARDS_ARM_STM32F4DISCOVERY_INCLUDE_BOARD_H
+#ifndef __BOARDS_ARM_S32K118EVB_INCLUDE_BOARD_H
+#define __BOARDS_ARM_S32K118EVB_INCLUDE_BOARD_H
/****************************************************************************
* Included Files
@@ -89,10 +89,9 @@
#define BOARD_LED_B_BIT (1 << BOARD_LED_B)
/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LEDs on board
- * the s32k118evb. The following definitions describe how NuttX controls the
+ * the S32K118EVB. The following definitions describe how NuttX controls the
* LEDs:
*
- *
* SYMBOL Meaning LED state
* RED GREEN BLUE
* ------------------- ---------------------------- -----------------
@@ -106,7 +105,7 @@
#define LED_SIGNAL 0 /* In a signal handler (no change) */
#define LED_ASSERTION 0 /* An assertion failed (no change) */
#define LED_PANIC 4 /* The system has crashed FLASH OFF OFF */
-#undef LED_IDLE /* S32K118EVN in sleep mode (Not used) */
+#undef LED_IDLE /* S32K118EVB in sleep mode (Not used) */
/* Button definitions *******************************************************/
@@ -134,7 +133,4 @@
#define PIN_LPUART0_RX PIN_LPUART0_RX_1 /* PTB0 */
#define PIN_LPUART0_TX PIN_LPUART0_TX_1 /* PTB1 */
-/* DMA Channel/Stream Selections ********************************************/
-
-
-#endif /* __BOARDS_ARM_STM32F4DISCOVERY_INCLUDE_BOARD_H */
+#endif /* __BOARDS_ARM_S32K118EVB_INCLUDE_BOARD_H */
diff --git a/boards/arm/s32k1xx/s32k118evb/src/Makefile b/boards/arm/s32k1xx/s32k118evb/src/Makefile
index ef53d27..87cf777 100644
--- a/boards/arm/s32k1xx/s32k118evb/src/Makefile
+++ b/boards/arm/s32k1xx/s32k118evb/src/Makefile
@@ -36,21 +36,21 @@
-include $(TOPDIR)/Make.defs
ASRCS =
-CSRCS = s32k118_boot.c s32k118_bringup.c s32k118_clockconfig.c
-CSRCS += s32k118_periphclocks.c
+CSRCS = s32k1xx_boot.c s32k1xx_bringup.c s32k1xx_clockconfig.c
+CSRCS += s32k1xx_periphclocks.c
ifeq ($(CONFIG_ARCH_LEDS),y)
-CSRCS += s32k118_autoleds.c
+CSRCS += s32k1xx_autoleds.c
else
-CSRCS += s32k118_userleds.c
+CSRCS += s32k1xx_userleds.c
endif
ifeq ($(CONFIG_ARCH_BUTTONS),y)
-CSRCS += s32k118_buttons.c
+CSRCS += s32k1xx_buttons.c
endif
ifeq ($(CONFIG_LIB_BOARDCTL),y)
-CSRCS += s32k118_appinit.c
+CSRCS += s32k1xx_appinit.c
endif
include $(TOPDIR)/boards/Board.mk
diff --git a/boards/arm/s32k1xx/s32k118evb/src/s32k118evb.h b/boards/arm/s32k1xx/s32k118evb/src/s32k118evb.h
index 4a0c3fb..76108fd 100644
--- a/boards/arm/s32k1xx/s32k118evb/src/s32k118evb.h
+++ b/boards/arm/s32k1xx/s32k118evb/src/s32k118evb.h
@@ -80,7 +80,6 @@
/* SPI chip selects */
-
/* Count of peripheral clock user configurations */
#define NUM_OF_PERIPHERAL_CLOCKS_0 10
@@ -90,7 +89,7 @@
****************************************************************************/
/****************************************************************************
- * Public data
+ * Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
@@ -100,11 +99,11 @@
extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[];
/****************************************************************************
- * Public Functions
+ * Public Function Prototypes
****************************************************************************/
/****************************************************************************
- * Name: s32k118_bringup
+ * Name: s32k1xx_bringup
*
* Description:
* Perform architecture-specific initialization
@@ -117,19 +116,19 @@ extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[];
*
****************************************************************************/
-int s32k118_bringup(void);
+int s32k1xx_bringup(void);
/****************************************************************************
- * Name: s32k118_spidev_initialize
+ * Name: s32k1xx_spidev_initialize
*
* Description:
- * Called to configure SPI chip select GPIO pins for the s32k118evb
+ * Called to configure SPI chip select GPIO pins for the S32K118EVB
* board.
*
****************************************************************************/
#ifdef CONFIG_S32K1XX_SPI
-void s32k118_spidev_initialize(void);
+void s32k1xx_spidev_initialize(void);
#endif
#endif /* __ASSEMBLY__ */
diff --git a/arch/arm/src/s32k1xx/chip.h b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_appinit.c
similarity index 59%
copy from arch/arm/src/s32k1xx/chip.h
copy to boards/arm/s32k1xx/s32k118evb/src/s32k1xx_appinit.c
index f3f9b9c..333806c 100644
--- a/arch/arm/src/s32k1xx/chip.h
+++ b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_appinit.c
@@ -1,5 +1,5 @@
-/************************************************************************************
- * arch/arm/src/s32k1xx/chip.h
+/****************************************************************************
+ * boards/arm/s32k1xx/s32k118evb/src/s32k1xx_appinit.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -31,47 +31,64 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ************************************************************************************/
+ ****************************************************************************/
-#ifndef __ARCH_ARM_SRC_S32K1XX_CHIP_H
-#define __ARCH_ARM_SRC_S32K1XX_CHIP_H
-
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
-/* Include the memory map and the chip definitions file. Other chip hardware files
- * should then include this file for the proper setup.
- */
+#include <nuttx/board.h>
-#include <arch/irq.h>
-#include "hardware/s32k1xx_memorymap.h"
+#include "s32k118evb.h"
-/* The common ARMv6/7-M vector handling logic expects the following definitions in
- * this file. ARMV6/7M_PERIPHERAL_INTERRUPTS provides the number of supported
- * external interrupts which, for this architecture, is provided in the
- * arch/s32k1xx/irq.h header file.
- */
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
-#define ARMV6M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT
-#define ARMV7M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT
+#ifndef OK
+# define OK 0
+#endif
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
-/************************************************************************************
- * Public Types
- ************************************************************************************/
+/****************************************************************************
+ * Name: board_app_initialize
+ *
+ * Description:
+ * Perform application specific initialization. This function is never
+ * called directly from application code, but only indirectly via the
+ * (non-standard) boardctl() interface using the command BOARDIOC_INIT.
+ *
+ * Input Parameters:
+ * arg - The boardctl() argument is passed to the board_app_initialize()
+ * implementation without modification. The argument has no
+ * meaning to NuttX; the meaning of the argument is a contract
+ * between the board-specific initialization logic and the
+ * matching application logic. The value cold be such things as a
+ * mode enumeration value, a set of DIP switch switch settings, a
+ * pointer to configuration data read from a file or serial FLASH,
+ * or whatever you would like to do with it. Every implementation
+ * should accept zero/NULL as a default configuration.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned on
+ * any failure to indicate the nature of the failure.
+ *
+ ****************************************************************************/
-/************************************************************************************
- * Public Data
- ************************************************************************************/
+int board_app_initialize(uintptr_t arg)
+{
+#ifdef CONFIG_BOARD_LATE_INITIALIZE
+ /* Board initialization already performed by board_late_initialize() */
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
+ return OK;
+#else
+ /* Perform board-specific initialization */
-#endif /* __ARCH_ARM_SRC_S32K1XX_CHIP_H */
+ return s32k1xx_bringup();
+#endif
+}
diff --git a/boards/arm/s32k1xx/s32k118evb/src/s32k118evb.h b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_autoleds.c
similarity index 52%
copy from boards/arm/s32k1xx/s32k118evb/src/s32k118evb.h
copy to boards/arm/s32k1xx/s32k118evb/src/s32k1xx_autoleds.c
index 4a0c3fb..5c9cee4 100644
--- a/boards/arm/s32k1xx/s32k118evb/src/s32k118evb.h
+++ b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_autoleds.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/arm/s32k1xx/s32k118evb/src/s32k118evb.h
+ * boards/arm/s32k1xx/s32k118evb/src/s32k1xx_autoleds.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -33,104 +33,133 @@
*
****************************************************************************/
-#ifndef __BOARDS_ARM_S32K1XX_S32K118EVB_SRC_S32K118EVB_H
-#define __BOARDS_ARM_S32K1XX_S32K118EVB_SRC_S32K118EVB_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-#include <nuttx/compiler.h>
-
-#include <stdint.h>
-
-#include "hardware/s32k1xx_pinmux.h"
-#include "s32k1xx_periphclocks.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* Configuration ************************************************************/
-
-/* S32K118EVB GPIOs *********************************************************/
-
-/* LEDs. The S32K118EVB has one RGB LED:
+/* The S32K118EVB has one RGB LED:
*
* RedLED PTD16 (FTM0CH1)
* GreenLED PTD15 (FTM0CH0)
* BlueLED PTE8 (FTM0CH6)
*
* An output of '1' illuminates the LED.
+ *
+ * If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board
+ * the Freedom K66F. The following definitions describe how NuttX controls
+ * the LEDs:
+ *
+ * SYMBOL Meaning LED state
+ * RED GREEN BLUE
+ * ------------------- ----------------------- -----------------
+ * LED_STARTED NuttX has been started OFF OFF OFF
+ * LED_HEAPALLOCATE Heap has been allocated OFF OFF ON
+ * LED_IRQSENABLED Interrupts enabled OFF OFF ON
+ * LED_STACKCREATED Idle stack created OFF ON OFF
+ * LED_INIRQ In an interrupt (no change)
+ * LED_SIGNAL In a signal handler (no change)
+ * LED_ASSERTION An assertion failed (no change)
+ * LED_PANIC The system has crashed FLASH OFF OFF
+ * LED_IDLE K66 is in sleep mode (Optional, not used)
*/
-#define GPIO_LED_R (PIN_PTD16 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
-#define GPIO_LED_G (PIN_PTD15 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
-#define GPIO_LED_B (PIN_PTE8 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
-/* Buttons. The S32K118EVB supports two buttons:
- *
- * SW2 PTD3
- * SW3 PTD5
- */
+#include <nuttx/config.h>
-#define GPIO_SW2 (PIN_PTD3 | PIN_INT_BOTH)
-#define GPIO_SW3 (PIN_PTD5 | PIN_INT_BOTH)
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
-/* SPI chip selects */
+#include <nuttx/board.h>
+#include <arch/board/board.h>
+#include "up_arch.h"
+#include "up_internal.h"
-/* Count of peripheral clock user configurations */
+#include "s32k1xx_pin.h"
+#include "s32k118evb.h"
-#define NUM_OF_PERIPHERAL_CLOCKS_0 10
+#include <arch/board/board.h>
-/****************************************************************************
- * Public Types
- ****************************************************************************/
+#ifdef CONFIG_ARCH_LEDS
/****************************************************************************
- * Public data
+ * Pre-processor Definitions
****************************************************************************/
-#ifndef __ASSEMBLY__
+/* Summary of all possible settings */
-/* User peripheral configuration structure 0 */
-
-extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[];
+#define LED_NOCHANGE 0 /* LED_IRQSENABLED, LED_INIRQ, LED_SIGNAL, LED_ASSERTION */
+#define LED_OFF_OFF_OFF 1 /* LED_STARTED */
+#define LED_OFF_OFF_ON 2 /* LED_HEAPALLOCATE */
+#define LED_OFF_ON_OFF 3 /* LED_STACKCREATED */
+#define LED_ON_OFF_OFF 4 /* LED_PANIC */
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
- * Name: s32k118_bringup
- *
- * Description:
- * Perform architecture-specific initialization
- *
- * CONFIG_BOARD_LATE_INITIALIZE=y :
- * Called from board_late_initialize().
- *
- * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y :
- * Called from the NSH library
- *
+ * Name: board_autoled_initialize
****************************************************************************/
-int s32k118_bringup(void);
+void board_autoled_initialize(void)
+{
+ /* Configure LED GPIOs for output */
+
+ s32k1xx_pinconfig(GPIO_LED_R);
+ s32k1xx_pinconfig(GPIO_LED_G);
+ s32k1xx_pinconfig(GPIO_LED_B);
+}
/****************************************************************************
- * Name: s32k118_spidev_initialize
- *
- * Description:
- * Called to configure SPI chip select GPIO pins for the s32k118evb
- * board.
- *
+ * Name: board_autoled_on
****************************************************************************/
-#ifdef CONFIG_S32K1XX_SPI
-void s32k118_spidev_initialize(void);
-#endif
+void board_autoled_on(int led)
+{
+ if (led != LED_NOCHANGE)
+ {
+ bool redon = false;
+ bool greenon = false;
+ bool blueon = false;
+
+ switch (led)
+ {
+ default:
+ case LED_OFF_OFF_OFF:
+ break;
+
+ case LED_OFF_OFF_ON:
+ blueon = true;
+ break;
+
+ case LED_OFF_ON_OFF:
+ greenon = true;
+ break;
+
+ case LED_ON_OFF_OFF:
+ redon = true;
+ break;
+ }
+
+ s32k1xx_gpiowrite(GPIO_LED_R, redon);
+ s32k1xx_gpiowrite(GPIO_LED_G, greenon);
+ s32k1xx_gpiowrite(GPIO_LED_B, blueon);
+ }
+}
+
+/****************************************************************************
+ * Name: board_autoled_off
+ ****************************************************************************/
-#endif /* __ASSEMBLY__ */
-#endif /* __BOARDS_ARM_S32K1XX_S32K118EVB_SRC_S32K118EVB_H */
+void board_autoled_off(int led)
+{
+ if (led == LED_ON_OFF_OFF)
+ {
+ s32k1xx_gpiowrite(GPIO_LED_R, true);
+ s32k1xx_gpiowrite(GPIO_LED_G, false);
+ s32k1xx_gpiowrite(GPIO_LED_B, false);
+ }
+}
+
+#endif /* CONFIG_ARCH_LEDS */
diff --git a/arch/arm/src/s32k1xx/chip.h b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_boot.c
similarity index 59%
copy from arch/arm/src/s32k1xx/chip.h
copy to boards/arm/s32k1xx/s32k118evb/src/s32k1xx_boot.c
index f3f9b9c..d2faffc 100644
--- a/arch/arm/src/s32k1xx/chip.h
+++ b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_boot.c
@@ -1,5 +1,5 @@
-/************************************************************************************
- * arch/arm/src/s32k1xx/chip.h
+/****************************************************************************
+ * boards/arm/s32k1xx/s32k118evb/src/s32k1xx_boot.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -31,47 +31,71 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ************************************************************************************/
+ ****************************************************************************/
-#ifndef __ARCH_ARM_SRC_S32K1XX_CHIP_H
-#define __ARCH_ARM_SRC_S32K1XX_CHIP_H
-
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
-/* Include the memory map and the chip definitions file. Other chip hardware files
- * should then include this file for the proper setup.
- */
+#include <debug.h>
-#include <arch/irq.h>
-#include "hardware/s32k1xx_memorymap.h"
+#include <nuttx/board.h>
-/* The common ARMv6/7-M vector handling logic expects the following definitions in
- * this file. ARMV6/7M_PERIPHERAL_INTERRUPTS provides the number of supported
- * external interrupts which, for this architecture, is provided in the
- * arch/s32k1xx/irq.h header file.
- */
+#include "s32k118evb.h"
-#define ARMV6M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT
-#define ARMV7M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
+/****************************************************************************
+ * Name: s32k1xx_board_initialize
+ *
+ * Description:
+ * All S32K1XX architectures must provide the following entry point. This
+ * entry point is called early in the initialization -- after all memory
+ * has been configured and mapped but before any devices have been
+ * initialized.
+ *
+ ****************************************************************************/
-/************************************************************************************
- * Public Types
- ************************************************************************************/
+void s32k1xx_board_initialize(void)
+{
+#ifdef CONFIG_S32K1XX_SPI
+ /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak
+ * function s32k1xx_spidev_initialize() has been brought into the link.
+ */
-/************************************************************************************
- * Public Data
- ************************************************************************************/
+ s32k1xx_spidev_initialize();
+#endif
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
+#ifdef CONFIG_ARCH_LEDS
+ /* Configure on-board LEDs if LED support has been selected. */
+
+ board_autoled_initialize();
+#endif
+}
+
+/****************************************************************************
+ * Name: board_late_initialize
+ *
+ * Description:
+ * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
+ * initialization call will be performed in the boot-up sequence to a
+ * function called board_late_initialize(). board_late_initialize() will
+ * be called immediately after up_initialize() is called and just before
+ * the initial application is started. This additional initialization
+ * phase may be used, for example, to initialize board-specific device
+ * drivers.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_BOARD_LATE_INITIALIZE
+void board_late_initialize(void)
+{
+ /* Perform board-specific initialization */
-#endif /* __ARCH_ARM_SRC_S32K1XX_CHIP_H */
+ s32k1xx_bringup();
+}
+#endif
diff --git a/arch/arm/src/s32k1xx/chip.h b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_bringup.c
similarity index 61%
copy from arch/arm/src/s32k1xx/chip.h
copy to boards/arm/s32k1xx/s32k118evb/src/s32k1xx_bringup.c
index f3f9b9c..495468a 100644
--- a/arch/arm/src/s32k1xx/chip.h
+++ b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_bringup.c
@@ -1,5 +1,5 @@
-/************************************************************************************
- * arch/arm/src/s32k1xx/chip.h
+/****************************************************************************
+ * boards/arm/s32k1xx/s32k118evb/src/s32k1xx_bringup.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -31,47 +31,79 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ************************************************************************************/
+ ****************************************************************************/
-#ifndef __ARCH_ARM_SRC_S32K1XX_CHIP_H
-#define __ARCH_ARM_SRC_S32K1XX_CHIP_H
-
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
-/* Include the memory map and the chip definitions file. Other chip hardware files
- * should then include this file for the proper setup.
- */
+#include <sys/types.h>
+#include <sys/mount.h>
+#include <syslog.h>
+
+#ifdef CONFIG_BUTTONS
+# include <nuttx/input/buttons.h>
+#endif
+
+#ifdef CONFIG_USERLED
+# include <nuttx/leds/userled.h>
+#endif
+
+#include "s32k118evb.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: s32k1xx_bringup
+ *
+ * Description:
+ * Perform architecture-specific initialization
+ *
+ * CONFIG_BOARD_LATE_INITIALIZE=y :
+ * Called from board_late_initialize().
+ *
+ * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y :
+ * Called from the NSH library
+ *
+ ****************************************************************************/
-#include <arch/irq.h>
-#include "hardware/s32k1xx_memorymap.h"
+int s32k1xx_bringup(void)
+{
+ int ret = OK;
-/* The common ARMv6/7-M vector handling logic expects the following definitions in
- * this file. ARMV6/7M_PERIPHERAL_INTERRUPTS provides the number of supported
- * external interrupts which, for this architecture, is provided in the
- * arch/s32k1xx/irq.h header file.
- */
+#ifdef CONFIG_BUTTONS
+ /* Register the BUTTON driver */
-#define ARMV6M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT
-#define ARMV7M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT
+ ret = btn_lower_initialize("/dev/buttons");
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret);
+ }
+#endif
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
+#ifdef CONFIG_USERLED
+ /* Register the LED driver */
-/************************************************************************************
- * Public Types
- ************************************************************************************/
+ ret = userled_lower_initialize("/dev/userleds");
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret);
+ }
+#endif
-/************************************************************************************
- * Public Data
- ************************************************************************************/
+#ifdef CONFIG_FS_PROCFS
+ /* Mount the procfs file system */
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
+ ret = mount(NULL, "/proc", "procfs", 0, NULL);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret);
+ }
+#endif
-#endif /* __ARCH_ARM_SRC_S32K1XX_CHIP_H */
+ return ret;
+}
diff --git a/boards/arm/s32k1xx/s32k118evb/src/s32k118evb.h b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_buttons.c
similarity index 51%
copy from boards/arm/s32k1xx/s32k118evb/src/s32k118evb.h
copy to boards/arm/s32k1xx/s32k118evb/src/s32k1xx_buttons.c
index 4a0c3fb..b03eb86 100644
--- a/boards/arm/s32k1xx/s32k118evb/src/s32k118evb.h
+++ b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_buttons.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/arm/s32k1xx/s32k118evb/src/s32k118evb.h
+ * boards/arm/s32k1xx/s32k118evb/src/s32k1xx_buttons.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -33,104 +33,133 @@
*
****************************************************************************/
-#ifndef __BOARDS_ARM_S32K1XX_S32K118EVB_SRC_S32K118EVB_H
-#define __BOARDS_ARM_S32K1XX_S32K118EVB_SRC_S32K118EVB_H
+/* The S32K118EVB supports two buttons:
+ *
+ * SW2 PTD3
+ * SW3 PTD5
+ */
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
-#include <nuttx/compiler.h>
#include <stdint.h>
+#include <errno.h>
-#include "hardware/s32k1xx_pinmux.h"
-#include "s32k1xx_periphclocks.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
-/* Configuration ************************************************************/
+#include "s32k1xx_pin.h"
+#include "s32k118evb.h"
-/* S32K118EVB GPIOs *********************************************************/
+#include <arch/board/board.h>
-/* LEDs. The S32K118EVB has one RGB LED:
- *
- * RedLED PTD16 (FTM0CH1)
- * GreenLED PTD15 (FTM0CH0)
- * BlueLED PTE8 (FTM0CH6)
- *
- * An output of '1' illuminates the LED.
- */
+#ifdef CONFIG_ARCH_BUTTONS
-#define GPIO_LED_R (PIN_PTD16 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
-#define GPIO_LED_G (PIN_PTD15 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
-#define GPIO_LED_B (PIN_PTE8 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
-/* Buttons. The S32K118EVB supports two buttons:
+/****************************************************************************
+ * Name: board_button_initialize
*
- * SW2 PTD3
- * SW3 PTD5
- */
-
-#define GPIO_SW2 (PIN_PTD3 | PIN_INT_BOTH)
-#define GPIO_SW3 (PIN_PTD5 | PIN_INT_BOTH)
-
-/* SPI chip selects */
-
+ * Description:
+ * board_button_initialize() must be called to initialize button resources.
+ * After that, board_buttons() may be called to collect the current state
+ * of all buttons or board_button_irq() may be called to register button
+ * interrupt handlers.
+ *
+ ****************************************************************************/
-/* Count of peripheral clock user configurations */
+void board_button_initialize(void)
+{
+ /* Configure the GPIO pins as interrupting inputs. */
-#define NUM_OF_PERIPHERAL_CLOCKS_0 10
+ s32k1xx_pinconfig(GPIO_SW2);
+ s32k1xx_pinconfig(GPIO_SW3);
+}
/****************************************************************************
- * Public Types
+ * Name: board_buttons
****************************************************************************/
-/****************************************************************************
- * Public data
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
+uint32_t board_buttons(void)
+{
+ uint32_t ret = 0;
-/* User peripheral configuration structure 0 */
+ if (s32k1xx_gpioread(GPIO_SW2))
+ {
+ ret |= BUTTON_SW2_BIT;
+ }
-extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[];
+ if (s32k1xx_gpioread(GPIO_SW3))
+ {
+ ret |= BUTTON_SW3_BIT;
+ }
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
+ return ret;
+}
/****************************************************************************
- * Name: s32k118_bringup
+ * Button support.
*
* Description:
- * Perform architecture-specific initialization
+ * board_button_initialize() must be called to initialize button resources.
+ * After that, board_buttons() may be called to collect the current state
+ * of all buttons or board_button_irq() may be called to register button
+ * interrupt handlers.
*
- * CONFIG_BOARD_LATE_INITIALIZE=y :
- * Called from board_late_initialize().
+ * After board_button_initialize() has been called, board_buttons() may be
+ * called to collect the state of all buttons. board_buttons() returns a
+ * 32-bit bit set with each bit associated with a button. See the
+ * BUTTON_*_BIT definitions in board.h for the meaning of each bit.
*
- * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y :
- * Called from the NSH library
+ * board_button_irq() may be called to register an interrupt handler that
+ * will be called when a button is depressed or released. The ID value is
+ * a button enumeration value that uniquely identifies a button resource.
+ * See the BUTTON_* definitions in board.h for the meaning of enumeration
+ * value.
*
****************************************************************************/
-int s32k118_bringup(void);
-
-/****************************************************************************
- * Name: s32k118_spidev_initialize
- *
- * Description:
- * Called to configure SPI chip select GPIO pins for the s32k118evb
- * board.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_S32K1XX_SPI
-void s32k118_spidev_initialize(void);
+#ifdef CONFIG_ARCH_IRQBUTTONS
+int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg)
+{
+ uint32_t pinset;
+ int ret;
+
+ /* Map the button id to the GPIO bit set. */
+
+ if (id == BUTTON_SW2)
+ {
+ pinset = GPIO_SW2;
+ }
+ else if (id == BUTTON_SW3)
+ {
+ pinset = GPIO_SW3;
+ }
+ else
+ {
+ return -EINVAL;
+ }
+
+ /* The button has already been configured as an interrupting input (by
+ * board_button_initialize() above).
+ *
+ * Attach the new button handler.
+ */
+
+ ret = s32k1xx_pinirqattach(pinset, irqhandler, NULL);
+ if (ret >= 0)
+ {
+ /* Then make sure that interrupts are enabled on the pin */
+
+ s32k1xx_pinirqenable(pinset);
+ }
+
+ return ret;
+}
#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __BOARDS_ARM_S32K1XX_S32K118EVB_SRC_S32K118EVB_H */
+#endif /* CONFIG_ARCH_BUTTONS */
diff --git a/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_clockconfig.c b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_clockconfig.c
new file mode 100644
index 0000000..cbec87d
--- /dev/null
+++ b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_clockconfig.c
@@ -0,0 +1,208 @@
+/****************************************************************************
+ * boards/arm/s32k1xx/s32k118evb/src/s32k1xx_clockconfig.c
+ *
+ * Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Most of the settings within this file derives from NXP sample code for
+ * the S32K1XX MCUs. That sample code has this licensing information:
+ *
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "s32k1xx_clockconfig.h"
+#include "s32k1xx_start.h"
+#include "s32k118evb.h"
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* Each S32K1XX board must provide the following initialized structure.
+ * This is needed to establish the initial board clocking.
+ */
+
+const struct clock_configuration_s g_initial_clkconfig =
+{
+ .scg =
+ {
+ .sirc =
+ {
+ .range = SCG_SIRC_RANGE_HIGH, /* RANGE - High range (8 MHz) */
+ .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV1 */
+ .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV2 */
+ .initialize = true, /* Initialize */
+ .stopmode = false, /* SIRCSTEN */
+ .lowpower = true, /* SIRCLPEN */
+ .locked = false, /* LK */
+ },
+ .firc =
+ {
+ .range = SCG_FIRC_RANGE_48M, /* RANGE */
+ .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV1 */
+ .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV2 */
+ .initialize = true, /* Initialize */
+ .stopmode = false, /* */
+ .lowpower = false, /* */
+ .regulator = true, /* FIRCREGOFF */
+ .locked = false, /* LK */
+ },
+ .sosc =
+ {
+ .mode = SCG_SOSC_MONITOR_DISABLE, /* SOSCCM */
+ .gain = SCG_SOSC_GAIN_LOW, /* HGO */
+ .range = SCG_SOSC_RANGE_HIGH, /* RANGE */
+ .extref = SCG_SOSC_REF_OSC, /* EREFS */
+ .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV1 */
+ .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV2 */
+ .initialize = true, /* Initialize */
+ .stopmode = false, /* */
+ .lowpower = false, /* */
+ .locked = false, /* LK */
+ },
+ .rtc =
+ {
+ .initialize = true, /* Initialize */
+ .clkin = 0 /* RTC_CLKIN */
+ },
+ .clockout =
+ {
+ .source = SCG_CLOCKOUT_SRC_FIRC, /* SCG CLKOUTSEL */
+ .initialize = true, /* Initialize */
+ },
+ .clockmode =
+ {
+ .rccr = /* RCCR - Run Clock Control Register */
+ {
+ .src = SCG_SYSTEM_CLOCK_SRC_FIRC, /* SCS */
+ .divslow = 2, /* DIVSLOW, range 1..16 */
+ .divbus = 2, /* DIVBUS, range 1..16 */
+ .divcore = 1 /* DIVCORE, range 1..16 */
+ },
+ .vccr = /* VCCR - VLPR Clock Control Register */
+ {
+ .src = SCG_SYSTEM_CLOCK_SRC_SIRC, /* SCS */
+ .divslow = 4, /* DIVSLOW, range 1..16 */
+ .divbus = 1, /* DIVBUS, range 1..16 */
+ .divcore = 2 /* DIVCORE, range 1..16 */
+ },
+
+ /* .altclk */
+
+ .initialize = true, /* Initialize */
+ },
+ },
+ .sim =
+ {
+ .clockout = /* Clock Out configuration. */
+ {
+ .source = SIM_CLKOUT_SEL_SYSTEM_SCG_CLKOUT, /* CLKOUTSEL */
+ .divider = 1, /* CLKOUTDIV, range 1..8 */
+ .initialize = true, /* Initialize */
+ .enable = false, /* CLKOUTEN */
+ },
+ .lpoclk = /* Low Power Clock configuration. */
+ {
+ .rtc_source = SIM_RTCCLK_SEL_SOSCDIV1_CLK, /* RTCCLKSEL */
+ .lpo_source = SIM_LPO_CLK_SEL_LPO_128K, /* LPOCLKSEL */
+ .initialize = true, /* Initialize */
+ .lpo32k = true, /* LPO32KCLKEN */
+ .lpo1k = true, /* LPO1KCLKEN */
+ },
+ .tclk = /* TCLK CLOCK configuration. */
+ {
+ .tclkfreq[0] = 0, /* TCLK0 */
+ .tclkfreq[1] = 0, /* TCLK1 */
+ .tclkfreq[2] = 0, /* TCLK2 */
+ .initialize = true, /* Initialize */
+ },
+ .platgate = /* Platform Gate Clock configuration. */
+ {
+ .initialize = true, /* Initialize */
+ .mscm = true, /* CGCMSCM */
+ .mpu = true, /* CGCMPU */
+ .dma = true, /* CGCDMA */
+ .erm = true, /* CGCERM */
+ .eim = true, /* CGCEIM */
+ },
+ .traceclk = /* Debug trace Clock Configuration. */
+ {
+ .source = CLOCK_TRACE_SRC_CORE_CLK, /* TRACECLK_SEL */
+ .divider = 1, /* TRACEDIV, range 1..8 */
+ .initialize = true, /* Initialize */
+ .enable = true, /* TRACEDIVEN */
+ .fraction = false, /* TRACEFRAC */
+ },
+#ifdef CONFIG_S32K1XX_HAVE_QSPI
+ .qspirefclk = /* Quad Spi Internal Reference Clock Gating. */
+ {
+ .refclk = false, /* Qspi reference clock gating */
+ },
+#endif
+ },
+ .pcc =
+ {
+ .count = NUM_OF_PERIPHERAL_CLOCKS_0, /* Number peripheral clock configurations */
+ .pclks = g_peripheral_clockconfig0 /* Peripheral clock configurations */
+ },
+ .pmc =
+ {
+ .lpoclk = /* Low Power Clock configuration. */
+ {
+ .trim = 0, /* Trimming value for LPO */
+ .initialize = true, /* Initialize */
+ .enable = true, /* Enable/disable LPO */
+ },
+ }
+};
diff --git a/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_periphclocks.c b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_periphclocks.c
new file mode 100644
index 0000000..370d7e4
--- /dev/null
+++ b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_periphclocks.c
@@ -0,0 +1,152 @@
+/****************************************************************************
+ * boards/arm/s32k1xx/s32k118evb/src/s32k1xx_periphclks.c
+ *
+ * Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Most of the settings within this file derives from NXP sample code for
+ * the S32K1XX MCUs. That sample code has this licensing information:
+ *
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "s32k1xx_periphclocks.h"
+#include "s32k118evb.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* Each S32K1XX board must provide the following initialized structure.
+ * This is needed to establish the initial peripheral clocking.
+ */
+
+const struct peripheral_clock_config_s g_peripheral_clockconfig0[] =
+{
+ {
+ .clkname = ADC0_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_SIRC_DIV2,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = DMAMUX0_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_OFF,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = LPTMR0_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_SIRC_DIV2,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = LPUART0_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_SIRC_DIV2,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = LPUART1_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_SIRC_DIV2,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = PORTA_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_OFF,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = PORTB_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_OFF,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = PORTC_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_OFF,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = PORTD_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_OFF,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+ {
+ .clkname = PORTE_CLK,
+ .clkgate = true,
+ .clksrc = CLK_SRC_OFF,
+ .frac = MULTIPLY_BY_ONE,
+ .divider = 1,
+ },
+};
diff --git a/arch/arm/src/s32k1xx/chip.h b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_userleds.c
similarity index 63%
copy from arch/arm/src/s32k1xx/chip.h
copy to boards/arm/s32k1xx/s32k118evb/src/s32k1xx_userleds.c
index f3f9b9c..5091c46 100644
--- a/arch/arm/src/s32k1xx/chip.h
+++ b/boards/arm/s32k1xx/s32k118evb/src/s32k1xx_userleds.c
@@ -1,5 +1,5 @@
-/************************************************************************************
- * arch/arm/src/s32k1xx/chip.h
+/****************************************************************************
+ * boards/arm/s32k1xx/s32k118evb/src/s32k1xx_userleds.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -31,47 +31,86 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ************************************************************************************/
+ ****************************************************************************/
-#ifndef __ARCH_ARM_SRC_S32K1XX_CHIP_H
-#define __ARCH_ARM_SRC_S32K1XX_CHIP_H
-
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
-/* Include the memory map and the chip definitions file. Other chip hardware files
- * should then include this file for the proper setup.
- */
-
-#include <arch/irq.h>
-#include "hardware/s32k1xx_memorymap.h"
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
-/* The common ARMv6/7-M vector handling logic expects the following definitions in
- * this file. ARMV6/7M_PERIPHERAL_INTERRUPTS provides the number of supported
- * external interrupts which, for this architecture, is provided in the
- * arch/s32k1xx/irq.h header file.
- */
+#include <nuttx/board.h>
-#define ARMV6M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT
-#define ARMV7M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT
+#include "up_arch.h"
+#include "up_internal.h"
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
+#include "s32k1xx_pin.h"
+#include "s32k118evb.h"
-/************************************************************************************
- * Public Types
- ************************************************************************************/
+#include <arch/board/board.h>
-/************************************************************************************
- * Public Data
- ************************************************************************************/
+#ifndef CONFIG_ARCH_LEDS
-/************************************************************************************
+/****************************************************************************
* Public Functions
- ************************************************************************************/
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_userled_initialize
+ ****************************************************************************/
+
+void board_userled_initialize(void)
+{
+ /* Configure LED GPIOs for output */
+
+ s32k1xx_pinconfig(GPIO_LED_R);
+ s32k1xx_pinconfig(GPIO_LED_G);
+ s32k1xx_pinconfig(GPIO_LED_B);
+}
+
+/****************************************************************************
+ * Name: board_userled
+ ****************************************************************************/
+
+void board_userled(int led, bool ledon)
+{
+ uint32_t ledcfg;
+
+ if (led == BOARD_LED_R)
+ {
+ ledcfg = GPIO_LED_R;
+ }
+ else if (led == BOARD_LED_G)
+ {
+ ledcfg = GPIO_LED_G;
+ }
+ else if (led == BOARD_LED_B)
+ {
+ ledcfg = GPIO_LED_B;
+ }
+ else
+ {
+ return;
+ }
+
+ s32k1xx_gpiowrite(ledcfg, ledon); /* High illuminates */
+}
+
+/****************************************************************************
+ * Name: board_userled_all
+ ****************************************************************************/
+
+void board_userled_all(uint8_t ledset)
+{
+ /* Low illuminates */
+
+ s32k1xx_gpiowrite(GPIO_LED_R, (ledset & BOARD_LED_R_BIT) != 0);
+ s32k1xx_gpiowrite(GPIO_LED_G, (ledset & BOARD_LED_G_BIT) != 0);
+ s32k1xx_gpiowrite(GPIO_LED_B, (ledset & BOARD_LED_B_BIT) != 0);
+}
-#endif /* __ARCH_ARM_SRC_S32K1XX_CHIP_H */
+#endif /* !CONFIG_ARCH_LEDS */
diff --git a/boards/arm/s32k1xx/s32k144evb/Kconfig b/boards/arm/s32k1xx/s32k144evb/Kconfig
new file mode 100644
index 0000000..cbc4ad6
--- /dev/null
+++ b/boards/arm/s32k1xx/s32k144evb/Kconfig
@@ -0,0 +1,8 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_BOARD_S32K144EVB
+
+endif # ARCH_BOARD_S32K144EVB
diff --git a/boards/arm/s32k1xx/s32k144evb/README.txt b/boards/arm/s32k1xx/s32k144evb/README.txt
new file mode 100644
index 0000000..eb55fb7
--- /dev/null
+++ b/boards/arm/s32k1xx/s32k144evb/README.txt
@@ -0,0 +1,15 @@
+README
+======
+
+This directory holds the port to the NXP S32K144EVB-Q100 development board.
+
+Contents
+========
+
+ o Status
+
+Status
+======
+
+ 2020-01-23: Configuration created (copy-paste from S32K146EVB).
+ Tested: Serial console, I2C, SPI.
\ No newline at end of file
diff --git a/boards/arm/s32k1xx/s32k146evb/configs/nsh/defconfig b/boards/arm/s32k1xx/s32k144evb/configs/nsh/defconfig
similarity index 88%
copy from boards/arm/s32k1xx/s32k146evb/configs/nsh/defconfig
copy to boards/arm/s32k1xx/s32k144evb/configs/nsh/defconfig
index e409d5a..8269069 100644
--- a/boards/arm/s32k1xx/s32k146evb/configs/nsh/defconfig
+++ b/boards/arm/s32k1xx/s32k144evb/configs/nsh/defconfig
@@ -10,14 +10,14 @@
# CONFIG_NSH_CMDOPT_HEXDUMP is not set
# CONFIG_NSH_CMDPARMS is not set
CONFIG_ARCH="arm"
-CONFIG_ARCH_BOARD="s32k146evb"
-CONFIG_ARCH_BOARD_S32K146EVB=y
+CONFIG_ARCH_BOARD="s32k144evb"
+CONFIG_ARCH_BOARD_S32K144EVB=y
CONFIG_ARCH_CHIP="s32k1xx"
-CONFIG_ARCH_CHIP_S32K146=y
+CONFIG_ARCH_CHIP_S32K144=y
CONFIG_ARCH_CHIP_S32K14X=y
CONFIG_ARCH_CHIP_S32K1XX=y
CONFIG_ARCH_STACKDUMP=y
-CONFIG_BOARD_LOOPSPERMSEC=2988
+CONFIG_BOARD_LOOPSPERMSEC=3997
CONFIG_BUILTIN=y
CONFIG_EXAMPLES_HELLO=y
CONFIG_FS_PROCFS=y
@@ -38,8 +38,8 @@ CONFIG_NSH_READLINE=y
CONFIG_PREALLOC_MQ_MSGS=4
CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=16
-CONFIG_RAM_SIZE=23552
-CONFIG_RAM_START=0x1ffffc00
+CONFIG_RAM_SIZE=61440
+CONFIG_RAM_START=0x1fff8000
CONFIG_RR_INTERVAL=200
CONFIG_S32K1XX_LPUART1=y
CONFIG_SCHED_WAITPID=y
diff --git a/boards/arm/s32k1xx/s32k146evb/include/board.h b/boards/arm/s32k1xx/s32k144evb/include/board.h
similarity index 74%
copy from boards/arm/s32k1xx/s32k146evb/include/board.h
copy to boards/arm/s32k1xx/s32k144evb/include/board.h
index da991a1..de63802 100644
--- a/boards/arm/s32k1xx/s32k146evb/include/board.h
+++ b/boards/arm/s32k1xx/s32k144evb/include/board.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/arm/s32k1xx/s32k146evb/include/board.h
+ * boards/arm/s32k1xx/s32k144evb/include/board.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -33,8 +33,8 @@
*
****************************************************************************/
-#ifndef __BOARDS_ARM_STM32F4DISCOVERY_INCLUDE_BOARD_H
-#define __BOARDS_ARM_STM32F4DISCOVERY_INCLUDE_BOARD_H
+#ifndef __BOARDS_ARM_S32K144EVB_INCLUDE_BOARD_H
+#define __BOARDS_ARM_S32K144EVB_INCLUDE_BOARD_H
/****************************************************************************
* Included Files
@@ -53,15 +53,15 @@
/* Clocking *****************************************************************/
-/* The S32K146EVB is fitted with a 8MHz Crystal */
+/* The S32K144EVB is fitted with a 8MHz Crystal */
#define BOARD_XTAL_FREQUENCY 8000000
-/* The S32K146 will run at 112MHz */
+/* The S32K144 will run at 112MHz */
/* LED definitions **********************************************************/
-/* The S32K146EVB has one RGB LED:
+/* The S32K144EVB has one RGB LED:
*
* RedLED PTD15 (FTM0 CH0)
* GreenLED PTD16 (FTM0 CH1)
@@ -89,10 +89,9 @@
#define BOARD_LED_B_BIT (1 << BOARD_LED_B)
/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LEDs on board
- * the s32k146evb. The following definitions describe how NuttX controls the
+ * the S32K144EVB. The following definitions describe how NuttX controls the
* LEDs:
*
- *
* SYMBOL Meaning LED state
* RED GREEN BLUE
* ------------------- ---------------------------- -----------------
@@ -106,11 +105,11 @@
#define LED_SIGNAL 0 /* In a signal handler (no change) */
#define LED_ASSERTION 0 /* An assertion failed (no change) */
#define LED_PANIC 4 /* The system has crashed FLASH OFF OFF */
-#undef LED_IDLE /* S32K146EVN in sleep mode (Not used) */
+#undef LED_IDLE /* S32K144EVB in sleep mode (Not used) */
/* Button definitions *******************************************************/
-/* The S32K146EVB supports two buttons:
+/* The S32K144EVB supports two buttons:
*
* SW2 PTC12
* SW3 PTC13
@@ -131,10 +130,35 @@
* OpenSDA UART RX PTC6 (LPUART1_RX)
*/
+#define PIN_LPUART0_RX PIN_LPUART0_RX_1 /* PTB0 */
+#define PIN_LPUART0_TX PIN_LPUART0_TX_1 /* PTB1 */
+
#define PIN_LPUART1_RX PIN_LPUART1_RX_1 /* PTC6 */
#define PIN_LPUART1_TX PIN_LPUART1_TX_1 /* PTC7 */
-/* DMA Channel/Stream Selections ********************************************/
+#define PIN_LPUART2_RX PIN_LPUART2_RX_1 /* PTA8 */
+#define PIN_LPUART2_TX PIN_LPUART2_TX_1 /* PTA9 */
+
+/* SPI selections ***********************************************************/
+
+#define PIN_LPSPI0_SCK PIN_LPSPI0_SCK_2 /* PTB2 */
+#define PIN_LPSPI0_MISO PIN_LPSPI0_SIN_2 /* PTB3 */
+#define PIN_LPSPI0_MOSI PIN_LPSPI0_SOUT_3 /* PTB4 */
+#define PIN_LPSPI0_PCS PIN_LPSPI0_PCS0_1 /* PTB0 */
+
+#define PIN_LPSPI1_SCK PIN_LPSPI1_SCK_1 /* PTB14 */
+#define PIN_LPSPI1_MISO PIN_LPSPI1_SIN_1 /* PTB15 */
+#define PIN_LPSPI1_MOSI PIN_LPSPI1_SOUT_1 /* PTB16 */
+#define PIN_LPSPI1_PCS PIN_LPSPI1_PCS3 /* PTB17 */
+
+#define PIN_LPSPI2_SCK PIN_LPSPI2_SCK_2 /* PTE15 */
+#define PIN_LPSPI2_MISO PIN_LPSPI2_SIN_2 /* PTE16 */
+#define PIN_LPSPI2_MOSI PIN_LPSPI2_SOUT_1 /* PTA8 */
+#define PIN_LPSPI2_PCS PIN_LPSPI2_PCS0_2 /* PTA9 */
+
+/* I2C selections ***********************************************************/
+#define PIN_LPI2C0_SCL PIN_LPI2C0_SCL_2 /* PTA3 */
+#define PIN_LPI2C0_SDA PIN_LPI2C0_SDA_2 /* PTA2 */
-#endif /* __BOARDS_ARM_STM32F4DISCOVERY_INCLUDE_BOARD_H */
+#endif /* __BOARDS_ARM_S32K144EVB_INCLUDE_BOARD_H */
diff --git a/boards/arm/s32k1xx/s32k144evb/scripts/Make.defs b/boards/arm/s32k1xx/s32k144evb/scripts/Make.defs
new file mode 100644
index 0000000..985e30c
--- /dev/null
+++ b/boards/arm/s32k1xx/s32k144evb/scripts/Make.defs
@@ -0,0 +1,131 @@
+############################################################################
+# boards/arm/s32k1xx/s32k144evb/scripts/Make.defs
+#
+# Copyright (C) 2018 Gregory Nutt. All rights reserved.
+# Author: Gregory Nutt <gn...@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+# used to endorse or promote products derived from this software
+# without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+include ${TOPDIR}/.config
+include ${TOPDIR}/tools/Config.mk
+include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs
+
+ifeq ($(CONFIG_BOOT_RUNFROMFLASH),y)
+ LDSCRIPT = flash.ld
+else ifeq ($(CONFIG_BOOT_RUNFROMISRAM),y)
+ LDSCRIPT = sram.ld
+endif
+
+$(warning, LDSCRIPT is $(LDSCRIPT))
+ifeq ($(WINTOOL),y)
+ # Windows-native toolchains
+ ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
+ ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
+ ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
+else
+ # Linux/Cygwin-native toolchain
+ ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
+ ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
+ ARCHSCRIPT = -T$(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
+endif
+$(warning, LDSCRIPT is $(LDSCRIPT))
+$(warning, ARCHSCRIPT is $(ARCHSCRIPT))
+
+CC = $(CROSSDEV)gcc
+CXX = $(CROSSDEV)g++
+CPP = $(CROSSDEV)gcc -E
+LD = $(CROSSDEV)ld
+STRIP = $(CROSSDEV)strip --strip-unneeded
+AR = $(ARCROSSDEV)ar rcs
+NM = $(ARCROSSDEV)nm
+OBJCOPY = $(CROSSDEV)objcopy
+OBJDUMP = $(CROSSDEV)objdump
+
+ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
+ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
+
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+ ARCHOPTIMIZATION = -g
+endif
+
+ifneq ($(CONFIG_DEBUG_NOOPT),y)
+ ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
+endif
+
+ARCHCFLAGS = -fno-builtin
+ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
+ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
+ARCHWARNINGSXX = -Wall -Wshadow -Wundef
+ARCHDEFINES =
+ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
+
+CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
+AFLAGS = $(CFLAGS) -D__ASSEMBLY__
+
+NXFLATLDFLAGS1 = -r -d -warn-common
+NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
+LDNXFLATFLAGS = -e main -s 2048
+
+ASMEXT = .S
+OBJEXT = .o
+LIBEXT = .a
+EXEEXT =
+
+ifneq ($(CROSSDEV),arm-nuttx-elf-)
+ LDFLAGS += -nostartfiles -nodefaultlibs
+endif
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+ LDFLAGS += -g
+endif
+
+
+HOSTCC = gcc
+HOSTINCLUDES = -I.
+HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
+HOSTLDFLAGS =
+ifeq ($(CONFIG_HOST_WINDOWS),y)
+ HOSTEXEEXT = .exe
+else
+ HOSTEXEEXT =
+endif
+
+ifeq ($(WINTOOL),y)
+ # Windows-native host tools
+ DIRLINK = $(TOPDIR)/tools/copydir.sh
+ DIRUNLINK = $(TOPDIR)/tools/unlink.sh
+ MKDEP = $(TOPDIR)/tools/mkwindeps.sh
+else
+ # Linux/Cygwin-native host tools
+ MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
+endif
diff --git a/boards/arm/s32k1xx/s32k148evb/scripts/flash.ld b/boards/arm/s32k1xx/s32k144evb/scripts/flash.ld
similarity index 91%
copy from boards/arm/s32k1xx/s32k148evb/scripts/flash.ld
copy to boards/arm/s32k1xx/s32k144evb/scripts/flash.ld
index b59ab9b..8d153a6 100644
--- a/boards/arm/s32k1xx/s32k148evb/scripts/flash.ld
+++ b/boards/arm/s32k1xx/s32k144evb/scripts/flash.ld
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/arm/s32k1xx/s32k148evb/scripts/flash.ld
+ * boards/arm/s32k1xx/s32k144evb/scripts/flash.ld
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -33,23 +33,23 @@
*
****************************************************************************/
-/* The S32K148 has 2Mb of FLASH beginning at address 0x0000:0000 and
- * 252Kb of SRAM beginning at address 0x1ffe:0000 (plus 4Kb of FlexRAM)
+/* The S32K144 has 512Kb of FLASH beginning at address 0x0000:0000 and
+ * 60Kb of SRAM beginning at address 0x1fff:8000 (plus 4Kb of FlexRAM)
*
* The on-chip RAM is split in two regions: SRAM_L and SRAM_U. The RAM is
* implemented such that the SRAM_L and SRAM_U ranges form a contiguous
* block in the memory map
*
- * SRAM_L 1ffe0000 - 1fffffff 128Kb
- * SRAM_U 20000000 - 2001efff 124Kb
+ * SRAM_L 1fff8000 - 1fffffff 32Kb
+ * SRAM_U 20000000 - 20006fff 28Kb
*/
MEMORY
{
vflash (rx) : ORIGIN = 0x00000000, LENGTH = 1K
pflash (rx) : ORIGIN = 0x00000400, LENGTH = 16
- dflash (rx) : ORIGIN = 0x00000410, LENGTH = 2047K-16
- sram (rwx) : ORIGIN = 0x1fff0000, LENGTH = 252K
+ dflash (rx) : ORIGIN = 0x00000410, LENGTH = 511K-16
+ sram (rwx) : ORIGIN = 0x1fff8000, LENGTH = 60K
}
OUTPUT_ARCH(arm)
diff --git a/boards/arm/s32k1xx/s32k144evb/scripts/s32k144.cfg b/boards/arm/s32k1xx/s32k144evb/scripts/s32k144.cfg
new file mode 100644
index 0000000..7d30a9f
--- /dev/null
+++ b/boards/arm/s32k1xx/s32k144evb/scripts/s32k144.cfg
@@ -0,0 +1,58 @@
+#
+# NXP S32K144 - 1x ARM Cortex-M4 @ up to 112 MHz
+#
+
+adapter_khz 4000
+transport select swd
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME s32k144
+}
+
+#
+# M4 JTAG mode TAP
+#
+if { [info exists M4_JTAG_TAPID] } {
+ set _M4_JTAG_TAPID $M4_JTAG_TAPID
+} else {
+ set _M4_JTAG_TAPID 0x4ba00477
+}
+
+#
+# M4 SWD mode TAP
+#
+if { [info exists M4_SWD_TAPID] } {
+ set _M4_SWD_TAPID $M4_SWD_TAPID
+} else {
+ set _M4_SWD_TAPID 0x2ba01477
+}
+
+source [find target/swj-dp.tcl]
+
+if { [using_jtag] } {
+ set _M4_TAPID $_M4_JTAG_TAPID
+} else {
+ set _M4_TAPID $_M4_SWD_TAPID
+}
+
+swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
+ -expected-id $_M4_TAPID
+
+target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4
+
+# S32K144 has 32+28 KB contiguous SRAM
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ set _WORKAREASIZE 0xF000
+}
+$_CHIPNAME.m4 configure -work-area-phys 0x1FFF8000 \
+ -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+$_CHIPNAME.m4 configure -rtos nuttx
+
+if { ![using_hla] } {
+ cortex_m reset_config vectreset
+}
diff --git a/boards/arm/s32k1xx/s32k148evb/scripts/sram.ld b/boards/arm/s32k1xx/s32k144evb/scripts/sram.ld
similarity index 90%
copy from boards/arm/s32k1xx/s32k148evb/scripts/sram.ld
copy to boards/arm/s32k1xx/s32k144evb/scripts/sram.ld
index c5819bf..210555e 100644
--- a/boards/arm/s32k1xx/s32k148evb/scripts/sram.ld
+++ b/boards/arm/s32k1xx/s32k144evb/scripts/sram.ld
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/arm/s32k1xx/s32k148evb/scripts/sram.ld
+ * boards/arm/s32k1xx/s32k144evb/scripts/sram.ld
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -33,21 +33,21 @@
*
****************************************************************************/
-/* The S32K148 has 2Mb of FLASH beginning at address 0x0000:0000 and
- * 252Kb of SRAM beginning at address 0x1ffe:0000 (plus 4Kb of FlexRAM)
+/* The S32K144 has 512Kb of FLASH beginning at address 0x0000:0000 and
+ * 60Kb of SRAM beginning at address 0x1fff:8000 (plus 4Kb of FlexRAM)
*
* The on-chip RAM is split in two regions: SRAM_L and SRAM_U. The RAM is
* implemented such that the SRAM_L and SRAM_U ranges form a contiguous
* block in the memory map
*
- * SRAM_L 1ffe0000 - 1fffffff 128Kb
- * SRAM_U 20000000 - 2001efff 124Kb
+ * SRAM_L 1fff8000 - 1fffffff 32Kb
+ * SRAM_U 20000000 - 20006fff 28Kb
*/
MEMORY
{
- flash (rx) : ORIGIN = 0x00000000, LENGTH = 2M
- sram (rwx) : ORIGIN = 0x1fff0000, LENGTH = 252K
+ flash (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+ sram (rwx) : ORIGIN = 0x1fff8000, LENGTH = 60K
}
OUTPUT_ARCH(arm)
diff --git a/boards/arm/s32k1xx/s32k144evb/src/.gitignore b/boards/arm/s32k1xx/s32k144evb/src/.gitignore
new file mode 100644
index 0000000..726d936
--- /dev/null
+++ b/boards/arm/s32k1xx/s32k144evb/src/.gitignore
@@ -0,0 +1,2 @@
+/.depend
+/Make.dep
diff --git a/boards/arm/s32k1xx/s32k146evb/src/Makefile b/boards/arm/s32k1xx/s32k144evb/src/Makefile
similarity index 85%
copy from boards/arm/s32k1xx/s32k146evb/src/Makefile
copy to boards/arm/s32k1xx/s32k144evb/src/Makefile
index 5237a26..27d9e16 100644
--- a/boards/arm/s32k1xx/s32k146evb/src/Makefile
+++ b/boards/arm/s32k1xx/s32k144evb/src/Makefile
@@ -1,5 +1,5 @@
############################################################################
-# boards/arm/s32k1xx/s32k146evb/src/Makefile
+# boards/arm/s32k1xx/s32k144evb/src/Makefile
#
# Copyright (C) 2019 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gn...@nuttx.org>
@@ -36,21 +36,25 @@
-include $(TOPDIR)/Make.defs
ASRCS =
-CSRCS = s32k146_boot.c s32k146_bringup.c s32k146_clockconfig.c
-CSRCS += s32k146_periphclocks.c
+CSRCS = s32k1xx_boot.c s32k1xx_bringup.c s32k1xx_clockconfig.c
+CSRCS += s32k1xx_periphclocks.c
ifeq ($(CONFIG_ARCH_LEDS),y)
-CSRCS += s32k146_autoleds.c
+CSRCS += s32k1xx_autoleds.c
else
-CSRCS += s32k146_userleds.c
+CSRCS += s32k1xx_userleds.c
endif
ifeq ($(CONFIG_ARCH_BUTTONS),y)
-CSRCS += s32k146_buttons.c
+CSRCS += s32k1xx_buttons.c
endif
ifeq ($(CONFIG_LIB_BOARDCTL),y)
-CSRCS += s32k146_appinit.c
+CSRCS += s32k1xx_appinit.c
+endif
+
+ifeq ($(CONFIG_S32K1XX_LPSPI),y)
+CSRCS += s32k1xx_spi.c
endif
include $(TOPDIR)/boards/Board.mk
diff --git a/boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h b/boards/arm/s32k1xx/s32k144evb/src/s32k144evb.h
similarity index 84%
copy from boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h
copy to boards/arm/s32k1xx/s32k144evb/src/s32k144evb.h
index 13cfc0c..546b44b 100644
--- a/boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h
+++ b/boards/arm/s32k1xx/s32k144evb/src/s32k144evb.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h
+ * boards/arm/s32k1xx/s32k144evb/src/s32k144evb.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -33,8 +33,8 @@
*
****************************************************************************/
-#ifndef __BOARDS_ARM_S32K1XX_S32K146EVB_SRC_S32K146EVB_H
-#define __BOARDS_ARM_S32K1XX_S32K146EVB_SRC_S32K146EVB_H
+#ifndef __BOARDS_ARM_S32K1XX_S32K144EVB_SRC_S32K144EVB_H
+#define __BOARDS_ARM_S32K1XX_S32K144EVB_SRC_S32K144EVB_H
/****************************************************************************
* Included Files
@@ -54,9 +54,9 @@
/* Configuration ************************************************************/
-/* S32K146EVB GPIOs *********************************************************/
+/* S32K144EVB GPIOs *********************************************************/
-/* LEDs. The S32K146EVB has one RGB LED:
+/* LEDs. The S32K144EVB has one RGB LED:
*
* RedLED PTD15 (FTM0 CH0)
* GreenLED PTD16 (FTM0 CH1)
@@ -67,9 +67,9 @@
#define GPIO_LED_R (PIN_PTD15 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
#define GPIO_LED_G (PIN_PTD16 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
-#define GPIO_LED_B (PIN_PTE8 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
+#define GPIO_LED_B (PIN_PTD0 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
-/* Buttons. The S32K146EVB supports two buttons:
+/* Buttons. The S32K144EVB supports two buttons:
*
* SW2 PTC12
* SW3 PTC13
@@ -80,17 +80,16 @@
/* SPI chip selects */
-
/* Count of peripheral clock user configurations */
-#define NUM_OF_PERIPHERAL_CLOCKS_0 11
+#define NUM_OF_PERIPHERAL_CLOCKS_0 15
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
- * Public data
+ * Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
@@ -100,11 +99,11 @@
extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[];
/****************************************************************************
- * Public Functions
+ * Public Function Prototypes
****************************************************************************/
/****************************************************************************
- * Name: s32k146_bringup
+ * Name: s32k1xx_bringup
*
* Description:
* Perform architecture-specific initialization
@@ -117,20 +116,20 @@ extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[];
*
****************************************************************************/
-int s32k146_bringup(void);
+int s32k1xx_bringup(void);
/****************************************************************************
- * Name: s32k146_spidev_initialize
+ * Name: s32k1xx_spidev_initialize
*
* Description:
- * Called to configure SPI chip select GPIO pins for the s32k146evb
+ * Called to configure SPI chip select GPIO pins for the S32K144EVB
* board.
*
****************************************************************************/
-#ifdef CONFIG_S32K1XX_SPI
-void s32k146_spidev_initialize(void);
+#ifdef CONFIG_S32K1XX_LPSPI
+void s32k1xx_spidev_initialize(void);
#endif
#endif /* __ASSEMBLY__ */
-#endif /* __BOARDS_ARM_S32K1XX_S32K146EVB_SRC_S32K146EVB_H */
+#endif /* __BOARDS_ARM_S32K1XX_S32K144EVB_SRC_S32K144EVB_H */
diff --git a/arch/arm/src/s32k1xx/chip.h b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_appinit.c
similarity index 59%
copy from arch/arm/src/s32k1xx/chip.h
copy to boards/arm/s32k1xx/s32k144evb/src/s32k1xx_appinit.c
index f3f9b9c..3806a16 100644
--- a/arch/arm/src/s32k1xx/chip.h
+++ b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_appinit.c
@@ -1,5 +1,5 @@
-/************************************************************************************
- * arch/arm/src/s32k1xx/chip.h
+/****************************************************************************
+ * boards/arm/s32k1xx/s32k144evb/src/s32k1xx_appinit.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -31,47 +31,64 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ************************************************************************************/
+ ****************************************************************************/
-#ifndef __ARCH_ARM_SRC_S32K1XX_CHIP_H
-#define __ARCH_ARM_SRC_S32K1XX_CHIP_H
-
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
-/* Include the memory map and the chip definitions file. Other chip hardware files
- * should then include this file for the proper setup.
- */
+#include <nuttx/board.h>
-#include <arch/irq.h>
-#include "hardware/s32k1xx_memorymap.h"
+#include "s32k144evb.h"
-/* The common ARMv6/7-M vector handling logic expects the following definitions in
- * this file. ARMV6/7M_PERIPHERAL_INTERRUPTS provides the number of supported
- * external interrupts which, for this architecture, is provided in the
- * arch/s32k1xx/irq.h header file.
- */
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
-#define ARMV6M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT
-#define ARMV7M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT
+#ifndef OK
+# define OK 0
+#endif
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
-/************************************************************************************
- * Public Types
- ************************************************************************************/
+/****************************************************************************
+ * Name: board_app_initialize
+ *
+ * Description:
+ * Perform application specific initialization. This function is never
+ * called directly from application code, but only indirectly via the
+ * (non-standard) boardctl() interface using the command BOARDIOC_INIT.
+ *
+ * Input Parameters:
+ * arg - The boardctl() argument is passed to the board_app_initialize()
+ * implementation without modification. The argument has no
+ * meaning to NuttX; the meaning of the argument is a contract
+ * between the board-specific initialization logic and the
+ * matching application logic. The value cold be such things as a
+ * mode enumeration value, a set of DIP switch switch settings, a
+ * pointer to configuration data read from a file or serial FLASH,
+ * or whatever you would like to do with it. Every implementation
+ * should accept zero/NULL as a default configuration.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned on
+ * any failure to indicate the nature of the failure.
+ *
+ ****************************************************************************/
-/************************************************************************************
- * Public Data
- ************************************************************************************/
+int board_app_initialize(uintptr_t arg)
+{
+#ifdef CONFIG_BOARD_LATE_INITIALIZE
+ /* Board initialization already performed by board_late_initialize() */
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
+ return OK;
+#else
+ /* Perform board-specific initialization */
-#endif /* __ARCH_ARM_SRC_S32K1XX_CHIP_H */
+ return s32k1xx_bringup();
+#endif
+}
diff --git a/boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_autoleds.c
similarity index 52%
copy from boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h
copy to boards/arm/s32k1xx/s32k144evb/src/s32k1xx_autoleds.c
index 13cfc0c..6d41b8a 100644
--- a/boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h
+++ b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_autoleds.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h
+ * boards/arm/s32k1xx/s32k144evb/src/s32k1xx_autoleds.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -33,104 +33,133 @@
*
****************************************************************************/
-#ifndef __BOARDS_ARM_S32K1XX_S32K146EVB_SRC_S32K146EVB_H
-#define __BOARDS_ARM_S32K1XX_S32K146EVB_SRC_S32K146EVB_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-#include <nuttx/compiler.h>
-
-#include <stdint.h>
-
-#include "hardware/s32k1xx_pinmux.h"
-#include "s32k1xx_periphclocks.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* Configuration ************************************************************/
-
-/* S32K146EVB GPIOs *********************************************************/
-
-/* LEDs. The S32K146EVB has one RGB LED:
+/* The S32K144EVB has one RGB LED:
*
* RedLED PTD15 (FTM0 CH0)
* GreenLED PTD16 (FTM0 CH1)
* BlueLED PTD0 (FTM0 CH2)
*
* An output of '1' illuminates the LED.
+ *
+ * If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board
+ * the Freedom K66F. The following definitions describe how NuttX controls
+ * the LEDs:
+ *
+ * SYMBOL Meaning LED state
+ * RED GREEN BLUE
+ * ------------------- ----------------------- -----------------
+ * LED_STARTED NuttX has been started OFF OFF OFF
+ * LED_HEAPALLOCATE Heap has been allocated OFF OFF ON
+ * LED_IRQSENABLED Interrupts enabled OFF OFF ON
+ * LED_STACKCREATED Idle stack created OFF ON OFF
+ * LED_INIRQ In an interrupt (no change)
+ * LED_SIGNAL In a signal handler (no change)
+ * LED_ASSERTION An assertion failed (no change)
+ * LED_PANIC The system has crashed FLASH OFF OFF
+ * LED_IDLE K66 is in sleep mode (Optional, not used)
*/
-#define GPIO_LED_R (PIN_PTD15 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
-#define GPIO_LED_G (PIN_PTD16 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
-#define GPIO_LED_B (PIN_PTE8 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
-/* Buttons. The S32K146EVB supports two buttons:
- *
- * SW2 PTC12
- * SW3 PTC13
- */
+#include <nuttx/config.h>
-#define GPIO_SW2 (PIN_PTC12 | PIN_INT_BOTH)
-#define GPIO_SW3 (PIN_PTC13 | PIN_INT_BOTH)
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
-/* SPI chip selects */
+#include <nuttx/board.h>
+#include <arch/board/board.h>
+#include "up_arch.h"
+#include "up_internal.h"
-/* Count of peripheral clock user configurations */
+#include "s32k1xx_pin.h"
+#include "s32k144evb.h"
-#define NUM_OF_PERIPHERAL_CLOCKS_0 11
+#include <arch/board/board.h>
-/****************************************************************************
- * Public Types
- ****************************************************************************/
+#ifdef CONFIG_ARCH_LEDS
/****************************************************************************
- * Public data
+ * Pre-processor Definitions
****************************************************************************/
-#ifndef __ASSEMBLY__
+/* Summary of all possible settings */
-/* User peripheral configuration structure 0 */
-
-extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[];
+#define LED_NOCHANGE 0 /* LED_IRQSENABLED, LED_INIRQ, LED_SIGNAL, LED_ASSERTION */
+#define LED_OFF_OFF_OFF 1 /* LED_STARTED */
+#define LED_OFF_OFF_ON 2 /* LED_HEAPALLOCATE */
+#define LED_OFF_ON_OFF 3 /* LED_STACKCREATED */
+#define LED_ON_OFF_OFF 4 /* LED_PANIC */
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
- * Name: s32k146_bringup
- *
- * Description:
- * Perform architecture-specific initialization
- *
- * CONFIG_BOARD_LATE_INITIALIZE=y :
- * Called from board_late_initialize().
- *
- * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y :
- * Called from the NSH library
- *
+ * Name: board_autoled_initialize
****************************************************************************/
-int s32k146_bringup(void);
+void board_autoled_initialize(void)
+{
+ /* Configure LED GPIOs for output */
+
+ s32k1xx_pinconfig(GPIO_LED_R);
+ s32k1xx_pinconfig(GPIO_LED_G);
+ s32k1xx_pinconfig(GPIO_LED_B);
+}
/****************************************************************************
- * Name: s32k146_spidev_initialize
- *
- * Description:
- * Called to configure SPI chip select GPIO pins for the s32k146evb
- * board.
- *
+ * Name: board_autoled_on
****************************************************************************/
-#ifdef CONFIG_S32K1XX_SPI
-void s32k146_spidev_initialize(void);
-#endif
+void board_autoled_on(int led)
+{
+ if (led != LED_NOCHANGE)
+ {
+ bool redon = false;
+ bool greenon = false;
+ bool blueon = false;
+
+ switch (led)
+ {
+ default:
+ case LED_OFF_OFF_OFF:
+ break;
+
+ case LED_OFF_OFF_ON:
+ blueon = true;
+ break;
+
+ case LED_OFF_ON_OFF:
+ greenon = true;
+ break;
+
+ case LED_ON_OFF_OFF:
+ redon = true;
+ break;
+ }
+
+ s32k1xx_gpiowrite(GPIO_LED_R, redon);
+ s32k1xx_gpiowrite(GPIO_LED_G, greenon);
+ s32k1xx_gpiowrite(GPIO_LED_B, blueon);
+ }
+}
+
+/****************************************************************************
+ * Name: board_autoled_off
+ ****************************************************************************/
-#endif /* __ASSEMBLY__ */
-#endif /* __BOARDS_ARM_S32K1XX_S32K146EVB_SRC_S32K146EVB_H */
+void board_autoled_off(int led)
+{
+ if (led == LED_ON_OFF_OFF)
+ {
+ s32k1xx_gpiowrite(GPIO_LED_R, true);
+ s32k1xx_gpiowrite(GPIO_LED_G, false);
+ s32k1xx_gpiowrite(GPIO_LED_B, false);
+ }
+}
+
+#endif /* CONFIG_ARCH_LEDS */
diff --git a/arch/arm/src/s32k1xx/chip.h b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_boot.c
similarity index 62%
copy from arch/arm/src/s32k1xx/chip.h
copy to boards/arm/s32k1xx/s32k144evb/src/s32k1xx_boot.c
index f3f9b9c..9cfb0cf 100644
--- a/arch/arm/src/s32k1xx/chip.h
+++ b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_boot.c
@@ -1,5 +1,5 @@
-/************************************************************************************
- * arch/arm/src/s32k1xx/chip.h
+/****************************************************************************
+ * boards/arm/s32k1xx/s32k144evb/src/s32k1xx_boot.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -31,47 +31,63 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ************************************************************************************/
+ ****************************************************************************/
-#ifndef __ARCH_ARM_SRC_S32K1XX_CHIP_H
-#define __ARCH_ARM_SRC_S32K1XX_CHIP_H
-
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
-/* Include the memory map and the chip definitions file. Other chip hardware files
- * should then include this file for the proper setup.
- */
+#include <debug.h>
+
+#include <nuttx/board.h>
-#include <arch/irq.h>
-#include "hardware/s32k1xx_memorymap.h"
+#include "s32k144evb.h"
-/* The common ARMv6/7-M vector handling logic expects the following definitions in
- * this file. ARMV6/7M_PERIPHERAL_INTERRUPTS provides the number of supported
- * external interrupts which, for this architecture, is provided in the
- * arch/s32k1xx/irq.h header file.
- */
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
-#define ARMV6M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT
-#define ARMV7M_PERIPHERAL_INTERRUPTS S32K1XX_IRQ_NEXTINT
+/****************************************************************************
+ * Name: s32k1xx_board_initialize
+ *
+ * Description:
+ * All S32K1XX architectures must provide the following entry point. This
+ * entry point is called early in the initialization -- after all memory
+ * has been configured and mapped but before any devices have been
+ * initialized.
+ *
+ ****************************************************************************/
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
+void s32k1xx_board_initialize(void)
+{
+#ifdef CONFIG_ARCH_LEDS
+ /* Configure on-board LEDs if LED support has been selected. */
-/************************************************************************************
- * Public Types
- ************************************************************************************/
+ board_autoled_initialize();
+#endif
+}
-/************************************************************************************
- * Public Data
- ************************************************************************************/
+/****************************************************************************
+ * Name: board_late_initialize
+ *
+ * Description:
+ * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
+ * initialization call will be performed in the boot-up sequence to a
+ * function called board_late_initialize(). board_late_initialize() will
+ * be called immediately after up_initialize() is called and just before
+ * the initial application is started. This additional initialization
+ * phase may be used, for example, to initialize board-specific device
+ * drivers.
+ *
+ ****************************************************************************/
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
+#ifdef CONFIG_BOARD_LATE_INITIALIZE
+void board_late_initialize(void)
+{
+ /* Perform board-specific initialization */
-#endif /* __ARCH_ARM_SRC_S32K1XX_CHIP_H */
+ s32k1xx_bringup();
+}
+#endif
diff --git a/boards/arm/s32k1xx/s32k148evb/src/s32k148evb.h b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_bringup.c
similarity index 51%
copy from boards/arm/s32k1xx/s32k148evb/src/s32k148evb.h
copy to boards/arm/s32k1xx/s32k144evb/src/s32k1xx_bringup.c
index ba85f50..607b3d4 100644
--- a/boards/arm/s32k1xx/s32k148evb/src/s32k148evb.h
+++ b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_bringup.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/arm/s32k1xx/s32k148evb/src/s32k148evb.h
+ * boards/arm/s32k1xx/s32k144evb/src/s32k1xx_bringup.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -33,78 +33,37 @@
*
****************************************************************************/
-#ifndef __BOARDS_ARM_S32K1XX_S32K148EVB_SRC_S32K148EVB_H
-#define __BOARDS_ARM_S32K1XX_S32K148EVB_SRC_S32K148EVB_H
-
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
-#include <nuttx/compiler.h>
-
-#include <stdint.h>
-
-#include "hardware/s32k1xx_pinmux.h"
-#include "s32k1xx_periphclocks.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/* Configuration ************************************************************/
-
-/* S32K148EVB GPIOs *********************************************************/
-
-/* LEDs. The S32K148EVB has one RGB LED:
- *
- * RedLED PTE21
- * GreenLED PTE22
- * BlueLED PTE23
- *
- * An output of '1' illuminates the LED.
- */
-#define GPIO_LED_R (PIN_PTE21 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
-#define GPIO_LED_G (PIN_PTE22 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
-#define GPIO_LED_B (PIN_PTE23 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
-
-/* Buttons. The S32K148EVB supports two buttons:
- *
- * SW3 PTC12
- * SW4 PTC13
- */
-
-#define GPIO_SW3 (PIN_PTC12 | PIN_INT_BOTH)
-#define GPIO_SW4 (PIN_PTC13 | PIN_INT_BOTH)
-
-/* SPI chip selects */
-
-
-/* Count of peripheral clock user configurations */
-
-#define NUM_OF_PERIPHERAL_CLOCKS_0 11
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
+#include <sys/types.h>
+#include <sys/mount.h>
+#include <syslog.h>
-/****************************************************************************
- * Public data
- ****************************************************************************/
+#ifdef CONFIG_BUTTONS
+# include <nuttx/input/buttons.h>
+#endif
-#ifndef __ASSEMBLY__
+#ifdef CONFIG_USERLED
+# include <nuttx/leds/userled.h>
+#endif
-/* User peripheral configuration structure 0 */
+#ifdef CONFIG_I2C_DRIVER
+# include <nuttx/i2c/i2c_master.h>
+# include "s32k1xx_lpi2c.h"
+#endif
-extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[];
+#include "s32k144evb.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
- * Name: s32k148_bringup
+ * Name: s32k1xx_bringup
*
* Description:
* Perform architecture-specific initialization
@@ -112,25 +71,71 @@ extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[];
* CONFIG_BOARD_LATE_INITIALIZE=y :
* Called from board_late_initialize().
*
- * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y :
+ * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y :
* Called from the NSH library
*
****************************************************************************/
-int s32k148_bringup(void);
+int s32k1xx_bringup(void)
+{
+ int ret = OK;
-/****************************************************************************
- * Name: s32k148_spidev_initialize
- *
- * Description:
- * Called to configure SPI chip select GPIO pins for the s32k148evb
- * board.
- *
- ****************************************************************************/
+#ifdef CONFIG_BUTTONS
+ /* Register the BUTTON driver */
+
+ ret = btn_lower_initialize("/dev/buttons");
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret);
+ }
+#endif
+
+#ifdef CONFIG_USERLED
+ /* Register the LED driver */
+
+ ret = userled_lower_initialize("/dev/userleds");
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret);
+ }
+#endif
+
+#ifdef CONFIG_FS_PROCFS
+ /* Mount the procfs file system */
+
+ ret = mount(NULL, "/proc", "procfs", 0, NULL);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret);
+ }
+#endif
+
+#ifdef CONFIG_S32K1XX_LPSPI
+ /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak
+ * function s32k1xx_spidev_initialize() has been brought into the link.
+ */
+
+ s32k1xx_spidev_initialize();
+#endif
-#ifdef CONFIG_S32K1XX_SPI
-void s32k148_spidev_initialize(void);
+#if defined(CONFIG_S32K1XX_LPI2C0) && defined(CONFIG_I2C_DRIVER)
+ FAR struct i2c_master_s *i2c;
+
+ i2c = s32k1xx_i2cbus_initialize(0);
+ if (i2c == NULL)
+ {
+ serr("ERROR: Failed to get I2C%d interface\n", bus);
+ }
+ else
+ {
+ ret = i2c_register(i2c, 0);
+ if (ret < 0)
+ {
+ serr("ERROR: Failed to register I2C%d driver: %d\n", bus, ret);
+ s32k1xx_i2cbus_uninitialize(i2c);
+ }
+ }
#endif
-#endif /* __ASSEMBLY__ */
-#endif /* __BOARDS_ARM_S32K1XX_S32K148EVB_SRC_S32K148EVB_H */
+ return ret;
+}
diff --git a/boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_buttons.c
similarity index 51%
copy from boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h
copy to boards/arm/s32k1xx/s32k144evb/src/s32k1xx_buttons.c
index 13cfc0c..d6c84d4 100644
--- a/boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h
+++ b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_buttons.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * boards/arm/s32k1xx/s32k146evb/src/s32k146evb.h
+ * boards/arm/s32k1xx/s32k144evb/src/s32k1xx_buttons.c
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gn...@nuttx.org>
@@ -33,104 +33,133 @@
*
****************************************************************************/
-#ifndef __BOARDS_ARM_S32K1XX_S32K146EVB_SRC_S32K146EVB_H
-#define __BOARDS_ARM_S32K1XX_S32K146EVB_SRC_S32K146EVB_H
+/* The S32K144EVB supports two buttons:
+ *
+ * SW2 PTC12
+ * SW3 PTC13
+ */
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
-#include <nuttx/compiler.h>
#include <stdint.h>
+#include <errno.h>
-#include "hardware/s32k1xx_pinmux.h"
-#include "s32k1xx_periphclocks.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
-/* Configuration ************************************************************/
+#include "s32k1xx_pin.h"
+#include "s32k144evb.h"
-/* S32K146EVB GPIOs *********************************************************/
+#include <arch/board/board.h>
-/* LEDs. The S32K146EVB has one RGB LED:
- *
- * RedLED PTD15 (FTM0 CH0)
- * GreenLED PTD16 (FTM0 CH1)
- * BlueLED PTD0 (FTM0 CH2)
- *
- * An output of '1' illuminates the LED.
- */
+#ifdef CONFIG_ARCH_BUTTONS
-#define GPIO_LED_R (PIN_PTD15 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
-#define GPIO_LED_G (PIN_PTD16 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
-#define GPIO_LED_B (PIN_PTE8 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
-/* Buttons. The S32K146EVB supports two buttons:
+/****************************************************************************
+ * Name: board_button_initialize
*
- * SW2 PTC12
- * SW3 PTC13
- */
-
-#define GPIO_SW2 (PIN_PTC12 | PIN_INT_BOTH)
-#define GPIO_SW3 (PIN_PTC13 | PIN_INT_BOTH)
-
-/* SPI chip selects */
-
+ * Description:
+ * board_button_initialize() must be called to initialize button resources.
+ * After that, board_buttons() may be called to collect the current state
+ * of all buttons or board_button_irq() may be called to register button
+ * interrupt handlers.
+ *
+ ****************************************************************************/
-/* Count of peripheral clock user configurations */
+void board_button_initialize(void)
+{
+ /* Configure the GPIO pins as interrupting inputs. */
-#define NUM_OF_PERIPHERAL_CLOCKS_0 11
+ s32k1xx_pinconfig(GPIO_SW2);
+ s32k1xx_pinconfig(GPIO_SW3);
+}
/****************************************************************************
- * Public Types
+ * Name: board_buttons
****************************************************************************/
-/****************************************************************************
- * Public data
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
+uint32_t board_buttons(void)
+{
+ uint32_t ret = 0;
-/* User peripheral configuration structure 0 */
+ if (s32k1xx_gpioread(GPIO_SW2))
+ {
+ ret |= BUTTON_SW2_BIT;
+ }
-extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[];
+ if (s32k1xx_gpioread(GPIO_SW3))
+ {
+ ret |= BUTTON_SW3_BIT;
+ }
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
+ return ret;
+}
/****************************************************************************
- * Name: s32k146_bringup
+ * Button support.
*
* Description:
- * Perform architecture-specific initialization
+ * board_button_initialize() must be called to initialize button resources.
+ * After that, board_buttons() may be called to collect the current state
+ * of all buttons or board_button_irq() may be called to register button
+ * interrupt handlers.
*
- * CONFIG_BOARD_LATE_INITIALIZE=y :
- * Called from board_late_initialize().
+ * After board_button_initialize() has been called, board_buttons() may be
+ * called to collect the state of all buttons. board_buttons() returns a
+ * 32-bit bit set with each bit associated with a button. See the
+ * BUTTON_*_BIT definitions in board.h for the meaning of each bit.
*
- * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y :
- * Called from the NSH library
+ * board_button_irq() may be called to register an interrupt handler that
+ * will be called when a button is depressed or released. The ID value is
+ * a button enumeration value that uniquely identifies a button resource.
+ * See the BUTTON_* definitions in board.h for the meaning of enumeration
+ * value.
*
****************************************************************************/
-int s32k146_bringup(void);
-
-/****************************************************************************
- * Name: s32k146_spidev_initialize
- *
- * Description:
- * Called to configure SPI chip select GPIO pins for the s32k146evb
- * board.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_S32K1XX_SPI
-void s32k146_spidev_initialize(void);
+#ifdef CONFIG_ARCH_IRQBUTTONS
+int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg)
+{
+ uint32_t pinset;
+ int ret;
+
+ /* Map the button id to the GPIO bit set. */
+
+ if (id == BUTTON_SW2)
+ {
+ pinset = GPIO_SW2;
+ }
+ else if (id == BUTTON_SW3)
+ {
+ pinset = GPIO_SW3;
+ }
+ else
+ {
+ return -EINVAL;
+ }
+
+ /* The button has already been configured as an interrupting input (by
+ * board_button_initialize() above).
+ *
+ * Attach the new button handler.
+ */
+
+ ret = s32k1xx_pinirqattach(pinset, irqhandler, NULL);
+ if (ret >= 0)
+ {
+ /* Then make sure that interrupts are enabled on the pin */
+
+ s32k1xx_pinirqenable(pinset);
+ }
+
+ return ret;
+}
#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __BOARDS_ARM_S32K1XX_S32K146EVB_SRC_S32K146EVB_H */
+#endif /* CONFIG_ARCH_BUTTONS */
diff --git a/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_clockconfig.c b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_clockconfig.c
new file mode 100644
index 0000000..1585765
--- /dev/null
+++ b/boards/arm/s32k1xx/s32k144evb/src/s32k1xx_clockconfig.c
@@ -0,0 +1,227 @@
+/****************************************************************************
+ * boards/arm/s32k1xx/s32k144evb/src/s32k1xx_clockconfig.c
+ *
+ * Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Most of the settings within this file derives from NXP sample code for
+ * the S32K1XX MCUs. That sample code has this licensing information:
+ *
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "s32k1xx_clockconfig.h"
+#include "s32k1xx_start.h"
+#include "s32k144evb.h"
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* Each S32K1XX board must provide the following initialized structure.
+ * This is needed to establish the initial board clocking.
+ */
+
+const struct clock_configuration_s g_initial_clkconfig =
+{
+ .scg =
+ {
+ .sirc =
+ {
+ .range = SCG_SIRC_RANGE_HIGH, /* RANGE - High range (8 MHz) */
+ .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV1 */
+ .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SIRCDIV2 */
+ .initialize = true, /* Initialize */
+ .stopmode = true, /* SIRCSTEN */
+ .lowpower = true, /* SIRCLPEN */
+ .locked = false, /* LK */
+ },
+ .firc =
+ {
+ .range = SCG_FIRC_RANGE_48M, /* RANGE */
+ .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV1 */
+ .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* FIRCDIV2 */
+ .initialize = true, /* Initialize */
+ .stopmode = false, /* */
+ .lowpower = false, /* */
+ .regulator = true, /* FIRCREGOFF */
+ .locked = false, /* LK */
+ },
+ .sosc =
+ {
+ .mode = SCG_SOSC_MONITOR_DISABLE, /* SOSCCM */
+ .gain = SCG_SOSC_GAIN_LOW, /* HGO */
+ .range = SCG_SOSC_RANGE_MID, /* RANGE */
+ .extref = SCG_SOSC_REF_OSC, /* EREFS */
+ .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV1 */
+ .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SOSCDIV2 */
+ .initialize = true, /* Initialize */
+ .stopmode = false, /* */
+ .lowpower = false, /* */
+ .locked = false, /* LK */
+ },
+ .spll =
+ {
+ .mode = SCG_SPLL_MONITOR_DISABLE, /* SPLLCM */
+ .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV1 */
+ .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV2 */
+ .prediv = 1, /* PREDIV */
+ .mult = 40, /* MULT */
+ .src = 0, /* SOURCE */
+ .initialize = true, /* Initialize */
+ .stopmode = false, /* */
+ .locked = false, /* LK */
... 4125 lines suppressed ...