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Posted to commits@tvm.apache.org by tq...@apache.org on 2026/06/22 03:15:01 UTC
(tvm-site) branch asf-site updated: deploying docs (apache/tvm@15f62fe0209c1d24723b083ff53d0c1ae206db93)
This is an automated email from the ASF dual-hosted git repository.
tqchen pushed a commit to branch asf-site
in repository https://gitbox.apache.org/repos/asf/tvm-site.git
The following commit(s) were added to refs/heads/asf-site by this push:
new b5fe930e712 deploying docs (apache/tvm@15f62fe0209c1d24723b083ff53d0c1ae206db93)
b5fe930e712 is described below
commit b5fe930e712c56afcbc9d1cc0ea693eaa644c450
Author: tvm-bot <95...@users.noreply.github.com>
AuthorDate: Mon Jun 22 03:14:52 2026 +0000
deploying docs (apache/tvm@15f62fe0209c1d24723b083ff53d0c1ae206db93)
---
.../import_model.zip | Bin 35138 -> 35138 bytes
.../dlight_gpu_scheduling.zip | Bin 26311 -> 26311 bytes
.../11c11e53c7dace51a8be968ee169ed0d/ir_module.zip | Bin 23790 -> 23790 bytes
.../tir_transformation.zip | Bin 15923 -> 15923 bytes
.../meta_schedule.zip | Bin 24239 -> 24239 bytes
.../mix_python_and_tvm_with_pymodule.zip | Bin 38907 -> 38907 bytes
.../relax_creation.zip | Bin 22467 -> 22467 bytes
.../relax_transformation.zip | Bin 11480 -> 11480 bytes
.../optimize_llm.zip | Bin 54007 -> 54007 bytes
.../bring_your_own_codegen.zip | Bin 36685 -> 36685 bytes
.../e2e_opt_model.zip | Bin 14501 -> 14501 bytes
.../quick_start.zip | Bin 16252 -> 16252 bytes
.../export_and_load_executable.zip | Bin 31408 -> 31408 bytes
.../tir_creation.zip | Bin 24580 -> 24580 bytes
.../cross_compilation_and_rpc.zip | Bin 62975 -> 62975 bytes
.../customize_opt.zip | Bin 20544 -> 20544 bytes
.../relax/tutorials/sg_execution_times.rst.txt | 6 +-
.../tensor_ir/tutorials/sg_execution_times.rst.txt | 4 +-
.../tensor_ir/tutorials/tir_transformation.rst.txt | 6 +-
.../get_started/tutorials/ir_module.rst.txt | 8 +-
.../get_started/tutorials/quick_start.rst.txt | 4 +-
.../tutorials/sg_execution_times.rst.txt | 6 +-
.../tutorials/cross_compilation_and_rpc.rst.txt | 6 +-
.../how_to/tutorials/e2e_opt_model.rst.txt | 2 +-
.../how_to/tutorials/sg_execution_times.rst.txt | 10 +-
docs/_sources/index.rst.txt | 12 +
docs/_sources/reference/api/python/index.rst.txt | 10 -
docs/_sources/sg_execution_times.rst.txt | 20 +-
.../api/python/tirx => tirx/api}/analysis.rst.txt | 0
docs/_sources/tirx/api/backend.rst.txt | 66 +
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.../python/tirx => tirx/api}/stmt_functor.rst.txt | 0
.../api/python/tirx => tirx/api}/tirx.rst.txt | 2 +-
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docs/_sources/tirx/arch/lowering_pipeline.rst.txt | 203 ++
docs/_sources/tirx/install.rst.txt | 100 +
docs/_sources/tirx/layout.rst.txt | 383 +++
docs/_sources/tirx/native_basics.rst.txt | 69 +
.../tirx/native_basics/cuda/buffers.rst.txt | 477 +++
.../tirx/native_basics/cuda/compiling.rst.txt | 112 +
.../tirx/native_basics/cuda/control_flow.rst.txt | 100 +
.../tirx/native_basics/cuda/data_types.rst.txt | 116 +
.../tirx/native_basics/cuda/first_kernel.rst.txt | 93 +
.../tirx/native_basics/cuda/functions.rst.txt | 351 ++
.../tirx/native_basics/cuda/parser_utils.rst.txt | 80 +
.../tirx/native_basics/cuda/threads_sync.rst.txt | 95 +
docs/_sources/tirx/overview.rst.txt | 196 ++
docs/_sources/tirx/tile_primitives.rst.txt | 297 ++
docs/_sources/tirx/tile_primitives/copy.rst.txt | 57 +
.../tirx/tile_primitives/copy/fallback.rst.txt | 158 +
.../tirx/tile_primitives/copy/gmem_smem.rst.txt | 209 ++
.../tirx/tile_primitives/copy/ldstmatrix.rst.txt | 218 ++
.../_sources/tirx/tile_primitives/copy/reg.rst.txt | 206 ++
.../tirx/tile_primitives/copy_async.rst.txt | 63 +
.../tirx/tile_primitives/copy_async/dsmem.rst.txt | 190 ++
.../tirx/tile_primitives/copy_async/ldgsts.rst.txt | 176 +
.../tile_primitives/copy_async/tcgen05_cp.rst.txt | 183 ++
.../copy_async/tcgen05_ldst.rst.txt | 172 +
.../tirx/tile_primitives/copy_async/tma.rst.txt | 200 ++
.../tirx/tile_primitives/elementwise.rst.txt | 48 +
.../tirx/tile_primitives/elementwise/reg.rst.txt | 133 +
.../tirx/tile_primitives/elementwise/smem.rst.txt | 136 +
docs/_sources/tirx/tile_primitives/gemm.rst.txt | 176 +
.../tirx/tile_primitives/gemm_async.rst.txt | 175 +
.../tirx/tile_primitives/permute_layout.rst.txt | 163 +
.../tirx/tile_primitives/reduction.rst.txt | 48 +
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.../tile_primitives/reduction/sm100_packed.rst.txt | 147 +
docs/_static/downloads/tirx_agentic.webp | Bin 0 -> 178394 bytes
docs/_static/downloads/tirx_megakernel.png | Bin 0 -> 412399 bytes
docs/_static/downloads/tirx_overview_hero.png | Bin 0 -> 475914 bytes
docs/arch/codegen.html | 10 +
docs/arch/device_target_interactions.html | 10 +
docs/arch/external_library_dispatch.html | 10 +
docs/arch/fusion.html | 10 +
docs/arch/index.html | 10 +
.../arch/introduction_to_module_serialization.html | 10 +
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docs/arch/relax_vm.html | 10 +
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docs/genindex.html | 1547 +++++----
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docs/how_to/tutorials/bring_your_own_codegen.html | 10 +
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docs/how_to/tutorials/customize_opt.html | 10 +
docs/how_to/tutorials/e2e_opt_model.html | 14 +-
.../tutorials/export_and_load_executable.html | 10 +
docs/how_to/tutorials/import_model.html | 10 +
docs/how_to/tutorials/index.html | 10 +
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docs/index.html | 62 +
docs/install/docker.html | 10 +
docs/install/from_source.html | 10 +
docs/install/index.html | 10 +
docs/objects.inv | Bin 23343 -> 25139 bytes
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docs/reference/api/python/meta_schedule.html | 31 +-
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docs/reference/api/python/relax/backend.html | 15 +-
docs/reference/api/python/relax/block_builder.html | 19 +-
docs/reference/api/python/relax/distributed.html | 15 +-
docs/reference/api/python/relax/dpl.html | 19 +-
docs/reference/api/python/relax/frontend.html | 25 +-
docs/reference/api/python/relax/op.html | 25 +-
docs/reference/api/python/relax/relax.html | 19 +-
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docs/reference/api/python/relax/transform.html | 29 +-
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docs/reference/api/python/s_tir/dlight.html | 117 +-
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docs/reference/api/python/script/ir_builder.html | 15 +-
docs/reference/api/python/script/parser.html | 15 +-
docs/reference/api/python/script/printer.html | 15 +-
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300 files changed, 29606 insertions(+), 3415 deletions(-)
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index 9214fe4a66d..288af24211f 100644
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diff --git a/docs/_downloads/f69433a4a80715725df90d1386679956/customize_opt.zip b/docs/_downloads/f69433a4a80715725df90d1386679956/customize_opt.zip
index 194f3018447..e5d00dddd60 100644
Binary files a/docs/_downloads/f69433a4a80715725df90d1386679956/customize_opt.zip and b/docs/_downloads/f69433a4a80715725df90d1386679956/customize_opt.zip differ
diff --git a/docs/_sources/deep_dive/relax/tutorials/sg_execution_times.rst.txt b/docs/_sources/deep_dive/relax/tutorials/sg_execution_times.rst.txt
index 43263c02034..ea03892e711 100644
--- a/docs/_sources/deep_dive/relax/tutorials/sg_execution_times.rst.txt
+++ b/docs/_sources/deep_dive/relax/tutorials/sg_execution_times.rst.txt
@@ -6,7 +6,7 @@
Computation times
=================
-**00:00.278** total execution time for 2 files **from deep_dive/relax/tutorials**:
+**00:00.276** total execution time for 2 files **from deep_dive/relax/tutorials**:
.. container::
@@ -33,8 +33,8 @@ Computation times
- Time
- Mem (MB)
* - :ref:`sphx_glr_deep_dive_relax_tutorials_relax_creation.py` (``relax_creation.py``)
- - 00:00.209
+ - 00:00.208
- 0.0
* - :ref:`sphx_glr_deep_dive_relax_tutorials_relax_transformation.py` (``relax_transformation.py``)
- - 00:00.069
+ - 00:00.068
- 0.0
diff --git a/docs/_sources/deep_dive/tensor_ir/tutorials/sg_execution_times.rst.txt b/docs/_sources/deep_dive/tensor_ir/tutorials/sg_execution_times.rst.txt
index 09686b495db..317ad8b8e12 100644
--- a/docs/_sources/deep_dive/tensor_ir/tutorials/sg_execution_times.rst.txt
+++ b/docs/_sources/deep_dive/tensor_ir/tutorials/sg_execution_times.rst.txt
@@ -6,7 +6,7 @@
Computation times
=================
-**00:00.894** total execution time for 4 files **from deep_dive/tensor_ir/tutorials**:
+**00:00.895** total execution time for 4 files **from deep_dive/tensor_ir/tutorials**:
.. container::
@@ -33,7 +33,7 @@ Computation times
- Time
- Mem (MB)
* - :ref:`sphx_glr_deep_dive_tensor_ir_tutorials_tir_creation.py` (``tir_creation.py``)
- - 00:00.380
+ - 00:00.383
- 0.0
* - :ref:`sphx_glr_deep_dive_tensor_ir_tutorials_tir_transformation.py` (``tir_transformation.py``)
- 00:00.354
diff --git a/docs/_sources/deep_dive/tensor_ir/tutorials/tir_transformation.rst.txt b/docs/_sources/deep_dive/tensor_ir/tutorials/tir_transformation.rst.txt
index 49e9a2f9558..062eb0e0f81 100644
--- a/docs/_sources/deep_dive/tensor_ir/tutorials/tir_transformation.rst.txt
+++ b/docs/_sources/deep_dive/tensor_ir/tutorials/tir_transformation.rst.txt
@@ -120,7 +120,7 @@ original implementation.
Execution time summary:
mean (ms) median (ms) max (ms) min (ms) std (ms)
- 2.8418 2.8418 2.8418 2.8418 0.0000
+ 2.7688 2.7688 2.7688 2.7688 0.0000
@@ -294,7 +294,7 @@ action involves reordering these two loops.
Execution time summary:
mean (ms) median (ms) max (ms) min (ms) std (ms)
- 0.8630 0.8630 0.8630 0.8630 0.0000
+ 0.8701 0.8701 0.8701 0.8701 0.0000
@@ -424,7 +424,7 @@ from the reduction update via the **decompose_reduction** primitive.
Execution time summary:
mean (ms) median (ms) max (ms) min (ms) std (ms)
- 0.3552 0.3552 0.3552 0.3552 0.0000
+ 0.3396 0.3396 0.3396 0.3396 0.0000
diff --git a/docs/_sources/get_started/tutorials/ir_module.rst.txt b/docs/_sources/get_started/tutorials/ir_module.rst.txt
index e853eb23ae0..76a97d0688c 100644
--- a/docs/_sources/get_started/tutorials/ir_module.rst.txt
+++ b/docs/_sources/get_started/tutorials/ir_module.rst.txt
@@ -696,8 +696,8 @@ We can deploy the IRModule on CPU by specifying the target as ``llvm``.
.. code-block:: none
- [[-0.01538962 0.3851107 0.03527965 0.13098207 -0.16662857 0.00333789
- -0.09144688 -0.0468705 0.06863248 0.2076945 ]]
+ [[-0.0547377 0.18783814 -0.04199328 -0.10805021 -0.03187234 0.19495451
+ 0.32176793 -0.14547694 0.02930979 0.00290294]]
@@ -763,8 +763,8 @@ Now we can compile the IRModule on GPU, the similar way as we did on CPU.
.. code-block:: none
- [[-0.01538961 0.38511077 0.03527965 0.1309821 -0.16662858 0.00333788
- -0.09144685 -0.04687053 0.06863243 0.2076945 ]]
+ [[-0.05473768 0.18783814 -0.04199325 -0.1080502 -0.03187232 0.1949545
+ 0.32176787 -0.14547694 0.02930982 0.00290294]]
diff --git a/docs/_sources/get_started/tutorials/quick_start.rst.txt b/docs/_sources/get_started/tutorials/quick_start.rst.txt
index 16c181d8628..6c39979b3b9 100644
--- a/docs/_sources/get_started/tutorials/quick_start.rst.txt
+++ b/docs/_sources/get_started/tutorials/quick_start.rst.txt
@@ -224,8 +224,8 @@ different devices.
.. code-block:: none
- [[24258.678 25923.42 25322.111 25038.97 23786.627 25547.55 24201.13
- 23894.576 25921.795 25842.598]]
+ [[25158.338 25288.748 25020.79 24822.875 25300.049 25050.55 24957.877
+ 24836.717 24695.543 25300.342]]
diff --git a/docs/_sources/get_started/tutorials/sg_execution_times.rst.txt b/docs/_sources/get_started/tutorials/sg_execution_times.rst.txt
index 1017d0d7f8c..223de77b755 100644
--- a/docs/_sources/get_started/tutorials/sg_execution_times.rst.txt
+++ b/docs/_sources/get_started/tutorials/sg_execution_times.rst.txt
@@ -6,7 +6,7 @@
Computation times
=================
-**00:05.939** total execution time for 2 files **from get_started/tutorials**:
+**00:05.922** total execution time for 2 files **from get_started/tutorials**:
.. container::
@@ -33,8 +33,8 @@ Computation times
- Time
- Mem (MB)
* - :ref:`sphx_glr_get_started_tutorials_ir_module.py` (``ir_module.py``)
- - 00:05.757
+ - 00:05.742
- 0.0
* - :ref:`sphx_glr_get_started_tutorials_quick_start.py` (``quick_start.py``)
- - 00:00.182
+ - 00:00.180
- 0.0
diff --git a/docs/_sources/how_to/tutorials/cross_compilation_and_rpc.rst.txt b/docs/_sources/how_to/tutorials/cross_compilation_and_rpc.rst.txt
index b0df56bc6cb..572599a8597 100644
--- a/docs/_sources/how_to/tutorials/cross_compilation_and_rpc.rst.txt
+++ b/docs/_sources/how_to/tutorials/cross_compilation_and_rpc.rst.txt
@@ -267,7 +267,7 @@ device and returns the measured cost. Network overhead is excluded.
.. code-block:: none
- 1.06e-07 secs/op
+ 1.09e-07 secs/op
@@ -857,8 +857,8 @@ This workflow is applicable to various deployment scenarios:
Converted PyTorch model to Relax:
- Number of parameters: 4
Using local target for demonstration
- Exported library to: /tmp/tmp4t1gpk2w/model_deployed.so
- Saved parameters to: /tmp/tmp4t1gpk2w/model_params.npz
+ Exported library to: /tmp/tmp61m_clkt/model_deployed.so
+ Saved parameters to: /tmp/tmp61m_clkt/model_params.npz
RPC workflow (works for any remote device):
==================================================
diff --git a/docs/_sources/how_to/tutorials/e2e_opt_model.rst.txt b/docs/_sources/how_to/tutorials/e2e_opt_model.rst.txt
index fc659ade8f2..d69db88a9a1 100644
--- a/docs/_sources/how_to/tutorials/e2e_opt_model.rst.txt
+++ b/docs/_sources/how_to/tutorials/e2e_opt_model.rst.txt
@@ -54,7 +54,7 @@ PyTorch.
.. code-block:: none
Downloading: "https://download.pytorch.org/models/resnet18-f37072fd.pth" to /workspace/.cache/torch/hub/checkpoints/resnet18-f37072fd.pth
- 0%| | 0.00/44.7M [00:00<?, ?B/s] 67%|██████▋ | 30.1M/44.7M [00:00<00:00, 315MB/s] 100%|██████████| 44.7M/44.7M [00:00<00:00, 342MB/s]
+ 0%| | 0.00/44.7M [00:00<?, ?B/s] 64%|██████▍ | 28.6M/44.7M [00:00<00:00, 300MB/s] 100%|██████████| 44.7M/44.7M [00:00<00:00, 330MB/s]
diff --git a/docs/_sources/how_to/tutorials/sg_execution_times.rst.txt b/docs/_sources/how_to/tutorials/sg_execution_times.rst.txt
index e2748c42324..5ee293a4665 100644
--- a/docs/_sources/how_to/tutorials/sg_execution_times.rst.txt
+++ b/docs/_sources/how_to/tutorials/sg_execution_times.rst.txt
@@ -6,7 +6,7 @@
Computation times
=================
-**00:16.688** total execution time for 8 files **from how_to/tutorials**:
+**00:16.660** total execution time for 8 files **from how_to/tutorials**:
.. container::
@@ -33,16 +33,16 @@ Computation times
- Time
- Mem (MB)
* - :ref:`sphx_glr_how_to_tutorials_optimize_llm.py` (``optimize_llm.py``)
- - 00:11.414
+ - 00:11.421
- 0.0
* - :ref:`sphx_glr_how_to_tutorials_import_model.py` (``import_model.py``)
- - 00:03.645
+ - 00:03.628
- 0.0
* - :ref:`sphx_glr_how_to_tutorials_e2e_opt_model.py` (``e2e_opt_model.py``)
- - 00:00.688
+ - 00:00.672
- 0.0
* - :ref:`sphx_glr_how_to_tutorials_cross_compilation_and_rpc.py` (``cross_compilation_and_rpc.py``)
- - 00:00.562
+ - 00:00.561
- 0.0
* - :ref:`sphx_glr_how_to_tutorials_customize_opt.py` (``customize_opt.py``)
- 00:00.331
diff --git a/docs/_sources/index.rst.txt b/docs/_sources/index.rst.txt
index 87af6cc267c..f8a730fc979 100644
--- a/docs/_sources/index.rst.txt
+++ b/docs/_sources/index.rst.txt
@@ -62,6 +62,18 @@ driving its costs down.
deep_dive/tensor_ir/index
deep_dive/relax/index
+.. toctree::
+ :maxdepth: 2
+ :caption: TIRx
+
+ tirx/overview
+ tirx/install
+ tirx/native_basics
+ tirx/layout
+ tirx/tile_primitives
+ tirx/arch/index
+ tirx/api/index
+
.. toctree::
:maxdepth: 1
:caption: API Reference
diff --git a/docs/_sources/reference/api/python/index.rst.txt b/docs/_sources/reference/api/python/index.rst.txt
index 4bef65f82df..6fba876950e 100644
--- a/docs/_sources/reference/api/python/index.rst.txt
+++ b/docs/_sources/reference/api/python/index.rst.txt
@@ -57,16 +57,6 @@ Python API
relax/transform
relax/dpl
-.. toctree::
- :maxdepth: 1
- :caption: tvm.tirx
-
- tirx/tirx
- tirx/analysis
- tirx/stmt_functor
- tirx/transform
- tirx/backend
-
.. toctree::
:maxdepth: 1
:caption: tvm.s_tir
diff --git a/docs/_sources/sg_execution_times.rst.txt b/docs/_sources/sg_execution_times.rst.txt
index 7029858016b..eee17fe0edd 100644
--- a/docs/_sources/sg_execution_times.rst.txt
+++ b/docs/_sources/sg_execution_times.rst.txt
@@ -6,7 +6,7 @@
Computation times
=================
-**00:23.799** total execution time for 16 files **from all galleries**:
+**00:23.753** total execution time for 16 files **from all galleries**:
.. container::
@@ -33,22 +33,22 @@ Computation times
- Time
- Mem (MB)
* - :ref:`sphx_glr_how_to_tutorials_optimize_llm.py` (``../how_to/tutorials/optimize_llm.py``)
- - 00:11.414
+ - 00:11.421
- 0.0
* - :ref:`sphx_glr_get_started_tutorials_ir_module.py` (``../get_started/tutorials/ir_module.py``)
- - 00:05.757
+ - 00:05.742
- 0.0
* - :ref:`sphx_glr_how_to_tutorials_import_model.py` (``../how_to/tutorials/import_model.py``)
- - 00:03.645
+ - 00:03.628
- 0.0
* - :ref:`sphx_glr_how_to_tutorials_e2e_opt_model.py` (``../how_to/tutorials/e2e_opt_model.py``)
- - 00:00.688
+ - 00:00.672
- 0.0
* - :ref:`sphx_glr_how_to_tutorials_cross_compilation_and_rpc.py` (``../how_to/tutorials/cross_compilation_and_rpc.py``)
- - 00:00.562
+ - 00:00.561
- 0.0
* - :ref:`sphx_glr_deep_dive_tensor_ir_tutorials_tir_creation.py` (``../deep_dive/tensor_ir/tutorials/tir_creation.py``)
- - 00:00.380
+ - 00:00.383
- 0.0
* - :ref:`sphx_glr_deep_dive_tensor_ir_tutorials_tir_transformation.py` (``../deep_dive/tensor_ir/tutorials/tir_transformation.py``)
- 00:00.354
@@ -57,16 +57,16 @@ Computation times
- 00:00.331
- 0.0
* - :ref:`sphx_glr_deep_dive_relax_tutorials_relax_creation.py` (``../deep_dive/relax/tutorials/relax_creation.py``)
- - 00:00.209
+ - 00:00.208
- 0.0
* - :ref:`sphx_glr_get_started_tutorials_quick_start.py` (``../get_started/tutorials/quick_start.py``)
- - 00:00.182
+ - 00:00.180
- 0.0
* - :ref:`sphx_glr_deep_dive_tensor_ir_tutorials_dlight_gpu_scheduling.py` (``../deep_dive/tensor_ir/tutorials/dlight_gpu_scheduling.py``)
- 00:00.152
- 0.0
* - :ref:`sphx_glr_deep_dive_relax_tutorials_relax_transformation.py` (``../deep_dive/relax/tutorials/relax_transformation.py``)
- - 00:00.069
+ - 00:00.068
- 0.0
* - :ref:`sphx_glr_how_to_tutorials_bring_your_own_codegen.py` (``../how_to/tutorials/bring_your_own_codegen.py``)
- 00:00.041
diff --git a/docs/_sources/reference/api/python/tirx/analysis.rst.txt b/docs/_sources/tirx/api/analysis.rst.txt
similarity index 100%
rename from docs/_sources/reference/api/python/tirx/analysis.rst.txt
rename to docs/_sources/tirx/api/analysis.rst.txt
diff --git a/docs/_sources/tirx/api/backend.rst.txt b/docs/_sources/tirx/api/backend.rst.txt
new file mode 100644
index 00000000000..3a391039019
--- /dev/null
+++ b/docs/_sources/tirx/api/backend.rst.txt
@@ -0,0 +1,66 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+tvm.backend.cuda
+================
+
+The CUDA backend — the tile-primitive dispatch, intrinsic builders, the ``T.cuda``
+/ ``T.ptx`` script namespaces, and the shared/tensor-memory pools — lives under
+``tvm.backend.cuda``, separate from the TIRx frontend (``tvm.tirx``). Other
+backends sit alongside it (``tvm.backend.rocm`` and so on).
+
+tvm.backend.cuda
+****************
+.. automodule:: tvm.backend.cuda
+ :members:
+ :imported-members:
+ :exclude-members: PrimExpr, Op, Call
+
+tvm.backend.cuda.lang
+*********************
+.. automodule:: tvm.backend.cuda.lang
+ :members:
+ :imported-members:
+ :exclude-members: PrimExpr, Op, Call
+
+tvm.backend.cuda.op
+*******************
+.. automodule:: tvm.backend.cuda.op
+ :members:
+ :imported-members:
+ :exclude-members: PrimExpr, Op, Call
+
+tvm.backend.cuda.script
+***********************
+.. automodule:: tvm.backend.cuda.script
+ :members:
+ :imported-members:
+ :exclude-members: PrimExpr, Op, Call
+
+tvm.backend.cuda.operator
+*************************
+.. automodule:: tvm.backend.cuda.operator
+ :members:
+ :imported-members:
+ :exclude-members: PrimExpr, Op, Call
+
+tvm.backend.cuda.target_tags
+****************************
+.. automodule:: tvm.backend.cuda.target_tags
+ :members:
+ :imported-members:
+ :exclude-members: PrimExpr, Op, Call
diff --git a/docs/_sources/reference/api/python/tirx/transform.rst.txt b/docs/_sources/tirx/api/index.rst.txt
similarity index 83%
copy from docs/_sources/reference/api/python/tirx/transform.rst.txt
copy to docs/_sources/tirx/api/index.rst.txt
index 6f476c1b300..ee77f1e48f1 100644
--- a/docs/_sources/reference/api/python/tirx/transform.rst.txt
+++ b/docs/_sources/tirx/api/index.rst.txt
@@ -15,10 +15,16 @@
specific language governing permissions and limitations
under the License.
+API Reference
+=============
-tvm.tirx.transform
-------------------
-.. automodule:: tvm.tirx.transform
- :members:
- :exclude-members: Attrs
- :imported-members:
+Python API for the ``tvm.tirx`` namespace.
+
+.. toctree::
+ :maxdepth: 1
+
+ tirx
+ analysis
+ stmt_functor
+ transform
+ backend
diff --git a/docs/_sources/reference/api/python/tirx/stmt_functor.rst.txt b/docs/_sources/tirx/api/stmt_functor.rst.txt
similarity index 100%
rename from docs/_sources/reference/api/python/tirx/stmt_functor.rst.txt
rename to docs/_sources/tirx/api/stmt_functor.rst.txt
diff --git a/docs/_sources/reference/api/python/tirx/tirx.rst.txt b/docs/_sources/tirx/api/tirx.rst.txt
similarity index 94%
rename from docs/_sources/reference/api/python/tirx/tirx.rst.txt
rename to docs/_sources/tirx/api/tirx.rst.txt
index d64c248344b..143f510fc98 100644
--- a/docs/_sources/reference/api/python/tirx/tirx.rst.txt
+++ b/docs/_sources/tirx/api/tirx.rst.txt
@@ -20,4 +20,4 @@ tvm.tirx
.. automodule:: tvm.tirx
:members:
:imported-members:
- :exclude-members: PrimExpr, const
+ :exclude-members: PrimExpr, Op, Call, const
diff --git a/docs/_sources/reference/api/python/tirx/transform.rst.txt b/docs/_sources/tirx/api/transform.rst.txt
similarity index 95%
rename from docs/_sources/reference/api/python/tirx/transform.rst.txt
rename to docs/_sources/tirx/api/transform.rst.txt
index 6f476c1b300..d847b2baf5d 100644
--- a/docs/_sources/reference/api/python/tirx/transform.rst.txt
+++ b/docs/_sources/tirx/api/transform.rst.txt
@@ -20,5 +20,5 @@ tvm.tirx.transform
------------------
.. automodule:: tvm.tirx.transform
:members:
- :exclude-members: Attrs
+ :exclude-members: Attrs, PrimExpr, Op, Call
:imported-members:
diff --git a/docs/_sources/reference/api/python/tirx/backend.rst.txt b/docs/_sources/tirx/arch/index.rst.txt
similarity index 85%
rename from docs/_sources/reference/api/python/tirx/backend.rst.txt
rename to docs/_sources/tirx/arch/index.rst.txt
index 35d64338024..f5eb56af1f8 100644
--- a/docs/_sources/reference/api/python/tirx/backend.rst.txt
+++ b/docs/_sources/tirx/arch/index.rst.txt
@@ -15,11 +15,12 @@
specific language governing permissions and limitations
under the License.
-tvm.tirx.backend
-================
+Compiler Internals
+==================
-tvm.tirx.backend
-*****************
-.. automodule:: tvm.tirx.backend
- :members:
- :imported-members:
+Internals of the TIRx compiler, for contributors.
+
+.. toctree::
+ :maxdepth: 1
+
+ lowering_pipeline
diff --git a/docs/_sources/tirx/arch/lowering_pipeline.rst.txt b/docs/_sources/tirx/arch/lowering_pipeline.rst.txt
new file mode 100644
index 00000000000..3f80301b668
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+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+TIRx lowering pipeline
+======================
+
+``tvm.compile(mod, target, tir_pipeline="tirx")`` runs an authored TIRx module
+through the **tirx pipeline** — an ordered sequence of TIR passes that turns the
+high-level constructs you write (tile primitives, ``TileLayout``-typed buffers,
+execution-scope ids) into split **host** + **device** functions, which the CUDA
+backend then renders to source. The pipeline is defined in
+``python/tvm/tirx/compilation_pipeline.py`` (``tirx_pipeline``); this page walks the
+passes in order.
+
+Where it sits
+-------------
+
+``tvm.compile`` first binds the target, runs the **tirx pipeline** (the module-level
+passes below), then applies **finalization** passes separately to the host and
+device functions, and finally hands each device function to the CUDA code
+generator:
+
+.. code-block:: text
+
+ authored TIRx ──BindTarget──▶ tirx_pipeline ──▶ host func ──host finalize──▶ C/LLVM
+ │
+ └──────────▶ device func ──device finalize──▶ CUDA
+
+The passes
+----------
+
+The ``tirx_pipeline`` module pass applies this exact sequence (a few are gated by
+``PassContext`` config):
+
+.. list-table::
+ :header-rows: 1
+ :widths: 6 32 62
+
+ * - #
+ - Pass
+ - What it does
+ * - 1
+ - ``LowerTIRx``
+ - the core lowering — see `Inside LowerTIRx`_ below
+ * - 2
+ - ``UnifyThreadBinding``
+ - merges equivalent thread-axis bindings so each ``threadIdx`` / ``blockIdx``
+ axis is declared once
+ * - 3
+ - ``StmtSimplify``
+ - statement-level arithmetic simplification (the arith analyzer)
+ * - 4
+ - ``LowerTIRxOpaque``
+ - lowers remaining opaque TIRx constructs to plain TIR
+ * - 5
+ - ``FlattenBuffer``
+ - flattens multi-dimensional ``BufferLoad`` / ``BufferStore`` to 1-D
+ * - 6
+ - ``BF16ComputeLegalize``
+ - rewrites ``bfloat16`` compute to a legal (f32-up-cast) form
+ * - 7
+ - ``NarrowDataType(32)``
+ - narrows index/loop ``PrimExpr`` dtypes to 32-bit where provably safe
+ * - 8
+ - ``VectorizeLoop``
+ - turns ``T.vectorized`` loops into vector ops (skipped if
+ ``tir.disable_vectorize``)
+ * - 9
+ - ``UnrollLoop``
+ - unrolls loops marked ``T.unroll`` (and small constant loops)
+ * - 10
+ - ``StmtSimplify``
+ - simplify again, now that vectorize/unroll exposed constants
+ * - 11
+ - ``CommonSubexprElim``
+ - hoists repeated subexpressions into temporaries (skipped if
+ ``tir.disable_cse_tir``)
+ * - 12
+ - ``FP8ComputeLegalize``
+ - rewrites ``float8`` compute to a legal form
+ * - 13
+ - ``VerifyMemory``
+ - checks no host-side code directly dereferences device memory (a safety gate)
+ * - 14
+ - ``AnnotateEntryFunc``
+ - marks the single PrimFunc as the module entry point
+ * - 15
+ - ``SplitHostDevice``
+ - splits each kernel into a **host** function and a **device** function at the
+ ``launch_thread`` boundary
+ * - 16
+ - ``MakePackedAPI``
+ - rewrites the host function to the packed-func ABI (the launcher TVM calls)
+ * - 17
+ - ``FP8StorageLegalize``
+ - legalizes ``float8`` storage (packing into supported container types)
+ * - 18
+ - ``BF16StorageLegalize``
+ - legalizes ``bfloat16`` storage
+
+**Finalization** then runs per function kind:
+
+- **host**: ``LowerTVMBuiltin`` (lower ``tvm_*`` builtins), ``LowerIntrin``
+ (target-specific intrinsics)
+- **device**: ``LowerWarpMemory`` (warp-scoped buffers → shuffles), ``StmtSimplify``,
+ ``LowerIntrin``
+
+Inside LowerTIRx
+----------------
+
+``LowerTIRx`` is itself a small sequence (``src/tirx/transform/lower_tirx.cc``):
+
+.. code-block:: text
+
+ LowerTIRx = Sequential([ TilePrimitiveDispatch, LowerTIRxCleanup ])
+
+- **``TilePrimitiveDispatch``** replaces every ``TilePrimitiveCall`` (``copy``,
+ ``gemm``, ``reduction``, …) with the body emitted by its selected backend
+ dispatch — the variant-selection and codegen described in
+ :doc:`../tile_primitives`.
+- **``LowerTIRxCleanup``** runs the ``LayoutApplier``: it resolves every
+ ``TileLayout``-typed buffer access into concrete physical address arithmetic
+ (``addr = data + elem_offset + layout.apply(coord)``), flattens the buffers, and
+ lowers the execution-scope ids (``T.cta_id`` / ``T.thread_id`` / … →
+ ``blockIdx`` / ``threadIdx`` via ``launch_thread``).
+
+So after ``LowerTIRx`` the module is plain TIR: no tile primitives, no
+``TileLayout`` indirection, scope ids resolved to thread axes.
+
+A worked example
+----------------
+
+Take a one-line scale kernel:
+
+.. code-block:: python
+
+ @T.prim_func
+ def scale(A_ptr: T.handle, B_ptr: T.handle):
+ A = T.match_buffer(A_ptr, (256,), "float32")
+ B = T.match_buffer(B_ptr, (256,), "float32")
+ T.device_entry(); bx = T.cta_id([1]); tx = T.thread_id([256])
+ B[tx] = A[tx] * T.float32(2.0)
+
+**After ``LowerTIRx``** the scope ids are real thread axes and the layout is applied
+(``A_1`` / ``B_1`` are the flattened 1-D views):
+
+.. code-block:: python
+
+ with T.launch_thread("blockIdx.x", 1) as blockIdx_x:
+ threadIdx_x = T.launch_thread("threadIdx.x", 256)
+ bx: T.let = blockIdx_x
+ tx: T.let = threadIdx_x
+ B_1[threadIdx_x] = A_1[threadIdx_x] * T.float32(2.0)
+
+**After ``SplitHostDevice`` + ``MakePackedAPI``** the one function has become two —
+a host launcher and a device kernel:
+
+.. code-block:: python
+
+ @I.ir_module
+ class Module:
+ def main(...): # host: packed-API launcher (computes the grid/block, launches)
+ ...
+ def scale_kernel(...): # device: the __global__ body, run on the GPU
+
+The CUDA backend then renders ``scale_kernel`` to the ``__global__`` function
+(``B_ptr[threadIdx.x] = A_ptr[threadIdx.x] * 2.0f``).
+
+Reproduce it yourself
+---------------------
+
+You can run any prefix of the pipeline by hand to inspect a stage — this is how the
+IR snippets across these docs were produced:
+
+.. code-block:: python
+
+ from tvm.tirx import transform as TT
+
+ target = tvm.target.Target("cuda")
+ mod = TT.BindTarget(target.with_host("llvm"))(tvm.IRModule({"main": scale}))
+ mod = TT.LowerTIRx()(mod) # tile primitives dispatched, layouts applied
+ print(mod.script()) # inspect the lowered TIRx IR
+
+Or compile the whole module and read the generated CUDA:
+
+.. code-block:: python
+
+ exe = tvm.compile(tvm.IRModule({"main": scale}), target=target, tir_pipeline="tirx")
+ print(exe.mod.imports[0].inspect_source())
diff --git a/docs/_sources/tirx/install.rst.txt b/docs/_sources/tirx/install.rst.txt
new file mode 100644
index 00000000000..3c273ba21e4
--- /dev/null
+++ b/docs/_sources/tirx/install.rst.txt
@@ -0,0 +1,100 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+Installation
+============
+
+There are two pieces:
+
+- the **TIRx compiler** (``tvm.tirx``), which ships inside Apache TVM — this is
+ all you need to write and compile kernels;
+- the optional **kernel library** (``tirx-kernels``), a set of ready-made GEMM
+ and attention kernels built with TIRx.
+
+Requirements
+------------
+
+- Python ≥ 3.10.
+- An NVIDIA GPU with a recent CUDA toolkit. The bundled kernels target Blackwell
+ (``sm_100a``); the compiler itself targets GPUs and accelerators more broadly.
+
+Install the TIRx compiler
+-------------------------
+
+Install the Apache TVM wheel (the TIRx compiler is the ``tvm.tirx`` module):
+
+.. code-block:: bash
+
+ pip install apache-tvm==0.25.0
+
+Verify:
+
+.. code-block:: bash
+
+ python -c "import tvm, tvm.tirx; print(tvm.__version__)"
+
+Install the kernel library (optional)
+-------------------------------------
+
+``tirx-kernels`` provides prebuilt kernels (``fp16_bf16_gemm``,
+``fp8_blockwise_gemm``, ``nvfp4_gemm``, ``flash_attention4``). It has no PyPI
+wheel — install it from source:
+
+.. code-block:: bash
+
+ git clone https://github.com/mlc-ai/tirx-kernels
+ cd tirx-kernels
+ pip install -e .
+
+Its runtime dependencies are **not** pulled from PyPI and must be available
+separately (they are imported lazily, so ``import tirx_kernels`` and kernel
+discovery work without them — they are only needed to actually compile/run a
+kernel):
+
+.. list-table::
+ :header-rows: 1
+ :widths: 18 24 58
+
+ * - Dependency
+ - Needed by
+ - Notes
+ * - ``tvm.tirx``
+ - all kernels
+ - the TIRx compiler (installed above, or put a source checkout's
+ ``python/`` on ``PYTHONPATH``)
+ * - ``torch``
+ - all kernels
+ - a CUDA build matching your GPU
+ * - ``deep_gemm``
+ - ``fp8_blockwise_gemm``
+ - optional — quantization helpers and the reference baseline
+ * - ``flashinfer``
+ - ``nvfp4_gemm``
+ - optional — quantization and the baseline
+
+Build from source
+-----------------
+
+To develop TIRx or build the docs, build TVM from source and make it importable.
+See :doc:`/install/from_source` for the full instructions; in short:
+
+.. code-block:: bash
+
+ export TVM_HOME=/path/to/tvm
+ export TVM_LIBRARY_PATH=$TVM_HOME/build
+ export PYTHONPATH=$TVM_HOME/python:$PYTHONPATH
+ python -c "import tvm, tvm.tirx; print(tvm.__file__)"
diff --git a/docs/_sources/tirx/layout.rst.txt b/docs/_sources/tirx/layout.rst.txt
new file mode 100644
index 00000000000..690e03ef974
--- /dev/null
+++ b/docs/_sources/tirx/layout.rst.txt
@@ -0,0 +1,383 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+Tensor Layout
+=============
+
+A tensor layout describes how a logical tensor is stored in physical resources.
+TIRx generalizes the classical *shape–stride* model: strides are semantically
+**named** and bound to **axes** that represent hardware resources — memory,
+threads, and devices. A layout maps each logical index to a *set* of coordinates
+on these named axes, decomposed into shard (``D``), replica (``R``), and offset
+(``O``).
+
+Interactive demo
+----------------
+
+Pick a preset, edit the logical shape and the ``S/R/O`` layout, choose a dtype +
+swizzle mode, then click an element to see exactly which physical thread(s) own
+it.
+
+.. raw:: html
+
+ <p>
+ <a class="reference external" href="https://mlc.ai/modern-gpu-programming-for-mlsys/_static/tirx-layout-demo/index.html"
+ target="_blank" rel="noopener"
+ style="display:inline-block; padding:10px 18px; background:#3b82f6;
+ color:#fff !important; font-weight:700; border-radius:8px;
+ text-decoration:none;">▶ Open the interactive layout demo ↗</a>
+ </p>
+
+TileLayout
+----------
+
+An **iter** is a triple ``(extent, stride, axis)`` that defines a linear,
+strided access on one axis.
+
+- **D (Shard).** A list of one or more iters, each with an extent and a stride on
+ some axis. ``D`` partitions the logical index across these iters and produces a
+ base coordinate; this generalizes shape–stride to multiple axes. Written in
+ parentheses, e.g. ``S[(8,2,4,2):(4@laneid,1@warpid,1@laneid,1)]``.
+- **R (Replica).** A set of replication iters that enumerate offsets in hardware
+ space, independent of the logical index. Adding each element of the set to the
+ ``D`` result yields replication or broadcasting. Written in square brackets,
+ e.g. ``R[2:4@warpid]``.
+- **O (Offset).** A fixed coordinate offset (one integer per axis) added to every
+ result. This places data at a base position or reserves exclusive resources.
+
+Formally, for a logical index ``x`` the layout produces
+
+.. math::
+
+ L(x) = \{\, D(x) + r + O \mid r \in R \,\},
+
+where ``D(x)`` is the base coordinate from the sharded iters, ``r`` ranges over
+all combinations of the replica iters (a single zero offset when ``R`` is empty),
+and ``O`` is the constant offset. ``L(x)`` can be a singleton or contain multiple
+coordinates. A term is written ``n @ axis``; if a stride is not paired with an
+axis, the memory axis ``m`` is used by default.
+
+Forward mapping
+~~~~~~~~~~~~~~~
+
+Evaluating ``L(x)`` for a logical coordinate ``x = (x_0, …, x_{r-1})`` in a shape
+``(S_0, …, S_{r-1})`` is four mechanical steps.
+
+**1. Flatten** the coordinate row-major to a single index:
+
+.. math::
+
+ \mathrm{flat} = \sum_{d} x_d \prod_{e > d} S_e .
+
+**2. Split** that index across the shard extents ``(e_0, …, e_{n-1})``
+(one component ``c_k`` per shard iter, innermost-first):
+
+.. math::
+
+ c_k = \left\lfloor \mathrm{flat} \,\Big/ \textstyle\prod_{l > k} e_l \right\rfloor
+ \bmod e_k .
+
+**3. Accumulate** each component onto its axis with its stride to get the base
+coordinate, then **add the offset**:
+
+.. math::
+
+ D(x)[a] = \sum_{k\,:\,a_k = a} c_k\, s_k ,
+ \qquad
+ \bigl(D(x) + O\bigr)[a] = D(x)[a] + O[a] .
+
+**4. Broadcast** the replica iters: ``r`` ranges over
+``∏_t [0, e_t)`` and adds, per replica iter ``(e_t, s_t, a_t)``, ``r_t s_t`` to
+axis ``a_t`` — yielding the set ``L(x)``:
+
+.. math::
+
+ L(x)[a] = D(x)[a] + O[a] + \sum_{t\,:\,a_t = a} r_t\, s_t .
+
+A shape is *admitted* by a layout when its total size equals
+``∏_k e_k``; the same layout then works for any such shape (the flatten/split
+re-derives the per-iter components).
+
+Case study: NVIDIA tensor-core tile
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Consider a logical ``(8, 16)`` tile distributed across 2 warps of 32 lanes each,
+with each lane holding part of the tile in its registers (the ``reg`` slot is the
+default memory axis ``m``)::
+
+ S[(8,2,4,2):(4@laneid,1@warpid,1@laneid,1)] + R[2:4@warpid] + 5@warpid
+
+The shard factors the logical indices into four iters of extent ``8, 2, 4, 2``
+over axes ``laneid, warpid, laneid, m``. Running the four steps on element
+``(i, j)``:
+
+#. **flatten:** ``flat = 16 i + j``.
+#. **split** by ``(8, 2, 4, 2)``: ``c_0 = i``, ``c_1 = ⌊j/8⌋``,
+ ``c_2 = ⌊j/2⌋ mod 4``, ``c_3 = j mod 2``.
+#. **accumulate + offset:** ``laneid = 4 c_0 + c_2 = 4 i + ⌊j/2⌋ mod 4`` (two
+ iters land on ``laneid``); ``warpid = c_1 + 5 = ⌊j/8⌋ + 5`` (offset
+ ``5@warpid``); ``m = c_3 = j mod 2``.
+#. **replica** ``R[2:4@warpid]``: ``r ∈ {0, 1}`` adds ``4r`` to ``warpid``, so
+ each element lives on **two** warps.
+
+So the full mapping is
+
+.. math::
+
+ \mathrm{laneid} = 4 i + \lfloor j/2 \rfloor \bmod 4, \quad
+ \mathrm{warpid} = \lfloor j/8 \rfloor + 5 + 4 r\ (r \in \{0,1\}), \quad
+ m = j \bmod 2 .
+
+The shard places the tile on warps ``{5, 6}`` (``⌊j/8⌋ + 5``); the replica copies
+it to ``{9, 10}``. A few elements:
+
+.. list-table::
+ :header-rows: 1
+ :widths: 14 10 26 12 20 10
+
+ * - ``(i, j)``
+ - flat
+ - ``(c0, c1, c2, c3)``
+ - laneid
+ - warpid (×2)
+ - ``m``
+ * - ``(0, 0)``
+ - 0
+ - ``(0, 0, 0, 0)``
+ - 0
+ - ``{5, 9}``
+ - 0
+ * - ``(0, 1)``
+ - 1
+ - ``(0, 0, 0, 1)``
+ - 0
+ - ``{5, 9}``
+ - 1
+ * - ``(0, 2)``
+ - 2
+ - ``(0, 0, 1, 0)``
+ - 1
+ - ``{5, 9}``
+ - 0
+ * - ``(1, 0)``
+ - 16
+ - ``(1, 0, 0, 0)``
+ - 4
+ - ``{5, 9}``
+ - 0
+ * - ``(0, 8)``
+ - 8
+ - ``(0, 1, 0, 0)``
+ - 0
+ - ``{6, 10}``
+ - 0
+ * - ``(7, 15)``
+ - 127
+ - ``(7, 1, 3, 1)``
+ - 31
+ - ``{6, 10}``
+ - 1
+
+Case study: Blackwell tensor memory
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The same machinery places a tensor into Blackwell **tensor memory**, a 2D address
+space addressed by ``TLane`` × ``TCol`` (both *memory* axes). Where the register
+tile bound strides to thread axes, here every stride binds to a memory axis, so
+the layout is a pure placement — no threads, no replica, no offset, and ``L(x)``
+is a singleton::
+
+ S[(2,128,112):(112@TCol,1@TLane,1@TCol)]
+
+Take the logical tile shape equal to the shard extents, ``(2, 128, 112)`` — then
+the split step is the identity (``c_k = x_k``), and element ``(a, l, c)`` maps to:
+
+.. math::
+
+ \mathrm{TLane} = l, \qquad \mathrm{TCol} = 112\,a + c .
+
+The extent-128 iter (``1@TLane``) lays the tile across **128 lanes**; the
+extent-2 iter (``112@TCol``) and the extent-112 iter (``1@TCol``) together cover
+**224 columns** (``TCol = 112 a + c ∈ [0, 224)``). A few elements:
+
+.. list-table::
+ :header-rows: 1
+ :widths: 28 14 14
+
+ * - ``(a, l, c)``
+ - TLane
+ - TCol
+ * - ``(0, 0, 0)``
+ - 0
+ - 0
+ * - ``(0, 5, 3)``
+ - 5
+ - 3
+ * - ``(1, 0, 0)``
+ - 0
+ - 112
+ * - ``(1, 127, 111)``
+ - 127
+ - 223
+
+The 224-wide span is intentionally **not a power of two**: a block-scaled FP8
+GEMM may use a 224-column tile because tensor memory cannot hold two accumulator
+stages plus the scale factors at 256. General-shape support is what lets the
+layout express this directly.
+
+**Scale factors (SFA / SFB).** A block-scaled MMA also keeps its per-block scale
+factors in tensor memory, and their layout is the first one here to use a
+**replica**. The atom is::
+
+ S[(32, sf_per_mma):(1@TLane, 1@TCol)] + R[4:32@TLane]
+
+— 32 rows on ``TLane`` and ``sf_per_mma`` scale factors on ``TCol``, with the
+replica ``R[4:32@TLane]`` routing that 32-row group across the **four warps** of a
+warpgroup (stride 32 covers lanes 0–127) — the "warpx4" router, so one physical
+scale-factor group feeds all four warps. The atom is then direct-summed with an
+outer over ``(M rows, K scale-factor groups)``, packing ``epc = 32 / SF_bits``
+scale factors into each 32-bit ``TCol`` cell (e.g. four fp8 ``e8m0`` SFs per cell);
+optional stride-0 ``reuse`` and outer ``pipe_depth`` iters express SF reuse across
+MMAs and double-buffering. So the one ``TileLayout`` model expresses both the
+accumulator (a pure placement, no replica) and its scale factors (a replicated,
+routed placement) in the same tensor-memory address space.
+
+Beyond GPU registers
+~~~~~~~~~~~~~~~~~~~~~~
+
+The same layout describes more than register tiles. Binding strides to a device
+axis (``pid``) expresses **distributed sharding** across a GPU mesh; binding them
+to on-chip memory axes expresses native accelerator memories — a 2D-partitioned
+scratchpad (partition ``P`` and free ``F`` axes), or NVIDIA Blackwell tensor
+memory with native 2D addressing (``TLane`` × ``TCol``). The demo includes
+presets for each.
+
+SwizzleLayout, ComposeLayout
+----------------------------
+
+Some layouts also need a *swizzle*: a non-linear, XOR-based permutation of the
+linear memory address. It is not expressible as a strided ``TileLayout`` (which
+is affine), so TIRx represents it as a separate ``SwizzleLayout`` composed with
+the tile layout: ``ComposeLayout(swizzle, tile)``. The tile layout produces a
+linear memory address; the swizzle then permutes that address.
+
+Why swizzle
+~~~~~~~~~~~
+
+Shared memory is organized into **32 banks of 4 bytes**. Consecutive 4-byte
+words land in consecutive banks and wrap every ``32 × 4 = 128`` bytes (one
+*bank line*). A bank conflict occurs when the threads of an access touch
+different addresses in the **same** bank.
+
+Store a tile row-major and the conflict is structural. Take an ``(8, 64)``
+``float16`` tile (``S[(8,64):(64@m,1@m)]`` — element ``(i, j)`` at address
+``m = 64i + j``). One row is ``64 × 2 = 128`` bytes = exactly one bank line, so
+walking *down a column* (fixed ``j``, increasing ``i``) jumps the address by a
+whole bank line and lands on the **same bank** every time — a 32-way column
+conflict. Swizzle scatters those accesses across banks.
+
+The transform
+~~~~~~~~~~~~~
+
+A ``SwizzleLayout`` has three integer parameters — ``per_element`` (M),
+``swizzle_len`` (B), and ``atom_len`` (S) — and maps a linear element address
+``m`` as follows (keeping the low ``M`` bits untouched and XOR-ing a higher bit
+group down into a lower one):
+
+.. math::
+
+ \text{addr}(m) = \bigl(f(m \gg M)\bigr)\!\cdot\! 2^{M} + (m \bmod 2^{M}),
+ \qquad
+ f(x) = x \oplus \bigl((x \mathbin{\&} (\,(2^{B}-1)\ll S\,)) \gg S\bigr).
+
+So the bits at positions ``[S, S+B)`` of ``x = m >> M`` are XOR-ed into bits
+``[0, B)``. The well-formedness requirement is ``S ≥ B``.
+
+Choosing the parameters
+~~~~~~~~~~~~~~~~~~~~~~~~~
+
+In practice the parameters come from the **element dtype** and the **swizzle
+mode** (the 32B / 64B / 128B shared-memory swizzle widths):
+
+.. math::
+
+ M = \operatorname{bitlen}\!\left(\frac{128}{\text{dtype bits}}\right) - 1,
+ \qquad
+ B = \begin{cases} 1 & 32\text{B} \\ 2 & 64\text{B} \\ 3 & 128\text{B} \end{cases},
+ \qquad
+ S = 3 .
+
+For example ``float16`` (16-bit) gives ``M = bitlen(8) - 1 = 3``; with 128B
+swizzle that is ``Swizzle(M=3, B=3, S=3)``. ``M`` keeps a 16-byte (128-bit)
+contiguous run unswizzled, matching the minimum vector access.
+
+Bank and line of an element
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Because a bank word is 4 bytes and an element is ``b = dtype_bytes`` bytes, the
+swizzled element address ``a = addr(m)`` lands in
+
+.. math::
+
+ \text{bankword} = \left\lfloor \frac{a \cdot b}{4} \right\rfloor,
+ \qquad
+ \text{bank} = \text{bankword} \bmod 32,
+ \qquad
+ \text{line} = \left\lfloor \frac{\text{bankword}}{32} \right\rfloor .
+
+Worked example: 128B swizzle, ``float16``, ``(8, 64)`` tile
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+With ``Swizzle(3,3,3)`` over ``m = 64i + j`` the address simplifies to
+
+.. math::
+
+ \text{addr}(i, j) = 64\,i + 8\,(\lfloor j/8 \rfloor \oplus i) + (j \bmod 8),
+
+and (``b = 2``) ``bank = ⌊addr/2⌋ mod 32``. Reading column ``j = 0`` down the
+8 rows gives ``addr = 72 i`` and banks ``0, 4, 8, 12, 16, 20, 24, 28`` — **eight
+distinct banks, no conflict**. Without the swizzle the same column is
+``bank = ⌊j/2⌋`` for every row — a single bank, fully serialized.
+
+**Key:** the 128B/``float16`` case above is just one instance — with swizzle, a
+read of any **8×16B column is conflict-free, under any format** (32B / 64B / 128B).
+The ``B`` parameter is chosen per swizzle width precisely so the eight 16-byte rows
+of a column always scatter across distinct banks.
+
+In the interactive demo, pick a dtype and a swizzle mode (``none`` / ``32B`` /
+``64B`` / ``128B``) in the *Swizzle (SMEM)* control. The physical panel switches
+to a *line × bank* view (each cell is one 4-byte bank word, holding
+``4 / dtype_bytes`` elements side by side): with ``none`` a column maps to one
+bank (the conflict); with a swizzle the same column is scattered across banks.
+
+Design rationale
+----------------
+
+- **General shape support.** Non-power-of-two shapes are common — in global
+ tensors, multi-stage shared-memory buffers, and capacity-limited on-chip
+ scratchpads — so the layout supports general shapes directly rather than as a
+ special case.
+- **Logical-to-physical mapping.** The map goes from logical coordinates to a set
+ of physical coordinates. This lets replication (one logical element in multiple
+ physical locations) be expressed cleanly, which a physical-to-logical
+ formulation cannot always represent for strided patterns.
+- **Explicit hardware axes.** Axes carry their hardware meaning in the layout
+ itself, so an expression is unambiguous without external context. For instance
+ ``1@tid`` (block-wide thread id) and ``1@tid_in_wg`` (thread id within a
+ warpgroup) are distinct rather than a generic ``t`` whose meaning depends on the
+ definition site. Legality and feasibility checks are left to tile primitive
+ dispatch.
diff --git a/docs/_sources/tirx/native_basics.rst.txt b/docs/_sources/tirx/native_basics.rst.txt
new file mode 100644
index 00000000000..6d373880372
--- /dev/null
+++ b/docs/_sources/tirx/native_basics.rst.txt
@@ -0,0 +1,69 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+TIRx Basics: CUDA C++/PTX native level
+======================================
+
+.. note::
+
+ Native-level kernel authoring for the **CUDA backend** (the ``"cuda"``
+ target): the thread hierarchy, memory scopes, the ``T.cuda.*`` / ``T.ptx.*``
+ intrinsics, and the compile / run / inspect loop. The complete kernels in
+ these chapters (``scale``, ``add``, ``smem_demo``, ``block_sum``, and the
+ warp all-reduce) are tested end-to-end on a CUDA GPU.
+
+What "native level" means
+-------------------------
+
+A native-level TIRx kernel reads like a structured device kernel: you place
+threads yourself, allocate shared/register buffers, write loops and barriers, and
+call device intrinsics directly. There is no automatic scheduling — what you write
+is what is emitted. This is the foundation the tile primitives
+(:doc:`tile_primitives`) are built on; everything here is what those primitives
+ultimately lower to, so it is also where you go when a hardware feature does not
+have a primitive yet.
+
+The authoring model
+-------------------
+
+- ``@T.prim_func`` (or ``@T.jit`` for compile-time-specialized) kernels, written
+ with ``from tvm.script import tirx as T``;
+- ``T.device_entry()`` plus *scope-id* intrinsics for thread binding;
+- ``T.match_buffer`` parameters and ``T.alloc_*`` scratch buffers;
+- ordinary loops, branches, and scalar math;
+- ``tvm.compile(mod, target=..., tir_pipeline="tirx")`` to build, then call the
+ result directly.
+
+All native authoring uses these imports. The ``__future__`` import lets ``@T.jit``
+kernels reference compile-time parameters inside type annotations (see
+:doc:`native_basics/cuda/functions`); it is harmless for ordinary kernels::
+
+ from __future__ import annotations
+ import tvm
+ from tvm.script import tirx as T
+
+.. toctree::
+ :maxdepth: 1
+
+ native_basics/cuda/first_kernel
+ native_basics/cuda/functions
+ native_basics/cuda/parser_utils
+ native_basics/cuda/data_types
+ native_basics/cuda/buffers
+ native_basics/cuda/control_flow
+ native_basics/cuda/threads_sync
+ native_basics/cuda/compiling
diff --git a/docs/_sources/tirx/native_basics/cuda/buffers.rst.txt b/docs/_sources/tirx/native_basics/cuda/buffers.rst.txt
new file mode 100644
index 00000000000..feb2763f625
--- /dev/null
+++ b/docs/_sources/tirx/native_basics/cuda/buffers.rst.txt
@@ -0,0 +1,477 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+Buffers and memory
+==================
+
+Parameter buffers are bound with ``T.match_buffer``; scratch buffers are created
+in the body with one of two declaration APIs (below). Index a buffer with
+``A[i, j]``, slice it with ``A[m0:m0+BM, 0:BK]`` (a ``BufferRegion``), and take a
+pointer with ``A.ptr_to([i, j])`` or the raw data pointer ``A.data``.
+
+Declaring buffers
+-----------------
+
+Two fundamental APIs create a buffer:
+
+- ``T.alloc_buffer(shape, dtype, scope=..., ...)`` — **allocates new storage**
+ (emits an ``AllocBuffer`` node) and returns the ``Buffer``. ``T.alloc_shared`` /
+ ``T.alloc_local`` are just ``alloc_buffer`` with ``scope="shared"`` /
+ ``scope="local"``.
+- ``T.decl_buffer(shape, dtype, data=..., ...)`` — **declares a view** over an
+ existing pointer ``data`` (no allocation); use it to alias or reinterpret
+ storage — a sub-region of a pool, or a tensor-memory address. With ``data=None``
+ it allocates, like ``alloc_buffer``.
+
+A buffer's ``data`` pointer is an immutable ``Var`` (``alloc_buffer`` defines it;
+``decl_buffer`` takes one). To back a buffer with a pointer *expression*, bind it
+first — see :doc:`data_types`.
+
+Both share one descriptor; the parameters that matter most:
+
+.. list-table::
+ :header-rows: 1
+ :widths: 28 72
+
+ * - Parameter
+ - Meaning
+ * - ``dtype``
+ - element type — ``"float32"``, ``"float16"``, ``"float4_e2m1fn"``, …
+ * - ``shape``
+ - logical shape (a tuple of extents)
+ * - ``layout``
+ - physical mapping (:doc:`TileLayout <../../layout>`); ``"default"`` = dense
+ row-major
+ * - ``elem_offset`` / ``allocated_addr``
+ - ``elem_offset`` (or ``byte_offset``) places a *view* at an offset into
+ ``data``; ``allocated_addr`` carries a pre-assigned address (tensor memory)
+ * - ``align``
+ - alignment of the data pointer, in bytes
+
+The ``scope`` argument selects the memory space:
+
+.. list-table::
+ :header-rows: 1
+ :widths: 26 22 52
+
+ * - Scope
+ - Shorthand
+ - Memory
+ * - ``"global"``
+ - (default)
+ - device global memory
+ * - ``"shared"``
+ - ``T.alloc_shared``
+ - static shared memory (``__shared__``)
+ * - ``"shared.dyn"``
+ - (pool)
+ - dynamic shared memory (pooled — see below)
+ * - ``"local"``
+ - ``T.alloc_local``
+ - per-thread registers
+ * - ``"tmem"``
+ - (TMEM pool)
+ - Blackwell tensor memory (see below)
+
+.. code-block:: python
+
+ A = T.match_buffer(A_ptr, (M, K), "float16", align=16) # parameter buffer
+ As = T.alloc_shared((BM, BK), "float16") # new shared tile
+ acc = T.alloc_local((4,), "float32") # register accumulator
+ view = T.decl_buffer((BM, BK), "float16", data=As.data) # a view over As
+
+**A ptr-based buffer is just metadata over a pointer.** For any non-tmem buffer,
+the declaration is a pointer plus a layout, and indexing resolves to an address::
+
+ addr(buffer[coord]) = buffer.data + elem_offset + layout.apply(coord, shape=shape)["m"]
+
+(``layout.apply`` returns the per-axis mapping; its ``"m"`` component is the
+element offset.) So the *same* logical access compiles to different address
+arithmetic depending purely on the buffer's metadata. Writing
+``B[i, j] = A[i, j] + 1`` over a 4×8 region, with ``B`` declared four ways:
+
+.. code-block:: python
+
+ from tvm.tirx.layout import TileLayout, S
+
+ B = T.match_buffer(p, (4, 8), "float32") # row-major
+ B = T.match_buffer(p, (4, 8), "float32", layout=TileLayout(S[(4, 8):(1, 4)])) # column-major
+ B = T.match_buffer(p, (4, 8), "float32", elem_offset=64) # shifted view
+ B = T.match_buffer(p, (4, 8), "float32", layout=TileLayout(S[(4, 8):(16, 1)])) # row stride 16
+
+each makes ``B[i, j]`` lower to a different index in the generated CUDA (the
+``A[i, j]`` load stays ``i*8 + j`` — only ``B``'s metadata changed):
+
+.. code-block:: c++
+
+ B_ptr[((i * 8) + j)] = ...; // row-major: i*8 + j
+ B_ptr[((j * 4) + i)] = ...; // column-major: j*4 + i
+ B_ptr[(((i * 8) + j) + 64)] = ...; // elem_offset=64: i*8 + j + 64
+ B_ptr[((i * 16) + j)] = ...; // row stride 16: i*16 + j
+
+Shared memory
+-------------
+
+Shared memory comes in two flavors — **static** (fixed at compile time) and
+**dynamic** (sized at launch) — plus a pool helper that manages the dynamic case.
+
+Static
+~~~~~~
+
+The simplest shared buffer is a **static** one — ``T.alloc_shared`` (that is,
+``scope="shared"``), sized at compile time. Stage data into it, ``cta_sync`` so the
+whole block sees the writes, then read it back:
+
+.. code-block:: python
+
+ @T.prim_func
+ def smem_demo(A_ptr: T.handle, B_ptr: T.handle):
+ A = T.match_buffer(A_ptr, (128,), "float32")
+ B = T.match_buffer(B_ptr, (128,), "float32")
+ T.device_entry()
+ bx = T.cta_id([1])
+ tx = T.thread_id([128])
+ sm = T.alloc_shared((128,), "float32") # static shared memory
+ sm[tx] = A[tx]
+ T.cuda.cta_sync()
+ B[tx] = sm[tx] * T.float32(2.0)
+
+It lowers to a plain ``__shared__`` array (generated CUDA, boilerplate elided):
+
+.. code-block:: c++
+
+ extern "C" __global__ void __launch_bounds__(128)
+ smem_demo_kernel(float* __restrict__ A_ptr, float* __restrict__ B_ptr) {
+ int tx = ((int)threadIdx.x);
+ __shared__ alignas(64) float sm_ptr[128]; // T.alloc_shared
+ sm_ptr[tx] = A_ptr[tx];
+ __syncthreads(); // T.cuda.cta_sync()
+ B_ptr[tx] = sm_ptr[tx] * 2.0f;
+ }
+
+Dynamic
+~~~~~~~
+
+**Dynamic** shared memory (``scope="shared.dyn"``) is sized per launch (the
+``sharedMemBytes`` launch parameter), not at compile time. A kernel may have **only
+one** dynamic-shared allocation — the *arena*. So you allocate it once and ``decl``
+each buffer as a view into it: ``T.decl_buffer`` with ``data=`` the arena pointer
+and an ``elem_offset``:
+
+.. code-block:: python
+
+ arena = T.alloc_buffer((128,), "float32", scope="shared.dyn") # the one arena
+ As = T.decl_buffer((64,), "float32", data=arena.data, scope="shared.dyn") # offset 0
+ Bs = T.decl_buffer((64,), "float32", data=arena.data, elem_offset=64, scope="shared.dyn") # offset 64
+ As[tx] = A[tx]
+ Bs[tx] = B[tx]
+ T.cuda.cta_sync()
+ C[tx] = As[tx] + Bs[tx]
+
+Both views share the single ``extern __shared__`` arena (generated CUDA,
+boilerplate elided; arena named ``smem`` for clarity):
+
+.. code-block:: c++
+
+ extern __shared__ __align__(64) float smem[]; // the one dynamic-shared arena
+ smem[tx] = A_ptr[tx]; // As — view at offset 0
+ smem[tx + 64] = B_ptr[tx]; // Bs — view at offset 64
+ __syncthreads();
+ C_ptr[tx] = smem[tx] + smem[tx + 64];
+
+(Two separate ``alloc_buffer(scope="shared.dyn")`` is an error — *only one dynamic
+shared memory allocation is allowed*.) So static shared memory is sized at compile
+time (``__shared__ T x[N];``); dynamic shared memory is this one launch-sized arena
+with views decl'd at offsets inside it.
+
+.. note::
+
+ **How TVM annotates the dynamic-shared size.** The arena's size is known at
+ compile time (here ``128`` floats = ``512`` bytes). During lowering TVM appends
+ a ``"tirx.use_dyn_shared_memory"`` tag to the device kernel's
+ ``tirx.kernel_launch_params``, and the host launcher computes the total bytes and
+ passes them as the last launch argument:
+
+ .. code-block:: python
+
+ # device kernel attribute:
+ "tirx.kernel_launch_params": ["blockIdx.x", "threadIdx.x", "tirx.use_dyn_shared_memory"]
+
+ # host-side launch call (..., gridDim.x, blockDim.x, dyn_shared_bytes):
+ T.call_packed("dyn_kernel", A.data, B.data, C.data, 1, 64, 512)
+
+ At run time that ``512`` becomes ``config.sharedMemBytes`` in the
+ ``cuLaunchKernelEx`` call. You never set it by hand — it is derived from the
+ ``shared.dyn`` allocation's size.
+
+Pool sugar
+~~~~~~~~~~
+
+``T.SMEMPool`` automates that arena bookkeeping — it bump-allocates the offsets so
+you don't ``decl`` views by hand. Beyond ``alloc`` / ``commit``, it offers
+per-buffer ``align=``, an ``alloc_mma`` helper that builds an MMA-compatible
+swizzle layout for you, and ``move_base_to`` to rewind the cursor and reuse space:
+
+.. code-block:: python
+
+ pool = T.SMEMPool() # bump allocator over shared.dyn
+ As = pool.alloc((BM, BK), "float16", align=128) # carve a tile
+ Bs = pool.alloc((BK, BN), "float16", align=128)
+ Cs = pool.alloc_mma((BM, BN), "float16") # MMA-compatible, swizzle inferred
+ pool.commit() # finalize the pool's size
+ # pool.move_base_to(offset) rewinds the cursor to reuse space
+
+The TMEM pool (`Tensor memory`_, below) is layered on top of an ``SMEMPool``.
+
+Registers
+---------
+
+Per-thread scratch lives in registers. Allocate it with ``T.alloc_local(shape,
+dtype)`` (i.e. ``scope="local"``): it is private to each thread and lowers to a
+local array kept in registers.
+
+.. code-block:: python
+
+ r = T.alloc_local((4,), "float32") # per-thread register array
+ for k in T.unroll(4):
+ r[k] = A[tx, k]
+ # ... compute on r[0..3] ...
+
+.. code-block:: c++
+
+ alignas(64) float r_ptr[4]; // per-thread, register-resident
+ r_ptr[0] = A_ptr[tx * 4 + 0];
+ r_ptr[1] = A_ptr[tx * 4 + 1];
+ // ...
+
+.. note::
+
+ The ``alignas(64)`` is the *default* buffer alignment — a buffer's
+ ``data_alignment`` defaults to ``runtime::kAllocAlignment`` (64 bytes), and the
+ CUDA codegen stamps it onto every allocation, including per-thread ``local``
+ arrays where it is meaningless. For these register-resident arrays it has **no
+ performance impact**: a thread-local array with statically-resolvable indices is
+ promoted to registers by nvcc/ptxas (scalar replacement of aggregates, SROA), so
+ it never lives in addressable local memory and the alignment is a no-op. (A
+ dynamically-indexed array that spilled to local memory would actually pick up the
+ over-alignment, but that is the unusual case.) This over-alignment of register
+ locals is a known rough edge we plan to fix (use the dtype's natural alignment
+ for ``local`` scope).
+
+Scalar
+~~~~~~
+
+A scalar is just a register array with **one element** — strictly, you don't need a
+separate concept. You can allocate a size-1 ``local`` buffer and index ``[0]``:
+
+.. code-block:: python
+
+ phase = T.alloc_local((1,), "int32") # 1-element register array
+ phase[0] = 0
+ while phase[0] < 4:
+ acc = acc + A[tx, phase[0]]
+ phase[0] += 1
+
+But writing ``phase[0]`` everywhere is clumsy, so a **scalar** is sugar for exactly
+this — a one-element register buffer you read and write **by name**:
+
+.. code-block:: python
+
+ phase: T.int32 = 0 # mutable scalar (sugar for the above)
+ while phase < 4:
+ acc = acc + A[tx, phase]
+ phase += 1
+
+ s = T.local_scalar("int32") # explicit form; assign by name (s = ..., not s[0])
+ acc: T.float32 = 0.0 # a type-annotated assignment also makes one
+
+The two are not just similar — they parse to **structurally identical TIRx**. The
+sugar is resolved entirely in the parser: ``phase: T.int32`` *is* that one-element
+``local`` buffer, and ``phase`` / ``phase += 1`` *are* ``phase[0]`` /
+``phase[0] += 1``. ``tvm.ir.assert_structural_equal`` on the two kernels passes, and
+the printer even renders the explicit ``alloc_local`` + ``[0]`` form **back** as the
+scalar form — so once parsing is done there is no difference at all. Both therefore
+lower to the same ``alignas(64) int phase_ptr[1];``; the scalar just lets you drop
+the ``[0]``. (``T.local_scalar`` / ``T.shared_scalar`` / ``T.alloc_scalar`` choose
+the scope explicitly.)
+
+.. note::
+
+ **Why not a** ``Var``\ **?** A TIRx ``Var`` is *immutable* — a single static
+ binding (it is exactly what ``T.let`` produces, below). A scalar needs to be
+ *mutable* — you reassign it in loops and accumulators — so it must be backed by a
+ one-element buffer you can store into repeatedly, not a ``Var``.
+
+``let``
+~~~~~~~
+
+A ``T.let`` binding is **immutable** — a single ``LetStmt`` (a named value, not a
+buffer). Use it for derived constants:
+
+.. code-block:: python
+
+ n: T.let = M * K # immutable binding (LetStmt)
+ half: T.let[T.int32] = N // 2 # ... with an explicit type
+
+It lowers to a **plain scalar C variable** — not a buffer (no array, no ``[0]``).
+For ``half: T.let = m * 2`` (with a runtime ``m``):
+
+.. code-block:: c++
+
+ int half = m * 2; // the `let` -> a const-like local
+
+Because the value is immutable, the simplifier is free to propagate and CSE it, so
+at the use sites you often see ``m * 2`` substituted directly (or shared through a
+common-subexpression temporary) rather than a reference to ``half``.
+
+.. note::
+
+ **Why have an immutable binding at all?** Because the value cannot change, the
+ arithmetic analyzer binds the var to it (``analyzer.Bind(var, value)`` when it
+ simplifies a ``LetStmt``), so facts proven about the value — constant bounds, the
+ modular set (divisibility / alignment), ranges — **propagate through every use**.
+ That feeds index simplification, bounds-check elimination, and
+ alignment/vectorization decisions. A *mutable* scalar is a memory load
+ (``buf[0]``): the analyzer cannot assume it stays constant, so none of those
+ properties carry through. A ``let`` is also a pure value — no allocation, and
+ free to inline / substitute / CSE — whereas a scalar is a one-element buffer with
+ load/store semantics.
+
+Tensor memory
+-------------
+
+Blackwell *tensor memory* is not a plain scratch scope: it must be explicitly
+reserved and freed with the warp-uniform ``T.ptx.tcgen05.alloc`` /
+``tcgen05.dealloc`` intrinsics, and each tensor is a view into it declared with
+``T.decl_buffer(..., scope="tmem", allocated_addr=<column>, layout=<tmem layout>)``.
+The ``allocated_addr`` (a column offset) is mandatory — the tensor-core dispatch
+asserts it — so ``T.alloc_buffer(scope="tmem")`` (which does **not** set it) will not
+work. Unlike shared memory, tensor memory is not directly addressable: it is read
+and written only through ``tcgen05`` ``mma`` / ``ld`` / ``st`` / ``cp``.
+
+By hand, one warp issues the allocation into a shared slot, you ``decl`` each
+tensor as a view at a column offset, and one warp frees it at the end:
+
+.. code-block:: python
+
+ addr = T.alloc_shared((1,), "uint32") # slot for the allocated base
+ if warp_id == alloc_warp: # tcgen05.alloc is warp-uniform
+ T.ptx.tcgen05.alloc(T.address_of(addr), n_cols=512, cta_group=cta_group)
+ acc = T.decl_buffer((CTA_M, 512), "float32", scope="tmem",
+ allocated_addr=0, layout=tmem_layout) # view at column 0
+ # ... use acc as a gemm_async / copy_async operand ...
+ if warp_id == alloc_warp:
+ T.ptx.tcgen05.relinquish_alloc_permit(cta_group=cta_group)
+ T.ptx.tcgen05.dealloc(addr, n_cols=512, cta_group=cta_group)
+
+You manage the column offsets and the ``tmem_layout`` (a datapath D/F layout)
+yourself. This is exactly the sequence the pool below emits.
+
+Pool
+~~~~
+
+``T.TMEMPool`` wraps all of that — the warp-uniform alloc/dealloc, the column
+bump-allocation, and the datapath layout:
+
+.. code-block:: python
+
+ tmem_addr = pool.alloc((1,), "uint32") # pool = the kernel's smem pool
+ tmem_pool = T.TMEMPool(pool, total_cols=512, cta_group=cta_group,
+ tmem_addr=tmem_addr)
+ acc = tmem_pool.alloc((CTA_M, 512), "float32") # allocated_addr set for you
+ tmem_pool.commit() # emits tcgen05.alloc (one warp)
+ # ... use acc ...
+ tmem_pool.dealloc() # emits tcgen05.dealloc (one warp)
+
+See the :doc:`../../tile_primitives` walkthroughs for full examples.
+
+Buffer APIs
+-----------
+
+A ``Buffer`` is metadata over a pointer (see *Declaring buffers* above), so most of
+its methods are *compile-time* reshapes/reinterprets that change index arithmetic
+or hand you a pointer — they emit no runtime op of their own. The common ones:
+
+.. list-table::
+ :header-rows: 1
+ :widths: 34 66
+
+ * - Method
+ - What it is
+ * - ``B.data``
+ - the raw data pointer (a ``Var``); prints as ``B_ptr``
+ * - ``B.ptr_to([i, j])``
+ - a typed pointer to an element (``address_of``); prints as ``&B_ptr[…]``
+ * - ``B.vload([i], dtype="float32x4")`` / ``B.vstore([i], v)``
+ - a vectorized load / store; prints as ``*(float4*)(B_ptr + …)``
+ * - ``B.view(*shape, layout=…)``
+ - reinterpret the same storage under a new shape/layout (no copy)
+ * - ``B.local(*shape, layout=…)``
+ - the calling thread's private register slice of a ``local`` buffer
+ * - ``B.permute(*dims)``
+ - a view with axes permuted (a transposed layout)
+ * - ``B.access_ptr(mask, …)``
+ - a masked access pointer (the ``tvm_access_ptr`` builtin), for passing a
+ region to an intrinsic
+
+**Pointers — ``ptr_to`` / ``data``.** ``ptr_to`` is how you hand an element address
+to an intrinsic or inline function; ``data`` is the base pointer:
+
+.. code-block:: python
+
+ B[tx] = T.cuda.func_call("ld", A.ptr_to([tx]), source_code=SRC, return_type="float32")
+
+.. code-block:: c++
+
+ B_ptr[tx] = ld(&A_ptr[tx]); // ptr_to([tx]) -> &A_ptr[tx]; A.data -> A_ptr
+
+**Vectorized access — ``vload`` / ``vstore``.** Move several elements as one wide
+transfer (see also :doc:`data_types`):
+
+.. code-block:: python
+
+ B.vstore([tx * 4], A.vload([tx * 4], dtype="float32x4"))
+
+.. code-block:: c++
+
+ *(float4*)(B_ptr + tx * 4) = *(float4*)(A_ptr + tx * 4);
+
+**Reshape / reinterpret — ``view`` / ``permute``.** Both are pure metadata; the
+data pointer is unchanged, only the index arithmetic differs. ``A.view(64, 4)``
+sees the 256-element buffer as ``64×4``; ``A.permute(1, 0)`` transposes the axes:
+
+.. code-block:: python
+
+ A2 = A.view(64, 4); y = A2[tx, 0] + A2[tx, 3] # A2[tx, j] -> A_ptr[tx*4 + j]
+ At = A.permute(1, 0); z = At[i, j] # At[i, j] -> A_ptr[j*4 + i]
+
+.. code-block:: c++
+
+ A2_ptr[tx * 4] /* +3 */ // view: row-major 64x4 index
+ At_ptr[(j * 4) + i] // permute: swapped strides
+
+**Registers — ``local``.** Decomposes a thread-axis ``local`` layout into the
+calling thread's flat register bundle (used pervasively by the tile primitives):
+
+.. code-block:: python
+
+ R = T.alloc_buffer((32, 8), "float32", scope="local", layout=TileLayout(S[(32, 8) : (1 @ laneid, 1)]))
+ Rl = R.local(8) # this lane's 8 registers
+
+.. code-block:: c++
+
+ alignas(64) float Rl_ptr[8]; // the lane's private registers
diff --git a/docs/_sources/tirx/native_basics/cuda/compiling.rst.txt b/docs/_sources/tirx/native_basics/cuda/compiling.rst.txt
new file mode 100644
index 00000000000..a56e40207d9
--- /dev/null
+++ b/docs/_sources/tirx/native_basics/cuda/compiling.rst.txt
@@ -0,0 +1,112 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+Compiling and inspecting
+========================
+
+Wrap the ``PrimFunc`` in an ``IRModule`` and compile with
+``tvm.compile(mod, target=..., tir_pipeline="tirx")``; it runs the TIRx lowering
+pipeline and returns an ``Executable`` you call directly. The arch (e.g.
+``sm_100a``) is auto-detected from the device, so the target ``"cuda"`` is enough.
+
+.. code-block:: python
+
+ target = tvm.target.Target("cuda")
+ exe = tvm.compile(tvm.IRModule({"main": scale}), target=target, tir_pipeline="tirx")
+
+``tir_pipeline="tirx"`` selects the TIRx lowering pipeline (``LowerTIRx`` →
+tile-primitive dispatch → host/device split → finalize). Compiling inside a
+``with target:`` block also works and lets the kernel pick up the target context.
+
+Inspecting the result
+---------------------
+
+Read the IR with ``.show()`` / ``.script()``, and read the generated CUDA from the
+compiled module.
+
+.. code-block:: python
+
+ scale.show() # pretty-print the TIRx (TVMScript)
+ print(scale.script()) # ... the same, as a string
+
+ # the generated CUDA C source, from the compiled Executable:
+ print(exe.mod.imports[0].inspect_source())
+
+Debug aids: ``T.print_buffer(C.data, "float32", False, False, 1, (M,))`` emits a
+runtime ``printf`` of a buffer into the kernel; ``T.hint("message")`` (statement
+or ``with`` block) attaches structured hints that survive a script round-trip.
+
+From simple to complex
+----------------------
+
+A natural native progression, each rung adding one capability:
+
+#. **Elementwise** — ``device_entry`` + ``thread_id`` + a guarded store (the first
+ kernel).
+#. **Shared-memory reduction** — stage into ``T.alloc_shared``, then a
+ ``cta_sync``-separated tree (shown in full below). Adds shared memory and a
+ block barrier.
+#. **Warp / block reduction** — ``T.tvm_warp_shuffle_xor`` or ``T.cuda.cta_sum``
+ to combine partial results across lanes/warps (the warp all-reduce in
+ :doc:`threads_sync`).
+#. **Async pipeline** — ``T.ptx.cp_async`` (or TMA ``cp_async.bulk.tensor``) with
+ ``T.ptx.mbarrier.*`` to overlap loads with compute.
+
+Rung 2 in full — a 256-element block sum via a shared-memory tree reduction
+(shared buffer, ``cta_sync``, a ``while`` loop, and a thread predicate):
+
+.. code-block:: python
+
+ @T.prim_func
+ def block_sum(A_ptr: T.handle, out_ptr: T.handle):
+ A = T.match_buffer(A_ptr, (256,), "float32")
+ out = T.match_buffer(out_ptr, (1,), "float32")
+
+ T.device_entry()
+ bx = T.cta_id([1])
+ tx = T.thread_id([256])
+
+ sm = T.alloc_shared((256,), "float32")
+ sm[tx] = A[tx]
+ T.cuda.cta_sync()
+
+ s = T.alloc_local((1,), "int32")
+ s[0] = 128
+ while s[0] >= 1:
+ if tx < s[0]:
+ sm[tx] += sm[tx + s[0]]
+ T.cuda.cta_sync()
+ s[0] = s[0] // 2
+
+ if tx == 0:
+ out[0] = sm[0]
+
+ exe = tvm.compile(tvm.IRModule({"main": block_sum}),
+ target=tvm.target.Target("cuda"), tir_pipeline="tirx")
+ a = torch.arange(256, device="cuda", dtype=torch.float32)
+ out = torch.zeros(1, device="cuda")
+ exe(a, out) # out[0] == 32640.0
+
+The full tile-level GEMM/attention ladder (sync → TMA → warp specialization →
+2-CTA cluster) is built on top of these and the dispatchable tile primitives in
+:doc:`../../tile_primitives`.
+
+Next steps
+----------
+
+- :doc:`../../layout` — how buffers map to physical resources (``TileLayout``).
+- :doc:`../../tile_primitives` — the dispatchable ops these native idioms lower to.
diff --git a/docs/_sources/tirx/native_basics/cuda/control_flow.rst.txt b/docs/_sources/tirx/native_basics/cuda/control_flow.rst.txt
new file mode 100644
index 00000000000..a2588e45b7e
--- /dev/null
+++ b/docs/_sources/tirx/native_basics/cuda/control_flow.rst.txt
@@ -0,0 +1,100 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+Control flow
+============
+
+Control flow is ``if``, the loop family, and ``while`` — each maps to the obvious
+CUDA.
+
+if
+--
+
+A Python ``if`` / ``else`` becomes a CUDA ``if`` / ``else``. Guard work by a
+thread/lane comparison, or elect a single issuing thread with
+``T.ptx.elect_sync()``:
+
+.. code-block:: python
+
+ if tx < 128:
+ A[tx] = A[tx] * T.float32(2.0)
+ else:
+ A[tx] = A[tx] + T.float32(1.0)
+
+ if T.ptx.elect_sync():
+ ... # one elected lane (e.g. to issue TMA/MMA)
+
+.. code-block:: c++
+
+ if (((int)threadIdx.x) < 128) {
+ A_ptr[tx] = A_ptr[tx] * 2.0f;
+ } else {
+ A_ptr[tx] = A_ptr[tx] + 1.0f;
+ }
+
+For an expression-level choice (no branch), use ``T.if_then_else(cond, a, b)``.
+
+loop
+----
+
+Loops come in four flavors; a plain Python ``range`` becomes ``T.serial``:
+
+- ``T.serial(n)`` — a sequential loop (ptxas may still unroll it).
+- ``T.unroll(n)`` — fully unrolled (expanded to straight-line statements).
+- ``T.vectorized(n)`` — a vectorized loop.
+- ``T.grid(*extents)`` — a nested loop nest.
+
+``break`` / ``continue`` work inside loops.
+
+.. code-block:: python
+
+ for i, j in T.grid(8, 8):
+ B[i, j] = T.max(A[i, j], T.float32(0.0))
+
+.. code-block:: c++
+
+ for (int i = 0; i < 8; ++i)
+ for (int j = 0; j < 8; ++j)
+ B_ptr[i * 8 + j] = max(A_ptr[i * 8 + j], 0.0f);
+
+``T.unroll(4)`` instead expands to four straight-line statements with no loop.
+
+while
+-----
+
+A ``while`` loop runs until its condition is false. Use a mutable scalar counter
+(see :doc:`buffers`):
+
+.. code-block:: python
+
+ i: T.int32 = 0
+ while i < 64:
+ A[i] = A[i] + T.float32(1.0)
+ i += 1
+
+It lowers to a ``while (1)`` with an early-exit ``break`` (the counter is a
+one-element register buffer):
+
+.. code-block:: c++
+
+ int i_ptr[1];
+ i_ptr[0] = 0;
+ while (1) {
+ if (!(i_ptr[0] < 64)) { break; }
+ A_ptr[i_ptr[0]] = A_ptr[i_ptr[0]] + 1.0f;
+ i_ptr[0] = i_ptr[0] + 1;
+ }
diff --git a/docs/_sources/tirx/native_basics/cuda/data_types.rst.txt b/docs/_sources/tirx/native_basics/cuda/data_types.rst.txt
new file mode 100644
index 00000000000..472ac8f0efb
--- /dev/null
+++ b/docs/_sources/tirx/native_basics/cuda/data_types.rst.txt
@@ -0,0 +1,116 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+Data types and expressions
+==========================
+
+Every TIRx expression carries a low-level **dtype** and a high-level **type**.
+
+Expression dtypes
+-----------------
+
+A ``PrimExpr``'s ``.dtype`` is its scalar (or vector) element type — ``float32``,
+``float16``, ``bfloat16``, ``int32``, ``uint8``, ``bool``, the low-precision
+``float8_e4m3fn`` / ``float4_e2m1fn`` …, ``handle`` (a pointer), and vector forms
+such as ``float32x4``. Each prints to the matching CUDA type. Allocating local and
+shared buffers across several dtypes, plus a vectorized ``float32x4`` load/store:
+
+.. code-block:: python
+
+ @T.prim_func
+ def dtypes(A_ptr: T.handle, O_ptr: T.handle):
+ A = T.match_buffer(A_ptr, (256,), "float32")
+ O = T.match_buffer(O_ptr, (256,), "float32")
+ T.device_entry(); bx = T.cta_id([1]); tx = T.thread_id([64])
+ f16 = T.alloc_local((1,), "float16") # register scalars ...
+ bf16 = T.alloc_local((1,), "bfloat16")
+ i32 = T.alloc_local((1,), "int32")
+ u8 = T.alloc_local((1,), "uint8")
+ b1 = T.alloc_local((1,), "bool")
+ sm = T.alloc_shared((64,), "float16") # ... and a shared tile
+ v = T.alloc_local((1,), "float32x4") # a vector-dtype register (float4)
+ v[0] = A.vload([tx * 4], dtype="float32x4") # vectorized load
+ O.vstore([tx * 4], v[0]) # vectorized store
+ # ... (use f16/bf16/i32/u8/b1/sm) ...
+
+lowers to (generated CUDA, elided):
+
+.. code-block:: c++
+
+ half f16_ptr[1]; // float16
+ nv_bfloat16 bf16_ptr[1]; // bfloat16
+ int i32_ptr[1]; // int32
+ uchar u8_ptr[1]; // uint8
+ signed char b1_ptr[1]; // bool
+ __shared__ alignas(64) half sm_ptr[64]; // shared float16
+ float4 v_ptr[1]; // float32x4 (vector)
+ v_ptr[0] = *(float4*)(A_ptr + tx * 4); // vectorized load
+ *(float4*)(O_ptr + tx * 4) = v_ptr[0]; // vectorized store
+
+A buffer's dtype can itself be a **vector type**: ``T.alloc_local((1,), "float32x4")``
+declares a ``float4`` register directly (you index it as ``v[0]``), and a
+``float32x4`` ``vload`` / ``vstore`` then moves it as one 16-byte access. The vector
+dtype is not tied to ``vload`` — any buffer or scalar can carry it.
+
+so the dtype → CUDA mapping is:
+
+.. list-table::
+ :header-rows: 1
+ :widths: 34 33 33
+
+ * - dtype → CUDA
+ - dtype → CUDA
+ - dtype → CUDA
+ * - ``float32`` → ``float``
+ - ``float16`` → ``half``
+ - ``bfloat16`` → ``nv_bfloat16``
+ * - ``int32`` → ``int``
+ - ``uint8`` → ``uchar``
+ - ``bool`` → ``signed char``
+ * - ``float32x4`` → ``float4``
+ - ``handle`` → ``T*`` (pointer)
+ - (vector dtypes → CUDA vector types)
+
+dtype vs type
+-------------
+
+The ``dtype`` is *low-level* — it says "what bits". Separately, a value has a
+high-level **type**: ``PrimType(dtype)`` for a scalar, or
+``PointerType(PrimType(dtype), scope)`` for a pointer. Most expressions are scalars
+(``PrimType``); the type system matters mainly for **pointers**.
+
+Pointers (``handle``)
+---------------------
+
+A buffer's ``data`` — its pointer — is a ``Var`` of pointer type, and it is
+**immutable** (a pointer is never reassigned). That shapes how you obtain one:
+
+- ``T.alloc_buffer(...)`` allocates storage **and** defines its ``data`` pointer.
+- ``T.decl_buffer(..., data=ptr)`` declares a buffer over an existing pointer
+ ``Var`` ``ptr``.
+- To back a buffer with a pointer **expression** — e.g. ``T.ptx.map_shared_rank``
+ (PTX ``mapa``) giving another cluster CTA's shared address — you must first bind
+ that expression to a pointer ``Var`` (``data`` must be a ``Var``, not an
+ expression), using a ``T.let`` of ``PointerType``:
+
+ .. code-block:: python
+
+ from tvm.ir.type import PointerType, PrimType
+
+ ptr: T.let[T.Var(name="ptr", dtype=PointerType(PrimType("uint64")))] = \
+ T.reinterpret("handle", T.ptx.map_shared_rank(mbar.ptr_to([0]), 0))
+ remote_mbar = T.decl_buffer([1], "uint64", data=ptr, scope="shared")
diff --git a/docs/_sources/tirx/native_basics/cuda/first_kernel.rst.txt b/docs/_sources/tirx/native_basics/cuda/first_kernel.rst.txt
new file mode 100644
index 00000000000..98c926576d7
--- /dev/null
+++ b/docs/_sources/tirx/native_basics/cuda/first_kernel.rst.txt
@@ -0,0 +1,93 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+Your first kernel
+=================
+
+A complete write → compile → run → inspect loop. This kernel scales a vector by 2
+with one block of 256 threads.
+
+.. code-block:: python
+
+ import numpy as np
+ import tvm
+ from tvm.script import tirx as T
+
+ @T.prim_func
+ def scale(A_ptr: T.handle, B_ptr: T.handle):
+ A = T.match_buffer(A_ptr, (256,), "float32")
+ B = T.match_buffer(B_ptr, (256,), "float32")
+
+ T.device_entry() # everything below runs on the device
+ bx = T.cta_id([1]) # 1 block (blockIdx)
+ tx = T.thread_id([256]) # 256 threads per block (threadIdx)
+
+ B[tx] = A[tx] * T.float32(2.0)
+
+ # compile for CUDA through the TIRx pipeline -> an Executable
+ exe = tvm.compile(tvm.IRModule({"main": scale}),
+ target=tvm.target.Target("cuda"), tir_pipeline="tirx")
+
+ dev = tvm.cuda(0)
+ a = tvm.runtime.tensor(np.random.rand(256).astype("float32"), device=dev)
+ b = tvm.runtime.tensor(np.zeros(256, "float32"), device=dev)
+ exe(a, b) # run
+ print(exe.mod.imports[0].inspect_source()) # the generated CUDA C
+
+What the surrounding calls do:
+
+- ``tvm.IRModule({"main": scale})`` wraps the ``PrimFunc`` into an *IRModule* — a
+ named collection of functions; ``"main"`` is the entry point the compiler builds
+ and the symbol you call.
+- ``tvm.compile(mod, target=..., tir_pipeline="tirx")`` returns an **Executable**:
+ the compiled host launcher plus device code, bundled together. You call it like
+ a function (``exe(a, b)``); arguments are positional and match the kernel's
+ parameter order.
+- ``tvm.cuda(0)`` is a handle to CUDA device 0; ``tvm.runtime.tensor(arr,
+ device=dev)`` places data on that device as a TVM tensor (an ``NDArray``).
+- ``exe.mod`` is the underlying runtime ``Module``; ``exe.mod.imports[0]`` is the
+ imported device (CUDA) module, and its ``.inspect_source()`` returns the
+ generated CUDA C.
+
+For this kernel, that last ``print`` produces (boilerplate elided):
+
+.. code-block:: c++
+
+ extern "C" __global__ void __launch_bounds__(256)
+ scale_kernel(float* __restrict__ A_ptr, float* __restrict__ B_ptr) {
+ int tx = ((int)threadIdx.x);
+ B_ptr[tx] = A_ptr[tx] * 2.0f;
+ }
+
+Every thread writes one element — a direct map from ``B[tx] = A[tx] * 2.0`` to the
+generated indexing.
+
+.. note::
+
+ The compiled ``Executable`` also accepts CUDA ``torch`` tensors **directly**
+ (zero-copy, via DLPack) — no conversion step needed:
+
+ .. code-block:: python
+
+ import torch
+ a = torch.rand(256, device="cuda")
+ b = torch.empty(256, device="cuda")
+ exe(a, b)
+ torch.testing.assert_close(b, a * 2)
+
+The following chapters expand each piece: :doc:`functions`, :doc:`buffers`,
+:doc:`control_flow`, :doc:`threads_sync`, and :doc:`compiling`.
diff --git a/docs/_sources/tirx/native_basics/cuda/functions.rst.txt b/docs/_sources/tirx/native_basics/cuda/functions.rst.txt
new file mode 100644
index 00000000000..25d3f7f7344
--- /dev/null
+++ b/docs/_sources/tirx/native_basics/cuda/functions.rst.txt
@@ -0,0 +1,351 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+Defining a function
+===================
+
+A kernel is a ``@T.prim_func`` (like ``scale`` in :doc:`first_kernel`), or a
+``@T.jit`` when it has compile-time parameters (see the last section). This
+chapter covers the parameter list — how to declare buffers, what types you can
+pass, symbolic shapes, and the ``prim_func`` / ``jit`` distinction.
+
+Declaring buffer parameters
+---------------------------
+
+There are two equivalent ways to take a tensor parameter:
+
+- **Handle + match_buffer.** Take a ``T.handle`` (an opaque data pointer) and bind
+ it in the body with ``T.match_buffer``. This is the explicit form and the one
+ that exposes every descriptor field — ``layout``, ``elem_offset``, ``scope``,
+ ``align``, and symbolic shapes:
+
+ .. code-block:: python
+
+ @T.prim_func
+ def f(A_ptr: T.handle, B_ptr: T.handle):
+ A = T.match_buffer(A_ptr, (256,), "float32", align=16)
+ B = T.match_buffer(B_ptr, (256,), "float32")
+ ...
+
+- **T.Buffer annotation.** Annotate the parameter directly. This is the concise
+ form — equivalent to a handle bound with ``match_buffer`` using the defaults:
+
+ .. code-block:: python
+
+ @T.prim_func
+ def f(A: T.Buffer((256,), "float32"), B: T.Buffer((256,), "float32")):
+ ...
+
+Both give you a ``Buffer`` you index with ``A[i]`` / ``A[i, j]``. Use ``T.Buffer``
+for the common case; drop to ``T.handle`` + ``match_buffer`` when you need a custom
+layout/offset/scope/alignment or a :ref:`symbolic shape <symbolic-shapes>`.
+
+What the parameter list accepts
+-------------------------------
+
+A ``PrimFunc`` parameter is one of the following. The third column is what you
+pass on the Python side when you call the compiled ``Executable``:
+
+.. list-table::
+ :header-rows: 1
+ :widths: 30 40 30
+
+ * - Annotation
+ - Is
+ - Pass at call time
+ * - ``T.Buffer((d0, d1), dtype)``
+ - a tensor parameter (shape + dtype fixed)
+ - a tensor on the right device
+ * - ``T.handle``
+ - an opaque data pointer (bind with ``match_buffer``)
+ - a tensor
+ * - ``T.int32`` / ``T.float32`` / …
+ - a runtime scalar
+ - a Python ``int`` / ``float``
+ * - ``T.constexpr`` (``@T.jit`` only)
+ - a compile-time constant
+ - supplied to ``.specialize(...)``, **not** at the call
+
+Tensors may be CUDA ``torch`` tensors (zero-copy via DLPack) or
+``tvm.runtime.tensor(...)``. Arguments are positional and match the parameter
+order. For example, a kernel with a scalar parameter::
+
+ @T.prim_func
+ def scal(A_ptr: T.handle, B_ptr: T.handle, s: T.float32):
+ A = T.match_buffer(A_ptr, (256,), "float32")
+ B = T.match_buffer(B_ptr, (256,), "float32")
+ T.device_entry(); bx = T.cta_id([1]); tx = T.thread_id([256])
+ B[tx] = A[tx] * s
+
+ exe(a, b, 3.0) # pass the scalar as a Python float
+
+.. _symbolic-shapes:
+
+Symbolic shapes
+---------------
+
+For a size that varies at run time, declare a free symbolic extent with
+``T.int32()`` and use it in the buffer shape. Its value is **inferred from the
+passed tensor** at run time, so a *single compiled kernel* handles any size:
+
+.. code-block:: python
+
+ @T.prim_func
+ def scale_dyn(a: T.handle, b: T.handle):
+ n = T.int32() # free symbolic extent
+ A = T.match_buffer(a, (n,), "float32")
+ B = T.match_buffer(b, (n,), "float32")
+ T.device_entry()
+ bx = T.cta_id([1]); tx = T.thread_id([1])
+ for i in range(n): # loop / launch bounds may use n
+ B[i] = A[i] * T.float32(2.0)
+
+ exe = tvm.compile(tvm.IRModule({"main": scale_dyn}),
+ target=tvm.target.Target("cuda"), tir_pipeline="tirx")
+ exe(torch.rand(100, device="cuda"), torch.empty(100, device="cuda")) # n = 100
+ exe(torch.rand(200, device="cuda"), torch.empty(200, device="cuda")) # n = 200, same kernel
+
+Both ``match_buffer`` calls share ``n``, so the two shapes are constrained equal;
+``n`` is never passed explicitly — it comes from the tensor.
+
+In the generated CUDA, ``n`` is just a runtime kernel argument; the host launcher
+reads it from the tensor's shape and passes it, and the loop bound uses it
+(boilerplate elided):
+
+.. code-block:: c++
+
+ extern "C" __global__ void
+ scale_dyn_kernel(float* __restrict__ A_ptr, float* __restrict__ B_ptr, int n) {
+ for (int i = 0; i < n; ++i) {
+ B_ptr[i] = A_ptr[i] * 2.0f;
+ }
+ }
+
+.. note::
+
+ You passed only two tensors, yet the kernel takes a third argument ``n`` — who
+ supplies it? A compiled ``Executable`` has two halves: a **host launcher** and
+ the **device kernel** above. When you call ``exe(a, b)``, the host launcher
+ unpacks the two tensors, reads ``n`` from ``a``'s shape (``a`` was matched as
+ ``(n,)``), checks that ``b`` agrees, computes the launch configuration, and then
+ invokes the device kernel — forwarding the data pointers **and** the resolved
+ ``n`` as explicit arguments. Nothing passes ``n`` by hand; the host side derives
+ it from the tensor metadata. The pass that does this is
+ ``tirx.transform.SplitHostDevice`` (followed by ``tirx.transform.MakePackedAPI``).
+
+You can see it in the IR. **Before** the split, the lowered module is a single
+merged function (trimmed):
+
+.. code-block:: python
+
+ @T.prim_func
+ def main(a: T.handle, b: T.handle):
+ n = T.int32()
+ A = T.match_buffer(a, (n,))
+ B = T.match_buffer(b, (n,))
+ with T.launch_thread("blockIdx.x", 1), T.launch_thread("threadIdx.x", 1):
+ for i in range(n):
+ B[i] = A[i] * T.float32(2.0)
+
+**After** ``SplitHostDevice``, it is two functions — a device kernel that takes
+``n`` as a parameter, and a host ``main`` that calls it, forwarding ``n`` (the
+trailing ``1, 1`` are the grid/block launch dims):
+
+.. code-block:: python
+
+ @T.prim_func # device
+ def scale_dyn_kernel(A_ptr: T.handle("float32"), B_ptr: T.handle("float32"), n: T.int32):
+ ...
+ for i in range(n):
+ B[i] = A[i] * T.float32(2.0)
+
+ @T.prim_func # host
+ def main(a: T.handle, b: T.handle):
+ n = T.int32()
+ A = T.match_buffer(a, (n,))
+ B = T.match_buffer(b, (n,))
+ T.call_packed("scale_dyn_kernel", A.data, B.data, n, 1, 1) # n forwarded
+
+``MakePackedAPI`` then fills in where ``n`` comes from — reading it from the
+argument's shape (essentially ``n = a.shape[0]``) — and adds the dtype / shape /
+device checks (e.g. asserting ``B.shape[0] == n``)::
+
+ n = T.Cast("int32", T.tvm_struct_get(a_shape, 0, 17, "int64")) # = a.shape[0]
+
+``@T.prim_func`` vs ``@T.jit``
+------------------------------
+
+- ``@T.prim_func`` parses the function immediately into a ``PrimFunc``. Sizes are
+ whatever you wrote — concrete ints, or runtime-symbolic vars (above).
+- ``@T.jit`` **defers** parsing until you call ``.specialize(**constexpr)``:
+ parameters annotated ``T.constexpr`` are baked in as compile-time constants and
+ the result is an ordinary ``PrimFunc``. Use it when you want sizes/flags fixed at
+ compile time (so the compiler can unroll, statically size shared memory, etc.).
+ Referencing a constexpr inside an annotation (e.g. ``T.Buffer((N,), ...)``)
+ requires ``from __future__ import annotations`` at the top of the file.
+
+.. code-block:: python
+
+ @T.jit
+ def add(A: T.Buffer((N,), "float32"), B: T.Buffer((N,), "float32"),
+ C: T.Buffer((N,), "float32"), *, N: T.constexpr):
+ T.device_entry(); bx = T.cta_id([1]); tx = T.thread_id([N])
+ C[tx] = A[tx] + B[tx]
+
+ kernel = add.specialize(N=256) # -> a PrimFunc with N = 256 baked in
+
+So: a **symbolic shape** is one kernel whose size is resolved at run time; a
+**constexpr + jit** produces a specialized kernel per value, resolved at compile
+time.
+
+Launch parameters
+-----------------
+
+``T.device_entry()``
+~~~~~~~~~~~~~~~~~~~~~
+
+``T.device_entry()`` is a flat marker (no ``with``) that splits the function:
+everything **before** it is host code — the ``T.match_buffer`` parameter binding
+and any shape reads — and everything **after** it is the **device kernel body**. It
+lowers to an ``AttrStmt("tirx.device_entry", ...)`` and is exactly the boundary the
+host/device split cuts along (the merged-vs-split modules shown above are split
+here).
+
+Scope ids
+~~~~~~~~~
+
+After ``device_entry`` you declare the thread hierarchy with *scope-id* intrinsics
+— each takes its launch extent as a list:
+
+.. code-block:: python
+
+ T.device_entry()
+ bx, by = T.cta_id([GM, GN]) # blockIdx.x / .y (grid extents)
+ warp_id = T.warp_id([4]) # cta -> warp
+ lane_id = T.lane_id([32]) # warp -> thread
+ tx = T.thread_id([128]) # cta -> flat thread id
+
+Available ids include ``cta_id``, ``thread_id``, ``warp_id``, ``warpgroup_id``,
+``warp_id_in_wg``, ``lane_id``, ``cluster_id``, ``cta_id_in_cluster``. (The legacy
+``T.launch_thread`` exists but native TIRx uses ``device_entry`` + scope-ids.)
+
+**Thread-block clusters** (Hopper/Blackwell) are declared with ``cluster_id``
+(kernel → cluster) and ``cta_id_in_cluster`` (cluster → cta). The
+``cta_id_in_cluster`` extent is the cluster's CTA dimension; its ``preferred=``
+argument sets the *preferred* cluster dimension (CUDA 12.8+):
+
+.. code-block:: python
+
+ cid = T.cluster_id([NUM_CLUSTERS]) # kernel -> cluster (grid of clusters)
+ rank = T.cta_id_in_cluster([CLUSTER_SIZE], # cluster -> cta
+ preferred=[CLUSTER_SIZE])
+ # -> cluster_dim = CLUSTER_SIZE, preferred_cluster_dim = CLUSTER_SIZE
+
+These become the ``CLUSTER_DIMENSION`` / ``PREFERRED_CLUSTER_DIMENSION`` launch
+attributes in the config below. (``cta_id`` and ``cta_id_in_cluster`` also take an
+optional ``preferred=``.) In the device code they lower to reads of the cluster
+PTX special registers:
+
+.. code-block:: c++
+
+ int cid = ...; // mov.u32 %0, %clusterid.x; (cluster index)
+ int rank = ...; // mov.u32 %0, %cluster_ctarank; (CTA rank within the cluster)
+
+The cluster *dimensions* themselves are not in the device code — they are set at
+launch time via the attributes above.
+
+Launching the kernel
+~~~~~~~~~~~~~~~~~~~~~
+
+During lowering the compiler **extracts every launch parameter** the kernel uses —
+the grid and block dimensions, plus the dynamic shared-memory size if any — into
+the device function's ``tirx.kernel_launch_params`` attribute. For the ``scale``
+kernel that list is ``["blockIdx.x", "threadIdx.x"]``; the host launcher computes
+each one's extent (from the scope-id extents and any symbolic shapes) and supplies
+them alongside the kernel arguments.
+
+The block size also drives the kernel's ``__launch_bounds__``. The first argument
+(max threads per block) is set automatically from the thread extent. To also set
+the second argument — the minimum blocks per SM, an occupancy hint — add
+``T.attr({"tirx.launch_bounds_min_blocks_per_sm": N})`` in the device region (note:
+``T.attr``, not ``func_attr``):
+
+.. code-block:: python
+
+ T.device_entry()
+ T.attr({"tirx.launch_bounds_min_blocks_per_sm": 2}) # second launch-bounds arg
+ bx = T.cta_id([1]); tx = T.thread_id([256])
+ ...
+
+.. code-block:: c++
+
+ extern "C" __global__ void __launch_bounds__(256, 2) scale_kernel(...) { ... }
+
+Without the attr the second argument is omitted (just ``__launch_bounds__(256)``).
+
+At run time the kernel is launched through the **CUDA Driver API**. TVM's CUDA
+runtime loads the module (``cuModuleLoadData``), fetches the function
+(``cuModuleGetFunction``, cached), and calls ``cuLaunchKernelEx`` with a
+``CUlaunchConfig``. Besides the grid/block dims, dynamic shared size, and stream,
+the config carries a list of launch *attributes* — the thread-block **cluster
+dimension** and **preferred cluster dimension** (Hopper/Blackwell), plus optional
+programmatic-dependent-launch and cooperative-launch flags. From
+``src/backend/cuda/runtime/cuda_module.cc``:
+
+.. code-block:: c++
+
+ std::vector<CUlaunchAttribute> attrs;
+
+ // 1) thread-block cluster dimension
+ if (wl.cluster_dim(0) != 1 || wl.cluster_dim(1) != 1 || wl.cluster_dim(2) != 1) {
+ CUlaunchAttribute attr{};
+ attr.id = CU_LAUNCH_ATTRIBUTE_CLUSTER_DIMENSION;
+ attr.value.clusterDim.x = wl.cluster_dim(0);
+ attr.value.clusterDim.y = wl.cluster_dim(1);
+ attr.value.clusterDim.z = wl.cluster_dim(2);
+ attrs.push_back(attr);
+ }
+ // 1b) preferred cluster dimension (CUDA 12.8+); (2) programmatic stream
+ // serialization and (3) cooperative launch are appended the same way
+ if (wl.preferred_cluster_dim(0) != 1 || wl.preferred_cluster_dim(1) != 1 ||
+ wl.preferred_cluster_dim(2) != 1) {
+ CUlaunchAttribute attr{};
+ attr.id = CU_LAUNCH_ATTRIBUTE_PREFERRED_CLUSTER_DIMENSION;
+ attr.value.clusterDim.x = wl.preferred_cluster_dim(0);
+ attr.value.clusterDim.y = wl.preferred_cluster_dim(1);
+ attr.value.clusterDim.z = wl.preferred_cluster_dim(2);
+ attrs.push_back(attr);
+ }
+
+ CUlaunchConfig config{};
+ config.gridDimX = wl.grid_dim(0);
+ config.gridDimY = wl.grid_dim(1);
+ config.gridDimZ = wl.grid_dim(2);
+ config.blockDimX = wl.block_dim(0);
+ config.blockDimY = wl.block_dim(1);
+ config.blockDimZ = wl.block_dim(2);
+ config.sharedMemBytes = wl.dyn_shmem_size;
+ config.hStream = strm;
+ config.attrs = attrs.empty() ? nullptr : attrs.data();
+ config.numAttrs = static_cast<unsigned int>(attrs.size());
+
+ CUresult result = cuLaunchKernelEx(&config, fcache_[device_id], void_args, nullptr);
+
+Here ``wl`` is the resolved workload (the grid/block/cluster extents derived from
+the launch parameters), ``fcache_[device_id]`` is the cached ``CUfunction``, and
+``void_args`` are the kernel arguments — the data pointers plus scalars like the
+symbolic ``n``.
diff --git a/docs/_sources/tirx/native_basics/cuda/parser_utils.rst.txt b/docs/_sources/tirx/native_basics/cuda/parser_utils.rst.txt
new file mode 100644
index 00000000000..b203797c37d
--- /dev/null
+++ b/docs/_sources/tirx/native_basics/cuda/parser_utils.rst.txt
@@ -0,0 +1,80 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+Parser utilities
+================
+
+A few helpers act at **parse time** (when TVMScript is turned into TIRx), letting
+you inline Python-computed values, factor out reusable fragments, and bundle
+parser-side state.
+
+``T.meta_var`` — inline a Python value
+--------------------------------------
+
+``T.meta_var(x)`` tells the parser to treat ``x`` — a value computed in **Python** —
+as a compile-time *meta* value and inline it directly into the IR, rather than
+parse it as a script variable. It avoids a throwaway local, and it drives
+metaprogramming: a plain Python ``for`` over a meta value unrolls in the parser.
+
+.. code-block:: python
+
+ n = T.meta_var(4) # n is a Python int, inlined
+ for j in range(n): # unrolled at parse time
+ acc[0] = acc[0] + A[tx, j]
+
+``@T.inline`` — inline functions
+--------------------------------
+
+``@T.inline`` defines a function whose body is **inlined at each call site** during
+parsing — no call appears in the generated code. It follows Python's lexical (LEGB)
+scoping with late binding, so a parameter shadows an enclosing variable:
+
+.. code-block:: python
+
+ @T.inline
+ def add_into(acc, x):
+ acc[0] = acc[0] + x
+
+ add_into(s.acc, A[tx, j]) # inlined -> s.acc[0] = s.acc[0] + A[tx, j]
+
+``@T.meta_class`` — parser-side state objects
+---------------------------------------------
+
+``@T.meta_class`` marks a plain Python class whose **instances are parser meta
+values**: their fields can hold buffers and scalars, so you can bundle related
+allocations and state into one object and use it in the kernel body.
+
+.. code-block:: python
+
+ @T.meta_class
+ class State:
+ def __init__(self, smem):
+ self.acc = T.alloc_local([1], "float32")
+ self.buf = T.decl_buffer([64], "float16", smem, scope="shared.dyn")
+
+ s = State(smem.data)
+ s.acc[0] = T.float32(0.0) # use its fields like ordinary buffers
+ # ... s.buf[i] ...
+
+This is handy for grouping a kernel's pipeline state (barriers, accumulators,
+scratch views) instead of threading many separate locals through the body.
+
+``T.constexpr``
+---------------
+
+``T.constexpr`` marks a compile-time kernel parameter, baked in by ``@T.jit``'s
+``.specialize(...)``. See :doc:`functions` for the details.
diff --git a/docs/_sources/tirx/native_basics/cuda/threads_sync.rst.txt b/docs/_sources/tirx/native_basics/cuda/threads_sync.rst.txt
new file mode 100644
index 00000000000..09a99050221
--- /dev/null
+++ b/docs/_sources/tirx/native_basics/cuda/threads_sync.rst.txt
@@ -0,0 +1,95 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+CUDA C++/PTX intrinsics
+=======================
+
+When no tile primitive covers what you need, two escape hatches reach the hardware
+directly: **call a backend intrinsic** (the ``T.cuda.*`` / ``T.ptx.*`` namespaces
+from ``tvm.backend.cuda``), or **inline raw CUDA** source.
+
+Calling backend intrinsics
+--------------------------
+
+``T.cuda.*`` and ``T.ptx.*`` expose the CUDA backend's device intrinsics directly —
+synchronization, mbarriers, reductions, and the PTX data-movement / MMA families:
+
+.. code-block:: python
+
+ T.cuda.cta_sync() # block barrier (__syncthreads)
+ T.cuda.warp_sync() # __syncwarp
+ T.cuda.warpgroup_sync(8) # warpgroup barrier
+ T.cuda.cta_sum(val, num_warps, scratch.ptr_to([0])) # block-level reduction
+
+ bar = T.alloc_shared((1,), "uint64")
+ T.ptx.mbarrier.init(bar.data, 1) # mbarrier for async completion
+ T.ptx.mbarrier.try_wait(bar.data, phase)
+
+A complete, runnable example — a warp all-reduce via ``T.tvm_warp_shuffle_xor``:
+
+.. code-block:: python
+
+ @T.prim_func
+ def warp_reduce(A_ptr: T.handle):
+ A = T.match_buffer(A_ptr, (32,), "float32", align=16)
+ T.device_entry()
+ cta_id = T.cta_id([1]); warp_id = T.warp_id([1]); lane_id = T.lane_id([32])
+ v = T.alloc_local((1,), "float32"); i = T.alloc_local((1,), "int32")
+ v[0] = T.float32(31 - lane_id)
+ i[0] = 16
+ while i[0] >= 1:
+ v[0] += T.tvm_warp_shuffle_xor(0xFFFFFFFF, v[0], i[0], 32, 32)
+ i[0] = i[0] // 2
+ A[lane_id] = v[0]
+
+The shuffle lowers straight to ``__shfl_xor_sync``:
+
+.. code-block:: c++
+
+ v_ptr[0] = v_ptr[0] + __shfl_xor_sync(0xFFFFFFFF, v_ptr[0], i_ptr[0], 32);
+
+Other families under ``T.ptx.*`` / ``T.cuda.*``: ``cp_async`` (LDGSTS),
+``cp_async.bulk.tensor`` (TMA), ``ldmatrix`` / ``stmatrix``, ``tcgen05.*``
+(Blackwell MMA), ``atomic_add``, ``fence`` … See :doc:`../../api/backend` for the
+full ``tvm.backend.cuda`` reference.
+
+Inlining raw CUDA
+-----------------
+
+For something with no intrinsic at all, inject a ``__device__`` function from a
+source string with ``T.cuda.func_call(name, *args, source_code=..., return_type=...)``:
+
+.. code-block:: python
+
+ SRC = r"""
+ __device__ __forceinline__ float my_relu(float x) { return x > 0.f ? x : 0.f; }
+ """
+
+ @T.prim_func
+ def k(A_ptr: T.handle, B_ptr: T.handle):
+ A = T.match_buffer(A_ptr, (256,), "float32")
+ B = T.match_buffer(B_ptr, (256,), "float32")
+ T.device_entry(); bx = T.cta_id([1]); tx = T.thread_id([256])
+ B[tx] = T.cuda.func_call("my_relu", A[tx], source_code=SRC, return_type="float32")
+
+The source is emitted verbatim and the call is wired in:
+
+.. code-block:: c++
+
+ __device__ __forceinline__ float my_relu(float x) { return x > 0.f ? x : 0.f; }
+ // ...
+ B_ptr[tx] = my_relu(A_ptr[tx]);
diff --git a/docs/_sources/tirx/overview.rst.txt b/docs/_sources/tirx/overview.rst.txt
new file mode 100644
index 00000000000..f53265fed4f
--- /dev/null
+++ b/docs/_sources/tirx/overview.rst.txt
@@ -0,0 +1,196 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+Overview
+========
+
+TIRx (pronounced *"tier-ex"*) is an open-source, hardware-native DSL and compiler
+for machine-learning kernels. It targets the part of the AI software stack
+where fast-moving kernels meet fast-moving hardware: TIRx compiles to GPUs and
+specialized AI accelerators today and is designed to grow with the hardware
+generations that follow. The same design makes it a substrate not only for
+expert-written kernels, but also for agent-generated kernels and megakernel
+systems.
+
+TIRx is the next-generation kernel-level compiler structure of Apache TVM, and
+is built on top of the TVM compiler infrastructure.
+
+.. figure:: https://raw.githubusercontent.com/tlc-pack/web-data/main/images/tirx/tirx_overview_hero.png
+ :align: center
+ :alt: A TIRx kernel keeps orchestration in hardware-native source while exposing tile
+ structure to the compiler; agentic, megakernel, and new-backend systems
+ build on the same structure.
+
+ A TIRx kernel keeps orchestration — pipeline state, roles, synchronization,
+ and backend intrinsics — in hardware-native source, while execution scope,
+ tensor layout, and tile primitive dispatch expose the recurring tile
+ structure to the compiler. Higher-level systems build on the same structure.
+
+Design Philosophy
+-----------------
+
+Kernel DSLs are most effective when they choose the right boundary between the
+programmer and the machine. For mature kernels on mature hardware, that boundary
+can be high-level: the compiler hides thread assignment, memory movement, layout
+details, and instruction selection behind compact tensor or tile abstractions,
+and this works well for established kernel patterns.
+
+At the frontier, the same boundary is under more pressure. New instructions,
+memory spaces, cooperation patterns, and kernel algorithms often appear *before*
+a compiler has enough built-in machinery to automate them well.
+
+TIRx chooses a **lower and more explicit boundary**. It keeps the parts of a
+kernel that frequently require expert control — pipeline structure,
+synchronization, role assignment, memory placement, and backend intrinsics — in
+hardware-native source code. At the same time, it exposes the recurring tile-level
+structure to the compiler through three constructs: *execution scope*, *tensor
+layout*, and *tile primitive dispatch*. Orchestration stays in hardware-native
+source code, while the recurring tile-level structure becomes visible to the
+compiler. Hardware-native control is powerful but costs engineering effort;
+exposing recurring operations as tile primitives relieves this, since authors
+reuse a dispatched implementation instead of re-writing the same operation for
+each kernel and backend.
+
+The result is a DSL that can **grow with the hardware**. A new feature can first
+be used directly as a native intrinsic, and later become a reusable primitive
+once the pattern stabilizes. This is the core design philosophy behind TIRx:
+keep the foundation small and explicit, and let the backend library evolve as
+new accelerator generations arrive.
+
+The Programming Model
+---------------------
+
+A TIRx program reads as a structured native kernel: loops, branches, buffers,
+synchronization, pipeline state, backend intrinsics, and hardware roles are
+written directly. Tile primitives appear exactly where a repeated hardware-level
+operation should become reusable and dispatchable.
+
+The model has three core ingredients.
+
+Execution scope
+~~~~~~~~~~~~~~~~~
+
+Execution scope describes both the active participants and the logical scope of
+a primitive invocation. Control flow such as ``if wg_id == ...``,
+``warp_id == ...``, or ``cbx == ...`` selects which hardware roles enter a
+region, while predicates such as ``T.ptx.elect_sync()`` further select the
+issuing thread.
+
+The primitive namespace is also part of the scope. For example, ``Tx.wg.*``
+denotes warpgroup-level primitives, while an unqualified ``Tx.*`` call defaults
+to thread-level invocation.
+
+Tensor layout
+~~~~~~~~~~~~~~
+
+Tensor layout, with a storage-first interface, describes how logical
+tensors map to physical resources. A tile may live in global memory, shared
+memory, registers, tensor memory, or accelerator SRAM.
+Users declare where each tile lives and how its elements are spread across
+lanes, warps, and registers; tile primitive dispatch reads those declarations to
+choose an implementation. A layout is a storage description, not a
+loop-transformation utility: users may construct a tile's layout, but never use
+layouts to transform loops.
+
+.. seealso::
+
+ The layout model — including the shard / replica / offset structure and its
+ design rationale — is described in :doc:`layout`, which also has an
+ interactive explorer.
+
+Tile primitive dispatch
+~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Tile primitive dispatch selects an implementation according to the primitive,
+the current execution scope, the operand layouts, and the target backend. For
+example:
+
+- A ``copy`` primitive may dispatch to TMA, vectorized loads/stores,
+ tensor-memory movement, accelerator DMA, or another backend-specific
+ implementation.
+- A matrix-multiply primitive may dispatch to WGMMA, ``tcgen05``, a
+ systolic-array instruction, or a backend-specific matmul engine.
+
+Once a variant is selected, dispatch generates the loops and addressing to
+apply that instruction across the whole tile.
+
+Putting it together
+~~~~~~~~~~~~~~~~~~~~~
+
+Across a full kernel, orchestration stays in ordinary source code, and the
+recurring hardware operations appear as tile primitives. For the building blocks —
+TMA loads, ``tcgen05`` async MMA, reductions, and the rest — see the per-dispatch
+walkthroughs in :doc:`tile_primitives`.
+
+What TIRx Enables
+-----------------
+
+TIRx is immediately useful as a kernel DSL. The same structure also helps with
+three things that are becoming important for ML systems: supporting new
+hardware, building megakernels, and agentic kernel programming.
+
+A stable extension boundary for future hardware
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+New hardware support is a staged process rather than a redesign of the DSL: a
+feature is first exposed as a backend intrinsic, then promoted into a tile
+primitive once the usage pattern repeats. Future hardware grows the backend
+library, not the core language.
+
+Megakernels and composable tile tasks
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Because TIRx tasks exist as compiler IR rather than separately compiled kernels,
+a megakernel compiler can stitch and schedule them directly — re-offsetting
+shared memory, renaming barriers, reassigning warp roles, and interleaving
+pipelines across tasks.
+
+.. figure:: https://raw.githubusercontent.com/tlc-pack/web-data/main/images/tirx/tirx_megakernel.png
+ :align: center
+ :alt: Kernel-by-kernel and CUDA-graph execution leave kernel boundaries
+ between tasks, while a megakernel fuses tasks into one kernel with
+ fine-grained dependencies and in-kernel scheduling.
+
+ From kernel-by-kernel launches to a single megakernel: fusing tasks into one
+ kernel exposes fine-grained dependencies and in-kernel (static or dynamic)
+ scheduling.
+
+Agentic kernel programming
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+TIRx exposes its IR and compiler utilities through TVM FFI across Python, C++,
+and Rust, and offers a structured search space with dense, pre-benchmark
+feedback (well-formedness, synchronization validity, race-freedom, value
+simulation).
+
+.. figure:: https://raw.githubusercontent.com/tlc-pack/web-data/main/images/tirx/tirx_agentic.webp
+ :align: center
+ :alt: Agent-visible compiler infrastructure exposes TIRx IR and utilities via
+ TVM FFI across Python, Rust, and C++, over a structured search space
+ spanning levels L1 to L4.
+
+ Agent-visible compiler infrastructure (IR and utilities over TVM FFI) plus a
+ structured search space (levels L1–L4) make TIRx a compiler-mediated
+ optimization surface for agents.
+
+Next Steps
+----------
+
+- :doc:`install` — install TIRx and the kernel library.
+- :doc:`layout` — the tensor layout model with an interactive explorer.
+- :doc:`arch/index` — compiler internals (lowering pipeline, passes, codegen).
+- :doc:`api/index` — the ``tvm.tirx`` Python API.
diff --git a/docs/_sources/tirx/tile_primitives.rst.txt b/docs/_sources/tirx/tile_primitives.rst.txt
new file mode 100644
index 00000000000..acf5330ec53
--- /dev/null
+++ b/docs/_sources/tirx/tile_primitives.rst.txt
@@ -0,0 +1,297 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+Tile Primitives
+===============
+
+.. note::
+
+ This page documents the tile-primitive surface and dispatch as it exists in
+ the source today; signatures and variants may change.
+
+Tile primitives are the dispatchable, hardware-level operations a TIRx kernel
+issues — data movement (``copy``, ``copy_async``), matrix multiply (``gemm``,
+``gemm_async``), reductions, elementwise math, and a few fused/compose forms.
+A primitive call is recorded as an **unresolved** ``TilePrimitiveCall`` IR node;
+the compiler later *dispatches* it — selecting a concrete lowering from the
+primitive, the execution scope, the operand layouts, the target, and an optional
+explicit hint — and replaces it with native IR (loops, address arithmetic,
+synchronization, and backend intrinsics).
+
+Calling convention
+------------------
+
+Tile primitives are called in TVMScript via ``from tvm.script import tirx as T``,
+on the injected ``Tx`` namespace. The namespace prefix selects the **cooperation
+scope**:
+
+- ``Tx.<name>(...)`` — unqualified, runs at **thread** scope.
+- ``Tx.warp.<name>`` / ``Tx.wg.<name>`` (alias ``Tx.warpgroup``) / ``Tx.cta.<name>``
+ / ``Tx.cluster.<name>`` / ``Tx.thread.<name>`` — bind a wider scope.
+
+Every primitive also accepts, besides its operands: ``scope`` (usually set by the
+namespace), ``workspace: dict[str, Buffer] | None``, ``dispatch: str | None``
+(force a named lowering variant), and ``**kwargs`` collected into a ``config``
+dict that tunes the chosen lowering. Operands are ``Buffer`` / ``BufferRegion``
+values, each carrying a :doc:`TileLayout <layout>` that dispatch reads.
+
+Wiring (three layers): the authoritative op list is the C++ registry
+(``src/tirx/op/tirx.cc``, 29 ops named ``tirx.tile.<name>``); the IR wrapper
+classes are in ``python/tvm/tirx/operator/tile_primitive/ops.py``; the
+user-facing ``Tx.*`` builders are in ``python/tvm/tirx/script/builder/tirx.py``.
+
+Primitive catalog
+-----------------
+
+The 29 primitives, grouped. Signatures show the operands plus the common
+``workspace``/``dispatch``/``scope``/``**kwargs`` tail (abbreviated ``...``).
+
+Data movement
+~~~~~~~~~~~~~~
+
+::
+
+ copy(dst, src, ...) # synchronous element copy src -> dst
+ copy_async(dst, src, ...) # asynchronous copy (caller commits/waits)
+ permute_layout(dst, src, ...) # rearrange under a different layout (may alias)
+
+Matrix multiply
+~~~~~~~~~~~~~~~~
+
+::
+
+ gemm(D, A, B, C, transpose_A=False, transpose_B=False,
+ alpha=1.0, beta=0.0, ...) # D = alpha*A*B + beta*C (register mma)
+ gemm_async(C, A, B, SFA=None, SFB=None,
+ transA=False, transB=False, accum=False, ...) # async / block-scaled
+
+Fill / memset / zero
+~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+ fill(dst, value, ...) # fill region with a scalar
+ memset(dst, value, ...) # set all elements to a value
+ zero(dst, src=None, ...) # zero out (in place if src omitted)
+
+Cast and elementwise
+~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+ cast(dst, src=None, ...) # dtype cast (buffer form)
+ sqrt / exp / exp2(dst, src=None, bias=None, scale=None, ...)
+ reciprocal(dst, src=None, ...) # dst = 1/src
+ silu(dst, src, ...) # dst = src*sigmoid(src)
+ add / sub / mul / fdiv(dst, src1, src2, ...) # element-wise arithmetic
+ maximum / minimum(dst, src1, src2, ...) # element-wise max / min
+ fma(dst, src, scale, bias, ...) # dst = src*scale + bias
+ select(dst, true_value, false_value, pred, scope=None) # dst = pred ? t : f
+
+Reductions
+~~~~~~~~~~
+
+::
+
+ sum / max / min(dst, src, axes=-1, accum=False, ...) # reduce over axes
+
+Fused / compose
+~~~~~~~~~~~~~~~~
+
+::
+
+ binary_reduce(...) # binary op then reduce, fused
+ unary_reduce(...) # unary (with bias/scale) then reduce
+ binary_chain(...) # chain two binary ops
+ reduce_negate(...) # reduce then negate
+ compose_op(...) # frame/context manager to group primitives
+
+Dispatch config
+---------------
+
+A call is materialized as a ``TilePrimitiveCall`` node whose fields carry
+everything dispatch needs (``python/tvm/tirx/stmt.py``):
+
+.. list-table::
+ :header-rows: 1
+ :widths: 14 22 64
+
+ * - Field
+ - Type
+ - Meaning
+ * - ``op``
+ - ``tvm.Op``
+ - primitive identity, e.g. ``tirx.tile.copy_async``
+ * - ``args``
+ - ``Array``
+ - operands (regions / scalars), in the order shown above
+ * - ``workspace``
+ - ``Map[str, Buffer]``
+ - pre-allocated scratch buffers
+ * - ``config``
+ - ``Map[str, Any]``
+ - open-ended tuning bag (table below)
+ * - ``dispatch``
+ - ``Optional[str]``
+ - forced variant name; ``None`` = auto-select
+ * - ``scope``
+ - ``ExecScope``
+ - cooperation scope (default ``thread``)
+
+``config`` has **no central schema** — each key is read only by the dispatch
+variant(s) that need it (via ``config.get(...)``); a key meant for another
+primitive is simply ignored. Only ``dispatch`` is generic. The keys observed in
+the CUDA backend, by consumer:
+
+.. list-table::
+ :header-rows: 1
+ :widths: 18 30 18 34
+
+ * - Key
+ - Used by
+ - Type / values
+ - Meaning
+ * - ``dispatch``
+ - any primitive
+ - variant name (str)
+ - force a lowering variant (also settable via the ``dispatch=`` kwarg)
+ * - ``vec_len``
+ - ``copy`` / ``copy_async`` (vectorized variants)
+ - int | None
+ - vectorization width for the copy
+ * - ``mbar``
+ - ``copy_async``: ``tma`` (g2s), ``dsmem``
+ - mbarrier handle
+ - completion barrier
+ * - ``cta_group``
+ - ``copy_async``: ``tma``, ``smem→tmem``; ``gemm_async``: ``tcgen05``
+ - ``1`` | ``2``
+ - CTA-group; ``2`` routes completion to the cluster
+ * - ``cta_mask``
+ - ``copy_async``: ``tma`` (g2s)
+ - int | None
+ - multicast CTA mask
+ * - ``cache_hint``
+ - ``copy_async``: ``tma``
+ - ``"evict_normal"`` | ``""``
+ - L2 cache eviction hint
+ * - ``oob``
+ - ``copy_async``: ``tma``
+ - ``"zero"`` | ``"nan"`` | None
+ - out-of-bounds fill policy (``nan`` is float-only)
+ * - ``use_tma_reduce``
+ - ``copy_async``: ``tma`` (s2g)
+ - str (e.g. ``"add"``) | None
+ - TMA store-with-reduction mode
+ * - ``prefetch_tensormap``
+ - ``copy_async``: ``tma``
+ - bool
+ - prefetch the tensor map at kernel entry
+ * - ``remote_cta_id``
+ - ``copy_async``: ``dsmem``
+ - int | PrimExpr
+ - target CTA for a cross-CTA shared→shared copy
+ * - ``descI``
+ - ``gemm_async``: ``tcgen05``
+ - uint32 | None
+ - pre-encoded MMA instruction descriptor
+ * - ``thread_reduce``
+ - ``reduction``: ``local`` (warp scope)
+ - bool
+ - per-thread shuffle reduction
+ * - ``rounding_mode``
+ - ``elementwise``: binary ops
+ - ``"rn"`` | ``"rz"`` | ...
+ - FP rounding mode for the packed form
+
+Three dispatch inputs are **implicit**, not config keys: the **execution scope**
+(set by the namespace, then refined against the active thread set tracked through
+control flow into ``inter``/``intra`` maps and a ``scope_kind``), the **operand
+layouts** (each ``Buffer.layout``), and the **target** (the dispatch table is
+keyed by its kind, e.g. ``"cuda"``).
+
+Dispatch mechanism
+------------------
+
+Pipeline
+~~~~~~~~
+
+Dispatch runs in the ``tirx.TilePrimitiveDispatch`` pass — the sole pass inside
+``LowerTIRx()``, the first stage of the compile pipeline. The C++ mutator
+``TilePrimitiveDispatcher`` walks the IR and, per call:
+
+#. resolves the ``(inter, intra)`` execution split for the call's scope from the
+ active set tracked through control flow (``if wg_id == ...``, ``warp_id``,
+ ``T.ptx.elect_sync()``);
+#. builds a ``DispatchContext`` carrying ``target``, scope, launch params, value
+ ranges, and the encoded ``inter``/``intra`` + ``scope_kind``;
+#. invokes the global FFI hook ``tirx.f_op_dispatcher`` (Python) with the call
+ and context, which returns a ``PrimFunc``;
+#. splices that ``PrimFunc`` body in place of the call and drains side-effect
+ callbacks (private allocs, device/host init statements).
+
+If any ``TilePrimitiveCall`` survives lowering, a verifier makes it a fatal error.
+
+Selection (``run_dispatch``)
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The Python dispatcher holds a table ``_DISPATCH_TABLE`` keyed by
+``(Op, target_kind)``. Each entry is a list of *cases*, registered by backends
+via ``@register_dispatch(op_name, target_kind, variant=..., priority=...,
+when=[preds])``. ``run_dispatch(op_call, sctx)``:
+
+#. ``key = (op_call.op, sctx.target.kind.name)``; look up cases. None → error.
+#. If ``op_call.dispatch`` is set, **filter** to that variant (error if unknown).
+#. Sort cases by ``(-priority, variant)`` — highest priority first.
+#. For each case, evaluate its predicates; if any fails, record the reason and
+ continue. If all pass, run the impl; on success return its ``PrimFunc``.
+#. An impl may still **decline** by raising ``DispatchFail`` (e.g. a hardware
+ constraint found while emitting) — the search continues.
+#. If every variant is rejected, raise a ``RuntimeError`` listing each variant's
+ rejection reason.
+
+So dispatch is **keyed by (primitive, target)**, then a **priority-ordered,
+predicate-guarded** case list, with an optional ``dispatch=`` override.
+
+Two recurring predicate helpers: ``validate_copy_op`` (both operands have a
+layout, equal dtype, equal non-unit extents) and ``_all_threads_active`` (the
+exec scope is full — ``laneid`` spans 32, etc., none of it narrowed by an
+enclosing ``if``), so a partial-warp copy is rejected rather than mis-lowered.
+
+Dispatch by primitive
+---------------------
+
+Each page below documents one primitive's dispatch in detail — the variants, how
+each is selected, the algorithm it runs, the IR it emits, and when it declines.
+
+.. toctree::
+ :maxdepth: 1
+
+ tile_primitives/copy
+ tile_primitives/copy_async
+ tile_primitives/gemm
+ tile_primitives/gemm_async
+ tile_primitives/elementwise
+ tile_primitives/reduction
+ tile_primitives/permute_layout
+
+See also
+--------
+
+- :doc:`layout` — the ``TileLayout`` model dispatch reads from operands.
+- :doc:`overview` — execution scope, tensor layout, and tile primitive dispatch
+ as the three core constructs.
diff --git a/docs/_sources/tirx/tile_primitives/copy.rst.txt b/docs/_sources/tirx/tile_primitives/copy.rst.txt
new file mode 100644
index 00000000000..a544300bf80
--- /dev/null
+++ b/docs/_sources/tirx/tile_primitives/copy.rst.txt
@@ -0,0 +1,57 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+copy
+====
+
+Synchronous element copy ``src → dst`` between global, shared, and register
+(``local``) memory. Four CUDA variants are registered. ``gmem_smem`` (global ↔
+shared) and the two register variants take disjoint memory-scope pairs; ``reg`` and
+``ldstmatrix`` both cover ``register ↔ shared``, where ``ldstmatrix`` is tried first
+and **declines to** ``reg`` unless the layouts are ldmatrix fragments. All three are
+priority 10; the scalar ``fallback`` (priority 0) runs only if they all decline.
+
+.. list-table::
+ :header-rows: 1
+ :widths: 22 14 64
+
+ * - Variant
+ - Pair
+ - Lowering
+ * - :doc:`copy/gmem_smem`
+ - global ↔ shared
+ - synthesized ``[outer, threads, vec]`` partition, vectorized ``copy_Nb``
+ * - :doc:`copy/reg`
+ - register ↔ shared/global
+ - partition induced by the register layout's thread axes
+ * - :doc:`copy/ldstmatrix`
+ - register ↔ shared
+ - warp-collective ``ldmatrix`` / ``stmatrix`` (m8n8 fragments)
+ * - :doc:`copy/fallback`
+ - any
+ - scalar single-thread copy (priority 0, catch-all)
+
+Each variant has its own deep walkthrough — accepted input, algorithm, a runnable
+demo program, the dispatch's TIRx IR, and the generated CUDA:
+
+.. toctree::
+ :maxdepth: 1
+
+ copy/gmem_smem
+ copy/reg
+ copy/ldstmatrix
+ copy/fallback
diff --git a/docs/_sources/tirx/tile_primitives/copy/fallback.rst.txt b/docs/_sources/tirx/tile_primitives/copy/fallback.rst.txt
new file mode 100644
index 00000000000..7e78c87bfd2
--- /dev/null
+++ b/docs/_sources/tirx/tile_primitives/copy/fallback.rst.txt
@@ -0,0 +1,158 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+copy → fallback
+===============
+
+The ``fallback`` variant is the **priority-0 catch-all**: a scalar, single-thread
+copy that runs only when every faster variant (:doc:`gmem_smem`, :doc:`reg`,
+:doc:`ldstmatrix`) has declined. It always works — for any valid copy at any scope
+— and is intentionally slow, so it emits a ``UserWarning`` when chosen. Source:
+``python/tvm/backend/cuda/operator/tile_primitive/copy/fallback.py``.
+
+What it accepts
+---------------
+
+Any valid copy. The only gate is ``_is_valid_copy`` (layouts present, equal dtype,
+equal non-unit extents); there is no scope, pair, or divisibility restriction. It is
+registered at ``priority=0`` so it is the last candidate the dispatcher tries:
+
+.. list-table::
+ :header-rows: 1
+ :widths: 22 78
+
+ * - Property
+ - Requirement
+ * - priority
+ - ``0`` — only reached after all priority-10 variants ``fail`` / decline
+ * - target / scope
+ - any (``thread`` / ``warp`` / ``warpgroup`` / ``cta``)
+ * - memory pair
+ - any (global / shared / local, either direction)
+ * - dtype / shape
+ - ``_is_valid_copy`` only — equal dtype and equal non-unit extents
+
+A typical reason the fast variants all decline: the region's element count does not
+divide the thread count, so the ``[outer, threads, vec]`` split has no solution
+(``gmem_smem`` declines), and neither side is a register layout (``reg`` /
+``ldstmatrix`` decline). Example: a warp (32 threads) copying a ``4×6 = 24``-element
+tile (``24 ∤ 32``).
+
+Demonstration program
+----------------------
+
+A warp copies a ``4×6`` ``float32`` tile global → shared and back. ``24`` is not
+divisible by ``32``, so this falls through to ``fallback`` (from
+``test_fallback.py``):
+
+.. code-block:: python
+
+ shape, dtype = (4, 6), "float32" # 24 elements, 32 threads -> 24 ∤ 32
+ s_layout = TileLayout(S[shape])
+ full = (slice(0, 4), slice(0, 6))
+
+ @T.prim_func
+ def kernel(A_ptr: T.handle, B_ptr: T.handle):
+ A = T.match_buffer(A_ptr, shape, dtype)
+ B = T.match_buffer(B_ptr, shape, dtype)
+ T.device_entry(); T.cta_id([1]); T.lane_id([32]); T.thread_id([32])
+ A_smem = T.alloc_buffer(shape, dtype, scope="shared", layout=s_layout)
+ Tx.warp.copy(A_smem[full], A[full]) # fallback
+ T.cuda.cta_sync()
+ Tx.warp.copy(B[full], A_smem[full]) # fallback
+
+Algorithm
+---------
+
+**1. Elect one thread.** For a multi-thread scope the copy is done entirely by the
+**first thread of the scope** — its ``laneid`` base, plus the warp offset within a
+warpgroup / cta (radix-32 composition of the per-axis offsets); every other thread
+skips it. For ``thread`` scope there is only one thread, so no guard is emitted:
+
+.. code-block:: python
+
+ if scope_kind == "thread":
+ def impl():
+ _copy_body(dst, src) # the single thread copies everything
+ else:
+ first_tid = int(sctx.intra["laneid"][1]) # first thread of the scope:
+ if scope_kind == "warpgroup":
+ first_tid += 32 * int(sctx.intra["wid_in_wg"][1]) # + warp offset within the wg
+ elif scope_kind == "cta":
+ first_tid += 32 * int(sctx.intra["warpid"][1]) # + warp offset within the cta
+ def impl():
+ tid = _axis_decl(tid_axis_name, sctx)
+ if tid == first_tid: # only the scope's first thread copies
+ _copy_body(dst, src)
+
+**2. Scalar nested loop over the region.** ``_copy_body`` iterates the non-unit
+extents with ``T.grid`` and copies one element per step — no vectorization, no
+partition:
+
+.. code-block:: python
+
+ with T.grid(*copy_extents) as lvs: # copy_extents = non-unit dst extents
+ dst[_dst_coord(lvs)] = src[_src_coord(lvs)]
+
+Generated TIRx IR
+-----------------
+
+``LowerTIRx`` produces the guarded scalar grid (global → shared shown):
+
+.. code-block:: python
+
+ if tid == 0: # first_tid (lane 0 for this warp scope)
+ for v_3, v_4 in T.grid(4, 6):
+ A_smem[v_3, v_4] = A[v_3, v_4]
+
+Generated CUDA
+--------------
+
+.. code-block:: c++
+
+ __shared__ alignas(64) float A_smem_ptr[24];
+ if (((int)threadIdx.x) == 0) { // lane 0 does the whole copy
+ for (int v_3 = 0; v_3 < 4; ++v_3)
+ for (int v_4 = 0; v_4 < 6; ++v_4)
+ A_smem_ptr[(v_3 * 6) + v_4] = A_ptr[(v_3 * 6) + v_4];
+ }
+
+Lane 0 copies all 24 elements one at a time; the other 31 lanes do nothing. (At
+lowering the dispatch also prints ``UserWarning: copy/fallback (scalar
+single-thread) picked … all faster variants rejected``.)
+
+How inputs change the algorithm
+-------------------------------
+
+The **scope** decides who runs the loop:
+
+.. list-table::
+ :header-rows: 1
+ :widths: 30 70
+
+ * - scope
+ - who copies
+ * - ``thread``
+ - the single thread, no ``if`` guard
+ * - ``warp`` / ``warpgroup`` / ``cta``
+ - only ``first_tid`` (the scope's first thread = lane base + warp offset); all
+ other threads skip
+
+The **shape** sets the ``T.grid`` bounds (the non-unit extents); the loop body is
+always one scalar element copy, regardless of dtype. There is no vectorization, so
+performance does not depend on dtype width — this variant exists for correctness,
+not speed.
diff --git a/docs/_sources/tirx/tile_primitives/copy/gmem_smem.rst.txt b/docs/_sources/tirx/tile_primitives/copy/gmem_smem.rst.txt
new file mode 100644
index 00000000000..d34578a9951
--- /dev/null
+++ b/docs/_sources/tirx/tile_primitives/copy/gmem_smem.rst.txt
@@ -0,0 +1,209 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+copy → gmem_smem
+================
+
+The ``gmem_smem`` variant lowers a synchronous ``copy`` between **global and
+shared** memory (either direction) when **neither side is a register**. Because
+neither operand carries a thread partition, the dispatch *synthesizes* one from the
+execution scope: it splits the region into ``[outer, threads, vec]`` and emits a
+serial loop of vectorized loads/stores. Source:
+``python/tvm/backend/cuda/operator/tile_primitive/copy/gmem_smem.py``.
+
+What it accepts
+---------------
+
+The predicate ``_is_gmem_smem`` gates the variant:
+
+.. code-block:: python
+
+ def _is_gmem_smem(op_call, sctx):
+ if not sctx.is_target("cuda"):
+ return False, "non-cuda target"
+ if sctx.scope_kind not in ("thread", "warp", "warpgroup", "cta"):
+ return False, f"unsupported exec_scope {sctx.scope_kind}"
+ for check in (
+ lambda: _all_threads_active(sctx), # full scope, no narrowing
+ lambda: _is_valid_copy(op_call, sctx), # layouts, equal dtype/extents
+ lambda: _scope_allowed(op_call, sctx, allowed_pairs=_GMEM_SMEM_PAIRS),
+ lambda: _divides_thread_cnt(op_call, sctx),
+ ):
+ ok, msg = check()
+ if not ok:
+ return False, msg
+ return True, None
+
+So the accepted input is:
+
+.. list-table::
+ :header-rows: 1
+ :widths: 22 78
+
+ * - Property
+ - Requirement
+ * - target
+ - ``cuda``
+ * - scope
+ - ``thread`` / ``warp`` / ``warpgroup`` / ``cta``, and **all threads active**
+ (``_all_threads_active`` — ``laneid`` spans 32, etc., none narrowed by an
+ enclosing ``if``)
+ * - memory pair
+ - ``(global, shared*)`` or ``(shared*, global)`` — ``_GMEM_SMEM_PAIRS``;
+ neither side is ``local``
+ * - dtype / shape
+ - both operands have a layout, equal dtype, equal non-unit extents
+ (``_is_valid_copy`` → ``validate_copy_op``)
+ * - divisibility
+ - the region's element count is divisible by the thread count
+ (``_divides_thread_cnt``) — otherwise the ``[outer, threads, vec]`` split has
+ no integer solution and the variant declines
+
+Demonstration program
+----------------------
+
+A warp (32 threads) copies a ``32×32`` ``float32`` tile global → shared and back
+(the round trip from ``test_gmem_smem.py``):
+
+.. code-block:: python
+
+ from tvm.script import tirx as T
+ from tvm.script.tirx import tile as Tx
+ from tvm.tirx.layout import S, TileLayout
+
+ shape, dtype = (32, 32), "float32"
+ s_layout = TileLayout(S[shape])
+ fs = (slice(0, 32), slice(0, 32))
+
+ @T.prim_func
+ def kernel(A_ptr: T.handle, B_ptr: T.handle):
+ A = T.match_buffer(A_ptr, shape, dtype)
+ B = T.match_buffer(B_ptr, shape, dtype)
+ T.device_entry()
+ T.cta_id([1]); T.lane_id([32]); T.thread_id([32])
+ A_smem = T.alloc_buffer(shape, dtype, scope="shared", layout=s_layout)
+ Tx.warp.copy(A_smem[fs], A[fs]) # global -> shared (this dispatch)
+ T.cuda.cta_sync()
+ Tx.warp.copy(B[fs], A_smem[fs]) # shared -> global (this dispatch)
+
+Algorithm
+---------
+
+**1. Synthesize the partition.** With 32 threads and ``32×32 = 1024`` elements,
+the dispatch builds a 3-D iteration ``[outer, threads, vec]`` via
+``align_layouts_gs``: it slices both layouts to the region, makes the **global**
+side drive the canonical (stride-descending) order, then carves a contiguous
+``vec`` tail and a ``threads`` chunk off it and re-groups the shared side to match.
+
+**2. Choose the vector width, widest first.** It tries element counts for
+``{128, 64, 32, 16, 8}`` bits and accepts the widest where (a) the contiguous tail
+divides it and (b) every **non-vec iter stride** (on both sides, the thread iter
+included) and both base offsets is a multiple of it, so the per-thread, per-round
+vector pointer is naturally aligned. (Only the innermost ``vec`` iter is excluded
+from that check.) For ``float32`` that is ``vec = 4`` (``4 × 4 B = 16 B = 128 bit``),
+giving ``outer = 1024 / (32 × 4) = 8``.
+
+**3. Emit a serial loop** (`gmem_smem.py`) — deliberately a Python ``for`` (so
+ptxas unrolls it), *not* ``T.unroll``:
+
+.. code-block:: python
+
+ for f in range(total_outer):
+ s_lin = s_p.apply(f, tid, v0, shape=apply_shape)["m"] # shared element offset
+ g_lin = g_p.apply(f, tid, v0, shape=apply_shape)["m"] # global element offset
+ s_off = _s_off(f, s_lin) # apply swizzle if any
+ s_ptr = _ptr_off(s_buf.ptr_to(s_zero), s_off)
+ g_ptr = _ptr_off(g_buf.ptr_to(g_zero), g_lin)
+ if g_is_src:
+ copy_op(s_ptr, g_ptr) # global -> shared
+ else:
+ copy_op(g_ptr, s_ptr) # shared -> global
+
+Each ``(f, tid, 0)`` coordinate is flattened by ``layout.apply`` against
+``[outer, threads, vec]``, so the emit never needs to know how the partition split
+the iters; ``copy_op`` is ``T.cuda.copy_{vec_bits}b`` (here ``copy_128b``).
+
+Generated TIRx IR
+-----------------
+
+Running ``LowerTIRx`` on the program above turns each ``Tx.warp.copy`` into the
+synthesized loop (global → shared shown, trimmed):
+
+.. code-block:: python
+
+ tid: T.let = threadIdx_x % 32
+ A_smem = T.alloc_shared((1024,))
+ for f in range(8): # outer = 8
+ s_lin = f * 128 + tid * 4 # 32 threads × vec 4 = 128 / round
+ g_lin = f * 128 + tid * 4
+ s_ptr = pointer_offset(A_smem, s_lin)
+ g_ptr = pointer_offset(A_1, g_lin) # A_1 = A.view(1024)
+ T.cuda.copy_bytes(s_ptr, g_ptr, 16) # 16 B = vec 4 × 4 B
+
+Generated CUDA
+--------------
+
+.. code-block:: c++
+
+ extern "C" __global__ void __launch_bounds__(32)
+ kernel_kernel(float* __restrict__ A_ptr, float* __restrict__ B_ptr) {
+ int tid = ((int)threadIdx.x);
+ __shared__ alignas(64) float A_smem_ptr[1024];
+ for (int f = 0; f < 8; ++f) {
+ int s_off = (f * 128) + (tid * 4);
+ void* s_ptr = tvm_builtin_pointer_offset(&A_smem_ptr[0], s_off);
+ void* g_ptr = tvm_builtin_pointer_offset(&A_ptr[0], s_off);
+ tvm_builtin_copy_128b(s_ptr, g_ptr); // 128-bit vector load+store
+ }
+ // ... __syncthreads(); then the shared -> global loop into B_ptr ...
+ }
+
+Thread ``tid`` handles elements ``[f·128 + tid·4 .. +4)`` each round; across 8
+rounds and 32 lanes that covers all 1024 elements, each as one 128-bit transfer.
+
+How inputs change the algorithm
+-------------------------------
+
+The element **dtype** sets the vector width (widest 128-bit transfer that stays
+aligned), which sets the round count. For the same ``32×32`` tile and 32 threads:
+
+.. list-table::
+ :header-rows: 1
+ :widths: 20 20 20 40
+
+ * - dtype
+ - ``vec``
+ - ``copy_bytes``
+ - ``outer = 1024 / (32 · vec)``
+ * - ``float32``
+ - 4
+ - 16 (``copy_128b``)
+ - 8
+ * - ``float16``
+ - 8
+ - 16 (``copy_128b``)
+ - 4
+ * - ``uint8``
+ - 16
+ - 16 (``copy_128b``)
+ - 2
+
+The **scope** sets which axis names the thread id (``warp`` → ``laneid``,
+``cta`` → ``tx``, …) and the thread count, hence the partition. A **swizzled**
+shared layout caps ``vec`` to one swizzle chunk and routes ``s_off`` through the
+swizzle (a recognized swizzle becomes a few register adds per round; otherwise
+``swizzle.apply`` per round).
diff --git a/docs/_sources/tirx/tile_primitives/copy/ldstmatrix.rst.txt b/docs/_sources/tirx/tile_primitives/copy/ldstmatrix.rst.txt
new file mode 100644
index 00000000000..11c4b2cf754
--- /dev/null
+++ b/docs/_sources/tirx/tile_primitives/copy/ldstmatrix.rst.txt
@@ -0,0 +1,218 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+copy → ldstmatrix
+=================
+
+The ``ldstmatrix`` variant lowers a ``copy`` between **register and shared** memory
+to the warp-collective PTX ``ldmatrix`` / ``stmatrix`` instructions: one
+instruction moves ``num`` 8×8 16-bit matrix tiles between shared memory and the
+warp's registers, with the hardware performing the lane↔element shuffle that an
+MMA fragment needs. It only applies when the register and shared **layouts match
+the m8n8 fragment geometry**; otherwise the copy falls back to :doc:`reg`. Source:
+``python/tvm/backend/cuda/operator/tile_primitive/copy/ld_stmatrix.py``.
+
+What it accepts
+---------------
+
+The predicate is lean — scope, a valid copy, and a register↔shared pair:
+
+.. code-block:: python
+
+ def _is_ldstmatrix(op_call, sctx):
+ if not sctx.is_target("cuda"):
+ return False, "non-cuda target"
+ if sctx.scope_kind not in ("warp", "warpgroup", "cta"):
+ return False, f"unsupported exec_scope {sctx.scope_kind} (need warp, warpgroup, or cta)"
+ for check in (
+ lambda: _all_threads_active(sctx),
+ lambda: _is_valid_copy(op_call, sctx),
+ lambda: _scope_allowed(op_call, sctx, allowed_pairs=_REG_SMEM_PAIRS), # (local, shared*)
+ ):
+ ok, msg = check()
+ if not ok:
+ return False, msg
+ return True, None
+
+The **real** gate is the layout fit, applied during emit. Both this variant and
+:doc:`reg` are priority 10 and both accept ``local ↔ shared``; ``ldstmatrix`` is
+tried first and **declines** (via ``fail(...)``) if the layouts are not ldmatrix
+fragments, leaving ``reg`` to handle the copy:
+
+.. code-block:: python
+
+ # _emit: try the widest matrix count that fits, else decline
+ for num in (4, 2, 1):
+ chosen = _try_num(r, s, num)
+ if chosen is not None:
+ break
+ if chosen is None:
+ fail("ldstmatrix layout doesn't fit any num ∈ {4,2,1}")
+
+.. list-table::
+ :header-rows: 1
+ :widths: 22 78
+
+ * - Property
+ - Requirement
+ * - target / scope
+ - ``cuda``; ``warp`` / ``warpgroup`` / ``cta`` (needs a full warp), all active
+ * - memory pair
+ - ``_REG_SMEM_PAIRS`` = ``(local, shared*)`` / ``(shared*, local)``
+ * - dtype
+ - 16-bit (``.b16``) — ldmatrix/stmatrix move 8 fp16 = 16 B per lane per tile
+ * - layout fit
+ - both operands regroup to ``[T/32, 8, 4, M/(2·num), num, 2]`` with the
+ register side equal to the m8n8 fragment pattern and the shared side row- or
+ column-major with 16-B-aligned tile strides (``_try_num``), for some
+ ``num ∈ {4, 2, 1}``
+
+Demonstration program
+----------------------
+
+A warp loads ``num = 2`` row-major matrix tiles (``M, N = 8, 16`` fp16) shared →
+register, from ``test_ld_stmatrix.py`` (register layout = the m8n8 fragment,
+``S[(8,4,2,2):(4@laneid, 1@laneid, 2, 1)]``):
+
+.. code-block:: python
+
+ from tvm.tirx.layout import S, TileLayout, laneid
+
+ num = 2; M, N = 8, num * 8
+ r_layout = TileLayout(S[(8, 4, num, 2) : (4 @ laneid, 1 @ laneid, 2, 1)])
+ s_layout = TileLayout(S[(8, 4, num, 2) : (num * 8, 2, 8, 1)]) # row-major
+ full = (slice(0, 8), slice(0, 4), slice(0, num), slice(0, 2))
+
+ @T.prim_func
+ def kernel(A_ptr: T.handle, B_ptr: T.handle):
+ A = T.match_buffer(A_ptr, (M, N), "float16")
+ B = T.match_buffer(B_ptr, (M, N), "float16")
+ T.device_entry(); T.cta_id([1]); T.lane_id([32]); tid = T.thread_id([32])
+ A_smem = T.alloc_buffer((8, 4, num, 2), "float16", scope="shared", layout=s_layout)
+ # ... stage A into A_smem (row = tid//4, cp = tid%4) ...
+ T.cuda.cta_sync()
+ R = T.alloc_buffer((8, 4, num, 2), "float16", scope="local", layout=r_layout)
+ Tx.warp.copy(R[full], A_smem[full]) # shared -> register (ldmatrix)
+ # ... write R back out to B ...
+
+Algorithm
+---------
+
+**1. Regroup both layouts to the matrix geometry.** ``_try_num(r, s, num)`` groups
+each layout's iters into ``[T/32, 8, 4, M/(2·num), num, 2]``: the warp-replication
+outer, the **8** rows of a tile, the **4** lane-column-pairs, ``m_outer`` tiles
+along M, the ``num`` tiles, and the inner **2** (the ``.b16`` element pair). If the
+group fails, the layout isn't a fragment → ``None``.
+
+**2. The register side must be the exact m8n8 fragment.** The 8/4/2 register
+strides must be ``(4, 1, 1)`` — i.e. the canonical ldmatrix fragment where lane
+``i`` holds row ``i//4``, column-pair ``i%4``:
+
+.. code-block:: python
+
+ r8, r4, _r_num_iters, r2 = rs
+ if (r8, r4, r2) != (4, 1, 1):
+ return None
+
+**3. The shared side decides** ``trans`` **and the per-tile stride** ``p``.
+Row-major shared (``s4, s2 == 2, 1``, ``s8`` a positive multiple of 8) → plain
+``ldmatrix`` with ``p = s8``; column-major (``s8 == 1``, ``s4 == 2·s2``,
+``s2`` a multiple of 8) → the ``.trans`` form:
+
+.. code-block:: python
+
+ if (s4, s2) == (2, 1) and s8 > 0 and s8 % 8 == 0:
+ return (rg, rsep, sg, ssep, False, s8, num) # trans=False, p=s8
+ if s8 == 1 and s2 > 0 and s2 % 8 == 0 and s4 == 2 * s2:
+ return (rg, rsep, sg, ssep, True, s2, num) # trans=True, p=s2
+
+The 8-multiple checks enforce 16-byte alignment (8 fp16) for every tile and every
+``m_outer`` advance, since each lane's ``.b16`` access reads 16 bytes.
+
+**4. Emit one instruction per** ``m_outer`` **tile group.** Each lane contributes
+its shared address (tile offset + ``(laneid % 8) · p``) and ``num`` register
+handles:
+
+.. code-block:: python
+
+ for mm in T.unroll(m_outer):
+ smem_ptr = _ptr_off(s_buf.ptr_to(s_zero), _smem_off(mm, tile_off + (laneid % 8) * p))
+ handles = [r_local.ptr_to([...]) for i in range(num)]
+ if direction == "ld":
+ T.ptx.ldmatrix(trans, num, ".b16", smem_ptr, *handles)
+ else:
+ T.ptx.stmatrix(trans, num, ".b16", smem_ptr, *handles, shape="m8n8", space="shared")
+
+(This is the one copy variant that **does** use ``T.unroll`` — ``m_outer`` is tiny.)
+
+Generated TIRx IR
+-----------------
+
+For the demo (``num = 2``, ``M = 8`` ⇒ ``m_outer = 1``):
+
+.. code-block:: python
+
+ for mm in T.unroll(1):
+ T.ptx.ldmatrix(T.bool(False), 2, ".b16", smem_ptr,
+ T.address_of(r_local[0]), T.address_of(r_local[2]))
+
+Generated CUDA
+--------------
+
+.. code-block:: c++
+
+ __forceinline__ __device__ void ptx_ldmatrix_2_b16_0(void* smem_ptr, void* dst0, void* dst1) {
+ // ...
+ "ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];"
+ // ...
+ }
+ // call site (per lane):
+ ptx_ldmatrix_2_b16_0(smem_ptr, &r_local_ptr[0], &r_local_ptr[2]);
+
+``num = 2`` becomes ``.x2`` with two destination registers; the warp's 32 lanes
+cooperatively supply the 8 source rows and receive the shuffled fragment.
+
+How inputs change the algorithm
+-------------------------------
+
+``num`` (the matrix count that fits) selects the instruction width and the number
+of register handles; ``trans`` (set by the shared layout) selects the transposing
+form:
+
+.. list-table::
+ :header-rows: 1
+ :widths: 20 20 60
+
+ * - input
+ - emitted
+ - PTX
+ * - ``num = 1``
+ - ``.x1``
+ - ``ldmatrix.sync.aligned.m8n8.x1.shared.b16 {%0}, [%1];``
+ * - ``num = 2``
+ - ``.x2``
+ - ``ldmatrix.sync.aligned.m8n8.x2.shared.b16 {%0, %1}, [%2];``
+ * - ``num = 4``
+ - ``.x4``
+ - ``ldmatrix.sync.aligned.m8n8.x4.shared.b16 {%0, %1, %2, %3}, [%4];``
+ * - ``trans = True``
+ - ``.trans``
+ - ``ldmatrix.sync.aligned.m8n8.x2.trans.shared.b16 {%0, %1}, [%2];``
+
+A larger M raises ``m_outer`` (more unrolled instructions per lane); the ``st``
+direction emits ``stmatrix`` with the same width/trans logic. If no ``num`` fits,
+the copy is handled by :doc:`reg` instead.
diff --git a/docs/_sources/tirx/tile_primitives/copy/reg.rst.txt b/docs/_sources/tirx/tile_primitives/copy/reg.rst.txt
new file mode 100644
index 00000000000..d195ffb5a4c
--- /dev/null
+++ b/docs/_sources/tirx/tile_primitives/copy/reg.rst.txt
@@ -0,0 +1,206 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+copy → reg
+==========
+
+The ``reg`` variant lowers a synchronous ``copy`` where **exactly one side is a
+register** (``local``) buffer and the other is ``shared*`` or ``global``. Unlike
+:doc:`gmem_smem`, the partition is **not synthesized** — it is *induced* by the
+register operand's layout: that layout's thread-axis iters already say which thread
+owns which logical coordinate, so the dispatch drops those axes, leaves each thread
+its private bundle of elements, and copies them in a vectorized serial loop. Source:
+``python/tvm/backend/cuda/operator/tile_primitive/copy/reg.py``.
+
+What it accepts
+---------------
+
+.. code-block:: python
+
+ def _is_reg_copy(op_call, sctx):
+ if not sctx.is_target("cuda"):
+ return False, "non-cuda target"
+ if sctx.scope_kind not in ("thread", "warp", "warpgroup", "cta"):
+ return False, f"unsupported exec_scope {sctx.scope_kind}"
+ for check in (
+ lambda: _all_threads_active(sctx),
+ lambda: _is_valid_copy(op_call, sctx),
+ lambda: _scope_allowed(op_call, sctx, allowed_pairs=_REG_PAIRS),
+ lambda: _r_side_layout_valid(op_call, sctx), # the register operand
+ lambda: _s_side_slice_ok(op_call), # the other operand
+ ):
+ ok, msg = check()
+ if not ok:
+ return False, msg
+ return True, None
+
+.. list-table::
+ :header-rows: 1
+ :widths: 22 78
+
+ * - Property
+ - Requirement
+ * - target / scope
+ - ``cuda``; ``thread`` / ``warp`` / ``warpgroup`` / ``cta`` with all threads
+ active
+ * - memory pair
+ - ``_REG_PAIRS`` = ``(local, shared*)`` / ``(shared*, local)`` /
+ ``(local, global)`` / ``(global, local)`` — exactly one side is ``local``
+ * - register layout
+ - ``_r_side_layout_valid``: the ``local`` operand is a non-swizzle
+ ``TileLayout`` whose thread-axis iters have **stride 1**, a register-level
+ subscope no wider than the exec scope, and a **zero sliced thread offset**
+ (the region doesn't split a thread axis)
+ * - other side
+ - ``_s_side_slice_ok``: the ``shared*`` / ``global`` operand slices cleanly to
+ its region
+
+Demonstration program
+----------------------
+
+A warp round-trips a ``32×8`` ``float32`` tile shared → register → shared, with the
+register layout ``S[(32,8):(1@laneid, 1)]`` — **lane ``i`` owns row ``i``** (8
+contiguous elements). From ``test_reg.py``:
+
+.. code-block:: python
+
+ from tvm.tirx.layout import S, TileLayout, laneid
+
+ shape, dtype = (32, 8), "float32"
+ r_layout = TileLayout(S[shape : (1 @ laneid, 1)]) # lane i -> row i, 8 regs
+ s_layout = TileLayout(S[shape])
+ fs = (slice(0, 32), slice(0, 8))
+
+ @T.prim_func
+ def kernel(B_ptr: T.handle):
+ B = T.match_buffer(B_ptr, shape, dtype)
+ T.device_entry(); T.cta_id([1]); T.lane_id([32]); tid = T.thread_id([32])
+ A_smem = T.alloc_buffer(shape, dtype, scope="shared", layout=s_layout)
+ for kk in range(8): A_smem[tid, kk] = T.cast(tid * 100 + kk + 1, dtype)
+ T.cuda.cta_sync()
+ R = T.alloc_buffer(shape, dtype, scope="local", layout=r_layout)
+ Tx.warp.copy(R[fs], A_smem[fs]) # shared -> register (this dispatch)
+ # ... clear A_smem, cta_sync ...
+ Tx.warp.copy(A_smem[fs], R[fs]) # register -> shared (this dispatch)
+ # ... cta_sync; B[tid, kk] = A_smem[tid, kk] ...
+
+Algorithm
+---------
+
+**1. Inherit the partition from R.** The register layout's thread axis (``laneid``)
+states that lane ``i`` owns row ``i``; the dispatch aligns the other (shared) side
+to that order, then **drops the thread iters** — what remains is each thread's
+private memory bundle: here ``8`` contiguous elements per lane.
+
+**2. Linearize and choose the vector width.** The per-thread elements are
+flattened into ``(extent, stride)`` atoms; the vector width is chosen widest-first
+(``128 → … → 8`` bits) so the contiguous tail divides it and the outer atom
+strides + base offsets are aligned. Crucially the **thread-axis strides are
+excluded** from this alignment check (they live in *partition-coordinate* space —
+which thread owns which element — and never appear in a single thread's physical
+address). For ``8`` contiguous ``float32`` that is ``vec = 4``, so ``outer = 2``.
+
+**3. Per-thread base offset + serial loop.** The shared-side base offset is built
+from thread-axis placeholders (substituted with the real ``T.lane_id()`` etc.),
+and the register side is a flat per-thread ``local`` buffer. The emit is a serial
+loop (not ``T.unroll`` — same flooding rationale as :doc:`gmem_smem`):
+
+.. code-block:: python
+
+ r_local = r_buf.local(*per_thread_r_shape) # flat per-thread registers
+ for f in range(total_outer):
+ ds, dr = _outer_const_offsets(outer, f) # shared / reg deltas
+ s_ptr = _ptr_off(s_buf.ptr_to(s_zero_indices), _s_iter_off(f, ds, s_off))
+ r_ptr = _ptr_off(r_local.ptr_to([0]), r_off_base + dr)
+ if r_is_src:
+ copy_op(s_ptr, r_ptr) # register -> shared/global
+ else:
+ copy_op(r_ptr, s_ptr) # shared/global -> register
+
+Generated TIRx IR
+-----------------
+
+``LowerTIRx`` turns the shared → register copy into a per-thread loop over the
+8-element register bundle (trimmed):
+
+.. code-block:: python
+
+ r_local = T.decl_buffer((8,), data=R.data, scope="local") # 8 regs / lane
+ for f in range(2): # outer = 8 / vec 4
+ s_ptr = pointer_offset(A_smem, ...) # this lane's row
+ r_ptr = pointer_offset(r_local, dr)
+ T.cuda.copy_bytes(r_ptr, s_ptr, 16) # 16 B = vec 4 × 4 B
+
+(The register → shared copy is the mirror: ``copy_bytes(s_ptr, r_ptr, 16)``.)
+
+Generated CUDA
+--------------
+
+.. code-block:: c++
+
+ alignas(64) float r_local_ptr[8]; // 8 registers, private to the lane
+ for (int f = 0; f < 2; ++f) {
+ void* r_ptr = tvm_builtin_pointer_offset(&r_local_ptr[0], dr);
+ void* s_ptr = tvm_builtin_pointer_offset(&A_smem_ptr[0], /* lane row + f*4 */);
+ tvm_builtin_copy_128b(r_ptr, s_ptr); // shared -> register
+ }
+ // ... register -> shared mirror writes A_smem back ...
+
+Each lane copies its own 8 elements as 2 × 128-bit transfers; no cross-lane
+addressing appears because the thread partition was resolved away at lowering.
+
+How inputs change the algorithm
+-------------------------------
+
+The register layout's **per-thread element count** (the non-thread extents — here
+``k``) and the **dtype** set the register count, vector width, and round count:
+
+.. list-table::
+ :header-rows: 1
+ :widths: 18 18 22 22 20
+
+ * - dtype
+ - ``k``
+ - regs / lane
+ - ``vec``
+ - ``outer = k / vec``
+ * - ``float32``
+ - 8
+ - 8
+ - 4
+ - 2
+ * - ``float32``
+ - 16
+ - 16
+ - 4
+ - 4
+ * - ``float16``
+ - 8
+ - 8
+ - 8
+ - 1
+ * - ``float16``
+ - 16
+ - 16
+ - 8
+ - 2
+
+The copy is always a 128-bit transfer (``copy_bytes = 16``) when the contiguous
+tail allows. The **scope** sets the thread axis (``warp`` → ``laneid``, ``cta`` →
+``tx``, …) the register layout must use; a different R layout (e.g. a strided or
+multi-row ownership) changes which elements each lane holds and therefore the atom
+list and ``outer``.
diff --git a/docs/_sources/tirx/tile_primitives/copy_async.rst.txt b/docs/_sources/tirx/tile_primitives/copy_async.rst.txt
new file mode 100644
index 00000000000..1d6fa0ad854
--- /dev/null
+++ b/docs/_sources/tirx/tile_primitives/copy_async.rst.txt
@@ -0,0 +1,63 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+copy_async
+==========
+
+Asynchronous copy. Every variant emits only the *issue* instruction — the caller is
+responsible for completion (``cp.async`` commit/wait for ``ldgsts``; mbarrier
+arrive/wait for the bulk-tensor and dsmem paths; ``tcgen05.commit`` /
+``tcgen05.wait`` for the tensor-memory paths). Selection is by the source/dest
+memory pair and scope.
+
+.. list-table::
+ :header-rows: 1
+ :widths: 26 16 14 44
+
+ * - Variant
+ - Pair
+ - Prio
+ - Issue instruction
+ * - :doc:`copy_async/ldgsts`
+ - global → shared
+ - 20
+ - ``cp.async`` (LDGSTS), per-thread vectorized
+ * - :doc:`copy_async/tma`
+ - global ↔ shared
+ - 10
+ - ``cp.async.bulk.tensor`` (TMA, descriptor-driven, single-thread)
+ * - :doc:`copy_async/dsmem`
+ - shared → shared (cross-CTA)
+ - 10
+ - ``cp.async.bulk`` shared::cluster (``mapa`` remote address)
+ * - :doc:`copy_async/tcgen05_cp`
+ - shared → tmem
+ - 10
+ - ``tcgen05.cp.32x128b.warpx4`` (matrix-descriptor driven)
+ * - :doc:`copy_async/tcgen05_ldst`
+ - tmem ↔ register
+ - 10
+ - ``tcgen05.ld`` / ``tcgen05.st`` (warpgroup, atom-matched)
+
+.. toctree::
+ :maxdepth: 1
+
+ copy_async/ldgsts
+ copy_async/tma
+ copy_async/dsmem
+ copy_async/tcgen05_cp
+ copy_async/tcgen05_ldst
diff --git a/docs/_sources/tirx/tile_primitives/copy_async/dsmem.rst.txt b/docs/_sources/tirx/tile_primitives/copy_async/dsmem.rst.txt
new file mode 100644
index 00000000000..bec98c5bcd3
--- /dev/null
+++ b/docs/_sources/tirx/tile_primitives/copy_async/dsmem.rst.txt
@@ -0,0 +1,190 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+copy_async → dsmem
+==================
+
+The ``dsmem`` variant lowers a ``copy_async`` whose **source and destination are
+both shared** memory but in **different CTAs of a cluster** (distributed shared
+memory). One elected thread on the source CTA maps the destination CTA's shared
+address into its own address space (PTX ``mapa``) and issues a bulk copy
+(``cp.async.bulk.shared::cluster``); the hardware decrements the *destination* CTA's
+mbarrier when the bytes land. Source:
+``python/tvm/backend/cuda/operator/tile_primitive/copy_async/dsmem.py``.
+
+What it accepts
+---------------
+
+Three predicates: a valid copy, a single-thread scope, and a shared → shared pair:
+
+.. code-block:: python
+
+ # register_dispatch(..., priority=10, when=[
+ predicate("validate_copy_op", ...),
+ predicate("single_thread", lambda op, sctx: (single_thread(op, sctx), "expected single thread")),
+ predicate("is_shared_to_shared", lambda op, sctx: (_is_shared_to_shared(op), "not shared-to-shared")),
+ # ])
+
+ def _is_shared_to_shared(op_call):
+ src_scope = op_call.src.buffer.scope()
+ dst_scope = op_call.dst.buffer.scope()
+ return src_scope.startswith("shared") and dst_scope.startswith("shared")
+
+.. list-table::
+ :header-rows: 1
+ :widths: 22 78
+
+ * - Property
+ - Requirement
+ * - target / priority
+ - ``cuda``; priority ``10``
+ * - scope
+ - **single thread** issues the copy (the source CTA elects one thread)
+ * - memory pair
+ - both ``shared*`` (``_is_shared_to_shared``); the copy targets a *remote* CTA
+ via ``remote_cta_id``
+ * - chunk size
+ - the contiguous chunk must be **≥ 16 bytes and a multiple of 16**
+ (``cp.async.bulk`` requirement) — else the dispatch declines (``fail``)
+ * - environment
+ - a **cluster launch** (so a remote CTA's shared memory exists), plus a caller
+ mbarrier on the destination CTA
+
+Demonstration program
+----------------------
+
+A 2-CTA cluster: CTA 0 stages a ``128×64`` ``float16`` tile global → its shared,
+then bulk-copies it into **CTA 1's** shared via ``dsmem``; CTA 1 waits on the
+mbarrier and writes the result out (from ``test_dsmem.py``):
+
+.. code-block:: python
+
+ from tvm.tirx.lang.pipeline import MBarrier
+
+ shape, dtype, CLUSTER_N = (128, 64), "float16", 2
+ src_layout = dst_layout = TileLayout(S[128, 64])
+ copy_bytes = 128 * 64 * 2
+ r = (slice(0, 128), slice(0, 64))
+
+ @T.prim_func
+ def dsmem_copy(A_ptr: T.handle, B_ptr: T.handle):
+ A = T.match_buffer(A_ptr, shape, dtype); B = T.match_buffer(B_ptr, shape, dtype)
+ T.device_entry()
+ cbx = T.cta_id_in_cluster([CLUSTER_N]); T.cta_id([CLUSTER_N]); tid = T.thread_id([1])
+ pool = T.SMEMPool()
+ src_smem = T.decl_buffer(list(shape), dtype, pool.alloc([8192], dtype, align=128).data,
+ elem_offset=0, scope="shared.dyn", layout=src_layout)
+ dst_smem = T.decl_buffer(list(shape), dtype, pool.alloc([8192], dtype, align=128).data,
+ elem_offset=0, scope="shared.dyn", layout=dst_layout)
+ mbar = MBarrier(pool, 1); pool.commit()
+ mbar.init(1); T.ptx.fence.mbarrier_init(); T.cuda.cluster_sync()
+ if tid == 0:
+ if cbx == 0: # source CTA
+ Tx.copy(src_smem[r], A[r]) # global -> local shared
+ T.ptx.fence.proxy_async("shared::cta")
+ Tx.copy_async(dst_smem[r], src_smem[r], dispatch="dsmem",
+ mbar=mbar.ptr_to([0]), remote_cta_id=T.int32(1)) # -> CTA 1
+ else: # destination CTA
+ T.ptx.mbarrier.arrive.expect_tx(mbar.ptr_to([0]), copy_bytes)
+ mbar.wait(0, 0)
+ Tx.copy(B[r], dst_smem[r]) # remote shared -> global
+ T.cuda.cluster_sync()
+
+Algorithm
+---------
+
+**1. Find the contiguous chunk.** The dispatch slices and groups both layouts to the
+copy region, walks inward to the longest matching contiguous stride-1 shard chain,
+and multiplies those extents into ``chunk_elements``; ``chunk_bytes`` must be ≥ 16
+and a multiple of 16 (a ``cp.async.bulk`` constraint), else it declines:
+
+.. code-block:: python
+
+ chunk_bytes = chunk_elements * dtype_bytes
+ if chunk_bytes < 16 or chunk_bytes % 16 != 0:
+ fail(...)
+
+**2. Map the remote address.** ``map_shared_rank`` (PTX ``mapa``) translates a local
+shared pointer into the destination CTA's window — applied to both the destination
+buffer pointer and the mbarrier:
+
+.. code-block:: python
+
+ remote_mbar = T.ptx.map_shared_rank(mbar, remote_cta_id)
+ cluster_dst = T.ptx.map_shared_rank(dst_buf.ptr_to(dst_st), remote_cta_id)
+
+**3. Issue one bulk copy per chunk.** Fully contiguous → a single instruction; a
+strided region loops over the outer (non-contiguous) extents, re-deriving the
+chunk's offsets each step:
+
+.. code-block:: python
+
+ if not outer_extents: # one contiguous chunk
+ T.ptx.cp_async.bulk.s2c(cluster_dst, src_buf.ptr_to(src_st), chunk_bytes, remote_mbar)
+ else:
+ for loop_vars in T.grid(*outer_extents): # one chunk per outer coord
+ ... # re-decl src/dst views at the per-chunk offset
+ T.ptx.cp_async.bulk.s2c(cluster_dst, src_ptr, chunk_bytes, remote_mbar)
+
+The ``complete_tx::bytes`` form makes the hardware decrement ``remote_mbar`` by
+``chunk_bytes`` on completion; the dispatch emits no wait — the caller arms the
+mbarrier (``arrive.expect_tx``) and waits.
+
+Generated TIRx IR
+-----------------
+
+The fully contiguous ``128×64`` fp16 tile (``16384`` bytes) is a **single chunk**:
+
+.. code-block:: python
+
+ T.ptx.cp_async.bulk.s2c(cluster_dst[0], src_ptr[0], 16384, remote_mbar[0])
+
+Generated CUDA
+--------------
+
+.. code-block:: c++
+
+ // map local shared addresses into CTA 1's window (mapa)
+ remote_mbar = tvm_builtin_ptx_mapa_u64(&mbar, /*rank=*/1); // asm: mapa.u64
+ cluster_dst = tvm_builtin_ptx_mapa_u64(&dst_smem, /*rank=*/1);
+ // bulk-copy 16384 bytes local shared -> CTA 1 shared, signalling its mbarrier
+ "cp.async.bulk.shared::cluster.shared::cta.mbarrier::complete_tx::bytes ..."
+
+One thread on CTA 0 launches the whole 16 KB transfer; CTA 1's mbarrier fires when
+it lands.
+
+How inputs change the algorithm
+-------------------------------
+
+.. list-table::
+ :header-rows: 1
+ :widths: 30 70
+
+ * - input
+ - effect
+ * - layout contiguity
+ - fully contiguous (matching row-major both sides) → **one** ``cp.async.bulk``;
+ a stride gap or mismatched outer stride → a loop of **N** chunks (one per
+ outer coord)
+ * - dtype / chunk size
+ - sets ``chunk_bytes`` (must stay ≥ 16 and a multiple of 16); smaller
+ contiguous runs mean smaller, more numerous chunks
+ * - ``remote_cta_id``
+ - the ``mapa`` rank — which cluster CTA receives the data
+ * - incompatible layouts
+ - e.g. row-major source vs column-major destination → no matching contiguous
+ chain → the dispatch declines (``fail``)
diff --git a/docs/_sources/tirx/tile_primitives/copy_async/ldgsts.rst.txt b/docs/_sources/tirx/tile_primitives/copy_async/ldgsts.rst.txt
new file mode 100644
index 00000000000..a49b7d3c02c
--- /dev/null
+++ b/docs/_sources/tirx/tile_primitives/copy_async/ldgsts.rst.txt
@@ -0,0 +1,176 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+copy_async → ldgsts
+===================
+
+The ``ldgsts`` variant lowers ``copy_async`` for a **global → shared** transfer to
+the PTX ``cp.async`` (LDGSTS) instruction: each thread issues an *asynchronous*
+vectorized copy that the hardware completes in the background, so the warp can keep
+computing while the load is in flight. It reuses the exact ``[outer, threads, vec]``
+partition of the synchronous :doc:`../copy/gmem_smem` variant; the differences are
+all in *what* is emitted and *when* it completes. Source:
+``python/tvm/backend/cuda/operator/tile_primitive/copy_async/ldgsts.py``.
+
+What it accepts
+---------------
+
+.. code-block:: python
+
+ _LDGSTS_PAIRS = [("global", "shared*")] # cp.async is unidirectional
+ _LDGSTS_VEC_BITS = (128, 64, 32) # cp_size ∈ {16, 8, 4} bytes
+
+ def _is_ldgsts(op_call, sctx):
+ if not sctx.is_target("cuda"):
+ return False, "non-cuda target"
+ if sctx.scope_kind not in ("thread", "warp", "warpgroup", "cta"):
+ return False, f"unsupported exec_scope {sctx.scope_kind}"
+ for check in (
+ lambda: _all_threads_active(sctx),
+ lambda: _is_valid_copy(op_call, sctx),
+ lambda: _scope_allowed(op_call, sctx, allowed_pairs=_LDGSTS_PAIRS),
+ lambda: _divides_thread_cnt_ldgsts(op_call, sctx),
+ ):
+ ok, msg = check()
+ if not ok:
+ return False, msg
+ return True, None
+
+.. list-table::
+ :header-rows: 1
+ :widths: 22 78
+
+ * - Property
+ - Requirement
+ * - target / scope
+ - ``cuda``; ``thread`` / ``warp`` / ``warpgroup`` / ``cta``, all active
+ * - direction
+ - **global → shared only** (``_LDGSTS_PAIRS``) — ``cp.async`` is unidirectional
+ * - dtype / shape
+ - ``_is_valid_copy``; region element count divides the thread count
+ * - vector width
+ - ``cp.async`` only accepts cp_size ∈ {4, 8, 16} bytes, so the candidate set is
+ restricted to ``_LDGSTS_VEC_BITS`` = ``{128, 64, 32}`` bits
+ * - priority
+ - ``20`` — selected for ``copy_async`` global→shared (vs the bulk/TMA variants)
+
+Demonstration program
+----------------------
+
+A CTA (128 threads) asynchronously loads a ``128×32`` ``float16`` tile global →
+shared, then commits and waits before reading it back (from ``test_ldgsts.py``):
+
+.. code-block:: python
+
+ shape, dtype = (128, 32), "float16"
+ s_layout = TileLayout(S[shape]); full = (slice(0, 128), slice(0, 32))
+
+ @T.prim_func
+ def copy_async(A_ptr: T.handle, B_ptr: T.handle):
+ A = T.match_buffer(A_ptr, shape, dtype)
+ B = T.match_buffer(B_ptr, shape, dtype)
+ T.device_entry(); T.cta_id([1]); T.warp_id([4]); T.lane_id([32]); tid = T.thread_id([128])
+ A_smem = T.alloc_buffer(shape, dtype, scope="shared", layout=s_layout)
+ Tx.cta.copy_async(A_smem[full], A[full], dispatch="ldgsts") # async global -> shared
+ T.ptx.cp_async.commit_group() # caller commits ...
+ T.ptx.cp_async.wait_group() # ... and waits
+ T.cuda.cta_sync()
+ Tx.cta.copy(B[full], A_smem[full])
+
+Algorithm
+---------
+
+**1. Same partition as** :doc:`../copy/gmem_smem`. ``align_layouts_gs`` builds the
+``[outer, threads, vec]`` split with the global side driving the canonical order —
+but the vector candidates are clamped to ``{128, 64, 32}`` bits so the byte size is
+a legal ``cp.async`` cp_size. For ``128×32 = 4096`` ``float16`` over 128 threads the
+widest legal width is ``vec = 8`` (``8 × 2 B = 16 B``), giving ``outer = 4``.
+
+**2. Emit** ``cp.async`` **instead of a synchronous copy**, and do **not** sync:
+
+.. code-block:: python
+
+ for f in range(total_outer):
+ s_lin = s_p.apply(f, tid, v0, shape=apply_shape)["m"]
+ g_lin = g_p.apply(f, tid, v0, shape=apply_shape)["m"]
+ s_ptr = _ptr_off(s_buf.ptr_to(s_zero), _s_off(f, s_lin))
+ g_ptr = _ptr_off(g_buf.ptr_to(g_zero), g_lin)
+ T.evaluate(T.ptx.cp_async(s_ptr, g_ptr, cp_size)) # async; cp_size = vec_bits // 8
+ # NO cta_sync — commit_group / wait_group / cta_sync are the caller's job
+
+Completion is the caller's responsibility (``cp_async.commit_group()`` then
+``cp_async.wait_group()``); the dispatch only issues the in-flight loads.
+
+Generated TIRx IR
+-----------------
+
+.. code-block:: python
+
+ for f in range(4): # outer = 4
+ s_ptr = pointer_offset(A_smem, ...)
+ g_ptr = pointer_offset(A_1, ...)
+ T.ptx.cp_async(s_ptr, g_ptr, 16, T.uint64(0), 0, -1, -1, "") # cp_size = 16 B
+
+Generated CUDA
+--------------
+
+.. code-block:: c++
+
+ // cp.async.cg copies 16 bytes shared <- global, asynchronously
+ tvm_builtin_ptx_cp_async_cg_16(s_ptr, g_ptr, /*cache_policy=*/0); // x4 (outer = 4)
+ // ...
+ tvm_builtin_ptx_cp_async_commit_group(); // asm: cp.async.commit_group;
+ tvm_builtin_ptx_cp_async_wait_group_0(); // asm: cp.async.wait_group 0;
+
+where the helper is ``asm volatile("cp.async.cg.shared.global [%0], [%1], 16;")``.
+Each thread issues 4 asynchronous 16-byte copies; nothing blocks until the caller's
+``wait_group``.
+
+How inputs change the algorithm
+-------------------------------
+
+The dtype/alignment set ``vec`` (hence ``cp_size`` and ``outer``), but unlike the
+synchronous variant the width is capped at 16 B (cp.async maximum):
+
+.. list-table::
+ :header-rows: 1
+ :widths: 24 18 20 38
+
+ * - case
+ - ``vec``
+ - ``cp_size``
+ - ``outer = 4096 / (128 · vec)``
+ * - ``float16``, aligned
+ - 8
+ - 16 B
+ - 4
+ * - ``float32``, aligned
+ - 4
+ - 16 B
+ - 8
+ * - 8-B-aligned only
+ - (clamped)
+ - 8 B
+ - (doubles)
+ * - 4-B-aligned only
+ - (clamped)
+ - 4 B
+ - (×4)
+
+If the region can't satisfy even a 4-byte (32-bit) cp_size, ``align_layouts_gs``
+finds no candidate and the variant declines. The **direction is fixed**: a
+shared → global ``copy_async`` is never ``ldgsts`` (hardware has no store form).
diff --git a/docs/_sources/tirx/tile_primitives/copy_async/tcgen05_cp.rst.txt b/docs/_sources/tirx/tile_primitives/copy_async/tcgen05_cp.rst.txt
new file mode 100644
index 00000000000..8f15aaafdc9
--- /dev/null
+++ b/docs/_sources/tirx/tile_primitives/copy_async/tcgen05_cp.rst.txt
@@ -0,0 +1,183 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+copy_async → tcgen05_cp
+=======================
+
+The ``tcgen05_cp`` variant lowers a ``copy_async`` from **shared memory to tensor
+memory** (Blackwell ``tmem``). One elected thread issues
+``tcgen05.cp.32x128b.warpx4``: a shared **matrix descriptor** names the source tile,
+and the ``warpx4`` multicast routes 32 lanes × 128 bits into the tensor-memory lanes
+owned by all four warps. The dispatch issues only the copy; the caller signals
+completion with ``tcgen05.commit``. Source:
+``python/tvm/backend/cuda/operator/tile_primitive/copy_async/tcgen05_cp.py``.
+
+What it accepts
+---------------
+
+Two predicates — a valid shared→tmem copy and a single-thread scope:
+
+.. code-block:: python
+
+ # register_dispatch(..., variant="smem->tmem", priority=10, when=[
+ predicate("validate_smem_tmem_copy", _is_valid_smem_tmem_copy),
+ predicate("exec_scope", _single_thread_exec), # exec_scope == "thread"
+ # ])
+
+ def _is_valid_smem_tmem_copy(op, sctx):
+ if not (src.scope().startswith("shared") and dst.scope() == "tmem"): ...
+ if not (src.layout and dst.layout): ...
+ if dst.allocated_addr is None: ...
+ rep = dst.layout.replica # the warpx4 router
+ if not (len(rep) == 1 and int(rep[0].extent) == 4
+ and int(rep[0].stride) == 32 and "TLane" in str(rep[0].axis)):
+ return False, f"requires R[4:32@TLane] on tmem, got {list(rep)}"
+ return True, None
+
+.. list-table::
+ :header-rows: 1
+ :widths: 22 78
+
+ * - Property
+ - Requirement
+ * - target / priority
+ - ``cuda`` (Blackwell, sm_100+); priority ``10``
+ * - scope
+ - **single thread** issues the copy
+ * - memory pair
+ - source ``shared*`` → destination ``tmem`` (with ``allocated_addr`` set by a
+ prior ``tcgen05.alloc``)
+ * - tmem layout
+ - the replica **must be exactly** ``R[4:32@TLane]`` — the warpx4 router that
+ fans the copy across all four warps' tensor-memory lanes
+ * - dtype
+ - sets ``elem_per_128b = 128 / dtype_bits`` (uint8 → 16) and the descriptor
+ swizzle mode
+
+Demonstration program
+----------------------
+
+A warpgroup allocates 16 tmem columns, fills a ``32×16`` ``uint8`` shared tile, and
+copies it into tmem with ``tcgen05_cp`` (from ``test_smem_tmem.py``; the readback /
+dealloc tail is elided):
+
+.. code-block:: python
+
+ from tvm.tirx.layout import R, S, TCol, TileLayout, TLane
+
+ A_smem = T.alloc_buffer([32, 16], "uint8", scope="shared",
+ layout=TileLayout(S[(32, 16) : (16, 1)]), align=1024)
+ tmem_addr = T.alloc_shared([1], "uint32")
+ cp_mbar = T.alloc_shared([1], "uint64")
+ if warp_id == 0:
+ T.ptx.tcgen05.alloc(T.address_of(tmem_addr), n_cols=16, cta_group=1)
+ # ... mbarrier.init, fence, cta_sync, fill A_smem from global ...
+ tmem = T.decl_buffer([32, 16], "uint8", scope="tmem", allocated_addr=tmem_addr[0],
+ layout=TileLayout(S[(32, 16) : (1 @ TLane, 1 @ TCol)] + R[4 : 32 @ TLane]))
+ if tid_in_wg == 0:
+ Tx.copy_async(tmem[0:32, 0:16], A_smem[0:32, 0:16], cta_group=1) # smem -> tmem
+ T.ptx.tcgen05.commit(cp_mbar.ptr_to([0]), cta_group=1) # caller signals
+ T.ptx.mbarrier.try_wait(cp_mbar.ptr_to([0]), 0)
+ # ... readback via tcgen05.ld, then tcgen05.dealloc ...
+
+(The ``copy_async`` is auto-dispatched to the ``smem->tmem`` variant — the source is
+shared and the destination is the ``R[4:32@TLane]`` tmem buffer.)
+
+Algorithm
+---------
+
+**1. Verify the warpx4 router and re-order.** After slicing both layouts to the
+region, the dispatch confirms the tmem replica is ``R[4:32@TLane]``, permutes to
+TLane-first / TCol-stride-descending, isolates the broadcast, and groups the
+remaining iters into ``(32, middle, elem_per_128b)`` — the 32×128-bit atom plus a
+list of *middle* tiles to loop over.
+
+**2. Encode the matrix descriptor once.** A 64-bit shared descriptor (leading-dim
+offset ``ldo``, stride-dim offset ``sdo``, swizzle mode) is encoded right after the
+shared buffer is allocated, cached per ``(smem_buf, ldo, sdo, swizzle)``:
+
+.. code-block:: python
+
+ desc_buf = decl_buffer((1,), "uint64", scope="local")
+ T.ptx.tcgen05.encode_matrix_descriptor(desc_buf.data, s_buf.ptr_to([0, 0]), ldo, sdo, swizzle)
+
+**3. Issue the copy** — one ``tcgen05.cp`` for a single atom, or an unrolled loop
+that bumps the tmem column offset and the descriptor's 16-byte shared offset per
+middle tile:
+
+.. code-block:: python
+
+ if total == 1:
+ T.ptx.tcgen05.cp(t_addr[0] + t_col0,
+ smem_desc_add_16B_offset(desc_buf[0], init_off_16B),
+ shape="32x128b", cta_group=cta_group, multicast="warpx4")
+ else:
+ for flat in T.unroll(total):
+ t_off, s_off = T.meta_var(compute_offsets(flat))
+ T.ptx.tcgen05.cp(t_addr[0] + t_col0 + t_off,
+ smem_desc_add_16B_offset(desc_buf[0], init_off_16B + s_off),
+ shape="32x128b", cta_group=cta_group, multicast="warpx4")
+
+The dispatch emits **no** ``tcgen05.commit`` / ``wait`` — the caller commits against
+an mbarrier (as in the demo).
+
+Generated TIRx IR
+-----------------
+
+The ``32×16`` uint8 tile is a single atom (ldo=16, sdo=8, swizzle=0):
+
+.. code-block:: python
+
+ T.ptx.tcgen05.encode_matrix_descriptor(cp_desc.data, T.address_of(A_smem[0]), 16, 8, 0)
+ T.ptx.tcgen05.cp(tmem_addr[0],
+ smem_desc_add_16B_offset(cp_desc[0], 0),
+ shape="32x128b", cta_group=1, multicast="warpx4")
+
+Generated CUDA
+--------------
+
+.. code-block:: c++
+
+ // one warpx4 copy: shared (named by the matrix descriptor) -> tensor memory
+ "tcgen05.cp.cta_group::1.32x128b.warpx4 [%0], %1;" // [%0]=tmem addr, %1=descriptor
+
+(Compiled for ``sm_100a``. End-to-end correctness — including the tmem readback —
+is covered by ``test_smem_tmem.py``.)
+
+How inputs change the algorithm
+-------------------------------
+
+.. list-table::
+ :header-rows: 1
+ :widths: 28 72
+
+ * - input
+ - effect
+ * - dtype
+ - sets ``elem_per_128b = 128 / dtype_bits`` (uint8 → 16, uint32 → 4) and the
+ descriptor swizzle mode (atom K-byte ∈ {16, 32, 64, 128} → swizzle 0/1/2/3)
+ * - number of tiles
+ - ``total`` middle tiles: ``1`` → a single ``tcgen05.cp``; ``> 1`` → an
+ unrolled loop, each step bumping the tmem column and the descriptor's 16-B
+ shared offset
+ * - shared swizzle layout
+ - changes the encoded ``swizzle`` mode (must match the shared buffer's swizzle)
+ * - tmem layout (D vs F) / cta_group
+ - the permutation order sets per-tile column steps; ``cta_group`` selects the
+ multicast routing (``cta_group::1`` vs ``::2``)
+ * - atom shape
+ - fixed at ``32x128b`` ``warpx4`` — a different atom would need a new variant
diff --git a/docs/_sources/tirx/tile_primitives/copy_async/tcgen05_ldst.rst.txt b/docs/_sources/tirx/tile_primitives/copy_async/tcgen05_ldst.rst.txt
new file mode 100644
index 00000000000..ee5510d2c76
--- /dev/null
+++ b/docs/_sources/tirx/tile_primitives/copy_async/tcgen05_ldst.rst.txt
@@ -0,0 +1,172 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+copy_async → tcgen05_ldst
+=========================
+
+The ``tcgen05_ldst`` variant lowers a ``copy_async`` between **tensor memory and
+registers** (Blackwell ``tcgen05.ld`` / ``tcgen05.st``). It is warpgroup-collective:
+the four warps cooperatively move a tensor-memory tile to/from their per-thread
+registers. One registration handles both directions — ``tmem → local`` lowers to
+``tcgen05.ld``, ``local → tmem`` to ``tcgen05.st`` — and the dispatch picks the
+widest instruction shape the register layout matches. As with the other async
+variants, completion (``tcgen05.wait.ld`` / ``wait.st``) is the caller's. Source:
+``python/tvm/backend/cuda/operator/tile_primitive/copy_async/tcgen05_ldst.py``.
+
+What it accepts
+---------------
+
+A single registration (``variant="tmem<->local"``); direction is inferred at
+lowering:
+
+.. code-block:: python
+
+ @register_dispatch("copy_async", "cuda", variant="tmem<->local", priority=10, when=[
+ predicate("validate_copy_op", _is_valid_copy),
+ predicate("exec_scope", exec_scope_ok, expected_scopes=["warpgroup"]),
+ predicate("storage_scope", _scope_allowed,
+ allowed_pairs=[("tmem", "local"), ("local", "tmem")]),
+ ])
+ # direction inferred in copy_tmem_local_impl:
+ # src tmem + dst local -> "tmem2local" (ld); else "local2tmem" (st)
+
+.. list-table::
+ :header-rows: 1
+ :widths: 22 78
+
+ * - Property
+ - Requirement
+ * - target / priority
+ - ``cuda`` (Blackwell, sm_100+); priority ``10``
+ * - scope
+ - **warpgroup** (``exec_scope_ok(expected_scopes=["warpgroup"])``) — the four
+ warps act together
+ * - memory pair
+ - ``(tmem, local)`` or ``(local, tmem)`` — exactly one side is tensor memory
+ * - register layout
+ - matched against a ``tcgen05_atom_layout`` (``.16x64b`` / ``.16x128b`` /
+ ``.16x256b``) for the fast path; otherwise the ``.32x32b`` fallback
+ * - tmem datapath
+ - classified ``D`` (M=128 identity) or ``F`` (M=64 scattered) — sets how
+ fragment rows map to lanes
+
+Demonstration program
+----------------------
+
+A warpgroup round-trips a ``128×8`` ``float16`` tile registers → tmem → registers
+(the GPU smoke test ``test_copy_tmem2reg_async``; ``WIDTH = 8`` for ``width_32b=4``,
+fp16):
+
+.. code-block:: python
+
+ from tvm.tirx.layout import S, TCol, TileLayout, TLane
+ from tvm.tirx.layout import tid_in_wg as axis_tid_in_wg
+
+ local_view = TileLayout(S[(128, WIDTH) : (1 @ axis_tid_in_wg, 1)])
+
+ @T.prim_func
+ def copy_async_test(A_ptr: T.handle, B_ptr: T.handle):
+ A = T.match_buffer(A_ptr, (128, WIDTH), "float16"); B = T.match_buffer(B_ptr, (128, WIDTH), "float16")
+ T.device_entry()
+ warp_id = T.warp_id([4]); wg_id = T.warpgroup_id([1]); tid = T.thread_id([128])
+ tmem_addr = T.alloc_shared([1], "uint32")
+ if wg_id == 0:
+ if warp_id == 0:
+ T.ptx.tcgen05.alloc(T.address_of(tmem_addr), n_cols=32, cta_group=1)
+ T.tvm_storage_sync("shared")
+ tmem = T.decl_buffer((128, WIDTH), "float16", scope="tmem", allocated_addr=tmem_addr[0],
+ layout=TileLayout(S[(128, WIDTH) : (1 @ TLane, 1 @ TCol)]))
+ A_reg = T.alloc_local((WIDTH,), "float16"); B_reg = T.alloc_local((WIDTH,), "float16")
+ A_local = A_reg.view(128, WIDTH, layout=local_view)
+ B_local = B_reg.view(128, WIDTH, layout=local_view)
+ # ... load A into A_reg, zero B_reg, cta_sync ...
+ Tx.wg.copy_async(tmem[:, :], A_local[:, :]); T.ptx.tcgen05.wait.st() # store (local -> tmem)
+ T.cuda.cta_sync()
+ Tx.wg.copy_async(B_local[:, :], tmem[:, :]); T.ptx.tcgen05.wait.ld() # load (tmem -> local)
+ # ... write B_reg out; tcgen05.dealloc ...
+
+Algorithm
+---------
+
+**1. Infer direction.** ``tmem → local`` is a load (``tcgen05.ld``); ``local → tmem``
+is a store (``tcgen05.st``).
+
+**2. Pick the instruction shape.** The dispatch matches the register layout against
+``tcgen05_atom_layout`` for ``.16x64b`` / ``.16x128b`` / ``.16x256b``
+(``_match_tcgen05_atom_layout``); the matched shape sets the column factor (2/4/8
+fp32 columns) and the ``num`` count. If nothing matches it falls back to
+``.32x32b`` and probes ``num ∈ {1, 2, 4, 8, …}`` against the column width.
+
+**3. Issue per datapath slab.** For an M=128 ``.16x*b`` copy the fragment spans two
+16-row slabs, so the warps issue the atom twice (``row = 0`` and ``row = 16``); the
+``.32x32b`` path covers M=128 in a single issue (``row = 0``):
+
+.. code-block:: python
+
+ op = T.ptx.tcgen05.ld if load else T.ptx.tcgen05.st
+ for slab in range(n_slabs): # 1 for .32x32b / M=64; 2 for .16x*b M=128
+ op(tmem_buf.allocated_addr[0],
+ *[local_32b[reg_base + i] for i in range(regs_eff)],
+ shape=shape, num=num_eff, row=slab * 16, col=col_off_32b)
+
+The dispatch emits **no** wait — the caller issues ``tcgen05.wait.ld()`` /
+``wait.st()`` (as in the demo).
+
+Generated TIRx IR
+-----------------
+
+For the ``128×8`` fp16 tile the layout takes the ``.32x32b`` path with ``num = 4``
+(4 registers per thread), one issue each way:
+
+.. code-block:: python
+
+ T.ptx.tcgen05.st(tmem_addr[0], 0, 0, "32x32b", 4, False, local_32b[0], local_32b[1],
+ local_32b[2], local_32b[3]) # local -> tmem
+ T.ptx.tcgen05.ld(tmem_addr[0], 0, 0, "32x32b", 4, False, local_32b_1[0], local_32b_1[1],
+ local_32b_1[2], local_32b_1[3]) # tmem -> local
+
+Generated CUDA
+--------------
+
+.. code-block:: c++
+
+ "tcgen05.st.sync.aligned.32x32b.x4.b32 ..." // 4 registers -> tmem
+ "tcgen05.ld.sync.aligned.32x32b.x4.b32 ..." // tmem -> 4 registers
+
+Verified end-to-end on ``sm_100a`` (the round trip reproduces the input exactly).
+
+How inputs change the algorithm
+-------------------------------
+
+.. list-table::
+ :header-rows: 1
+ :widths: 28 72
+
+ * - input
+ - effect
+ * - register layout
+ - matches a ``.16x64b`` / ``.16x128b`` / ``.16x256b`` atom → that shape; no
+ match → the ``.32x32b`` fallback (this demo)
+ * - column width / dtype
+ - sets ``num`` (the ``.xN`` count) and the registers per thread
+ (``elem_per_32b = 32 / dtype_bits``)
+ * - direction
+ - ``tmem → local`` → ``tcgen05.ld``; ``local → tmem`` → ``tcgen05.st`` (same
+ shape/num logic)
+ * - datapath D vs F
+ - ``D`` (M=128) covers all 128 rows; an M=128 ``.16x*b`` copy issues two slabs
+ (``row = 0`` / ``row = 16``); ``F`` (M=64) scatters rows to lanes
diff --git a/docs/_sources/tirx/tile_primitives/copy_async/tma.rst.txt b/docs/_sources/tirx/tile_primitives/copy_async/tma.rst.txt
new file mode 100644
index 00000000000..5de6ed7f1b7
--- /dev/null
+++ b/docs/_sources/tirx/tile_primitives/copy_async/tma.rst.txt
@@ -0,0 +1,200 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+copy_async → tma
+================
+
+The ``tma`` variant lowers ``copy_async`` between **global and shared** to the
+hardware **Tensor Memory Accelerator**: a single elected thread issues a
+descriptor-driven bulk copy (``cp.async.bulk.tensor``), and the hardware walks the
+multi-dimensional tile described by a ``cuTensorMap``. The descriptor is built once
+on the host (``cuTensorMapEncodeTiled``); the device only *issues* the copy — the
+hardware signals the caller's mbarrier when the transfer completes (the dispatch
+itself emits no completion op). Source:
+``python/tvm/backend/cuda/operator/tile_primitive/copy_async/tma.py``.
+
+What it accepts
+---------------
+
+The dispatch registers two predicates — a valid copy and a **single-thread** scope:
+
+.. code-block:: python
+
+ # register_dispatch(..., priority=10, when=[
+ predicate("validate_copy_op", lambda op, sctx: (validate_copy_op(op, sctx), "not a valid copy op")),
+ predicate("single_thread", lambda op, sctx: (single_thread(op, sctx), "expected single thread")),
+ # ])
+
+ def single_thread(op_call, sctx):
+ return sctx.is_thread # exactly one elected thread issues the TMA
+
+.. list-table::
+ :header-rows: 1
+ :widths: 22 78
+
+ * - Property
+ - Requirement
+ * - target / priority
+ - ``cuda``; priority ``10`` (the bulk path for ``copy_async`` global ↔ shared)
+ * - scope
+ - **single thread** (``sctx.is_thread``) — TMA is issued by one thread, not a
+ partitioned warp
+ * - direction
+ - ``global → shared`` (g2s) or ``shared → global`` (s2g), inferred from the
+ buffer scopes at lowering
+ * - dtype / shape
+ - ``validate_copy_op``: both sides have layouts, equal dtype, equal non-unit
+ extents
+ * - layout
+ - must form a legal descriptor: rank ≤ 5, innermost stride 1, innermost box
+ fits the shared swizzle atom (else the plan search shrinks / declines)
+
+Demonstration program
+----------------------
+
+One thread bulk-copies an ``8×256`` ``float16`` tile global → shared (with a
+128-byte swizzled shared layout), signals an mbarrier, waits, then reads it back
+(mirrors ``test_tma.py``'s G2S smoke test):
+
+.. code-block:: python
+
+ from tvm.tirx.cuda.operator.tile_primitive.tma_utils import mma_shared_layout
+
+ g_shape = s_shape = (8, 256); dtype = "float16"
+ shared_layout = mma_shared_layout(dtype, 3, (8, 256)) # 128-B swizzle
+ smem_bytes = 8 * 256 * 2
+
+ @T.prim_func
+ def copy_async(A_ptr: T.handle, B_ptr: T.handle):
+ A = T.match_buffer(A_ptr, g_shape, dtype, layout=TileLayout(S[8, 256]))
+ B = T.match_buffer(B_ptr, g_shape, dtype, layout=TileLayout(S[8, 256]))
+ T.device_entry(); T.cta_id([1]); tid = T.thread_id([8])
+ dyn = T.alloc_buffer([smem_bytes + 8], "uint8", scope="shared.dyn") # arena
+ A_smem = T.decl_buffer(s_shape, dtype, dyn.data, elem_offset=0, layout=shared_layout)
+ mbarrier = T.decl_buffer([1], "uint64", dyn.data, elem_offset=smem_bytes // 8)
+ phase: T.int32 = 0
+ if tid == 0:
+ T.ptx.mbarrier.init(mbarrier.ptr_to([0]), 1)
+ T.ptx.fence.proxy_async("shared::cta"); T.cuda.cta_sync()
+ if tid == 0:
+ Tx.copy_async(A_smem[0:8, 0:256], A[0:8, 0:256], dispatch="tma", mbar=mbarrier.ptr_to([0]))
+ T.ptx.mbarrier.arrive.expect_tx(mbarrier.ptr_to([0]), smem_bytes)
+ T.ptx.mbarrier.try_wait(mbarrier.ptr_to([0]), phase)
+ T.ptx.fence.proxy_async("shared::cta"); T.cuda.cta_sync()
+ Tx.cta.copy(B[0:8, 0:256], A_smem[0:8, 0:256])
+
+Algorithm
+---------
+
+**1. Infer direction from scopes.** ``global → shared`` is g2s, ``shared → global``
+is s2g (anything else is an error):
+
+.. code-block:: python
+
+ if src.scope() == "global" and dst.scope().startswith("shared"):
+ direction, s_buf, g_buf = "g2s", dst, src
+ elif src.scope().startswith("shared") and dst.scope() == "global":
+ direction, s_buf, g_buf = "s2g", src, dst
+
+**2. Plan the descriptor (L1 → L2 → L3).** The dispatch canonicalizes both
+layouts (L1), then for each global iter finds the maximal contiguous stride-1 shard
+chain and cuts the axis into descriptor **box** segments (L2), then stacks those
+into a ``cuTensorMap`` and validates the hardware constraints — rank ≤ 5, innermost
+stride 1, innermost box fits the shared swizzle atom — shrinking the chain prefix
+and retrying if a constraint fails (L3). Adjacent fully-boxed contiguous dims are
+merged, and an over-256 box may trigger element-type promotion.
+
+**3. Emit the host descriptor once,** keyed by a cache so a repeated copy reuses it:
+
+.. code-block:: python
+
+ T.call_packed("runtime.cuTensorMapEncodeTiled", tensormap, dtype_str, rank,
+ tensor_ptr, *reversed(shape), *reversed(strides[:-1]),
+ *reversed(box_dim), *element_strides, 0, swizzle_mode, 2, oob_fill)
+
+**4. Emit the device issue loop** — an unrolled loop over the issue axes, one
+``cp.async.bulk.tensor`` per step, direction-specific:
+
+.. code-block:: python
+
+ if direction == "g2s":
+ T.ptx.cp_async.bulk.tensor.g2c(plan.rank, s_buf.ptr_to(s_st), mbar,
+ T.address_of(tensor_map), cta_mask, cta_group,
+ cache_hint, *tma_coords)
+ else:
+ T.ptx.cp_async.bulk.tensor.s2g(plan.rank, s_buf.ptr_to(s_st),
+ T.address_of(tensor_map), cache_hint, *tma_coords)
+
+Like all ``copy_async`` variants the dispatch emits no completion — the caller's
+mbarrier ``arrive.expect_tx`` / ``try_wait`` (g2s) close the loop.
+
+Generated TIRx IR
+-----------------
+
+The ``8×256`` swizzled tile produces a **rank-3** descriptor and a single issue:
+
+.. code-block:: python
+
+ # host (once): encode the tensor map (rank 3, reversed shape/box/strides, swizzle 3)
+ T.call_packed("runtime.cuTensorMapEncodeTiled", A_ptr_tensormap, "float16", 3,
+ A.data, 64, 8, 4, 512, 128, 64, 8, 4, 1, 1, 1, 0, 3, 2, 0)
+ # device:
+ for loop_vars in T.unroll(1):
+ T.ptx.cp_async.bulk.tensor.g2c(3, T.address_of(s_buf_w_offset[0]),
+ T.address_of(mbarrier[0]),
+ T.address_of(A_ptr_tensormap), 0, 1, ..., 0, 0, 0)
+
+Generated CUDA
+--------------
+
+.. code-block:: c++
+
+ // one TMA instruction copies the whole rank-3 tile, async, into shared
+ "cp.async.bulk.tensor.3d.shared::cluster.global.mbarrier::complete_tx::bytes"
+ ".cta_group::1 [%0], [%1, {%3, %4, %5}], [%2];"
+ // call: ptx_cp_async_bulk_tensor_g2cluster_tile_3d(smem, mbar, tensormap, coords...)
+
+The three ``{%3, %4, %5}`` are the descriptor coordinates; ``[%1]`` is the
+tensor-map address, ``[%2]`` the mbarrier. One thread launches the entire 8×256
+copy. (This was compiled for ``sm_100a`` — Blackwell — so the instruction carries
+the ``.cta_group::1`` qualifier; on Hopper the qualifier is omitted.)
+
+How inputs change the algorithm
+-------------------------------
+
+.. list-table::
+ :header-rows: 1
+ :widths: 26 74
+
+ * - input
+ - effect
+ * - direction
+ - ``g2s`` → ``cp.async.bulk.tensor.*.g2c``; ``s2g`` → ``…s2g``; with a reduce
+ op → ``…s2g_reduce`` (e.g. ``add``)
+ * - shared swizzle mode
+ - sets the ``swizzle_mode`` in the descriptor and the innermost-box constraint;
+ a 128-B swizzle on a 2-D tile yields a **rank-3** descriptor (the inner axis
+ splits into swizzle atoms), as in the demo
+ * - box shape / chain prefix
+ - more selected stride-1 shards → more box>1 descriptor dims; merge collapses
+ contiguous full-box dims; box > 256 triggers dtype promotion (1→2→4→8 B)
+ * - dtype
+ - sets element size and the descriptor's element strides / box byte width
+
+A copy whose layout cannot form a legal descriptor (rank > 5 after shrinking, or no
+swizzle-atom-aligned innermost box) makes the plan search fail and the variant
+declines.
diff --git a/docs/_sources/tirx/tile_primitives/elementwise.rst.txt b/docs/_sources/tirx/tile_primitives/elementwise.rst.txt
new file mode 100644
index 00000000000..4b6bf010547
--- /dev/null
+++ b/docs/_sources/tirx/tile_primitives/elementwise.rst.txt
@@ -0,0 +1,48 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+elementwise
+===========
+
+Covers ``cast``, ``fill``, the unary ops (``zero``, ``reciprocal``, ``sqrt``,
+``exp``, ``exp2``, ``silu``), the binary ops (``add``, ``sub``, ``mul``,
+``fdiv``), and ``fma``. Every op registers **two** variants — ``reg`` and
+``smem`` — both at priority 10; the operand storage scope (all-register vs
+all-shared) is the mutually-exclusive discriminator. Each op is described by an
+``OpSpec`` (a ``parse`` that builds the destination + source list, optional dtype
+checks, and the scalar expression applied per element).
+
+.. list-table::
+ :header-rows: 1
+ :widths: 24 18 58
+
+ * - Variant
+ - Operands
+ - Lowering
+ * - :doc:`elementwise/reg`
+ - all register
+ - partition induced by the register layout; op applied per register
+ * - :doc:`elementwise/smem`
+ - all shared
+ - synthesized ``[outer, threads, vec]`` partition; op applied per (vectorized)
+ element
+
+.. toctree::
+ :maxdepth: 1
+
+ elementwise/reg
+ elementwise/smem
diff --git a/docs/_sources/tirx/tile_primitives/elementwise/reg.rst.txt b/docs/_sources/tirx/tile_primitives/elementwise/reg.rst.txt
new file mode 100644
index 00000000000..2deceb03eb5
--- /dev/null
+++ b/docs/_sources/tirx/tile_primitives/elementwise/reg.rst.txt
@@ -0,0 +1,133 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+elementwise → reg
+=================
+
+The ``reg`` variant lowers an elementwise op (``sqrt``, ``exp``, ``add``,
+``fma``, …) when **all operands are register** (``local``) buffers. Like the copy
+:doc:`../copy/reg` variant the partition is *induced* by the operands' register
+layout — the thread axes are dropped, leaving each thread its private bundle — and
+the op is applied to every register in that bundle. Source:
+``python/tvm/backend/cuda/operator/tile_primitive/elementwise/reg.py``.
+
+What it accepts
+---------------
+
+``is_reg_ewise(spec)`` builds the predicate:
+
+.. code-block:: python
+
+ def check(op_call, sctx):
+ if not sctx.is_target("cuda"): return False, "non-cuda target"
+ if sctx.scope_kind not in ("thread", "warp", "warpgroup", "cta"): ...
+ ok, reason = _all_threads_active(sctx)
+ plan, msg = spec.parse(op_call)
+ for br in buffer_regions(plan):
+ if br.buffer.scope() != "local": # every operand register
+ return False, f"operand scope {br.buffer.scope()} != local"
+ if br.buffer.layout is None: ...
+ # + spec.check_extras (dtype rules), pick_anchor + _validate_anchor_layout,
+ # _validate_scope_level_anchor
+
+.. list-table::
+ :header-rows: 1
+ :widths: 22 78
+
+ * - Property
+ - Requirement
+ * - target / scope / priority
+ - ``cuda``; ``thread`` / ``warp`` / ``warpgroup`` / ``cta`` (all active);
+ priority ``10``
+ * - operands
+ - **every** operand in ``local`` (registers)
+ * - op
+ - any registry op (unary / binary / ``fma``); ``spec.check_extras`` validates
+ the dtype combo
+ * - register layout
+ - the anchor register layout must validate, and its thread axis must match the
+ scope (it induces the partition)
+
+Demonstration program
+----------------------
+
+A warp takes the elementwise ``sqrt`` of a ``32×8`` ``float32`` register tile
+(register layout ``S[(32,8):(1@laneid,1)]`` — lane ``i`` owns row ``i``):
+
+.. code-block:: python
+
+ from tvm.tirx.layout import S, TileLayout, laneid
+
+ r_layout = TileLayout(S[(32, 8) : (1 @ laneid, 1)]); fs = (slice(0, 32), slice(0, 8))
+
+ @T.prim_func
+ def k(A_ptr: T.handle, B_ptr: T.handle):
+ A = T.match_buffer(A_ptr, (32, 8), "float32"); B = T.match_buffer(B_ptr, (32, 8), "float32")
+ T.device_entry(); T.cta_id([1]); T.lane_id([32]); tid = T.thread_id([32])
+ A_smem = T.alloc_buffer((32, 8), "float32", scope="shared", layout=TileLayout(S[(32, 8)]))
+ Tx.warp.copy(A_smem[fs], A[fs]); T.cuda.cta_sync()
+ R = T.alloc_buffer((32, 8), "float32", scope="local", layout=r_layout)
+ Tx.warp.copy(R[fs], A_smem[fs])
+ Tx.warp.sqrt(R[fs], R[fs]) # elementwise reg dispatch
+ Tx.warp.copy(A_smem[fs], R[fs]); T.cuda.cta_sync()
+ Tx.warp.copy(B[fs], A_smem[fs])
+
+Algorithm
+---------
+
+**1. Parse and check.** ``spec.parse`` builds the op plan; the predicate confirms
+every operand is a register buffer and the anchor register layout is valid.
+
+**2. Induce the partition** from the anchor's thread axis (``laneid`` here): drop
+the thread iters, leaving each thread its private bundle (8 elements per lane).
+
+**3. Apply the op per register** — a per-thread loop over the bundle:
+
+Generated TIRx IR
+-----------------
+
+.. code-block:: python
+
+ buffer[f] = T.sqrt(buffer_1[f]) # over each register f in the lane's bundle
+
+Generated CUDA
+--------------
+
+.. code-block:: c++
+
+ r_local_ptr[f_2] = sqrtf(r_local_ptr[f_2]); // per-register, private to the lane
+
+(Verified on ``sm_100a`` — the result equals ``sqrt(A)``.)
+
+How inputs change the algorithm
+-------------------------------
+
+.. list-table::
+ :header-rows: 1
+ :widths: 28 72
+
+ * - input
+ - effect
+ * - op
+ - unary → ``sqrtf`` / ``expf`` / … per register; binary → ``a + b`` per
+ register; ``fma`` → ``a * b + c``
+ * - dtype
+ - the register element type (``sqrtf`` vs ``hsqrt`` etc.); the bundle size is
+ the per-lane element count
+ * - register layout
+ - the anchor's thread axis sets the partition; a wider per-lane bundle means a
+ longer loop
diff --git a/docs/_sources/tirx/tile_primitives/elementwise/smem.rst.txt b/docs/_sources/tirx/tile_primitives/elementwise/smem.rst.txt
new file mode 100644
index 00000000000..4bf5e8b5f06
--- /dev/null
+++ b/docs/_sources/tirx/tile_primitives/elementwise/smem.rst.txt
@@ -0,0 +1,136 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+elementwise → smem
+==================
+
+The ``smem`` variant lowers an elementwise op (``sqrt``, ``exp``, ``add``,
+``fma``, …) when **all operands are in shared memory**. Like the copy
+:doc:`../copy/gmem_smem` variant it *synthesizes* a ``[outer, threads, vec]``
+partition from the execution scope, then applies the op to each (vectorized)
+element. Source:
+``python/tvm/backend/cuda/operator/tile_primitive/elementwise/smem.py``.
+
+What it accepts
+---------------
+
+``is_smem_ewise(spec)`` builds the predicate:
+
+.. code-block:: python
+
+ def check(op_call, sctx):
+ if not sctx.is_target("cuda"): return False, "non-cuda target"
+ if sctx.scope_kind not in ("thread", "warp", "warpgroup", "cta"): ...
+ ok, reason = _all_threads_active(sctx) # full scope
+ plan, msg = spec.parse(op_call) # parse the op's operands
+ for br in buffer_regions(plan):
+ if not br.buffer.scope().startswith("shared"): # every operand shared*
+ return False, f"operand scope {br.buffer.scope()} != shared*"
+ if br.buffer.layout is None: ...
+ # + spec.check_extras (dtype rules) and anchor-layout validation
+
+.. list-table::
+ :header-rows: 1
+ :widths: 22 78
+
+ * - Property
+ - Requirement
+ * - target / scope / priority
+ - ``cuda``; ``thread`` / ``warp`` / ``warpgroup`` / ``cta`` (all active);
+ priority ``10``
+ * - operands
+ - **every** operand (inputs and output) in ``shared*``
+ * - op
+ - any op in the registry (unary ``sqrt``/``exp``/``zero``…, binary
+ ``add``/``mul``…, ``fma``); ``spec.check_extras`` validates the dtype combo
+ * - layout
+ - operands have layouts; the layout sets the **vector width** (the partition
+ itself is synthesized from the scope's thread count, not the layout)
+
+Demonstration program
+----------------------
+
+A CTA takes the elementwise ``sqrt`` of a ``32×32`` ``float32`` shared tile
+(adapted from ``test_unary.py`` — here a 256-thread CTA, so the partition is one
+round):
+
+.. code-block:: python
+
+ s_layout = TileLayout(S[(32, 32)]); full = (slice(0, 32), slice(0, 32))
+
+ @T.prim_func
+ def unary_op(A_ptr: T.handle):
+ A = T.match_buffer(A_ptr, (32, 32), "float32", layout=s_layout)
+ T.device_entry(); T.cta_id([1]); T.warp_id([8]); T.lane_id([32]); T.thread_id([256])
+ A_smem = T.alloc_buffer((32, 32), "float32", scope="shared", layout=s_layout)
+ Tx.cta.copy(A_smem[full], A[full])
+ Tx.cta.sqrt(A_smem[full], A_smem[full]) # elementwise smem dispatch
+ Tx.cta.copy(A[full], A_smem[full])
+
+Algorithm
+---------
+
+**1. Parse the op and check operands.** ``spec.parse`` turns the call into a plan
+(inputs, output, the op); the predicate confirms every operand is shared.
+
+**2. Synthesize the partition** from the scope's **thread count** (as
+:doc:`../copy/gmem_smem` does): split the region into ``[outer, threads, vec]``,
+with the vector width taken from the layout's innermost contiguous run. For
+``32×32 = 1024`` ``float32`` over 256 threads, ``vec = 4`` ⇒ ``outer = 1``.
+
+**3. Apply the op per element.** Instead of a copy, each (thread, round) reads its
+``vec`` elements, applies the op, and writes back — vectorized:
+
+Generated TIRx IR
+-----------------
+
+.. code-block:: python
+
+ for f in range(1): # outer = 1
+ A_smem[tid * 4 + vec] = T.sqrt(A_smem[tid * 4 + vec])
+
+Generated CUDA
+--------------
+
+The ``vec = 4`` element bundle becomes a ``float4`` and the op is applied per
+component:
+
+.. code-block:: c++
+
+ float4 v_ = *(float4*)(&A_smem_ptr[tid * 4]);
+ __1.x = sqrtf(v_.x); __1.y = sqrtf(v_.y);
+ __1.z = sqrtf(v_.z); __1.w = sqrtf(v_.w);
+
+(Verified on ``sm_100a`` — the tile equals ``sqrt(A)``.)
+
+How inputs change the algorithm
+-------------------------------
+
+.. list-table::
+ :header-rows: 1
+ :widths: 28 72
+
+ * - input
+ - effect
+ * - op
+ - unary → ``sqrtf`` / ``expf`` / … per component; binary → the two inputs
+ combined (``a + b``); ``fma`` → ``a * b + c``
+ * - dtype
+ - sets the vector width (``vec = widest aligned`` ⇒ the round count), as in
+ :doc:`../copy/gmem_smem`
+ * - scope
+ - sets the thread axis and count, hence the synthesized partition
diff --git a/docs/_sources/tirx/tile_primitives/gemm.rst.txt b/docs/_sources/tirx/tile_primitives/gemm.rst.txt
new file mode 100644
index 00000000000..e737621dcb6
--- /dev/null
+++ b/docs/_sources/tirx/tile_primitives/gemm.rst.txt
@@ -0,0 +1,176 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+gemm
+====
+
+``gemm`` computes ``D = alpha·A@B + beta·C`` at **warp** scope as a fully-unrolled
+nest of warp-collective ``mma.sync.aligned.m16n8k{16,8}`` instructions. A and B
+fragments and the C/D accumulators **all live in registers** — the caller stages A
+and B into register fragments first (typically via :doc:`copy/ldstmatrix`). The
+dispatch tiles M/N/K into ``m16n8k`` atoms and emits one ``mma`` per output tile,
+accumulating over K in place. Source:
+``python/tvm/backend/cuda/operator/tile_primitive/gemm/mma_m16n8k_.py``. (For the
+Blackwell async tensor-core path see :doc:`gemm_async`.)
+
+What it accepts
+---------------
+
+.. code-block:: python
+
+ # register_dispatch("gemm", "cuda", priority=10, when=[
+ predicate("full_active_lanes", _full_active_lanes), # whole warp, un-narrowed
+ predicate("no_replica", _no_replica), # no broadcast axes on D/A/B/C
+ # ])
+ # in the impl:
+ for buf, name in ((D, "D"), (A, "A"), (B, "B"), (C, "C")):
+ if buf.scope() != "local":
+ fail(f"gemm mma requires {name} in register (local) scope, got {buf.scope()}")
+
+.. list-table::
+ :header-rows: 1
+ :widths: 22 78
+
+ * - Property
+ - Requirement
+ * - target / scope / priority
+ - ``cuda``; **warp** (``mma.sync`` is warp-collective — all 32 lanes active,
+ ``_full_active_lanes``); priority ``10``
+ * - operand scope
+ - **A, B, C, D all in registers** (``local``); a shared operand makes the
+ dispatch ``fail`` (stage with ldmatrix first)
+ * - no replica
+ - none of D/A/B/C may carry a broadcast/replica axis (``_no_replica``)
+ * - shape
+ - ``M % 16 == 0``, ``N % 8 == 0``, ``K % 8`` (k8) or ``% 16`` (k16) — each
+ dim must tile into the m16n8k fragment frame
+ * - dtype
+ - inputs ``float16`` / ``bfloat16``; accumulator ``float32``
+ * - alpha / beta
+ - ``alpha == 1.0``; ``beta ∈ {0.0, 1.0}`` (0 → ``D = A@B``; 1 → ``D = A@B + C``)
+
+Demonstration program
+----------------------
+
+A single warp computes ``D[16,8] = A[16,16] @ B[16,8]`` in ``float16`` (f32
+accumulate) — one ``m16n8k16`` atom (from ``test_gemm_mma_m16n8k_.py``):
+
+.. code-block:: python
+
+ from tvm.tirx.layout import S, TileLayout, laneid
+
+ D_FRAG = TileLayout(S[(2, 8, 4, 2) : (2, 4 @ laneid, 1 @ laneid, 1)])
+ A_FRAG_K8 = TileLayout(S[(2, 8, 4, 2) : (2, 4 @ laneid, 1 @ laneid, 1)])
+ B_FRAG_K8 = TileLayout(S[(4, 2, 8) : (1 @ laneid, 1, 4 @ laneid)])
+ A_FRAG = A_FRAG_K8.tile_to([16, 16], [16, 8]); B_FRAG = B_FRAG_K8.tile_to([16, 8], [8, 8])
+
+ @T.prim_func
+ def gemm(A_ptr: T.handle, B_ptr: T.handle, D_ptr: T.handle):
+ A_g = T.match_buffer(A_ptr, (16, 16), "float16"); B_g = T.match_buffer(B_ptr, (16, 8), "float16")
+ D_g = T.match_buffer(D_ptr, (16, 8), "float32")
+ T.device_entry(); T.cta_id([1]); T.warp_id([1]); lane = T.lane_id([32])
+ A_f = T.alloc_buffer((16, 16), "float16", scope="local", layout=A_FRAG)
+ B_f = T.alloc_buffer((16, 8), "float16", scope="local", layout=B_FRAG)
+ D_f = T.alloc_buffer((16, 8), "float32", scope="local", layout=D_FRAG)
+ A_reg = A_f.local(8) # stage A into the lane's 8 regs
+ for s in T.unroll(8):
+ kp, kHi, rM = s % 2, (s // 2) % 2, s // 4
+ A_reg[s] = A_g[lane // 4 + 8 * rM, 2 * (lane % 4) + kp + 8 * kHi]
+ B_reg = B_f.local(4) # stage B into the lane's 4 regs
+ for s in T.unroll(4):
+ kp, kHi = s % 2, s // 2
+ B_reg[s] = B_g[2 * (lane % 4) + kp + 8 * kHi, lane // 4]
+ Tx.warp.gemm(D_f, A_f, B_f, D_f, transpose_A=False, transpose_B=False, alpha=1.0, beta=0.0)
+ D_reg = D_f.local(4) # write the 4 result regs out
+ for s in T.unroll(4):
+ rN, rM = s % 2, s // 2
+ D_g[lane // 4 + 8 * rM, 2 * (lane % 4) + rN] = D_reg[s]
+
+Algorithm
+---------
+
+**1. Tile and fragment-group.** The dispatch slices each operand's layout to its
+region and, for each candidate instruction (``m16n8k16`` then ``m16n8k8``), tries to
+group the operand sub-layouts (``D_M, D_N, A_M, A_K, B_K, B_N, C_*``) into the fixed
+m16n8k frame, anchoring A/C on D's M, B/C on D's N, and B on A's K. The first
+instruction that fits, with matching warp-tiling, wins.
+
+**2. Derive register layouts.** Each operand gets a per-lane register view: D/C as
+``[Mo, No, rM, rN]`` (4 f32), A as ``[Mo, Ko, rM, kHi, k_pack]``, B as
+``[Ko, No, kHi, k_pack]`` — the exact register order ``mma.sync`` expects.
+
+**3. Emit the unrolled nest** — initialize D (from C if ``beta==1``, else 0), then
+accumulate over K in place, one ``mma`` per (m, n) tile:
+
+.. code-block:: python
+
+ for m in T.unroll(M_tiles):
+ for n in T.unroll(N_tiles):
+ for rM, rN in ...: d_local[m, n, rM, rN] = c_local[...] if use_c else T.float32(0)
+ for k in T.unroll(K_tiles):
+ d_ptrs = [d_local.ptr_to([m, n, rM, rN]) for rM in range(2) for rN in range(2)] # 4 f32
+ a_ptrs = [a_local.ptr_to([m, k, rM, kHi, 0]) for kHi in range(n_kHi) for rM in range(2)]
+ b_ptrs = [b_local.ptr_to([k, n, kHi, 0]) for kHi in range(n_kHi)]
+ T.ptx.mma(shape_str, "row", "col", "float32", a_type, b_type, "float32",
+ d_ptrs, a_ptrs, b_ptrs, d_ptrs) # d = a·b + d
+
+Generated TIRx IR
+-----------------
+
+The single 16×8×16 tile lowers to one ``mma`` (4 D regs, 4 A regs, 2 B regs):
+
+.. code-block:: python
+
+ T.ptx.mma("m16n8k16", "row", "col", "float32", "float16", "float16", "float32",
+ 4, 4, 2, 4, False, T.address_of(d_local[0]), ...)
+
+Generated CUDA
+--------------
+
+.. code-block:: c++
+
+ "mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 "
+ "{%0, %1, %2, %3}, {%4, %5, %6, %7}, {%8, %9}, {%0, %1, %2, %3};"
+
+The accumulator ``{%0..%3}`` is both the C input and the D output (in-place
+accumulate); ``{%4..%7}`` are A's four ``b32`` registers, ``{%8, %9}`` B's two.
+Verified on ``sm_100a`` (``D == A@B`` within fp16 tolerance).
+
+How inputs change the algorithm
+-------------------------------
+
+.. list-table::
+ :header-rows: 1
+ :widths: 28 72
+
+ * - input
+ - effect
+ * - input dtype
+ - ``float16`` → ``…f32.f16.f16.f32``; ``bfloat16`` → ``…f32.bf16.bf16.f32``
+ (register counts unchanged — 2 elems per ``b32``)
+ * - K instruction
+ - ``k16`` → A 4 ``b32`` / B 2 ``b32``; ``k8`` → A 2 / B 1
+ (``mma.…m16n8k8.…``)
+ * - M / N / K extents
+ - set the ``M_tiles`` / ``N_tiles`` / ``K_tiles`` unrolled loop counts (one
+ ``mma`` per (m, n), K accumulated in place)
+ * - beta
+ - ``0`` → D zero-initialized; ``1`` → D initialized from C (the ``mma`` itself
+ is identical)
+ * - operand scope
+ - A/B **must** be register fragments; a shared operand makes the dispatch
+ ``fail`` (stage via :doc:`copy/ldstmatrix` first)
diff --git a/docs/_sources/tirx/tile_primitives/gemm_async.rst.txt b/docs/_sources/tirx/tile_primitives/gemm_async.rst.txt
new file mode 100644
index 00000000000..1f784f5c2bb
--- /dev/null
+++ b/docs/_sources/tirx/tile_primitives/gemm_async.rst.txt
@@ -0,0 +1,175 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+gemm_async
+==========
+
+``gemm_async`` lowers a matrix multiply to the **Blackwell asynchronous
+tensor-core** instruction ``tcgen05.mma``. The A and B operands live in **shared
+memory** (named by 64-bit *matrix descriptors*), the accumulator lives in **tensor
+memory**, and one elected thread launches the MMA, which runs asynchronously; the
+caller signals completion with ``tcgen05.commit`` against an mbarrier. It also
+supports **block-scaled** low precision (fp8 / fp4 with per-block scale factors
+``SFA`` / ``SFB`` in tensor memory). Source:
+``python/tvm/backend/cuda/operator/tile_primitive/gemm_async/tcgen05.py``. (For the
+synchronous warp-register path see :doc:`gemm`.)
+
+What it accepts
+---------------
+
+A single predicate — single-thread or warp scope:
+
+.. code-block:: python
+
+ # register_dispatch("gemm_async", "cuda", priority=10, when=[
+ predicate("single_thread_or_warp",
+ lambda op, sctx: (single_thread(op, sctx) or sctx.is_warp,
+ f"unsupported exec_scope {sctx.exec_scope}"))
+ # ])
+
+.. list-table::
+ :header-rows: 1
+ :widths: 22 78
+
+ * - Property
+ - Requirement
+ * - target / scope / priority
+ - ``cuda`` (Blackwell, sm_100+); **single thread or warp**; priority ``10``
+ * - operands
+ - A, B in **shared** (B always; A shared, or tmem for the TMEM-A path); the
+ accumulator **C/D in tmem** (``float32``)
+ * - dtype
+ - regular: A/B ``float16`` / ``bfloat16``; block-scaled: A/B
+ ``float8_e4m3fn`` / ``float4_e2m1fn`` with ``SFA`` / ``SFB`` scale factors in
+ tmem; accumulator always ``float32``
+ * - shape
+ - ``M ∈ {64, 128}`` (×2 for cta_group=2); ``N`` divisible by 8 (cta_group=1) or
+ 16 (cta_group=2); ``K`` divisible by ``MMA_K`` = 16 (f16/bf16) / 32 (fp8) /
+ 64 (fp4)
+ * - cta_group
+ - ``1`` (one CTA) or ``2`` (two CTAs split the operand)
+
+Demonstration program
+----------------------
+
+A warpgroup multiplies a ``128×64`` × ``64×128`` ``float16`` tile (f32 accumulate)
+into a tmem accumulator, after TMA-loading A/B into shared (from
+``test_gemm_async.py``; setup/readback abbreviated):
+
+.. code-block:: python
+
+ from tvm.tirx.layout import S, TCol, TLane, TileLayout, tid_in_wg as axis_tid_in_wg
+ from tvm.tirx.cuda.operator.tile_primitive.tma_utils import mma_shared_layout
+
+ A_smem = T.alloc_buffer((3,128,64), "float16", scope="shared", layout=mma_shared_layout("float16", 3, (3,128,64)))
+ B_smem = T.alloc_buffer((3,128,64), "float16", scope="shared", layout=mma_shared_layout("float16", 3, (3,128,64)))
+ tmem_addr = T.alloc_shared([1], "uint32"); mma_mbar = T.alloc_shared([1], "uint64")
+ # ... mbarrier.init, cta_sync ...
+ if warp_id == 0:
+ T.ptx.tcgen05.alloc(T.address_of(tmem_addr), n_cols=512, cta_group=1)
+ T.cuda.cta_sync()
+ tmem = T.decl_buffer((128, 512), "float32", scope="tmem", allocated_addr=tmem_addr[0],
+ layout=TileLayout(S[(128, 512) : (1 @ TLane, 1 @ TCol)]))
+ # ... TMA-load A_smem, B_smem from global, wait ...
+ if tid_in_wg == 0:
+ Tx.gemm_async(tmem[0:128, 256:384], A_smem[1:2, :, :], B_smem[2:3, :, :], dispatch="tcgen05")
+ T.ptx.tcgen05.commit(mma_mbar.ptr_to([0]), cta_group=1) # caller signals completion
+ T.ptx.mbarrier.try_wait(mma_mbar.ptr_to([0]), 0)
+ # ... tcgen05.fence.after_thread_sync(); read tmem back via tcgen05.ld; dealloc ...
+
+Algorithm
+---------
+
+**1. Encode shared matrix descriptors.** Each shared operand gets a 64-bit
+descriptor (leading-dim offset ``ldo``, stride-dim offset ``sdo``, swizzle mode)
+naming its tile to the tensor core:
+
+.. code-block:: python
+
+ T.ptx.tcgen05.encode_matrix_descriptor(descA.data, A_smem.ptr_to([0]), ldo, sdo, swizzle)
+ T.ptx.tcgen05.encode_matrix_descriptor(descB.data, B_smem.ptr_to([0]), ldo, sdo, swizzle)
+
+**2. Choose the MMA tile.** ``M_mma × N_mma`` are chosen to tile ``M``/``N`` (with
+``MMA_K`` set by dtype: 16 f16/bf16, 32 fp8, 64 fp4); a compile-time *instruction
+descriptor* packs the shape and dtypes.
+
+**3. Issue the async MMA** in an unrolled ``(mi, ni, ki)`` nest, accumulating into
+the tmem accumulator (``enable_input_d`` turns accumulation on for ``ki > 0``):
+
+.. code-block:: python
+
+ T.ptx.tcgen05.mma(
+ "float32", A_type, B_type,
+ T.cuda.get_tmem_addr(tmem_addr, mi * M_mma, tmem_col), # C in tmem
+ smem_desc_add_16B_offset(descA, a_off), descB_val, descI, # A / B descriptors
+ use_a_tmem=a_is_tmem, cta_group=cta_group,
+ enable_input_d=(ki != 0), # accumulate over K
+ )
+
+For **block-scaled** fp8/fp4 the emit becomes ``T.ptx.tcgen05.mma.block_scale(...)``
+with two extra tmem addresses — ``SFA`` / ``SFB`` — and the scale-factor dtypes; the
+instruction descriptor is encoded at runtime. As with the other async ops, the
+dispatch emits **no** completion — the caller's ``tcgen05.commit`` + mbarrier wait
+close it.
+
+Generated TIRx IR
+-----------------
+
+For the ``128×64 × 64×128`` fp16 tile (swizzle mode 3):
+
+.. code-block:: python
+
+ T.ptx.tcgen05.encode_matrix_descriptor(T.address_of(descA[0]), T.address_of(A_smem[0]), 64, 64, 3)
+ T.ptx.tcgen05.encode_matrix_descriptor(T.address_of(descB[0]), T.address_of(B_smem[0]), 64, 64, 3)
+ T.ptx.tcgen05.mma("float32", "float16", "float16",
+ T.cuda.get_tmem_addr(tmem_addr[0], mi * 128, 256 + ni * 128), ...)
+
+Generated CUDA
+--------------
+
+.. code-block:: c++
+
+ // async tensor-core MMA: A,B (shared, via descriptors) -> C (tmem)
+ "tcgen05.mma.cta_group::1.kind::f16 [%0], %1, %2, %3, ...;"
+ // [%0] = C tmem address; %1 = A descriptor; %2 = B descriptor; %3 = instr descriptor
+
+``kind::f16`` selects the fp16/bf16 datapath. Verified on ``sm_100a`` (the tmem
+result, read back, equals ``A@B`` within fp16 tolerance).
+
+How inputs change the algorithm
+-------------------------------
+
+.. list-table::
+ :header-rows: 1
+ :widths: 28 72
+
+ * - input
+ - effect
+ * - dtype
+ - ``float16``/``bfloat16`` → ``kind::f16``, ``MMA_K = 16``; ``fp8`` →
+ ``MMA_K = 32``; ``fp4`` → ``MMA_K = 64`` and the **block-scaled** path
+ * - block scaling (SFA/SFB)
+ - present → ``tcgen05.mma.block_scale`` with SFA/SFB tmem scale-factor
+ addresses and a runtime-encoded instruction descriptor
+ * - cta_group
+ - ``1`` → one CTA, ``M ∈ {64, 128}``; ``2`` → two CTAs split the operand,
+ ``M ∈ {128, 256}`` and half the per-CTA N
+ * - M / N / K extents
+ - set the ``(mi, ni, ki)`` unrolled loop counts; K iterations accumulate into
+ the same tmem accumulator
+ * - shared swizzle
+ - sets the ``swizzle`` mode + ``ldo``/``sdo`` in the matrix descriptors
diff --git a/docs/_sources/tirx/tile_primitives/permute_layout.rst.txt b/docs/_sources/tirx/tile_primitives/permute_layout.rst.txt
new file mode 100644
index 00000000000..05186d4be11
--- /dev/null
+++ b/docs/_sources/tirx/tile_primitives/permute_layout.rst.txt
@@ -0,0 +1,163 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+permute_layout
+==============
+
+``permute_layout`` rearranges a warp's data from a source ``TileLayout`` to a
+destination one — typically an in-place transpose. The single CUDA variant
+(``warp_xor_swizzle``) stages each lane's elements through registers and writes them
+back under the destination layout, with a per-lane **XOR swizzle** on the iteration
+index chosen so that *both* the read and the write phase are shared-memory
+bank-conflict-free. A ``warp_sync`` separates the two phases so the op is safe even
+when source and destination alias. Source:
+``python/tvm/backend/cuda/operator/tile_primitive/permute_layout/warp_xor_swizzle.py``.
+
+What it accepts
+---------------
+
+The predicate (``_why_reject``) gates the variant:
+
+.. code-block:: python
+
+ if sctx.scope_kind != "warp": return "scope is not 'warp'"
+ if src_buf.dtype != dst_buf.dtype: return "dtype mismatch"
+ if src_ext_i != dst_ext_i: return "extent mismatch"
+ if dtype_bytes not in (1, 2, 4, 8, 16): return "unsupported dtype byte width"
+ if not isinstance(src_buf.layout, TileLayout): return "src not a plain TileLayout"
+ if not isinstance(dst_buf.layout, TileLayout): return "dst not a plain TileLayout"
+ # + layouts must slice/canonicalize; _choose_xor_k must find a valid k (else fail)
+
+.. list-table::
+ :header-rows: 1
+ :widths: 22 78
+
+ * - Property
+ - Requirement
+ * - target / scope / priority
+ - ``cuda``; **warp** scope only; priority ``20``
+ * - operands
+ - equal dtype, equal (compile-time) extents; both plain ``TileLayout`` (no
+ swizzle wrapper); dtype byte width ∈ {1, 2, 4, 8, 16}
+ * - bank-freedom
+ - ``_choose_xor_k`` must find an XOR-bit count ``k ∈ [0, log2(P)]`` that makes
+ **both** phases bank-conflict-free, else the dispatch declines (``fail``)
+
+Demonstration program
+----------------------
+
+A warp transposes the inner ``4×32`` block of a scale-factor tile — source layout
+strides ``(…, 32, 1)``, destination ``(…, 1, 4)`` — for two pipeline stages (the
+canonical SF-transpose, from ``test_permute_layout.py``):
+
+.. code-block:: python
+
+ pipe, blk, dtype = 2, 128, "float32"; high = 1
+ shape = (pipe, high, 4, 32)
+ pre = TileLayout(S[shape : (blk, 128, 32, 1)]) # source
+ post = TileLayout(S[shape : (blk, 128, 1, 4)]) # destination (4↔32 transposed)
+
+ @T.prim_func
+ def f(A: T.handle, B: T.handle):
+ A_buf = T.match_buffer(A, shape, dtype, layout=pre)
+ B_buf = T.match_buffer(B, shape, dtype, layout=post)
+ T.device_entry(); T.cta_id([1]); T.thread_id([32])
+ for s in T.serial(0, pipe):
+ Tx.warp.permute_layout(B_buf[s, 0:1, 0:4, 0:32], A_buf[s, 0:1, 0:4, 0:32])
+
+Algorithm
+---------
+
+**1. Align the two layouts.** Both layouts are sliced to the region and
+canonicalized; if their shards differ in structure (a linear layout collapses to 1-D
+under canon, a transposed one keeps its multi-dim shape) the source is regrouped to
+the destination's shape. From the destination shard come the iteration ``extent``
+and the per-side strides ``src_str`` / ``dst_str``. ``P`` = elements per lane =
+``prod(extent) / 32`` (here ``4``).
+
+**2. Choose the XOR swizzle.** ``_choose_xor_k`` simulates the shared-memory bank
+pattern at shard granularity for ``k = 0, 1, … log2(P)`` and picks the smallest
+``k`` whose ``shift`` / ``mask`` make *both* phases conflict-free (here ``shift = 3``,
+``mask = 3``).
+
+**3. Emit two register-staged phases.** Each lane reads its ``P`` elements through
+the source layout into registers (the swizzle permutes which register holds which
+iteration), a ``warp_sync`` follows, then the registers are written back through the
+destination layout:
+
+.. code-block:: python
+
+ regs = T.alloc_buffer((P,), dtype, scope="local")
+ for r in T.unroll(0, P): # read via src layout
+ j = r ^ ((lane_id >> shift) & mask)
+ idx = decompose(lane_id + j * 32, extent)
+ regs[r] = src_buf[project(idx, src_st)]
+ T.cuda.warp_sync()
+ for r in T.unroll(0, P): # write via dst layout
+ j = r ^ ((lane_id >> shift) & mask)
+ idx = decompose(lane_id + j * 32, extent)
+ dst_buf[project(idx, dst_st)] = regs[r]
+ T.cuda.warp_sync()
+
+Generated TIRx IR
+-----------------
+
+.. code-block:: python
+
+ regs[r] = A_buf[s*128 + (r ^ ((tx >> 3) & 3)) % 4 * 32 + tx] # phase 1 (src order)
+ T.cuda.warp_sync()
+ B_buf[s*128 + tx * 4 + (r ^ ((tx >> 3) & 3)) % 4] = regs[r] # phase 2 (dst order)
+ T.cuda.warp_sync()
+
+Generated CUDA
+--------------
+
+.. code-block:: c++
+
+ alignas(64) float regs_ptr[4];
+ regs_ptr[0] = A_buf_ptr[(s*128) + (((0 ^ ((threadIdx.x >> 3) & 3)) & 3) * 32) + threadIdx.x];
+ regs_ptr[1] = A_buf_ptr[(s*128) + (((1 ^ ((threadIdx.x >> 3) & 3)) & 3) * 32) + threadIdx.x];
+ regs_ptr[2] = A_buf_ptr[(s*128) + (((2 ^ ((threadIdx.x >> 3) & 3)) & 3) * 32) + threadIdx.x];
+ regs_ptr[3] = A_buf_ptr[(s*128) + (((3 ^ ((threadIdx.x >> 3) & 3)) & 3) * 32) + threadIdx.x];
+ __syncwarp();
+ // ... 4 transposed writes into B_buf_ptr, then __syncwarp();
+
+Each lane owns column ``threadIdx.x`` and stages its 4 rows through ``regs``; the
+``(threadIdx.x >> 3)`` XOR rotates the register order per lane-group of 8 so the
+write phase hits distinct banks. Verified on ``sm_100a`` — the ``4×32`` block is
+transposed for every pipeline stage.
+
+How inputs change the algorithm
+-------------------------------
+
+.. list-table::
+ :header-rows: 1
+ :widths: 28 72
+
+ * - input
+ - effect
+ * - layout strides (the permutation)
+ - define ``extent`` / ``src_str`` / ``dst_str`` and hence ``P`` and the
+ per-element index math (the transpose pattern)
+ * - dtype byte width
+ - feeds the bank simulation in ``_choose_xor_k``; 4-byte dtypes always admit a
+ valid ``k`` (one element per bank), while stride-1 **sub-4-byte** reads can
+ pack several lanes into one bank and make the dispatch ``fail``
+ * - chosen ``k``
+ - sets ``shift`` / ``mask`` of the XOR swizzle (``k = 0`` ⇒ no swizzle)
+ * - ``P`` (= elements/lane)
+ - the number of staged registers and unrolled iterations per phase
diff --git a/docs/_sources/tirx/tile_primitives/reduction.rst.txt b/docs/_sources/tirx/tile_primitives/reduction.rst.txt
new file mode 100644
index 00000000000..41e39e131a0
--- /dev/null
+++ b/docs/_sources/tirx/tile_primitives/reduction.rst.txt
@@ -0,0 +1,48 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+reduction
+=========
+
+Covers ``sum``, ``max``, ``min`` (reduce over ``axes``). Three variants: ``local``
+and ``shared`` (priority 10, discriminated by operand storage scope) and
+``sm100_packed`` (priority 20, which pre-empts the others for the thread-scope
+float32 case on Blackwell).
+
+.. list-table::
+ :header-rows: 1
+ :widths: 26 14 60
+
+ * - Variant
+ - Prio
+ - Lowering
+ * - :doc:`reduction/local`
+ - 10
+ - register src/dst; sequential thread reduction (+ optional warp shuffle)
+ * - :doc:`reduction/shared`
+ - 10
+ - shared src/dst; adaptive group-size ``__shfl_xor`` tree
+ * - :doc:`reduction/sm100_packed`
+ - 20
+ - Blackwell thread-scope fp32 ≥8: packed ``add.f32x2`` / ``max3``/``min3``
+
+.. toctree::
+ :maxdepth: 1
+
+ reduction/local
+ reduction/shared
+ reduction/sm100_packed
diff --git a/docs/_sources/tirx/tile_primitives/reduction/local.rst.txt b/docs/_sources/tirx/tile_primitives/reduction/local.rst.txt
new file mode 100644
index 00000000000..184d8a395d0
--- /dev/null
+++ b/docs/_sources/tirx/tile_primitives/reduction/local.rst.txt
@@ -0,0 +1,136 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+reduction → local
+=================
+
+The ``local`` variant lowers a reduction (``sum`` / ``max`` / ``min``) when **both
+source and destination are register** (``local``) buffers. At thread scope it is a
+plain sequential reduction over each thread's own elements; at warp scope, if the
+destination layout carries a ``laneid`` replica, it also folds across lanes with a
+``__shfl_xor`` tree. Source:
+``python/tvm/backend/cuda/operator/tile_primitive/reduction/local.py``.
+
+What it accepts
+---------------
+
+.. code-block:: python
+
+ @register_dispatch(op_name, "cuda", variant="local", priority=10, when=[
+ predicate("storage_scope", _match_reduction_storage_scope, expected_scope=["local"]),
+ predicate("local_valid", validate_reduction_local),
+ ])
+
+.. list-table::
+ :header-rows: 1
+ :widths: 22 78
+
+ * - Property
+ - Requirement
+ * - target / priority
+ - ``cuda``; priority ``10``
+ * - operand scope
+ - src **and** dst in ``local`` (registers), equal dtype
+ * - exec scope
+ - ``thread`` (always valid — pure thread-local); ``warp`` / ``warpgroup``
+ require a valid (non-swizzled) ``TileLayout``; ``warp`` may additionally
+ cross-lane reduce when ``thread_reduce`` and a ``laneid`` shard→replica
+ pattern are present
+ * - shape
+ - dst spatial dims match src; reduced dims have ``local_extent == 1`` on dst
+
+Demonstration program
+----------------------
+
+A single thread reduces a 4-element ``float32`` register vector to a scalar
+(thread-wise path, from ``test_reduction.py``):
+
+.. code-block:: python
+
+ @T.prim_func
+ def test_func(A_ptr: T.handle, B_ptr: T.handle):
+ A = T.match_buffer(A_ptr, [4], "float32", layout=TileLayout(S[(4,)]))
+ B = T.match_buffer(B_ptr, [1], "float32", layout=TileLayout(S[(1,)]))
+ T.device_entry(); T.cta_id([1]); T.thread_id([1])
+ A_local = T.alloc_buffer([4], "float32", scope="local")
+ B_local = T.alloc_buffer([1], "float32", scope="local")
+ for i in T.serial(4): A_local[i] = A[i]
+ Tx.sum(B_local, A_local, accum=False) # reduction local dispatch
+ B[0] = B_local[0]
+
+(4 < 8 elements, so this stays on ``local`` rather than the
+:doc:`sm100_packed` fast path.)
+
+Algorithm
+---------
+
+**Thread-wise** (``_emit_reduction_local_thread_wise``): a spatial loop over the
+output positions, each initialized to the op's identity (unless ``accum``), then a
+reduction loop accumulating the source — no cross-thread communication:
+
+.. code-block:: python
+
+ for spa in range(spatial_len):
+ if not accum: dst[spa] = identity
+ for red in range(reduction_len):
+ dst[spa] = op(dst[spa], src[spa, red])
+
+**Warp-shuffle** (``_gen_warp_shuffle_reduce``): when the dst layout has a
+``laneid`` replica, each lane first reduces its own elements, then
+``T.cuda.warp_reduce`` folds across lanes — a ``__shfl_xor`` tree over the **full**
+``0xFFFFFFFF`` mask. (This differs from :doc:`shared`, which uses explicit
+``tvm_warp_shuffle_xor`` steps over ``__activemask()`` at the *group* width.)
+
+Generated TIRx IR
+-----------------
+
+For the 4-element thread reduction:
+
+.. code-block:: python
+
+ for spa in range(1):
+ for red in range(4):
+ dst[...] = dst[...] + src[...] # op = sum
+
+Generated CUDA
+--------------
+
+.. code-block:: c++
+
+ for (int red = 0; red < 4; ++red)
+ B_local_ptr[0] = B_local_ptr[0] + A_local_ptr[red];
+
+(Verified on ``sm_100a`` — ``B == sum(A)``.)
+
+How inputs change the algorithm
+-------------------------------
+
+.. list-table::
+ :header-rows: 1
+ :widths: 28 72
+
+ * - input
+ - effect
+ * - op
+ - ``sum`` → ``+``, ``max`` → ``max``, ``min`` → ``min`` (and the identity)
+ * - exec scope
+ - ``thread`` → sequential; ``warp`` with a ``laneid`` replica → adds a
+ ``__shfl_xor`` cross-lane tree
+ * - axes / shape
+ - set the spatial vs reduction loop extents
+ * - accum
+ - ``True`` reuses the old dst value instead of the identity
diff --git a/docs/_sources/tirx/tile_primitives/reduction/shared.rst.txt b/docs/_sources/tirx/tile_primitives/reduction/shared.rst.txt
new file mode 100644
index 00000000000..5d61dc6c874
--- /dev/null
+++ b/docs/_sources/tirx/tile_primitives/reduction/shared.rst.txt
@@ -0,0 +1,136 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+reduction → shared
+==================
+
+The ``shared`` variant lowers a reduction (``sum`` / ``max`` / ``min``) when
+**both source and destination are shared** memory. At CTA / warpgroup / warp scope
+it partitions the threads into groups — one group per output position — has each
+thread gather a chunk of the reduction axis, then folds the group with an adaptive
+``__shfl_xor`` tree. Source:
+``python/tvm/backend/cuda/operator/tile_primitive/reduction/shared.py``.
+
+What it accepts
+---------------
+
+.. code-block:: python
+
+ @register_dispatch(op_name, "cuda", variant="shared", priority=10, when=[
+ predicate("storage_scope", _match_reduction_storage_scope, expected_scope=["shared*"]),
+ predicate("shared_valid", validate_reduction_shared),
+ ])
+
+.. list-table::
+ :header-rows: 1
+ :widths: 22 78
+
+ * - Property
+ - Requirement
+ * - target / priority
+ - ``cuda``; priority ``10``
+ * - operand scope
+ - src **and** dst in ``shared*``, equal dtype
+ * - exec scope
+ - ``cta`` / ``warpgroup`` / ``warp`` (shuffle tree) or ``thread`` (sequential)
+ * - thread binding
+ - ``threadIdx.x`` present and **1-D** (no ``threadIdx.y`` / ``z``)
+ * - shape
+ - ``dst`` size equals the source's spatial extent (product of the non-reduced
+ dims)
+
+Demonstration program
+----------------------
+
+A 32-thread CTA reduces each row of a ``4×8`` ``float32`` shared tile (reduce
+axis ``-1``) to a ``4``-vector (from ``test_reduction.py``):
+
+.. code-block:: python
+
+ @T.prim_func
+ def test_reduction(A_ptr: T.handle, B_ptr: T.handle):
+ A = T.match_buffer(A_ptr, (4, 8), "float32", layout=TileLayout(S[(4, 8)]))
+ B = T.match_buffer(B_ptr, (4,), "float32", layout=TileLayout(S[(4,)]))
+ T.device_entry(); T.cta_id([1]); T.thread_id([32])
+ A_smem = T.alloc_buffer((4, 8), "float32", scope="shared", layout=TileLayout(S[(4, 8)]))
+ B_smem = T.alloc_buffer((4,), "float32", scope="shared", layout=TileLayout(S[(4,)]))
+ Tx.cta.copy(A_smem, A); T.cuda.cta_sync()
+ Tx.cta.sum(B_smem, A_smem, axes=(-1,), accum=False) # reduction shared dispatch
+ T.cuda.cta_sync()
+ Tx.cta.copy(B, B_smem)
+
+Algorithm
+---------
+
+**1. Choose the group size.** ``group_size = min(next_power_of_2(reduction_len),
+32, thread_cnt)`` — here ``reduction_len = 8`` ⇒ ``group_size = 8``. Each group of 8
+lanes cooperatively reduces one row; the CTA processes the 4 rows in parallel.
+
+**2. Gather + shuffle tree.** Each lane loads its slice of the reduction axis into a
+register, then ``log2(group_size)`` ``shfl_xor`` steps (masks ``1, 2, 4``) fold the
+group; lane 0 of each group writes the result, followed by a barrier:
+
+.. code-block:: python
+
+ mask = T.tvm_warp_activemask()
+ for i in range(n_shuffles): # n_shuffles = log2(group_size)
+ thread_data[0] = op(thread_data[0],
+ T.tvm_warp_shuffle_xor(mask, thread_data[0], 1 << i, group_size, 32))
+
+(``warp`` uses ``warp_sync``; ``warpgroup`` ``warpgroup_sync(8)``; ``cta``
+``cta_sync``. Thread scope is instead the sequential loop of :doc:`local`.)
+
+Generated TIRx IR
+-----------------
+
+.. code-block:: python
+
+ thread_data[0] = thread_data[0] + T.tvm_warp_shuffle_xor(T.tvm_warp_activemask(), thread_data[0], 1, 8, 32)
+ thread_data[0] = thread_data[0] + T.tvm_warp_shuffle_xor(T.tvm_warp_activemask(), thread_data[0], 2, 8, 32)
+ thread_data[0] = thread_data[0] + T.tvm_warp_shuffle_xor(T.tvm_warp_activemask(), thread_data[0], 4, 8, 32)
+
+Generated CUDA
+--------------
+
+.. code-block:: c++
+
+ thread_data_ptr[0] = thread_data_ptr[0] + __shfl_xor_sync(__activemask(), thread_data_ptr[0], 1, 8);
+ thread_data_ptr[0] = thread_data_ptr[0] + __shfl_xor_sync(__activemask(), thread_data_ptr[0], 2, 8);
+ thread_data_ptr[0] = thread_data_ptr[0] + __shfl_xor_sync(__activemask(), thread_data_ptr[0], 4, 8);
+
+(Verified on ``sm_100a`` — each ``B[r] == sum(A[r, :])``. The shuffle width ``8``
+is the group size, not the full warp.)
+
+How inputs change the algorithm
+-------------------------------
+
+.. list-table::
+ :header-rows: 1
+ :widths: 28 72
+
+ * - input
+ - effect
+ * - op
+ - ``sum`` → ``+`` shuffle tree; ``max`` / ``min`` → the corresponding combine
+ * - reduction length / thread count
+ - set ``group_size = min(next_pow2(reduction_len), 32, thread_cnt)`` and hence
+ the number of shuffle steps
+ * - exec scope
+ - ``cta`` / ``warpgroup`` / ``warp`` → shuffle tree (different sync); ``thread``
+ → sequential loop
+ * - accum
+ - ``True`` combines the reduced value with the old dst
diff --git a/docs/_sources/tirx/tile_primitives/reduction/sm100_packed.rst.txt b/docs/_sources/tirx/tile_primitives/reduction/sm100_packed.rst.txt
new file mode 100644
index 00000000000..b1c2e5de443
--- /dev/null
+++ b/docs/_sources/tirx/tile_primitives/reduction/sm100_packed.rst.txt
@@ -0,0 +1,147 @@
+.. Licensed to the Apache Software Foundation (ASF) under one
+ or more contributor license agreements. See the NOTICE file
+ distributed with this work for additional information
+ regarding copyright ownership. The ASF licenses this file
+ to you under the Apache License, Version 2.0 (the
+ "License"); you may not use this file except in compliance
+ with the License. You may obtain a copy of the License at
+
+.. http://www.apache.org/licenses/LICENSE-2.0
+
+.. Unless required by applicable law or agreed to in writing,
+ software distributed under the License is distributed on an
+ "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ KIND, either express or implied. See the License for the
+ specific language governing permissions and limitations
+ under the License.
+
+reduction → sm100_packed
+========================
+
+The ``sm100_packed`` variant is a **Blackwell-only fast path** (priority **20**, so
+it pre-empts :doc:`local`) for a thread-scope reduction of a 1-D ``float32`` vector
+of at least 8 elements to a scalar. It uses the SM100 packed math instructions —
+``add.f32x2`` for ``sum``, ``max3.f32`` / ``min3.f32`` for ``max`` / ``min`` —
+to fold two (or three) lanes of data per instruction. Source:
+``python/tvm/backend/cuda/operator/tile_primitive/reduction/sm100_packed.py``.
+
+What it accepts
+---------------
+
+All of the following must hold (else the dispatch declines and :doc:`local` runs):
+
+.. code-block:: python
+
+ @register_dispatch(op_name, "cuda", variant=variant_name, priority=20,
+ when=[
+ predicate("exec_scope", exec_scope_ok, expected_scopes=["thread"]),
+ predicate("local_scope", _local_scope_match), # src & dst local
+ predicate("dst_len", _dst_len_ok, expected_len=1), # reduce to scalar
+ predicate("src_ndim", _src_ndim_ok, expected_ndim=1),
+ predicate("dtype", _dtype_ok, expected_dtype="float32"),
+ predicate("sm_version", sm_version_ok, min_version=100),
+ predicate("reduction_len", _reduction_len_ok, min_len=8),
+ ])
+
+.. list-table::
+ :header-rows: 1
+ :widths: 22 78
+
+ * - Property
+ - Requirement
+ * - target / priority
+ - ``cuda`` ``sm_100+`` (Blackwell); priority ``20`` (beats ``local``)
+ * - exec scope
+ - ``thread`` only
+ * - operands
+ - src & dst ``local``, both ``float32``; dst length ``1``; src **1-D** with
+ ``≥ 8`` elements
+
+Demonstration program
+----------------------
+
+A single thread sums a 32-element ``float32`` register vector on ``sm_100a`` (from
+``test_reduction.py``):
+
+.. code-block:: python
+
+ @T.prim_func
+ def test_func(A_ptr: T.handle, B_ptr: T.handle):
+ A = T.match_buffer(A_ptr, [32], "float32", layout=TileLayout(S[(32,)]))
+ B = T.match_buffer(B_ptr, [1], "float32", layout=TileLayout(S[(1,)]))
+ T.device_entry(); T.cta_id([1]); T.thread_id([1])
+ A_local = T.alloc_buffer([32], "float32", scope="local")
+ B_local = T.alloc_buffer([1], "float32", scope="local")
+ for i in T.serial(32): A_local[i] = A[i]
+ Tx.sum(B_local, A_local, accum=False) # -> sm100_packed (len 32 >= 8, fp32, sm100)
+ B[0] = B_local[0]
+
+ target = tvm.target.Target({"kind": "cuda", "arch": "sm_100a"})
+
+Algorithm
+---------
+
+**sum (packed_add_sum).** Keep an 8-wide ``float32`` accumulator. Load the first 8
+elements; for each further chunk of 8, pairwise-add it in with four ``add.f32x2``
+(each adds two ``float2`` lanes at once); handle the remainder scalar; then collapse
+the accumulator ``8 → 4 → 2 → 1`` with three more ``add.f32x2``:
+
+.. code-block:: python
+
+ # final tree (8 -> 4 -> 2 -> 1)
+ T.ptx.add_f32x2(T.address_of(local_sum[0]),
+ T.cuda.make_float2(local_sum[0], local_sum[1]),
+ T.cuda.make_float2(local_sum[2], local_sum[3]), ftz=True)
+ T.ptx.add_f32x2(T.address_of(local_sum[4]),
+ T.cuda.make_float2(local_sum[4], local_sum[5]),
+ T.cuda.make_float2(local_sum[6], local_sum[7]), ftz=True)
+ T.ptx.add_f32x2(T.address_of(local_sum[0]),
+ T.cuda.make_float2(local_sum[0], local_sum[1]),
+ T.cuda.make_float2(local_sum[4], local_sum[5]), ftz=True)
+ dst[...] = local_sum[0] + local_sum[1]
+
+**max / min (3input_maxmin).** A 4-wide accumulator folded three-at-a-time with the
+``max3.f32`` / ``min3.f32`` instructions.
+
+Generated TIRx IR
+-----------------
+
+.. code-block:: python
+
+ T.ptx.add_f32x2(T.address_of(local_sum[0]),
+ T.cuda.make_float2(local_sum[0], local_sum[1]),
+ T.cuda.make_float2(local_sum[2], local_sum[3])) # ... the 8->4->2->1 tree
+
+Generated CUDA
+--------------
+
+.. code-block:: c++
+
+ // packed pairwise add: two float lanes per instruction
+ "add.rn.ftz.f32x2 %0, %1, %2;"
+ // call: tvm_builtin_ptx_add_f32x2_rn_ftz(&local_sum_ptr[0],
+ // tvm_builtin_make_float2(local_sum_ptr[0], local_sum_ptr[1]),
+ // tvm_builtin_make_float2(local_sum_ptr[2], local_sum_ptr[3]));
+
+(Verified on ``sm_100a`` — ``B == sum(A)`` for a 32-element vector.)
+
+How inputs change the algorithm
+-------------------------------
+
+.. list-table::
+ :header-rows: 1
+ :widths: 28 72
+
+ * - input
+ - effect
+ * - op
+ - ``sum`` → the ``add.f32x2`` packed tree; ``max`` / ``min`` → the
+ ``max3.f32`` / ``min3.f32`` 3-input fold
+ * - reduction length
+ - the chunk-of-8 (sum) / chunk handling and the scalar remainder loop; must be
+ ``≥ 8``
+ * - accum
+ - ``True`` folds the old dst value into the first accumulator slot
+ * - anything outside the gate
+ - non-fp32, 2-D src, dst length > 1, pre-Blackwell, or ``< 8`` elements → the
+ dispatch declines and :doc:`local` handles it
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diff --git a/docs/_static/downloads/tirx_overview_hero.png b/docs/_static/downloads/tirx_overview_hero.png
new file mode 100644
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diff --git a/docs/arch/codegen.html b/docs/arch/codegen.html
index 9ccfb1ffc1f..14823e94d88 100644
--- a/docs/arch/codegen.html
+++ b/docs/arch/codegen.html
@@ -225,6 +225,16 @@
<li class="toctree-l1"><a class="reference internal" href="../deep_dive/tensor_ir/index.html">TensorIR</a></li>
<li class="toctree-l1"><a class="reference internal" href="../deep_dive/relax/index.html">Relax</a></li>
</ul>
+<p class="caption" role="heading"><span class="caption-text">TIRx</span></p>
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/overview.html">Overview</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/install.html">Installation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/native_basics.html">TIRx Basics: CUDA C++/PTX native level</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/layout.html">Tensor Layout</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/tile_primitives.html">Tile Primitives</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/arch/index.html">Compiler Internals</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/api/index.html">API Reference</a></li>
+</ul>
<p class="caption" role="heading"><span class="caption-text">API Reference</span></p>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../reference/api/python/index.html">Python API</a></li>
diff --git a/docs/arch/device_target_interactions.html b/docs/arch/device_target_interactions.html
index 97f4ccf6edd..f3da10da630 100644
--- a/docs/arch/device_target_interactions.html
+++ b/docs/arch/device_target_interactions.html
@@ -222,6 +222,16 @@
<li class="toctree-l1"><a class="reference internal" href="../deep_dive/tensor_ir/index.html">TensorIR</a></li>
<li class="toctree-l1"><a class="reference internal" href="../deep_dive/relax/index.html">Relax</a></li>
</ul>
+<p class="caption" role="heading"><span class="caption-text">TIRx</span></p>
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/overview.html">Overview</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/install.html">Installation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/native_basics.html">TIRx Basics: CUDA C++/PTX native level</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/layout.html">Tensor Layout</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/tile_primitives.html">Tile Primitives</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/arch/index.html">Compiler Internals</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/api/index.html">API Reference</a></li>
+</ul>
<p class="caption" role="heading"><span class="caption-text">API Reference</span></p>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../reference/api/python/index.html">Python API</a></li>
diff --git a/docs/arch/external_library_dispatch.html b/docs/arch/external_library_dispatch.html
index f0f93d35a33..59fa94cb69e 100644
--- a/docs/arch/external_library_dispatch.html
+++ b/docs/arch/external_library_dispatch.html
@@ -225,6 +225,16 @@
<li class="toctree-l1"><a class="reference internal" href="../deep_dive/tensor_ir/index.html">TensorIR</a></li>
<li class="toctree-l1"><a class="reference internal" href="../deep_dive/relax/index.html">Relax</a></li>
</ul>
+<p class="caption" role="heading"><span class="caption-text">TIRx</span></p>
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/overview.html">Overview</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/install.html">Installation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/native_basics.html">TIRx Basics: CUDA C++/PTX native level</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/layout.html">Tensor Layout</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/tile_primitives.html">Tile Primitives</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/arch/index.html">Compiler Internals</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/api/index.html">API Reference</a></li>
+</ul>
<p class="caption" role="heading"><span class="caption-text">API Reference</span></p>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../reference/api/python/index.html">Python API</a></li>
diff --git a/docs/arch/fusion.html b/docs/arch/fusion.html
index aa1fa97cca4..26163eda725 100644
--- a/docs/arch/fusion.html
+++ b/docs/arch/fusion.html
@@ -226,6 +226,16 @@
<li class="toctree-l1"><a class="reference internal" href="../deep_dive/tensor_ir/index.html">TensorIR</a></li>
<li class="toctree-l1"><a class="reference internal" href="../deep_dive/relax/index.html">Relax</a></li>
</ul>
+<p class="caption" role="heading"><span class="caption-text">TIRx</span></p>
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/overview.html">Overview</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/install.html">Installation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/native_basics.html">TIRx Basics: CUDA C++/PTX native level</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/layout.html">Tensor Layout</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/tile_primitives.html">Tile Primitives</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/arch/index.html">Compiler Internals</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/api/index.html">API Reference</a></li>
+</ul>
<p class="caption" role="heading"><span class="caption-text">API Reference</span></p>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../reference/api/python/index.html">Python API</a></li>
diff --git a/docs/arch/index.html b/docs/arch/index.html
index 3090e3b6fd5..886d1075ba5 100644
--- a/docs/arch/index.html
+++ b/docs/arch/index.html
@@ -249,6 +249,16 @@
<li class="toctree-l1"><a class="reference internal" href="../deep_dive/tensor_ir/index.html">TensorIR</a></li>
<li class="toctree-l1"><a class="reference internal" href="../deep_dive/relax/index.html">Relax</a></li>
</ul>
+<p class="caption" role="heading"><span class="caption-text">TIRx</span></p>
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/overview.html">Overview</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/install.html">Installation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/native_basics.html">TIRx Basics: CUDA C++/PTX native level</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/layout.html">Tensor Layout</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/tile_primitives.html">Tile Primitives</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/arch/index.html">Compiler Internals</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/api/index.html">API Reference</a></li>
+</ul>
<p class="caption" role="heading"><span class="caption-text">API Reference</span></p>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../reference/api/python/index.html">Python API</a></li>
diff --git a/docs/arch/introduction_to_module_serialization.html b/docs/arch/introduction_to_module_serialization.html
index f3b3f286a29..b4cee7272e4 100644
--- a/docs/arch/introduction_to_module_serialization.html
+++ b/docs/arch/introduction_to_module_serialization.html
@@ -226,6 +226,16 @@
<li class="toctree-l1"><a class="reference internal" href="../deep_dive/tensor_ir/index.html">TensorIR</a></li>
<li class="toctree-l1"><a class="reference internal" href="../deep_dive/relax/index.html">Relax</a></li>
</ul>
+<p class="caption" role="heading"><span class="caption-text">TIRx</span></p>
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/overview.html">Overview</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/install.html">Installation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/native_basics.html">TIRx Basics: CUDA C++/PTX native level</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/layout.html">Tensor Layout</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/tile_primitives.html">Tile Primitives</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/arch/index.html">Compiler Internals</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/api/index.html">API Reference</a></li>
+</ul>
<p class="caption" role="heading"><span class="caption-text">API Reference</span></p>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../reference/api/python/index.html">Python API</a></li>
diff --git a/docs/arch/pass_infra.html b/docs/arch/pass_infra.html
index 97b26ab0485..d1b09d866f5 100644
--- a/docs/arch/pass_infra.html
+++ b/docs/arch/pass_infra.html
@@ -220,6 +220,16 @@
<li class="toctree-l1"><a class="reference internal" href="../deep_dive/tensor_ir/index.html">TensorIR</a></li>
<li class="toctree-l1"><a class="reference internal" href="../deep_dive/relax/index.html">Relax</a></li>
</ul>
+<p class="caption" role="heading"><span class="caption-text">TIRx</span></p>
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/overview.html">Overview</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/install.html">Installation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/native_basics.html">TIRx Basics: CUDA C++/PTX native level</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/layout.html">Tensor Layout</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/tile_primitives.html">Tile Primitives</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/arch/index.html">Compiler Internals</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/api/index.html">API Reference</a></li>
+</ul>
<p class="caption" role="heading"><span class="caption-text">API Reference</span></p>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../reference/api/python/index.html">Python API</a></li>
diff --git a/docs/arch/relax_vm.html b/docs/arch/relax_vm.html
index 35d8f71bc62..7f4c04bce0e 100644
--- a/docs/arch/relax_vm.html
+++ b/docs/arch/relax_vm.html
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<li class="toctree-l1"><a class="reference internal" href="../deep_dive/relax/index.html">Relax</a></li>
</ul>
+<p class="caption" role="heading"><span class="caption-text">TIRx</span></p>
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/overview.html">Overview</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/install.html">Installation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/native_basics.html">TIRx Basics: CUDA C++/PTX native level</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/layout.html">Tensor Layout</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/tile_primitives.html">Tile Primitives</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/arch/index.html">Compiler Internals</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/api/index.html">API Reference</a></li>
+</ul>
<p class="caption" role="heading"><span class="caption-text">API Reference</span></p>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../reference/api/python/index.html">Python API</a></li>
diff --git a/docs/contribute/testing.html b/docs/contribute/testing.html
index b201c0b7622..e95cff221f0 100644
--- a/docs/contribute/testing.html
+++ b/docs/contribute/testing.html
@@ -200,6 +200,16 @@
<li class="toctree-l1"><a class="reference internal" href="../deep_dive/tensor_ir/index.html">TensorIR</a></li>
<li class="toctree-l1"><a class="reference internal" href="../deep_dive/relax/index.html">Relax</a></li>
</ul>
+<p class="caption" role="heading"><span class="caption-text">TIRx</span></p>
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/overview.html">Overview</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/install.html">Installation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/native_basics.html">TIRx Basics: CUDA C++/PTX native level</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/layout.html">Tensor Layout</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/tile_primitives.html">Tile Primitives</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/arch/index.html">Compiler Internals</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../tirx/api/index.html">API Reference</a></li>
+</ul>
<p class="caption" role="heading"><span class="caption-text">API Reference</span></p>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../reference/api/python/index.html">Python API</a></li>
diff --git a/docs/deep_dive/relax/abstraction.html b/docs/deep_dive/relax/abstraction.html
index 97b78fbfdd6..81fc97c635c 100644
--- a/docs/deep_dive/relax/abstraction.html
+++ b/docs/deep_dive/relax/abstraction.html
@@ -211,6 +211,16 @@
</ul>
</li>
</ul>
+<p class="caption" role="heading"><span class="caption-text">TIRx</span></p>
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/overview.html">Overview</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/install.html">Installation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/native_basics.html">TIRx Basics: CUDA C++/PTX native level</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/layout.html">Tensor Layout</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/tile_primitives.html">Tile Primitives</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/arch/index.html">Compiler Internals</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/api/index.html">API Reference</a></li>
+</ul>
<p class="caption" role="heading"><span class="caption-text">API Reference</span></p>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../../reference/api/python/index.html">Python API</a></li>
diff --git a/docs/deep_dive/relax/dpl.html b/docs/deep_dive/relax/dpl.html
index aef6cd9fe5a..e2f0c3ec64f 100644
--- a/docs/deep_dive/relax/dpl.html
+++ b/docs/deep_dive/relax/dpl.html
@@ -234,6 +234,16 @@
</ul>
</li>
</ul>
+<p class="caption" role="heading"><span class="caption-text">TIRx</span></p>
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/overview.html">Overview</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/install.html">Installation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/native_basics.html">TIRx Basics: CUDA C++/PTX native level</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/layout.html">Tensor Layout</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/tile_primitives.html">Tile Primitives</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/arch/index.html">Compiler Internals</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/api/index.html">API Reference</a></li>
+</ul>
<p class="caption" role="heading"><span class="caption-text">API Reference</span></p>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../../reference/api/python/index.html">Python API</a></li>
diff --git a/docs/deep_dive/relax/index.html b/docs/deep_dive/relax/index.html
index 6cdd930872c..31e734acd45 100644
--- a/docs/deep_dive/relax/index.html
+++ b/docs/deep_dive/relax/index.html
@@ -207,6 +207,16 @@
</ul>
</li>
</ul>
+<p class="caption" role="heading"><span class="caption-text">TIRx</span></p>
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/overview.html">Overview</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/install.html">Installation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/native_basics.html">TIRx Basics: CUDA C++/PTX native level</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/layout.html">Tensor Layout</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/tile_primitives.html">Tile Primitives</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/arch/index.html">Compiler Internals</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/api/index.html">API Reference</a></li>
+</ul>
<p class="caption" role="heading"><span class="caption-text">API Reference</span></p>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../../reference/api/python/index.html">Python API</a></li>
diff --git a/docs/deep_dive/relax/learning.html b/docs/deep_dive/relax/learning.html
index f09a0176e18..94f2c47d5b6 100644
--- a/docs/deep_dive/relax/learning.html
+++ b/docs/deep_dive/relax/learning.html
@@ -220,6 +220,16 @@
</ul>
</li>
</ul>
+<p class="caption" role="heading"><span class="caption-text">TIRx</span></p>
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/overview.html">Overview</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/install.html">Installation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/native_basics.html">TIRx Basics: CUDA C++/PTX native level</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/layout.html">Tensor Layout</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/tile_primitives.html">Tile Primitives</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/arch/index.html">Compiler Internals</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/api/index.html">API Reference</a></li>
+</ul>
<p class="caption" role="heading"><span class="caption-text">API Reference</span></p>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../../reference/api/python/index.html">Python API</a></li>
diff --git a/docs/deep_dive/relax/tutorials/index.html b/docs/deep_dive/relax/tutorials/index.html
index dbe4d71962a..cab3f234f58 100644
--- a/docs/deep_dive/relax/tutorials/index.html
+++ b/docs/deep_dive/relax/tutorials/index.html
@@ -198,6 +198,16 @@
<li class="toctree-l1"><a class="reference internal" href="../../tensor_ir/index.html">TensorIR</a></li>
<li class="toctree-l1"><a class="reference internal" href="../index.html">Relax</a></li>
</ul>
+<p class="caption" role="heading"><span class="caption-text">TIRx</span></p>
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/overview.html">Overview</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/install.html">Installation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/native_basics.html">TIRx Basics: CUDA C++/PTX native level</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/layout.html">Tensor Layout</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/tile_primitives.html">Tile Primitives</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/arch/index.html">Compiler Internals</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/api/index.html">API Reference</a></li>
+</ul>
<p class="caption" role="heading"><span class="caption-text">API Reference</span></p>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../../../reference/api/python/index.html">Python API</a></li>
diff --git a/docs/deep_dive/relax/tutorials/relax_creation.html b/docs/deep_dive/relax/tutorials/relax_creation.html
index 96d2c3d74a8..4feb9f6752b 100644
--- a/docs/deep_dive/relax/tutorials/relax_creation.html
+++ b/docs/deep_dive/relax/tutorials/relax_creation.html
@@ -200,6 +200,16 @@
<li class="toctree-l1"><a class="reference internal" href="../../tensor_ir/index.html">TensorIR</a></li>
<li class="toctree-l1"><a class="reference internal" href="../index.html">Relax</a></li>
</ul>
+<p class="caption" role="heading"><span class="caption-text">TIRx</span></p>
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/overview.html">Overview</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/install.html">Installation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/native_basics.html">TIRx Basics: CUDA C++/PTX native level</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/layout.html">Tensor Layout</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/tile_primitives.html">Tile Primitives</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/arch/index.html">Compiler Internals</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/api/index.html">API Reference</a></li>
+</ul>
<p class="caption" role="heading"><span class="caption-text">API Reference</span></p>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../../../reference/api/python/index.html">Python API</a></li>
@@ -371,11 +381,11 @@ TensorIR functions in Relax function.</p>
<span class="k">class</span><span class="w"> </span><span class="nc">RelaxModuleWithTIR</span><span class="p">:</span>
<span class="nd">@T</span><span class="o">.</span><span class="n">prim_func</span><span class="p">(</span><span class="n">s_tir</span><span class="o">=</span><span class="kc">True</span><span class="p">)</span>
<span class="k">def</span><span class="w"> </span><span class="nf">relu</span><span class="p">(</span><a href="../../../reference/api/python/relax/relax.html#tvm.relax.Var" title="tvm.relax.Var" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">x</span></a><span class="p">:</span> <span class="n">T</span><span class="o">.</span><span class="n">handle</span><span class="p">,</span> <span class="n">y</span><span class="p" [...]
- <a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">n</span></a> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">int64</span><span class="p">()</span>
+ <a href="../../../tirx/api/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">n</span></a> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">int64</span><span class="p">()</span>
<span class="n">m</span> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">int64</span><span class="p">()</span>
- <span class="n">X</span> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">match_buffer</span><span class="p">(</span><a href="../../../reference/api/python/relax/relax.html#tvm.relax.Var" title="tvm.relax.Var" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">x</span></a><span class="p">,</span> <span class="p">(</span><a href="../../../reference/api/python/tirx/tirx.html#tvm. [...]
- <span class="n">Y</span> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">match_buffer</span><span class="p">(</span><span class="n">y</span><span class="p">,</span> <span class="p">(</span><a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">n</span></a><span class="p">,</span> <span class="n [...]
- <span class="k">for</span> <span class="n">i</span><span class="p">,</span> <span class="n">j</span> <span class="ow">in</span> <span class="n">T</span><span class="o">.</span><span class="n">grid</span><span class="p">(</span><a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">n</span></a><span class="p">,</span> <span class="n">m [...]
+ <span class="n">X</span> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">match_buffer</span><span class="p">(</span><a href="../../../reference/api/python/relax/relax.html#tvm.relax.Var" title="tvm.relax.Var" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">x</span></a><span class="p">,</span> <span class="p">(</span><a href="../../../tirx/api/tirx.html#tvm.tirx.Var" title=" [...]
+ <span class="n">Y</span> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">match_buffer</span><span class="p">(</span><span class="n">y</span><span class="p">,</span> <span class="p">(</span><a href="../../../tirx/api/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">n</span></a><span class="p">,</span> <span class="n">m</span><span c [...]
+ <span class="k">for</span> <span class="n">i</span><span class="p">,</span> <span class="n">j</span> <span class="ow">in</span> <span class="n">T</span><span class="o">.</span><span class="n">grid</span><span class="p">(</span><a href="../../../tirx/api/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">n</span></a><span class="p">,</span> <span class="n">m</span><span clas [...]
<span class="k">with</span> <span class="n">T</span><span class="o">.</span><span class="n">sblock</span><span class="p">(</span><span class="s2">"relu"</span><span class="p">):</span>
<span class="n">vi</span><span class="p">,</span> <span class="n">vj</span> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">axis</span><span class="o">.</span><span class="n">remap</span><span class="p">(</span><span class="s2">"SS"</span><span class="p">,</span> <span class="p">[</span><span class="n">i</span><span class="p">,</span> <span class="n">j</span><span class="p">])</span>
<span class="n">Y</span><span class="p">[</span><span class="n">vi</span><span class="p">,</span> <span class="n">vj</span><span class="p">]</span> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">max</span><span class="p">(</span><span class="n">X</span><span class="p">[</span><span class="n">vi</span><span class="p">,</span> <span class="n">vj</span><span class="p">],</span> <span class="n">T</span><span class="o">.</span><span cl [...]
@@ -388,11 +398,11 @@ TensorIR functions in Relax function.</p>
<span class="n">w1</span><span class="p">:</span> <span class="n">R</span><span class="o">.</span><span class="n">Tensor</span><span class="p">((</span><span class="mi">10</span><span class="p">,</span> <span class="mi">128</span><span class="p">),</span> <span class="n">dtype</span><span class="o">=</span><span class="s2">"float32"</span><span class="p">),</span>
<span class="n">b1</span><span class="p">:</span> <span class="n">R</span><span class="o">.</span><span class="n">Tensor</span><span class="p">((</span><span class="mi">10</span><span class="p">,),</span> <span class="n">dtype</span><span class="o">=</span><span class="s2">"float32"</span><span class="p">),</span>
<span class="p">)</span> <span class="o">-></span> <span class="n">R</span><span class="o">.</span><span class="n">Tensor</span><span class="p">((</span><span class="s2">"n"</span><span class="p">,</span> <span class="mi">10</span><span class="p">),</span> <span class="n">dtype</span><span class="o">=</span><span class="s2">"float32"</span><span class="p">):</span>
- <a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">n</span></a> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">int64</span><span class="p">()</span>
+ <a href="../../../tirx/api/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">n</span></a> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">int64</span><span class="p">()</span>
<span class="bp">cls</span> <span class="o">=</span> <span class="n">RelaxModuleWithTIR</span>
<span class="k">with</span> <span class="n">R</span><span class="o">.</span><span class="n">dataflow</span><span class="p">():</span>
<a href="../../../reference/api/python/relax/relax.html#tvm.relax.DataflowVar" title="tvm.relax.DataflowVar" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">lv0</span></a> <span class="o">=</span> <span class="n">R</span><span class="o">.</span><span class="n">matmul</span><span class="p">(</span><span class="n">data</span><span class="p">,</span> <span class="n">R</span><span class="o">.</span><span class="n" [...]
- <a href="../../../reference/api/python/relax/relax.html#tvm.relax.DataflowVar" title="tvm.relax.DataflowVar" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">lv1</span></a> <span class="o">=</span> <span class="n">R</span><span class="o">.</span><span class="n">call_tir</span><span class="p">(</span><span class="bp">cls</span><span class="o">.</span><span class="n">relu</span><span class="p">,</span> <a href=". [...]
+ <a href="../../../reference/api/python/relax/relax.html#tvm.relax.DataflowVar" title="tvm.relax.DataflowVar" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">lv1</span></a> <span class="o">=</span> <span class="n">R</span><span class="o">.</span><span class="n">call_tir</span><span class="p">(</span><span class="bp">cls</span><span class="o">.</span><span class="n">relu</span><span class="p">,</span> <a href=". [...]
<span class="n">lv2</span> <span class="o">=</span> <span class="n">R</span><span class="o">.</span><span class="n">matmul</span><span class="p">(</span><a href="../../../reference/api/python/relax/relax.html#tvm.relax.DataflowVar" title="tvm.relax.DataflowVar" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">lv1</span></a><span class="p">,</span> <span class="n">R</span><span class="o">.</span><span class="n"> [...]
<span class="n">R</span><span class="o">.</span><span class="n">output</span><span class="p">(</span><span class="n">lv2</span><span class="p">)</span>
<span class="k">return</span> <span class="n">lv2</span>
@@ -450,8 +460,8 @@ format, while we support syntax sugar for the input</p>
binding. So the printed output is different from the written TVMScript code,
as</p>
<div class="highlight-python notranslate"><div class="highlight"><pre><span></span><span class="n">lv</span><span class="p">:</span> <span class="n">R</span><span class="o">.</span><span class="n">Tensor</span><span class="p">((</span><span class="mi">784</span><span class="p">,</span> <span class="mi">128</span><span class="p">),</span> <span class="n">dtype</span><span class="o">=</span><span class="s2">"float32"</span><span class="p">)</span> <span class="o">=</span> <span c [...]
-<a href="../../../reference/api/python/relax/relax.html#tvm.relax.DataflowVar" title="tvm.relax.DataflowVar" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">lv1</span></a><span class="p">:</span> <span class="n">R</span><span class="o">.</span><span class="n">Tensor</span><span class="p">((</span><a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tir [...]
-<a href="../../../reference/api/python/relax/relax.html#tvm.relax.DataflowVar" title="tvm.relax.DataflowVar" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">lv0</span></a><span class="p">:</span> <span class="n">R</span><span class="o">.</span><span class="n">Tensor</span><span class="p">((</span><a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tir [...]
+<a href="../../../reference/api/python/relax/relax.html#tvm.relax.DataflowVar" title="tvm.relax.DataflowVar" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">lv1</span></a><span class="p">:</span> <span class="n">R</span><span class="o">.</span><span class="n">Tensor</span><span class="p">((</span><a href="../../../tirx/api/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backre [...]
+<a href="../../../reference/api/python/relax/relax.html#tvm.relax.DataflowVar" title="tvm.relax.DataflowVar" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">lv0</span></a><span class="p">:</span> <span class="n">R</span><span class="o">.</span><span class="n">Tensor</span><span class="p">((</span><a href="../../../tirx/api/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backre [...]
</pre></div>
</div>
</div>
@@ -539,21 +549,21 @@ Tensor Expression(TE), TensorIR functions or other TVM packed functions.</p>
<span class="bp">self</span><span class="o">.</span><span class="n">fc2</span> <span class="o">=</span> <span class="n">nn</span><span class="o">.</span><span class="n">Linear</span><span class="p">(</span><span class="mi">128</span><span class="p">,</span> <span class="mi">10</span><span class="p">)</span>
<span class="k">def</span><span class="w"> </span><span class="nf">forward</span><span class="p">(</span><span class="bp">self</span><span class="p">,</span> <a href="../../../reference/api/python/relax/relax.html#tvm.relax.Var" title="tvm.relax.Var" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">x</span></a><span class="p">):</span>
- <a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">n</span></a> <span class="o">=</span> <a href="../../../reference/api/python/relax/relax.html#tvm.relax.Var" title="tvm.relax.Var" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">x</span></a><span class="o">.</span [...]
+ <a href="../../../tirx/api/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">n</span></a> <span class="o">=</span> <a href="../../../reference/api/python/relax/relax.html#tvm.relax.Var" title="tvm.relax.Var" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">x</span></a><span class="o">.</span><span class="n"> [...]
<span class="c1"># We can call external functions using nn.extern</span>
<a href="../../../reference/api/python/relax/relax.html#tvm.relax.Var" title="tvm.relax.Var" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">x</span></a> <span class="o">=</span> <span class="n">nn</span><span class="o">.</span><span class="n">extern</span><span class="p">(</span>
<span class="s2">"env.linear"</span><span class="p">,</span>
<span class="p">[</span><a href="../../../reference/api/python/relax/relax.html#tvm.relax.Var" title="tvm.relax.Var" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">x</span></a><span class="p">,</span> <span class="bp">self</span><span class="o">.</span><span class="n">fc1</span><span class="o">.</span><span class="n">weight</span><span class="p">,</span> <span class="bp">self</span><span class="o">.</span><sp [...]
- <span class="n">out</span><span class="o">=</span><span class="n">nn</span><span class="o">.</span><span class="n">Tensor</span><span class="o">.</span><span class="n">placeholder</span><span class="p">((</span><a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">n</span></a><span class="p">,</span> <span class="mi">128</span><s [...]
+ <span class="n">out</span><span class="o">=</span><span class="n">nn</span><span class="o">.</span><span class="n">Tensor</span><span class="o">.</span><span class="n">placeholder</span><span class="p">((</span><a href="../../../tirx/api/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">n</span></a><span class="p">,</span> <span class="mi">128</span><span class="p">),< [...]
<span class="p">)</span>
<span class="c1"># We can also call TensorIR via Tensor Expression API in TOPI</span>
<a href="../../../reference/api/python/relax/relax.html#tvm.relax.Var" title="tvm.relax.Var" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">x</span></a> <span class="o">=</span> <span class="n">nn</span><span class="o">.</span><span class="n">tensor_expr_op</span><span class="p">(</span><a href="../../../reference/api/python/topi.html#tvm.topi.nn.relu" title="tvm.topi.nn.relu" class="sphx-glr-backref-module-tvm-t [...]
<span class="c1"># We can also call other TVM packed functions</span>
<a href="../../../reference/api/python/relax/relax.html#tvm.relax.Var" title="tvm.relax.Var" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">x</span></a> <span class="o">=</span> <span class="n">nn</span><span class="o">.</span><span class="n">tensor_ir_op</span><span class="p">(</span>
- <a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">tir_linear</span></a><span class="p">,</span>
+ <a href="../../../tirx/api/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">tir_linear</span></a><span class="p">,</span>
<span class="s2">"tir_linear"</span><span class="p">,</span>
<span class="p">[</span><a href="../../../reference/api/python/relax/relax.html#tvm.relax.Var" title="tvm.relax.Var" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">x</span></a><span class="p">,</span> <span class="bp">self</span><span class="o">.</span><span class="n">fc2</span><span class="o">.</span><span class="n">weight</span><span class="p">,</span> <span class="bp">self</span><span class="o">.</span><sp [...]
- <span class="n">out</span><span class="o">=</span><span class="n">nn</span><span class="o">.</span><span class="n">Tensor</span><span class="o">.</span><span class="n">placeholder</span><span class="p">((</span><a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">n</span></a><span class="p">,</span> <span class="mi">10</span><sp [...]
+ <span class="n">out</span><span class="o">=</span><span class="n">nn</span><span class="o">.</span><span class="n">Tensor</span><span class="o">.</span><span class="n">placeholder</span><span class="p">((</span><a href="../../../tirx/api/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">n</span></a><span class="p">,</span> <span class="mi">10</span><span class="p">),</ [...]
<span class="p">)</span>
<span class="k">return</span> <a href="../../../reference/api/python/relax/relax.html#tvm.relax.Var" title="tvm.relax.Var" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">x</span></a>
@@ -631,8 +641,8 @@ creating Relax programs. It is a IR builder API, which is more
low-level and widely used in TVM’s internal logic, e.g writing a
customized pass.</p>
<div class="highlight-Python notranslate"><div class="highlight"><pre><span></span><span class="n">bb</span> <span class="o">=</span> <span class="n">relax</span><span class="o">.</span><span class="n">BlockBuilder</span><span class="p">()</span>
-<a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">n</span></a> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">int64</span><span class="p">()</span>
-<a href="../../../reference/api/python/relax/relax.html#tvm.relax.Var" title="tvm.relax.Var" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">x</span></a> <span class="o">=</span> <a href="../../../reference/api/python/relax/relax.html#tvm.relax.Var" title="tvm.relax.Var" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class"><span class="n">relax</span><span class="o">.</span><span class="n">Var</span></ [...]
+<a href="../../../tirx/api/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">n</span></a> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">int64</span><span class="p">()</span>
+<a href="../../../reference/api/python/relax/relax.html#tvm.relax.Var" title="tvm.relax.Var" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">x</span></a> <span class="o">=</span> <a href="../../../reference/api/python/relax/relax.html#tvm.relax.Var" title="tvm.relax.Var" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class"><span class="n">relax</span><span class="o">.</span><span class="n">Var</span></ [...]
<a href="../../../reference/api/python/relax/relax.html#tvm.relax.Var" title="tvm.relax.Var" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">fc1_weight</span></a> <span class="o">=</span> <a href="../../../reference/api/python/relax/relax.html#tvm.relax.Var" title="tvm.relax.Var" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class"><span class="n">relax</span><span class="o">.</span><span class="n">Var [...]
<a href="../../../reference/api/python/relax/relax.html#tvm.relax.Var" title="tvm.relax.Var" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">fc1_bias</span></a> <span class="o">=</span> <a href="../../../reference/api/python/relax/relax.html#tvm.relax.Var" title="tvm.relax.Var" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class"><span class="n">relax</span><span class="o">.</span><span class="n">Var</ [...]
<a href="../../../reference/api/python/relax/relax.html#tvm.relax.Var" title="tvm.relax.Var" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">fc2_weight</span></a> <span class="o">=</span> <a href="../../../reference/api/python/relax/relax.html#tvm.relax.Var" title="tvm.relax.Var" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class"><span class="n">relax</span><span class="o">.</span><span class="n">Var [...]
@@ -681,16 +691,16 @@ Relax functions, TensorIR functions and other TVM packed functions.</p>
<a href="../../../reference/api/python/relax/relax.html#tvm.relax.call_dps_packed" title="tvm.relax.call_dps_packed" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-function"><span class="n">relax</span><span class="o">.</span><span class="n">call_dps_packed</span></a><span class="p">(</span>
<span class="s2">"env.linear"</span><span class="p">,</span>
<span class="p">[</span><a href="../../../reference/api/python/relax/relax.html#tvm.relax.Var" title="tvm.relax.Var" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">x</span></a><span class="p">,</span> <a href="../../../reference/api/python/relax/relax.html#tvm.relax.Var" title="tvm.relax.Var" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n" [...]
- <span class="n">out_ty</span><span class="o">=</span><a href="../../../reference/api/python/relax/relax.html#tvm.relax.TensorType" title="tvm.relax.TensorType" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class"><span class="n">relax</span><span class="o">.</span><span class="n">TensorType</span></a><span class="p">((</span><a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx [...]
+ <span class="n">out_ty</span><span class="o">=</span><a href="../../../reference/api/python/relax/relax.html#tvm.relax.TensorType" title="tvm.relax.TensorType" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class"><span class="n">relax</span><span class="o">.</span><span class="n">TensorType</span></a><span class="p">((</span><a href="../../../tirx/api/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref- [...]
<span class="p">)</span>
<span class="p">)</span>
<a href="../../../reference/api/python/relax/relax.html#tvm.relax.DataflowVar" title="tvm.relax.DataflowVar" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">lv1</span></a> <span class="o">=</span> <span class="n">bb</span><span class="o">.</span><span class="n">emit_te</span><span class="p">(</span><a href="../../../reference/api/python/topi.html#tvm.topi.nn.relu" title="tvm.topi.nn.relu" class="sphx-glr-backref-m [...]
- <a href="../../../reference/api/python/ir.html#tvm.ir.GlobalVar" title="tvm.ir.GlobalVar" class="sphx-glr-backref-module-tvm-ir sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">tir_gv</span></a> <span class="o">=</span> <span class="n">bb</span><span class="o">.</span><span class="n">add_func</span><span class="p">(</span><a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref-module-tvm-t [...]
+ <a href="../../../reference/api/python/ir.html#tvm.ir.GlobalVar" title="tvm.ir.GlobalVar" class="sphx-glr-backref-module-tvm-ir sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">tir_gv</span></a> <span class="o">=</span> <span class="n">bb</span><span class="o">.</span><span class="n">add_func</span><span class="p">(</span><a href="../../../tirx/api/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref-module-tvm-tirx sphx-glr-back [...]
<a href="../../../reference/api/python/relax/relax.html#tvm.relax.DataflowVar" title="tvm.relax.DataflowVar" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">gv</span></a> <span class="o">=</span> <span class="n">bb</span><span class="o">.</span><span class="n">emit</span><span class="p">(</span>
<a href="../../../reference/api/python/relax/relax.html#tvm.relax.call_tir" title="tvm.relax.call_tir" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-function"><span class="n">relax</span><span class="o">.</span><span class="n">call_tir</span></a><span class="p">(</span>
<a href="../../../reference/api/python/ir.html#tvm.ir.GlobalVar" title="tvm.ir.GlobalVar" class="sphx-glr-backref-module-tvm-ir sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">tir_gv</span></a><span class="p">,</span>
<span class="p">[</span><a href="../../../reference/api/python/relax/relax.html#tvm.relax.DataflowVar" title="tvm.relax.DataflowVar" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">lv1</span></a><span class="p">,</span> <a href="../../../reference/api/python/relax/relax.html#tvm.relax.Var" title="tvm.relax.Var" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instanc [...]
- <span class="n">out_ty</span><span class="o">=</span><a href="../../../reference/api/python/relax/relax.html#tvm.relax.TensorType" title="tvm.relax.TensorType" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class"><span class="n">relax</span><span class="o">.</span><span class="n">TensorType</span></a><span class="p">((</span><a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx [...]
+ <span class="n">out_ty</span><span class="o">=</span><a href="../../../reference/api/python/relax/relax.html#tvm.relax.TensorType" title="tvm.relax.TensorType" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class"><span class="n">relax</span><span class="o">.</span><span class="n">TensorType</span></a><span class="p">((</span><a href="../../../tirx/api/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref- [...]
<span class="p">)</span>
<span class="p">)</span>
<span class="n">bb</span><span class="o">.</span><span class="n">emit_output</span><span class="p">(</span><a href="../../../reference/api/python/relax/relax.html#tvm.relax.DataflowVar" title="tvm.relax.DataflowVar" class="sphx-glr-backref-module-tvm-relax sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">gv</span></a><span class="p">)</span>
diff --git a/docs/deep_dive/relax/tutorials/relax_transformation.html b/docs/deep_dive/relax/tutorials/relax_transformation.html
index 6df0b21d239..f772967ab01 100644
--- a/docs/deep_dive/relax/tutorials/relax_transformation.html
+++ b/docs/deep_dive/relax/tutorials/relax_transformation.html
@@ -45,7 +45,7 @@
<script type="text/javascript" src="../../../_static/js/tlcpack_theme.js"></script>
<link rel="index" title="Index" href="../../../genindex.html" />
<link rel="search" title="Search" href="../../../search.html" />
- <link rel="next" title="Python API" href="../../../reference/api/python/index.html" />
+ <link rel="next" title="Overview" href="../../../tirx/overview.html" />
<link rel="prev" title="Relax Creation" href="relax_creation.html" />
</head>
@@ -200,6 +200,16 @@
<li class="toctree-l1"><a class="reference internal" href="../../tensor_ir/index.html">TensorIR</a></li>
<li class="toctree-l1"><a class="reference internal" href="../index.html">Relax</a></li>
</ul>
+<p class="caption" role="heading"><span class="caption-text">TIRx</span></p>
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/overview.html">Overview</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/install.html">Installation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/native_basics.html">TIRx Basics: CUDA C++/PTX native level</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/layout.html">Tensor Layout</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/tile_primitives.html">Tile Primitives</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/arch/index.html">Compiler Internals</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/api/index.html">API Reference</a></li>
+</ul>
<p class="caption" role="heading"><span class="caption-text">API Reference</span></p>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../../../reference/api/python/index.html">Python API</a></li>
@@ -700,7 +710,7 @@ We have also shown how to define and apply custom transformations.</p>
<div class="rst-footer-buttons" role="navigation" aria-label="footer navigation">
- <a href="../../../reference/api/python/index.html" class="btn btn-neutral float-right" title="Python API" accesskey="n" rel="next">Next <span class="fa fa-arrow-circle-right"></span></a>
+ <a href="../../../tirx/overview.html" class="btn btn-neutral float-right" title="Overview" accesskey="n" rel="next">Next <span class="fa fa-arrow-circle-right"></span></a>
<a href="relax_creation.html" class="btn btn-neutral float-left" title="Relax Creation" accesskey="p" rel="prev"><span class="fa fa-arrow-circle-left"></span> Previous</a>
diff --git a/docs/deep_dive/relax/tutorials/sg_execution_times.html b/docs/deep_dive/relax/tutorials/sg_execution_times.html
index 2e2a7866eb5..cf9ab88368d 100644
--- a/docs/deep_dive/relax/tutorials/sg_execution_times.html
+++ b/docs/deep_dive/relax/tutorials/sg_execution_times.html
@@ -198,6 +198,16 @@
<li class="toctree-l1"><a class="reference internal" href="../../tensor_ir/index.html">TensorIR</a></li>
<li class="toctree-l1"><a class="reference internal" href="../index.html">Relax</a></li>
</ul>
+<p class="caption" role="heading"><span class="caption-text">TIRx</span></p>
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/overview.html">Overview</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/install.html">Installation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/native_basics.html">TIRx Basics: CUDA C++/PTX native level</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/layout.html">Tensor Layout</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/tile_primitives.html">Tile Primitives</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/arch/index.html">Compiler Internals</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/api/index.html">API Reference</a></li>
+</ul>
<p class="caption" role="heading"><span class="caption-text">API Reference</span></p>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../../../reference/api/python/index.html">Python API</a></li>
@@ -297,7 +307,7 @@
<section id="computation-times">
<span id="sphx-glr-deep-dive-relax-tutorials-sg-execution-times"></span><h1>Computation times<a class="headerlink" href="#computation-times" title="Link to this heading"></a></h1>
-<p><strong>00:00.278</strong> total execution time for 2 files <strong>from deep_dive/relax/tutorials</strong>:</p>
+<p><strong>00:00.276</strong> total execution time for 2 files <strong>from deep_dive/relax/tutorials</strong>:</p>
<div class="docutils container">
<style scoped>
<link href="https://cdnjs.cloudflare.com/ajax/libs/twitter-bootstrap/5.3.0/css/bootstrap.min.css" rel="stylesheet" />
@@ -319,11 +329,11 @@ $(document).ready( function () {
</thead>
<tbody>
<tr class="row-even"><td><p><a class="reference internal" href="relax_creation.html#sphx-glr-deep-dive-relax-tutorials-relax-creation-py"><span class="std std-ref">Relax Creation</span></a> (<code class="docutils literal notranslate"><span class="pre">relax_creation.py</span></code>)</p></td>
-<td><p>00:00.209</p></td>
+<td><p>00:00.208</p></td>
<td><p>0.0</p></td>
</tr>
<tr class="row-odd"><td><p><a class="reference internal" href="relax_transformation.html#sphx-glr-deep-dive-relax-tutorials-relax-transformation-py"><span class="std std-ref">Transformation</span></a> (<code class="docutils literal notranslate"><span class="pre">relax_transformation.py</span></code>)</p></td>
-<td><p>00:00.069</p></td>
+<td><p>00:00.068</p></td>
<td><p>0.0</p></td>
</tr>
</tbody>
diff --git a/docs/deep_dive/tensor_ir/abstraction.html b/docs/deep_dive/tensor_ir/abstraction.html
index 9bd42bee088..9fdafb8cb6f 100644
--- a/docs/deep_dive/tensor_ir/abstraction.html
+++ b/docs/deep_dive/tensor_ir/abstraction.html
@@ -212,6 +212,16 @@
</li>
<li class="toctree-l1"><a class="reference internal" href="../relax/index.html">Relax</a></li>
</ul>
+<p class="caption" role="heading"><span class="caption-text">TIRx</span></p>
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/overview.html">Overview</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/install.html">Installation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/native_basics.html">TIRx Basics: CUDA C++/PTX native level</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/layout.html">Tensor Layout</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/tile_primitives.html">Tile Primitives</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/arch/index.html">Compiler Internals</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/api/index.html">API Reference</a></li>
+</ul>
<p class="caption" role="heading"><span class="caption-text">API Reference</span></p>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../../reference/api/python/index.html">Python API</a></li>
diff --git a/docs/deep_dive/tensor_ir/index.html b/docs/deep_dive/tensor_ir/index.html
index 5d0c6f5d08d..f3b371e4639 100644
--- a/docs/deep_dive/tensor_ir/index.html
+++ b/docs/deep_dive/tensor_ir/index.html
@@ -209,6 +209,16 @@
</li>
<li class="toctree-l1"><a class="reference internal" href="../relax/index.html">Relax</a></li>
</ul>
+<p class="caption" role="heading"><span class="caption-text">TIRx</span></p>
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/overview.html">Overview</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/install.html">Installation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/native_basics.html">TIRx Basics: CUDA C++/PTX native level</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/layout.html">Tensor Layout</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/tile_primitives.html">Tile Primitives</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/arch/index.html">Compiler Internals</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/api/index.html">API Reference</a></li>
+</ul>
<p class="caption" role="heading"><span class="caption-text">API Reference</span></p>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../../reference/api/python/index.html">Python API</a></li>
diff --git a/docs/deep_dive/tensor_ir/learning.html b/docs/deep_dive/tensor_ir/learning.html
index 17e6e671e0b..76be60ffdd4 100644
--- a/docs/deep_dive/tensor_ir/learning.html
+++ b/docs/deep_dive/tensor_ir/learning.html
@@ -217,6 +217,16 @@
</li>
<li class="toctree-l1"><a class="reference internal" href="../relax/index.html">Relax</a></li>
</ul>
+<p class="caption" role="heading"><span class="caption-text">TIRx</span></p>
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/overview.html">Overview</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/install.html">Installation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/native_basics.html">TIRx Basics: CUDA C++/PTX native level</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/layout.html">Tensor Layout</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/tile_primitives.html">Tile Primitives</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/arch/index.html">Compiler Internals</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../tirx/api/index.html">API Reference</a></li>
+</ul>
<p class="caption" role="heading"><span class="caption-text">API Reference</span></p>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../../reference/api/python/index.html">Python API</a></li>
diff --git a/docs/deep_dive/tensor_ir/tutorials/dlight_gpu_scheduling.html b/docs/deep_dive/tensor_ir/tutorials/dlight_gpu_scheduling.html
index 805721c2b1e..cd1fbdd4193 100644
--- a/docs/deep_dive/tensor_ir/tutorials/dlight_gpu_scheduling.html
+++ b/docs/deep_dive/tensor_ir/tutorials/dlight_gpu_scheduling.html
@@ -200,6 +200,16 @@
<li class="toctree-l1"><a class="reference internal" href="../index.html">TensorIR</a></li>
<li class="toctree-l1"><a class="reference internal" href="../../relax/index.html">Relax</a></li>
</ul>
+<p class="caption" role="heading"><span class="caption-text">TIRx</span></p>
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/overview.html">Overview</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/install.html">Installation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/native_basics.html">TIRx Basics: CUDA C++/PTX native level</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/layout.html">Tensor Layout</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/tile_primitives.html">Tile Primitives</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/arch/index.html">Compiler Internals</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/api/index.html">API Reference</a></li>
+</ul>
<p class="caption" role="heading"><span class="caption-text">API Reference</span></p>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../../../reference/api/python/index.html">Python API</a></li>
@@ -365,8 +375,8 @@ produces a general-reduction kernel, and <code class="docutils literal notransla
</div>
<p>At this point every TIR function in <code class="docutils literal notranslate"><span class="pre">mod</span></code> is <strong>unscheduled</strong> — it has no thread bindings
and would not run efficiently on a GPU. Let’s see what functions we have:</p>
-<div class="highlight-Python notranslate"><div class="highlight"><pre><span></span><span class="k">for</span> <a href="../../../reference/api/python/ir.html#tvm.ir.GlobalVar" title="tvm.ir.GlobalVar" class="sphx-glr-backref-module-tvm-ir sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">gv</span></a><span class="p">,</span> <a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref-module-tvm-tirx sph [...]
- <span class="k">if</span> <span class="nb">isinstance</span><span class="p">(</span><a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">func</span></a><span class="p">,</span> <a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref-module-tvm-tirx sphx-glr-bac [...]
+<div class="highlight-Python notranslate"><div class="highlight"><pre><span></span><span class="k">for</span> <a href="../../../reference/api/python/ir.html#tvm.ir.GlobalVar" title="tvm.ir.GlobalVar" class="sphx-glr-backref-module-tvm-ir sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">gv</span></a><span class="p">,</span> <a href="../../../tirx/api/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-typ [...]
+ <span class="k">if</span> <span class="nb">isinstance</span><span class="p">(</span><a href="../../../tirx/api/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">func</span></a><span class="p">,</span> <a href="../../../tirx/api/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class"><span class="n [...]
<span class="nb">print</span><span class="p">(</span><span class="sa">f</span><span class="s2">" </span><span class="si">{</span><a href="../../../reference/api/python/ir.html#tvm.ir.GlobalVar" title="tvm.ir.GlobalVar" class="sphx-glr-backref-module-tvm-ir sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">gv</span></a><span class="o">.</span><span class="n">name_hint</span><span class="si">}</span><span class="s2">"</span><span class="p">)</span>
</pre></div>
</div>
@@ -655,15 +665,15 @@ does not log this directly, but you can figure it out by applying rules one at a
<span class="k">for</span> <a href="https://docs.python.org/3/library/stdtypes.html#str" title="builtins.str" class="sphx-glr-backref-module-builtins sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">rule_name</span></a><span class="p">,</span> <span class="n">rule</span> <span class="ow">in</span> <a href="https://docs.python.org/3/library/collections.html#collections.OrderedDict" title="collections.OrderedDict" class="sphx-glr-backref-module-collections sphx-glr [...]
<span class="k">with</span> <a href="../../../reference/api/python/target.html#tvm.target.Target" title="tvm.target.Target" class="sphx-glr-backref-module-tvm-target sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">target</span></a><span class="p">:</span>
<span class="n">test_mod</span> <span class="o">=</span> <a href="../../../reference/api/python/transform.html#tvm.ir.transform.ModulePass" title="tvm.ir.transform.ModulePass" class="sphx-glr-backref-module-tvm-ir-transform sphx-glr-backref-type-py-class"><span class="n">dl</span><span class="o">.</span><span class="n">ApplyDefaultSchedule</span></a><span class="p">(</span><span class="n">rule</span><span class="p">)(</span><span class="n">mod</span><span class="p">)</span>
- <span class="k">for</span> <a href="../../../reference/api/python/ir.html#tvm.ir.GlobalVar" title="tvm.ir.GlobalVar" class="sphx-glr-backref-module-tvm-ir sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">gv</span></a><span class="p">,</span> <a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">func</sp [...]
- <span class="k">if</span> <span class="nb">isinstance</span><span class="p">(</span><a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">func</span></a><span class="p">,</span> <a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref-module-tvm-tirx sphx-glr [...]
+ <span class="k">for</span> <a href="../../../reference/api/python/ir.html#tvm.ir.GlobalVar" title="tvm.ir.GlobalVar" class="sphx-glr-backref-module-tvm-ir sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">gv</span></a><span class="p">,</span> <a href="../../../tirx/api/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">func</span></a> <span cla [...]
+ <span class="k">if</span> <span class="nb">isinstance</span><span class="p">(</span><a href="../../../tirx/api/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">func</span></a><span class="p">,</span> <a href="../../../tirx/api/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class"><span clas [...]
<span class="k">if</span> <span class="s2">"tirx.is_scheduled"</span> <span class="ow">in</span> <a href="../../../reference/api/python/ir.html#tvm.ir.BaseFunc.attrs" title="tvm.ir.BaseFunc.attrs" class="sphx-glr-backref-module-tvm-ir sphx-glr-backref-type-py-property"><span class="n">func</span><span class="o">.</span><span class="n">attrs</span></a> <span class="ow">and</span> <a href="../../../reference/api/python/ir.html#tvm.ir.BaseFunc.attrs" title="tvm.ir.Base [...]
<a href="https://docs.python.org/3/library/stdtypes.html#dict" title="builtins.dict" class="sphx-glr-backref-module-builtins sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">rule_assignment</span></a><span class="p">[</span><a href="../../../reference/api/python/ir.html#tvm.ir.GlobalVar" title="tvm.ir.GlobalVar" class="sphx-glr-backref-module-tvm-ir sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">gv</span></a><span class= [...]
</pre></div>
</div>
<p><strong>Step 2</strong>: Functions not claimed by any specialized rule will fall through to <code class="docutils literal notranslate"><span class="pre">Fallback</span></code>.</p>
<div class="highlight-Python notranslate"><div class="highlight"><pre><span></span><a href="https://docs.python.org/3/library/stdtypes.html#list" title="builtins.list" class="sphx-glr-backref-module-builtins sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">all_tir_funcs</span></a> <span class="o">=</span> <span class="p">[</span>
- <a href="../../../reference/api/python/ir.html#tvm.ir.GlobalVar" title="tvm.ir.GlobalVar" class="sphx-glr-backref-module-tvm-ir sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">gv</span></a><span class="o">.</span><span class="n">name_hint</span> <span class="k">for</span> <a href="../../../reference/api/python/ir.html#tvm.ir.GlobalVar" title="tvm.ir.GlobalVar" class="sphx-glr-backref-module-tvm-ir sphx-glr-backref-type-py-class sphx-glr-backref-instance"><sp [...]
+ <a href="../../../reference/api/python/ir.html#tvm.ir.GlobalVar" title="tvm.ir.GlobalVar" class="sphx-glr-backref-module-tvm-ir sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">gv</span></a><span class="o">.</span><span class="n">name_hint</span> <span class="k">for</span> <a href="../../../reference/api/python/ir.html#tvm.ir.GlobalVar" title="tvm.ir.GlobalVar" class="sphx-glr-backref-module-tvm-ir sphx-glr-backref-type-py-class sphx-glr-backref-instance"><sp [...]
<span class="p">]</span>
<a href="https://docs.python.org/3/library/stdtypes.html#list" title="builtins.list" class="sphx-glr-backref-module-builtins sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">fallback_funcs</span></a> <span class="o">=</span> <span class="p">[</span><span class="n">name</span> <span class="k">for</span> <span class="n">name</span> <span class="ow">in</span> <a href="https://docs.python.org/3/library/stdtypes.html#list" title="builtins.list" class="sphx-glr-backref [...]
@@ -747,11 +757,11 @@ with <code class="docutils literal notranslate"><span class="pre">op_names</span
<span class="nd">@ScheduleRule</span><span class="o">.</span><span class="n">from_callable</span><span class="p">(</span><span class="s2">"MyTileAndBind"</span><span class="p">)</span>
-<span class="k">def</span><span class="w"> </span><span class="nf">my_tile_and_bind</span><span class="p">(</span><a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">func</span></a><span class="p">:</span> <a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref-mo [...]
+<span class="k">def</span><span class="w"> </span><span class="nf">my_tile_and_bind</span><span class="p">(</span><a href="../../../tirx/api/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">func</span></a><span class="p">:</span> <a href="../../../tirx/api/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-typ [...]
<span class="w"> </span><span class="sd">"""A minimal rule: for single-block injective functions, tile and bind to GPU threads."""</span>
- <span class="k">if</span> <span class="ow">not</span> <span class="nb">isinstance</span><span class="p">(</span><a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">func</span></a><span class="p">,</span> <a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref- [...]
+ <span class="k">if</span> <span class="ow">not</span> <span class="nb">isinstance</span><span class="p">(</span><a href="../../../tirx/api/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">func</span></a><span class="p">,</span> <a href="../../../tirx/api/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-t [...]
<span class="k">return</span> <span class="kc">None</span>
- <span class="n">sch</span> <span class="o">=</span> <span class="n">s_tir</span><span class="o">.</span><span class="n">Schedule</span><span class="p">(</span><a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">func</span></a><span class="p">)</span>
+ <span class="n">sch</span> <span class="o">=</span> <span class="n">s_tir</span><span class="o">.</span><span class="n">Schedule</span><span class="p">(</span><a href="../../../tirx/api/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">func</span></a><span class="p">)</span>
<span class="c1"># Use normalize_prim_func to get block info with correct spatial/reduction classification.</span>
<span class="c1"># This is the same analysis used by built-in DLight rules.</span>
<span class="n">block_infos</span> <span class="o">=</span> <a href="../../../reference/api/python/s_tir/dlight.html#tvm.s_tir.dlight.normalize_prim_func" title="tvm.s_tir.dlight.normalize_prim_func" class="sphx-glr-backref-module-tvm-s_tir-dlight sphx-glr-backref-type-py-function"><span class="n">normalize_prim_func</span></a><span class="p">(</span><span class="n">sch</span><span class="p">)</span>
diff --git a/docs/deep_dive/tensor_ir/tutorials/index.html b/docs/deep_dive/tensor_ir/tutorials/index.html
index 9da982f636c..3c3f5b814cf 100644
--- a/docs/deep_dive/tensor_ir/tutorials/index.html
+++ b/docs/deep_dive/tensor_ir/tutorials/index.html
@@ -199,6 +199,16 @@
<li class="toctree-l1"><a class="reference internal" href="../index.html">TensorIR</a></li>
<li class="toctree-l1"><a class="reference internal" href="../../relax/index.html">Relax</a></li>
</ul>
+<p class="caption" role="heading"><span class="caption-text">TIRx</span></p>
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/overview.html">Overview</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/install.html">Installation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/native_basics.html">TIRx Basics: CUDA C++/PTX native level</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/layout.html">Tensor Layout</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/tile_primitives.html">Tile Primitives</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/arch/index.html">Compiler Internals</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/api/index.html">API Reference</a></li>
+</ul>
<p class="caption" role="heading"><span class="caption-text">API Reference</span></p>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../../../reference/api/python/index.html">Python API</a></li>
diff --git a/docs/deep_dive/tensor_ir/tutorials/meta_schedule.html b/docs/deep_dive/tensor_ir/tutorials/meta_schedule.html
index a63e4931c99..0414d560d38 100644
--- a/docs/deep_dive/tensor_ir/tutorials/meta_schedule.html
+++ b/docs/deep_dive/tensor_ir/tutorials/meta_schedule.html
@@ -200,6 +200,16 @@
<li class="toctree-l1"><a class="reference internal" href="../index.html">TensorIR</a></li>
<li class="toctree-l1"><a class="reference internal" href="../../relax/index.html">Relax</a></li>
</ul>
+<p class="caption" role="heading"><span class="caption-text">TIRx</span></p>
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/overview.html">Overview</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/install.html">Installation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/native_basics.html">TIRx Basics: CUDA C++/PTX native level</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/layout.html">Tensor Layout</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/tile_primitives.html">Tile Primitives</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/arch/index.html">Compiler Internals</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/api/index.html">API Reference</a></li>
+</ul>
<p class="caption" role="heading"><span class="caption-text">API Reference</span></p>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../../../reference/api/python/index.html">Python API</a></li>
diff --git a/docs/deep_dive/tensor_ir/tutorials/sg_execution_times.html b/docs/deep_dive/tensor_ir/tutorials/sg_execution_times.html
index 1c1640eacd6..3ceb72ac257 100644
--- a/docs/deep_dive/tensor_ir/tutorials/sg_execution_times.html
+++ b/docs/deep_dive/tensor_ir/tutorials/sg_execution_times.html
@@ -198,6 +198,16 @@
<li class="toctree-l1"><a class="reference internal" href="../index.html">TensorIR</a></li>
<li class="toctree-l1"><a class="reference internal" href="../../relax/index.html">Relax</a></li>
</ul>
+<p class="caption" role="heading"><span class="caption-text">TIRx</span></p>
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/overview.html">Overview</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/install.html">Installation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/native_basics.html">TIRx Basics: CUDA C++/PTX native level</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/layout.html">Tensor Layout</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/tile_primitives.html">Tile Primitives</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/arch/index.html">Compiler Internals</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/api/index.html">API Reference</a></li>
+</ul>
<p class="caption" role="heading"><span class="caption-text">API Reference</span></p>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../../../reference/api/python/index.html">Python API</a></li>
@@ -297,7 +307,7 @@
<section id="computation-times">
<span id="sphx-glr-deep-dive-tensor-ir-tutorials-sg-execution-times"></span><h1>Computation times<a class="headerlink" href="#computation-times" title="Link to this heading"></a></h1>
-<p><strong>00:00.894</strong> total execution time for 4 files <strong>from deep_dive/tensor_ir/tutorials</strong>:</p>
+<p><strong>00:00.895</strong> total execution time for 4 files <strong>from deep_dive/tensor_ir/tutorials</strong>:</p>
<div class="docutils container">
<style scoped>
<link href="https://cdnjs.cloudflare.com/ajax/libs/twitter-bootstrap/5.3.0/css/bootstrap.min.css" rel="stylesheet" />
@@ -319,7 +329,7 @@ $(document).ready( function () {
</thead>
<tbody>
<tr class="row-even"><td><p><a class="reference internal" href="tir_creation.html#sphx-glr-deep-dive-tensor-ir-tutorials-tir-creation-py"><span class="std std-ref">TensorIR Creation</span></a> (<code class="docutils literal notranslate"><span class="pre">tir_creation.py</span></code>)</p></td>
-<td><p>00:00.380</p></td>
+<td><p>00:00.383</p></td>
<td><p>0.0</p></td>
</tr>
<tr class="row-odd"><td><p><a class="reference internal" href="tir_transformation.html#sphx-glr-deep-dive-tensor-ir-tutorials-tir-transformation-py"><span class="std std-ref">Transformation</span></a> (<code class="docutils literal notranslate"><span class="pre">tir_transformation.py</span></code>)</p></td>
diff --git a/docs/deep_dive/tensor_ir/tutorials/tir_creation.html b/docs/deep_dive/tensor_ir/tutorials/tir_creation.html
index 21d326557be..1135b0db41a 100644
--- a/docs/deep_dive/tensor_ir/tutorials/tir_creation.html
+++ b/docs/deep_dive/tensor_ir/tutorials/tir_creation.html
@@ -201,6 +201,16 @@
<li class="toctree-l1"><a class="reference internal" href="../index.html">TensorIR</a></li>
<li class="toctree-l1"><a class="reference internal" href="../../relax/index.html">Relax</a></li>
</ul>
+<p class="caption" role="heading"><span class="caption-text">TIRx</span></p>
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/overview.html">Overview</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/install.html">Installation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/native_basics.html">TIRx Basics: CUDA C++/PTX native level</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/layout.html">Tensor Layout</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/tile_primitives.html">Tile Primitives</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/arch/index.html">Compiler Internals</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/api/index.html">API Reference</a></li>
+</ul>
<p class="caption" role="heading"><span class="caption-text">API Reference</span></p>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../../../reference/api/python/index.html">Python API</a></li>
@@ -349,11 +359,11 @@ format of the ir_module and in TVMScript:</p>
<a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">Y</span></a> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">alloc_buffer</span><span class="p">((</span><span class="mi">128</span><span class="p">,</span> <span class="mi">128</span><span class="p">),</span> <a href="https://docs.python.org/3/li [...]
<span class="k">for</span> <span class="n">i</span> <span class="ow">in</span> <span class="nb">range</span><span class="p">(</span><span class="mi">128</span><span class="p">):</span>
<span class="k">for</span> <span class="n">j</span> <span class="ow">in</span> <span class="nb">range</span><span class="p">(</span><span class="mi">128</span><span class="p">):</span>
- <span class="k">for</span> <a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.IterVar" title="tvm.tirx.IterVar" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">k</span></a> <span class="ow">in</span> <span class="nb">range</span><span class="p">(</span><span class="mi">128</span><span class="p">):</span>
+ <span class="k">for</span> <a href="../../../tirx/api/tirx.html#tvm.tirx.IterVar" title="tvm.tirx.IterVar" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">k</span></a> <span class="ow">in</span> <span class="nb">range</span><span class="p">(</span><span class="mi">128</span><span class="p">):</span>
<span class="k">with</span> <span class="n">T</span><span class="o">.</span><span class="n">sblock</span><span class="p">(</span><span class="s2">"Y"</span><span class="p">):</span>
<span class="n">vi</span> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">axis</span><span class="o">.</span><span class="n">spatial</span><span class="p">(</span><span class="mi">128</span><span class="p">,</span> <span class="n">i</span><span class="p">)</span>
<span class="n">vj</span> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">axis</span><span class="o">.</span><span class="n">spatial</span><span class="p">(</span><span class="mi">128</span><span class="p">,</span> <span class="n">j</span><span class="p">)</span>
- <span class="n">vk</span> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">axis</span><span class="o">.</span><span class="n">reduce</span><span class="p">(</span><span class="mi">128</span><span class="p">,</span> <a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.IterVar" title="tvm.tirx.IterVar" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">k< [...]
+ <span class="n">vk</span> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">axis</span><span class="o">.</span><span class="n">reduce</span><span class="p">(</span><span class="mi">128</span><span class="p">,</span> <a href="../../../tirx/api/tirx.html#tvm.tirx.IterVar" title="tvm.tirx.IterVar" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">k</span></a><span c [...]
<span class="n">T</span><span class="o">.</span><span class="n">reads</span><span class="p">(</span><a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">A</span></a><span class="p">[</span><span class="n">vi</span><span class="p">,</span> <span class="n">vk</span><span class="p">],</span> <a href="../../../reference/api/pyt [...]
<span class="n">T</span><span class="o">.</span><span class="n">writes</span><span class="p">(</span><a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">Y</span></a><span class="p">[</span><span class="n">vi</span><span class="p">,</span> <span class="n">vj</span><span class="p">])</span>
<span class="k">with</span> <span class="n">T</span><span class="o">.</span><span class="n">init</span><span class="p">():</span>
@@ -389,9 +399,9 @@ be inferred from the block body;</p></li>
<a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">C</span></a><span class="p">:</span> <span class="n">T</span><span class="o">.</span><span class="n">Buffer</span><span class="p">((</span><span class="mi">128</span><span class="p">,</span> <span class="mi">128</span><span class="p">),</span> <span class="s2">"float32"</span>< [...]
<span class="p">):</span>
<a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">Y</span></a> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">alloc_buffer</span><span class="p">((</span><span class="mi">128</span><span class="p">,</span> <span class="mi">128</span><span class="p">),</span> <a href="https://docs.python.org/3/li [...]
- <span class="k">for</span> <span class="n">i</span><span class="p">,</span> <span class="n">j</span><span class="p">,</span> <a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.IterVar" title="tvm.tirx.IterVar" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">k</span></a> <span class="ow">in</span> <span class="n">T</span><span class="o">.</span><span class="n">grid</span><span class="p">(</span><span cla [...]
+ <span class="k">for</span> <span class="n">i</span><span class="p">,</span> <span class="n">j</span><span class="p">,</span> <a href="../../../tirx/api/tirx.html#tvm.tirx.IterVar" title="tvm.tirx.IterVar" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">k</span></a> <span class="ow">in</span> <span class="n">T</span><span class="o">.</span><span class="n">grid</span><span class="p">(</span><span class="mi">128</span [...]
<span class="k">with</span> <span class="n">T</span><span class="o">.</span><span class="n">sblock</span><span class="p">(</span><span class="s2">"Y"</span><span class="p">):</span>
- <span class="n">vi</span><span class="p">,</span> <span class="n">vj</span><span class="p">,</span> <span class="n">vk</span> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">axis</span><span class="o">.</span><span class="n">remap</span><span class="p">(</span><span class="s2">"SSR"</span><span class="p">,</span> <span class="p">[</span><span class="n">i</span><span class="p">,</span> <span class="n">j</span><span class=" [...]
+ <span class="n">vi</span><span class="p">,</span> <span class="n">vj</span><span class="p">,</span> <span class="n">vk</span> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">axis</span><span class="o">.</span><span class="n">remap</span><span class="p">(</span><span class="s2">"SSR"</span><span class="p">,</span> <span class="p">[</span><span class="n">i</span><span class="p">,</span> <span class="n">j</span><span class=" [...]
<span class="k">with</span> <span class="n">T</span><span class="o">.</span><span class="n">init</span><span class="p">():</span>
<a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">Y</span></a><span class="p">[</span><span class="n">vi</span><span class="p">,</span> <span class="n">vj</span><span class="p">]</span> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">float32</span><span class="p">(</span><span class=" [...]
<a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">Y</span></a><span class="p">[</span><span class="n">vi</span><span class="p">,</span> <span class="n">vj</span><span class="p">]</span> <span class="o">=</span> <a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm- [...]
@@ -415,7 +425,7 @@ be inferred from the block body;</p></li>
interaction with Python is feasible. For instance, Python variables can
be used to ascertain the shape and data type of a TensorIR.</p>
<div class="highlight-Python notranslate"><div class="highlight"><pre><span></span><span class="c1"># Python variables</span>
-<a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">M</span></a> <span class="o">=</span> <a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">N</span></a> <span class="o">=</span> <a href=". [...]
+<a href="../../../tirx/api/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">M</span></a> <span class="o">=</span> <a href="../../../tirx/api/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">N</span></a> <span class="o">=</span> <a href="../../../tirx/api/tirx.html#tvm.tir [...]
<a href="https://docs.python.org/3/library/stdtypes.html#str" title="builtins.str" class="sphx-glr-backref-module-builtins sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">dtype</span></a> <span class="o">=</span> <span class="s2">"float32"</span>
@@ -424,18 +434,18 @@ be used to ascertain the shape and data type of a TensorIR.</p>
<span class="k">class</span><span class="w"> </span><span class="nc">ConciseModuleFromPython</span><span class="p">:</span>
<span class="nd">@T</span><span class="o">.</span><span class="n">prim_func</span><span class="p">(</span><span class="n">s_tir</span><span class="o">=</span><span class="kc">True</span><span class="p">)</span>
<span class="k">def</span><span class="w"> </span><span class="nf">mm_relu</span><span class="p">(</span>
- <a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">A</span></a><span class="p">:</span> <span class="n">T</span><span class="o">.</span><span class="n">Buffer</span><span class="p">((</span><a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-typ [...]
- <a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">B</span></a><span class="p">:</span> <span class="n">T</span><span class="o">.</span><span class="n">Buffer</span><span class="p">((</span><a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-typ [...]
- <a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">C</span></a><span class="p">:</span> <span class="n">T</span><span class="o">.</span><span class="n">Buffer</span><span class="p">((</span><a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-typ [...]
+ <a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">A</span></a><span class="p">:</span> <span class="n">T</span><span class="o">.</span><span class="n">Buffer</span><span class="p">((</span><a href="../../../tirx/api/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-g [...]
+ <a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">B</span></a><span class="p">:</span> <span class="n">T</span><span class="o">.</span><span class="n">Buffer</span><span class="p">((</span><a href="../../../tirx/api/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-g [...]
+ <a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">C</span></a><span class="p">:</span> <span class="n">T</span><span class="o">.</span><span class="n">Buffer</span><span class="p">((</span><a href="../../../tirx/api/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-g [...]
<span class="p">):</span>
- <a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">Y</span></a> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">alloc_buffer</span><span class="p">((</span><a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-back [...]
- <span class="k">for</span> <span class="n">i</span><span class="p">,</span> <span class="n">j</span><span class="p">,</span> <a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.IterVar" title="tvm.tirx.IterVar" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">k</span></a> <span class="ow">in</span> <span class="n">T</span><span class="o">.</span><span class="n">grid</span><span class="p">(</span><a href=" [...]
+ <a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">Y</span></a> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">alloc_buffer</span><span class="p">((</span><a href="../../../tirx/api/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class [...]
+ <span class="k">for</span> <span class="n">i</span><span class="p">,</span> <span class="n">j</span><span class="p">,</span> <a href="../../../tirx/api/tirx.html#tvm.tirx.IterVar" title="tvm.tirx.IterVar" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">k</span></a> <span class="ow">in</span> <span class="n">T</span><span class="o">.</span><span class="n">grid</span><span class="p">(</span><a href="../../../tirx/api [...]
<span class="k">with</span> <span class="n">T</span><span class="o">.</span><span class="n">sblock</span><span class="p">(</span><span class="s2">"Y"</span><span class="p">):</span>
- <span class="n">vi</span><span class="p">,</span> <span class="n">vj</span><span class="p">,</span> <span class="n">vk</span> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">axis</span><span class="o">.</span><span class="n">remap</span><span class="p">(</span><span class="s2">"SSR"</span><span class="p">,</span> <span class="p">[</span><span class="n">i</span><span class="p">,</span> <span class="n">j</span><span class=" [...]
+ <span class="n">vi</span><span class="p">,</span> <span class="n">vj</span><span class="p">,</span> <span class="n">vk</span> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">axis</span><span class="o">.</span><span class="n">remap</span><span class="p">(</span><span class="s2">"SSR"</span><span class="p">,</span> <span class="p">[</span><span class="n">i</span><span class="p">,</span> <span class="n">j</span><span class=" [...]
<span class="k">with</span> <span class="n">T</span><span class="o">.</span><span class="n">init</span><span class="p">():</span>
<a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">Y</span></a><span class="p">[</span><span class="n">vi</span><span class="p">,</span> <span class="n">vj</span><span class="p">]</span> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">cast</span><span class="p">(</span><span class="n"> [...]
<a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">Y</span></a><span class="p">[</span><span class="n">vi</span><span class="p">,</span> <span class="n">vj</span><span class="p">]</span> <span class="o">=</span> <a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm- [...]
- <span class="k">for</span> <span class="n">i</span><span class="p">,</span> <span class="n">j</span> <span class="ow">in</span> <span class="n">T</span><span class="o">.</span><span class="n">grid</span><span class="p">(</span><a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">M</span></a><span class="p">,</span> <a href="../../.. [...]
+ <span class="k">for</span> <span class="n">i</span><span class="p">,</span> <span class="n">j</span> <span class="ow">in</span> <span class="n">T</span><span class="o">.</span><span class="n">grid</span><span class="p">(</span><a href="../../../tirx/api/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">M</span></a><span class="p">,</span> <a href="../../../tirx/api/tirx.ht [...]
<span class="k">with</span> <span class="n">T</span><span class="o">.</span><span class="n">sblock</span><span class="p">(</span><span class="s2">"C"</span><span class="p">):</span>
<span class="n">vi</span><span class="p">,</span> <span class="n">vj</span> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">axis</span><span class="o">.</span><span class="n">remap</span><span class="p">(</span><span class="s2">"SS"</span><span class="p">,</span> <span class="p">[</span><span class="n">i</span><span class="p">,</span> <span class="n">j</span><span class="p">])</span>
<a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">C</span></a><span class="p">[</span><span class="n">vi</span><span class="p">,</span> <span class="n">vj</span><span class="p">]</span> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">max</span><span class="p">(</span><a href="../../../ref [...]
@@ -459,31 +469,31 @@ be used to ascertain the shape and data type of a TensorIR.</p>
<span class="nd">@T</span><span class="o">.</span><span class="n">prim_func</span><span class="p">(</span><span class="n">s_tir</span><span class="o">=</span><span class="kc">True</span><span class="p">)</span>
<span class="k">def</span><span class="w"> </span><span class="nf">mm_relu</span><span class="p">(</span><span class="n">a</span><span class="p">:</span> <span class="n">T</span><span class="o">.</span><span class="n">handle</span><span class="p">,</span> <span class="n">b</span><span class="p">:</span> <span class="n">T</span><span class="o">.</span><span class="n">handle</span><span class="p">,</span> <span class="n">c</span><span class="p">:</span> <span class="n">T</span><span cl [...]
<span class="c1"># Dynamic shape definition</span>
- <a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">M</span></a> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">int32</span><span class="p">()</span>
- <a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">N</span></a> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">int32</span><span class="p">()</span>
- <a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">K</span></a> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">int32</span><span class="p">()</span>
+ <a href="../../../tirx/api/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">M</span></a> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">int32</span><span class="p">()</span>
+ <a href="../../../tirx/api/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">N</span></a> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">int32</span><span class="p">()</span>
+ <a href="../../../tirx/api/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">K</span></a> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">int32</span><span class="p">()</span>
<span class="c1"># Bind the input buffers with the dynamic shapes</span>
- <a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">A</span></a> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">match_buffer</span><span class="p">(</span><span class="n">a</span><span class="p">,</span> <span class="p">[</span><a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.Var" ti [...]
- <a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">B</span></a> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">match_buffer</span><span class="p">(</span><span class="n">b</span><span class="p">,</span> <span class="p">[</span><a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.Var" ti [...]
- <a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">C</span></a> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">match_buffer</span><span class="p">(</span><span class="n">c</span><span class="p">,</span> <span class="p">[</span><a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.Var" ti [...]
- <a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">Y</span></a> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">alloc_buffer</span><span class="p">((</span><a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-back [...]
- <span class="k">for</span> <span class="n">i</span><span class="p">,</span> <span class="n">j</span><span class="p">,</span> <a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.IterVar" title="tvm.tirx.IterVar" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">k</span></a> <span class="ow">in</span> <span class="n">T</span><span class="o">.</span><span class="n">grid</span><span class="p">(</span><a href=" [...]
+ <a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">A</span></a> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">match_buffer</span><span class="p">(</span><span class="n">a</span><span class="p">,</span> <span class="p">[</span><a href="../../../tirx/api/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var [...]
+ <a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">B</span></a> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">match_buffer</span><span class="p">(</span><span class="n">b</span><span class="p">,</span> <span class="p">[</span><a href="../../../tirx/api/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var [...]
+ <a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">C</span></a> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">match_buffer</span><span class="p">(</span><span class="n">c</span><span class="p">,</span> <span class="p">[</span><a href="../../../tirx/api/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var [...]
+ <a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">Y</span></a> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">alloc_buffer</span><span class="p">((</span><a href="../../../tirx/api/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class [...]
+ <span class="k">for</span> <span class="n">i</span><span class="p">,</span> <span class="n">j</span><span class="p">,</span> <a href="../../../tirx/api/tirx.html#tvm.tirx.IterVar" title="tvm.tirx.IterVar" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">k</span></a> <span class="ow">in</span> <span class="n">T</span><span class="o">.</span><span class="n">grid</span><span class="p">(</span><a href="../../../tirx/api [...]
<span class="k">with</span> <span class="n">T</span><span class="o">.</span><span class="n">sblock</span><span class="p">(</span><span class="s2">"Y"</span><span class="p">):</span>
- <span class="n">vi</span><span class="p">,</span> <span class="n">vj</span><span class="p">,</span> <span class="n">vk</span> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">axis</span><span class="o">.</span><span class="n">remap</span><span class="p">(</span><span class="s2">"SSR"</span><span class="p">,</span> <span class="p">[</span><span class="n">i</span><span class="p">,</span> <span class="n">j</span><span class=" [...]
+ <span class="n">vi</span><span class="p">,</span> <span class="n">vj</span><span class="p">,</span> <span class="n">vk</span> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">axis</span><span class="o">.</span><span class="n">remap</span><span class="p">(</span><span class="s2">"SSR"</span><span class="p">,</span> <span class="p">[</span><span class="n">i</span><span class="p">,</span> <span class="n">j</span><span class=" [...]
<span class="k">with</span> <span class="n">T</span><span class="o">.</span><span class="n">init</span><span class="p">():</span>
<a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">Y</span></a><span class="p">[</span><span class="n">vi</span><span class="p">,</span> <span class="n">vj</span><span class="p">]</span> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">cast</span><span class="p">(</span><span class="n"> [...]
<a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">Y</span></a><span class="p">[</span><span class="n">vi</span><span class="p">,</span> <span class="n">vj</span><span class="p">]</span> <span class="o">=</span> <a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm- [...]
- <span class="k">for</span> <span class="n">i</span><span class="p">,</span> <span class="n">j</span> <span class="ow">in</span> <span class="n">T</span><span class="o">.</span><span class="n">grid</span><span class="p">(</span><a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">M</span></a><span class="p">,</span> <a href="../../.. [...]
+ <span class="k">for</span> <span class="n">i</span><span class="p">,</span> <span class="n">j</span> <span class="ow">in</span> <span class="n">T</span><span class="o">.</span><span class="n">grid</span><span class="p">(</span><a href="../../../tirx/api/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">M</span></a><span class="p">,</span> <a href="../../../tirx/api/tirx.ht [...]
<span class="k">with</span> <span class="n">T</span><span class="o">.</span><span class="n">sblock</span><span class="p">(</span><span class="s2">"C"</span><span class="p">):</span>
<span class="n">vi</span><span class="p">,</span> <span class="n">vj</span> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">axis</span><span class="o">.</span><span class="n">remap</span><span class="p">(</span><span class="s2">"SS"</span><span class="p">,</span> <span class="p">[</span><span class="n">i</span><span class="p">,</span> <span class="n">j</span><span class="p">])</span>
<a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">C</span></a><span class="p">[</span><span class="n">vi</span><span class="p">,</span> <span class="n">vj</span><span class="p">]</span> <span class="o">=</span> <span class="n">T</span><span class="o">.</span><span class="n">max</span><span class="p">(</span><a href="../../../ref [...]
</pre></div>
</div>
<p>Now let’s check the runtime dynamic shape inference:</p>
-<div class="highlight-Python notranslate"><div class="highlight"><pre><span></span><span class="k">def</span><span class="w"> </span><span class="nf">evaluate_dynamic_shape</span><span class="p">(</span><span class="n">lib</span><span class="p">:</span> <span class="n">tvm</span><span class="o">.</span><span class="n">runtime</span><span class="o">.</span><span class="n">Module</span><span class="p">,</span> <span class="n">m</span><span class="p">:</span> <span class="nb">int</span><spa [...]
- <a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">A</span></a> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">runtime</span><span class="o">.</span><span class="n">tensor</span><span class="p">(</span><span class="n">np</span><span class="o">.</span><span class="n">random</span><span class="o">.</ [...]
- <a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">B</span></a> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">runtime</span><span class="o">.</span><span class="n">tensor</span><span class="p">(</span><span class="n">np</span><span class="o">.</span><span class="n">random</span><span class="o">.</ [...]
+<div class="highlight-Python notranslate"><div class="highlight"><pre><span></span><span class="k">def</span><span class="w"> </span><span class="nf">evaluate_dynamic_shape</span><span class="p">(</span><span class="n">lib</span><span class="p">:</span> <span class="n">tvm</span><span class="o">.</span><span class="n">runtime</span><span class="o">.</span><span class="n">Module</span><span class="p">,</span> <span class="n">m</span><span class="p">:</span> <span class="nb">int</span><spa [...]
+ <a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">A</span></a> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">runtime</span><span class="o">.</span><span class="n">tensor</span><span class="p">(</span><span class="n">np</span><span class="o">.</span><span class="n">random</span><span class="o">.</ [...]
+ <a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">B</span></a> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">runtime</span><span class="o">.</span><span class="n">tensor</span><span class="p">(</span><span class="n">np</span><span class="o">.</span><span class="n">random</span><span class="o">.</ [...]
<a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">C</span></a> <span class="o">=</span> <span class="n">tvm</span><span class="o">.</span><span class="n">runtime</span><span class="o">.</span><span class="n">tensor</span><span class="p">(</span><span class="n">np</span><span class="o">.</span><span class="n">zeros</span><span class="p">((</ [...]
<span class="n">lib</span><span class="p">(</span><a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">A</span></a><span class="p">,</span> <a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">B</span>< [...]
<span class="k">return</span> <a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">C</span><span class="o">.</span><span class="n">numpy</span></a><span class="p">()</span>
@@ -492,8 +502,8 @@ be used to ascertain the shape and data type of a TensorIR.</p>
<span class="c1"># Compile lib only once</span>
<span class="n">dyn_shape_lib</span> <span class="o">=</span> <a href="../../../reference/api/python/driver.html#tvm.compile" title="tvm.compile" class="sphx-glr-backref-module-tvm sphx-glr-backref-type-py-function"><span class="n">tvm</span><span class="o">.</span><span class="n">compile</span></a><span class="p">(</span><span class="n">DynamicShapeModule</span><span class="p">,</span> <span class="n">target</span><span class="o">=</span><span class="s2">"llvm"</span><span cla [...]
<span class="c1"># Able to handle different shapes</span>
-<span class="nb">print</span><span class="p">(</span><span class="n">evaluate_dynamic_shape</span><span class="p">(</span><span class="n">dyn_shape_lib</span><span class="p">,</span> <span class="n">m</span><span class="o">=</span><span class="mi">4</span><span class="p">,</span> <span class="n">n</span><span class="o">=</span><span class="mi">4</span><span class="p">,</span> <a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.IterVar" title="tvm.tirx.IterVar" class="sphx-glr- [...]
-<span class="nb">print</span><span class="p">(</span><span class="n">evaluate_dynamic_shape</span><span class="p">(</span><span class="n">dyn_shape_lib</span><span class="p">,</span> <span class="n">m</span><span class="o">=</span><span class="mi">64</span><span class="p">,</span> <span class="n">n</span><span class="o">=</span><span class="mi">64</span><span class="p">,</span> <a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.IterVar" title="tvm.tirx.IterVar" class="sphx-gl [...]
+<span class="nb">print</span><span class="p">(</span><span class="n">evaluate_dynamic_shape</span><span class="p">(</span><span class="n">dyn_shape_lib</span><span class="p">,</span> <span class="n">m</span><span class="o">=</span><span class="mi">4</span><span class="p">,</span> <span class="n">n</span><span class="o">=</span><span class="mi">4</span><span class="p">,</span> <a href="../../../tirx/api/tirx.html#tvm.tirx.IterVar" title="tvm.tirx.IterVar" class="sphx-glr-backref-module-tv [...]
+<span class="nb">print</span><span class="p">(</span><span class="n">evaluate_dynamic_shape</span><span class="p">(</span><span class="n">dyn_shape_lib</span><span class="p">,</span> <span class="n">m</span><span class="o">=</span><span class="mi">64</span><span class="p">,</span> <span class="n">n</span><span class="o">=</span><span class="mi">64</span><span class="p">,</span> <a href="../../../tirx/api/tirx.html#tvm.tirx.IterVar" title="tvm.tirx.IterVar" class="sphx-glr-backref-module- [...]
</pre></div>
</div>
<div class="sphx-glr-script-out highlight-none notranslate"><div class="highlight"><pre><span></span>[[0.8231925 0.74687773 0.61615294 1.0123911 ]
@@ -533,15 +543,15 @@ TE creation method.</p>
<a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">A</span></a> <span class="o">=</span> <a href="../../../reference/api/python/te.html#tvm.te.placeholder" title="tvm.te.placeholder" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-function"><span class="n">te</span><span class="o">.</span><span class="n">placeholder</span></a><spa [...]
<a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">B</span></a> <span class="o">=</span> <a href="../../../reference/api/python/te.html#tvm.te.placeholder" title="tvm.te.placeholder" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-function"><span class="n">te</span><span class="o">.</span><span class="n">placeholder</span></a><spa [...]
-<a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.IterVar" title="tvm.tirx.IterVar" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">k</span></a> <span class="o">=</span> <a href="../../../reference/api/python/te.html#tvm.te.reduce_axis" title="tvm.te.reduce_axis" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-function"><span class="n">te</span><span class="o">.</span><span class="n">reduce_axis [...]
-<a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">Y</span></a> <span class="o">=</span> <a href="../../../reference/api/python/te.html#tvm.te.compute" title="tvm.te.compute" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-function"><span class="n">te</span><span class="o">.</span><span class="n">compute</span></a><span class="p"> [...]
+<a href="../../../tirx/api/tirx.html#tvm.tirx.IterVar" title="tvm.tirx.IterVar" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">k</span></a> <span class="o">=</span> <a href="../../../reference/api/python/te.html#tvm.te.reduce_axis" title="tvm.te.reduce_axis" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-function"><span class="n">te</span><span class="o">.</span><span class="n">reduce_axis</span></a><span [...]
+<a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">Y</span></a> <span class="o">=</span> <a href="../../../reference/api/python/te.html#tvm.te.compute" title="tvm.te.compute" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-function"><span class="n">te</span><span class="o">.</span><span class="n">compute</span></a><span class="p"> [...]
<a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">C</span></a> <span class="o">=</span> <a href="../../../reference/api/python/te.html#tvm.te.compute" title="tvm.te.compute" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-function"><span class="n">te</span><span class="o">.</span><span class="n">compute</span></a><span class="p"> [...]
</pre></div>
</div>
<p>Here <code class="docutils literal notranslate"><span class="pre">te.compute</span></code> takes the signature <code class="docutils literal notranslate"><span class="pre">te.compute(output_shape,</span> <span class="pre">fcompute)</span></code>.
And the fcompute function describes how we want to compute the value of each
element <code class="docutils literal notranslate"><span class="pre">Y[i,</span> <span class="pre">j]</span></code> for a given index:</p>
-<div class="highlight-python notranslate"><div class="highlight"><pre><span></span><span class="k">lambda</span> <span class="n">i</span><span class="p">,</span> <span class="n">j</span><span class="p">:</span> <a href="../../../reference/api/python/te.html#tvm.te.sum" title="tvm.te.sum" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-function"><span class="n">te</span><span class="o">.</span><span class="n">sum</span></a><span class="p">(</span><a href="../../../reference [...]
+<div class="highlight-python notranslate"><div class="highlight"><pre><span></span><span class="k">lambda</span> <span class="n">i</span><span class="p">,</span> <span class="n">j</span><span class="p">:</span> <a href="../../../reference/api/python/te.html#tvm.te.sum" title="tvm.te.sum" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-function"><span class="n">te</span><span class="o">.</span><span class="n">sum</span></a><span class="p">(</span><a href="../../../reference [...]
</pre></div>
</div>
<p>The aforementioned lambda expression encapsulates the computation:
@@ -549,8 +559,8 @@ element <code class="docutils literal notranslate"><span class="pre">Y[i,</span>
we can formulate a TensorIR function by incorporating the pertinent parameters of interest.
In this specific instance, we aim to construct a function with two input parameters <strong>A, B</strong>
and one output parameter <strong>C</strong>.</p>
-<div class="highlight-Python notranslate"><div class="highlight"><pre><span></span><a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">te_func</span></a> <span class="o">=</span> <a href="../../../reference/api/python/te.html#tvm.te.create_prim_func" title="tvm.te.create_prim_func" class="sphx-glr-backref-module-tvm-te sphx-glr-b [...]
-<span class="n">TEModule</span> <span class="o">=</span> <a href="../../../reference/api/python/ir.html#tvm.ir.Node" title="tvm.ir.Node" class="sphx-glr-backref-module-tvm-ir sphx-glr-backref-type-py-class"><span class="n">tvm</span><span class="o">.</span><span class="n">IRModule</span></a><span class="p">({</span><span class="s2">"mm_relu"</span><span class="p">:</span> <a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="s [...]
+<div class="highlight-Python notranslate"><div class="highlight"><pre><span></span><a href="../../../tirx/api/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">te_func</span></a> <span class="o">=</span> <a href="../../../reference/api/python/te.html#tvm.te.create_prim_func" title="tvm.te.create_prim_func" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-fu [...]
+<span class="n">TEModule</span> <span class="o">=</span> <a href="../../../reference/api/python/ir.html#tvm.ir.Node" title="tvm.ir.Node" class="sphx-glr-backref-module-tvm-ir sphx-glr-backref-type-py-class"><span class="n">tvm</span><span class="o">.</span><span class="n">IRModule</span></a><span class="p">({</span><span class="s2">"mm_relu"</span><span class="p">:</span> <a href="../../../tirx/api/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref-m [...]
<span class="n">TEModule</span><span class="o">.</span><span class="n">show</span><span class="p">()</span>
</pre></div>
</div>
@@ -587,15 +597,15 @@ class Module:
<p>We can also create a dynamic-shape function using Tensor Expression. The only difference
is that we need to specify the shape of the input tensors as symbolic variables.</p>
<div class="highlight-Python notranslate"><div class="highlight"><pre><span></span><span class="c1"># Declare symbolic variables</span>
-<a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">M</span></a><span class="p">,</span> <a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">N</span></a><span class="p">,</span> <a href="../ [...]
-<a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">A</span></a> <span class="o">=</span> <a href="../../../reference/api/python/te.html#tvm.te.placeholder" title="tvm.te.placeholder" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-function"><span class="n">te</span><span class="o">.</span><span class="n">placeholder</span></a><spa [...]
-<a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">B</span></a> <span class="o">=</span> <a href="../../../reference/api/python/te.html#tvm.te.placeholder" title="tvm.te.placeholder" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-function"><span class="n">te</span><span class="o">.</span><span class="n">placeholder</span></a><spa [...]
-<a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.IterVar" title="tvm.tirx.IterVar" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">k</span></a> <span class="o">=</span> <a href="../../../reference/api/python/te.html#tvm.te.reduce_axis" title="tvm.te.reduce_axis" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-function"><span class="n">te</span><span class="o">.</span><span class="n">reduce_axis [...]
-<a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">Y</span></a> <span class="o">=</span> <a href="../../../reference/api/python/te.html#tvm.te.compute" title="tvm.te.compute" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-function"><span class="n">te</span><span class="o">.</span><span class="n">compute</span></a><span class="p"> [...]
-<a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">C</span></a> <span class="o">=</span> <a href="../../../reference/api/python/te.html#tvm.te.compute" title="tvm.te.compute" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-function"><span class="n">te</span><span class="o">.</span><span class="n">compute</span></a><span class="p"> [...]
-
-<a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">dyn_te_func</span></a> <span class="o">=</span> <a href="../../../reference/api/python/te.html#tvm.te.create_prim_func" title="tvm.te.create_prim_func" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-function"><span class="n">te</span><span class="o">.</span><span [...]
-<span class="n">DynamicTEModule</span> <span class="o">=</span> <a href="../../../reference/api/python/ir.html#tvm.ir.Node" title="tvm.ir.Node" class="sphx-glr-backref-module-tvm-ir sphx-glr-backref-type-py-class"><span class="n">tvm</span><span class="o">.</span><span class="n">IRModule</span></a><span class="p">({</span><span class="s2">"mm_relu"</span><span class="p">:</span> <a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" c [...]
+<a href="../../../tirx/api/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">M</span></a><span class="p">,</span> <a href="../../../tirx/api/tirx.html#tvm.tirx.Var" title="tvm.tirx.Var" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">N</span></a><span class="p">,</span> <a href="../../../tirx/api/tirx.html#tvm.tirx. [...]
+<a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">A</span></a> <span class="o">=</span> <a href="../../../reference/api/python/te.html#tvm.te.placeholder" title="tvm.te.placeholder" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-function"><span class="n">te</span><span class="o">.</span><span class="n">placeholder</span></a><spa [...]
+<a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">B</span></a> <span class="o">=</span> <a href="../../../reference/api/python/te.html#tvm.te.placeholder" title="tvm.te.placeholder" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-function"><span class="n">te</span><span class="o">.</span><span class="n">placeholder</span></a><spa [...]
+<a href="../../../tirx/api/tirx.html#tvm.tirx.IterVar" title="tvm.tirx.IterVar" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">k</span></a> <span class="o">=</span> <a href="../../../reference/api/python/te.html#tvm.te.reduce_axis" title="tvm.te.reduce_axis" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-function"><span class="n">te</span><span class="o">.</span><span class="n">reduce_axis</span></a><span [...]
+<a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">Y</span></a> <span class="o">=</span> <a href="../../../reference/api/python/te.html#tvm.te.compute" title="tvm.te.compute" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-function"><span class="n">te</span><span class="o">.</span><span class="n">compute</span></a><span class="p"> [...]
+<a href="../../../reference/api/python/te.html#tvm.te.Tensor" title="tvm.te.Tensor" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">C</span></a> <span class="o">=</span> <a href="../../../reference/api/python/te.html#tvm.te.compute" title="tvm.te.compute" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-function"><span class="n">te</span><span class="o">.</span><span class="n">compute</span></a><span class="p"> [...]
+
+<a href="../../../tirx/api/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-class sphx-glr-backref-instance"><span class="n">dyn_te_func</span></a> <span class="o">=</span> <a href="../../../reference/api/python/te.html#tvm.te.create_prim_func" title="tvm.te.create_prim_func" class="sphx-glr-backref-module-tvm-te sphx-glr-backref-type-py-function"><span class="n">te</span><span class="o">.</span><span class="n">create [...]
+<span class="n">DynamicTEModule</span> <span class="o">=</span> <a href="../../../reference/api/python/ir.html#tvm.ir.Node" title="tvm.ir.Node" class="sphx-glr-backref-module-tvm-ir sphx-glr-backref-type-py-class"><span class="n">tvm</span><span class="o">.</span><span class="n">IRModule</span></a><span class="p">({</span><span class="s2">"mm_relu"</span><span class="p">:</span> <a href="../../../tirx/api/tirx.html#tvm.tirx.PrimFunc" title="tvm.tirx.PrimFunc" class="sphx-glr-ba [...]
<span class="n">DynamicTEModule</span><span class="o">.</span><span class="n">show</span><span class="p">()</span>
</pre></div>
</div>
diff --git a/docs/deep_dive/tensor_ir/tutorials/tir_transformation.html b/docs/deep_dive/tensor_ir/tutorials/tir_transformation.html
index dd065445047..6a40ed44628 100644
--- a/docs/deep_dive/tensor_ir/tutorials/tir_transformation.html
+++ b/docs/deep_dive/tensor_ir/tutorials/tir_transformation.html
@@ -200,6 +200,16 @@
<li class="toctree-l1"><a class="reference internal" href="../index.html">TensorIR</a></li>
<li class="toctree-l1"><a class="reference internal" href="../../relax/index.html">Relax</a></li>
</ul>
+<p class="caption" role="heading"><span class="caption-text">TIRx</span></p>
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/overview.html">Overview</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/install.html">Installation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/native_basics.html">TIRx Basics: CUDA C++/PTX native level</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/layout.html">Tensor Layout</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/tile_primitives.html">Tile Primitives</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/arch/index.html">Compiler Internals</a></li>
+<li class="toctree-l1"><a class="reference internal" href="../../../tirx/api/index.html">API Reference</a></li>
+</ul>
<p class="caption" role="heading"><span class="caption-text">API Reference</span></p>
<ul>
<li class="toctree-l1"><a class="reference internal" href="../../../reference/api/python/index.html">Python API</a></li>
@@ -360,7 +370,7 @@ original implementation.</p>
<span class="k">def</span><span class="w"> </span><span class="nf">evaluate</span><span class="p">(</span><span class="n">mod</span><span class="p">:</span> <a href="../../../reference/api/python/ir.html#tvm.ir.Node" title="tvm.ir.Node" class="sphx-glr-backref-module-tvm-ir sphx-glr-backref-type-py-class"><span class="n">tvm</span><span class="o">.</span><span class="n">IRModule</span></a><span class="p">):</span>
- <span class="n">lib</span> <span class="o">=</span> <a href="../../../reference/api/python/tirx/tirx.html#tvm.tirx.build" title="tvm.tirx.build" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-function"><span class="n">tvm</span><span class="o">.</span><span class="n">tirx</span><span class="o">.</span><span class="n">build</span></a><span class="p">(</span><span class="n">mod</span><span class="p">,</span> <span class="n">target</span><span class="o">=</span><span c [...]
+ <span class="n">lib</span> <span class="o">=</span> <a href="../../../tirx/api/tirx.html#tvm.tirx.build" title="tvm.tirx.build" class="sphx-glr-backref-module-tvm-tirx sphx-glr-backref-type-py-function"><span class="n">tvm</span><span class="o">.</span><span class="n">tirx</span><span class="o">.</span><span class="n">build</span></a><span class="p">(</span><span class="n">mod</span><span class="p">,</span> <span class="n">target</span><span class="o">=</span><span class="s2">"l [...]
<span class="c1"># check correctness</span>
<span class="n">lib</span><span class="p">(</span><span class="n">a_nd</span><span class="p">,</span> <span class="n">b_nd</span><span class="p">,</span> <span class="n">c_nd</span><span class="p">)</span>
<span class="n">np</span><span class="o">.</span><span class="n">testing</span><span class="o">.</span><span class="n">assert_allclose</span><span class="p">(</span><span class="n">c_nd</span><span class="o">.</span><span class="n">numpy</span><span class="p">(),</span> <span class="n">c_np</span><span class="p">,</span> <span class="n">rtol</span><span class="o">=</span><span class="mf">1e-5</span><span class="p">)</span>
@@ -374,7 +384,7 @@ original implementation.</p>
</div>
<div class="sphx-glr-script-out highlight-none notranslate"><div class="highlight"><pre><span></span>Execution time summary:
mean (ms) median (ms) max (ms) min (ms) std (ms)
- 2.8418 2.8418 2.8418 2.8418 0.0000
+ 2.7688 2.7688 2.7688 2.7688 0.0000
</pre></div>
</div>
<section id="initialization-schedule">
@@ -472,7 +482,7 @@ class Module:
Execution time summary:
mean (ms) median (ms) max (ms) min (ms) std (ms)
- 0.8630 0.8630 0.8630 0.8630 0.0000
+ 0.8701 0.8701 0.8701 0.8701 0.0000
</pre></div>
</div>
</section>
@@ -568,7 +578,7 @@ class Module:
Execution time summary:
mean (ms) median (ms) max (ms) min (ms) std (ms)
- 0.3552 0.3552 0.3552 0.3552 0.0000
+ 0.3396 0.3396 0.3396 0.3396 0.0000
</pre></div>
</div>
</section>
diff --git a/docs/errors.html b/docs/errors.html
index 3bcdb97c805..3412c872ff6 100644
--- a/docs/errors.html
+++ b/docs/errors.html
@@ -205,6 +205,16 @@
<li class="toctree-l1"><a class="reference internal" href="deep_dive/tensor_ir/index.html">TensorIR</a></li>
<li class="toctree-l1"><a class="reference internal" href="deep_dive/relax/index.html">Relax</a></li>
</ul>
+<p class="caption" role="heading"><span class="caption-text">TIRx</span></p>
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="tirx/overview.html">Overview</a></li>
+<li class="toctree-l1"><a class="reference internal" href="tirx/install.html">Installation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="tirx/native_basics.html">TIRx Basics: CUDA C++/PTX native level</a></li>
+<li class="toctree-l1"><a class="reference internal" href="tirx/layout.html">Tensor Layout</a></li>
+<li class="toctree-l1"><a class="reference internal" href="tirx/tile_primitives.html">Tile Primitives</a></li>
+<li class="toctree-l1"><a class="reference internal" href="tirx/arch/index.html">Compiler Internals</a></li>
+<li class="toctree-l1"><a class="reference internal" href="tirx/api/index.html">API Reference</a></li>
+</ul>
<p class="caption" role="heading"><span class="caption-text">API Reference</span></p>
<ul>
<li class="toctree-l1"><a class="reference internal" href="reference/api/python/index.html">Python API</a></li>
diff --git a/docs/genindex.html b/docs/genindex.html
index ea821e06fa9..18c7501d81a 100644
--- a/docs/genindex.html
+++ b/docs/genindex.html
@@ -197,6 +197,16 @@
<li class="toctree-l1"><a class="reference internal" href="deep_dive/tensor_ir/index.html">TensorIR</a></li>
<li class="toctree-l1"><a class="reference internal" href="deep_dive/relax/index.html">Relax</a></li>
</ul>
+<p class="caption" role="heading"><span class="caption-text">TIRx</span></p>
+<ul>
+<li class="toctree-l1"><a class="reference internal" href="tirx/overview.html">Overview</a></li>
+<li class="toctree-l1"><a class="reference internal" href="tirx/install.html">Installation</a></li>
+<li class="toctree-l1"><a class="reference internal" href="tirx/native_basics.html">TIRx Basics: CUDA C++/PTX native level</a></li>
+<li class="toctree-l1"><a class="reference internal" href="tirx/layout.html">Tensor Layout</a></li>
+<li class="toctree-l1"><a class="reference internal" href="tirx/tile_primitives.html">Tile Primitives</a></li>
+<li class="toctree-l1"><a class="reference internal" href="tirx/arch/index.html">Compiler Internals</a></li>
+<li class="toctree-l1"><a class="reference internal" href="tirx/api/index.html">API Reference</a></li>
+</ul>
<p class="caption" role="heading"><span class="caption-text">API Reference</span></p>
<ul>
<li class="toctree-l1"><a class="reference internal" href="reference/api/python/index.html">Python API</a></li>
@@ -328,12 +338,12 @@
<ul>
<li><a href="reference/api/python/te.html#tvm.te.abs">(in module tvm.te)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.abs">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.abs">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/testing.html#tvm.testing.Path.absolute">absolute() (tvm.testing.Path method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Buffer.access_ptr">access_ptr() (tvm.tirx.Buffer method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Buffer.access_ptr">access_ptr() (tvm.tirx.Buffer method)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.IndexPutAttrs.accumulate">accumulate (tvm.relax.op.op_attrs.IndexPutAttrs property)</a>
</li>
@@ -342,7 +352,7 @@
<ul>
<li><a href="reference/api/python/te.html#tvm.te.acos">(in module tvm.te)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.acos">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.acos">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.acosh">acosh() (in module tvm.relax.op)</a>
@@ -350,7 +360,7 @@
<ul>
<li><a href="reference/api/python/te.html#tvm.te.acosh">(in module tvm.te)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.acosh">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.acosh">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.nn.adaptive_avg_pool1d">adaptive_avg_pool1d() (in module tvm.relax.op.nn)</a>
@@ -375,14 +385,14 @@
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.AdaptivePool3DAttrs">AdaptivePool3DAttrs (class in tvm.relax.op.op_attrs)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Add">Add (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Add">Add (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.add">add() (in module tvm.relax.op)</a>
<ul>
<li><a href="reference/api/python/te.html#tvm.te.add">(in module tvm.te)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.add">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.add">(in module tvm.tirx)</a>
</li>
<li><a href="reference/api/python/topi.html#tvm.topi.nn.add">(in module tvm.topi.nn)</a>
</li>
@@ -397,7 +407,7 @@
</li>
<li><a href="reference/api/python/s_tir/schedule.html#tvm.s_tir.schedule.Schedule.add_unit_loop">add_unit_loop() (tvm.s_tir.schedule.Schedule method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.address_of">address_of() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.address_of">address_of() (in module tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/transform.html#tvm.relax.transform.AdjustMatmulOrder">AdjustMatmulOrder() (in module tvm.relax.transform)</a>
</li>
@@ -411,16 +421,16 @@
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.ROIAlignAttrs.aligned">aligned (tvm.relax.op.op_attrs.ROIAlignAttrs property)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.HoistedConditionals.All">All (tvm.tirx.transform.HoistedConditionals attribute)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.HoistedConditionals.All">All (tvm.tirx.transform.HoistedConditionals attribute)</a>
<ul>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.HoistedLetBindings.All">(tvm.tirx.transform.HoistedLetBindings attribute)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.HoistedLetBindings.All">(tvm.tirx.transform.HoistedLetBindings attribute)</a>
</li>
</ul></li>
<li><a href="reference/api/python/te.html#tvm.te.all">all() (in module tvm.te)</a>
<ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.all">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.all">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.all_class_non_max_suppression">all_class_non_max_suppression() (in module tvm.relax.op)</a>
@@ -461,7 +471,7 @@
</li>
<li><a href="reference/api/python/relax/transform.html#tvm.relax.transform.AllocateWorkspace">AllocateWorkspace() (in module tvm.relax.transform)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.AllocBuffer">AllocBuffer (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.AllocBuffer">AllocBuffer (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.ccl.allreduce">allreduce() (in module tvm.relax.op.ccl)</a>
@@ -477,7 +487,7 @@
</li>
<li><a href="reference/api/python/arith.html#tvm.arith.Analyzer">Analyzer (class in tvm.arith)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.And">And (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.And">And (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/s_tir/schedule.html#tvm.s_tir.schedule.Schedule.annotate">annotate() (tvm.s_tir.schedule.Schedule method)</a>
</li>
@@ -485,14 +495,14 @@
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.distributed.annotate_sharding">annotate_sharding() (in module tvm.relax.op.distributed)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.AnnotateEntryFunc">AnnotateEntryFunc() (in module tvm.tirx.transform)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.AnnotateEntryFunc">AnnotateEntryFunc() (in module tvm.tirx.transform)</a>
</li>
<li><a href="reference/api/python/relax/transform.html#tvm.relax.transform.AnnotateTIROpPattern">AnnotateTIROpPattern() (in module tvm.relax.transform)</a>
</li>
<li><a href="reference/api/python/te.html#tvm.te.any">any() (in module tvm.te)</a>
<ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.any">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.any">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/s_tir/schedule.html#tvm.s_tir.schedule.Trace.append">append() (tvm.s_tir.schedule.Trace method)</a>
@@ -501,7 +511,7 @@
</li>
<li><a href="reference/api/python/relax/training.html#tvm.relax.training.AppendLoss">AppendLoss() (in module tvm.relax.training)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.Apply">Apply() (in module tvm.tirx.transform)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.Apply">Apply() (in module tvm.tirx.transform)</a>
</li>
<li><a href="reference/api/python/s_tir/dlight.html#tvm.s_tir.dlight.ScheduleRule.apply">apply() (tvm.s_tir.dlight.ScheduleRule method)</a>
@@ -514,12 +524,12 @@
</li>
<li><a href="reference/api/python/meta_schedule.html#tvm.s_tir.meta_schedule.ScheduleRule.apply">(tvm.s_tir.meta_schedule.ScheduleRule method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Layout.apply">(tvm.tirx.Layout method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Layout.apply">(tvm.tirx.Layout method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Predicate.apply">(tvm.tirx.Predicate method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Predicate.apply">(tvm.tirx.Predicate method)</a>
</li>
</ul></li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.StmtSimplifyConfig.apply_constraints_to_boolean_branches">apply_constraints_to_boolean_branches (tvm.tirx.transform.StmtSimplifyConfig property)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.StmtSimplifyConfig.apply_constraints_to_boolean_branches">apply_constraints_to_boolean_branches (tvm.tirx.transform.StmtSimplifyConfig property)</a>
</li>
<li><a href="reference/api/python/s_tir/schedule.html#tvm.s_tir.schedule.Trace.apply_json_to_schedule">apply_json_to_schedule() (tvm.s_tir.schedule.Trace static method)</a>
</li>
@@ -527,7 +537,7 @@
</li>
</ul></td>
<td style="width: 33%; vertical-align: top;"><ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Layout.apply_to_shape">apply_to_shape() (tvm.tirx.Layout method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Layout.apply_to_shape">apply_to_shape() (tvm.tirx.Layout method)</a>
</li>
<li><a href="reference/api/python/s_tir/dlight.html#tvm.s_tir.dlight.ApplyDefaultSchedule">ApplyDefaultSchedule (class in tvm.s_tir.dlight)</a>
</li>
@@ -560,7 +570,7 @@
<ul>
<li><a href="reference/api/python/te.html#tvm.te.asin">(in module tvm.te)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.asin">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.asin">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.asinh">asinh() (in module tvm.relax.op)</a>
@@ -568,7 +578,7 @@
<ul>
<li><a href="reference/api/python/te.html#tvm.te.asinh">(in module tvm.te)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.asinh">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.asinh">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/te.html#tvm.te.TensorSlice.asobject">asobject() (tvm.te.TensorSlice method)</a>
@@ -583,9 +593,9 @@
</li>
<li><a href="reference/api/python/ir.html#tvm.ir.assert_structural_equal">assert_structural_equal() (in module tvm.ir)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.AssertStmt">AssertStmt (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.AssertStmt">AssertStmt (class in tvm.tirx)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.assume">assume() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.assume">assume() (in module tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.StridedSliceAttrs.assume_inbound">assume_inbound (tvm.relax.op.op_attrs.StridedSliceAttrs property)</a>
</li>
@@ -598,13 +608,13 @@
<ul>
<li><a href="reference/api/python/te.html#tvm.te.atan">(in module tvm.te)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.atan">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.atan">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.atan2">atan2() (in module tvm.relax.op)</a>
<ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.atan2">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.atan2">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.atanh">atanh() (in module tvm.relax.op)</a>
@@ -612,7 +622,7 @@
<ul>
<li><a href="reference/api/python/te.html#tvm.te.atanh">(in module tvm.te)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.atanh">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.atanh">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/transform.html#tvm.relax.transform.AttachAttrLayoutFreeBuffers">AttachAttrLayoutFreeBuffers() (in module tvm.relax.transform)</a>
@@ -639,13 +649,13 @@
<li><a href="reference/api/python/s_tir/schedule.html#tvm.s_tir.schedule.Instruction.attrs">(tvm.s_tir.schedule.Instruction attribute)</a>
</li>
</ul></li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.AttrStmt">AttrStmt (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.AttrStmt">AttrStmt (class in tvm.tirx)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.UnrollLoopConfig.auto_max_depth">auto_max_depth (tvm.tirx.transform.UnrollLoopConfig property)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.UnrollLoopConfig.auto_max_depth">auto_max_depth (tvm.tirx.transform.UnrollLoopConfig property)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.UnrollLoopConfig.auto_max_extent">auto_max_extent (tvm.tirx.transform.UnrollLoopConfig property)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.UnrollLoopConfig.auto_max_extent">auto_max_extent (tvm.tirx.transform.UnrollLoopConfig property)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.UnrollLoopConfig.auto_max_step">auto_max_step (tvm.tirx.transform.UnrollLoopConfig property)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.UnrollLoopConfig.auto_max_step">auto_max_step (tvm.tirx.transform.UnrollLoopConfig property)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.nn.avg_pool1d">avg_pool1d() (in module tvm.relax.op.nn)</a>
</li>
@@ -767,18 +777,18 @@
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.SoftplusAttrs.beta">beta (tvm.relax.op.op_attrs.SoftplusAttrs property)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.BF16ComputeLegalize">BF16ComputeLegalize() (in module tvm.tirx.transform)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.BF16ComputeLegalize">BF16ComputeLegalize() (in module tvm.tirx.transform)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.BF16StorageLegalize">BF16StorageLegalize() (in module tvm.tirx.transform)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.BF16StorageLegalize">BF16StorageLegalize() (in module tvm.tirx.transform)</a>
</li>
<li><a href="reference/api/python/topi.html#tvm.topi.nn.binarize_pack">binarize_pack() (in module tvm.topi.nn)</a>
</li>
<li><a href="reference/api/python/topi.html#tvm.topi.nn.binary_dense">binary_dense() (in module tvm.topi.nn)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Bind">Bind (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Bind">Bind (class in tvm.tirx)</a>
<ul>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.HoistedLetBindings.Bind">(tvm.tirx.transform.HoistedLetBindings attribute)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.HoistedLetBindings.Bind">(tvm.tirx.transform.HoistedLetBindings attribute)</a>
</li>
</ul></li>
<li><a href="reference/api/python/arith.html#tvm.arith.Analyzer.bind">bind() (tvm.arith.Analyzer method)</a>
@@ -799,7 +809,7 @@
</li>
<li><a href="reference/api/python/relax/transform.html#tvm.relax.transform.BindSymbolicVars">BindSymbolicVars() (in module tvm.relax.transform)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.BindTarget">BindTarget() (in module tvm.tirx.transform)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.BindTarget">BindTarget() (in module tvm.tirx.transform)</a>
</li>
</ul></td>
<td style="width: 33%; vertical-align: top;"><ul>
@@ -811,46 +821,48 @@
</li>
<li><a href="reference/api/python/topi.html#tvm.topi.nn.bitserial_dense">bitserial_dense() (in module tvm.topi.nn)</a>
</li>
- <li><a href="reference/api/python/relax/op.html#tvm.relax.op.bitwise_and">bitwise_and() (in module tvm.relax.op)</a>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.bitwise_and">bitwise_and() (in module tvm.backend.cuda.op)</a>
<ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.bitwise_and">(in module tvm.tirx)</a>
+ <li><a href="reference/api/python/relax/op.html#tvm.relax.op.bitwise_and">(in module tvm.relax.op)</a>
+</li>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.bitwise_and">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.bitwise_not">bitwise_not() (in module tvm.relax.op)</a>
<ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.bitwise_not">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.bitwise_not">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.bitwise_or">bitwise_or() (in module tvm.relax.op)</a>
<ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.bitwise_or">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.bitwise_or">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.bitwise_xor">bitwise_xor() (in module tvm.relax.op)</a>
<ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.bitwise_xor">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.bitwise_xor">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/block_builder.html#tvm.relax.block_builder.BlockBuilder">BlockBuilder (class in tvm.relax.block_builder)</a>
</li>
<li><a href="reference/api/python/s_tir/schedule.html#tvm.s_tir.schedule.Schedule.blockize">blockize() (tvm.s_tir.schedule.Schedule method)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.HoistedConditionals.BooleanExpression">BooleanExpression (tvm.tirx.transform.HoistedConditionals attribute)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.HoistedConditionals.BooleanExpression">BooleanExpression (tvm.tirx.transform.HoistedConditionals attribute)</a>
</li>
<li><a href="reference/api/python/relax/analysis.html#tvm.relax.analysis.bound_vars">bound_vars() (in module tvm.relax.analysis)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.break_loop">break_loop() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.break_loop">break_loop() (in module tvm.tirx)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Broadcast">Broadcast (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Broadcast">Broadcast (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/runtime/disco.html#tvm.runtime.disco.Session.broadcast">broadcast() (tvm.runtime.disco.Session method)</a>
<ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Layout.broadcast">(tvm.tirx.Layout method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Layout.broadcast">(tvm.tirx.Layout method)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.ccl.broadcast_from_worker0">broadcast_from_worker0() (in module tvm.relax.op.ccl)</a>
@@ -863,18 +875,18 @@
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.bucketize">bucketize() (in module tvm.relax.op)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Buffer">Buffer (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Buffer">Buffer (class in tvm.tirx)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.BufferLoad">BufferLoad (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.BufferLoad">BufferLoad (class in tvm.tirx)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.BufferRegion">BufferRegion (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.BufferRegion">BufferRegion (class in tvm.tirx)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.BufferStore">BufferStore (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.BufferStore">BufferStore (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/relax.html#tvm.relax.build">build() (in module tvm.relax)</a>
<ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.build">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.build">(in module tvm.tirx)</a>
</li>
<li><a href="reference/api/python/meta_schedule.html#tvm.s_tir.meta_schedule.Builder.build">(tvm.s_tir.meta_schedule.Builder method)</a>
</li>
@@ -883,9 +895,9 @@
</li>
<li><a href="reference/api/python/relax/transform.html#tvm.relax.transform.BundleModelParams">BundleModelParams() (in module tvm.relax.transform)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Buffer.byte_offset">byte_offset (tvm.tirx.Buffer property)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Buffer.byte_offset">byte_offset (tvm.tirx.Buffer property)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Buffer.byte_offset_of">byte_offset_of() (tvm.tirx.Buffer method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Buffer.byte_offset_of">byte_offset_of() (tvm.tirx.Buffer method)</a>
</li>
</ul></td>
</tr></table>
@@ -910,16 +922,12 @@
<li><a href="reference/api/python/s_tir/analysis.html#tvm.s_tir.analysis.calculate_allocated_bytes">calculate_allocated_bytes() (in module tvm.s_tir.analysis)</a>
</li>
<li><a href="reference/api/python/relax/relax.html#tvm.relax.Call">Call (class in tvm.relax)</a>
-
- <ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Call">(class in tvm.tirx)</a>
</li>
- </ul></li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.call_builtin_with_ctx">call_builtin_with_ctx() (in module tvm.relax.op)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.call_cpacked">call_cpacked() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.call_cpacked">call_cpacked() (in module tvm.tirx)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.call_cpacked_lowered">call_cpacked_lowered() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.call_cpacked_lowered">call_cpacked_lowered() (in module tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/relax.html#tvm.relax.call_dps_packed">call_dps_packed() (in module tvm.relax)</a>
@@ -929,25 +937,29 @@
<li><a href="reference/api/python/relax/relax.html#tvm.relax.BasePyModule.call_dps_packed">(tvm.relax.BasePyModule method)</a>
</li>
</ul></li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.call_extern">call_extern() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.call_extern">call_extern() (in module tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.call_inplace_packed">call_inplace_packed() (in module tvm.relax.op)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.call_intrin">call_intrin() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.call_intrin">call_intrin() (in module tvm.backend.cuda.op)</a>
+
+ <ul>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.call_intrin">(in module tvm.tirx)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.call_llvm_intrin">call_llvm_intrin() (in module tvm.tirx)</a>
+ </ul></li>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.call_llvm_intrin">call_llvm_intrin() (in module tvm.tirx)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.call_llvm_pure_intrin">call_llvm_pure_intrin() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.call_llvm_pure_intrin">call_llvm_pure_intrin() (in module tvm.tirx)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.call_packed">call_packed() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.call_packed">call_packed() (in module tvm.tirx)</a>
<ul>
<li><a href="reference/api/python/runtime/disco.html#tvm.runtime.disco.Session.call_packed">(tvm.runtime.disco.Session method)</a>
</li>
</ul></li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.call_packed_lowered">call_packed_lowered() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.call_packed_lowered">call_packed_lowered() (in module tvm.tirx)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.call_pure_extern">call_pure_extern() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.call_pure_extern">call_pure_extern() (in module tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/relax.html#tvm.relax.call_pure_packed">call_pure_packed() (in module tvm.relax)</a>
@@ -970,7 +982,7 @@
<ul>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.call_tir">(in module tvm.relax.op)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.call_tir">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.call_tir">(in module tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/relax.html#tvm.relax.BasePyModule.call_tir">(tvm.relax.BasePyModule method)</a>
</li>
@@ -991,7 +1003,7 @@
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.call_tir_with_grad">(in module tvm.relax.op)</a>
</li>
</ul></li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.CallEffectKind">CallEffectKind (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.CallEffectKind">CallEffectKind (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/ir.html#tvm.ir.CallingConv">CallingConv (class in tvm.ir)</a>
</li>
@@ -1013,11 +1025,11 @@
</li>
<li><a href="reference/api/python/arith.html#tvm.arith.Analyzer.canonical_simplify">canonical_simplify() (tvm.arith.Analyzer method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Layout.canonicalize">canonicalize() (tvm.tirx.Layout method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Layout.canonicalize">canonicalize() (tvm.tirx.Layout method)</a>
</li>
<li><a href="reference/api/python/relax/transform.html#tvm.relax.transform.CanonicalizeBindings">CanonicalizeBindings() (in module tvm.relax.transform)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Cast">Cast (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Cast">Cast (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.AttentionAttrs.causal_mask">causal_mask (tvm.relax.op.op_attrs.AttentionAttrs property)</a>
</li>
@@ -1026,7 +1038,7 @@
<ul>
<li><a href="reference/api/python/te.html#tvm.te.ceil">(in module tvm.te)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.ceil">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.ceil">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.Pool1DAttrs.ceil_mode">ceil_mode (tvm.relax.op.op_attrs.Pool1DAttrs property)</a>
@@ -1037,7 +1049,7 @@
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.Pool3DAttrs.ceil_mode">(tvm.relax.op.op_attrs.Pool3DAttrs property)</a>
</li>
</ul></li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.ceildiv">ceildiv() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.ceildiv">ceildiv() (in module tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.BatchNormAttrs.center">center (tvm.relax.op.op_attrs.BatchNormAttrs property)</a>
@@ -1095,7 +1107,7 @@
<li><a href="reference/api/python/rpc.html#tvm.rpc.TrackerSession.close">(tvm.rpc.TrackerSession method)</a>
</li>
</ul></li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.clz">clz() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.clz">clz() (in module tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.collapse_sum_like">collapse_sum_like() (in module tvm.relax.op)</a>
</li>
@@ -1108,7 +1120,7 @@
<li><a href="reference/api/python/te.html#tvm.te.comm_reducer">comm_reducer() (in module tvm.te)</a>
<ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.comm_reducer">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.comm_reducer">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/contrib.html#tvm.contrib.tvmjs.TensorCacheShardingManager.commit">commit() (tvm.contrib.tvmjs.TensorCacheShardingManager method)</a>
@@ -1117,9 +1129,9 @@
</li>
<li><a href="reference/api/python/meta_schedule.html#tvm.s_tir.meta_schedule.Database.commit_workload">commit_workload() (tvm.s_tir.meta_schedule.Database method)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.CommonSubexprElim">CommonSubexprElim() (in module tvm.tirx.transform)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.CommonSubexprElim">CommonSubexprElim() (in module tvm.tirx.transform)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.CommReducer">CommReducer (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.CommReducer">CommReducer (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/arith.html#tvm.arith.CompareResult">CompareResult (class in tvm.arith)</a>
</li>
@@ -1131,7 +1143,7 @@
</li>
<li><a href="reference/api/python/support.html#tvm.support.xcode.compile_metal">compile_metal() (in module tvm.support.xcode)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.ComposeLayout">ComposeLayout (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.ComposeLayout">ComposeLayout (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/analysis.html#tvm.relax.analysis.computable_at_compile_time">computable_at_compile_time() (in module tvm.relax.analysis)</a>
</li>
@@ -1155,9 +1167,11 @@
</li>
<li><a href="reference/api/python/rpc.html#tvm.rpc.connect_tracker">connect_tracker() (in module tvm.rpc)</a>
</li>
- <li><a href="reference/api/python/relax/relax.html#tvm.relax.const">const() (in module tvm.relax)</a>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.const">const() (in module tvm.backend.cuda.op)</a>
<ul>
+ <li><a href="reference/api/python/relax/relax.html#tvm.relax.const">(in module tvm.relax)</a>
+</li>
<li><a href="reference/api/python/te.html#tvm.te.const">(in module tvm.te)</a>
</li>
</ul></li>
@@ -1175,12 +1189,10 @@
</li>
<li><a href="reference/api/python/relax/analysis.html#tvm.relax.analysis.contains_impure_call">contains_impure_call() (in module tvm.relax.analysis)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.continue_loop">continue_loop() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.continue_loop">continue_loop() (in module tvm.tirx)</a>
</li>
<li><a href="reference/api/python/topi.html#tvm.topi.nn.conv">conv() (in module tvm.topi.nn)</a>
</li>
- </ul></td>
- <td style="width: 33%; vertical-align: top;"><ul>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.nn.conv1d">conv1d() (in module tvm.relax.op.nn)</a>
<ul>
@@ -1225,6 +1237,8 @@
</li>
<li><a href="reference/api/python/topi.html#tvm.topi.nn.conv2d_NCHWc_OIHWo">conv2d_NCHWc_OIHWo() (in module tvm.topi.nn)</a>
</li>
+ </ul></td>
+ <td style="width: 33%; vertical-align: top;"><ul>
<li><a href="reference/api/python/topi.html#tvm.topi.nn.conv2d_nhwc">conv2d_nhwc() (in module tvm.topi.nn)</a>
</li>
<li><a href="reference/api/python/topi.html#tvm.topi.testing.conv2d_nhwc_python">conv2d_nhwc_python() (in module tvm.topi.testing)</a>
@@ -1293,7 +1307,7 @@
</li>
<li><a href="reference/api/python/contrib.html#tvm.contrib.cudnn.conv_output_shape">conv_output_shape() (in module tvm.contrib.cudnn)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.StmtSimplifyConfig.convert_boolean_to_and_of_ors">convert_boolean_to_and_of_ors (tvm.tirx.transform.StmtSimplifyConfig property)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.StmtSimplifyConfig.convert_boolean_to_and_of_ors">convert_boolean_to_and_of_ors (tvm.tirx.transform.StmtSimplifyConfig property)</a>
</li>
<li><a href="reference/api/python/contrib.html#tvm.contrib.dlpack.convert_func">convert_func() (in module tvm.contrib.dlpack)</a>
</li>
@@ -1301,7 +1315,7 @@
</li>
<li><a href="reference/api/python/relax/transform.html#tvm.relax.transform.ConvertLayout">ConvertLayout() (in module tvm.relax.transform)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.ConvertSSA">ConvertSSA() (in module tvm.tirx.transform)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.ConvertSSA">ConvertSSA() (in module tvm.tirx.transform)</a>
</li>
<li><a href="reference/api/python/relax/transform.html#tvm.relax.transform.ConvertToDataflow">ConvertToDataflow() (in module tvm.relax.transform)</a>
</li>
@@ -1325,7 +1339,7 @@
</li>
<li><a href="reference/api/python/runtime/disco.html#tvm.runtime.disco.Session.copy_to_worker_0">copy_to_worker_0() (tvm.runtime.disco.Session method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.copysign">copysign() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.copysign">copysign() (in module tvm.tirx)</a>
</li>
<li><a href="reference/api/python/contrib.html#tvm.contrib.coreml_runtime.CoreMLModule">CoreMLModule (class in tvm.contrib.coreml_runtime)</a>
</li>
@@ -1338,7 +1352,7 @@
<ul>
<li><a href="reference/api/python/te.html#tvm.te.cos">(in module tvm.te)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.cos">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.cos">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.cosh">cosh() (in module tvm.relax.op)</a>
@@ -1346,7 +1360,7 @@
<ul>
<li><a href="reference/api/python/te.html#tvm.te.cosh">(in module tvm.te)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.cosh">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.cosh">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/meta_schedule.html#tvm.s_tir.meta_schedule.CostModel">CostModel (class in tvm.s_tir.meta_schedule)</a>
@@ -1432,6 +1446,88 @@
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.Resize2DAttrs.cubic_exclude">cubic_exclude (tvm.relax.op.op_attrs.Resize2DAttrs property)</a>
</li>
<li><a href="reference/api/python/rpc.html#tvm.rpc.RPCSession.cuda">cuda() (tvm.rpc.RPCSession method)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_atomic_add">cuda_atomic_add() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_atomic_cas">cuda_atomic_cas() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_bfloat162float">cuda_bfloat162float() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_cluster_sync">cuda_cluster_sync() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_copy_128b">cuda_copy_128b() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_copy_16b">cuda_copy_16b() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_copy_32b">cuda_copy_32b() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_copy_64b">cuda_copy_64b() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_copy_8b">cuda_copy_8b() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_copy_bytes">cuda_copy_bytes() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_cta_max">cuda_cta_max() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_cta_min">cuda_cta_min() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_cta_reduce">cuda_cta_reduce() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_cta_sum">cuda_cta_sum() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_cta_sync">cuda_cta_sync() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_cvta_generic_to_shared">cuda_cvta_generic_to_shared() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_float22half2">cuda_float22half2() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_float8tohalf8">cuda_float8tohalf8() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_func_call">cuda_func_call() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_get_tmem_addr">cuda_get_tmem_addr() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_grid_sync">cuda_grid_sync() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_half2float">cuda_half2float() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_half8tofloat8">cuda_half8tofloat8() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_ldg">cuda_ldg() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_nano_sleep">cuda_nano_sleep() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_printf">cuda_printf() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_runtime_instr_desc">cuda_runtime_instr_desc() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_sm100_tma_2sm_mbarrier_addr">cuda_sm100_tma_2sm_mbarrier_addr() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_smem_addr_from_uint64">cuda_smem_addr_from_uint64() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_syncthreads_and">cuda_syncthreads_and() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_syncthreads_or">cuda_syncthreads_or() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_thread_fence">cuda_thread_fence() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_thread_rank">cuda_thread_rank() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_trap_when_assert_failed">cuda_trap_when_assert_failed() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_warp_max">cuda_warp_max() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_warp_min">cuda_warp_min() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_warp_reduce">cuda_warp_reduce() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_warp_sum">cuda_warp_sum() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_warp_sync">cuda_warp_sync() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.cuda_warpgroup_sync">cuda_warpgroup_sync() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.script.CUDANamespace">CUDANamespace (class in tvm.backend.cuda.script)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.cumprod">cumprod() (in module tvm.relax.op)</a>
</li>
@@ -1493,7 +1589,7 @@
</li>
<li><a href="reference/api/python/relax/relax.html#tvm.relax.DataflowVar">DataflowVar (class in tvm.relax)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.DataProducer">DataProducer (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.DataProducer">DataProducer (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/relax.html#tvm.relax.DataTypeImm">DataTypeImm (class in tvm.relax)</a>
</li>
@@ -1513,7 +1609,7 @@
</li>
<li><a href="reference/api/python/relax/relax.html#tvm.relax.ExecBuilder.declare_function">declare_function() (tvm.relax.ExecBuilder method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.DeclBuffer">DeclBuffer (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.DeclBuffer">DeclBuffer (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/s_tir/schedule.html#tvm.s_tir.schedule.Schedule.decompose_padding">decompose_padding() (tvm.s_tir.schedule.Schedule method)</a>
</li>
@@ -1649,7 +1745,7 @@
</li>
<li><a href="reference/api/python/topi.html#tvm.topi.nn.Workload.dilation_w">dilation_w (tvm.topi.nn.Workload attribute)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Layout.direct_sum">direct_sum() (tvm.tirx.Layout method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Layout.direct_sum">direct_sum() (tvm.tirx.Layout method)</a>
</li>
<li><a href="reference/api/python/support.html#tvm.support.utils.DirectoryCreatedPastAtExit">DirectoryCreatedPastAtExit</a>
</li>
@@ -1657,12 +1753,12 @@
</li>
<li><a href="reference/api/python/relax/backend.html#tvm.relax.backend.DispatchSortScan">DispatchSortScan (class in tvm.relax.backend)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Div">Div (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Div">Div (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/te.html#tvm.te.div">div() (in module tvm.te)</a>
<ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.div">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.div">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.divide">divide() (in module tvm.relax.op)</a>
@@ -1687,7 +1783,7 @@
</li>
<li><a href="reference/api/python/contrib.html#tvm.contrib.download.download_testdata">download_testdata() (in module tvm.contrib.download)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.dp4a">dp4a() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.dp4a">dp4a() (in module tvm.tirx)</a>
</li>
<li><a href="reference/api/python/runtime/disco.html#tvm.runtime.disco.DPackedFunc">DPackedFunc (class in tvm.runtime.disco)</a>
</li>
@@ -1743,7 +1839,7 @@
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.EinsumAttrs">EinsumAttrs (class in tvm.relax.op.op_attrs)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Buffer.elem_offset_of">elem_offset_of() (tvm.tirx.Buffer method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Buffer.elem_offset_of">elem_offset_of() (tvm.tirx.Buffer method)</a>
</li>
<li><a href="reference/api/python/relax/transform.html#tvm.relax.transform.EliminateCommonSubexpr">EliminateCommonSubexpr() (in module tvm.relax.transform)</a>
</li>
@@ -1775,7 +1871,7 @@
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.grad.end_checkpoint">end_checkpoint() (in module tvm.relax.op.grad)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.end_profile_intrinsic">end_profile_intrinsic() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.end_profile_intrinsic">end_profile_intrinsic() (in module tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/block_builder.html#tvm.relax.block_builder.BlockBuilder.end_scope">end_scope() (tvm.relax.block_builder.BlockBuilder method)</a>
</li>
@@ -1799,7 +1895,7 @@
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.RMSNormAttrs.epsilon">(tvm.relax.op.op_attrs.RMSNormAttrs property)</a>
</li>
</ul></li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.EQ">EQ (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.EQ">EQ (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.equal">equal() (in module tvm.relax.op)</a>
</li>
@@ -1812,7 +1908,7 @@
<ul>
<li><a href="reference/api/python/te.html#tvm.te.erf">(in module tvm.te)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.erf">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.erf">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/analysis.html#tvm.relax.analysis.estimate_memory_usage">estimate_memory_usage() (in module tvm.relax.analysis)</a>
@@ -1825,7 +1921,7 @@
</li>
<li><a href="reference/api/python/s_tir/analysis.html#tvm.s_tir.analysis.estimate_tir_flops">estimate_tir_flops() (in module tvm.s_tir.analysis)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Evaluate">Evaluate (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Evaluate">Evaluate (class in tvm.tirx)</a>
</li>
</ul></td>
<td style="width: 33%; vertical-align: top;"><ul>
@@ -1837,7 +1933,7 @@
</li>
<li><a href="reference/api/python/relax/relax.html#tvm.relax.ExecBuilder">ExecBuilder (class in tvm.relax)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.ExecScope">ExecScope (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.ExecScope">ExecScope (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/contrib.html#tvm.contrib.cudnn.exists">exists() (in module tvm.contrib.cudnn)</a>
@@ -1852,12 +1948,12 @@
<ul>
<li><a href="reference/api/python/te.html#tvm.te.exp">(in module tvm.te)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.exp">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.exp">(in module tvm.tirx)</a>
</li>
</ul></li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.exp10">exp10() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.exp10">exp10() (in module tvm.tirx)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.exp2">exp2() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.exp2">exp2() (in module tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.expand_dims">expand_dims() (in module tvm.relax.op)</a>
</li>
@@ -1869,7 +1965,7 @@
</li>
<li><a href="reference/api/python/testing.html#tvm.testing.Path.expanduser">expanduser() (tvm.testing.Path method)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.UnrollLoopConfig.explicit_unroll">explicit_unroll (tvm.tirx.transform.UnrollLoopConfig property)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.UnrollLoopConfig.explicit_unroll">explicit_unroll (tvm.tirx.transform.UnrollLoopConfig property)</a>
</li>
<li><a href="reference/api/python/contrib.html#tvm.contrib.hexagon.export_module">export_module() (in module tvm.contrib.hexagon)</a>
</li>
@@ -1887,12 +1983,12 @@
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.vision.Expr">(in module tvm.relax.op.vision)</a>
</li>
</ul></li>
- <li><a href="reference/api/python/tirx/analysis.html#tvm.tirx.analysis.analysis.expr_deep_equal">expr_deep_equal() (in module tvm.tirx.analysis.analysis)</a>
+ <li><a href="tirx/api/analysis.html#tvm.tirx.analysis.analysis.expr_deep_equal">expr_deep_equal() (in module tvm.tirx.analysis.analysis)</a>
</li>
<li><a href="reference/api/python/relax/relax.html#tvm.relax.ExprFunctor">ExprFunctor (class in tvm.relax)</a>
<ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.ExprFunctor">(class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.ExprFunctor">(class in tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/s_tir/schedule.html#tvm.s_tir.schedule.ExprRV">ExprRV (in module tvm.s_tir.schedule)</a>
@@ -1943,7 +2039,7 @@
</li>
<li><a href="reference/api/python/support.html#tvm.support.utils.filelock">filelock() (in module tvm.support.utils)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.Filter">Filter() (in module tvm.tirx.transform)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.Filter">Filter() (in module tvm.tirx.transform)</a>
</li>
<li><a href="reference/api/python/relax/block_builder.html#tvm.relax.block_builder.BlockBuilder.finalize">finalize() (tvm.relax.block_builder.BlockBuilder method)</a>
</li>
@@ -1973,46 +2069,46 @@
<li><a href="reference/api/python/topi.html#tvm.topi.nn.flatten">(in module tvm.topi.nn)</a>
</li>
</ul></li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.FlattenBuffer">FlattenBuffer() (in module tvm.tirx.transform)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.FlattenBuffer">FlattenBuffer() (in module tvm.tirx.transform)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.flip">flip() (in module tvm.relax.op)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.FlipAttrs">FlipAttrs (class in tvm.relax.op.op_attrs)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.FloatImm">FloatImm (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.FloatImm">FloatImm (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.floor">floor() (in module tvm.relax.op)</a>
<ul>
<li><a href="reference/api/python/te.html#tvm.te.floor">(in module tvm.te)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.floor">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.floor">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.floor_divide">floor_divide() (in module tvm.relax.op)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.floor_mod">floor_mod() (in module tvm.relax.op)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.FloorDiv">FloorDiv (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.FloorDiv">FloorDiv (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/te.html#tvm.te.floordiv">floordiv() (in module tvm.te)</a>
<ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.floordiv">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.floordiv">(in module tvm.tirx)</a>
</li>
</ul></li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.FloorMod">FloorMod (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.FloorMod">FloorMod (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/te.html#tvm.te.floormod">floormod() (in module tvm.te)</a>
<ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.floormod">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.floormod">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/te.html#tvm.te.fmod">fmod() (in module tvm.te)</a>
<ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.fmod">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.fmod">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/transform.html#tvm.relax.transform.FoldBatchnormToConv2D">FoldBatchnormToConv2D (class in tvm.relax.transform)</a>
@@ -2021,19 +2117,19 @@
</li>
</ul></td>
<td style="width: 33%; vertical-align: top;"><ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.For">For (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.For">For (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.NonMaximumSuppressionAttrs.force_suppress">force_suppress (tvm.relax.op.op_attrs.NonMaximumSuppressionAttrs property)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.ForceNarrowIndexToInt32">ForceNarrowIndexToInt32() (in module tvm.tirx.transform)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.ForceNarrowIndexToInt32">ForceNarrowIndexToInt32() (in module tvm.tirx.transform)</a>
</li>
<li><a href="reference/api/python/s_tir/schedule.html#tvm.s_tir.schedule.Schedule.fork_seed">fork_seed() (tvm.s_tir.schedule.Schedule method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.ForKind">ForKind (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.ForKind">ForKind (class in tvm.tirx)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.FP8ComputeLegalize">FP8ComputeLegalize() (in module tvm.tirx.transform)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.FP8ComputeLegalize">FP8ComputeLegalize() (in module tvm.tirx.transform)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.FP8StorageLegalize">FP8StorageLegalize() (in module tvm.tirx.transform)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.FP8StorageLegalize">FP8StorageLegalize() (in module tvm.tirx.transform)</a>
</li>
<li><a href="reference/api/python/relax/analysis.html#tvm.relax.analysis.free_symbolic_vars">free_symbolic_vars() (in module tvm.relax.analysis)</a>
</li>
@@ -2047,13 +2143,13 @@
</li>
<li><a href="reference/api/python/ir.html#tvm.ir.IRModule.from_expr">from_expr() (tvm.ir.IRModule static method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.IndexMap.from_func">from_func() (tvm.tirx.IndexMap static method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.IndexMap.from_func">from_func() (tvm.tirx.IndexMap static method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.IndexMap.from_func_with_separators">from_func_with_separators() (tvm.tirx.IndexMap static method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.IndexMap.from_func_with_separators">from_func_with_separators() (tvm.tirx.IndexMap static method)</a>
</li>
<li><a href="reference/api/python/relax/frontend.html#tvm.relax.frontend.torch.from_fx">from_fx() (in module tvm.relax.frontend.torch)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.TileLayout.from_iters">from_iters() (tvm.tirx.TileLayout static method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.TileLayout.from_iters">from_iters() (tvm.tirx.TileLayout static method)</a>
</li>
<li><a href="reference/api/python/ir.html#tvm.ir.Range.from_min_extent">from_min_extent() (tvm.ir.Range static method)</a>
</li>
@@ -2125,7 +2221,7 @@
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.GatherNDAttrs">GatherNDAttrs (class in tvm.relax.op.op_attrs)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.GE">GE (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.GE">GE (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.nn.gelu">gelu() (in module tvm.relax.op.nn)</a>
</li>
@@ -2166,7 +2262,7 @@
</li>
<li><a href="reference/api/python/script/ir_builder.html#tvm.script.ir_builder.IRBuilder.get">(tvm.script.ir_builder.IRBuilder method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.TensorIntrin.get">(tvm.tirx.TensorIntrin static method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.TensorIntrin.get">(tvm.tirx.TensorIntrin static method)</a>
</li>
</ul></li>
<li><a href="reference/api/python/topi.html#tvm.topi.image.get_1d_indices">get_1d_indices() (in module tvm.topi.image)</a>
@@ -2181,7 +2277,7 @@
</li>
<li><a href="reference/api/python/topi.html#tvm.topi.image.get_3d_pixel">get_3d_pixel() (in module tvm.topi.image)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.get_active_lane_mask">get_active_lane_mask() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.get_active_lane_mask">get_active_lane_mask() (in module tvm.tirx)</a>
</li>
<li><a href="reference/api/python/meta_schedule.html#tvm.s_tir.meta_schedule.Database.get_all_tuning_records">get_all_tuning_records() (tvm.s_tir.meta_schedule.Database method)</a>
</li>
@@ -2209,7 +2305,7 @@
</li>
<li><a href="reference/api/python/relax/relax.html#tvm.relax.get_default_pipeline">get_default_pipeline() (in module tvm.relax)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.get_default_tir_pipeline">get_default_tir_pipeline() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.get_default_tir_pipeline">get_default_tir_pipeline() (in module tvm.tirx)</a>
</li>
<li><a href="reference/api/python/s_tir/schedule.html#tvm.s_tir.schedule.SBlockScope.get_deps_by_dst">get_deps_by_dst() (tvm.s_tir.schedule.SBlockScope method)</a>
</li>
@@ -2217,7 +2313,7 @@
</li>
<li><a href="reference/api/python/contrib.html#tvm.contrib.hexagon.ContainerSession.get_env">get_env() (tvm.contrib.hexagon.ContainerSession method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Buffer.get_flattened_buffer">get_flattened_buffer() (tvm.tirx.Buffer method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Buffer.get_flattened_buffer">get_flattened_buffer() (tvm.tirx.Buffer method)</a>
</li>
<li><a href="reference/api/python/relax/relax.html#tvm.relax.BasePyModule.get_function">get_function() (tvm.relax.BasePyModule method)</a>
@@ -2277,7 +2373,7 @@
</li>
<li><a href="reference/api/python/relax/relax.html#tvm.relax.get_pipeline">get_pipeline() (in module tvm.relax)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.TilePrimitiveCall.get_private_buffers">get_private_buffers() (tvm.tirx.TilePrimitiveCall method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.TilePrimitiveCall.get_private_buffers">get_private_buffers() (tvm.tirx.TilePrimitiveCall method)</a>
</li>
<li><a href="reference/api/python/s_tir/schedule.html#tvm.s_tir.schedule.Schedule.get_producers">get_producers() (tvm.s_tir.schedule.Schedule method)</a>
</li>
@@ -2289,7 +2385,7 @@
</li>
<li><a href="reference/api/python/s_tir/schedule.html#tvm.s_tir.schedule.ScheduleState.get_sblock_scope">get_sblock_scope() (tvm.s_tir.schedule.ScheduleState method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.TileLayout.get_scope">get_scope() (tvm.tirx.TileLayout method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.TileLayout.get_scope">get_scope() (tvm.tirx.TileLayout method)</a>
</li>
<li><a href="reference/api/python/relax/relax.html#tvm.relax.get_shape_of">get_shape_of() (in module tvm.relax)</a>
</li>
@@ -2309,7 +2405,7 @@
</li>
<li><a href="reference/api/python/target.html#tvm.target.Target.get_target_device_type">get_target_device_type() (tvm.target.Target method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.get_tir_pipeline">get_tir_pipeline() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.get_tir_pipeline">get_tir_pipeline() (in module tvm.tirx)</a>
</li>
<li><a href="reference/api/python/meta_schedule.html#tvm.s_tir.meta_schedule.Database.get_top_k">get_top_k() (tvm.s_tir.meta_schedule.Database method)</a>
</li>
@@ -2327,7 +2423,7 @@
</li>
<li><a href="reference/api/python/relax/relax.html#tvm.relax.PyExprMutator.get_var_remap">get_var_remap() (tvm.relax.PyExprMutator method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.get_vscale_expr">get_vscale_expr() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.get_vscale_expr">get_vscale_expr() (in module tvm.tirx)</a>
</li>
<li><a href="reference/api/python/s_tir/analysis.html#tvm.s_tir.analysis.get_vtcm_compaction_passes">get_vtcm_compaction_passes() (in module tvm.s_tir.analysis)</a>
</li>
@@ -2360,7 +2456,7 @@
<li><a href="reference/api/python/testing.html#tvm.testing.Path.group">group() (tvm.testing.Path method)</a>
<ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.TileLayout.group">(tvm.tirx.TileLayout method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.TileLayout.group">(tvm.tirx.TileLayout method)</a>
</li>
</ul></li>
<li><a href="reference/api/python/topi.html#tvm.topi.nn.group_conv1d_ncw">group_conv1d_ncw() (in module tvm.topi.nn)</a>
@@ -2405,7 +2501,7 @@
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.Conv3DTransposeAttrs.groups">(tvm.relax.op.op_attrs.Conv3DTransposeAttrs property)</a>
</li>
</ul></li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.GT">GT (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.GT">GT (class in tvm.tirx)</a>
</li>
</ul></td>
</tr></table>
@@ -2415,7 +2511,7 @@
<td style="width: 33%; vertical-align: top;"><ul>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.hamming_window">hamming_window() (in module tvm.relax.op)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.handle_add_byte_offset">handle_add_byte_offset() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.handle_add_byte_offset">handle_add_byte_offset() (in module tvm.tirx)</a>
</li>
<li><a href="reference/api/python/testing.html#tvm.testing.Path.hardlink_to">hardlink_to() (tvm.testing.Path method)</a>
</li>
@@ -2449,21 +2545,21 @@
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.HintOnDeviceAttrs">HintOnDeviceAttrs (class in tvm.relax.op.op_attrs)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.HoistExpressionConfig.hoisted_conditionals">hoisted_conditionals (tvm.tirx.transform.HoistExpressionConfig property)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.HoistExpressionConfig.hoisted_conditionals">hoisted_conditionals (tvm.tirx.transform.HoistExpressionConfig property)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.HoistExpressionConfig.hoisted_let_bindings">hoisted_let_bindings (tvm.tirx.transform.HoistExpressionConfig property)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.HoistExpressionConfig.hoisted_let_bindings">hoisted_let_bindings (tvm.tirx.transform.HoistExpressionConfig property)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.HoistedConditionals">HoistedConditionals (class in tvm.tirx.transform)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.HoistedConditionals">HoistedConditionals (class in tvm.tirx.transform)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.HoistedLetBindings">HoistedLetBindings (class in tvm.tirx.transform)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.HoistedLetBindings">HoistedLetBindings (class in tvm.tirx.transform)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.HoistExpressionConfig">HoistExpressionConfig (class in tvm.tirx.transform)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.HoistExpressionConfig">HoistExpressionConfig (class in tvm.tirx.transform)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.HoistIfThenElseConfig">HoistIfThenElseConfig (class in tvm.tirx.transform)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.HoistIfThenElseConfig">HoistIfThenElseConfig (class in tvm.tirx.transform)</a>
</li>
<li><a href="reference/api/python/testing.html#tvm.testing.Path.home">home() (tvm.testing.Path class method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.hypot">hypot() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.hypot">hypot() (in module tvm.tirx)</a>
</li>
</ul></td>
</tr></table>
@@ -2486,22 +2582,22 @@
<li><a href="reference/api/python/te.html#tvm.te.if_then_else">if_then_else() (in module tvm.te)</a>
<ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.if_then_else">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.if_then_else">(in module tvm.tirx)</a>
</li>
<li><a href="reference/api/python/topi.html#tvm.topi.nn.if_then_else">(in module tvm.topi.nn)</a>
</li>
</ul></li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.HoistedConditionals.IfElseExpr">IfElseExpr (tvm.tirx.transform.HoistedConditionals attribute)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.HoistedConditionals.IfElseExpr">IfElseExpr (tvm.tirx.transform.HoistedConditionals attribute)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.HoistedConditionals.IfElseStmt">IfElseStmt (tvm.tirx.transform.HoistedConditionals attribute)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.HoistedConditionals.IfElseStmt">IfElseStmt (tvm.tirx.transform.HoistedConditionals attribute)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.IfThenElse">IfThenElse (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.IfThenElse">IfThenElse (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.NLLLossAttrs.ignore_index">ignore_index (tvm.relax.op.op_attrs.NLLLossAttrs property)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.ignore_loop_partition">ignore_loop_partition() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.ignore_loop_partition">ignore_loop_partition() (in module tvm.tirx)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.RemoveNoOpConfig.ignore_profiler_call">ignore_profiler_call (tvm.tirx.transform.RemoveNoOpConfig property)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.RemoveNoOpConfig.ignore_profiler_call">ignore_profiler_call (tvm.tirx.transform.RemoveNoOpConfig property)</a>
</li>
<li><a href="reference/api/python/relax/relax.html#tvm.relax.ExecBuilder.imm">imm() (tvm.relax.ExecBuilder method)</a>
</li>
@@ -2530,24 +2626,24 @@
<li><a href="reference/api/python/te.html#tvm.te.indexdiv">indexdiv() (in module tvm.te)</a>
<ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.indexdiv">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.indexdiv">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.MeshgridAttrs.indexing">indexing (tvm.relax.op.op_attrs.MeshgridAttrs property)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.IndexMap">IndexMap (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.IndexMap">IndexMap (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/te.html#tvm.te.indexmod">indexmod() (in module tvm.te)</a>
<ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.indexmod">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.indexmod">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.IndexPutAttrs">IndexPutAttrs (class in tvm.relax.op.op_attrs)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.SplitAttrs.indices_or_sections">indices_or_sections (tvm.relax.op.op_attrs.SplitAttrs property)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.infinity">infinity() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.infinity">infinity() (in module tvm.tirx)</a>
</li>
<li><a href="reference/api/python/transform.html#tvm.ir.transform.Pass.info">info (tvm.ir.transform.Pass property)</a>
</li>
@@ -2562,7 +2658,7 @@
<li><a href="reference/api/python/relax/transform.html#tvm.relax.transform.InlinePrivateFunctions">InlinePrivateFunctions() (in module tvm.relax.transform)</a>
<ul>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.InlinePrivateFunctions">(in module tvm.tirx.transform)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.InlinePrivateFunctions">(in module tvm.tirx.transform)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.LayoutTransformAttrs.input_axis_separators">input_axis_separators (tvm.relax.op.op_attrs.LayoutTransformAttrs property)</a>
@@ -2593,13 +2689,13 @@
</li>
<li><a href="reference/api/python/arith.html#tvm.arith.IntervalSet">IntervalSet (class in tvm.arith)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.IntImm">IntImm (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.IntImm">IntImm (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/arith.html#tvm.arith.IntSet">IntSet (class in tvm.arith)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.NonMaximumSuppressionAttrs.invalid_to_bottom">invalid_to_bottom (tvm.relax.op.op_attrs.NonMaximumSuppressionAttrs property)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.IndexMap.inverse">inverse() (tvm.tirx.IndexMap method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.IndexMap.inverse">inverse() (tvm.tirx.IndexMap method)</a>
</li>
<li><a href="reference/api/python/arith.html#tvm.arith.inverse_affine_iter_map">inverse_affine_iter_map() (in module tvm.arith)</a>
</li>
@@ -2633,7 +2729,7 @@
<li><a href="reference/api/python/script/parser.html#tvm.script.parser.ir_module">(in module tvm.script.parser)</a>
</li>
</ul></li>
- <li><a href="reference/api/python/tirx/stmt_functor.html#tvm.tirx.stmt_functor.ir_transform">ir_transform() (in module tvm.tirx.stmt_functor)</a>
+ <li><a href="tirx/api/stmt_functor.html#tvm.tirx.stmt_functor.ir_transform">ir_transform() (in module tvm.tirx.stmt_functor)</a>
</li>
<li><a href="reference/api/python/script/ir_builder.html#tvm.script.ir_builder.IRBuilder">IRBuilder (class in tvm.script.ir_builder)</a>
</li>
@@ -2659,13 +2755,13 @@
</li>
<li><a href="reference/api/python/testing.html#tvm.testing.Path.is_dir">is_dir() (tvm.testing.Path method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Layout.is_direct_sum_left">is_direct_sum_left() (tvm.tirx.Layout method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Layout.is_direct_sum_left">is_direct_sum_left() (tvm.tirx.Layout method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Layout.is_direct_sum_right">is_direct_sum_right() (tvm.tirx.Layout method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Layout.is_direct_sum_right">is_direct_sum_right() (tvm.tirx.Layout method)</a>
</li>
<li><a href="reference/api/python/s_tir/dlight.html#tvm.s_tir.dlight.SBlockInfo.is_elementwise">is_elementwise() (tvm.s_tir.dlight.SBlockInfo method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.IndexMap.is_equivalent_to">is_equivalent_to() (tvm.tirx.IndexMap method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.IndexMap.is_equivalent_to">is_equivalent_to() (tvm.tirx.IndexMap method)</a>
</li>
<li><a href="reference/api/python/arith.html#tvm.arith.IntSet.is_everything">is_everything() (tvm.arith.IntSet method)</a>
</li>
@@ -2695,28 +2791,28 @@
</li>
<li><a href="reference/api/python/s_tir/dlight.html#tvm.s_tir.dlight.SBlockInfo.is_reduction">is_reduction() (tvm.s_tir.dlight.SBlockInfo method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Buffer.is_scalar">is_scalar() (tvm.tirx.Buffer method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Buffer.is_scalar">is_scalar() (tvm.tirx.Buffer method)</a>
</li>
<li><a href="reference/api/python/testing.html#tvm.testing.Path.is_socket">is_socket() (tvm.testing.Path method)</a>
</li>
<li><a href="reference/api/python/support.html#tvm.support.utils.is_source_path">is_source_path() (in module tvm.support.utils)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Layout.is_swizzle">is_swizzle() (tvm.tirx.Layout method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Layout.is_swizzle">is_swizzle() (tvm.tirx.Layout method)</a>
</li>
<li><a href="reference/api/python/testing.html#tvm.testing.Path.is_symlink">is_symlink() (tvm.testing.Path method)</a>
</li>
<li><a href="reference/api/python/s_tir/dlight.html#tvm.s_tir.dlight.ScheduleRule.is_target_available">is_target_available() (tvm.s_tir.dlight.ScheduleRule method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Layout.is_tile_inner">is_tile_inner() (tvm.tirx.Layout method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Layout.is_tile_inner">is_tile_inner() (tvm.tirx.Layout method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Layout.is_tile_outer">is_tile_outer() (tvm.tirx.Layout method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Layout.is_tile_outer">is_tile_outer() (tvm.tirx.Layout method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Layout.is_trainium">is_trainium() (tvm.tirx.Layout method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Layout.is_trainium">is_trainium() (tvm.tirx.Layout method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Layout.is_trivial">is_trivial() (tvm.tirx.Layout method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Layout.is_trivial">is_trivial() (tvm.tirx.Layout method)</a>
<ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.TileLayout.is_trivial">(tvm.tirx.TileLayout method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.TileLayout.is_trivial">(tvm.tirx.TileLayout method)</a>
</li>
</ul></li>
<li><a href="reference/api/python/arith.html#tvm.arith.Analyzer.is_z3_enabled">is_z3_enabled (tvm.arith.Analyzer property)</a>
@@ -2726,7 +2822,7 @@
<ul>
<li><a href="reference/api/python/te.html#tvm.te.isfinite">(in module tvm.te)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.isfinite">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.isfinite">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.isinf">isinf() (in module tvm.relax.op)</a>
@@ -2734,7 +2830,7 @@
<ul>
<li><a href="reference/api/python/te.html#tvm.te.isinf">(in module tvm.te)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.isinf">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.isinf">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.isnan">isnan() (in module tvm.relax.op)</a>
@@ -2742,10 +2838,10 @@
<ul>
<li><a href="reference/api/python/te.html#tvm.te.isnan">(in module tvm.te)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.isnan">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.isnan">(in module tvm.tirx)</a>
</li>
</ul></li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.isnullptr">isnullptr() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.isnullptr">isnullptr() (in module tvm.tirx)</a>
</li>
<li><a href="reference/api/python/ir.html#tvm.ir.DictAttrs.items">items() (tvm.ir.DictAttrs method)</a>
@@ -2767,7 +2863,7 @@
</li>
<li><a href="reference/api/python/arith.html#tvm.arith.IterSumExpr">IterSumExpr (class in tvm.arith)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.IterVar">IterVar (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.IterVar">IterVar (class in tvm.tirx)</a>
</li>
</ul></td>
</tr></table>
@@ -2863,7 +2959,7 @@
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.LayerNormAttrs">LayerNormAttrs (class in tvm.relax.op.op_attrs)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Layout">Layout (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Layout">Layout (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.AdaptivePool1DAttrs.layout">layout (tvm.relax.op.op_attrs.AdaptivePool1DAttrs property)</a>
@@ -2897,9 +2993,9 @@
</li>
<li><a href="reference/api/python/testing.html#tvm.testing.Path.lchmod">lchmod() (tvm.testing.Path method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.ldexp">ldexp() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.ldexp">ldexp() (in module tvm.tirx)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.LE">LE (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.LE">LE (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/topi.html#tvm.topi.nn.leaky_relu">leaky_relu() (in module tvm.topi.nn)</a>
</li>
@@ -2915,17 +3011,17 @@
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.less_equal">less_equal() (in module tvm.relax.op)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Let">Let (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Let">Let (class in tvm.tirx)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.HoistedLetBindings.LetExpr">LetExpr (tvm.tirx.transform.HoistedLetBindings attribute)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.HoistedLetBindings.LetExpr">LetExpr (tvm.tirx.transform.HoistedLetBindings attribute)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.LetStmt">LetStmt (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.LetStmt">LetStmt (in module tvm.tirx)</a>
</li>
<li><a href="reference/api/python/support.html#tvm.support.libinfo">libinfo() (in module tvm.support)</a>
</li>
<li><a href="reference/api/python/relax/transform.html#tvm.relax.transform.LiftTransformParams">LiftTransformParams() (in module tvm.relax.transform)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.likely">likely() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.likely">likely() (in module tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.linear">linear() (in module tvm.relax.op)</a>
</li>
@@ -2969,7 +3065,7 @@
</li>
<li><a href="reference/api/python/runtime/disco.html#tvm.runtime.disco.Session.load_vm_module">load_vm_module() (tvm.runtime.disco.Session method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Buffer.local">local() (tvm.tirx.Buffer method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Buffer.local">local() (tvm.tirx.Buffer method)</a>
</li>
<li><a href="reference/api/python/testing.html#tvm.testing.local_run">local_run() (in module tvm.testing)</a>
</li>
@@ -2980,21 +3076,21 @@
<ul>
<li><a href="reference/api/python/te.html#tvm.te.log">(in module tvm.te)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.log">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.log">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/te.html#tvm.te.log10">log10() (in module tvm.te)</a>
<ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.log10">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.log10">(in module tvm.tirx)</a>
</li>
</ul></li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.log1p">log1p() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.log1p">log1p() (in module tvm.tirx)</a>
</li>
<li><a href="reference/api/python/te.html#tvm.te.log2">log2() (in module tvm.te)</a>
<ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.log2">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.log2">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.log_add_exp">log_add_exp() (in module tvm.relax.op)</a>
@@ -3012,7 +3108,7 @@
<li><a href="reference/api/python/te.html#tvm.te.logaddexp">logaddexp() (in module tvm.te)</a>
<ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.logaddexp">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.logaddexp">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.logical_and">logical_and() (in module tvm.relax.op)</a>
@@ -3031,7 +3127,7 @@
</ul></li>
<li><a href="reference/api/python/script/ir_builder.html#tvm.script.ir_builder.ir.lookup_name">lookup_name() (in module tvm.script.ir_builder.ir)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.lookup_param">lookup_param() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.lookup_param">lookup_param() (in module tvm.tirx)</a>
</li>
<li><a href="reference/api/python/script/ir_builder.html#tvm.script.ir_builder.ir.lookup_vdevice">lookup_vdevice() (in module tvm.script.ir_builder.ir)</a>
</li>
@@ -3043,17 +3139,17 @@
</li>
<li><a href="reference/api/python/relax/transform.html#tvm.relax.transform.LowerGPUIPCAllocStorage">LowerGPUIPCAllocStorage (class in tvm.relax.transform)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.LowerIntrin">LowerIntrin() (in module tvm.tirx.transform)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.LowerIntrin">LowerIntrin() (in module tvm.tirx.transform)</a>
</li>
<li><a href="reference/api/python/relax/transform.html#tvm.relax.transform.LowerRuntimeBuiltin">LowerRuntimeBuiltin() (in module tvm.relax.transform)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.LowerTIRx">LowerTIRx() (in module tvm.tirx.transform)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.LowerTIRx">LowerTIRx() (in module tvm.tirx.transform)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.LowerTIRxOpaque">LowerTIRxOpaque() (in module tvm.tirx.transform)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.LowerTIRxOpaque">LowerTIRxOpaque() (in module tvm.tirx.transform)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.LowerTVMBuiltin">LowerTVMBuiltin() (in module tvm.tirx.transform)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.LowerTVMBuiltin">LowerTVMBuiltin() (in module tvm.tirx.transform)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.LowerWarpMemory">LowerWarpMemory() (in module tvm.tirx.transform)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.LowerWarpMemory">LowerWarpMemory() (in module tvm.tirx.transform)</a>
</li>
<li><a href="reference/api/python/topi.html#tvm.topi.nn.lrn">lrn() (in module tvm.topi.nn)</a>
</li>
@@ -3065,7 +3161,7 @@
</li>
<li><a href="reference/api/python/topi.html#tvm.topi.testing.lstm_python">lstm_python() (in module tvm.topi.testing)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.LT">LT (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.LT">LT (class in tvm.tirx)</a>
</li>
</ul></td>
</tr></table>
@@ -3077,15 +3173,15 @@
</li>
<li><a href="reference/api/python/ir.html#tvm.ir.make_node">make_node() (in module tvm.ir)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.MakePackedAPI">MakePackedAPI() (in module tvm.tirx.transform)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.MakePackedAPI">MakePackedAPI() (in module tvm.tirx.transform)</a>
</li>
<li><a href="reference/api/python/ir.html#tvm.ir.Map">Map (class in tvm.ir)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.IndexMap.map_indices">map_indices() (tvm.tirx.IndexMap method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.IndexMap.map_indices">map_indices() (tvm.tirx.IndexMap method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.IndexMap.map_shape">map_shape() (tvm.tirx.IndexMap method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.IndexMap.map_shape">map_shape() (tvm.tirx.IndexMap method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.IndexMap.map_tensor">map_tensor() (tvm.tirx.IndexMap method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.IndexMap.map_tensor">map_tensor() (tvm.tirx.IndexMap method)</a>
</li>
<li><a href="reference/api/python/support.html#tvm.support.popen_pool.PopenPoolExecutor.map_with_error_catching">map_with_error_catching() (tvm.support.popen_pool.PopenPoolExecutor method)</a>
</li>
@@ -3095,7 +3191,7 @@
</li>
<li><a href="reference/api/python/relax/block_builder.html#tvm.relax.block_builder.BlockBuilder.match_cast">match_cast() (tvm.relax.block_builder.BlockBuilder method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.MatchBufferRegion">MatchBufferRegion (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.MatchBufferRegion">MatchBufferRegion (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/relax.html#tvm.relax.MatchCast">MatchCast (class in tvm.relax)</a>
</li>
@@ -3123,14 +3219,14 @@
</li>
<li><a href="reference/api/python/topi.html#tvm.topi.testing.matrix_set_diag">matrix_set_diag() (in module tvm.topi.testing)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Max">Max (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Max">Max (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.max">max() (in module tvm.relax.op)</a>
<ul>
<li><a href="reference/api/python/te.html#tvm.te.max">(in module tvm.te)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.max">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.max">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.NonMaximumSuppressionAttrs.max_output_size">max_output_size (tvm.relax.op.op_attrs.NonMaximumSuppressionAttrs property)</a>
@@ -3143,12 +3239,12 @@
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.nn.max_pool3d">max_pool3d() (in module tvm.relax.op.nn)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.RemoveNoOpConfig.max_simplification_steps">max_simplification_steps (tvm.tirx.transform.RemoveNoOpConfig property)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.RemoveNoOpConfig.max_simplification_steps">max_simplification_steps (tvm.tirx.transform.RemoveNoOpConfig property)</a>
</li>
<li><a href="reference/api/python/te.html#tvm.te.max_value">max_value() (in module tvm.te)</a>
<ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.max_value">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.max_value">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.maximum">maximum() (in module tvm.relax.op)</a>
@@ -3187,20 +3283,20 @@
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.Resize2DAttrs.method">method (tvm.relax.op.op_attrs.Resize2DAttrs property)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Min">Min (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Min">Min (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.min">min() (in module tvm.relax.op)</a>
<ul>
<li><a href="reference/api/python/te.html#tvm.te.min">(in module tvm.te)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.min">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.min">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/te.html#tvm.te.min_value">min_value() (in module tvm.te)</a>
<ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.min_value">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.min_value">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.minimum">minimum() (in module tvm.relax.op)</a>
@@ -3209,7 +3305,15 @@
</li>
<li><a href="reference/api/python/testing.html#tvm.testing.Path.mkdir">mkdir() (tvm.testing.Path method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Mod">Mod (class in tvm.tirx)</a>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.mma_fill">mma_fill() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.mma_fill_legacy">mma_fill_legacy() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.mma_store">mma_store() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.mma_store_legacy">mma_store_legacy() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Mod">Mod (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/s_tir/schedule.html#tvm.s_tir.schedule.Schedule.mod">mod (tvm.s_tir.schedule.Schedule property)</a>
</li>
@@ -3230,6 +3334,18 @@
<ul>
<li><a href="reference/api/python/arith.html#module-tvm.arith">tvm.arith</a>
+</li>
+ <li><a href="tirx/api/backend.html#module-tvm.backend.cuda">tvm.backend.cuda</a>
+</li>
+ <li><a href="tirx/api/backend.html#module-tvm.backend.cuda.lang">tvm.backend.cuda.lang</a>
+</li>
+ <li><a href="tirx/api/backend.html#module-tvm.backend.cuda.op">tvm.backend.cuda.op</a>
+</li>
+ <li><a href="tirx/api/backend.html#module-tvm.backend.cuda.operator">tvm.backend.cuda.operator</a>
+</li>
+ <li><a href="tirx/api/backend.html#module-tvm.backend.cuda.script">tvm.backend.cuda.script</a>
+</li>
+ <li><a href="tirx/api/backend.html#module-tvm.backend.cuda.target_tags">tvm.backend.cuda.target_tags</a>
</li>
<li><a href="reference/api/python/contrib.html#module-tvm.contrib">tvm.contrib</a>
</li>
@@ -3411,15 +3527,13 @@
</li>
<li><a href="reference/api/python/testing.html#module-tvm.testing">tvm.testing</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#module-tvm.tirx">tvm.tirx</a>
-</li>
- <li><a href="reference/api/python/tirx/analysis.html#module-tvm.tirx.analysis.analysis">tvm.tirx.analysis.analysis</a>
+ <li><a href="tirx/api/tirx.html#module-tvm.tirx">tvm.tirx</a>
</li>
- <li><a href="reference/api/python/tirx/backend.html#module-tvm.tirx.backend">tvm.tirx.backend</a>
+ <li><a href="tirx/api/analysis.html#module-tvm.tirx.analysis.analysis">tvm.tirx.analysis.analysis</a>
</li>
- <li><a href="reference/api/python/tirx/stmt_functor.html#module-tvm.tirx.stmt_functor">tvm.tirx.stmt_functor</a>
+ <li><a href="tirx/api/stmt_functor.html#module-tvm.tirx.stmt_functor">tvm.tirx.stmt_functor</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#module-tvm.tirx.transform">tvm.tirx.transform</a>
+ <li><a href="tirx/api/transform.html#module-tvm.tirx.transform">tvm.tirx.transform</a>
</li>
<li><a href="reference/api/python/topi.html#module-tvm.topi.cpp">tvm.topi.cpp</a>
</li>
@@ -3448,7 +3562,7 @@
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.BatchNormAttrs.momentum">momentum (tvm.relax.op.op_attrs.BatchNormAttrs property)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Mul">Mul (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Mul">Mul (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.multibox_transform_loc">multibox_transform_loc() (in module tvm.relax.op)</a>
@@ -3467,7 +3581,7 @@
<ul>
<li><a href="reference/api/python/te.html#tvm.te.multiply">(in module tvm.te)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.multiply">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.multiply">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/relax.html#tvm.relax.DataflowBlockRewrite.mutate_irmodule">mutate_irmodule() (tvm.relax.DataflowBlockRewrite method)</a>
@@ -3487,7 +3601,7 @@
<li><a href="reference/api/python/s_tir/schedule.html#tvm.s_tir.schedule.InstructionKind.name">name (tvm.s_tir.schedule.InstructionKind attribute)</a>
<ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.ExecScope.name">(tvm.tirx.ExecScope property)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.ExecScope.name">(tvm.tirx.ExecScope property)</a>
</li>
</ul></li>
<li><a href="reference/api/python/script/ir_builder.html#tvm.script.ir_builder.IRBuilder.name">name() (tvm.script.ir_builder.IRBuilder static method)</a>
@@ -3500,7 +3614,7 @@
</li>
<li><a href="reference/api/python/topi.html#tvm.topi.nn.namedtuple">namedtuple() (in module tvm.topi.nn)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.NarrowDataType">NarrowDataType() (in module tvm.tirx.transform)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.NarrowDataType">NarrowDataType() (in module tvm.tirx.transform)</a>
</li>
<li><a href="reference/api/python/topi.html#tvm.topi.image.nchw_pack_layout">nchw_pack_layout() (in module tvm.topi.image)</a>
</li>
@@ -3508,25 +3622,25 @@
</li>
<li><a href="reference/api/python/te.html#tvm.te.Tensor.ndim">ndim (tvm.te.Tensor property)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.NE">NE (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.NE">NE (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/te.html#tvm.te.nearbyint">nearbyint() (in module tvm.te)</a>
<ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.nearbyint">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.nearbyint">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.negative">negative() (in module tvm.relax.op)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.HoistedConditionals.Never">Never (tvm.tirx.transform.HoistedConditionals attribute)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.HoistedConditionals.Never">Never (tvm.tirx.transform.HoistedConditionals attribute)</a>
<ul>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.HoistedLetBindings.Never">(tvm.tirx.transform.HoistedLetBindings attribute)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.HoistedLetBindings.Never">(tvm.tirx.transform.HoistedLetBindings attribute)</a>
</li>
</ul></li>
<li><a href="reference/api/python/meta_schedule.html#tvm.s_tir.meta_schedule.TaskScheduler.next_task_id">next_task_id() (tvm.s_tir.meta_schedule.TaskScheduler method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.nextafter">nextafter() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.nextafter">nextafter() (in module tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.nn.nll_loss">nll_loss() (in module tvm.relax.op.nn)</a>
@@ -3542,8 +3656,6 @@
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.grad.no_grad">no_grad() (in module tvm.relax.op.grad)</a>
</li>
- </ul></td>
- <td style="width: 33%; vertical-align: top;"><ul>
<li><a href="reference/api/python/ir.html#tvm.ir.Node">Node (class in tvm.ir)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.non_max_suppression">non_max_suppression() (in module tvm.relax.op)</a>
@@ -3554,7 +3666,7 @@
</ul></li>
<li><a href="reference/api/python/topi.html#tvm.topi.testing.non_max_suppression_python">non_max_suppression_python() (in module tvm.topi.testing)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.IndexMap.non_surjective_inverse">non_surjective_inverse() (tvm.tirx.IndexMap method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.IndexMap.non_surjective_inverse">non_surjective_inverse() (tvm.tirx.IndexMap method)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.NonMaximumSuppressionAttrs">NonMaximumSuppressionAttrs (class in tvm.relax.op.op_attrs)</a>
</li>
@@ -3562,6 +3674,8 @@
</li>
<li><a href="reference/api/python/contrib.html#tvm.contrib.random.normal">normal() (in module tvm.contrib.random)</a>
</li>
+ </ul></td>
+ <td style="width: 33%; vertical-align: top;"><ul>
<li><a href="reference/api/python/relax/transform.html#tvm.relax.transform.Normalize">Normalize() (in module tvm.relax.transform)</a>
</li>
<li><a href="reference/api/python/relax/block_builder.html#tvm.relax.block_builder.BlockBuilder.normalize">normalize() (tvm.relax.block_builder.BlockBuilder method)</a>
@@ -3576,7 +3690,7 @@
</li>
<li><a href="reference/api/python/relax/transform.html#tvm.relax.transform.NormalizeGlobalVar">NormalizeGlobalVar() (in module tvm.relax.transform)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Not">Not (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Not">Not (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.not_equal">not_equal() (in module tvm.relax.op)</a>
</li>
@@ -3600,6 +3714,40 @@
<li><a href="reference/api/python/runtime/disco.html#tvm.runtime.disco.Session.num_workers">(tvm.runtime.disco.Session property)</a>
</li>
</ul></li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.nvshmem_barrier_all">nvshmem_barrier_all() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.nvshmem_fence">nvshmem_fence() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.nvshmem_getmem_nbi">nvshmem_getmem_nbi() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.nvshmem_getmem_nbi_block">nvshmem_getmem_nbi_block() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.nvshmem_getmem_nbi_warp">nvshmem_getmem_nbi_warp() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.nvshmem_my_pe">nvshmem_my_pe() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.nvshmem_n_pes">nvshmem_n_pes() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.nvshmem_putmem_nbi">nvshmem_putmem_nbi() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.nvshmem_putmem_nbi_block">nvshmem_putmem_nbi_block() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.nvshmem_putmem_nbi_warp">nvshmem_putmem_nbi_warp() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.nvshmem_putmem_signal_nbi">nvshmem_putmem_signal_nbi() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.nvshmem_putmem_signal_nbi_block">nvshmem_putmem_signal_nbi_block() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.nvshmem_putmem_signal_nbi_warp">nvshmem_putmem_signal_nbi_warp() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.nvshmem_quiet">nvshmem_quiet() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.nvshmem_signal_op">nvshmem_signal_op() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.nvshmem_wait_until">nvshmem_wait_until() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.script.NVSHMEMNamespace">NVSHMEMNamespace (class in tvm.backend.cuda.script)</a>
+</li>
</ul></td>
</tr></table>
@@ -3608,7 +3756,7 @@
<td style="width: 33%; vertical-align: top;"><ul>
<li><a href="reference/api/python/relax/relax.html#tvm.relax.ObjectType">ObjectType (class in tvm.relax)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Buffer.offset_of">offset_of() (tvm.tirx.Buffer method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Buffer.offset_of">offset_of() (tvm.tirx.Buffer method)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.one_hot">one_hot() (in module tvm.relax.op)</a>
@@ -3648,7 +3796,7 @@
</li>
<li><a href="reference/api/python/target.html#tvm.target.TargetKind.options_from_name">options_from_name() (tvm.target.TargetKind static method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Or">Or (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Or">Or (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.Conv1DAttrs.out_dtype">out_dtype (tvm.relax.op.op_attrs.Conv1DAttrs property)</a>
@@ -3734,7 +3882,7 @@
<h2 id="P">P</h2>
<table style="width: 100%" class="indextable genindextable"><tr>
<td style="width: 33%; vertical-align: top;"><ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Layout.pack">pack() (tvm.tirx.Layout method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Layout.pack">pack() (tvm.tirx.Layout method)</a>
</li>
<li><a href="reference/api/python/contrib.html#tvm.contrib.hexagon.pack_imports">pack_imports() (in module tvm.contrib.hexagon)</a>
</li>
@@ -3824,14 +3972,14 @@
</li>
<li><a href="reference/api/python/contrib.html#tvm.contrib.tvmjs.TensorCacheShardingManager.pending_nbytes">pending_nbytes (tvm.contrib.tvmjs.TensorCacheShardingManager property)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Buffer.permute">permute() (tvm.tirx.Buffer method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Buffer.permute">permute() (tvm.tirx.Buffer method)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.TileLayout.permute_by_groups">permute_by_groups() (tvm.tirx.TileLayout method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.TileLayout.permute_by_groups">permute_by_groups() (tvm.tirx.TileLayout method)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.permute_dims">permute_dims() (in module tvm.relax.op)</a>
<ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.TileLayout.permute_dims">(tvm.tirx.TileLayout method)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.TileLayout.permute_dims">(tvm.tirx.TileLayout method)</a>
</li>
</ul></li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.PermuteDimsAttrs">PermuteDimsAttrs (class in tvm.relax.op.op_attrs)</a>
@@ -3850,7 +3998,7 @@
</li>
<li><a href="reference/api/python/ir.html#tvm.ir.PointerType">PointerType (class in tvm.ir)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.PointerValueTypeRewrite">PointerValueTypeRewrite() (in module tvm.tirx.transform)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.PointerValueTypeRewrite">PointerValueTypeRewrite() (in module tvm.tirx.transform)</a>
</li>
<li><a href="reference/api/python/topi.html#tvm.topi.nn.pool1d">pool1d() (in module tvm.topi.nn)</a>
</li>
@@ -3860,8 +4008,6 @@
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.Pool2DAttrs">Pool2DAttrs (class in tvm.relax.op.op_attrs)</a>
</li>
- </ul></td>
- <td style="width: 33%; vertical-align: top;"><ul>
<li><a href="reference/api/python/topi.html#tvm.topi.nn.pool3d">pool3d() (in module tvm.topi.nn)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.op_attrs.Pool3DAttrs">Pool3DAttrs (class in tvm.relax.op.op_attrs)</a>
@@ -3891,7 +4037,7 @@
<li><a href="reference/api/python/te.html#tvm.te.popcount">popcount() (in module tvm.te)</a>
<ul>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.popcount">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.popcount">(in module tvm.tirx)</a>
</li>
</ul></li>
<li><a href="reference/api/python/support.html#tvm.support.popen_pool.PopenPoolExecutor">PopenPoolExecutor (class in tvm.support.popen_pool)</a>
@@ -3903,7 +4049,7 @@
<li><a href="reference/api/python/relax/analysis.html#tvm.relax.analysis.post_order_visit">post_order_visit() (in module tvm.relax.analysis)</a>
<ul>
- <li><a href="reference/api/python/tirx/stmt_functor.html#tvm.tirx.stmt_functor.post_order_visit">(in module tvm.tirx.stmt_functor)</a>
+ <li><a href="tirx/api/stmt_functor.html#tvm.tirx.stmt_functor.post_order_visit">(in module tvm.tirx.stmt_functor)</a>
</li>
</ul></li>
<li><a href="reference/api/python/meta_schedule.html#tvm.s_tir.meta_schedule.SearchStrategy.post_tuning">post_tuning() (tvm.s_tir.meta_schedule.SearchStrategy method)</a>
@@ -3914,17 +4060,17 @@
</ul></li>
<li><a href="reference/api/python/meta_schedule.html#tvm.s_tir.meta_schedule.Postproc">Postproc (class in tvm.s_tir.meta_schedule)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.pow">pow() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.pow">pow() (in module tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.power">power() (in module tvm.relax.op)</a>
<ul>
<li><a href="reference/api/python/te.html#tvm.te.power">(in module tvm.te)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.power">(in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.power">(in module tvm.tirx)</a>
</li>
</ul></li>
- <li><a href="reference/api/python/tirx/stmt_functor.html#tvm.tirx.stmt_functor.pre_order_visit">pre_order_visit() (in module tvm.tirx.stmt_functor)</a>
+ <li><a href="tirx/api/stmt_functor.html#tvm.tirx.stmt_functor.pre_order_visit">pre_order_visit() (in module tvm.tirx.stmt_functor)</a>
</li>
<li><a href="reference/api/python/meta_schedule.html#tvm.s_tir.meta_schedule.SearchStrategy.pre_tuning">pre_tuning() (tvm.s_tir.meta_schedule.SearchStrategy method)</a>
@@ -3932,7 +4078,7 @@
<li><a href="reference/api/python/meta_schedule.html#tvm.s_tir.meta_schedule.TuneContext.pre_tuning">(tvm.s_tir.meta_schedule.TuneContext method)</a>
</li>
</ul></li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.Predicate">Predicate (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Predicate">Predicate (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/relax/training.html#tvm.relax.training.Trainer.predict">predict() (tvm.relax.training.Trainer method)</a>
@@ -3950,13 +4096,13 @@
</li>
<li><a href="reference/api/python/arith.html#tvm.arith.PresburgerSet">PresburgerSet (class in tvm.arith)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.prim_func_pass">prim_func_pass() (in module tvm.tirx.transform)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.prim_func_pass">prim_func_pass() (in module tvm.tirx.transform)</a>
</li>
<li><a href="reference/api/python/ir.html#tvm.ir.PrimExpr">PrimExpr (class in tvm.ir)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.PrimFunc">PrimFunc (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.PrimFunc">PrimFunc (class in tvm.tirx)</a>
</li>
- <li><a href="reference/api/python/tirx/transform.html#tvm.tirx.transform.PrimFuncPass">PrimFuncPass (class in tvm.tirx.transform)</a>
+ <li><a href="tirx/api/transform.html#tvm.tirx.transform.PrimFuncPass">PrimFuncPass (class in tvm.tirx.transform)</a>
</li>
<li><a href="reference/api/python/ir.html#tvm.ir.PrimType">PrimType (class in tvm.ir)</a>
@@ -3974,29 +4120,217 @@
</li>
<li><a href="reference/api/python/instrument.html#tvm.ir.instrument.PrintBeforeAll">PrintBeforeAll (class in tvm.ir.instrument)</a>
</li>
+ </ul></td>
+ <td style="width: 33%; vertical-align: top;"><ul>
<li><a href="reference/api/python/transform.html#tvm.ir.transform.PrintIR">PrintIR() (in module tvm.ir.transform)</a>
</li>
<li><a href="reference/api/python/runtime/disco.html#tvm.runtime.disco.ProcessSession">ProcessSession (class in tvm.runtime.disco)</a>
</li>
<li><a href="reference/api/python/relax/op.html#tvm.relax.op.prod">prod() (in module tvm.relax.op)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.ProducerLoad">ProducerLoad (class in tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.ProducerLoad">ProducerLoad (class in tvm.tirx)</a>
</li>
<li><a href="reference/api/python/meta_schedule.html#tvm.s_tir.meta_schedule.Profiler">Profiler (class in tvm.s_tir.meta_schedule)</a>
</li>
<li><a href="reference/api/python/arith.html#tvm.arith.ProofStrength">ProofStrength (class in tvm.arith)</a>
</li>
- <li><a href="reference/api/python/tirx/tirx.html#tvm.tirx.ptr_byte_offset">ptr_byte_offset() (in module tvm.tirx)</a>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.ptr_byte_offset">ptr_byte_offset() (in module tvm.tirx)</a>
+</li>
+ <li><a href="tirx/api/tirx.html#tvm.tirx.Buffer.ptr_to">ptr_to() (tvm.tirx.Buffer method)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.ptx_add_f32">ptx_add_f32() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.ptx_add_f32x2">ptx_add_f32x2() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.ptx_add_f64">ptx_add_f64() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.ptx_any_sync">ptx_any_sync() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.ptx_bar_arrive">ptx_bar_arrive() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.ptx_bar_sync">ptx_bar_sync() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.ptx_barrier_cluster_arrive">ptx_barrier_cluster_arrive() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.ptx_barrier_cluster_wait">ptx_barrier_cluster_wait() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.ptx_clc_query_cancel">ptx_clc_query_cancel() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.ptx_clc_try_cancel">ptx_clc_try_cancel() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.ptx_cp_async">ptx_cp_async() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.ptx_cp_async_bulk">ptx_cp_async_bulk() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.ptx_cp_async_bulk_commit_group">ptx_cp_async_bulk_commit_group() (in module tvm.backend.cuda.op)</a>
+</li>
+ <li><a href="tirx/api/backend.html#tvm.backend.cuda.op.ptx_cp_async_bulk_shared_to_cluster">ptx_cp_async_bulk_shared_to_cluster() (in module tvm.backend.cuda.op)</a>
+</li>
... 34832 lines suppressed ...