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Posted to commits@nuttx.apache.org by ac...@apache.org on 2020/01/15 14:27:14 UTC
[incubator-nuttx] branch pr105 updated (bf5d48a -> 39c0d47)
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a change to branch pr105
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git.
from bf5d48a Add SPWM example to test STM32L4 PWM driver low level operations
new 07489a1 arch/arm/include/cxd56xx/audio.h: Fix minor typos
new ad3acf6 fix warning: passing argument 4 of up_x11initialize from incompatible pointer type
new 72cff79 boards: spresense: Update README.txt regarding SMP
new 86afa7e ReleaseNotes: Fix the latest version number info
new 70119a3 sched/signal/sig_default.c: fix compilation error when CONFIG_SIG_SIGPIPE_ACTION undefined
new 39c0d47 arch/arm/src/nrf52: use the same naming convention for register defs
The 6 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
ReleaseNotes | 2 +-
arch/arm/include/cxd56xx/audio.h | 2 +-
arch/arm/src/nrf52/hardware/nrf52_ficr.h | 11 +---
arch/arm/src/nrf52/hardware/nrf52_gpio.h | 14 ++---
arch/arm/src/nrf52/hardware/nrf52_rng.h | 40 +++++++------
arch/arm/src/nrf52/hardware/nrf52_saadc.h | 56 ++++++++---------
arch/arm/src/nrf52/hardware/nrf52_tim.h | 99 +++++++++++++++++++++++++++++++
arch/arm/src/nrf52/hardware/nrf52_wdt.h | 24 ++++++--
arch/arm/src/nrf52/nrf52_gpio.c | 12 ++--
arch/arm/src/nrf52/nrf52_rng.c | 20 +++----
arch/arm/src/nrf52/nrf52_wdt.c | 25 ++++----
arch/arm/src/nrf52/nrf52_wdt.h | 24 +++-----
arch/sim/src/sim/up_internal.h | 2 +-
arch/sim/src/sim/up_x11framebuffer.c | 2 +-
boards/arm/cxd56xx/spresense/README.txt | 2 +-
sched/signal/sig_default.c | 2 +-
16 files changed, 217 insertions(+), 120 deletions(-)
create mode 100644 arch/arm/src/nrf52/hardware/nrf52_tim.h
[incubator-nuttx] 04/06: ReleaseNotes: Fix the latest version
number info
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch pr105
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 86afa7ee9eb682c1815254079305c02813d18f4e
Author: Masayuki Ishikawa <Ma...@jp.sony.com>
AuthorDate: Wed Jan 15 16:17:16 2020 +0900
ReleaseNotes: Fix the latest version number info
Signed-off-by: Masayuki Ishikawa <Ma...@jp.sony.com>
---
ReleaseNotes | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/ReleaseNotes b/ReleaseNotes
index e9c6022..72b478d 100644
--- a/ReleaseNotes
+++ b/ReleaseNotes
@@ -25651,7 +25651,7 @@ information):
NuttX-8.2 Release Notes
------------------------
-The 133nd release of NuttX, Version 8.3, was made on November 16, 2019,
+The 133rd release of NuttX, Version 8.2, was made on November 16, 2019,
and is available for download from the Bitbucket.org website. Note
that release consists of two tarballs: nuttx-8.2.tar.gz and
apps-8.2.tar.gz. These are available from:
[incubator-nuttx] 05/06: sched/signal/sig_default.c: fix
compilation error when CONFIG_SIG_SIGPIPE_ACTION undefined
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch pr105
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 70119a30b64ded8188dc5d87ebce4feb775c2c1b
Author: raiden00pl <ra...@gmail.com>
AuthorDate: Wed Jan 15 14:42:32 2020 +0100
sched/signal/sig_default.c: fix compilation error when CONFIG_SIG_SIGPIPE_ACTION undefined
---
sched/signal/sig_default.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sched/signal/sig_default.c b/sched/signal/sig_default.c
index 1cd861b..69a7bb6 100644
--- a/sched/signal/sig_default.c
+++ b/sched/signal/sig_default.c
@@ -62,7 +62,7 @@
#if defined(CONFIG_SIG_SIGUSR1_ACTION) || defined(CONFIG_SIG_SIGUSR2_ACTION) || \
defined(CONFIG_SIG_SIGALRM_ACTION) || defined(CONFIG_SIG_SIGPOLL_ACTION) || \
- defined(CONFIG_SIG_SIGKILL_ACTION)
+ defined(CONFIG_SIG_SIGKILL_ACTION) || defined(CONFIG_SIG_SIGPIPE_ACTION)
# define HAVE_NXSIG_ABNORMAL_TERMINANTION 1
#endif
[incubator-nuttx] 06/06: arch/arm/src/nrf52: use the same naming
convention for register defs
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch pr105
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 39c0d47e16960af7405119eb0b2fcb9a9be0bec6
Author: raiden00pl <ra...@gmail.com>
AuthorDate: Wed Jan 15 15:18:19 2020 +0100
arch/arm/src/nrf52: use the same naming convention for register defs
arch/arm/src/nrf52/hardware/nrf52_ficr.h: remove invalid defs
arch/arm/src/nrf52/hardware: add TIMER register defs
---
arch/arm/src/nrf52/hardware/nrf52_ficr.h | 11 +---
arch/arm/src/nrf52/hardware/nrf52_gpio.h | 14 ++---
arch/arm/src/nrf52/hardware/nrf52_rng.h | 40 +++++++------
arch/arm/src/nrf52/hardware/nrf52_saadc.h | 56 ++++++++---------
arch/arm/src/nrf52/hardware/nrf52_tim.h | 99 +++++++++++++++++++++++++++++++
arch/arm/src/nrf52/hardware/nrf52_wdt.h | 24 ++++++--
arch/arm/src/nrf52/nrf52_gpio.c | 12 ++--
arch/arm/src/nrf52/nrf52_rng.c | 20 +++----
arch/arm/src/nrf52/nrf52_wdt.c | 25 ++++----
arch/arm/src/nrf52/nrf52_wdt.h | 24 +++-----
10 files changed, 211 insertions(+), 114 deletions(-)
diff --git a/arch/arm/src/nrf52/hardware/nrf52_ficr.h b/arch/arm/src/nrf52/hardware/nrf52_ficr.h
index e047593..e73d0d2 100644
--- a/arch/arm/src/nrf52/hardware/nrf52_ficr.h
+++ b/arch/arm/src/nrf52/hardware/nrf52_ficr.h
@@ -149,15 +149,6 @@
/* FICR Register Bitfield Definitions **************************************************************/
-#define NRF52_FICR_READY_READY (1 << 0) /* FICR is ready */
-
-#define NRF52_FICR_CONFIG_WEN (1 << 0) /* Enable write program memory */
-
-#define NRF52_FICR_ICACHECNF_CACHEEN (1 << 0) /* Cache enable */
-#define NRF52_FICR_ICACHECNF_CACHEPROFEN (1 << 8) /* Cache profiling enable */
-
-/* ENABLE Register */
-
-/* INTENSET Register */
+/* TODO: */
#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_FICR_H */
diff --git a/arch/arm/src/nrf52/hardware/nrf52_gpio.h b/arch/arm/src/nrf52/hardware/nrf52_gpio.h
index 47a7751..4d0aace 100644
--- a/arch/arm/src/nrf52/hardware/nrf52_gpio.h
+++ b/arch/arm/src/nrf52/hardware/nrf52_gpio.h
@@ -95,12 +95,12 @@
/* Register bit definitions *********************************************************/
-#define NRF52_GPIO_CNF_DIR (1 << 0) /* Bit 0: Pin direction */
-#define NRF52_GPIO_CNF_INPUT (1 << 1) /* Bit 1: Input buffer disconnect */
-#define NRF52_GPIO_CNF_PULL_SHIFT (2)
-#define NRF52_GPIO_CNF_PULL_MASK (0x3 << NRF52_GPIO_CNF_PULL_SHIFT)
-# define NRF52_GPIO_CNF_PULL_DISABLED (0 << NRF52_GPIO_CNF_PULL_SHIFT)
-# define NRF52_GPIO_CNF_PULL_DOWN (1 << NRF52_GPIO_CNF_PULL_SHIFT)
-# define NRF52_GPIO_CNF_PULL_UP (3 << NRF52_GPIO_CNF_PULL_SHIFT)
+#define GPIO_CNF_DIR (1 << 0) /* Bit 0: Pin direction */
+#define GPIO_CNF_INPUT (1 << 1) /* Bit 1: Input buffer disconnect */
+#define GPIO_CNF_PULL_SHIFT (2)
+#define GPIO_CNF_PULL_MASK (0x3 << GPIO_CNF_PULL_SHIFT)
+# define GPIO_CNF_PULL_DISABLED (0 << GPIO_CNF_PULL_SHIFT)
+# define GPIO_CNF_PULL_DOWN (1 << GPIO_CNF_PULL_SHIFT)
+# define GPIO_CNF_PULL_UP (3 << GPIO_CNF_PULL_SHIFT)
#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_GPIO_H */
diff --git a/arch/arm/src/nrf52/hardware/nrf52_rng.h b/arch/arm/src/nrf52/hardware/nrf52_rng.h
index b322a09..726000e 100644
--- a/arch/arm/src/nrf52/hardware/nrf52_rng.h
+++ b/arch/arm/src/nrf52/hardware/nrf52_rng.h
@@ -48,34 +48,38 @@
* Pre-processor Definitions
************************************************************************************/
-/* Register Offsets *****************************************************************/
+/* Register Offsets for RNG *********************************************************/
-#define NRF52_RNG_T_START_OFFSET 0x000 /* RNG Task Start */
-#define NRF52_RNG_T_STOP_OFFSET 0x004 /* RNG Task Stop */
-#define NRF52_RNG_EVENT_RDY_OFFSET 0x100 /* RNG Eevent ValRDY */
-#define NRF52_RNG_SHORT_OFFSET 0x200 /* RNG Short Register */
-#define NRF52_RNG_INT_SET_OFFSET 0x304 /* RNG INT SET Register */
-#define NRF52_RNG_INT_CLR_OFFSET 0x308 /* RNG INT CLR Register */
-#define NRF52_RNG_CONFIG_OFFSET 0x504 /* RNG CONFIG Register */
-#define NRF52_RNG_VALUE_OFFSET 0x508 /* RNG Value Register */
+#define NRF52_RNG_TASKS_START_OFFSET 0x0000 /* RNG Task Start */
+#define NRF52_RNG_TASKS_STOP_OFFSET 0x0004 /* RNG Task Stop */
+#define NRF52_RNG_EVENTS_RDY_OFFSET 0x0100 /* RNG Eevent ValRDY */
+#define NRF52_RNG_SHORTS_OFFSET 0x0200 /* RNG Short Register */
+#define NRF52_RNG_INTSET_OFFSET 0x0304 /* RNG INT SET Register */
+#define NRF52_RNG_INTCLR_OFFSET 0x0308 /* RNG INT CLR Register */
+#define NRF52_RNG_CONFIG_OFFSET 0x0504 /* RNG CONFIG Register */
+#define NRF52_RNG_VALUE_OFFSET 0x0508 /* RNG Value Register */
-/* Register Addresses ***************************************************************/
+/* Register Addresses for RNG *******************************************************/
-#define NRF52_RNG_T_START (NRF52_RNG_BASE + NRF52_RNG_T_START_OFFSET)
-#define NRF52_RNG_T_STOP (NRF52_RNG_BASE + NRF52_RNG_T_STOP_OFFSET)
-#define NRF52_RNG_EVENT_RDY (NRF52_RNG_BASE + NRF52_RNG_EVENT_RDY_OFFSET)
+#define NRF52_RNG_TASKS_START (NRF52_RNG_BASE + NRF52_RNG_TASKS_START_OFFSET)
+#define NRF52_RNG_TASKS_STOP (NRF52_RNG_BASE + NRF52_RNG_TASKS_STOP_OFFSET)
+#define NRF52_RNG_EVENTS_RDY (NRF52_RNG_BASE + NRF52_RNG_EVENTS_RDY_OFFSET)
-#define NRF52_RNG_SHORT (NRF52_RNG_BASE + NRF52_RNG_SHORT_OFFSET)
-#define NRF52_RNG_INT_SET (NRF52_RNG_BASE + NRF52_RNG_INT_SET_OFFSET)
-#define NRF52_RNG_INT_CLR (NRF52_RNG_BASE + NRF52_RNG_INT_CLR_OFFSET)
+#define NRF52_RNG_SHORTS (NRF52_RNG_BASE + NRF52_RNG_SHORTS_OFFSET)
+#define NRF52_RNG_INTSET (NRF52_RNG_BASE + NRF52_RNG_INTSET_OFFSET)
+#define NRF52_RNG_INTCLR (NRF52_RNG_BASE + NRF52_RNG_INTCLR_OFFSET)
#define NRF52_RNG_CONFIG (NRF52_RNG_BASE + NRF52_RNG_CONFIG_OFFSET)
#define NRF52_RNG_VALUE (NRF52_RNG_BASE + NRF52_RNG_VALUE_OFFSET)
/* Register Bitfield Definitions ****************************************************/
-/* IntEnSet / IntEnClr Register Bit */
+/* INTSET/INTCLR Register */
-#define NRF52_RNG_INT_EVENT_RDY (1<<0)
+#define RNG_INT_RDY (1 << 0) /* Bit 0: VALRDY event */
+
+/* CONFIG Register */
+
+#define RNG_CONFIG_DERCEN (1 << 0) /* Bit 0: Bias correction */
#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_STM32_RNG_H */
diff --git a/arch/arm/src/nrf52/hardware/nrf52_saadc.h b/arch/arm/src/nrf52/hardware/nrf52_saadc.h
index 9b7fdd7..8704d71 100644
--- a/arch/arm/src/nrf52/hardware/nrf52_saadc.h
+++ b/arch/arm/src/nrf52/hardware/nrf52_saadc.h
@@ -49,33 +49,33 @@
/* Register offsets for SAADC **********************************************/
-#define NRF52_SAADC_TASKS_START 0x0000 /* Start the SAADCM */
-#define NRF52_SAADC_TASKS_SAMPLE 0x0004 /* Takes one SAADC sample */
-#define NRF52_SAADC_TASKS_STOP 0x0008 /* Stop the SAADC */
-#define NRF52_SAADC_TASKS_CALEOFFSET 0x000c /* Starts offset auto-calibration */
-#define NRF52_SAADC_EVENTS_STARTED 0x0100 /* The SAADC has started */
-#define NRF52_SAADC_EVENTS_END 0x0104 /* The SAADC has filled up the result buffer */
-#define NRF52_SAADC_EVENTS_DONE 0x0108 /* A conversio ntask has been completed */
-#define NRF52_SAADC_EVENTS_RESULTDONE 0x010c /* Result ready for transfer to RAM */
-#define NRF52_SAADC_EVENTS_CALDONE 0x0110 /* Calibration is complete */
-#define NRF52_SAADC_EVENTS_STOPPED 0x0110 /* The SAADC has stopped */
-#define NRF52_SAADC_EVENTS_CHLIMH(x) (0x118 + (x + 0x8)) /* Limit high event for channel x */
-#define NRF52_SAADC_EVENTS_CHLIML(x) (0x11c + (x + 0x8)) /* Limit low event for channel x */
-#define NRF52_SAADC_INTEN 0x0300 /* Enable or disable interrupt */
-#define NRF52_SAADC_INTENSET 0x0304 /* Enable interrupt */
-#define NRF52_SAADC_INTENCLR 0x0308 /* Disable interrupt */
-#define NRF52_SAADC_STATUS 0x0400 /* Status */
-#define NRF52_SAADC_ENABLE 0x0500 /* Enable or disable SAADC */
-#define NRF52_SAADC_CHPSELP(x) (0x510 + (x + 0x10)) /* Input positive pin for CH[x] */
-#define NRF52_SAADC_CHPSELN(x) (0x514 + (x + 0x10)) /* Input negative pin for CH[x] */
-#define NRF52_SAADC_CHCONFIG(x) (0x518 + (x + 0x10)) /* Input configuration for CH[x] */
-#define NRF52_SAADC_CHLIMIT(x) (0x51c + (x + 0x10)) /* High/low limits for event monitoring of a CH[x] */
-#define NRF52_SAADC_RESOLUTION 0x05f0 /* Resolution configuration */
-#define NRF52_SAADC_OVERSAMPLE 0x05f4 /* Oversampling configuration */
-#define NRF52_SAADC_SAMPLERATE 0x05f8 /* Controls normal or continous sample rate */
-#define NRF52_SAADC_PTR 0x062c /* Data pointer */
-#define NRF52_SAADC_MAXCNT 0x0630 /* Maximum number of 16-bit samples */
-#define NRF52_SAADC_AMOUNT 0x0634 /* Number of 16-bit samples written to buffer */
+#define NRF52_SAADC_TASKS_START_OFFSET 0x0000 /* Start the SAADCM */
+#define NRF52_SAADC_TASKS_SAMPLE_OFFSET 0x0004 /* Takes one SAADC sample */
+#define NRF52_SAADC_TASKS_STOP_OFFSET 0x0008 /* Stop the SAADC */
+#define NRF52_SAADC_TASKS_CALOFFSET_OFFSET 0x000c /* Starts offset auto-calibration */
+#define NRF52_SAADC_EVENTS_STARTED_OFFSET 0x0100 /* The SAADC has started */
+#define NRF52_SAADC_EVENTS_END_OFFSET 0x0104 /* The SAADC has filled up the result buffer */
+#define NRF52_SAADC_EVENTS_DONE_OFFSET 0x0108 /* A conversio ntask has been completed */
+#define NRF52_SAADC_EVENTS_RESDONE_OFFSET 0x010c /* Result ready for transfer to RAM */
+#define NRF52_SAADC_EVENTS_CALDONE_OFFSET 0x0110 /* Calibration is complete */
+#define NRF52_SAADC_EVENTS_STOPPED_OFFSET 0x0110 /* The SAADC has stopped */
+#define NRF52_SAADC_EVENTS_CHLIMH_OFFSET(x) (0x118 + (x + 0x8)) /* Limit high event for channel x */
+#define NRF52_SAADC_EVENTS_CHLIML_OFFSET(x) (0x11c + (x + 0x8)) /* Limit low event for channel x */
+#define NRF52_SAADC_INTEN_OFFSET 0x0300 /* Enable or disable interrupt */
+#define NRF52_SAADC_INTENSET_OFFSET 0x0304 /* Enable interrupt */
+#define NRF52_SAADC_INTENCLR_OFFSET 0x0308 /* Disable interrupt */
+#define NRF52_SAADC_STATUS_OFFSET 0x0400 /* Status */
+#define NRF52_SAADC_ENABLE_OFFSET 0x0500 /* Enable or disable SAADC */
+#define NRF52_SAADC_CHPSELP_OFFSET(x) (0x510 + (x + 0x10)) /* Input positive pin for CH[x] */
+#define NRF52_SAADC_CHPSELN_OFFSET(x) (0x514 + (x + 0x10)) /* Input negative pin for CH[x] */
+#define NRF52_SAADC_CHCONFIG_OFFSET(x) (0x518 + (x + 0x10)) /* Input configuration for CH[x] */
+#define NRF52_SAADC_CHLIMIT_OFFSET(x) (0x51c + (x + 0x10)) /* High/low limits for event monitoring of a CH[x] */
+#define NRF52_SAADC_RESOLUTION_OFFSET 0x05f0 /* Resolution configuration */
+#define NRF52_SAADC_OVERSAMPLE_OFFSET 0x05f4 /* Oversampling configuration */
+#define NRF52_SAADC_SAMPLERATE_OFFSET 0x05f8 /* Controls normal or continous sample rate */
+#define NRF52_SAADC_PTR_OFFSET 0x062c /* Data pointer */
+#define NRF52_SAADC_MAXCNT_OFFSET 0x0630 /* Maximum number of 16-bit samples */
+#define NRF52_SAADC_AMOUNT_OFFSET 0x0634 /* Number of 16-bit samples written to buffer */
/* Register Bitfield Definitions for SAADC *********************************/
@@ -84,7 +84,7 @@
#define SAADC_INT_STARTED (1 << 0) /* Bit 0: Interrupt for event STARTED */
#define SAADC_INT_END (1 << 1) /* Bit 1: Interrupt for event END */
#define SAADC_INT_DONE (1 << 2) /* Bit 2: Interrupt for event DONE */
-#define SAADC_INT_RESULTDONE (1 << 3) /* Bit 3: Interrupt for event RESULTDONE */
+#define SAADC_INT_RESDONE (1 << 3) /* Bit 3: Interrupt for event RESULTDONE */
#define SAADC_INT_CALDONE (1 << 4) /* Bit 4: Interrupt for event CALIBRATEDONE */
#define SAADC_INT_STOPPED (1 << 5) /* Bit 5: Interrupt for event STOPPED */
#define SAADC_INT_CHXLIMH(x) (1 << (x + 0x6)) /* Bit (x+6): Interrupt for event CHxLIMITH */
diff --git a/arch/arm/src/nrf52/hardware/nrf52_tim.h b/arch/arm/src/nrf52/hardware/nrf52_tim.h
new file mode 100644
index 0000000..1440df3
--- /dev/null
+++ b/arch/arm/src/nrf52/hardware/nrf52_tim.h
@@ -0,0 +1,99 @@
+/****************************************************************************
+ * arch/arm/src/nrf52/hardware/nrf52_tim.h
+ *
+ * Copyright (C) 2020 Gregory Nutt. All rights reserved.
+ * Author: Mateusz Szafoni <ra...@railab.me>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_TIM_H
+#define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_TIM_H
+
+/****************************************************************************
+ * Included Files
+ ***************************************************************************/
+
+#include <nuttx/config.h>
+#include "hardware/nrf52_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ***************************************************************************/
+
+/* Register offsets for TIM ************************************************/
+
+#define NRF52_TIM_TASKS_START_OFFSET 0x0000 /* Start Timer */
+#define NRF52_TIM_TASKS_STOP_OFFSET 0x0004 /* Stop Timer */
+#define NRF52_TIM_TASKS_COUNT_OFFSET 0x0008 /* Increment Timer*/
+#define NRF52_TIM_TASKS_CLEAR_OFFSET 0x000c /* Clear time */
+#define NRF52_TIM_TASKS_SHUTDOWN_OFFSET 0x0010 /* Shutdown Timer */
+#define NRF52_TIM_TASKS_CAPTURE_OFFSET(x) (0x0040 + ((x) * 0x04)) /* Capture Timer value to CC[x] */
+#define NRF52_TIM_EVENTS_COMPARE_OFFSET(x) (0x0140 + ((x) * 0x04)) /* Compare event on CC[x] */
+#define NRF52_TIM_SHORTS_OFFSET 0x0200 /* Shortcuts between local events and tasks */
+#define NRF52_TIM_INTENSET_OFFSET 0x0304 /* Enable interrupt */
+#define NRF52_TIM_MODE_OFFSET 0x0504 /* Timer mode selection */
+#define NRF52_TIM_BITMODE_OFFSET 0x0508 /* Configure the number of bits used by the Timer */
+#define NRF52_TIM_PRESCALER_OFFSET 0x0510 /* Timer prescaler register */
+#define NRF52_TIM_CC_OFFSET(x) (0x0540 + ((x) * 0x04)) /* Capture/Compare register x */
+
+/* Register offsets for TIM ************************************************/
+
+/* SHORTS Register */
+
+#define TIM_SHORTS_COMPARE_CLEAR(x) (1 << (x)) /* Bits 0-5: */
+#define TIM_SHORTS_COMPARE_STOP(x) (1 << (x + 0x8)) /* Bits 8-13 */
+
+/* INTENSET/INTENCLR Register */
+
+#define TIM_INT_COMPARE(x) (1 << (x + 0x16)) /* Bits 16-21 */
+
+/* MODE Register */
+
+#define TIM_MODE_SHIFT (0) /* Bits 0-1: Timer mode */
+#define TIM_MODE_MASK (0x3 << TIM_MODE_SHIFT)
+# define TIM_MODE_TIMER (0x0 << TIM_MODE_SHIFT) /* 0: Timer mode */
+# define TIM_MODE_COUNTER (0x1 << TIM_MODE_SHIFT) /* 1: Counter mode */
+# define TIM_MODE_LPCONUTER (0x2 << TIM_MODE_SHIFT) /* 2: Low Power Counter mode */
+
+/* BITMODE Register */
+
+#define TIM_BITMODE_SHIFT (0) /* Bits 0-1: Timer bit width */
+#define TIM_BITMODE_MASK (0x3 << TIM_BITMODE_SHIFT)
+# define TIM_BITMODE_16B (0x0 << TIM_BITMODE_SHIFT) /* 0: 16 bit */
+# define TIM_BITMODE_8B (0x1 << TIM_BITMODE_SHIFT) /* 1: 8 bit */
+# define TIM_BITMODE_24B (0x2 << TIM_BITMODE_SHIFT) /* 2: 24 bit */
+# define TIM_BITMODE_32B (0x3 << TIM_BITMODE_SHIFT) /* 3: 32 bit */
+
+/* PRESCALER Register */
+
+#define TIM_PRESCALER_SHIFT (0) /* Bits 0-3: Prescaler value */
+#define TIM_PRESCALER_MASK (0xf << TIM_PRESCALER_SHIFT)
+
+#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_TIM_H */
diff --git a/arch/arm/src/nrf52/hardware/nrf52_wdt.h b/arch/arm/src/nrf52/hardware/nrf52_wdt.h
index 0ad0447..c0bd241 100644
--- a/arch/arm/src/nrf52/hardware/nrf52_wdt.h
+++ b/arch/arm/src/nrf52/hardware/nrf52_wdt.h
@@ -89,15 +89,27 @@
#define NRF52_WDT_RR6 (NRF52_WDT_BASE + NRF52_WDT_RR6_OFFSET)
#define NRF52_WDT_RR7 (NRF52_WDT_BASE + NRF52_WDT_RR7_OFFSET)
-/* UART Register Bitfield Definitions **************************************************************/
+/* WDT Register Bitfield Definitions ***************************************************************/
-/* ENABLE Register */
+/* INTENSET/INTENCLR Register */
-#define NRF52_UART_ENABLE_DISABLE (0)
-#define NRF52_UART_ENABLE_ENABLE (4)
+#define WDT_INT_TIMEOUT (1 << 0) /* Bit 0: TIMEOUT */
-/* INTENSET Register */
+/* REQSTATUS[x] Register */
-#define NRF52_UART_INTENSET_RXDRDY (1 << 2)
+#define WDT_REQSTATUS_RR(x) (1 << (x)) /* Bits 0-7: Request status for RR[i] register */
+
+/* RREN[x] Register */
+
+#define WDT_RREN_RR(x) (1 << (x)) /* Bits 0-7: Enable or disable RR[i] register */
+
+/* CONFIG Register */
+
+#define WDT_CONFIG_SLEEP (1 << 0) /* Bit 0: */
+#define WDT_CONFIG_HALT (1 << 0) /* Bit 3: */
+
+/* RR[x] Register */
+
+#define WDT_RR_VALUE (0x6E524635UL) /* Fixed value, don't modify it */
#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_WDT_H */
diff --git a/arch/arm/src/nrf52/nrf52_gpio.c b/arch/arm/src/nrf52/nrf52_gpio.c
index 2ccc1ef..278524e 100644
--- a/arch/arm/src/nrf52/nrf52_gpio.c
+++ b/arch/arm/src/nrf52/nrf52_gpio.c
@@ -144,17 +144,17 @@ static inline void nrf52_gpio_mode(nrf52_pinset_t cfgset,
mode = cfgset & GPIO_MODE_MASK;
regval = getreg32(offset);
- regval &= NRF52_GPIO_CNF_PULL_MASK;
+ regval &= GPIO_CNF_PULL_MASK;
if (mode == GPIO_PULLUP)
{
- regval &= NRF52_GPIO_CNF_PULL_MASK;
- regval |= NRF52_GPIO_CNF_PULL_UP;
+ regval &= GPIO_CNF_PULL_MASK;
+ regval |= GPIO_CNF_PULL_UP;
}
else if (mode == GPIO_PULLDOWN)
{
- regval &= NRF52_GPIO_CNF_PULL_MASK;
- regval |= NRF52_GPIO_CNF_PULL_DOWN;
+ regval &= GPIO_CNF_PULL_MASK;
+ regval |= GPIO_CNF_PULL_DOWN;
}
putreg32(regval, offset);
@@ -243,7 +243,7 @@ int nrf52_gpio_unconfig(nrf52_pinset_t cfgset)
/* Configure as input and disconnect input buffer */
- putreg32(NRF52_GPIO_CNF_INPUT, offset);
+ putreg32(GPIO_CNF_INPUT, offset);
return OK;
}
diff --git a/arch/arm/src/nrf52/nrf52_rng.c b/arch/arm/src/nrf52/nrf52_rng.c
index d31a305..a7e97f8 100644
--- a/arch/arm/src/nrf52/nrf52_rng.c
+++ b/arch/arm/src/nrf52/nrf52_rng.c
@@ -91,8 +91,8 @@ static struct rng_dev_s g_rngdev;
static const struct file_operations g_rngops =
{
- .open = nrf52_rng_open, /* open */
- .read = nrf52_rng_read, /* read */
+ .open = nrf52_rng_open, /* open */
+ .read = nrf52_rng_read, /* read */
};
/****************************************************************************
@@ -104,11 +104,11 @@ static void nrf52_rng_start(void)
irqstate_t flag;
flag = enter_critical_section();
- nrf52_event_clear(NRF52_RNG_EVENT_RDY);
+ nrf52_event_clear(NRF52_RNG_EVENTS_RDY);
putreg32(1, NRF52_RNG_CONFIG);
- nrf52_interrupt_enable(NRF52_RNG_INT_SET, NRF52_RNG_INT_EVENT_RDY);
- nrf52_task_trigger(NRF52_RNG_T_START);
+ nrf52_interrupt_enable(NRF52_RNG_INTSET, RNG_INT_RDY);
+ nrf52_task_trigger(NRF52_RNG_TASKS_START);
up_enable_irq(NRF52_IRQ_RNG);
@@ -122,10 +122,10 @@ static void nrf52_rng_stop(void)
up_disable_irq(NRF52_IRQ_RNG);
- nrf52_task_trigger(NRF52_RNG_T_STOP);
- nrf52_interrupt_disable(NRF52_RNG_INT_CLR, NRF52_RNG_INT_EVENT_RDY);
+ nrf52_task_trigger(NRF52_RNG_TASKS_STOP);
+ nrf52_interrupt_disable(NRF52_RNG_INTCLR, RNG_INT_RDY);
- nrf52_event_clear(NRF52_RNG_EVENT_RDY);
+ nrf52_event_clear(NRF52_RNG_EVENTS_RDY);
leave_critical_section(flag);
}
@@ -169,9 +169,9 @@ static int nrf52_rng_irqhandler(int irq, FAR void *context, FAR void *arg)
FAR struct rng_dev_s *priv = (struct rng_dev_s *) &g_rngdev;
uint8_t *addr;
- if (getreg32(NRF52_RNG_EVENT_RDY) == NRF52_RNG_INT_EVENT_RDY)
+ if (getreg32(NRF52_RNG_EVENTS_RDY) == RNG_INT_RDY)
{
- nrf52_event_clear(NRF52_RNG_EVENT_RDY);
+ nrf52_event_clear(NRF52_RNG_EVENTS_RDY);
if (priv->rd_count < priv->buflen)
{
addr = priv->rd_buf + priv->rd_count++;
diff --git a/arch/arm/src/nrf52/nrf52_wdt.c b/arch/arm/src/nrf52/nrf52_wdt.c
index c34575d..d444cef 100644
--- a/arch/arm/src/nrf52/nrf52_wdt.c
+++ b/arch/arm/src/nrf52/nrf52_wdt.c
@@ -192,7 +192,7 @@ static void nrf52_wdt_int_enable(uint32_t int_mask)
static void nrf52_wdt_task_trigger(void)
{
- putreg32(NRF_WDT_TASK_SET, NRF52_WDT_TASKS_START);
+ putreg32(1, NRF52_WDT_TASKS_START);
}
/****************************************************************************
@@ -213,7 +213,7 @@ static void nrf52_wdt_reload_request_set(int rr_register)
{
/* Each register is 32-bit (4 bytes), then multiply by 4 to get offset */
- putreg32(NRF_WDT_RR_VALUE, NRF52_WDT_RR0 + (4 * rr_register));
+ putreg32(WDT_RR_VALUE, NRF52_WDT_RR0 + (4 * rr_register));
}
/****************************************************************************
@@ -261,8 +261,8 @@ static void nrf52_wdt_reload_value_set(uint32_t reload_value)
* Start the watchdog timer, resetting the time to the current timeout,
*
* Input Parameters:
- * lower - A pointer the publicly visible representation of the "lower-half"
- * driver state structure.
+ * lower - A pointer the publicly visible representation of the
+ * "lower-half" driver state structure.
*
* Returned Values:
* Zero on success; a negated errno value on failure.
@@ -285,7 +285,7 @@ static int nrf52_start(FAR struct watchdog_lowerhalf_s *lower)
flags = enter_critical_section();
priv->lastreset = clock_systimer();
priv->started = true;
- nrf52_wdt_int_enable(NRF_WDT_INT_TIMEOUT_MASK);
+ nrf52_wdt_int_enable(WDT_INT_TIMEOUT);
nrf52_wdt_task_trigger();
leave_critical_section(flags);
}
@@ -300,8 +300,8 @@ static int nrf52_start(FAR struct watchdog_lowerhalf_s *lower)
* Stop the watchdog timer
*
* Input Parameters:
- * lower - A pointer the publicly visible representation of the "lower-half"
- * driver state structure.
+ * lower - A pointer the publicly visible representation of the
+ * "lower-half" driver state structure.
*
* Returned Values:
* Zero on success; a negated errno value on failure.
@@ -325,8 +325,8 @@ static int nrf52_stop(FAR struct watchdog_lowerhalf_s *lower)
* the watchdog timer or "petting the dog".
*
* Input Parameters:
- * lower - A pointer the publicly visible representation of the "lower-half"
- * driver state structure.
+ * lower - A pointer the publicly visible representation of the
+ * "lower-half" driver state structure.
*
* Returned Values:
* Zero on success; a negated errno value on failure.
@@ -460,7 +460,8 @@ static int nrf52_settimeout(FAR struct watchdog_lowerhalf_s *lower,
up_enable_irq(NRF52_IRQ_WDT);
- wdinfo(" mode=%d priority=%d\n", WDT_CONFIG_MODE, WDT_CONFIG_IRQ_PRIORITY);
+ wdinfo(" mode=%d priority=%d\n", WDT_CONFIG_MODE,
+ WDT_CONFIG_IRQ_PRIORITY);
return OK;
}
@@ -503,8 +504,8 @@ int nrf52_wdt_initialize(FAR const char *devpath, int16_t mode_sleep,
priv->ops = &g_wdtops;
priv->started = false;
- priv->mode = (mode_halt << WDT_CONFIG_HALT_POS) |
- (mode_sleep << WDT_CONFIG_SLEEP_POS);
+ priv->mode = (mode_halt << WDT_CONFIG_HALT) |
+ (mode_sleep << WDT_CONFIG_SLEEP);
#if 0
/* Request LSECLK firstly */
diff --git a/arch/arm/src/nrf52/nrf52_wdt.h b/arch/arm/src/nrf52/nrf52_wdt.h
index 3c95087..00afbda 100644
--- a/arch/arm/src/nrf52/nrf52_wdt.h
+++ b/arch/arm/src/nrf52/nrf52_wdt.h
@@ -45,17 +45,17 @@
#ifdef CONFIG_WATCHDOG
/****************************************************************************
- * Pre-processor Definitions
+ * Public Types
****************************************************************************/
-#define NRF_WDT_RR_VALUE 0x6E524635UL /* Fixed value, don't modify it */
-#define NRF_WDT_TASK_SET 1
-#define WDT_CONFIG_HALT_POS 3
-#define WDT_CONFIG_SLEEP_POS 0
-#define NRF_WDT_INT_TIMEOUT_MASK 1
+enum wdt_behaviour_e
+{
+ WDG_PAUSE = 0,
+ WDG_RUN = 1
+};
/****************************************************************************
- * Public Types
+ * Public Functions
****************************************************************************/
#undef EXTERN
@@ -67,16 +67,6 @@ extern "C"
#define EXTERN extern
#endif
-enum wdt_behaviour_e
-{
- WDG_PAUSE = 0,
- WDG_RUN = 1
-};
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
/****************************************************************************
* Name: nrf52_wdt_initialize
*
[incubator-nuttx] 02/06: fix warning: passing argument 4 of
up_x11initialize from incompatible pointer type
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch pr105
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit ad3acf63ad384f94f71ec36ed54ba266d4c2fb1f
Author: chao.an <an...@xiaomi.com>
AuthorDate: Mon Dec 16 19:50:48 2019 +0800
fix warning: passing argument 4 of up_x11initialize from incompatible pointer type
Change-Id: I8fbb506d104dd6a0c41c86ca977e28097694910b
Signed-off-by: chao.an <an...@xiaomi.com>
---
arch/sim/src/sim/up_internal.h | 2 +-
arch/sim/src/sim/up_x11framebuffer.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/sim/src/sim/up_internal.h b/arch/sim/src/sim/up_internal.h
index 0a69ca9..f40de35 100644
--- a/arch/sim/src/sim/up_internal.h
+++ b/arch/sim/src/sim/up_internal.h
@@ -306,7 +306,7 @@ unsigned long up_getwalltime(void);
#ifdef CONFIG_SIM_X11FB
int up_x11initialize(unsigned short width, unsigned short height,
- void **fbmem, unsigned int *fblen, unsigned char *bpp,
+ void **fbmem, size_t *fblen, unsigned char *bpp,
unsigned short *stride);
#ifdef CONFIG_FB_CMAP
int up_x11cmap(unsigned short first, unsigned short len,
diff --git a/arch/sim/src/sim/up_x11framebuffer.c b/arch/sim/src/sim/up_x11framebuffer.c
index f3634ac..94cd922 100644
--- a/arch/sim/src/sim/up_x11framebuffer.c
+++ b/arch/sim/src/sim/up_x11framebuffer.c
@@ -359,7 +359,7 @@ shmerror:
****************************************************************************/
int up_x11initialize(unsigned short width, unsigned short height,
- void **fbmem, unsigned int *fblen, unsigned char *bpp,
+ void **fbmem, size_t *fblen, unsigned char *bpp,
unsigned short *stride)
{
XWindowAttributes windowAttributes;
[incubator-nuttx] 01/06: arch/arm/include/cxd56xx/audio.h: Fix
minor typos
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch pr105
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 07489a1a866cf90960034c620842fe3d6f2517ba
Author: Nathan Hartman <ha...@gmail.com>
AuthorDate: Tue Jan 14 18:51:09 2020 -0500
arch/arm/include/cxd56xx/audio.h: Fix minor typos
---
arch/arm/include/cxd56xx/audio.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/cxd56xx/audio.h b/arch/arm/include/cxd56xx/audio.h
index ad2864e..edcd824 100644
--- a/arch/arm/include/cxd56xx/audio.h
+++ b/arch/arm/include/cxd56xx/audio.h
@@ -38,7 +38,7 @@
#ifndef __ARCH_ARM_INCLUDE_CXD56XX_AUDIO_H
#define __ARCH_ARM_INCLUDE_CXD56XX_AUDIO_H
-/* API Documents creater with Doxgen */
+/* API Documents created with Doxygen */
/* cxd56_audio_api Audio Driver API
*
[incubator-nuttx] 03/06: boards: spresense: Update README.txt
regarding SMP
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch pr105
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 72cff79dcc639cfce02b566f49a9905f71af6cc4
Author: Masayuki Ishikawa <Ma...@jp.sony.com>
AuthorDate: Wed Jan 15 17:08:09 2020 +0900
boards: spresense: Update README.txt regarding SMP
Signed-off-by: Masayuki Ishikawa <Ma...@jp.sony.com>
---
boards/arm/cxd56xx/spresense/README.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/boards/arm/cxd56xx/spresense/README.txt b/boards/arm/cxd56xx/spresense/README.txt
index cb94798..738c5bf 100644
--- a/boards/arm/cxd56xx/spresense/README.txt
+++ b/boards/arm/cxd56xx/spresense/README.txt
@@ -25,7 +25,7 @@ Configuration sub-directories
smp
This is a configuration to run Spresense in SMP mode. To use this
- configuration, new boot loader which will be released later must be used.
+ configuration, bootloader for Spresense SDK 1.5.0 or later must be intalled.
wifi