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Posted to commits@nuttx.apache.org by "pkarashchenko (via GitHub)" <gi...@apache.org> on 2023/09/06 14:00:58 UTC
[GitHub] [nuttx] pkarashchenko opened a new pull request, #10491: arch/xtensa/esp32s3: add UART RS485 support
pkarashchenko opened a new pull request, #10491:
URL: https://github.com/apache/nuttx/pull/10491
## Summary
This commit adds support of RS485 support in ESP32-S3 serial driver
## Impact
Improve ESP32-S3 driver layer
## Testing
Tested using ESP32-S3 based board with UART1 connected to UART2 of the same board with MAX486 based TTL to RS485 converter
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[GitHub] [nuttx] xiaoxiang781216 merged pull request #10491: arch/xtensa/esp32s3: add UART RS485 support
Posted by "xiaoxiang781216 (via GitHub)" <gi...@apache.org>.
xiaoxiang781216 merged PR #10491:
URL: https://github.com/apache/nuttx/pull/10491
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[GitHub] [nuttx] acassis commented on a diff in pull request #10491: arch/xtensa/esp32s3: add UART RS485 support
Posted by "acassis (via GitHub)" <gi...@apache.org>.
acassis commented on code in PR #10491:
URL: https://github.com/apache/nuttx/pull/10491#discussion_r1317731913
##########
arch/xtensa/src/esp32s3/Kconfig:
##########
@@ -1026,26 +1076,51 @@ endif # ESP32S3_UART1
if ESP32S3_UART2
+config ESP32S3_UART2_RS485
+ bool "RS-485 on UART2"
+ default n
+ ---help---
+ Enable RS-485 interface on UART2. Your board config will have to
+ provide GPIO_UART2_RS485_DIR pin definition.
+
+config ESP32S3_UART2_RS485_DIR_PIN
+ int "UART2 RS-485 DIR pin"
+ default 27
+ range 0 48
+ depends on ESP32S3_UART2_RS485
+ ---help---
+ DIR pin for RS-485 on UART2. This pin will control the RS485 enable
+ TX of the RS485 transceiver.
+
+config ESP32S3_UART2_RS485_DIR_POLARITY
+ int "UART2 RS-485 DIR pin polarity"
+ default 1
+ range 0 1
+ depends on ESP32S3_UART2_RS485
+ ---help---
+ Polarity of DIR pin for RS-485 on UART2. Set to state on DIR pin which
+ enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
config ESP32S3_UART2_TXPIN
int "UART2 Tx Pin"
- default 17
+ default 21
range 0 48
config ESP32S3_UART2_RXPIN
int "UART2 Rx Pin"
- default 16
+ default 22
range 0 48
config ESP32S3_UART2_RTSPIN
int "UART2 RTS Pin"
depends on SERIAL_IFLOWCONTROL
- default 35
+ default 23
range 0 48
config ESP32S3_UART2_CTSPIN
int "UART2 CTS Pin"
depends on SERIAL_OFLOWCONTROL
- default 36
+ default 24
Review Comment:
Why to change the default pins?
BTW, for UART0 and UART1 we have "native" pins (pins that don't pass by IO Matrix, but are select-able over IO MUX), but for UART2 we don't. So any pin used is fine. I suggest to follow the ESP-IDF definition in this case
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[GitHub] [nuttx] pkarashchenko commented on a diff in pull request #10491: arch/xtensa/esp32s3: add UART RS485 support
Posted by "pkarashchenko (via GitHub)" <gi...@apache.org>.
pkarashchenko commented on code in PR #10491:
URL: https://github.com/apache/nuttx/pull/10491#discussion_r1317337880
##########
arch/xtensa/src/esp32s3/esp32s3_serial.c:
##########
@@ -445,9 +458,18 @@ static int esp32s3_setup(struct uart_dev_s *dev)
}
#endif
- /* No Tx idle interval */
+#ifdef HAVE_RS485
+ if (priv->rs485_dir_gpio != 0)
+ {
+ esp32s3_lowputc_set_tx_idle_time(priv, 1);
Review Comment:
As an alternative we can go with value 1 for both RS485 and RS323 cases and remove additional if
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[GitHub] [nuttx] pkarashchenko commented on a diff in pull request #10491: arch/xtensa/esp32s3: add UART RS485 support
Posted by "pkarashchenko (via GitHub)" <gi...@apache.org>.
pkarashchenko commented on code in PR #10491:
URL: https://github.com/apache/nuttx/pull/10491#discussion_r1321617256
##########
arch/xtensa/src/esp32s3/Kconfig:
##########
@@ -1026,26 +1076,51 @@ endif # ESP32S3_UART1
if ESP32S3_UART2
+config ESP32S3_UART2_RS485
+ bool "RS-485 on UART2"
+ default n
+ ---help---
+ Enable RS-485 interface on UART2. Your board config will have to
+ provide GPIO_UART2_RS485_DIR pin definition.
+
+config ESP32S3_UART2_RS485_DIR_PIN
+ int "UART2 RS-485 DIR pin"
+ default 27
+ range 0 48
+ depends on ESP32S3_UART2_RS485
+ ---help---
+ DIR pin for RS-485 on UART2. This pin will control the RS485 enable
+ TX of the RS485 transceiver.
+
+config ESP32S3_UART2_RS485_DIR_POLARITY
+ int "UART2 RS-485 DIR pin polarity"
+ default 1
+ range 0 1
+ depends on ESP32S3_UART2_RS485
+ ---help---
+ Polarity of DIR pin for RS-485 on UART2. Set to state on DIR pin which
+ enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
config ESP32S3_UART2_TXPIN
int "UART2 Tx Pin"
- default 17
+ default 21
range 0 48
config ESP32S3_UART2_RXPIN
int "UART2 Rx Pin"
- default 16
+ default 22
range 0 48
config ESP32S3_UART2_RTSPIN
int "UART2 RTS Pin"
depends on SERIAL_IFLOWCONTROL
- default 35
+ default 23
range 0 48
config ESP32S3_UART2_CTSPIN
int "UART2 CTS Pin"
depends on SERIAL_OFLOWCONTROL
- default 36
+ default 24
Review Comment:
This is a slippery path as I see that default pins for UART control signals are the same as pins used for USB (pins 19/20), but unconditionally hard coded.
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[GitHub] [nuttx] pkarashchenko commented on a diff in pull request #10491: arch/xtensa/esp32s3: add UART RS485 support
Posted by "pkarashchenko (via GitHub)" <gi...@apache.org>.
pkarashchenko commented on code in PR #10491:
URL: https://github.com/apache/nuttx/pull/10491#discussion_r1317736067
##########
arch/xtensa/src/esp32s3/Kconfig:
##########
@@ -1026,26 +1076,51 @@ endif # ESP32S3_UART1
if ESP32S3_UART2
+config ESP32S3_UART2_RS485
+ bool "RS-485 on UART2"
+ default n
+ ---help---
+ Enable RS-485 interface on UART2. Your board config will have to
+ provide GPIO_UART2_RS485_DIR pin definition.
+
+config ESP32S3_UART2_RS485_DIR_PIN
+ int "UART2 RS-485 DIR pin"
+ default 27
+ range 0 48
+ depends on ESP32S3_UART2_RS485
+ ---help---
+ DIR pin for RS-485 on UART2. This pin will control the RS485 enable
+ TX of the RS485 transceiver.
+
+config ESP32S3_UART2_RS485_DIR_POLARITY
+ int "UART2 RS-485 DIR pin polarity"
+ default 1
+ range 0 1
+ depends on ESP32S3_UART2_RS485
+ ---help---
+ Polarity of DIR pin for RS-485 on UART2. Set to state on DIR pin which
+ enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
config ESP32S3_UART2_TXPIN
int "UART2 Tx Pin"
- default 17
+ default 21
range 0 48
config ESP32S3_UART2_RXPIN
int "UART2 Rx Pin"
- default 16
+ default 22
range 0 48
config ESP32S3_UART2_RTSPIN
int "UART2 RTS Pin"
depends on SERIAL_IFLOWCONTROL
- default 35
+ default 23
range 0 48
config ESP32S3_UART2_CTSPIN
int "UART2 CTS Pin"
depends on SERIAL_OFLOWCONTROL
- default 36
+ default 24
Review Comment:
Could you please advice the PIN numbers?
The reason of change here is to change `ESP32S3_UART2_TXPIN` and `ESP32S3_UART2_RXPIN` definition to avoid conflict with same pins for UART1.
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[GitHub] [nuttx] tmedicci commented on a diff in pull request #10491: arch/xtensa/esp32s3: add UART RS485 support
Posted by "tmedicci (via GitHub)" <gi...@apache.org>.
tmedicci commented on code in PR #10491:
URL: https://github.com/apache/nuttx/pull/10491#discussion_r1321582680
##########
arch/xtensa/src/esp32s3/Kconfig:
##########
@@ -1026,26 +1076,51 @@ endif # ESP32S3_UART1
if ESP32S3_UART2
+config ESP32S3_UART2_RS485
+ bool "RS-485 on UART2"
+ default n
+ ---help---
+ Enable RS-485 interface on UART2. Your board config will have to
+ provide GPIO_UART2_RS485_DIR pin definition.
+
+config ESP32S3_UART2_RS485_DIR_PIN
+ int "UART2 RS-485 DIR pin"
+ default 27
+ range 0 48
+ depends on ESP32S3_UART2_RS485
+ ---help---
+ DIR pin for RS-485 on UART2. This pin will control the RS485 enable
+ TX of the RS485 transceiver.
+
+config ESP32S3_UART2_RS485_DIR_POLARITY
+ int "UART2 RS-485 DIR pin polarity"
+ default 1
+ range 0 1
+ depends on ESP32S3_UART2_RS485
+ ---help---
+ Polarity of DIR pin for RS-485 on UART2. Set to state on DIR pin which
+ enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
config ESP32S3_UART2_TXPIN
int "UART2 Tx Pin"
- default 17
+ default 21
range 0 48
config ESP32S3_UART2_RXPIN
int "UART2 Rx Pin"
- default 16
+ default 22
range 0 48
config ESP32S3_UART2_RTSPIN
int "UART2 RTS Pin"
depends on SERIAL_IFLOWCONTROL
- default 35
+ default 23
range 0 48
config ESP32S3_UART2_CTSPIN
int "UART2 CTS Pin"
depends on SERIAL_OFLOWCONTROL
- default 36
+ default 24
Review Comment:
@acassis , ESP-IDF doesn't define default pins for UART2 because it's only accessible through the GPIO matrix (so, "it doesn't matter", in fact): https://github.com/espressif/esp-idf/blob/release/v5.1/components/soc/esp32s3/include/soc/uart_pins.h#L33
I think we only need to ensure that we're not using the IO Mux-enabled pins for UART0 and UART1 on UART2.
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