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Posted to commits@nuttx.apache.org by ac...@apache.org on 2021/11/09 12:23:05 UTC
[incubator-nuttx] branch master updated (1f37158 -> 00befc4)
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git.
from 1f37158 board: Run ./tools/refresh.sh --silent all
new 17cf3ed arch/risc-v/esp32c3: Add register definitions for the USB Serial/JTAG controller.
new ebd9496 arch/riscv/esp32c3: Add the USB-Serial Driver.
new 23039c9 esp32c3/Make.defs: Alawys build esp32c3_serial.c
new 044508c boards/esp32c3-devkit: Add a defconfig for the USB CDC Console.
new 00befc4 Documentation/esp32c3: Document the CDC console defconfig.
The 5 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
.../risc-v/esp32c3/boards/esp32c3-devkit/index.rst | 14 +
Documentation/platforms/risc-v/esp32c3/index.rst | 7 +-
arch/risc-v/src/esp32c3/Kconfig | 6 +
arch/risc-v/src/esp32c3/Make.defs | 6 +-
arch/risc-v/src/esp32c3/esp32c3_config.h | 8 +
arch/risc-v/src/esp32c3/esp32c3_lowputc.c | 7 +-
arch/risc-v/src/esp32c3/esp32c3_serial.c | 50 +-
arch/risc-v/src/esp32c3/esp32c3_usbserial.c | 462 ++++++++
.../src/esp32c3/esp32c3_usbserial.h} | 29 +-
arch/risc-v/src/esp32c3/hardware/esp32c3_soc.h | 1 +
.../src/esp32c3/hardware/esp32c3_usb_serial_jtag.h | 1233 ++++++++++++++++++++
.../configs/{nsh => usbconsole}/defconfig | 5 +-
12 files changed, 1797 insertions(+), 31 deletions(-)
create mode 100644 arch/risc-v/src/esp32c3/esp32c3_usbserial.c
copy arch/{arm/src/am335x/chip.h => risc-v/src/esp32c3/esp32c3_usbserial.h} (78%)
create mode 100644 arch/risc-v/src/esp32c3/hardware/esp32c3_usb_serial_jtag.h
copy boards/risc-v/esp32c3/esp32c3-devkit/configs/{nsh => usbconsole}/defconfig (91%)
[incubator-nuttx] 01/05: arch/risc-v/esp32c3: Add register
definitions for the USB Serial/JTAG controller.
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 17cf3edf469776593b8f84f99ea7e2fb002a0701
Author: Abdelatif Guettouche <ab...@espressif.com>
AuthorDate: Mon Oct 18 14:53:30 2021 +0200
arch/risc-v/esp32c3: Add register definitions for the USB Serial/JTAG
controller.
Signed-off-by: Abdelatif Guettouche <ab...@espressif.com>
---
.../src/esp32c3/hardware/esp32c3_usb_serial_jtag.h | 1233 ++++++++++++++++++++
1 file changed, 1233 insertions(+)
diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_usb_serial_jtag.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_usb_serial_jtag.h
new file mode 100644
index 0000000..d1dcba4
--- /dev/null
+++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_usb_serial_jtag.h
@@ -0,0 +1,1233 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c3/hardware/esp32c3_usb_serial_jtag.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_USB_SERIAL_JTAG_H
+#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_USB_SERIAL_JTAG_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "esp32c3_soc.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/** Configuration Registers */
+
+/** USB_SERIAL_JTAG_EP1_REG register
+ * USB_SERIAL_JTAG_EP1_REG.
+ */
+
+#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0)
+
+/* USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [8:0]; default: 0;
+ * Write and read byte data to/from UART Tx/Rx FIFO through this field.
+ * When USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set then user can write
+ * data (up to 64 bytes) into UART Tx FIFO. When
+ * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user can check
+ * USB_SERIAL_JTAG_OUT_EP1_WR_ADDR and USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to
+ * know how many data is received, then read that amount of data from UART
+ * Rx
+ * FIFO.
+ */
+
+#define USB_SERIAL_JTAG_RDWR_BYTE 0x000000ff
+#define USB_SERIAL_JTAG_RDWR_BYTE_M (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S)
+#define USB_SERIAL_JTAG_RDWR_BYTE_V 0x000000ff
+#define USB_SERIAL_JTAG_RDWR_BYTE_S 0
+
+/** USB_SERIAL_JTAG_CONF0_REG register
+ * USB_SERIAL_JTAG_CONF0_REG.
+ */
+
+#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18)
+
+/* USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0;
+ * Select internal/external PHY. 1’b0: internal PHY, 1’b1: external
+ * PHY
+ */
+
+#define USB_SERIAL_JTAG_PHY_SEL (BIT(0))
+#define USB_SERIAL_JTAG_PHY_SEL_M (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S)
+#define USB_SERIAL_JTAG_PHY_SEL_V 0x00000001
+#define USB_SERIAL_JTAG_PHY_SEL_S 0
+
+/* USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0;
+ * Enable software control USB D+ D-
+ * exchange
+ */
+
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE (BIT(1))
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S)
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V 0x00000001
+#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S 1
+
+/* USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0;
+ * USB D+ D-
+ * exchange
+ */
+
+#define USB_SERIAL_JTAG_EXCHG_PINS (BIT(2))
+#define USB_SERIAL_JTAG_EXCHG_PINS_M (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S)
+#define USB_SERIAL_JTAG_EXCHG_PINS_V 0x00000001
+#define USB_SERIAL_JTAG_EXCHG_PINS_S 2
+
+/* USB_SERIAL_JTAG_VREFL : R/W; bitpos: [5:3]; default: 0;
+ * Control single-end input high threshold. 1.76V to 2V, step
+ * 80mV
+ */
+
+#define USB_SERIAL_JTAG_VREFL 0x00000003
+#define USB_SERIAL_JTAG_VREFL_M (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S)
+#define USB_SERIAL_JTAG_VREFL_V 0x00000003
+#define USB_SERIAL_JTAG_VREFL_S 3
+
+/* USB_SERIAL_JTAG_VREFH : R/W; bitpos: [7:5]; default: 0;
+ * Control single-end input low threshold. 0.8V to 1.04V, step
+ * 80mV
+ */
+
+#define USB_SERIAL_JTAG_VREFH 0x00000003
+#define USB_SERIAL_JTAG_VREFH_M (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S)
+#define USB_SERIAL_JTAG_VREFH_V 0x00000003
+#define USB_SERIAL_JTAG_VREFH_S 5
+
+/* USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0;
+ * Enable software control input
+ * threshold
+ */
+
+#define USB_SERIAL_JTAG_VREF_OVERRIDE (BIT(7))
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_M (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S)
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_V 0x00000001
+#define USB_SERIAL_JTAG_VREF_OVERRIDE_S 7
+
+/* USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0;
+ * Enable software control USB D+ D- pullup
+ * pulldown
+ */
+
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE (BIT(8))
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S)
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V 0x00000001
+#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S 8
+
+/* USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1;
+ * Control USB D+ pull
+ * up.
+ */
+
+#define USB_SERIAL_JTAG_DP_PULLUP (BIT(9))
+#define USB_SERIAL_JTAG_DP_PULLUP_M (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S)
+#define USB_SERIAL_JTAG_DP_PULLUP_V 0x00000001
+#define USB_SERIAL_JTAG_DP_PULLUP_S 9
+
+/* USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0;
+ * Control USB D+ pull
+ * down.
+ */
+
+#define USB_SERIAL_JTAG_DP_PULLDOWN (BIT(10))
+#define USB_SERIAL_JTAG_DP_PULLDOWN_M (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S)
+#define USB_SERIAL_JTAG_DP_PULLDOWN_V 0x00000001
+#define USB_SERIAL_JTAG_DP_PULLDOWN_S 10
+
+/* USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0;
+ * Control USB D- pull
+ * up.
+ */
+
+#define USB_SERIAL_JTAG_DM_PULLUP (BIT(11))
+#define USB_SERIAL_JTAG_DM_PULLUP_M (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S)
+#define USB_SERIAL_JTAG_DM_PULLUP_V 0x00000001
+#define USB_SERIAL_JTAG_DM_PULLUP_S 11
+
+/* USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0;
+ * Control USB D- pull
+ * down.
+ */
+
+#define USB_SERIAL_JTAG_DM_PULLDOWN (BIT(12))
+#define USB_SERIAL_JTAG_DM_PULLDOWN_M (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S)
+#define USB_SERIAL_JTAG_DM_PULLDOWN_V 0x00000001
+#define USB_SERIAL_JTAG_DM_PULLDOWN_S 12
+
+/* USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0;
+ * Control pull up
+ * value.
+ */
+
+#define USB_SERIAL_JTAG_PULLUP_VALUE (BIT(13))
+#define USB_SERIAL_JTAG_PULLUP_VALUE_M (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S)
+#define USB_SERIAL_JTAG_PULLUP_VALUE_V 0x00000001
+#define USB_SERIAL_JTAG_PULLUP_VALUE_S 13
+
+/* USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1;
+ * Enable USB pad
+ * function.
+ */
+
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE (BIT(14))
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S)
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V 0x00000001
+#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S 14
+
+/** USB_SERIAL_JTAG_TEST_REG register
+ * USB_SERIAL_JTAG_TEST_REG.
+ */
+
+#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c)
+
+/* USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
+ * Enable test of the USB
+ * pad
+ */
+
+#define USB_SERIAL_JTAG_TEST_ENABLE (BIT(0))
+#define USB_SERIAL_JTAG_TEST_ENABLE_M (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S)
+#define USB_SERIAL_JTAG_TEST_ENABLE_V 0x00000001
+#define USB_SERIAL_JTAG_TEST_ENABLE_S 0
+
+/* USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0;
+ * USB pad oen in
+ * test
+ */
+
+#define USB_SERIAL_JTAG_TEST_USB_OE (BIT(1))
+#define USB_SERIAL_JTAG_TEST_USB_OE_M (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S)
+#define USB_SERIAL_JTAG_TEST_USB_OE_V 0x00000001
+#define USB_SERIAL_JTAG_TEST_USB_OE_S 1
+
+/* USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0;
+ * USB D+ tx value in
+ * test
+ */
+
+#define USB_SERIAL_JTAG_TEST_TX_DP (BIT(2))
+#define USB_SERIAL_JTAG_TEST_TX_DP_M (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S)
+#define USB_SERIAL_JTAG_TEST_TX_DP_V 0x00000001
+#define USB_SERIAL_JTAG_TEST_TX_DP_S 2
+
+/* USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0;
+ * USB D- tx value in
+ * test
+ */
+
+#define USB_SERIAL_JTAG_TEST_TX_DM (BIT(3))
+#define USB_SERIAL_JTAG_TEST_TX_DM_M (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S)
+#define USB_SERIAL_JTAG_TEST_TX_DM_V 0x00000001
+#define USB_SERIAL_JTAG_TEST_TX_DM_S 3
+
+/** USB_SERIAL_JTAG_MISC_CONF_REG register
+ * USB_SERIAL_JTAG_MISC_CONF_REG.
+ */
+
+#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44)
+
+/* USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0;
+ * 1'h1: Force clock on for register. 1'h0: Support clock only when
+ * application writes
+ * registers.
+ */
+
+#define USB_SERIAL_JTAG_CLK_EN (BIT(0))
+#define USB_SERIAL_JTAG_CLK_EN_M (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S)
+#define USB_SERIAL_JTAG_CLK_EN_V 0x00000001
+#define USB_SERIAL_JTAG_CLK_EN_S 0
+
+/** USB_SERIAL_JTAG_MEM_CONF_REG register
+ * USB_SERIAL_JTAG_MEM_CONF_REG.
+ */
+
+#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48)
+
+/* USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0;
+ * 1: power down usb
+ * memory.
+ */
+
+#define USB_SERIAL_JTAG_USB_MEM_PD (BIT(0))
+#define USB_SERIAL_JTAG_USB_MEM_PD_M (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S)
+#define USB_SERIAL_JTAG_USB_MEM_PD_V 0x00000001
+#define USB_SERIAL_JTAG_USB_MEM_PD_S 0
+
+/* USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1;
+ * 1: Force clock on for usb
+ * memory.
+ */
+
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN (BIT(1))
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S)
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V 0x00000001
+#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S 1
+
+/** Status Registers */
+
+/** USB_SERIAL_JTAG_EP1_CONF_REG register
+ * USB_SERIAL_JTAG_EP1_CONF_REG.
+ */
+
+#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4)
+
+/* USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0;
+ * Set this bit to indicate writing byte data to UART Tx FIFO is done.
+ * This bit then stays 0 until data in UART Tx FIFO is read by the USB
+ * Host.
+ */
+
+#define USB_SERIAL_JTAG_WR_DONE (BIT(0))
+#define USB_SERIAL_JTAG_WR_DONE_M (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S)
+#define USB_SERIAL_JTAG_WR_DONE_V 0x00000001
+#define USB_SERIAL_JTAG_WR_DONE_S 0
+
+/* USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1;
+ * 1'b1: Indicate UART Tx FIFO is not full and data can be written into
+ * in. After writing USB_SERIAL_JTAG_WR_DONE, this will be 1’b0 until the
+ * data is sent to the USB
+ * Host.
+ */
+
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE (BIT(1))
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V 0x00000001
+#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S 1
+
+/* USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0;
+ * 1'b1: Indicate there is data in UART Rx
+ * FIFO.
+ */
+
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x00000001
+#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2
+
+/** USB_SERIAL_JTAG_JFIFO_ST_REG register
+ * USB_SERIAL_JTAG_JFIFO_ST_REG.
+ */
+
+#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20)
+/* USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [2:0]; default: 0;
+ * JTAG in fifo
+ * counter.
+ */
+
+#define USB_SERIAL_JTAG_IN_FIFO_CNT 0x00000003
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_M (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S)
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_V 0x00000003
+#define USB_SERIAL_JTAG_IN_FIFO_CNT_S 0
+
+/* USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1;
+ * 1: JTAG in fifo is
+ * empty.
+ */
+
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY (BIT(2))
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S)
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V 0x00000001
+#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S 2
+
+/* USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0;
+ * 1: JTAG in fifo is
+ * full.
+ */
+
+#define USB_SERIAL_JTAG_IN_FIFO_FULL (BIT(3))
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_M (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S)
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_V 0x00000001
+#define USB_SERIAL_JTAG_IN_FIFO_FULL_S 3
+
+/* USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [6:4]; default: 0;
+ * JTAT out fifo
+ * counter.
+ */
+
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT 0x00000003
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V 0x00000003
+#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S 4
+
+/* USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1;
+ * 1: JTAG out fifo is
+ * empty.
+ */
+
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY (BIT(6))
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V 0x00000001
+#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S 6
+
+/* USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0;
+ * 1: JTAG out fifo is
+ * full.
+ */
+
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL (BIT(7))
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V 0x00000001
+#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S 7
+
+/* USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0;
+ * Write 1 to reset JTAG in
+ * fifo.
+ */
+
+#define USB_SERIAL_JTAG_IN_FIFO_RESET (BIT(8))
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_M (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S)
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_V 0x00000001
+#define USB_SERIAL_JTAG_IN_FIFO_RESET_S 8
+
+/* USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0;
+ * Write 1 to reset JTAG out
+ * fifo.
+ */
+
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET (BIT(9))
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S)
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V 0x00000001
+#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S 9
+
+/** USB_SERIAL_JTAG_FRAM_NUM_REG register
+ * USB_SERIAL_JTAG_FRAM_NUM_REG.
+ */
+
+#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24)
+
+/* USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [11:0]; default: 0;
+ * Frame index of received SOF
+ * frame.
+ */
+
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX 0x000007ff
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S)
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x000007ff
+#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S 0
+
+/** USB_SERIAL_JTAG_IN_EP0_ST_REG register
+ * USB_SERIAL_JTAG_IN_EP0_ST_REG.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28)
+
+/* USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [2:0]; default: 1;
+ * State of IN Endpoint 0.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP0_STATE 0x00000003
+#define USB_SERIAL_JTAG_IN_EP0_STATE_M (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP0_STATE_V 0x00000003
+#define USB_SERIAL_JTAG_IN_EP0_STATE_S 0
+
+/* USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [9:2]; default: 0;
+ * Write data address of IN endpoint 0.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S 2
+
+/* USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [16:9]; default: 0;
+ * Read data address of IN endpoint 0.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S 9
+
+/** USB_SERIAL_JTAG_IN_EP1_ST_REG register
+ * USB_SERIAL_JTAG_IN_EP1_ST_REG.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c)
+
+/* USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [2:0]; default: 1;
+ * State of IN Endpoint 1.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP1_STATE 0x00000003
+#define USB_SERIAL_JTAG_IN_EP1_STATE_M (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP1_STATE_V 0x00000003
+#define USB_SERIAL_JTAG_IN_EP1_STATE_S 0
+
+/* USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [9:2]; default: 0;
+ * Write data address of IN endpoint 1.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S 2
+
+/* USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [16:9]; default: 0;
+ * Read data address of IN endpoint
+ * 1.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S 9
+
+/** USB_SERIAL_JTAG_IN_EP2_ST_REG register
+ * USB_SERIAL_JTAG_IN_EP2_ST_REG.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30)
+
+/* USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [2:0]; default: 1;
+ * State of IN Endpoint
+ * 2.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP2_STATE 0x00000003
+#define USB_SERIAL_JTAG_IN_EP2_STATE_M (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP2_STATE_V 0x00000003
+#define USB_SERIAL_JTAG_IN_EP2_STATE_S 0
+
+/* USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [9:2]; default: 0;
+ * Write data address of IN endpoint
+ * 2.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S 2
+
+/* USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [16:9]; default: 0;
+ * Read data address of IN endpoint
+ * 2.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S 9
+
+/** USB_SERIAL_JTAG_IN_EP3_ST_REG register
+ * USB_SERIAL_JTAG_IN_EP3_ST_REG.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34)
+
+/* USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [2:0]; default: 1;
+ * State of IN Endpoint
+ * 3.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP3_STATE 0x00000003
+#define USB_SERIAL_JTAG_IN_EP3_STATE_M (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S)
+#define USB_SERIAL_JTAG_IN_EP3_STATE_V 0x00000003
+#define USB_SERIAL_JTAG_IN_EP3_STATE_S 0
+
+/* USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [9:2]; default: 0;
+ * Write data address of IN endpoint
+ * 3.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S 2
+
+/* USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [16:9]; default: 0;
+ * Read data address of IN endpoint
+ * 3.
+ */
+
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S)
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V 0x0000007f
+#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S 9
+
+/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register
+ * USB_SERIAL_JTAG_OUT_EP0_ST_REG.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38)
+
+/* USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [2:0]; default: 0;
+ * State of OUT Endpoint
+ * 0.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP0_STATE 0x00000003
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_M (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_V 0x00000003
+#define USB_SERIAL_JTAG_OUT_EP0_STATE_S 0
+
+/* USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [9:2]; default: 0;
+ * Write data address of OUT endpoint 0. When
+ * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are
+ * USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT
+ * EP0.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR 0x0000007f
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V 0x0000007f
+#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S 2
+
+/* USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [16:9]; default: 0;
+ * Read data address of OUT endpoint
+ * 0.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR 0x0000007f
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V 0x0000007f
+#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S 9
+
+/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register
+ * USB_SERIAL_JTAG_OUT_EP1_ST_REG.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c)
+
+/* USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [2:0]; default: 0;
+ * State of OUT Endpoint
+ * 1.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP1_STATE 0x00000003
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_M (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_V 0x00000003
+#define USB_SERIAL_JTAG_OUT_EP1_STATE_S 0
+
+/* USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [9:2]; default: 0;
+ * Write data address of OUT endpoint 1. When
+ * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are
+ * USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT
+ * EP1.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR 0x0000007f
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V 0x0000007f
+#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S 2
+
+/* USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [16:9]; default: 0;
+ * Read data address of OUT endpoint
+ * 1.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR 0x0000007f
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V 0x0000007f
+#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S 9
+
+/* USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [23:16]; default: 0;
+ * Data count in OUT endpoint 1 when one packet is
+ * received.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT 0x0000007f
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S)
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V 0x0000007f
+#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S 16
+
+/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register
+ * USB_SERIAL_JTAG_OUT_EP2_ST_REG.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40)
+
+/* USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [2:0]; default: 0;
+ * State of OUT Endpoint
+ * 2.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP2_STATE 0x00000003
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_M (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S)
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_V 0x00000003
+#define USB_SERIAL_JTAG_OUT_EP2_STATE_S 0
+
+/* USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [9:2]; default: 0;
+ * Write data address of OUT endpoint 2. When
+ * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are
+ * USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT
+ * EP2.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR 0x0000007f
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V 0x0000007f
+#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S 2
+
+/* USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [16:9]; default: 0;
+ * Read data address of OUT endpoint
+ * 2.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR 0x0000007f
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V 0x0000007f
+#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S 9
+
+/** Interrupt Registers */
+
+/** USB_SERIAL_JTAG_INT_RAW_REG register
+ * USB_SERIAL_JTAG_INT_RAW_REG.
+ */
+
+#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8)
+
+/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
+ * The raw interrupt bit turns to high level when a flush command is
+ * received for IN endpoint 2 of
+ * JTAG.
+ */
+
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V 0x00000001
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S 0
+
+/* USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
+ * The raw interrupt bit turns to high level when a SOF frame is
+ * received.
+ */
+
+#define USB_SERIAL_JTAG_SOF_INT_RAW (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_RAW_M (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S)
+#define USB_SERIAL_JTAG_SOF_INT_RAW_V 0x00000001
+#define USB_SERIAL_JTAG_SOF_INT_RAW_S 1
+
+/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW :
+ * R/WTC/SS; bitpos: [2]; default: 0;
+ * The raw interrupt bit turns to high level when the Serial Port OUT
+ * Endpoint received one
+ * packet.
+ */
+
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x00000001
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S 2
+
+/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW:
+ * R/WTC/SS; bitpos: [3]; default: 1;
+ * The raw interrupt bit turns to high level when the Serial Port IN
+ * Endpoint is
+ * empty.
+ */
+
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V 0x00000001
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S 3
+
+/* USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
+ * The raw interrupt bit turns to high level when a PID error is
+ * detected.
+ */
+
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V 0x00000001
+#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S 4
+
+/* USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
+ * The raw interrupt bit turns to high level when a CRC5 error is
+ * detected.
+ */
+
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V 0x00000001
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S 5
+
+/* USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
+ * The raw interrupt bit turns to high level when a CRC16 error is
+ * detected.
+ */
+
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V 0x00000001
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S 6
+
+/* USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
+ * The raw interrupt bit turns to high level when a bit stuffing error is
+ * detected.
+ */
+
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V 0x00000001
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S 7
+
+/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW:
+ * R/WTC/SS; bitpos: [8]; default: 0;
+ * The raw interrupt bit turns to high level when an IN token for IN
+ * endpoint 1 is
+ * received.
+ */
+
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x00000001
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8
+
+/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
+ * The raw interrupt bit turns to high level when a USB bus reset is
+ * detected.
+ */
+
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V 0x00000001
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S 9
+
+/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW:
+ * R/WTC/SS; bitpos: [10]; default: 0;
+ * The raw interrupt bit turns to high level when OUT endpoint 1 received
+ * packet with zero
+ * payload.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V 0x00000001
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S 10
+
+/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW:
+ * R/WTC/SS; bitpos: [11]; default: 0;
+ * The raw interrupt bit turns to high level when OUT endpoint 2 received
+ * packet with zero
+ * payload.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x00000001
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11
+
+/** USB_SERIAL_JTAG_INT_ST_REG register
+ * USB_SERIAL_JTAG_INT_ST_REG.
+ */
+
+#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc)
+
+/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0;
+ * The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V 0x00000001
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S 0
+
+/* USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0;
+ * The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_SOF_INT_ST (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_ST_M (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S)
+#define USB_SERIAL_JTAG_SOF_INT_ST_V 0x00000001
+#define USB_SERIAL_JTAG_SOF_INT_ST_S 1
+
+/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0;
+ * The raw interrupt status bit for the
+ * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V 0x00000001
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S 2
+
+/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0;
+ * The raw interrupt status bit for the
+ * USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V 0x00000001
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S 3
+
+/* USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0;
+ * The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V 0x00000001
+#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S 4
+
+/* USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0;
+ * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V 0x00000001
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S 5
+
+/* USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0;
+ * The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V 0x00000001
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S 6
+
+/* USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0;
+ * The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V 0x00000001
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S 7
+
+/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0;
+ * The raw interrupt status bit for the
+ * USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x00000001
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S 8
+
+/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0;
+ * The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V 0x00000001
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S 9
+
+/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST: RO; bitpos: [10]; default: 0;
+ * The raw interrupt status bit for the
+ * USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x00000001
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10
+
+/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST: RO; bitpos: [11]; default: 0;
+ * The raw interrupt status bit for the
+ * USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x00000001
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11
+
+/** USB_SERIAL_JTAG_INT_ENA_REG register
+ * USB_SERIAL_JTAG_INT_ENA_REG.
+ */
+
+#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10)
+/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0;
+ * The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V 0x00000001
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S 0
+
+/* USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0;
+ * The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_SOF_INT_ENA (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_ENA_M (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S)
+#define USB_SERIAL_JTAG_SOF_INT_ENA_V 0x00000001
+#define USB_SERIAL_JTAG_SOF_INT_ENA_S 1
+
+/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA: R/W; bitpos: [2]; default: 0;
+ * The interrupt enable bit for the
+ * USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x00000001
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S 2
+
+/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0;
+ * The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V 0x00000001
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S 3
+
+/* USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0;
+ * The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V 0x00000001
+#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S 4
+
+/* USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
+ * The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V 0x00000001
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S 5
+
+/* USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
+ * The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V 0x00000001
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S 6
+
+/* USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
+ * The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V 0x00000001
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S 7
+
+/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA: R/W; bitpos: [8]; default: 0;
+ * The interrupt enable bit for the
+ * USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x00000001
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8
+
+/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0;
+ * The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V 0x00000001
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S 9
+
+/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA :
+ * R/W; bitpos: [10]; default: 0;
+ * The interrupt enable bit for the
+ * USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x00000001
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10
+
+/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA :
+ * R/W; bitpos: [11]; default: 0;
+ * The interrupt enable bit for the
+ * USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x00000001
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11
+
+/* USB_SERIAL_JTAG_INT_CLR_REG register
+ * USB_SERIAL_JTAG_INT_CLR_REG.
+ */
+
+#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14)
+
+/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR (BIT(0))
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S)
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V 0x00000001
+#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S 0
+
+/* USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_SOF_INT_CLR (BIT(1))
+#define USB_SERIAL_JTAG_SOF_INT_CLR_M (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S)
+#define USB_SERIAL_JTAG_SOF_INT_CLR_V 0x00000001
+#define USB_SERIAL_JTAG_SOF_INT_CLR_S 1
+
+/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2))
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S)
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x00000001
+#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S 2
+
+/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR (BIT(3))
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S)
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V 0x00000001
+#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S 3
+
+/* USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR (BIT(4))
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V 0x00000001
+#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S 4
+
+/* USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR (BIT(5))
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V 0x00000001
+#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S 5
+
+/* USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR (BIT(6))
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V 0x00000001
+#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S 6
+
+/* USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR (BIT(7))
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S)
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V 0x00000001
+#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S 7
+
+/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8))
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S)
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x00000001
+#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8
+
+/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR (BIT(9))
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S)
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V 0x00000001
+#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S 9
+
+/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR: WT; bitpos: [10]; default: 0
+ * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10))
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S)
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x00000001
+#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10
+
+/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR:
+ * WT; bitpos: [11]; default: 0;
+ * Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
+ * interrupt.
+ */
+
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11))
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S)
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x00000001
+#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11
+
+/* Version Registers */
+
+/* USB_SERIAL_JTAG_DATE_REG register
+ * USB_SERIAL_JTAG_DATE_REG.
+ */
+
+#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80)
+
+/* USB_SERIAL_JTAG_DATE : R/W; bitpos: [32:0]; default: 33583872;
+ * register version.
+ */
+
+#define USB_SERIAL_JTAG_DATE 0xffffffff
+#define USB_SERIAL_JTAG_DATE_M (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S)
+#define USB_SERIAL_JTAG_DATE_V 0xffffffff
+#define USB_SERIAL_JTAG_DATE_S 0
+
+#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_USB_SERIAL_JTAG_H */
[incubator-nuttx] 03/05: esp32c3/Make.defs: Alawys build
esp32c3_serial.c
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 23039c92cf79a61eb6ac19a65df94f64a2393ff0
Author: Abdelatif Guettouche <ab...@espressif.com>
AuthorDate: Mon Nov 8 13:55:26 2021 +0100
esp32c3/Make.defs: Alawys build esp32c3_serial.c
Signed-off-by: Abdelatif Guettouche <ab...@espressif.com>
---
arch/risc-v/src/esp32c3/Make.defs | 6 +-----
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/arch/risc-v/src/esp32c3/Make.defs b/arch/risc-v/src/esp32c3/Make.defs
index b77eff4..a1db77d 100644
--- a/arch/risc-v/src/esp32c3/Make.defs
+++ b/arch/risc-v/src/esp32c3/Make.defs
@@ -50,7 +50,7 @@ endif
CHIP_CSRCS = esp32c3_allocateheap.c esp32c3_start.c esp32c3_wdt.c esp32c3_idle.c
CHIP_CSRCS += esp32c3_irq.c
CHIP_CSRCS += esp32c3_clockconfig.c esp32c3_gpio.c
-CHIP_CSRCS += esp32c3_lowputc.c
+CHIP_CSRCS += esp32c3_lowputc.c esp32c3_serial.c
CHIP_CSRCS += esp32c3_systemreset.c esp32c3_resetcause.c
CHIP_CSRCS += esp32c3_uid.c
@@ -60,10 +60,6 @@ else
CHIP_CSRCS += esp32c3_timerisr.c
endif
-ifeq ($(CONFIG_ESP32C3_UART),y)
-CHIP_CSRCS += esp32c3_serial.c
-endif
-
ifeq ($(CONFIG_ESP32C3_USBSERIAL),y)
CHIP_CSRCS += esp32c3_usbserial.c
endif
[incubator-nuttx] 04/05: boards/esp32c3-devkit: Add a defconfig for
the USB CDC Console.
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 044508c97928788d889535b6b886053f8a1f355b
Author: Abdelatif Guettouche <ab...@espressif.com>
AuthorDate: Mon Nov 8 13:58:11 2021 +0100
boards/esp32c3-devkit: Add a defconfig for the USB CDC Console.
Signed-off-by: Abdelatif Guettouche <ab...@espressif.com>
---
.../esp32c3-devkit/configs/usbconsole/defconfig | 46 ++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/usbconsole/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/usbconsole/defconfig
new file mode 100644
index 0000000..60bc2b7
--- /dev/null
+++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/usbconsole/defconfig
@@ -0,0 +1,46 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_ESP32C3_UART0 is not set
+# CONFIG_NSH_ARGCAT is not set
+# CONFIG_NSH_CMDOPT_HEXDUMP is not set
+# CONFIG_NSH_CMDPARMS is not set
+CONFIG_ARCH="risc-v"
+CONFIG_ARCH_BOARD="esp32c3-devkit"
+CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y
+CONFIG_ARCH_CHIP="esp32c3"
+CONFIG_ARCH_CHIP_ESP32C3=y
+CONFIG_ARCH_CHIP_ESP32C3WROOM02=y
+CONFIG_ARCH_INTERRUPTSTACK=1536
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_BOARD_LOOPSPERMSEC=15000
+CONFIG_BUILTIN=y
+CONFIG_DEV_ZERO=y
+CONFIG_ESP32C3_USBSERIAL=y
+CONFIG_EXAMPLES_HELLO=y
+CONFIG_FS_PROCFS=y
+CONFIG_HOST_MACOS=y
+CONFIG_IDLETHREAD_STACKSIZE=2048
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LIBC_PERROR_STDOUT=y
+CONFIG_LIBC_STRERROR=y
+CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_READLINE=y
+CONFIG_NSH_STRERROR=y
+CONFIG_PREALLOC_TIMERS=0
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_START_DAY=29
+CONFIG_START_MONTH=11
+CONFIG_START_YEAR=2019
+CONFIG_SYSTEM_NSH=y
+CONFIG_USER_ENTRYPOINT="nsh_main"
[incubator-nuttx] 02/05: arch/riscv/esp32c3: Add the USB-Serial
Driver.
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit ebd94961c7ef018c270e81e8ab3157a84731fa32
Author: Abdelatif Guettouche <ab...@espressif.com>
AuthorDate: Tue Oct 19 15:15:45 2021 +0200
arch/riscv/esp32c3: Add the USB-Serial Driver.
Signed-off-by: Abdelatif Guettouche <ab...@espressif.com>
---
arch/risc-v/src/esp32c3/Kconfig | 6 +
arch/risc-v/src/esp32c3/Make.defs | 4 +
arch/risc-v/src/esp32c3/esp32c3_config.h | 8 +
arch/risc-v/src/esp32c3/esp32c3_lowputc.c | 7 +-
arch/risc-v/src/esp32c3/esp32c3_serial.c | 50 ++-
arch/risc-v/src/esp32c3/esp32c3_usbserial.c | 462 +++++++++++++++++++++
.../{esp32c3_config.h => esp32c3_usbserial.h} | 50 +--
arch/risc-v/src/esp32c3/hardware/esp32c3_soc.h | 1 +
8 files changed, 546 insertions(+), 42 deletions(-)
diff --git a/arch/risc-v/src/esp32c3/Kconfig b/arch/risc-v/src/esp32c3/Kconfig
index 1044de2..6d4bfb2 100644
--- a/arch/risc-v/src/esp32c3/Kconfig
+++ b/arch/risc-v/src/esp32c3/Kconfig
@@ -229,6 +229,12 @@ config ESP32C3_UART1
select UART1_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
+config ESP32C3_USBSERIAL
+ bool "USB-Serial Driver"
+ default n
+ select OTHER_UART_SERIALDRIVER
+ select ARCH_HAVE_SERIAL_TERMIOS
+
config ESP32C3_I2C0
bool "I2C 0"
default n
diff --git a/arch/risc-v/src/esp32c3/Make.defs b/arch/risc-v/src/esp32c3/Make.defs
index e239c1b..b77eff4 100644
--- a/arch/risc-v/src/esp32c3/Make.defs
+++ b/arch/risc-v/src/esp32c3/Make.defs
@@ -64,6 +64,10 @@ ifeq ($(CONFIG_ESP32C3_UART),y)
CHIP_CSRCS += esp32c3_serial.c
endif
+ifeq ($(CONFIG_ESP32C3_USBSERIAL),y)
+CHIP_CSRCS += esp32c3_usbserial.c
+endif
+
ifeq ($(CONFIG_ESP32C3_RNG),y)
CHIP_CSRCS += esp32c3_rng.c
endif
diff --git a/arch/risc-v/src/esp32c3/esp32c3_config.h b/arch/risc-v/src/esp32c3/esp32c3_config.h
index 04c792f..0c520a4 100644
--- a/arch/risc-v/src/esp32c3/esp32c3_config.h
+++ b/arch/risc-v/src/esp32c3/esp32c3_config.h
@@ -49,15 +49,23 @@
*/
#undef HAVE_SERIAL_CONSOLE
+#undef CONSOLE_UART
#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_ESP32C3_UART0)
# undef CONFIG_UART1_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
+# define CONSOLE_UART 1
#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_ESP32C3_UART1)
# undef CONFIG_UART0_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
+# define CONSOLE_UART 1
#else
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
#endif
+#ifdef CONFIG_ESP32C3_USBSERIAL
+# define HAVE_SERIAL_CONSOLE 1
+# define HAVE_UART_DEVICE 1
+#endif
+
#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_CONFIG_H */
diff --git a/arch/risc-v/src/esp32c3/esp32c3_lowputc.c b/arch/risc-v/src/esp32c3/esp32c3_lowputc.c
index 9523506..c38b973 100644
--- a/arch/risc-v/src/esp32c3/esp32c3_lowputc.c
+++ b/arch/risc-v/src/esp32c3/esp32c3_lowputc.c
@@ -45,6 +45,7 @@
#include "esp32c3_clockconfig.h"
#include "esp32c3_config.h"
#include "esp32c3_gpio.h"
+#include "esp32c3_usbserial.h"
#include "esp32c3_lowputc.h"
@@ -800,7 +801,7 @@ void esp32c3_lowputc_restore_pins(const struct esp32c3_uart_s *priv)
void riscv_lowputc(char ch)
{
-#ifdef HAVE_SERIAL_CONSOLE
+#ifdef CONSOLE_UART
# if defined(CONFIG_UART0_SERIAL_CONSOLE)
struct esp32c3_uart_s *priv = &g_uart0_config;
@@ -816,7 +817,9 @@ void riscv_lowputc(char ch)
esp32c3_lowputc_send_byte(priv, ch);
-#endif /* HAVE_CONSOLE */
+#elif defined (CONFIG_ESP32C3_USBSERIAL)
+ esp32c3_usbserial_write(ch);
+#endif /* CONSOLE_UART */
}
/****************************************************************************
diff --git a/arch/risc-v/src/esp32c3/esp32c3_serial.c b/arch/risc-v/src/esp32c3/esp32c3_serial.c
index f172339..1962e1e 100644
--- a/arch/risc-v/src/esp32c3/esp32c3_serial.c
+++ b/arch/risc-v/src/esp32c3/esp32c3_serial.c
@@ -52,6 +52,10 @@
#include "esp32c3_irq.h"
#include "esp32c3_lowputc.h"
+#ifdef CONFIG_ESP32C3_USBSERIAL
+# include "esp32c3_usbserial.h"
+#endif
+
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@@ -72,7 +76,7 @@
* the console and the corresponding peripheral was also selected.
*/
-#ifdef HAVE_SERIAL_CONSOLE
+#ifdef CONSOLE_UART
# if defined(CONFIG_UART0_SERIAL_CONSOLE)
# define CONSOLE_DEV g_uart0_dev /* UART0 is console */
# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
@@ -82,7 +86,7 @@
# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
# define UART1_ASSIGNED 1
# endif /* CONFIG_UART0_SERIAL_CONSOLE */
-#else /* No console */
+#else /* No UART console */
# undef CONSOLE_DEV
# if defined(CONFIG_ESP32C3_UART0)
# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
@@ -91,7 +95,12 @@
# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
# define UART1_ASSIGNED 1
# endif
-#endif /* HAVE_SERIAL_CONSOLE */
+#endif /* CONSOLE_UART */
+
+#ifdef CONFIG_ESP32C3_USBSERIAL
+# define CONSOLE_DEV g_uart_usbserial
+# define TTYACM0_DEV g_uart_usbserial
+#endif
/* Pick ttys1 */
@@ -109,6 +118,8 @@
* Private Function Prototypes
****************************************************************************/
+#ifdef CONFIG_ESP32C3_UART
+
/* Serial driver methods */
static int esp32c3_setup(struct uart_dev_s *dev);
@@ -127,11 +138,14 @@ static int esp32c3_ioctl(struct file *filep, int cmd, unsigned long arg);
static bool esp32c3_rxflowcontrol(struct uart_dev_s *dev,
unsigned int nbuffered, bool upper);
#endif
+#endif
/****************************************************************************
* Private Data
****************************************************************************/
+#ifdef CONFIG_ESP32C3_UART
+
/* Operations */
static struct uart_ops_s g_uart_ops =
@@ -219,10 +233,14 @@ static uart_dev_t g_uart1_dev =
#endif
+#endif /* CONFIG_ESP32C3_UART */
+
/****************************************************************************
* Private Functions
****************************************************************************/
+#ifdef CONFIG_ESP32C3_UART
+
/****************************************************************************
* Name: uart_interrupt
*
@@ -992,6 +1010,7 @@ static bool esp32c3_rxflowcontrol(struct uart_dev_s *dev,
return ret;
}
#endif
+#endif /* CONFIG_ESP32C3_UART */
/****************************************************************************
* Public Functions
@@ -1019,7 +1038,10 @@ void riscv_earlyserialinit(void)
/* Disable all UARTS interrupts */
+#ifdef TTYS0_DEV
esp32c3_lowputc_disable_all_uart_int(TTYS0_DEV.priv, NULL);
+#endif
+
#ifdef TTYS1_DEV
esp32c3_lowputc_disable_all_uart_int(TTYS1_DEV.priv, NULL);
#endif
@@ -1029,7 +1051,7 @@ void riscv_earlyserialinit(void)
* open.
*/
-#ifdef HAVE_SERIAL_CONSOLE
+#ifdef CONSOLE_UART
esp32c3_setup(&CONSOLE_DEV);
#endif
}
@@ -1051,13 +1073,17 @@ void riscv_serialinit(void)
uart_register("/dev/console", &CONSOLE_DEV);
#endif
- /* At least one UART char driver will logically be registered */
-
+#ifdef TTYS0_DEV
uart_register("/dev/ttyS0", &TTYS0_DEV);
+#endif
-#ifdef TTYS1_DEV
+#ifdef TTYS1_DEV
uart_register("/dev/ttyS1", &TTYS1_DEV);
#endif
+
+#ifdef CONFIG_ESP32C3_USBSERIAL
+ uart_register("/dev/ttyACM0", &TTYACM0_DEV);
+#endif
}
/****************************************************************************
@@ -1070,10 +1096,11 @@ void riscv_serialinit(void)
int up_putc(int ch)
{
-#ifdef HAVE_SERIAL_CONSOLE
+#ifdef CONSOLE_UART
uint32_t int_status;
esp32c3_lowputc_disable_all_uart_int(CONSOLE_DEV.priv, &int_status);
+#endif
/* Check for LF */
@@ -1085,6 +1112,8 @@ int up_putc(int ch)
}
riscv_lowputc(ch);
+
+#ifdef CONSOLE_UART
esp32c3_lowputc_restore_all_uart_int(CONSOLE_DEV.priv, &int_status);
#endif
return ch;
@@ -1104,10 +1133,11 @@ int up_putc(int ch)
int up_putc(int ch)
{
-#ifdef HAVE_SERIAL_CONSOLE
+#ifdef CONSOLE_UART
uint32_t int_status;
esp32c3_lowputc_disable_all_uart_int(CONSOLE_DEV.priv, &int_status);
+#endif
/* Check for LF */
@@ -1119,6 +1149,8 @@ int up_putc(int ch)
}
riscv_lowputc(ch);
+
+#ifdef CONSOLE_UART
esp32c3_lowputc_restore_all_uart_int(CONSOLE_DEV.priv, &int_status);
#endif
return ch;
diff --git a/arch/risc-v/src/esp32c3/esp32c3_usbserial.c b/arch/risc-v/src/esp32c3/esp32c3_usbserial.c
new file mode 100644
index 0000000..d612e38
--- /dev/null
+++ b/arch/risc-v/src/esp32c3/esp32c3_usbserial.c
@@ -0,0 +1,462 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c3/esp32c3_usbserial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/kmalloc.h>
+#include <nuttx/serial/serial.h>
+#include <arch/irq.h>
+
+#include "riscv_arch.h"
+
+#include "hardware/esp32c3_soc.h"
+#include "hardware/esp32c3_system.h"
+#include "hardware/esp32c3_usb_serial_jtag.h"
+
+#include "esp32c3_config.h"
+#include "esp32c3_irq.h"
+
+/****************************************************************************
+ * Pre-processor Macros
+ ****************************************************************************/
+
+/* The hardware buffer has a fixed size of 64 bytes */
+
+#define ESP32C3_USBCDC_BUFFERSIZE 64
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct esp32c3_priv_s
+{
+ const uint8_t periph; /* peripheral ID */
+ const uint8_t irq; /* IRQ number assigned to the peripheral */
+ int cpuint; /* CPU interrupt assigned */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static int esp32c3_interrupt(int irq, void *context, void *arg);
+
+/* Serial driver methods */
+
+static int esp32c3_setup(struct uart_dev_s *dev);
+static void esp32c3_shutdown(struct uart_dev_s *dev);
+static int esp32c3_attach(struct uart_dev_s *dev);
+static void esp32c3_detach(struct uart_dev_s *dev);
+static void esp32c3_txint(struct uart_dev_s *dev, bool enable);
+static void esp32c3_rxint(struct uart_dev_s *dev, bool enable);
+static bool esp32c3_rxavailable(struct uart_dev_s *dev);
+static bool esp32c3_txready(struct uart_dev_s *dev);
+static void esp32c3_send(struct uart_dev_s *dev, int ch);
+static int esp32c3_receive(struct uart_dev_s *dev, unsigned int *status);
+static int esp32c3_ioctl(struct file *filep, int cmd, unsigned long arg);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static char g_rxbuffer[ESP32C3_USBCDC_BUFFERSIZE];
+static char g_txbuffer[ESP32C3_USBCDC_BUFFERSIZE];
+
+static struct esp32c3_priv_s g_usbserial_priv =
+{
+ .periph = ESP32C3_PERIPH_USB,
+ .irq = ESP32C3_IRQ_USB,
+};
+
+static struct uart_ops_s g_uart_ops =
+{
+ .setup = esp32c3_setup,
+ .shutdown = esp32c3_shutdown,
+ .attach = esp32c3_attach,
+ .detach = esp32c3_detach,
+ .txint = esp32c3_txint,
+ .rxint = esp32c3_rxint,
+ .rxavailable = esp32c3_rxavailable,
+ .txready = esp32c3_txready,
+ .txempty = NULL,
+ .send = esp32c3_send,
+ .receive = esp32c3_receive,
+ .ioctl = esp32c3_ioctl,
+};
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+uart_dev_t g_uart_usbserial =
+{
+ .isconsole = true,
+ .recv =
+ {
+ .size = ESP32C3_USBCDC_BUFFERSIZE,
+ .buffer = g_rxbuffer,
+ },
+ .xmit =
+ {
+ .size = ESP32C3_USBCDC_BUFFERSIZE,
+ .buffer = g_txbuffer,
+ },
+ .ops = &g_uart_ops,
+ .priv = &g_usbserial_priv,
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32c3_interrupt
+ *
+ * Description:
+ * This is the common UART interrupt handler. It will be invoked
+ * when an interrupt received on the device. It should call
+ * uart_transmitchars or uart_receivechar to perform the appropriate data
+ * transfers.
+ *
+ ****************************************************************************/
+
+static int esp32c3_interrupt(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ uint32_t regval;
+
+ regval = getreg32(USB_SERIAL_JTAG_INT_ST_REG);
+
+ /* Send buffer has room and can accept new data. */
+
+ if (regval & USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST)
+ {
+ putreg32(USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR,
+ USB_SERIAL_JTAG_INT_CLR_REG);
+ uart_xmitchars(dev);
+ }
+
+ /* Data from the host are available to read. */
+
+ if (regval & USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST)
+ {
+ putreg32(USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR,
+ USB_SERIAL_JTAG_INT_CLR_REG);
+ uart_recvchars(dev);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32c3_setup
+ *
+ * Description:
+ * This method is called the first time that the serial port is opened.
+ *
+ ****************************************************************************/
+
+static int esp32c3_setup(struct uart_dev_s *dev)
+{
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32c3_shutdown
+ *
+ * Description:
+ * This method is called when the serial port is closed.
+ *
+ ****************************************************************************/
+
+static void esp32c3_shutdown(struct uart_dev_s *dev)
+{
+}
+
+/****************************************************************************
+ * Name: esp32c3_txint
+ *
+ * Description:
+ * Call to enable or disable TX interrupts
+ *
+ ****************************************************************************/
+
+static void esp32c3_txint(struct uart_dev_s *dev, bool enable)
+{
+ if (enable)
+ {
+ modifyreg32(USB_SERIAL_JTAG_INT_ENA_REG, 0,
+ USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA);
+ }
+ else
+ {
+ modifyreg32(USB_SERIAL_JTAG_INT_ENA_REG,
+ USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32c3_rxint
+ *
+ * Description:
+ * Call to enable or disable RXRDY interrupts
+ *
+ ****************************************************************************/
+
+static void esp32c3_rxint(struct uart_dev_s *dev, bool enable)
+{
+ if (enable)
+ {
+ modifyreg32(USB_SERIAL_JTAG_INT_ENA_REG, 0,
+ USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA);
+ }
+ else
+ {
+ modifyreg32(USB_SERIAL_JTAG_INT_ENA_REG,
+ USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32c3_attach
+ *
+ * Description:
+ * Configure the UART to operation in interrupt driven mode. This method
+ * is called when the serial port is opened. Normally, this is just after
+ * the the setup() method is called, however, the serial console may
+ * operate in a non-interrupt driven mode during the boot phase.
+ *
+ * RX and TX interrupts are not enabled by the attach method (unless
+ * the hardware supports multiple levels of interrupt enabling). The RX
+ * and TX interrupts are not enabled until the txint() and rxint() methods
+ * are called.
+ *
+ ****************************************************************************/
+
+static int esp32c3_attach(struct uart_dev_s *dev)
+{
+ struct esp32c3_priv_s *priv = dev->priv;
+ int ret;
+
+ DEBUGASSERT(priv->cpuint == -ENOMEM);
+
+ /* Try to attach the IRQ to a CPU int */
+
+ priv->cpuint = esp32c3_request_irq(priv->periph,
+ ESP32C3_INT_PRIO_DEF,
+ ESP32C3_INT_LEVEL);
+ if (priv->cpuint < 0)
+ {
+ return priv->cpuint;
+ }
+
+ /* Attach and enable the IRQ */
+
+ ret = irq_attach(priv->irq, esp32c3_interrupt, dev);
+ if (ret == OK)
+ {
+ up_enable_irq(priv->cpuint);
+ }
+ else
+ {
+ up_disable_irq(priv->cpuint);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32c3_detach
+ *
+ * Description:
+ * Detach UART interrupts. This method is called when the serial port is
+ * closed normally just before the shutdown method is called. The
+ * exception is the serial console which is never shutdown.
+ *
+ ****************************************************************************/
+
+static void esp32c3_detach(struct uart_dev_s *dev)
+{
+ struct esp32c3_priv_s *priv = dev->priv;
+
+ DEBUGASSERT(priv->cpuint != -ENOMEM);
+
+ up_disable_irq(priv->cpuint);
+ irq_detach(priv->irq);
+ esp32c3_free_cpuint(priv->periph);
+
+ priv->cpuint = -ENOMEM;
+}
+
+/****************************************************************************
+ * Name: esp32c3_rxavailable
+ *
+ * Description:
+ * Return true if the receive holding register is not empty
+ *
+ ****************************************************************************/
+
+static bool esp32c3_rxavailable(struct uart_dev_s *dev)
+{
+ uint32_t regval;
+
+ regval = getreg32(USB_SERIAL_JTAG_EP1_CONF_REG);
+
+ return regval & USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL;
+}
+
+/****************************************************************************
+ * Name: esp32c3_txready
+ *
+ * Description:
+ * Return true if the transmit holding register is empty (TXRDY)
+ *
+ ****************************************************************************/
+
+static bool esp32c3_txready(struct uart_dev_s *dev)
+{
+ uint32_t regval;
+
+ regval = getreg32(USB_SERIAL_JTAG_EP1_CONF_REG);
+
+ return regval & USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE;
+}
+
+/****************************************************************************
+ * Name: esp32c3_send
+ *
+ * Description:
+ * This method will send one byte on the UART.
+ *
+ ****************************************************************************/
+
+static void esp32c3_send(struct uart_dev_s *dev, int ch)
+{
+ /* Write the character to the buffer. */
+
+ putreg32(ch, USB_SERIAL_JTAG_EP1_REG);
+
+ /* Flush the character out. */
+
+ putreg32(1, USB_SERIAL_JTAG_EP1_CONF_REG);
+}
+
+/****************************************************************************
+ * Name: esp32_receive
+ *
+ * Description:
+ * Called (usually) from the interrupt level to receive one character.
+ *
+ ****************************************************************************/
+
+static int esp32c3_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+ *status = 0;
+ return getreg32(USB_SERIAL_JTAG_EP1_REG) & USB_SERIAL_JTAG_RDWR_BYTE;
+}
+
+/****************************************************************************
+ * Name: esp32c3_ioctl
+ *
+ * Description:
+ * All ioctl calls will be routed through this method
+ *
+ ****************************************************************************/
+
+static int esp32c3_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+#if defined(CONFIG_SERIAL_TERMIOS)
+ struct inode *inode = filep->f_inode;
+ struct uart_dev_s *dev = inode->i_private;
+#endif
+ int ret = OK;
+
+ switch (cmd)
+ {
+#ifdef CONFIG_SERIAL_TERMIOS
+ case TCGETS:
+ {
+ struct termios *termiosp = (struct termios *)arg;
+
+ if (!termiosp)
+ {
+ ret = -EINVAL;
+ }
+ else
+ {
+ /* The USB Serial Console has fixed configuration of:
+ * 9600 baudrate, no parity, 8 bits, 1 stopbit.
+ */
+
+ termiosp->c_cflag = CS8;
+ cfsetispeed(termiosp, 9600);
+ }
+ }
+ break;
+
+ case TCSETS:
+ ret = -ENOTTY;
+ break;
+#endif /* CONFIG_SERIAL_TERMIOS */
+
+ default:
+ ret = -ENOTTY;
+ break;
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32c3_usbserial_write
+ *
+ * Description:
+ * Write one character through the USB serial. Used mainly for early
+ * debugging.
+ *
+ ****************************************************************************/
+
+void esp32c3_usbserial_write(char ch)
+{
+ while (!esp32c3_txready(&g_uart_usbserial));
+
+ esp32c3_send(&g_uart_usbserial, ch);
+}
+
diff --git a/arch/risc-v/src/esp32c3/esp32c3_config.h b/arch/risc-v/src/esp32c3/esp32c3_usbserial.h
similarity index 53%
copy from arch/risc-v/src/esp32c3/esp32c3_config.h
copy to arch/risc-v/src/esp32c3/esp32c3_usbserial.h
index 04c792f..9c5f3f9 100644
--- a/arch/risc-v/src/esp32c3/esp32c3_config.h
+++ b/arch/risc-v/src/esp32c3/esp32c3_usbserial.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/risc-v/src/esp32c3/esp32c3_config.h
+ * arch/risc-v/src/esp32c3/esp32c3_usbserial.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -18,46 +18,34 @@
*
****************************************************************************/
-#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_CONFIG_H
-#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_CONFIG_H
+#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_USBSERIAL_H
+#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_USBSERIAL_H
/****************************************************************************
* Included Files
****************************************************************************/
-#include <nuttx/config.h>
-#include <arch/chip/chip.h>
-#include <arch/board/board.h>
+#include <nuttx/serial/serial.h>
/****************************************************************************
- * Pre-processor Definitions
+ * Public Data
****************************************************************************/
-/* UARTs ********************************************************************/
+extern uart_dev_t g_uart_usbserial;
-/* Are any UARTs enabled? */
-
-#undef HAVE_UART_DEVICE
-#if defined(CONFIG_ESP32C3_UART0) || defined(CONFIG_ESP32C3_UART1)
-# define HAVE_UART_DEVICE 1 /* Flag to indicate a UART has been selected */
-#endif
-
-/* Serial Console ***********************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
-/* Is there a serial console? There should be no more than one defined. It
- * could be on any UARTn. n E {0,1}
- */
+/****************************************************************************
+ * Name: esp32c3_usbserial_write
+ *
+ * Description:
+ * Write one character through the USB serial. Used mainly for early
+ * debugging.
+ *
+ ****************************************************************************/
-#undef HAVE_SERIAL_CONSOLE
-#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_ESP32C3_UART0)
-# undef CONFIG_UART1_SERIAL_CONSOLE
-# define HAVE_SERIAL_CONSOLE 1
-#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_ESP32C3_UART1)
-# undef CONFIG_UART0_SERIAL_CONSOLE
-# define HAVE_SERIAL_CONSOLE 1
-#else
-# undef CONFIG_UART0_SERIAL_CONSOLE
-# undef CONFIG_UART1_SERIAL_CONSOLE
-#endif
+void esp32c3_usbserial_write(char ch);
-#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_CONFIG_H */
+#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_USBSERIAL_H */
diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_soc.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_soc.h
index 75a15c8..27e2c5f 100644
--- a/arch/risc-v/src/esp32c3/hardware/esp32c3_soc.h
+++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_soc.h
@@ -73,6 +73,7 @@
#define DR_REG_TWAI_BASE 0x6002B000
#define DR_REG_I2S0_BASE 0x6002D000
#define DR_REG_APB_SARADC_BASE 0x60040000
+#define DR_REG_USB_SERIAL_JTAG_BASE 0x60043000
#define DR_REG_AES_XTS_BASE 0x600CC000
/* Registers Operation */
[incubator-nuttx] 05/05: Documentation/esp32c3: Document the CDC
console defconfig.
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 00befc4ec670b7158d50f23f799b4ad0bea114cf
Author: Abdelatif Guettouche <ab...@espressif.com>
AuthorDate: Mon Nov 8 19:00:47 2021 +0100
Documentation/esp32c3: Document the CDC console defconfig.
Signed-off-by: Abdelatif Guettouche <ab...@espressif.com>
---
.../risc-v/esp32c3/boards/esp32c3-devkit/index.rst | 14 ++++++++++++++
Documentation/platforms/risc-v/esp32c3/index.rst | 7 ++++---
2 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-devkit/index.rst b/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-devkit/index.rst
index 180245a..f68af97 100644
--- a/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-devkit/index.rst
+++ b/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-devkit/index.rst
@@ -95,3 +95,17 @@ To test it, just run the following command::
nsh> watcher
nsh> watched
+usbconsole
+==========
+
+This configuration tests the built-in USB-to-serial converter found in ESP32-C3 (revision 3).
+`esptool` can be used to check the version of the chip and if this feature is
+supported. Running `esptool.py -p <port> chip_id` should have `Chip is
+ESP32-C3 (revision 3)` in its output.
+When connecting the board a new device should appear, a `/dev/ttyACMX` on Linux
+or a `/dev/cu.usbmodemXXX` om macOS.
+This can be used to flash and monitor the device with the usual commands::
+
+ make download ESPTOOL_PORT=/dev/ttyACM0
+ minicom -D /dev/ttyACM0
+
diff --git a/Documentation/platforms/risc-v/esp32c3/index.rst b/Documentation/platforms/risc-v/esp32c3/index.rst
index 3946ae2..d65e1382 100644
--- a/Documentation/platforms/risc-v/esp32c3/index.rst
+++ b/Documentation/platforms/risc-v/esp32c3/index.rst
@@ -101,9 +101,9 @@ Peripheral Support
The following list indicates the state of peripherals' support in NuttX:
-========== ======= =====
-Peripheral Support NOTES
-========== ======= =====
+=========== ======= =====
+Peripheral Support NOTES
+=========== ======= =====
GPIO Yes
UART Yes
SPI Yes
@@ -122,6 +122,7 @@ Bluetooth Yes
LED_PWM Yes
SHA Yes
RSA Yes
+CDC Console Yes Rev.3
========== ======= =====
Supported Boards