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Posted to commits@nuttx.apache.org by xi...@apache.org on 2021/09/23 09:49:17 UTC
[incubator-nuttx] branch master updated (47c60b2 -> f2f2040)
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git.
from 47c60b2 arch/arm: Remove -march and -mtune
new 2834d2a esp32_spiflash.c/esp32_spiram.c: Remove some unused macros/functions/variables.
new 3d8a6fb esp32_spiram.c: Remove esp_himem_reserved_area_size from esp32_spiram.c file. This function is already defined in esp_himem and is used only when that file is built. We don't need another weak function.
new f2f2040 esp32_spiram/psram/himem: Add and fix the files' sections.
The 3 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
arch/xtensa/src/esp32/esp32_himem.h | 8 +
arch/xtensa/src/esp32/esp32_psram.c | 432 ++++++++++++++++-----------------
arch/xtensa/src/esp32/esp32_psram.h | 6 +-
arch/xtensa/src/esp32/esp32_spiflash.c | 3 -
arch/xtensa/src/esp32/esp32_spiram.c | 78 +-----
arch/xtensa/src/esp32/esp32_spiram.h | 8 +
6 files changed, 234 insertions(+), 301 deletions(-)
[incubator-nuttx] 01/03: esp32_spiflash.c/esp32_spiram.c: Remove
some unused macros/functions/variables.
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 2834d2a46f198933d8671227208d1a8e8724d58b
Author: Abdelatif Guettouche <ab...@espressif.com>
AuthorDate: Tue Sep 21 14:34:32 2021 +0200
esp32_spiflash.c/esp32_spiram.c: Remove some unused macros/functions/variables.
Signed-off-by: Abdelatif Guettouche <ab...@espressif.com>
---
arch/xtensa/src/esp32/esp32_psram.c | 10 ------
arch/xtensa/src/esp32/esp32_spiflash.c | 3 --
arch/xtensa/src/esp32/esp32_spiram.c | 60 ----------------------------------
3 files changed, 73 deletions(-)
diff --git a/arch/xtensa/src/esp32/esp32_psram.c b/arch/xtensa/src/esp32/esp32_psram.c
index 87672d0..6b9ec45 100644
--- a/arch/xtensa/src/esp32/esp32_psram.c
+++ b/arch/xtensa/src/esp32/esp32_psram.c
@@ -52,10 +52,6 @@
* Pre-processor Definitions
****************************************************************************/
-#ifndef MIN
-#define MIN(a, b) (((a) < (b)) ? (a) : (b))
-#endif
-
#define RTC_VDDSDIO_TIEH_1_8V 0 /* TIEH field value for 1.8V VDDSDIO */
#define RTC_VDDSDIO_TIEH_3_3V 1 /* TIEH field value for 3.3V VDDSDIO */
@@ -338,12 +334,6 @@ static int psram_2t_mode_check(psram_spi_num_t spi_num);
#endif
/****************************************************************************
- * ROM function prototypes
- ****************************************************************************/
-
-extern void ets_delay_us(int delay_us);
-
-/****************************************************************************
* Private Functions
****************************************************************************/
diff --git a/arch/xtensa/src/esp32/esp32_spiflash.c b/arch/xtensa/src/esp32/esp32_spiflash.c
index fab43c1..295bfec 100644
--- a/arch/xtensa/src/esp32/esp32_spiflash.c
+++ b/arch/xtensa/src/esp32/esp32_spiflash.c
@@ -90,9 +90,6 @@
# define MIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
-#define DPORT_INTERRUPT_DISABLE()
-#define DPORT_INTERRUPT_RESTORE()
-
/* Flash MMU table for PRO CPU */
#define PRO_MMU_TABLE ((volatile uint32_t *)DPORT_PRO_FLASH_MMU_TABLE_REG)
diff --git a/arch/xtensa/src/esp32/esp32_spiram.c b/arch/xtensa/src/esp32/esp32_spiram.c
index c95f73a..1d82a95 100644
--- a/arch/xtensa/src/esp32/esp32_spiram.c
+++ b/arch/xtensa/src/esp32/esp32_spiram.c
@@ -47,10 +47,6 @@
* Pre-processor Definitions
****************************************************************************/
-#ifndef MIN
-#define MIN(a, b) (((a) < (b)) ? (a) : (b))
-#endif
-
#ifndef CONFIG_SMP
# define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL
#else
@@ -75,10 +71,6 @@
# error "FLASH speed can only be equal to or higher than SRAM speed while SRAM is enabled!"
#endif
-#if defined(CONFIG_BOOT_SDRAM_DATA)
-extern uint8_t _ext_ram_bss_start;
-extern uint8_t _ext_ram_bss_end;
-#endif
static bool spiram_inited = false;
/****************************************************************************
@@ -324,58 +316,6 @@ int esp_spiram_init(void)
return OK;
}
-#if 0
-/* DMA is not supported yet */
-
-static uint8_t *dma_heap;
-
-int esp_spiram_reserve_dma_pool(size_t size)
-{
- minfo("Reserving pool of %dK of internal memory for DMA/internal\
- allocations", size / 1024);
-
- /* Pool may be allocated in multiple non-contiguous chunks, depending on
- * available RAM
- */
-
- while (size > 0)
- {
- size_t next_size = heap_caps_get_largest_free_block(MALLOC_CAP_DMA |
- MALLOC_CAP_INTERNAL);
-
- next_size = MIN(next_size, size);
-
- minfo("Allocating block of size %d bytes", next_size);
-
- dma_heap = heap_caps_malloc(next_size, MALLOC_CAP_DMA |
- MALLOC_CAP_INTERNAL);
-
- if (!dma_heap || next_size == 0)
- {
- return ESP_ERR_NO_MEM;
- }
-
- uint32_t caps[] =
- {
- 0, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL,
- MALLOC_CAP_8BIT | MALLOC_CAP_32BIT
- };
-
- int e = heap_caps_add_region_with_caps(caps, (intptr_t) dma_heap,
- (intptr_t) dma_heap + next_size - 1);
-
- if (e != ESP_OK)
- {
- return e;
- }
-
- size -= next_size;
- }
-
- return OK;
-}
-#endif
-
size_t esp_spiram_get_size(void)
{
int size = esp_spiram_get_chip_size();
[incubator-nuttx] 02/03: esp32_spiram.c: Remove
esp_himem_reserved_area_size from esp32_spiram.c file. This function is
already defined in esp_himem and is used only when that file is built. We
don't need another weak function.
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 3d8a6fb676d6c5453e44469e20925374de01e06e
Author: Abdelatif Guettouche <ab...@espressif.com>
AuthorDate: Wed Sep 22 17:21:40 2021 +0200
esp32_spiram.c: Remove esp_himem_reserved_area_size from esp32_spiram.c
file. This function is already defined in esp_himem and is used only
when that file is built. We don't need another weak function.
Signed-off-by: Abdelatif Guettouche <ab...@espressif.com>
---
arch/xtensa/src/esp32/esp32_spiram.c | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/arch/xtensa/src/esp32/esp32_spiram.c b/arch/xtensa/src/esp32/esp32_spiram.c
index 1d82a95..c6eef15 100644
--- a/arch/xtensa/src/esp32/esp32_spiram.c
+++ b/arch/xtensa/src/esp32/esp32_spiram.c
@@ -77,16 +77,6 @@ static bool spiram_inited = false;
* Private Functions
****************************************************************************/
-/* If no function in esp_himem.c is used, this function will be linked into
- * the binary instead of the one in esp_himem.c, automatically making sure
- * no memory is reserved if no himem function is used.
- */
-
-size_t weak_function esp_himem_reserved_area_size(void)
-{
- return 0;
-}
-
/****************************************************************************
* Public Functions
****************************************************************************/
[incubator-nuttx] 03/03: esp32_spiram/psram/himem: Add and fix the
files' sections.
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit f2f2040c44e3e23ca5c8db9bd0a6fdf94b1db4e5
Author: Abdelatif Guettouche <ab...@espressif.com>
AuthorDate: Wed Sep 22 17:20:30 2021 +0200
esp32_spiram/psram/himem: Add and fix the files' sections.
Signed-off-by: Abdelatif Guettouche <ab...@espressif.com>
---
arch/xtensa/src/esp32/esp32_himem.h | 8 +
arch/xtensa/src/esp32/esp32_psram.c | 422 +++++++++++++++++------------------
arch/xtensa/src/esp32/esp32_psram.h | 6 +-
arch/xtensa/src/esp32/esp32_spiram.c | 10 +-
arch/xtensa/src/esp32/esp32_spiram.h | 8 +
5 files changed, 235 insertions(+), 219 deletions(-)
diff --git a/arch/xtensa/src/esp32/esp32_himem.h b/arch/xtensa/src/esp32/esp32_himem.h
index baf776f..1f29c51 100644
--- a/arch/xtensa/src/esp32/esp32_himem.h
+++ b/arch/xtensa/src/esp32/esp32_himem.h
@@ -32,12 +32,20 @@ extern "C"
{
#endif
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
/* Indicates that a mapping will only be read from. Note that this is unused
* for now.
*/
#define ESP_HIMEM_MAPFLAG_RO 1
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
+
/* Allocate a block in high memory
*
* params:
diff --git a/arch/xtensa/src/esp32/esp32_psram.c b/arch/xtensa/src/esp32/esp32_psram.c
index 6b9ec45..7ecda49 100644
--- a/arch/xtensa/src/esp32/esp32_psram.c
+++ b/arch/xtensa/src/esp32/esp32_psram.c
@@ -416,6 +416,217 @@ static int IRAM_ATTR esp32_get_vddsdio_config(
return OK;
}
+/* register initialization for sram cache params and r/w commands */
+
+static void IRAM_ATTR
+ psram_cache_init(int psram_cache_mode, int vaddrmode)
+{
+ uint32_t regval;
+
+ switch (psram_cache_mode)
+ {
+ case PSRAM_CACHE_F80M_S80M:
+
+ /* flash 1 div clk,80+40; */
+
+ modifyreg32(SPI_DATE_REG(0), BIT(31), 0);
+
+ /* pre clk div , ONLY IF SPI/SRAM@ DIFFERENT SPEED,JUST FOR SPI0.
+ * FLASH DIV 2+SRAM DIV4
+ */
+
+ modifyreg32(SPI_DATE_REG(0), BIT(30), 0);
+ break;
+
+ case PSRAM_CACHE_F80M_S40M:
+ modifyreg32(SPI_CLOCK_REG(0), SPI_CLK_EQU_SYSCLK_M, 0);
+ SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKDIV_PRE_V, 0,
+ SPI_CLKDIV_PRE_S);
+ SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKCNT_N, 1, SPI_CLKCNT_N_S);
+ SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKCNT_H, 0, SPI_CLKCNT_H_S);
+ SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKCNT_L, 1, SPI_CLKCNT_L_S);
+ modifyreg32(SPI_DATE_REG(0), BIT(31), 0); /* flash 1 div clk */
+
+ /* pre clk div , ONLY IF SPI/SRAM@ DIFFERENT SPEED,JUST FOR SPI0. */
+
+ modifyreg32(SPI_DATE_REG(0), BIT(30), 0);
+ break;
+ case PSRAM_CACHE_F40M_S40M:
+ default:
+
+ /* flash 1 div clk */
+
+ modifyreg32(SPI_DATE_REG(0), BIT(31), 0);
+
+ /* pre clk div */
+
+ modifyreg32(SPI_DATE_REG(0), BIT(30), 0);
+ break;
+ }
+
+ /* disable dio mode for cache command */
+
+ modifyreg32(SPI_CACHE_SCTRL_REG(0), SPI_USR_SRAM_DIO_M, 0);
+
+ /* enable qio mode for cache command */
+
+ modifyreg32(SPI_CACHE_SCTRL_REG(0), 0, SPI_USR_SRAM_QIO_M);
+
+ /* enable cache read command */
+
+ modifyreg32(SPI_CACHE_SCTRL_REG(0), 0, SPI_CACHE_SRAM_USR_RCMD_M);
+
+ /* enable cache write command */
+
+ modifyreg32(SPI_CACHE_SCTRL_REG(0), 0, SPI_CACHE_SRAM_USR_WCMD_M);
+
+ /* write address for cache command */
+
+ SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_ADDR_BITLEN_V, 23,
+ SPI_SRAM_ADDR_BITLEN_S);
+
+ /* enable cache read dummy */
+
+ modifyreg32(SPI_CACHE_SCTRL_REG(0), 0, SPI_USR_RD_SRAM_DUMMY_M);
+
+ /* config sram cache r/w command */
+
+ SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0),
+ SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 7,
+ SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S);
+
+ SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0),
+ SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V,
+ PSRAM_FAST_READ_QUAD,
+ SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S); /* 0xEB */
+
+ SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0),
+ SPI_CACHE_SRAM_USR_WR_CMD_BITLEN, 7,
+ SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S);
+
+ SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0),
+ SPI_CACHE_SRAM_USR_WR_CMD_VALUE,
+ PSRAM_QUAD_WRITE,
+ SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S); /* 0x38 */
+
+ /* dummy, psram cache : 40m--+1dummy; 80m--+2dummy */
+
+ SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_DUMMY_CYCLELEN_V,
+ PSRAM_FAST_READ_QUAD_DUMMY + extra_dummy,
+ SPI_SRAM_DUMMY_CYCLELEN_S);
+
+ switch (psram_cache_mode)
+ {
+ /* in this mode , no delay is needed */
+
+ case PSRAM_CACHE_F80M_S80M:
+ break;
+
+ /* if sram is @40M, need 2 cycles of delay */
+
+ case PSRAM_CACHE_F80M_S40M:
+ case PSRAM_CACHE_F40M_S40M:
+ default:
+ if (s_clk_mode == PSRAM_CLK_MODE_DCLK)
+ {
+ /* read command length, 2 bytes(1byte for delay), sending in qio
+ * mode in cache
+ */
+
+ SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0),
+ SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 15,
+ SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S);
+
+ /* 0xEB, read command value,(0x00 for delay,0xeb for cmd) */
+
+ SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0),
+ SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V,
+ ((PSRAM_FAST_READ_QUAD) << 8),
+ SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S);
+
+ /* write command length,2 bytes(1byte for delay,send in qio mode
+ * in cache)
+ */
+
+ SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0),
+ SPI_CACHE_SRAM_USR_WR_CMD_BITLEN, 15,
+ SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S);
+
+ /* 0x38, write command value,(0x00 for delay) */
+
+ SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0),
+ SPI_CACHE_SRAM_USR_WR_CMD_VALUE,
+ ((PSRAM_QUAD_WRITE) << 8),
+ SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S);
+
+ /* dummy, psram cache : 40m--+1dummy; 80m--+2dummy */
+
+ SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0),
+ SPI_SRAM_DUMMY_CYCLELEN_V,
+ PSRAM_FAST_READ_QUAD_DUMMY + extra_dummy,
+ SPI_SRAM_DUMMY_CYCLELEN_S);
+ }
+ break;
+ }
+
+ modifyreg32(DPORT_PRO_CACHE_CTRL_REG,
+ DPORT_PRO_DRAM_HL | DPORT_PRO_DRAM_SPLIT, 0);
+ modifyreg32(DPORT_APP_CACHE_CTRL_REG,
+ DPORT_APP_DRAM_HL | DPORT_APP_DRAM_SPLIT, 0);
+ if (vaddrmode == PSRAM_VADDR_MODE_LOWHIGH)
+ {
+ modifyreg32(DPORT_PRO_CACHE_CTRL_REG, 0, DPORT_PRO_DRAM_HL);
+ modifyreg32(DPORT_APP_CACHE_CTRL_REG, 0, DPORT_APP_DRAM_HL);
+ }
+ else
+ {
+ if (vaddrmode == PSRAM_VADDR_MODE_EVENODD)
+ {
+ modifyreg32(DPORT_PRO_CACHE_CTRL_REG, 0, DPORT_PRO_DRAM_SPLIT);
+ modifyreg32(DPORT_APP_CACHE_CTRL_REG, 0, DPORT_APP_DRAM_SPLIT);
+ }
+ }
+
+ /* use Dram1 to visit ext sram. */
+
+ modifyreg32(DPORT_PRO_CACHE_CTRL1_REG,
+ DPORT_PRO_CACHE_MASK_DRAM1 | DPORT_PRO_CACHE_MASK_OPSDRAM, 0);
+
+ /* cache page mode :
+ * 1 -->16k
+ * 4 -->2k
+ * 0 -->32k,(accord with the settings in cache_sram_mmu_set)
+ */
+
+ /* get into unknown exception if not comment */
+
+ regval = getreg32(DPORT_PRO_CACHE_CTRL1_REG);
+ regval &= ~(DPORT_PRO_CMMU_SRAM_PAGE_MODE <<
+ DPORT_PRO_CMMU_SRAM_PAGE_MODE_S);
+ putreg32(regval, DPORT_PRO_CACHE_CTRL1_REG);
+
+ /* use DRAM1 to visit ext sram. */
+
+ modifyreg32(DPORT_APP_CACHE_CTRL1_REG,
+ DPORT_APP_CACHE_MASK_DRAM1 |
+ DPORT_APP_CACHE_MASK_OPSDRAM, 0);
+
+ /* cache page mode :
+ * 1 -->16k
+ * 4 -->2k
+ * 0 -->32k, (accord with the settings in cache_sram_mmu_set)
+ */
+
+ regval = getreg32(DPORT_APP_CACHE_CTRL1_REG);
+ regval &= ~(DPORT_APP_CMMU_SRAM_PAGE_MODE <<
+ DPORT_APP_CMMU_SRAM_PAGE_MODE_S);
+ putreg32(regval, DPORT_APP_CACHE_CTRL1_REG);
+
+ /* ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM) */
+
+ modifyreg32(SPI_PIN_REG(0), SPI_CS1_DIS_M, 0);
+}
+
static void psram_clear_spi_fifo(psram_spi_num_t spi_num)
{
int i;
@@ -1561,215 +1772,4 @@ psram_enable(int mode, int vaddrmode) /* psram init */
return OK;
}
-/* register initialization for sram cache params and r/w commands */
-
-static void IRAM_ATTR
-psram_cache_init(int psram_cache_mode, int vaddrmode)
-{
- uint32_t regval;
-
- switch (psram_cache_mode)
- {
- case PSRAM_CACHE_F80M_S80M:
-
- /* flash 1 div clk,80+40; */
-
- modifyreg32(SPI_DATE_REG(0), BIT(31), 0);
-
- /* pre clk div , ONLY IF SPI/SRAM@ DIFFERENT SPEED,JUST FOR SPI0.
- * FLASH DIV 2+SRAM DIV4
- */
-
- modifyreg32(SPI_DATE_REG(0), BIT(30), 0);
- break;
-
- case PSRAM_CACHE_F80M_S40M:
- modifyreg32(SPI_CLOCK_REG(0), SPI_CLK_EQU_SYSCLK_M, 0);
- SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKDIV_PRE_V, 0,
- SPI_CLKDIV_PRE_S);
- SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKCNT_N, 1, SPI_CLKCNT_N_S);
- SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKCNT_H, 0, SPI_CLKCNT_H_S);
- SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKCNT_L, 1, SPI_CLKCNT_L_S);
- modifyreg32(SPI_DATE_REG(0), BIT(31), 0); /* flash 1 div clk */
-
- /* pre clk div , ONLY IF SPI/SRAM@ DIFFERENT SPEED,JUST FOR SPI0. */
-
- modifyreg32(SPI_DATE_REG(0), BIT(30), 0);
- break;
- case PSRAM_CACHE_F40M_S40M:
- default:
-
- /* flash 1 div clk */
-
- modifyreg32(SPI_DATE_REG(0), BIT(31), 0);
-
- /* pre clk div */
-
- modifyreg32(SPI_DATE_REG(0), BIT(30), 0);
- break;
- }
-
- /* disable dio mode for cache command */
-
- modifyreg32(SPI_CACHE_SCTRL_REG(0), SPI_USR_SRAM_DIO_M, 0);
-
- /* enable qio mode for cache command */
-
- modifyreg32(SPI_CACHE_SCTRL_REG(0), 0, SPI_USR_SRAM_QIO_M);
-
- /* enable cache read command */
-
- modifyreg32(SPI_CACHE_SCTRL_REG(0), 0, SPI_CACHE_SRAM_USR_RCMD_M);
-
- /* enable cache write command */
-
- modifyreg32(SPI_CACHE_SCTRL_REG(0), 0, SPI_CACHE_SRAM_USR_WCMD_M);
-
- /* write address for cache command */
-
- SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_ADDR_BITLEN_V, 23,
- SPI_SRAM_ADDR_BITLEN_S);
-
- /* enable cache read dummy */
-
- modifyreg32(SPI_CACHE_SCTRL_REG(0), 0, SPI_USR_RD_SRAM_DUMMY_M);
-
- /* config sram cache r/w command */
-
- SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0),
- SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 7,
- SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S);
-
- SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0),
- SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V,
- PSRAM_FAST_READ_QUAD,
- SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S); /* 0xEB */
-
- SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0),
- SPI_CACHE_SRAM_USR_WR_CMD_BITLEN, 7,
- SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S);
-
- SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0),
- SPI_CACHE_SRAM_USR_WR_CMD_VALUE,
- PSRAM_QUAD_WRITE,
- SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S); /* 0x38 */
-
- /* dummy, psram cache : 40m--+1dummy; 80m--+2dummy */
-
- SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_DUMMY_CYCLELEN_V,
- PSRAM_FAST_READ_QUAD_DUMMY + extra_dummy,
- SPI_SRAM_DUMMY_CYCLELEN_S);
-
- switch (psram_cache_mode)
- {
- /* in this mode , no delay is needed */
-
- case PSRAM_CACHE_F80M_S80M:
- break;
-
- /* if sram is @40M, need 2 cycles of delay */
-
- case PSRAM_CACHE_F80M_S40M:
- case PSRAM_CACHE_F40M_S40M:
- default:
- if (s_clk_mode == PSRAM_CLK_MODE_DCLK)
- {
- /* read command length, 2 bytes(1byte for delay), sending in qio
- * mode in cache
- */
-
- SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0),
- SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 15,
- SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S);
-
- /* 0xEB, read command value,(0x00 for delay,0xeb for cmd) */
-
- SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0),
- SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V,
- ((PSRAM_FAST_READ_QUAD) << 8),
- SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S);
-
- /* write command length,2 bytes(1byte for delay,send in qio mode
- * in cache)
- */
-
- SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0),
- SPI_CACHE_SRAM_USR_WR_CMD_BITLEN, 15,
- SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S);
-
- /* 0x38, write command value,(0x00 for delay) */
-
- SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0),
- SPI_CACHE_SRAM_USR_WR_CMD_VALUE,
- ((PSRAM_QUAD_WRITE) << 8),
- SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S);
-
- /* dummy, psram cache : 40m--+1dummy; 80m--+2dummy */
-
- SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0),
- SPI_SRAM_DUMMY_CYCLELEN_V,
- PSRAM_FAST_READ_QUAD_DUMMY + extra_dummy,
- SPI_SRAM_DUMMY_CYCLELEN_S);
- }
- break;
- }
-
- modifyreg32(DPORT_PRO_CACHE_CTRL_REG,
- DPORT_PRO_DRAM_HL | DPORT_PRO_DRAM_SPLIT, 0);
- modifyreg32(DPORT_APP_CACHE_CTRL_REG,
- DPORT_APP_DRAM_HL | DPORT_APP_DRAM_SPLIT, 0);
- if (vaddrmode == PSRAM_VADDR_MODE_LOWHIGH)
- {
- modifyreg32(DPORT_PRO_CACHE_CTRL_REG, 0, DPORT_PRO_DRAM_HL);
- modifyreg32(DPORT_APP_CACHE_CTRL_REG, 0, DPORT_APP_DRAM_HL);
- }
- else
- {
- if (vaddrmode == PSRAM_VADDR_MODE_EVENODD)
- {
- modifyreg32(DPORT_PRO_CACHE_CTRL_REG, 0, DPORT_PRO_DRAM_SPLIT);
- modifyreg32(DPORT_APP_CACHE_CTRL_REG, 0, DPORT_APP_DRAM_SPLIT);
- }
- }
-
- /* use Dram1 to visit ext sram. */
-
- modifyreg32(DPORT_PRO_CACHE_CTRL1_REG,
- DPORT_PRO_CACHE_MASK_DRAM1 | DPORT_PRO_CACHE_MASK_OPSDRAM, 0);
-
- /* cache page mode :
- * 1 -->16k
- * 4 -->2k
- * 0 -->32k,(accord with the settings in cache_sram_mmu_set)
- */
-
- /* get into unknown exception if not comment */
-
- regval = getreg32(DPORT_PRO_CACHE_CTRL1_REG);
- regval &= ~(DPORT_PRO_CMMU_SRAM_PAGE_MODE <<
- DPORT_PRO_CMMU_SRAM_PAGE_MODE_S);
- putreg32(regval, DPORT_PRO_CACHE_CTRL1_REG);
-
- /* use DRAM1 to visit ext sram. */
-
- modifyreg32(DPORT_APP_CACHE_CTRL1_REG,
- DPORT_APP_CACHE_MASK_DRAM1 |
- DPORT_APP_CACHE_MASK_OPSDRAM, 0);
-
- /* cache page mode :
- * 1 -->16k
- * 4 -->2k
- * 0 -->32k, (accord with the settings in cache_sram_mmu_set)
- */
-
- regval = getreg32(DPORT_APP_CACHE_CTRL1_REG);
- regval &= ~(DPORT_APP_CMMU_SRAM_PAGE_MODE <<
- DPORT_APP_CMMU_SRAM_PAGE_MODE_S);
- putreg32(regval, DPORT_APP_CACHE_CTRL1_REG);
-
- /* ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM) */
-
- modifyreg32(SPI_PIN_REG(0), SPI_CS1_DIS_M, 0);
-}
-
#endif /* CONFIG_ESP32_SPIRAM */
diff --git a/arch/xtensa/src/esp32/esp32_psram.h b/arch/xtensa/src/esp32/esp32_psram.h
index abb5cba..c081d0d 100644
--- a/arch/xtensa/src/esp32/esp32_psram.h
+++ b/arch/xtensa/src/esp32/esp32_psram.h
@@ -22,7 +22,7 @@
#define __ARCH_XTENSA_SRC_ESP32_ESP32_PSRAM_H
/****************************************************************************
- * Included Files
+ * Pre-processor Definitions
****************************************************************************/
#define PSRAM_CACHE_F80M_S40M 0
@@ -55,6 +55,10 @@
* odd ones.
*/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
+
/* Description: Get PSRAM size
* return:
* - PSRAM_SIZE_MAX if psram not enabled or not valid
diff --git a/arch/xtensa/src/esp32/esp32_spiram.c b/arch/xtensa/src/esp32/esp32_spiram.c
index c6eef15..c2b9f35 100644
--- a/arch/xtensa/src/esp32/esp32_spiram.c
+++ b/arch/xtensa/src/esp32/esp32_spiram.c
@@ -57,10 +57,6 @@
#endif
#endif
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
/* Let's to assume SPIFLASH SPEED == SPIRAM SPEED for now */
#if defined(CONFIG_ESP32_SPIRAM_SPEED_40M)
@@ -71,12 +67,12 @@
# error "FLASH speed can only be equal to or higher than SRAM speed while SRAM is enabled!"
#endif
-static bool spiram_inited = false;
-
/****************************************************************************
- * Private Functions
+ * Private Data
****************************************************************************/
+static bool spiram_inited = false;
+
/****************************************************************************
* Public Functions
****************************************************************************/
diff --git a/arch/xtensa/src/esp32/esp32_spiram.h b/arch/xtensa/src/esp32/esp32_spiram.h
index 28734a9..3ae3e27 100644
--- a/arch/xtensa/src/esp32/esp32_spiram.h
+++ b/arch/xtensa/src/esp32/esp32_spiram.h
@@ -30,6 +30,10 @@
#include <stdbool.h>
#include "xtensa_attr.h"
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
#define ESP_SPIRAM_SIZE_16MBITS 0 /* SPI RAM size is 16 MBits */
#define ESP_SPIRAM_SIZE_32MBITS 1 /* SPI RAM size is 32 MBits */
#define ESP_SPIRAM_SIZE_64MBITS 2 /* SPI RAM size is 64 MBits */
@@ -74,6 +78,10 @@
#define SRAM_MMU_EDGE_CHECK(mmu_val,num,psize) (((mmu_val) + (num)) > ((8*1024)/(psize)))
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
+
/* Description: get SPI RAM size
* return
* - ESP_SPIRAM_SIZE_INVALID if SPI RAM not enabled or not valid