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Posted to commits@mynewt.apache.org by st...@apache.org on 2016/09/29 01:34:36 UTC
[29/49] incubator-mynewt-core git commit: directory re-org
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/6a7432f4/libs/bootutil/test/src/boot_test.c
----------------------------------------------------------------------
diff --git a/libs/bootutil/test/src/boot_test.c b/libs/bootutil/test/src/boot_test.c
deleted file mode 100644
index 10cd045..0000000
--- a/libs/bootutil/test/src/boot_test.c
+++ /dev/null
@@ -1,1169 +0,0 @@
-/**
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#include <assert.h>
-#include <stddef.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <inttypes.h>
-#include "syscfg/syscfg.h"
-#include "testutil/testutil.h"
-#include "hal/hal_flash.h"
-#include "hal/flash_map.h"
-#include "bootutil/image.h"
-#include "bootutil/loader.h"
-#include "bootutil/bootutil_misc.h"
-#include "../src/bootutil_priv.h"
-
-#include "mbedtls/sha256.h"
-
-#define BOOT_TEST_HEADER_SIZE 0x200
-
-/** Internal flash layout. */
-static struct flash_area boot_test_area_descs[] = {
- [0] = { .fa_off = 0x00020000, .fa_size = 128 * 1024 },
- [1] = { .fa_off = 0x00040000, .fa_size = 128 * 1024 },
- [2] = { .fa_off = 0x00060000, .fa_size = 128 * 1024 },
- [3] = { .fa_off = 0x00080000, .fa_size = 128 * 1024 },
- [4] = { .fa_off = 0x000a0000, .fa_size = 128 * 1024 },
- [5] = { .fa_off = 0x000c0000, .fa_size = 128 * 1024 },
- [6] = { .fa_off = 0x000e0000, .fa_size = 128 * 1024 },
- [7] = { 0 },
-};
-
-/** Areas representing the beginning of image slots. */
-static uint8_t boot_test_slot_areas[] = {
- 0, 3,
-};
-
-/** Flash offsets of the two image slots. */
-static struct {
- uint8_t flash_id;
- uint32_t address;
-} boot_test_img_addrs[] = {
- { 0, 0x20000 },
- { 0, 0x80000 },
-};
-
-#define BOOT_TEST_AREA_IDX_SCRATCH 6
-
-static uint8_t
-boot_test_util_byte_at(int img_msb, uint32_t image_offset)
-{
- uint32_t u32;
- uint8_t *u8p;
-
- TEST_ASSERT(image_offset < 0x01000000);
- u32 = image_offset + (img_msb << 24);
- u8p = (void *)&u32;
- return u8p[image_offset % 4];
-}
-
-static void
-boot_test_util_init_flash(void)
-{
- const struct flash_area *area_desc;
- int rc;
-
- rc = hal_flash_init();
- TEST_ASSERT(rc == 0);
-
- for (area_desc = boot_test_area_descs;
- area_desc->fa_size != 0;
- area_desc++) {
-
- rc = flash_area_erase(area_desc, 0, area_desc->fa_size);
- TEST_ASSERT(rc == 0);
- }
-}
-
-static void
-boot_test_util_copy_area(int from_area_idx, int to_area_idx)
-{
- const struct flash_area *from_area_desc;
- const struct flash_area *to_area_desc;
- void *buf;
- int rc;
-
- from_area_desc = boot_test_area_descs + from_area_idx;
- to_area_desc = boot_test_area_descs + to_area_idx;
-
- TEST_ASSERT(from_area_desc->fa_size == to_area_desc->fa_size);
-
- buf = malloc(from_area_desc->fa_size);
- TEST_ASSERT(buf != NULL);
-
- rc = flash_area_read(from_area_desc, 0, buf,
- from_area_desc->fa_size);
- TEST_ASSERT(rc == 0);
-
- rc = flash_area_erase(to_area_desc,
- 0,
- to_area_desc->fa_size);
- TEST_ASSERT(rc == 0);
-
- rc = flash_area_write(to_area_desc, 0, buf,
- to_area_desc->fa_size);
- TEST_ASSERT(rc == 0);
-
- free(buf);
-}
-
-static void
-boot_test_util_swap_areas(int area_idx1, int area_idx2)
-{
- const struct flash_area *area_desc1;
- const struct flash_area *area_desc2;
- void *buf1;
- void *buf2;
- int rc;
-
- area_desc1 = boot_test_area_descs + area_idx1;
- area_desc2 = boot_test_area_descs + area_idx2;
-
- TEST_ASSERT(area_desc1->fa_size == area_desc2->fa_size);
-
- buf1 = malloc(area_desc1->fa_size);
- TEST_ASSERT(buf1 != NULL);
-
- buf2 = malloc(area_desc2->fa_size);
- TEST_ASSERT(buf2 != NULL);
-
- rc = flash_area_read(area_desc1, 0, buf1, area_desc1->fa_size);
- TEST_ASSERT(rc == 0);
-
- rc = flash_area_read(area_desc2, 0, buf2, area_desc2->fa_size);
- TEST_ASSERT(rc == 0);
-
- rc = flash_area_erase(area_desc1, 0, area_desc1->fa_size);
- TEST_ASSERT(rc == 0);
-
- rc = flash_area_erase(area_desc2, 0, area_desc2->fa_size);
- TEST_ASSERT(rc == 0);
-
- rc = flash_area_write(area_desc1, 0, buf2, area_desc1->fa_size);
- TEST_ASSERT(rc == 0);
-
- rc = flash_area_write(area_desc2, 0, buf1, area_desc2->fa_size);
- TEST_ASSERT(rc == 0);
-
- free(buf1);
- free(buf2);
-}
-
-static void
-boot_test_util_write_image(const struct image_header *hdr, int slot)
-{
- uint32_t image_off;
- uint32_t off;
- uint8_t flash_id;
- uint8_t buf[256];
- int chunk_sz;
- int rc;
- int i;
-
- TEST_ASSERT(slot == 0 || slot == 1);
-
- flash_id = boot_test_img_addrs[slot].flash_id;
- off = boot_test_img_addrs[slot].address;
-
- rc = hal_flash_write(flash_id, off, hdr, sizeof *hdr);
- TEST_ASSERT(rc == 0);
-
- off += hdr->ih_hdr_size;
-
- image_off = 0;
- while (image_off < hdr->ih_img_size) {
- if (hdr->ih_img_size - image_off > sizeof buf) {
- chunk_sz = sizeof buf;
- } else {
- chunk_sz = hdr->ih_img_size - image_off;
- }
-
- for (i = 0; i < chunk_sz; i++) {
- buf[i] = boot_test_util_byte_at(slot, image_off + i);
- }
-
- rc = hal_flash_write(flash_id, off + image_off, buf, chunk_sz);
- TEST_ASSERT(rc == 0);
-
- image_off += chunk_sz;
- }
-}
-
-static void
-boot_test_util_write_hash(const struct image_header *hdr, int slot)
-{
- uint8_t tmpdata[1024];
- uint8_t hash[32];
- int rc;
- uint32_t off;
- uint32_t blk_sz;
- uint32_t sz;
- mbedtls_sha256_context ctx;
- uint8_t flash_id;
- uint32_t addr;
- struct image_tlv tlv;
-
- mbedtls_sha256_init(&ctx);
- mbedtls_sha256_starts(&ctx, 0);
-
- flash_id = boot_test_img_addrs[slot].flash_id;
- addr = boot_test_img_addrs[slot].address;
-
- sz = hdr->ih_hdr_size + hdr->ih_img_size;
- for (off = 0; off < sz; off += blk_sz) {
- blk_sz = sz - off;
- if (blk_sz > sizeof(tmpdata)) {
- blk_sz = sizeof(tmpdata);
- }
- rc = hal_flash_read(flash_id, addr + off, tmpdata, blk_sz);
- TEST_ASSERT(rc == 0);
- mbedtls_sha256_update(&ctx, tmpdata, blk_sz);
- }
- mbedtls_sha256_finish(&ctx, hash);
-
- tlv.it_type = IMAGE_TLV_SHA256;
- tlv._pad = 0;
- tlv.it_len = sizeof(hash);
-
- rc = hal_flash_write(flash_id, addr + off, &tlv, sizeof(tlv));
- TEST_ASSERT(rc == 0);
- off += sizeof(tlv);
- rc = hal_flash_write(flash_id, addr + off, hash, sizeof(hash));
- TEST_ASSERT(rc == 0);
-}
-
-static void
-boot_test_util_verify_area(const struct flash_area *area_desc,
- const struct image_header *hdr,
- uint32_t image_addr, int img_msb)
-{
- struct image_header temp_hdr;
- uint32_t area_end;
- uint32_t img_size;
- uint32_t img_off;
- uint32_t img_end;
- uint32_t addr;
- uint8_t buf[256];
- int rem_area;
- int past_image;
- int chunk_sz;
- int rem_img;
- int rc;
- int i;
-
- addr = area_desc->fa_off;
-
- if (hdr != NULL) {
- img_size = hdr->ih_img_size;
-
- if (addr == image_addr) {
- rc = hal_flash_read(area_desc->fa_flash_id, image_addr,
- &temp_hdr, sizeof temp_hdr);
- TEST_ASSERT(rc == 0);
- TEST_ASSERT(memcmp(&temp_hdr, hdr, sizeof *hdr) == 0);
-
- addr += hdr->ih_hdr_size;
- }
- } else {
- img_size = 0;
- }
-
- area_end = area_desc->fa_off + area_desc->fa_size;
- img_end = image_addr + img_size;
- past_image = addr >= img_end;
-
- while (addr < area_end) {
- rem_area = area_end - addr;
- rem_img = img_end - addr;
-
- if (hdr != NULL) {
- img_off = addr - image_addr - hdr->ih_hdr_size;
- } else {
- img_off = 0;
- }
-
- if (rem_area > sizeof buf) {
- chunk_sz = sizeof buf;
- } else {
- chunk_sz = rem_area;
- }
-
- rc = hal_flash_read(area_desc->fa_flash_id, addr, buf, chunk_sz);
- TEST_ASSERT(rc == 0);
-
- for (i = 0; i < chunk_sz; i++) {
- if (rem_img > 0) {
- TEST_ASSERT(buf[i] == boot_test_util_byte_at(img_msb,
- img_off + i));
- } else if (past_image) {
-#if 0
- TEST_ASSERT(buf[i] == 0xff);
-#endif
- }
- }
-
- addr += chunk_sz;
- }
-}
-
-static void
-boot_test_util_verify_status_clear(void)
-{
- struct boot_img_trailer bit;
- const struct flash_area *fap;
- int rc;
-
- rc = flash_area_open(FLASH_AREA_IMAGE_0, &fap);
- TEST_ASSERT(rc == 0);
-
- rc = flash_area_read(fap, fap->fa_size - sizeof(bit), &bit, sizeof(bit));
- TEST_ASSERT(rc == 0);
-
- TEST_ASSERT(bit.bit_copy_start != BOOT_IMG_MAGIC ||
- bit.bit_copy_done != 0xff);
-}
-
-static void
-boot_test_util_verify_flash(const struct image_header *hdr0, int orig_slot_0,
- const struct image_header *hdr1, int orig_slot_1)
-{
- const struct flash_area *area_desc;
- int area_idx;
-
- area_idx = 0;
-
- while (1) {
- area_desc = boot_test_area_descs + area_idx;
- if (area_desc->fa_off == boot_test_img_addrs[1].address &&
- area_desc->fa_flash_id == boot_test_img_addrs[1].flash_id) {
- break;
- }
-
- boot_test_util_verify_area(area_desc, hdr0,
- boot_test_img_addrs[0].address, orig_slot_0);
- area_idx++;
- }
-
- while (1) {
- if (area_idx == BOOT_TEST_AREA_IDX_SCRATCH) {
- break;
- }
-
- area_desc = boot_test_area_descs + area_idx;
- boot_test_util_verify_area(area_desc, hdr1,
- boot_test_img_addrs[1].address, orig_slot_1);
- area_idx++;
- }
-}
-
-TEST_CASE(boot_test_nv_ns_10)
-{
- struct boot_rsp rsp;
- int rc;
-
- struct image_header hdr = {
- .ih_magic = IMAGE_MAGIC,
- .ih_tlv_size = 4 + 32,
- .ih_hdr_size = BOOT_TEST_HEADER_SIZE,
- .ih_img_size = 12 * 1024,
- .ih_flags = IMAGE_F_SHA256,
- .ih_ver = { 0, 2, 3, 4 },
- };
-
- struct boot_req req = {
- .br_area_descs = boot_test_area_descs,
- .br_slot_areas = boot_test_slot_areas,
- .br_num_image_areas = BOOT_TEST_AREA_IDX_SCRATCH + 1,
- .br_scratch_area_idx = BOOT_TEST_AREA_IDX_SCRATCH,
- .br_img_sz = (384 * 1024),
- };
-
- boot_test_util_init_flash();
- boot_test_util_write_image(&hdr, 0);
- boot_test_util_write_hash(&hdr, 0);
-
- rc = boot_go(&req, &rsp);
- TEST_ASSERT(rc == 0);
-
- TEST_ASSERT(memcmp(rsp.br_hdr, &hdr, sizeof hdr) == 0);
- TEST_ASSERT(rsp.br_flash_id == boot_test_img_addrs[0].flash_id);
- TEST_ASSERT(rsp.br_image_addr == boot_test_img_addrs[0].address);
-
- boot_test_util_verify_flash(&hdr, 0, NULL, 0xff);
- boot_test_util_verify_status_clear();
-}
-
-TEST_CASE(boot_test_nv_ns_01)
-{
- struct boot_rsp rsp;
- int rc;
-
-
- struct image_header hdr = {
- .ih_magic = IMAGE_MAGIC,
- .ih_tlv_size = 4 + 32,
- .ih_hdr_size = BOOT_TEST_HEADER_SIZE,
- .ih_img_size = 10 * 1024,
- .ih_flags = IMAGE_F_SHA256,
- .ih_ver = { 1, 2, 3, 432 },
- };
-
- struct boot_req req = {
- .br_area_descs = boot_test_area_descs,
- .br_slot_areas = boot_test_slot_areas,
- .br_num_image_areas = BOOT_TEST_AREA_IDX_SCRATCH + 1,
- .br_scratch_area_idx = BOOT_TEST_AREA_IDX_SCRATCH,
- .br_img_sz = (384 * 1024),
- };
-
- boot_test_util_init_flash();
- boot_test_util_write_image(&hdr, 1);
- boot_test_util_write_hash(&hdr, 1);
-
- boot_vect_write_test(FLASH_AREA_IMAGE_1);
- rc = boot_go(&req, &rsp);
- TEST_ASSERT(rc == 0);
-
- TEST_ASSERT(memcmp(rsp.br_hdr, &hdr, sizeof hdr) == 0);
- TEST_ASSERT(rsp.br_flash_id == boot_test_img_addrs[0].flash_id);
- TEST_ASSERT(rsp.br_image_addr == boot_test_img_addrs[0].address);
-
- boot_test_util_verify_flash(&hdr, 1, NULL, 0xff);
- boot_test_util_verify_status_clear();
-}
-
-TEST_CASE(boot_test_nv_ns_11)
-{
- struct boot_rsp rsp;
- int rc;
-
- struct image_header hdr0 = {
- .ih_magic = IMAGE_MAGIC,
- .ih_tlv_size = 4 + 32,
- .ih_hdr_size = BOOT_TEST_HEADER_SIZE,
- .ih_img_size = 5 * 1024,
- .ih_flags = IMAGE_F_SHA256,
- .ih_ver = { 0, 5, 21, 432 },
- };
-
- struct image_header hdr1 = {
- .ih_magic = IMAGE_MAGIC,
- .ih_tlv_size = 4 + 32,
- .ih_hdr_size = BOOT_TEST_HEADER_SIZE,
- .ih_img_size = 32 * 1024,
- .ih_flags = IMAGE_F_SHA256,
- .ih_ver = { 1, 2, 3, 432 },
- };
-
- struct boot_req req = {
- .br_area_descs = boot_test_area_descs,
- .br_slot_areas = boot_test_slot_areas,
- .br_num_image_areas = BOOT_TEST_AREA_IDX_SCRATCH + 1,
- .br_scratch_area_idx = BOOT_TEST_AREA_IDX_SCRATCH,
- .br_img_sz = (384 * 1024),
- };
-
- boot_test_util_init_flash();
- boot_test_util_write_image(&hdr0, 0);
- boot_test_util_write_hash(&hdr0, 0);
- boot_test_util_write_image(&hdr1, 1);
- boot_test_util_write_hash(&hdr1, 1);
-
- rc = boot_go(&req, &rsp);
- TEST_ASSERT(rc == 0);
-
- TEST_ASSERT(memcmp(rsp.br_hdr, &hdr0, sizeof hdr0) == 0);
- TEST_ASSERT(rsp.br_flash_id == boot_test_img_addrs[0].flash_id);
- TEST_ASSERT(rsp.br_image_addr == boot_test_img_addrs[0].address);
-
- boot_test_util_verify_flash(&hdr0, 0, &hdr1, 1);
- boot_test_util_verify_status_clear();
-}
-
-TEST_CASE(boot_test_vm_ns_10)
-{
- struct boot_rsp rsp;
- int rc;
-
-
- struct image_header hdr = {
- .ih_magic = IMAGE_MAGIC,
- .ih_tlv_size = 4 + 32,
- .ih_hdr_size = BOOT_TEST_HEADER_SIZE,
- .ih_img_size = 12 * 1024,
- .ih_flags = IMAGE_F_SHA256,
- .ih_ver = { 0, 2, 3, 4 },
- };
-
- struct boot_req req = {
- .br_area_descs = boot_test_area_descs,
- .br_slot_areas = boot_test_slot_areas,
- .br_num_image_areas = BOOT_TEST_AREA_IDX_SCRATCH + 1,
- .br_scratch_area_idx = BOOT_TEST_AREA_IDX_SCRATCH,
- .br_img_sz = (384 * 1024),
- };
-
- boot_test_util_init_flash();
- boot_test_util_write_image(&hdr, 0);
- boot_test_util_write_hash(&hdr, 0);
-
- rc = boot_go(&req, &rsp);
- TEST_ASSERT(rc == 0);
-
- TEST_ASSERT(memcmp(rsp.br_hdr, &hdr, sizeof hdr) == 0);
- TEST_ASSERT(rsp.br_flash_id == boot_test_img_addrs[0].flash_id);
- TEST_ASSERT(rsp.br_image_addr == boot_test_img_addrs[0].address);
-
- boot_test_util_verify_flash(&hdr, 0, NULL, 0xff);
- boot_test_util_verify_status_clear();
-}
-
-TEST_CASE(boot_test_vm_ns_01)
-{
- struct boot_rsp rsp;
- int rc;
-
- struct image_header hdr = {
- .ih_magic = IMAGE_MAGIC,
- .ih_tlv_size = 4 + 32,
- .ih_hdr_size = BOOT_TEST_HEADER_SIZE,
- .ih_img_size = 10 * 1024,
- .ih_flags = IMAGE_F_SHA256,
- .ih_ver = { 1, 2, 3, 432 },
- };
-
- struct boot_req req = {
- .br_area_descs = boot_test_area_descs,
- .br_slot_areas = boot_test_slot_areas,
- .br_num_image_areas = BOOT_TEST_AREA_IDX_SCRATCH + 1,
- .br_scratch_area_idx = BOOT_TEST_AREA_IDX_SCRATCH,
- .br_img_sz = (384 * 1024),
- };
-
- boot_test_util_init_flash();
- boot_test_util_write_image(&hdr, 1);
- boot_test_util_write_hash(&hdr, 1);
-
- rc = boot_vect_write_test(FLASH_AREA_IMAGE_1);
- TEST_ASSERT(rc == 0);
-
- rc = boot_go(&req, &rsp);
- TEST_ASSERT(rc == 0);
-
- TEST_ASSERT(memcmp(rsp.br_hdr, &hdr, sizeof hdr) == 0);
- TEST_ASSERT(rsp.br_flash_id == boot_test_img_addrs[0].flash_id);
- TEST_ASSERT(rsp.br_image_addr == boot_test_img_addrs[0].address);
-
- boot_test_util_verify_flash(&hdr, 1, NULL, 0xff);
- boot_test_util_verify_status_clear();
-}
-
-TEST_CASE(boot_test_vm_ns_11_a)
-{
- struct boot_rsp rsp;
- int rc;
-
- struct image_header hdr0 = {
- .ih_magic = IMAGE_MAGIC,
- .ih_tlv_size = 4 + 32,
- .ih_hdr_size = BOOT_TEST_HEADER_SIZE,
- .ih_img_size = 5 * 1024,
- .ih_flags = IMAGE_F_SHA256,
- .ih_ver = { 0, 5, 21, 432 },
- };
-
- struct image_header hdr1 = {
- .ih_magic = IMAGE_MAGIC,
- .ih_tlv_size = 4 + 32,
- .ih_hdr_size = BOOT_TEST_HEADER_SIZE,
- .ih_img_size = 32 * 1024,
- .ih_flags = IMAGE_F_SHA256,
- .ih_ver = { 1, 2, 3, 432 },
- };
-
- struct boot_req req = {
- .br_area_descs = boot_test_area_descs,
- .br_slot_areas = boot_test_slot_areas,
- .br_num_image_areas = BOOT_TEST_AREA_IDX_SCRATCH + 1,
- .br_scratch_area_idx = BOOT_TEST_AREA_IDX_SCRATCH,
- .br_img_sz = (384 * 1024),
- };
-
- boot_test_util_init_flash();
- boot_test_util_write_image(&hdr0, 0);
- boot_test_util_write_hash(&hdr0, 0);
- boot_test_util_write_image(&hdr1, 1);
- boot_test_util_write_hash(&hdr1, 1);
-
- rc = boot_go(&req, &rsp);
- TEST_ASSERT(rc == 0);
-
- TEST_ASSERT(memcmp(rsp.br_hdr, &hdr0, sizeof hdr0) == 0);
- TEST_ASSERT(rsp.br_flash_id == boot_test_img_addrs[0].flash_id);
- TEST_ASSERT(rsp.br_image_addr == boot_test_img_addrs[0].address);
-
- boot_test_util_verify_flash(&hdr0, 0, &hdr1, 1);
- boot_test_util_verify_status_clear();
-}
-
-TEST_CASE(boot_test_vm_ns_11_b)
-{
- struct boot_rsp rsp;
- int rc;
-
- struct image_header hdr0 = {
- .ih_magic = IMAGE_MAGIC,
- .ih_tlv_size = 4 + 32,
- .ih_hdr_size = BOOT_TEST_HEADER_SIZE,
- .ih_img_size = 5 * 1024,
- .ih_flags = IMAGE_F_SHA256,
- .ih_ver = { 0, 5, 21, 432 },
- };
-
- struct image_header hdr1 = {
- .ih_magic = IMAGE_MAGIC,
- .ih_tlv_size = 4 + 32,
- .ih_hdr_size = BOOT_TEST_HEADER_SIZE,
- .ih_img_size = 32 * 1024,
- .ih_flags = IMAGE_F_SHA256,
- .ih_ver = { 1, 2, 3, 432 },
- };
-
- struct boot_req req = {
- .br_area_descs = boot_test_area_descs,
- .br_slot_areas = boot_test_slot_areas,
- .br_num_image_areas = BOOT_TEST_AREA_IDX_SCRATCH + 1,
- .br_scratch_area_idx = BOOT_TEST_AREA_IDX_SCRATCH,
- .br_img_sz = (384 * 1024),
- };
-
- boot_test_util_init_flash();
- boot_test_util_write_image(&hdr0, 0);
- boot_test_util_write_hash(&hdr0, 0);
- boot_test_util_write_image(&hdr1, 1);
- boot_test_util_write_hash(&hdr1, 1);
-
- rc = boot_vect_write_test(FLASH_AREA_IMAGE_1);
- TEST_ASSERT(rc == 0);
-
- rc = boot_go(&req, &rsp);
- TEST_ASSERT(rc == 0);
-
- TEST_ASSERT(memcmp(rsp.br_hdr, &hdr1, sizeof hdr1) == 0);
- TEST_ASSERT(rsp.br_flash_id == boot_test_img_addrs[0].flash_id);
- TEST_ASSERT(rsp.br_image_addr == boot_test_img_addrs[0].address);
-
- boot_test_util_verify_flash(&hdr1, 1, &hdr0, 0);
- boot_test_util_verify_status_clear();
-}
-
-TEST_CASE(boot_test_vm_ns_11_2areas)
-{
- struct boot_rsp rsp;
- int rc;
-
- struct image_header hdr0 = {
- .ih_magic = IMAGE_MAGIC,
- .ih_tlv_size = 4 + 32,
- .ih_hdr_size = BOOT_TEST_HEADER_SIZE,
- .ih_img_size = 5 * 1024,
- .ih_flags = IMAGE_F_SHA256,
- .ih_ver = { 0, 5, 21, 432 },
- };
-
- struct image_header hdr1 = {
- .ih_magic = IMAGE_MAGIC,
- .ih_tlv_size = 4 + 32,
- .ih_hdr_size = BOOT_TEST_HEADER_SIZE,
- .ih_img_size = 196 * 1024,
- .ih_flags = IMAGE_F_SHA256,
- .ih_ver = { 1, 2, 3, 432 },
- };
-
- struct boot_req req = {
- .br_area_descs = boot_test_area_descs,
- .br_slot_areas = boot_test_slot_areas,
- .br_num_image_areas = BOOT_TEST_AREA_IDX_SCRATCH + 1,
- .br_scratch_area_idx = BOOT_TEST_AREA_IDX_SCRATCH,
- .br_img_sz = (384 * 1024),
- };
-
- boot_test_util_init_flash();
- boot_test_util_write_image(&hdr0, 0);
- boot_test_util_write_hash(&hdr0, 0);
- boot_test_util_write_image(&hdr1, 1);
- boot_test_util_write_hash(&hdr1, 1);
-
- rc = boot_vect_write_test(FLASH_AREA_IMAGE_1);
- TEST_ASSERT(rc == 0);
-
- rc = boot_go(&req, &rsp);
- TEST_ASSERT(rc == 0);
-
- TEST_ASSERT(memcmp(rsp.br_hdr, &hdr1, sizeof hdr1) == 0);
- TEST_ASSERT(rsp.br_flash_id == boot_test_img_addrs[0].flash_id);
- TEST_ASSERT(rsp.br_image_addr == boot_test_img_addrs[0].address);
-
- boot_test_util_verify_flash(&hdr1, 1, &hdr0, 0);
- boot_test_util_verify_status_clear();
-}
-
-TEST_CASE(boot_test_nv_bs_10)
-{
- struct boot_status status;
- struct boot_rsp rsp;
- int rc;
-
- struct image_header hdr = {
- .ih_magic = IMAGE_MAGIC,
- .ih_tlv_size = 4 + 32,
- .ih_hdr_size = BOOT_TEST_HEADER_SIZE,
- .ih_img_size = 12 * 1024,
- .ih_flags = IMAGE_F_SHA256,
- .ih_ver = { 0, 2, 3, 4 },
- };
-
- struct boot_req req = {
- .br_area_descs = boot_test_area_descs,
- .br_slot_areas = boot_test_slot_areas,
- .br_num_image_areas = BOOT_TEST_AREA_IDX_SCRATCH + 1,
- .br_scratch_area_idx = BOOT_TEST_AREA_IDX_SCRATCH,
- .br_img_sz = (384 * 1024),
- };
-
- boot_test_util_init_flash();
- boot_test_util_write_image(&hdr, 0);
- boot_test_util_write_hash(&hdr, 0);
- boot_test_util_swap_areas(boot_test_slot_areas[1],
- BOOT_TEST_AREA_IDX_SCRATCH);
-#if 0
- status.length = hdr.ih_hdr_size + hdr.ih_img_size + hdr.ih_tlv_size;
- status.state = 1;
-
- rc = boot_write_status(&status);
- TEST_ASSERT(rc == 0);
- conf_load();
-#else
- (void)status;
-#endif
- rc = boot_go(&req, &rsp);
- TEST_ASSERT(rc == 0);
-
- TEST_ASSERT(memcmp(rsp.br_hdr, &hdr, sizeof hdr) == 0);
- TEST_ASSERT(rsp.br_flash_id == boot_test_img_addrs[0].flash_id);
- TEST_ASSERT(rsp.br_image_addr == boot_test_img_addrs[0].address);
-
- boot_test_util_verify_flash(&hdr, 0, NULL, 0xff);
- boot_test_util_verify_status_clear();
-}
-
-TEST_CASE(boot_test_nv_bs_11)
-{
- struct boot_status status;
- struct boot_rsp rsp;
- int rc;
-
- struct image_header hdr0 = {
- .ih_magic = IMAGE_MAGIC,
- .ih_tlv_size = 4 + 32,
- .ih_hdr_size = BOOT_TEST_HEADER_SIZE,
- .ih_img_size = 12 * 1024,
- .ih_flags = IMAGE_F_SHA256,
- .ih_ver = { 0, 2, 3, 4 },
- };
-
- struct image_header hdr1 = {
- .ih_magic = IMAGE_MAGIC,
- .ih_tlv_size = 4 + 32,
- .ih_hdr_size = BOOT_TEST_HEADER_SIZE,
- .ih_img_size = 17 * 1024,
- .ih_flags = IMAGE_F_SHA256,
- .ih_ver = { 1, 1, 5, 5 },
- };
-
- struct boot_req req = {
- .br_area_descs = boot_test_area_descs,
- .br_slot_areas = boot_test_slot_areas,
- .br_num_image_areas = BOOT_TEST_AREA_IDX_SCRATCH + 1,
- .br_scratch_area_idx = BOOT_TEST_AREA_IDX_SCRATCH,
- .br_img_sz = (384 * 1024),
- };
-
- boot_test_util_init_flash();
- boot_test_util_write_image(&hdr0, 0);
- boot_test_util_write_hash(&hdr0, 0);
- boot_test_util_write_image(&hdr1, 1);
- boot_test_util_write_hash(&hdr1, 1);
- rc = boot_vect_write_test(FLASH_AREA_IMAGE_1);
- boot_test_util_copy_area(5,
- BOOT_TEST_AREA_IDX_SCRATCH);
-
- boot_req_set(&req);
- status.idx = 0;
- status.elem_sz = 1;
- status.state = 1;
-
- rc = boot_write_status(&status);
- TEST_ASSERT(rc == 0);
-
- rc = boot_go(&req, &rsp);
- TEST_ASSERT(rc == 0);
-
- TEST_ASSERT(memcmp(rsp.br_hdr, &hdr1, sizeof hdr1) == 0);
- TEST_ASSERT(rsp.br_flash_id == boot_test_img_addrs[0].flash_id);
- TEST_ASSERT(rsp.br_image_addr == boot_test_img_addrs[0].address);
-
- boot_test_util_verify_flash(&hdr1, 1, &hdr0, 0);
- boot_test_util_verify_status_clear();
-}
-
-TEST_CASE(boot_test_nv_bs_11_2areas)
-{
- struct boot_status status;
- struct boot_rsp rsp;
- int rc;
-
- struct image_header hdr0 = {
- .ih_magic = IMAGE_MAGIC,
- .ih_tlv_size = 4 + 32,
- .ih_hdr_size = BOOT_TEST_HEADER_SIZE,
- .ih_img_size = 150 * 1024,
- .ih_flags = IMAGE_F_SHA256,
- .ih_ver = { 0, 5, 21, 432 },
- };
-
- struct image_header hdr1 = {
- .ih_magic = IMAGE_MAGIC,
- .ih_tlv_size = 4 + 32,
- .ih_hdr_size = BOOT_TEST_HEADER_SIZE,
- .ih_img_size = 190 * 1024,
- .ih_flags = IMAGE_F_SHA256,
- .ih_ver = { 1, 2, 3, 432 },
- };
-
- struct boot_req req = {
- .br_area_descs = boot_test_area_descs,
- .br_slot_areas = boot_test_slot_areas,
- .br_num_image_areas = BOOT_TEST_AREA_IDX_SCRATCH + 1,
- .br_scratch_area_idx = BOOT_TEST_AREA_IDX_SCRATCH,
- .br_img_sz = (384 * 1024),
- };
-
- boot_test_util_init_flash();
- boot_test_util_write_image(&hdr0, 0);
- boot_test_util_write_hash(&hdr0, 0);
- boot_test_util_write_image(&hdr1, 1);
- boot_test_util_write_hash(&hdr1, 1);
- rc = boot_vect_write_test(FLASH_AREA_IMAGE_1);
-
- boot_test_util_swap_areas(2, 5);
-
- status.idx = 1;
- status.elem_sz = 1;
- status.state = 0;
-
- rc = boot_write_status(&status);
- TEST_ASSERT(rc == 0);
-
- rc = boot_go(&req, &rsp);
- TEST_ASSERT(rc == 0);
-
- TEST_ASSERT(memcmp(rsp.br_hdr, &hdr1, sizeof hdr1) == 0);
- TEST_ASSERT(rsp.br_flash_id == boot_test_img_addrs[0].flash_id);
- TEST_ASSERT(rsp.br_image_addr == boot_test_img_addrs[0].address);
-
- boot_test_util_verify_flash(&hdr1, 1, &hdr0, 0);
- boot_test_util_verify_status_clear();
-}
-
-TEST_CASE(boot_test_vb_ns_11)
-{
- const struct flash_area *fap;
- struct boot_img_trailer bit;
- struct boot_rsp rsp;
- int rc;
- int i;
-
- struct image_header hdr0 = {
- .ih_magic = IMAGE_MAGIC,
- .ih_tlv_size = 4 + 32,
- .ih_hdr_size = BOOT_TEST_HEADER_SIZE,
- .ih_img_size = 5 * 1024,
- .ih_flags = IMAGE_F_SHA256,
- .ih_ver = { 0, 5, 21, 432 },
- };
-
- struct image_header hdr1 = {
- .ih_magic = IMAGE_MAGIC,
- .ih_tlv_size = 4 + 32,
- .ih_hdr_size = BOOT_TEST_HEADER_SIZE,
- .ih_img_size = 32 * 1024,
- .ih_flags = IMAGE_F_SHA256,
- .ih_ver = { 1, 2, 3, 432 },
- };
-
- struct boot_req req = {
- .br_area_descs = boot_test_area_descs,
- .br_slot_areas = boot_test_slot_areas,
- .br_num_image_areas = BOOT_TEST_AREA_IDX_SCRATCH + 1,
- .br_scratch_area_idx = BOOT_TEST_AREA_IDX_SCRATCH,
- .br_img_sz = (384 * 1024),
- };
-
- boot_test_util_init_flash();
- boot_test_util_write_image(&hdr0, 0);
- boot_test_util_write_hash(&hdr0, 0);
- boot_test_util_write_image(&hdr1, 1);
- boot_test_util_write_hash(&hdr1, 1);
-
- rc = flash_area_open(FLASH_AREA_IMAGE_0, &fap);
- TEST_ASSERT(rc == 0);
-
- memset(&bit, 0xff, sizeof(bit));
- bit.bit_copy_start = BOOT_IMG_MAGIC;
- bit.bit_copy_done = 0;
- bit.bit_img_ok = 1;
-
- rc = flash_area_write(fap, fap->fa_size - sizeof(bit), &bit, sizeof(bit));
- TEST_ASSERT(rc == 0);
-
- rc = boot_vect_write_test(FLASH_AREA_IMAGE_1);
- TEST_ASSERT(rc == 0);
-
- /* First boot should use the test image. */
- rc = boot_go(&req, &rsp);
- TEST_ASSERT(rc == 0);
-
- TEST_ASSERT(memcmp(rsp.br_hdr, &hdr1, sizeof hdr1) == 0);
- TEST_ASSERT(rsp.br_flash_id == boot_test_img_addrs[0].flash_id);
- TEST_ASSERT(rsp.br_image_addr == boot_test_img_addrs[0].address);
-
- boot_test_util_verify_flash(&hdr1, 1, &hdr0, 0);
- boot_test_util_verify_status_clear();
-
- /* Ensure all subsequent boots use the main image. */
- for (i = 0; i < 10; i++) {
- rc = boot_go(&req, &rsp);
- TEST_ASSERT(rc == 0);
-
- TEST_ASSERT(memcmp(rsp.br_hdr, &hdr0, sizeof hdr0) == 0);
- TEST_ASSERT(rsp.br_flash_id == boot_test_img_addrs[0].flash_id);
- TEST_ASSERT(rsp.br_image_addr == boot_test_img_addrs[0].address);
-
- boot_test_util_verify_flash(&hdr0, 0, &hdr1, 1);
- boot_test_util_verify_status_clear();
- boot_vect_write_main();
- }
-}
-
-TEST_CASE(boot_test_no_hash)
-{
- struct boot_rsp rsp;
- int rc;
-
- struct image_header hdr0 = {
- .ih_magic = IMAGE_MAGIC,
- .ih_tlv_size = 4 + 32,
- .ih_hdr_size = BOOT_TEST_HEADER_SIZE,
- .ih_img_size = 12 * 1024,
- .ih_flags = IMAGE_F_SHA256,
- .ih_ver = { 0, 2, 3, 4 },
- };
- struct image_header hdr1 = {
- .ih_magic = IMAGE_MAGIC,
- .ih_tlv_size = 0,
- .ih_hdr_size = BOOT_TEST_HEADER_SIZE,
- .ih_img_size = 32 * 1024,
- .ih_flags = 0,
- .ih_ver = { 1, 2, 3, 432 },
- };
-
- struct boot_req req = {
- .br_area_descs = boot_test_area_descs,
- .br_slot_areas = boot_test_slot_areas,
- .br_num_image_areas = BOOT_TEST_AREA_IDX_SCRATCH + 1,
- .br_scratch_area_idx = BOOT_TEST_AREA_IDX_SCRATCH,
- .br_img_sz = (384 * 1024),
- };
-
- boot_test_util_init_flash();
- boot_test_util_write_image(&hdr0, 0);
- boot_test_util_write_hash(&hdr0, 0);
- boot_test_util_write_image(&hdr1, 1);
-
- rc = boot_vect_write_test(FLASH_AREA_IMAGE_1);
- TEST_ASSERT(rc == 0);
-
- rc = boot_go(&req, &rsp);
- TEST_ASSERT(rc == 0);
-
- TEST_ASSERT(memcmp(rsp.br_hdr, &hdr0, sizeof hdr0) == 0);
-
- boot_test_util_verify_flash(&hdr0, 0, NULL, 0xff);
- boot_test_util_verify_status_clear();
-}
-
-TEST_CASE(boot_test_no_flag_has_hash)
-{
- struct boot_rsp rsp;
- int rc;
-
- struct image_header hdr0 = {
- .ih_magic = IMAGE_MAGIC,
- .ih_tlv_size = 4 + 32,
- .ih_hdr_size = BOOT_TEST_HEADER_SIZE,
- .ih_img_size = 12 * 1024,
- .ih_flags = IMAGE_F_SHA256,
- .ih_ver = { 0, 2, 3, 4 },
- };
- struct image_header hdr1 = {
- .ih_magic = IMAGE_MAGIC,
- .ih_tlv_size = 4 + 32,
- .ih_hdr_size = BOOT_TEST_HEADER_SIZE,
- .ih_img_size = 32 * 1024,
- .ih_flags = 0,
- .ih_ver = { 1, 2, 3, 432 },
- };
-
- struct boot_req req = {
- .br_area_descs = boot_test_area_descs,
- .br_slot_areas = boot_test_slot_areas,
- .br_num_image_areas = BOOT_TEST_AREA_IDX_SCRATCH + 1,
- .br_scratch_area_idx = BOOT_TEST_AREA_IDX_SCRATCH,
- .br_img_sz = (384 * 1024),
- };
-
- boot_test_util_init_flash();
- boot_test_util_write_image(&hdr0, 0);
- boot_test_util_write_hash(&hdr0, 0);
- boot_test_util_write_image(&hdr1, 1);
- boot_test_util_write_hash(&hdr1, 1);
-
- rc = boot_vect_write_test(FLASH_AREA_IMAGE_1);
- TEST_ASSERT(rc == 0);
-
- rc = boot_go(&req, &rsp);
- TEST_ASSERT(rc == 0);
-
- TEST_ASSERT(memcmp(rsp.br_hdr, &hdr0, sizeof hdr0) == 0);
-
- boot_test_util_verify_flash(&hdr0, 0, NULL, 0xff);
- boot_test_util_verify_status_clear();
-}
-
-TEST_CASE(boot_test_invalid_hash)
-{
- struct boot_rsp rsp;
- int rc;
-
- struct image_header hdr0 = {
- .ih_magic = IMAGE_MAGIC,
- .ih_tlv_size = 4 + 32,
- .ih_hdr_size = BOOT_TEST_HEADER_SIZE,
- .ih_img_size = 12 * 1024,
- .ih_flags = IMAGE_F_SHA256,
- .ih_ver = { 0, 2, 3, 4 },
- };
- struct image_header hdr1 = {
- .ih_magic = IMAGE_MAGIC,
- .ih_tlv_size = 4 + 32,
- .ih_hdr_size = BOOT_TEST_HEADER_SIZE,
- .ih_img_size = 32 * 1024,
- .ih_flags = 0,
- .ih_ver = { 1, 2, 3, 432 },
- };
-
- struct boot_req req = {
- .br_area_descs = boot_test_area_descs,
- .br_slot_areas = boot_test_slot_areas,
- .br_num_image_areas = BOOT_TEST_AREA_IDX_SCRATCH + 1,
- .br_scratch_area_idx = BOOT_TEST_AREA_IDX_SCRATCH,
- .br_img_sz = (384 * 1024),
- };
-
- struct image_tlv tlv = {
- .it_type = IMAGE_TLV_SHA256,
- .it_len = 32
- };
- boot_test_util_init_flash();
- boot_test_util_write_image(&hdr0, 0);
- boot_test_util_write_hash(&hdr0, 0);
- boot_test_util_write_image(&hdr1, 1);
- rc = hal_flash_write(boot_test_img_addrs[1].flash_id,
- boot_test_img_addrs[1].address + hdr1.ih_hdr_size + hdr1.ih_img_size,
- &tlv, sizeof(tlv));
- TEST_ASSERT(rc == 0);
-
- rc = boot_vect_write_test(FLASH_AREA_IMAGE_1);
- TEST_ASSERT(rc == 0);
-
- rc = boot_go(&req, &rsp);
- TEST_ASSERT(rc == 0);
-
- TEST_ASSERT(memcmp(rsp.br_hdr, &hdr0, sizeof hdr0) == 0);
-
- boot_test_util_verify_flash(&hdr0, 0, NULL, 0xff);
- boot_test_util_verify_status_clear();
-}
-
-TEST_SUITE(boot_test_main)
-{
- boot_test_nv_ns_10();
- boot_test_nv_ns_01();
- boot_test_nv_ns_11();
- boot_test_vm_ns_10();
- boot_test_vm_ns_01();
- boot_test_vm_ns_11_a();
- boot_test_vm_ns_11_b();
- boot_test_vm_ns_11_2areas();
- boot_test_nv_bs_10();
- boot_test_nv_bs_11();
- boot_test_nv_bs_11_2areas();
- boot_test_vb_ns_11();
- boot_test_no_hash();
- boot_test_no_flag_has_hash();
- boot_test_invalid_hash();
-}
-
-int
-boot_test_all(void)
-{
- boot_test_main();
- return tu_any_failed;
-}
-
-#if MYNEWT_VAL(SELFTEST)
-
-int
-main(int argc, char **argv)
-{
- tu_config.tc_print_results = 1;
- tu_parse_args(argc, argv);
-
- tu_init();
-
- boot_test_all();
-
- return tu_any_failed;
-}
-
-#endif
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/6a7432f4/libs/cmsis-core/pkg.yml
----------------------------------------------------------------------
diff --git a/libs/cmsis-core/pkg.yml b/libs/cmsis-core/pkg.yml
deleted file mode 100644
index 7c3d5de..0000000
--- a/libs/cmsis-core/pkg.yml
+++ /dev/null
@@ -1,27 +0,0 @@
-#
-# Licensed to the Apache Software Foundation (ASF) under one
-# or more contributor license agreements. See the NOTICE file
-# distributed with this work for additional information
-# regarding copyright ownership. The ASF licenses this file
-# to you under the Apache License, Version 2.0 (the
-# "License"); you may not use this file except in compliance
-# with the License. You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing,
-# software distributed under the License is distributed on an
-# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
-# KIND, either express or implied. See the License for the
-# specific language governing permissions and limitations
-# under the License.
-#
-
-pkg.name: libs/cmsis-core
-pkg.description: CMSIS-CORE abstraction layer for Cortex-M processors.
-pkg.author: "Keil"
-pkg.homepage: "http://www.keil.com/pack/doc/CMSIS/Core/html/index.html"
-pkg.keywords:
- - cmsis
- - core
-pkg.type: sdk
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/6a7432f4/libs/cmsis-core/src/cmsis_nvic.c
----------------------------------------------------------------------
diff --git a/libs/cmsis-core/src/cmsis_nvic.c b/libs/cmsis-core/src/cmsis_nvic.c
deleted file mode 100644
index a350791..0000000
--- a/libs/cmsis-core/src/cmsis_nvic.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/* mbed Microcontroller Library - cmsis_nvic for XXXX
- * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
- *
- * CMSIS-style functionality to support dynamic vectors
- */
-#include "bsp/cmsis_nvic.h"
-
-#ifndef __CORTEX_M
- #error "Macro __CORTEX_M not defined; must define cortex-m type!"
-#endif
-
-#if (__CORTEX_M == 0)
- #ifndef __VTOR_PRESENT
- /* no VTOR is defined so we assume we can't relocate the vector table */
- #define __VTOR_PRESENT (0)
-#endif
-#endif
-
-extern char __isr_vector[];
-extern char __vector_tbl_reloc__[];
-
-void
-NVIC_Relocate(void)
-{
- uint32_t *current_location;
- uint32_t *new_location;
- int i;
-
- /*
- * Relocate the vector table from its current position to the position
- * designated in the linker script.
- */
- current_location = (uint32_t *)&__isr_vector;
- new_location = (uint32_t *)&__vector_tbl_reloc__;
-
- if (new_location != current_location) {
- for (i = 0; i < NVIC_NUM_VECTORS; i++) {
- new_location[i] = current_location[i];
- }
- }
-
- /* Set VTOR except for M0 */
-#if ((__CORTEX_M == 0) && (__VTOR_PRESENT == 0))
-#else
- SCB->VTOR = (uint32_t)&__vector_tbl_reloc__;
-#endif
-}
-
-void
-NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
- uint32_t *vectors;
-#if ((__CORTEX_M == 0) && (__VTOR_PRESENT == 0))
- vectors = (uint32_t *)&__vector_tbl_reloc__;
-#else
- vectors = (uint32_t *)SCB->VTOR;
-#endif
- vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
- __DMB();
-}
-
-uint32_t
-NVIC_GetVector(IRQn_Type IRQn)
-{
- uint32_t *vectors;
-#if (__CORTEX_M == 0)
- vectors = (uint32_t *)&__vector_tbl_reloc__;
-#else
- vectors = (uint32_t*)SCB->VTOR;
-#endif
- return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/6a7432f4/libs/cmsis-core/src/ext/core_ca9.h
----------------------------------------------------------------------
diff --git a/libs/cmsis-core/src/ext/core_ca9.h b/libs/cmsis-core/src/ext/core_ca9.h
deleted file mode 100644
index bae5f65..0000000
--- a/libs/cmsis-core/src/ext/core_ca9.h
+++ /dev/null
@@ -1,271 +0,0 @@
-/**************************************************************************//**
- * @file core_ca9.h
- * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
- * @version
- * @date 25 March 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2012 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CA9_H_GENERIC
-#define __CORE_CA9_H_GENERIC
-
-
-/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_A9
- @{
- */
-
-/* CMSIS CA9 definitions */
-#define __CA9_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
-#define __CA9_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
-#define __CA9_CMSIS_VERSION ((__CA9_CMSIS_VERSION_MAIN << 16) | \
- __CA9_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_A (0x09) /*!< Cortex-A Core */
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
- #define __STATIC_ASM static __asm
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
- #define __STATIC_INLINE static inline
- #define __STATIC_ASM static __asm
-
-#elif defined ( __TMS470__ )
- #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
- #define __STATIC_INLINE static inline
- #define __STATIC_ASM static __asm
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
- #define __STATIC_INLINE static inline
- #define __STATIC_ASM static __asm
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
- #define __STATIC_INLINE static inline
- #define __STATIC_ASM static __asm
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __TMS470__ )
- #if defined __TI_VFP_SUPPORT__
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-#endif
-
-#include <stdint.h> /*!< standard types definitions */
-#include "core_caInstr.h" /*!< Core Instruction Access */
-#include "core_caFunc.h" /*!< Core Function Access */
-#include "core_cm4_simd.h" /*!< Compiler specific SIMD Intrinsics */
-
-#endif /* __CORE_CA9_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CA9_H_DEPENDANT
-#define __CORE_CA9_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CA9_REV
- #define __CA9_REV 0x0000
- #warning "__CA9_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __FPU_PRESENT
- #define __FPU_PRESENT 1
- #warning "__FPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 1
- #endif
-
- #if __Vendor_SysTickConfig == 0
- #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/*@} end of group Cortex_A9 */
-
-
-/*******************************************************************************
- * Register Abstraction
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-A processor based devices.
-*/
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/** \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t reserved1:7; /*!< bit: 20..23 Reserved */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-
-/*@} end of group CMSIS_CORE */
-
-/*@} end of CMSIS_Core_FPUFunctions */
-
-
-#endif /* __CORE_CA9_H_GENERIC */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-
-
-#endif
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/6a7432f4/libs/cmsis-core/src/ext/core_caFunc.h
----------------------------------------------------------------------
diff --git a/libs/cmsis-core/src/ext/core_caFunc.h b/libs/cmsis-core/src/ext/core_caFunc.h
deleted file mode 100644
index 3f40094..0000000
--- a/libs/cmsis-core/src/ext/core_caFunc.h
+++ /dev/null
@@ -1,1161 +0,0 @@
-/**************************************************************************//**
- * @file core_caFunc.h
- * @brief CMSIS Cortex-A Core Function Access Header File
- * @version V3.10
- * @date 9 May 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2012 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CAFUNC_H__
-#define __CORE_CAFUNC_H__
-
-
-/* ########################### Core Function Access ########################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
- @{
- */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-#define MODE_USR 0x10
-#define MODE_FIQ 0x11
-#define MODE_IRQ 0x12
-#define MODE_SVC 0x13
-#define MODE_MON 0x16
-#define MODE_ABT 0x17
-#define MODE_HYP 0x1A
-#define MODE_UND 0x1B
-#define MODE_SYS 0x1F
-
-/** \brief Get APSR Register
-
- This function returns the content of the APSR Register.
-
- \return APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
- register uint32_t __regAPSR __ASM("apsr");
- return(__regAPSR);
-}
-
-
-/** \brief Get CPSR Register
-
- This function returns the content of the CPSR Register.
-
- \return CPSR Register value
- */
-__STATIC_INLINE uint32_t __get_CPSR(void)
-{
- register uint32_t __regCPSR __ASM("cpsr");
- return(__regCPSR);
-}
-
-/** \brief Set Stack Pointer
-
- This function assigns the given value to the current stack pointer.
-
- \param [in] topOfStack Stack Pointer value to set
- */
-register uint32_t __regSP __ASM("sp");
-__STATIC_INLINE void __set_SP(uint32_t topOfStack)
-{
- __regSP = topOfStack;
-}
-
-
-/** \brief Get link register
-
- This function returns the value of the link register
-
- \return Value of link register
- */
-register uint32_t __reglr __ASM("lr");
-__STATIC_INLINE uint32_t __get_LR(void)
-{
- return(__reglr);
-}
-
-/** \brief Set link register
-
- This function sets the value of the link register
-
- \param [in] lr LR value to set
- */
-__STATIC_INLINE void __set_LR(uint32_t lr)
-{
- __reglr = lr;
-}
-
-/** \brief Set Process Stack Pointer
-
- This function assigns the given value to the USR/SYS Stack Pointer (PSP).
-
- \param [in] topOfProcStack USR/SYS Stack Pointer value to set
- */
-__STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
-{
- ARM
- PRESERVE8
-
- BIC R0, R0, #7 ;ensure stack is 8-byte aligned
- MRS R1, CPSR
- CPS #MODE_SYS ;no effect in USR mode
- MOV SP, R0
- MSR CPSR_c, R1 ;no effect in USR mode
- ISB
- BX LR
-
-}
-
-/** \brief Set User Mode
-
- This function changes the processor state to User Mode
-
- \param [in] topOfProcStack USR/SYS Stack Pointer value to set
- */
-__STATIC_ASM void __set_CPS_USR(void)
-{
- ARM
-
- CPS #MODE_USR
- BX LR
-}
-
-
-/** \brief Enable FIQ
-
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq __enable_fiq
-
-
-/** \brief Disable FIQ
-
- This function disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq __disable_fiq
-
-
-/** \brief Get FPSCR
-
- This function returns the current value of the Floating Point Status/Control register.
-
- \return Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- register uint32_t __regfpscr __ASM("fpscr");
- return(__regfpscr);
-#else
- return(0);
-#endif
-}
-
-
-/** \brief Set FPSCR
-
- This function assigns the given value to the Floating Point Status/Control register.
-
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- register uint32_t __regfpscr __ASM("fpscr");
- __regfpscr = (fpscr);
-#endif
-}
-
-/** \brief Get FPEXC
-
- This function returns the current value of the Floating Point Exception Control register.
-
- \return Floating Point Exception Control register value
- */
-__STATIC_INLINE uint32_t __get_FPEXC(void)
-{
-#if (__FPU_PRESENT == 1)
- register uint32_t __regfpexc __ASM("fpexc");
- return(__regfpexc);
-#else
- return(0);
-#endif
-}
-
-
-/** \brief Set FPEXC
-
- This function assigns the given value to the Floating Point Exception Control register.
-
- \param [in] fpscr Floating Point Exception Control value to set
- */
-__STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
-{
-#if (__FPU_PRESENT == 1)
- register uint32_t __regfpexc __ASM("fpexc");
- __regfpexc = (fpexc);
-#endif
-}
-
-/** \brief Get CPACR
-
- This function returns the current value of the Coprocessor Access Control register.
-
- \return Coprocessor Access Control register value
- */
-__STATIC_INLINE uint32_t __get_CPACR(void)
-{
- register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
- return __regCPACR;
-}
-
-/** \brief Set CPACR
-
- This function assigns the given value to the Coprocessor Access Control register.
-
- \param [in] cpacr Coporcessor Acccess Control value to set
- */
-__STATIC_INLINE void __set_CPACR(uint32_t cpacr)
-{
- register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
- __regCPACR = cpacr;
- __ISB();
-}
-
-/** \brief Get CBAR
-
- This function returns the value of the Configuration Base Address register.
-
- \return Configuration Base Address register value
- */
-__STATIC_INLINE uint32_t __get_CBAR() {
- register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
- return(__regCBAR);
-}
-
-/** \brief Get TTBR0
-
- This function returns the value of the Configuration Base Address register.
-
- \return Translation Table Base Register 0 value
- */
-__STATIC_INLINE uint32_t __get_TTBR0() {
- register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
- return(__regTTBR0);
-}
-
-/** \brief Set TTBR0
-
- This function assigns the given value to the Coprocessor Access Control register.
-
- \param [in] ttbr0 Translation Table Base Register 0 value to set
- */
-__STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
- register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
- __regTTBR0 = ttbr0;
- __ISB();
-}
-
-/** \brief Get DACR
-
- This function returns the value of the Domain Access Control Register.
-
- \return Domain Access Control Register value
- */
-__STATIC_INLINE uint32_t __get_DACR() {
- register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
- return(__regDACR);
-}
-
-/** \brief Set DACR
-
- This function assigns the given value to the Coprocessor Access Control register.
-
- \param [in] dacr Domain Access Control Register value to set
- */
-__STATIC_INLINE void __set_DACR(uint32_t dacr) {
- register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
- __regDACR = dacr;
- __ISB();
-}
-
-/******************************** Cache and BTAC enable ****************************************************/
-
-/** \brief Set SCTLR
-
- This function assigns the given value to the System Control Register.
-
- \param [in] sctlr System Control Register, value to set
- */
-__STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
-{
- register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
- __regSCTLR = sctlr;
-}
-
-/** \brief Get SCTLR
-
- This function returns the value of the System Control Register.
-
- \return System Control Register value
- */
-__STATIC_INLINE uint32_t __get_SCTLR() {
- register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
- return(__regSCTLR);
-}
-
-/** \brief Enable Caches
-
- Enable Caches
- */
-__STATIC_INLINE void __enable_caches(void) {
- // Set I bit 12 to enable I Cache
- // Set C bit 2 to enable D Cache
- __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
-}
-
-/** \brief Disable Caches
-
- Disable Caches
- */
-__STATIC_INLINE void __disable_caches(void) {
- // Clear I bit 12 to disable I Cache
- // Clear C bit 2 to disable D Cache
- __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
- __ISB();
-}
-
-/** \brief Enable BTAC
-
- Enable BTAC
- */
-__STATIC_INLINE void __enable_btac(void) {
- // Set Z bit 11 to enable branch prediction
- __set_SCTLR( __get_SCTLR() | (1 << 11));
- __ISB();
-}
-
-/** \brief Disable BTAC
-
- Disable BTAC
- */
-__STATIC_INLINE void __disable_btac(void) {
- // Clear Z bit 11 to disable branch prediction
- __set_SCTLR( __get_SCTLR() & ~(1 << 11));
-}
-
-
-/** \brief Enable MMU
-
- Enable MMU
- */
-__STATIC_INLINE void __enable_mmu(void) {
- // Set M bit 0 to enable the MMU
- // Set AFE bit to enable simplified access permissions model
- // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
- __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
- __ISB();
-}
-
-/** \brief Enable MMU
-
- Enable MMU
- */
-__STATIC_INLINE void __disable_mmu(void) {
- // Clear M bit 0 to disable the MMU
- __set_SCTLR( __get_SCTLR() & ~1);
- __ISB();
-}
-
-/******************************** TLB maintenance operations ************************************************/
-/** \brief Invalidate the whole tlb
-
- TLBIALL. Invalidate the whole tlb
- */
-
-__STATIC_INLINE void __ca9u_inv_tlb_all(void) {
- register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
- __TLBIALL = 0;
- __DSB();
- __ISB();
-}
-
-/******************************** BTB maintenance operations ************************************************/
-/** \brief Invalidate entire branch predictor array
-
- BPIALL. Branch Predictor Invalidate All.
- */
-
-__STATIC_INLINE void __v7_inv_btac(void) {
- register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
- __BPIALL = 0;
- __DSB(); //ensure completion of the invalidation
- __ISB(); //ensure instruction fetch path sees new state
-}
-
-
-/******************************** L1 cache operations ******************************************************/
-
-/** \brief Invalidate the whole I$
-
- ICIALLU. Instruction Cache Invalidate All to PoU
- */
-__STATIC_INLINE void __v7_inv_icache_all(void) {
- register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
- __ICIALLU = 0;
- __DSB(); //ensure completion of the invalidation
- __ISB(); //ensure instruction fetch path sees new I cache state
-}
-
-/** \brief Clean D$ by MVA
-
- DCCMVAC. Data cache clean by MVA to PoC
- */
-__STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
- register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
- __DCCMVAC = (uint32_t)va;
- __DMB(); //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief Invalidate D$ by MVA
-
- DCIMVAC. Data cache invalidate by MVA to PoC
- */
-__STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
- register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
- __DCIMVAC = (uint32_t)va;
- __DMB(); //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief Clean and Invalidate D$ by MVA
-
- DCCIMVAC. Data cache clean and invalidate by MVA to PoC
- */
-__STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
- register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
- __DCCIMVAC = (uint32_t)va;
- __DMB(); //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief
- * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
- */
-#pragma push
-#pragma arm
-__STATIC_ASM void __v7_all_cache(uint32_t op) {
- ARM
-
- PUSH {R4-R11}
-
- MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
- ANDS R3, R6, #0x07000000 // Extract coherency level
- MOV R3, R3, LSR #23 // Total cache levels << 1
- BEQ Finished // If 0, no need to clean
-
- MOV R10, #0 // R10 holds current cache level << 1
-Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
- MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
- AND R1, R1, #7 // Isolate those lower 3 bits
- CMP R1, #2
- BLT Skip // No cache or only instruction cache at this level
-
- MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
- ISB // ISB to sync the change to the CacheSizeID reg
- MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
- AND R2, R1, #7 // Extract the line length field
- ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
- LDR R4, =0x3FF
- ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
- CLZ R5, R4 // R5 is the bit position of the way size increment
- LDR R7, =0x7FFF
- ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
-
-Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
-
-Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
- ORR R11, R11, R7, LSL R2 // Factor in the Set number
- CMP R0, #0
- BNE Dccsw
- MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
- B cont
-Dccsw CMP R0, #1
- BNE Dccisw
- MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
- B cont
-Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW, Clean and Invalidate by Set/Way
-cont SUBS R9, R9, #1 // Decrement the Way number
- BGE Loop3
- SUBS R7, R7, #1 // Decrement the Set number
- BGE Loop2
-Skip ADD R10, R10, #2 // increment the cache number
- CMP R3, R10
- BGT Loop1
-
-Finished
- DSB
- POP {R4-R11}
- BX lr
-
-}
-#pragma pop
-
-/** \brief __v7_all_cache - helper function
-
- */
-
-/** \brief Invalidate the whole D$
-
- DCISW. Invalidate by Set/Way
- */
-
-__STATIC_INLINE void __v7_inv_dcache_all(void) {
- __v7_all_cache(0);
-}
-
-/** \brief Clean the whole D$
-
- DCCSW. Clean by Set/Way
- */
-
-__STATIC_INLINE void __v7_clean_dcache_all(void) {
- __v7_all_cache(1);
-}
-
-/** \brief Clean and invalidate the whole D$
-
- DCCISW. Clean and Invalidate by Set/Way
- */
-
-__STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
- __v7_all_cache(2);
-}
-
-#include "core_ca_mmu.h"
-
-#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
-
-#error IAR Compiler support not implemented for Cortex-A
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-
-/* GNU gcc specific functions */
-
-#define MODE_USR 0x10
-#define MODE_FIQ 0x11
-#define MODE_IRQ 0x12
-#define MODE_SVC 0x13
-#define MODE_MON 0x16
-#define MODE_ABT 0x17
-#define MODE_HYP 0x1A
-#define MODE_UND 0x1B
-#define MODE_SYS 0x1F
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
-{
- __ASM volatile ("cpsie i");
-}
-
-/** \brief Disable IRQ Interrupts
-
- This function disables IRQ interrupts by setting the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
-{
- uint32_t result;
-
- __ASM volatile ("mrs %0, cpsr" : "=r" (result));
- __ASM volatile ("cpsid i");
- return(result & 0x80);
-}
-
-
-/** \brief Get APSR Register
-
- This function returns the content of the APSR Register.
-
- \return APSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
-{
-#if 1
- uint32_t result;
-
- __ASM volatile ("mrs %0, apsr" : "=r" (result) );
- return (result);
-#else
- register uint32_t __regAPSR __ASM("apsr");
- return(__regAPSR);
-#endif
-}
-
-
-/** \brief Get CPSR Register
-
- This function returns the content of the CPSR Register.
-
- \return CPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
-{
-#if 1
- register uint32_t __regCPSR;
- __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
-#else
- register uint32_t __regCPSR __ASM("cpsr");
-#endif
- return(__regCPSR);
-}
-
-#if 0
-/** \brief Set Stack Pointer
-
- This function assigns the given value to the current stack pointer.
-
- \param [in] topOfStack Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
-{
- register uint32_t __regSP __ASM("sp");
- __regSP = topOfStack;
-}
-#endif
-
-/** \brief Get link register
-
- This function returns the value of the link register
-
- \return Value of link register
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
-{
- register uint32_t __reglr __ASM("lr");
- return(__reglr);
-}
-
-#if 0
-/** \brief Set link register
-
- This function sets the value of the link register
-
- \param [in] lr LR value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
-{
- register uint32_t __reglr __ASM("lr");
- __reglr = lr;
-}
-#endif
-
-/** \brief Set Process Stack Pointer
-
- This function assigns the given value to the USR/SYS Stack Pointer (PSP).
-
- \param [in] topOfProcStack USR/SYS Stack Pointer value to set
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/** \brief Set User Mode
-
- This function changes the processor state to User Mode
-
- \param [in] topOfProcStack USR/SYS Stack Pointer value to set
- */
-extern void __set_CPS_USR(void);
-
-/** \brief Enable FIQ
-
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq __enable_fiq
-
-
-/** \brief Disable FIQ
-
- This function disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq __disable_fiq
-
-
-/** \brief Get FPSCR
-
- This function returns the current value of the Floating Point Status/Control register.
-
- \return Floating Point Status/Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-#if 1
- uint32_t result;
-
- __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
- return (result);
-#else
- register uint32_t __regfpscr __ASM("fpscr");
- return(__regfpscr);
-#endif
-#else
- return(0);
-#endif
-}
-
-
-/** \brief Set FPSCR
-
- This function assigns the given value to the Floating Point Status/Control register.
-
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-#if 1
- __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
-#else
- register uint32_t __regfpscr __ASM("fpscr");
- __regfpscr = (fpscr);
-#endif
-#endif
-}
-
-/** \brief Get FPEXC
-
- This function returns the current value of the Floating Point Exception Control register.
-
- \return Floating Point Exception Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
-{
-#if (__FPU_PRESENT == 1)
-#if 1
- uint32_t result;
-
- __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
- return (result);
-#else
- register uint32_t __regfpexc __ASM("fpexc");
- return(__regfpexc);
-#endif
-#else
- return(0);
-#endif
-}
-
-
-/** \brief Set FPEXC
-
- This function assigns the given value to the Floating Point Exception Control register.
-
- \param [in] fpscr Floating Point Exception Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
-{
-#if (__FPU_PRESENT == 1)
-#if 1
- __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
-#else
- register uint32_t __regfpexc __ASM("fpexc");
- __regfpexc = (fpexc);
-#endif
-#endif
-}
-
-/** \brief Get CPACR
-
- This function returns the current value of the Coprocessor Access Control register.
-
- \return Coprocessor Access Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
-{
-#if 1
- register uint32_t __regCPACR;
- __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
-#else
- register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
-#endif
- return __regCPACR;
-}
-
-/** \brief Set CPACR
-
- This function assigns the given value to the Coprocessor Access Control register.
-
- \param [in] cpacr Coporcessor Acccess Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
-{
-#if 1
- __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
-#else
- register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
- __regCPACR = cpacr;
-#endif
- __ISB();
-}
-
-/** \brief Get CBAR
-
- This function returns the value of the Configuration Base Address register.
-
- \return Configuration Base Address register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
-#if 1
- register uint32_t __regCBAR;
- __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
-#else
- register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
-#endif
- return(__regCBAR);
-}
-
-/** \brief Get TTBR0
-
- This function returns the value of the Configuration Base Address register.
-
- \return Translation Table Base Register 0 value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
-#if 1
- register uint32_t __regTTBR0;
- __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
-#else
- register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
-#endif
- return(__regTTBR0);
-}
-
-/** \brief Set TTBR0
-
- This function assigns the given value to the Coprocessor Access Control register.
-
- \param [in] ttbr0 Translation Table Base Register 0 value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
-#if 1
- __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
-#else
- register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
- __regTTBR0 = ttbr0;
-#endif
- __ISB();
-}
-
-/** \brief Get DACR
-
- This function returns the value of the Domain Access Control Register.
-
- \return Domain Access Control Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
-#if 1
- register uint32_t __regDACR;
- __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
-#else
- register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
-#endif
- return(__regDACR);
-}
-
-/** \brief Set DACR
-
- This function assigns the given value to the Coprocessor Access Control register.
-
- \param [in] dacr Domain Access Control Register value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
-#if 1
- __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
-#else
- register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
- __regDACR = dacr;
-#endif
- __ISB();
-}
-
-/******************************** Cache and BTAC enable ****************************************************/
-
-/** \brief Set SCTLR
-
- This function assigns the given value to the System Control Register.
-
- \param [in] sctlr System Control Register, value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
-{
-#if 1
- __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
-#else
- register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
- __regSCTLR = sctlr;
-#endif
-}
-
-/** \brief Get SCTLR
-
- This function returns the value of the System Control Register.
-
- \return System Control Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
-#if 1
- register uint32_t __regSCTLR;
- __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
-#else
- register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
-#endif
- return(__regSCTLR);
-}
-
-/** \brief Enable Caches
-
- Enable Caches
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
- // Set I bit 12 to enable I Cache
- // Set C bit 2 to enable D Cache
- __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
-}
-
-/** \brief Disable Caches
-
- Disable Caches
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
- // Clear I bit 12 to disable I Cache
- // Clear C bit 2 to disable D Cache
- __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
- __ISB();
-}
-
-/** \brief Enable BTAC
-
- Enable BTAC
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
- // Set Z bit 11 to enable branch prediction
- __set_SCTLR( __get_SCTLR() | (1 << 11));
- __ISB();
-}
-
-/** \brief Disable BTAC
-
- Disable BTAC
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
- // Clear Z bit 11 to disable branch prediction
- __set_SCTLR( __get_SCTLR() & ~(1 << 11));
-}
-
-
-/** \brief Enable MMU
-
- Enable MMU
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
- // Set M bit 0 to enable the MMU
- // Set AFE bit to enable simplified access permissions model
- // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
- __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
- __ISB();
-}
-
-/** \brief Enable MMU
-
- Enable MMU
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
- // Clear M bit 0 to disable the MMU
- __set_SCTLR( __get_SCTLR() & ~1);
- __ISB();
-}
-
-/******************************** TLB maintenance operations ************************************************/
-/** \brief Invalidate the whole tlb
-
- TLBIALL. Invalidate the whole tlb
- */
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
-#if 1
- __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
-#else
- register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
- __TLBIALL = 0;
-#endif
- __DSB();
- __ISB();
-}
-
-/******************************** BTB maintenance operations ************************************************/
-/** \brief Invalidate entire branch predictor array
-
- BPIALL. Branch Predictor Invalidate All.
- */
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
-#if 1
- __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
-#else
- register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
- __BPIALL = 0;
-#endif
- __DSB(); //ensure completion of the invalidation
- __ISB(); //ensure instruction fetch path sees new state
-}
-
-
-/******************************** L1 cache operations ******************************************************/
-
-/** \brief Invalidate the whole I$
-
- ICIALLU. Instruction Cache Invalidate All to PoU
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
-#if 1
- __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
-#else
- register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
- __ICIALLU = 0;
-#endif
- __DSB(); //ensure completion of the invalidation
- __ISB(); //ensure instruction fetch path sees new I cache state
-}
-
-/** \brief Clean D$ by MVA
-
- DCCMVAC. Data cache clean by MVA to PoC
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
-#if 1
- __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
-#else
- register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
- __DCCMVAC = (uint32_t)va;
-#endif
- __DMB(); //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief Invalidate D$ by MVA
-
- DCIMVAC. Data cache invalidate by MVA to PoC
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
-#if 1
- __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
-#else
- register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
- __DCIMVAC = (uint32_t)va;
-#endif
- __DMB(); //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief Clean and Invalidate D$ by MVA
-
- DCCIMVAC. Data cache clean and invalidate by MVA to PoC
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
-#if 1
- __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
-#else
- register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
- __DCCIMVAC = (uint32_t)va;
-#endif
- __DMB(); //ensure the ordering of data cache maintenance operations and their effects
-}
-
-/** \brief
- * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
- */
-
-/** \brief __v7_all_cache - helper function
-
- */
-
-extern void __v7_all_cache(uint32_t op);
-
-
-/** \brief Invalidate the whole D$
-
- DCISW. Invalidate by Set/Way
- */
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
- __v7_all_cache(0);
-}
-
-/** \brief Clean the whole D$
-
- DCCSW. Clean by Set/Way
- */
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
- __v7_all_cache(1);
-}
-
-/** \brief Clean and invalidate the whole D$
-
- DCCISW. Clean and Invalidate by Set/Way
- */
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
- __v7_all_cache(2);
-}
-
-#include "core_ca_mmu.h"
-
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
-
-#error TASKING Compiler support not implemented for Cortex-A
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-#endif /* __CORE_CAFUNC_H__ */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/6a7432f4/libs/cmsis-core/src/ext/core_caInstr.h
----------------------------------------------------------------------
diff --git a/libs/cmsis-core/src/ext/core_caInstr.h b/libs/cmsis-core/src/ext/core_caInstr.h
deleted file mode 100644
index b1d3435..0000000
--- a/libs/cmsis-core/src/ext/core_caInstr.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/**************************************************************************//**
- * @file core_caInstr.h
- * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
- * @version
- * @date 04. December 2012
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2012 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-#ifndef __CORE_CAINSTR_H__
-#define __CORE_CAINSTR_H__
-
-#define __CORTEX_M 0x3
-#include "core_cmInstr.h"
-#undef __CORTEX_M
-
-#endif
-