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Posted to commits@mynewt.apache.org by an...@apache.org on 2022/02/04 13:25:56 UTC
[mynewt-nimble] 02/02: nimble/ll: Add support for non-32768 os_cputime freq
This is an automated email from the ASF dual-hosted git repository.
andk pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-nimble.git
commit 7cac65c0ecd55179fcd70a5305c7ac1f3e79968f
Author: Andrzej Kaczmarek <an...@codecoup.pl>
AuthorDate: Fri Jan 28 14:41:18 2022 +0100
nimble/ll: Add support for non-32768 os_cputime freq
This removes restrictions to force 32768Hz clock for os_cputime and
uses explicit convertions from usecs to ticks instead of precalculated
values.
---
nimble/controller/include/controller/ble_ll.h | 4 ----
.../controller/include/controller/ble_ll_sched.h | 1 -
nimble/controller/include/controller/ble_ll_tmr.h | 12 ++++++++++-
nimble/controller/src/ble_ll_conn.c | 8 +++++---
nimble/controller/src/ble_ll_sched.c | 23 +++++++++++-----------
nimble/controller/syscfg.yml | 1 -
6 files changed, 28 insertions(+), 21 deletions(-)
diff --git a/nimble/controller/include/controller/ble_ll.h b/nimble/controller/include/controller/ble_ll.h
index d148fbe..c51d410 100644
--- a/nimble/controller/include/controller/ble_ll.h
+++ b/nimble/controller/include/controller/ble_ll.h
@@ -37,10 +37,6 @@
extern "C" {
#endif
-#if MYNEWT_VAL(OS_CPUTIME_FREQ) != 32768
-#error 32.768kHz clock required
-#endif
-
#if defined(MYNEWT) && MYNEWT_VAL(BLE_LL_HCI_VS_EVENT_ON_ASSERT)
#ifdef NDEBUG
#define BLE_LL_ASSERT(cond) (void(0))
diff --git a/nimble/controller/include/controller/ble_ll_sched.h b/nimble/controller/include/controller/ble_ll_sched.h
index 45e148c..4ce687e 100644
--- a/nimble/controller/include/controller/ble_ll_sched.h
+++ b/nimble/controller/include/controller/ble_ll_sched.h
@@ -26,7 +26,6 @@ extern "C" {
/* Time per BLE scheduler slot */
#define BLE_LL_SCHED_USECS_PER_SLOT (1250)
-#define BLE_LL_SCHED_TICKS_PER_SLOT (41) /* 1 tick = 30.517 usecs */
/*
* Worst case time needed for scheduled advertising item. This is the longest
diff --git a/nimble/controller/include/controller/ble_ll_tmr.h b/nimble/controller/include/controller/ble_ll_tmr.h
index 9dd6ab4..2d79427 100644
--- a/nimble/controller/include/controller/ble_ll_tmr.h
+++ b/nimble/controller/include/controller/ble_ll_tmr.h
@@ -27,7 +27,8 @@
extern "C" {
#endif
-#define USECS_PER_TICK (31)
+#define USECS_PER_TICK ((1000000 + MYNEWT_VAL(OS_CPUTIME_FREQ) - 1) / \
+ MYNEWT_VAL(OS_CPUTIME_FREQ))
#define LL_TMR_LT(_t1, _t2) ((int32_t)((_t1) - (_t2)) < 0)
#define LL_TMR_GT(_t1, _t2) ((int32_t)((_t1) - (_t2)) > 0)
@@ -49,15 +50,24 @@ ble_ll_tmr_get(void)
static inline uint32_t
ble_ll_tmr_t2u(uint32_t ticks)
{
+#if MYNEWT_VAL(OS_CPUTIME_FREQ) == 31250
+ return ticks * 32;
+#endif
+
return os_cputime_ticks_to_usecs(ticks);
}
static inline uint32_t
ble_ll_tmr_u2t(uint32_t usecs)
{
+#if MYNEWT_VAL(OS_CPUTIME_FREQ) == 31250
+ return usecs / 32;
+#endif
+#if MYNEWT_VAL(OS_CPUTIME_FREQ) == 32768
if (usecs <= 31249) {
return (usecs * 137439) / 4194304;
}
+#endif
return os_cputime_usecs_to_ticks(usecs);
}
diff --git a/nimble/controller/src/ble_ll_conn.c b/nimble/controller/src/ble_ll_conn.c
index d3579ed..7e3baab 100644
--- a/nimble/controller/src/ble_ll_conn.c
+++ b/nimble/controller/src/ble_ll_conn.c
@@ -2222,7 +2222,8 @@ ble_ll_conn_next_event(struct ble_ll_conn_sm *connsm)
#if MYNEWT_VAL(BLE_LL_STRICT_CONN_SCHEDULING)
itvl = g_ble_ll_sched_data.sch_ticks_per_period;
#else
- itvl = MYNEWT_VAL(BLE_LL_CONN_INIT_SLOTS) * BLE_LL_SCHED_TICKS_PER_SLOT;
+ itvl = ble_ll_tmr_u2t(MYNEWT_VAL(BLE_LL_CONN_INIT_SLOTS) *
+ BLE_LL_SCHED_USECS_PER_SLOT);
#endif
#if MYNEWT_VAL(BLE_LL_ROLE_PERIPHERAL)
if (connsm->conn_role == BLE_LL_CONN_ROLE_SLAVE) {
@@ -2339,8 +2340,9 @@ ble_ll_conn_created(struct ble_ll_conn_sm *connsm, struct ble_mbuf_hdr *rxhdr)
#else
connsm->ce_end_time = connsm->anchor_point +
- (MYNEWT_VAL(BLE_LL_CONN_INIT_SLOTS) * BLE_LL_SCHED_TICKS_PER_SLOT)
- + ble_ll_tmr_u2t(connsm->slave_cur_tx_win_usecs) + 1;
+ ble_ll_tmr_u2t(MYNEWT_VAL(BLE_LL_CONN_INIT_SLOTS) *
+ BLE_LL_SCHED_USECS_PER_SLOT +
+ connsm->slave_cur_tx_win_usecs) + 1;
#endif
connsm->slave_cur_window_widening = BLE_LL_JITTER_USECS;
diff --git a/nimble/controller/src/ble_ll_sched.c b/nimble/controller/src/ble_ll_sched.c
index 94b45e8..0ba6a89 100644
--- a/nimble/controller/src/ble_ll_sched.c
+++ b/nimble/controller/src/ble_ll_sched.c
@@ -718,7 +718,7 @@ ble_ll_sched_master_new(struct ble_ll_conn_sm *connsm,
* We received packet on advertising channel which means this is a legacy
* PDU on 1 Mbps - we do as described above.
*/
- earliest_start = adv_rxend + 57;
+ earliest_start = adv_rxend + ble_ll_tmr_u2t(1752);
} else {
/*
* The calculations are similar as above.
@@ -731,27 +731,28 @@ ble_ll_sched_master_new(struct ble_ll_conn_sm *connsm,
*
*/
if (ble_hdr->rxinfo.phy == BLE_PHY_1M) {
- // 150 + 352 + 2500 = 3002us = 98.37 ticks
- earliest_start = adv_rxend + 98;
+ /* 150 + 352 + 2500 = 3002us */
+ earliest_start = adv_rxend + ble_ll_tmr_u2t(3002);
} else if (ble_hdr->rxinfo.phy == BLE_PHY_2M) {
- // 150 + 180 + 2500 = 2830us = 92.73 ticks
- earliest_start = adv_rxend + 93;
+ /* 150 + 180 + 2500 = 2830us */
+ earliest_start = adv_rxend + ble_ll_tmr_u2t(2830);
} else if (ble_hdr->rxinfo.phy == BLE_PHY_CODED) {
- // 150 + 2896 + 3750 = 6796us = 222.69 ticks
- earliest_start = adv_rxend + 223;
+ /* 150 + 2896 + 3750 = 6796us */
+ earliest_start = adv_rxend + ble_ll_tmr_u2t(6796);
} else {
BLE_LL_ASSERT(0);
}
}
sch->start_time = earliest_start - g_ble_ll_sched_offset_ticks;
- sch->end_time = earliest_start + MYNEWT_VAL(BLE_LL_CONN_INIT_SLOTS) *
- BLE_LL_SCHED_TICKS_PER_SLOT;
+ sch->end_time = earliest_start +
+ ble_ll_tmr_u2t(MYNEWT_VAL(BLE_LL_CONN_INIT_SLOTS) *
+ BLE_LL_SCHED_USECS_PER_SLOT);
orig_start_time = sch->start_time;
- min_win_offset = MYNEWT_VAL(BLE_LL_CONN_INIT_MIN_WIN_OFFSET) *
- BLE_LL_SCHED_TICKS_PER_SLOT;
+ min_win_offset = ble_ll_tmr_u2t(MYNEWT_VAL(BLE_LL_CONN_INIT_MIN_WIN_OFFSET) *
+ BLE_LL_SCHED_USECS_PER_SLOT);
sch->start_time += min_win_offset;
sch->end_time += min_win_offset;
diff --git a/nimble/controller/syscfg.yml b/nimble/controller/syscfg.yml
index bb46311..9f17350 100644
--- a/nimble/controller/syscfg.yml
+++ b/nimble/controller/syscfg.yml
@@ -516,7 +516,6 @@ syscfg.vals.!BLE_HOST:
BLE_LL_HCI_VS_EVENT_ON_ASSERT: 1
syscfg.restrictions:
- - OS_CPUTIME_FREQ == 32768
- BLE_LL_PUBLIC_DEV_ADDR <= 0xffffffffffff
- BLE_LL_PA == 0 || BLE_LL_PA_GPIO >= 0
- BLE_LL_LNA == 0 || BLE_LL_LNA_GPIO >= 0