git commit: Fix the bug that ram cache and evcuation may not work well in disks (vols) larger than 2TB.

[we...@apache.org]

Updated Branches:
  refs/heads/master f0a98cdc7 -> 3be674317


Fix the bug that ram cache and evcuation may not work well
in disks (vols) larger than 2TB.


Project: http://git-wip-us.apache.org/repos/asf/trafficserver/repo
Commit: http://git-wip-us.apache.org/repos/asf/trafficserver/commit/3be67431
Tree: http://git-wip-us.apache.org/repos/asf/trafficserver/tree/3be67431
Diff: http://git-wip-us.apache.org/repos/asf/trafficserver/diff/3be67431

Branch: refs/heads/master
Commit: 3be67431789c00b2d47ca9e91c5bf326e62164e0
Parents: f0a98cd
Author: weijin <we...@apache.org>
Authored: Fri Jun 29 00:30:57 2012 +0800
Committer: weijin <we...@apache.org>
Committed: Fri Jun 29 00:30:57 2012 +0800

----------------------------------------------------------------------
 CHANGES                    |    3 +++
 iocore/cache/Cache.cc      |    3 ++-
 iocore/cache/CacheDir.cc   |    3 ++-
 iocore/cache/CacheWrite.cc |    5 +++--
 4 files changed, 10 insertions(+), 4 deletions(-)
----------------------------------------------------------------------


http://git-wip-us.apache.org/repos/asf/trafficserver/blob/3be67431/CHANGES
----------------------------------------------------------------------
diff --git a/CHANGES b/CHANGES
index 757b907..e303174 100644
--- a/CHANGES
+++ b/CHANGES
@@ -1,5 +1,8 @@
                                                          -*- coding: utf-8 -*-
 Changes with Apache Traffic Server 3.3.0
+  *) Fix a bug that ram cache and evcuation can not work
+    well in disks larger than 2TB. Author: weijin
+
   *) [TS-1321] improve RT on Cluster purge missing objects
    Author: Bin Chen
 

http://git-wip-us.apache.org/repos/asf/trafficserver/blob/3be67431/iocore/cache/Cache.cc
----------------------------------------------------------------------
diff --git a/iocore/cache/Cache.cc b/iocore/cache/Cache.cc
index 9cf90ce..5083b48 100644
--- a/iocore/cache/Cache.cc
+++ b/iocore/cache/Cache.cc
@@ -1971,7 +1971,8 @@ CacheVC::handleRead(int event, Event *e)
 
   // check ram cache
   ink_debug_assert(vol->mutex->thread_holding == this_ethread());
-  if (vol->ram_cache->get(read_key, &buf, 0, dir_offset(&dir)))
+  int64_t o = dir_offset(&dir);
+  if (vol->ram_cache->get(read_key, &buf, (uint32_t)(o >> 32), (uint32_t)o));
     goto LramHit;
 
   // check if it was read in the last open_read call

http://git-wip-us.apache.org/repos/asf/trafficserver/blob/3be67431/iocore/cache/CacheDir.cc
----------------------------------------------------------------------
diff --git a/iocore/cache/CacheDir.cc b/iocore/cache/CacheDir.cc
index 13a3d34..ffc6fff 100644
--- a/iocore/cache/CacheDir.cc
+++ b/iocore/cache/CacheDir.cc
@@ -778,7 +778,8 @@ dir_lookaside_fixup(CacheKey *key, Vol *d)
       int res = dir_overwrite(key, d, &b->new_dir, &b->dir, false);
       DDebug("dir_lookaside", "fixup %X %X offset %"PRId64" phase %d %d",
             key->word(0), key->word(1), dir_offset(&b->new_dir), dir_phase(&b->new_dir), res);
-      d->ram_cache->fixup(key, 0, dir_offset(&b->dir), 0, dir_offset(&b->new_dir));
+      int64_t o = dir_offset(&b->dir), n = dir_offset(&b->new_dir);
+      d->ram_cache->fixup(key, (uint32_t)(o >> 32), (uint32_t)o, (uint32_t)(n >> 32), (uint32_t)n);
       d->lookaside[i].remove(b);
       free_EvacuationBlock(b, d->mutex->thread_holding);
       return res;

http://git-wip-us.apache.org/repos/asf/trafficserver/blob/3be67431/iocore/cache/CacheWrite.cc
----------------------------------------------------------------------
diff --git a/iocore/cache/CacheWrite.cc b/iocore/cache/CacheWrite.cc
index a75b5fb..f98aaad 100644
--- a/iocore/cache/CacheWrite.cc
+++ b/iocore/cache/CacheWrite.cc
@@ -534,7 +534,8 @@ CacheVC::evacuateDocDone(int event, Event *e)
 
           }
           if (dir_overwrite(&doc->first_key, vol, &dir, &overwrite_dir)) {
-            vol->ram_cache->fixup(&doc->first_key, 0, dir_offset(&overwrite_dir), 0, dir_offset(&dir));
+            int64_t o = dir_offset(&overwrite_dir), n = dir_offset(&dir);
+            vol->ram_cache->fixup(&doc->first_key, (uint32_t)(o >> 32), (uint32_t)o, (uint32_t)(n >> 32), (uint32_t)n);
           }
         } else {
           DDebug("cache_evac", "evacuating earliest: %X %d", (int) doc->key.word(0), (int) dir_offset(&overwrite_dir));
@@ -715,7 +716,7 @@ Vol::evac_range(off_t low, off_t high, int evac_phase)
   for (int i = si; i <= ei; i++) {
     EvacuationBlock *b = evacuate[i].head;
     EvacuationBlock *first = 0;
-    int first_offset = INT_MAX;
+    int64_t first_offset = INT64_MAX;
     for (; b; b = b->link.next) {
       int64_t offset = dir_offset(&b->dir);
       int phase = dir_phase(&b->dir);