You are viewing a plain text version of this content. The canonical link for it is here.
Posted to commits@mynewt.apache.org by GitBox <gi...@apache.org> on 2021/02/04 20:29:26 UTC
[GitHub] [mynewt-core] mlaz commented on a change in pull request #2466: mcu/nxp: Update NXP SDK and add Kinetis common HAL.
mlaz commented on a change in pull request #2466:
URL: https://github.com/apache/mynewt-core/pull/2466#discussion_r570522918
##########
File path: hw/mcu/nxp/kinetis/src/hal_flash.c
##########
@@ -0,0 +1,178 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+*
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/*
+ * Internal flash for MK82F25615.
Review comment:
Addressed.
##########
File path: hw/mcu/nxp/kinetis/src/hal_hw_id.c
##########
@@ -22,26 +22,27 @@
#include <hal/hal_bsp.h>
-#include "MK64F12.h"
+#include "fsl_sim.h"
#ifndef min
#define min(a, b) ((a)<(b)?(a):(b))
#endif
-#define MK64F12_HW_ID_LEN 7
+#define MK8xF_HW_ID_LEN sizeof(sim_uid_t)
Review comment:
Addressed.
##########
File path: hw/mcu/nxp/kinetis/src/hal_watchdog.c
##########
@@ -25,7 +25,7 @@
#include "fsl_wdog.h"
#include "fsl_rcm.h"
-/* #define WATCHDOG_STUB */
+//#define WATCHDOG_STUB
Review comment:
Addressed.
##########
File path: hw/mcu/nxp/kinetis/src/hal_i2c.c
##########
@@ -0,0 +1,412 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "os/os_time.h"
+#include "mcu/kinetis_hal.h"
+#include "mcu/mcu.h"
+#include "hal/hal_i2c.h"
+
+#include <fsl_i2c.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+#define NXP_HAL_I2C_MAX 4
+
+struct nxp_hal_i2c {
+ I2C_Type* dev;
+ uint32_t scl_pin;
+ uint32_t sda_pin;
+ PORT_Type *port;
+ port_mux_t mux;
+ IRQn_Type irqn;
+ void (*irq_handler)(void);
+ i2c_master_handle_t handle;
+ struct os_sem sync;
+ status_t stat;
+ bool enabled;
+ bool ongoing;
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void i2c0_irq(void);
+static struct nxp_hal_i2c hal_i2c0 = {
+ .dev = I2C0,
+ .scl_pin = MYNEWT_VAL(I2C_0_PIN_SCL),
+ .sda_pin = MYNEWT_VAL(I2C_0_PIN_SDA),
+ .port = MYNEWT_VAL(I2C_0_PORT),
+ .mux = MYNEWT_VAL(I2C_0_MUX),
+ .irqn = I2C0_IRQn,
+ .irq_handler = i2c0_irq,
+ .stat = 0,
+ .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_1)
+static void i2c1_irq(void);
+static struct nxp_hal_i2c hal_i2c1 = {
+ .dev = I2C1,
+ .scl_pin = MYNEWT_VAL(I2C_1_PIN_SCL),
+ .sda_pin = MYNEWT_VAL(I2C_1_PIN_SDA),
+ .port = MYNEWT_VAL(I2C_1_PORT),
+ .mux = MYNEWT_VAL(I2C_1_MUX),
+ .irqn = I2C1_IRQn,
+ .irq_handler = i2c1_irq,
+ .stat = 0,
+ .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_2)
+static void i2c2_irq(void);
+static struct nxp_hal_i2c hal_i2c2 = {
+ .dev = I2C2,
+ .scl_pin = MYNEWT_VAL(I2C_2_PIN_SCL),
+ .sda_pin = MYNEWT_VAL(I2C_2_PIN_SDA),
+ .port = MYNEWT_VAL(I2C_2_PORT),
+ .mux = MYNEWT_VAL(I2C_2_MUX),
+ .irqn = I2C2_IRQn,
+ .irq_handler = i2c2_irq,
+ .stat = 0,
+ .enabled = false
+};
+#endif
+
+#if MYNEWT_VAL(I2C_3)
+static void i2c3_irq(void);
+static struct nxp_hal_i2c hal_i2c3 = {
+ .dev = I2C3,
+ .scl_pin = MYNEWT_VAL(I2C_3_PIN_SCL),
+ .sda_pin = MYNEWT_VAL(I2C_3_PIN_SDA),
+ .port = MYNEWT_VAL(I2C_3_PORT),
+ .mux = MYNEWT_VAL(I2C_3_MUX),
+ .irqn = I2C3_IRQn,
+ .irq_handler = i2c3_irq,
+ .stat = 0,
+ .enabled = false
+};
+#endif
+
+static struct nxp_hal_i2c *i2c_modules[NXP_HAL_I2C_MAX] = {
+#if MYNEWT_VAL(I2C_0)
+ &hal_i2c0,
+#else
+ NULL,
+#endif
+#if MYNEWT_VAL(I2C_1)
+ &hal_i2c1,
+#else
+ NULL,
+#endif
+#if MYNEWT_VAL(I2C_2)
+ &hal_i2c2,
+#else
+ NULL,
+#endif
+#if MYNEWT_VAL(I2C_3)
+ &hal_i2c3,
+#else
+ NULL,
+#endif
+};
+
+#if MYNEWT_VAL(I2C_0)
+static void
+i2c0_irq(void)
+{
+ I2C_MasterTransferHandleIRQ(hal_i2c0.dev, &hal_i2c0.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_1)
+static void
+i2c1_irq(void)
+{
+ I2C_MasterTransferHandleIRQ(hal_i2c1.dev, &hal_i2c1.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_2)
+static void
+i2c2_irq(void)
+{
+ I2C_MasterTransferHandleIRQ(hal_i2c2.dev, &hal_i2c2.handle);
+}
+#endif
+#if MYNEWT_VAL(I2C_3)
+static void
+i2c3_irq(void)
+{
+ I2C_MasterTransferHandleIRQ(hal_i2c3.dev, &hal_i2c3.handle);
+}
+#endif
+
+static void
+master_xfer_cb(I2C_Type *dev,
+ i2c_master_handle_t *handle,
+ status_t status,
+ void *userData)
+{
+ struct nxp_hal_i2c *i2c = userData;
+ i2c->stat = status;
+ os_sem_release(&i2c->sync);
+}
+
+static struct nxp_hal_i2c*
+hal_i2c_resolve(uint8_t i2c_num)
+{
+ if (i2c_num >= NXP_HAL_I2C_MAX) {
+ return NULL;
+ }
+
+ return i2c_modules[i2c_num];
+}
+
+static void
+i2c_init_hw(struct nxp_hal_i2c *i2c, int pin_scl, int pin_sda)
+{
+ uint32_t clock_freq;
+ i2c_master_config_t master_cfg;
+
+ const port_pin_config_t pincfg = {
+ kPORT_PullUp,
+ kPORT_FastSlewRate,
+ kPORT_PassiveFilterDisable,
+ kPORT_OpenDrainEnable,
+ kPORT_LowDriveStrength,
+ i2c->mux,
+ kPORT_UnlockRegister
+ };
+ PORT_SetPinConfig(i2c->port, i2c->scl_pin, &pincfg);
+ PORT_SetPinConfig(i2c->port, i2c->sda_pin, &pincfg);
+
+ clock_freq = CLOCK_GetFreq(kCLOCK_BusClk);
+ I2C_MasterGetDefaultConfig(&master_cfg);
+ I2C_MasterInit(i2c->dev, &master_cfg, clock_freq);
+
+ I2C_MasterTransferCreateHandle(i2c->dev, &i2c->handle, master_xfer_cb, i2c);
+ NVIC_ClearPendingIRQ(i2c->irqn);
+ NVIC_SetVector(i2c->irqn, (uint32_t) i2c->irq_handler);
+ NVIC_EnableIRQ(i2c->irqn);
+}
+
+static int
+i2c_config(struct nxp_hal_i2c *i2c, uint32_t frequency)
+{
+ uint32_t clock_freq;
+ uint32_t baudrate;
+
+ switch (frequency) {
+ case 100:
+ baudrate = 100000U;
+ break;
+ case 400:
+ baudrate = 400000U;
+ break;
+ case 1000:
+ baudrate = 1000000U;
+ break;
+ default:
Review comment:
Addressed.
##########
File path: hw/mcu/nxp/kinetis/src/hal_spi.c
##########
@@ -0,0 +1,624 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <errno.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "mcu/mcu.h"
+#include "mcu/kinetis_hal.h"
+#include "hal/hal_spi.h"
+
+#include <fsl_dspi.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+/* The maximum number of SPI interfaces we will allow */
+#define NXP_HAL_SPI_MAX 3
+
+enum spi_type_t {
+ TYPE_MASTER = HAL_SPI_TYPE_MASTER,
+ TYPE_SLAVE = HAL_SPI_TYPE_SLAVE
+};
+
+struct nxp_hal_spi {
+ SPI_Type* dev;
+ uint32_t clk_pin;
+ uint32_t pcs_pin;
+ uint32_t sout_pin;
+ uint32_t sin_pin;
+ PORT_Type *port;
+ port_mux_t mux;
+ IRQn_Type irqn;
+ void (*irq_handler)(void);
+ hal_spi_txrx_cb txrx_cb;
+ void* txrx_cb_arg;
+ bool enabled;
+ enum spi_type_t type;
+};
+
+struct nxp_spi_master {
+ struct nxp_hal_spi hal_spi;
+ dspi_master_config_t config;
+ dspi_master_handle_t handle;
+};
+
+struct nxp_spi_slave {
+ struct nxp_hal_spi hal_spi;
+ dspi_slave_config_t config;
+ dspi_slave_handle_t handle;
+};
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void spi0_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void spi1_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void spi2_irq(void);
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+struct nxp_spi_master hal_spi0 = {
+ .hal_spi = {
+ .dev = SPI0,
+ .clk_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+ .pcs_pin = 0, /* unused */
+ .sout_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+ .sin_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
+ .port = MYNEWT_VAL(SPI_0_MASTER_PORT),
+ .mux = MYNEWT_VAL(SPI_0_MASTER_MUX),
+ .irqn = SPI0_IRQn,
+ .irq_handler = spi0_irq,
+ .txrx_cb = NULL,
+ .txrx_cb_arg = NULL,
+ .enabled = false,
+ .type = HAL_SPI_TYPE_MASTER,
+ },
+ .config = {0},
+ .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+struct nxp_spi_slave hal_spi0 = {
+ .hal_spi = {
+ .dev = SPI0,
+ .clk_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+ .pcs_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
+ .sout_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+ .sin_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+ .port = MYNEWT_VAL(SPI_0_SLAVE_PORT),
+ .mux = MYNEWT_VAL(SPI_0_SLAVE_MUX),
+ .irqn = SPI0_IRQn,
+ .irq_handler = spi0_irq,
+ .txrx_cb = NULL,
+ .txrx_cb_arg = NULL,
+ .enabled = false,
+ .type = HAL_SPI_TYPE_SLAVE,
+ },
+ .config = {0},
+ .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER)
+struct nxp_spi_master hal_spi1 = {
+ .hal_spi = {
+ .dev = SPI1,
+ .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+ .pcs_pin = 0, /* unused */
+ .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+ .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+ .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+ .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+ .irqn = SPI1_IRQn,
+ .irq_handler = spi1_irq,
+ .txrx_cb = NULL,
+ .txrx_cb_arg = NULL,
+ .enabled = false,
+ .type = HAL_SPI_TYPE_MASTER,
+ },
+ .config = {0},
+ .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+struct nxp_spi_slave hal_spi1 = {
+ .hal_spi = {
+ .dev = SPI1,
+ .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+ .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+ .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+ .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+ .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+ .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+ .irqn = SPI1_IRQn,
+ .irq_handler = spi1_irq,
+ .txrx_cb = NULL,
+ .txrx_cb_arg = NULL,
+ .enabled = false,
+ .type = HAL_SPI_TYPE_SLAVE,
+ },
+ .config = {0},
+ .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER)
+struct nxp_spi_master hal_spi2 = {
+ .hal_spi = {
+ .dev = SPI2,
+ .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+ .pcs_pin = 0, /* unused */
+ .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+ .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+ .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+ .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+ .irqn = SPI2_IRQn,
+ .irq_handler = spi2_irq,
+ .txrx_cb = NULL,
+ .txrx_cb_arg = NULL,
+ .enabled = false,
+ .type = HAL_SPI_TYPE_MASTER,
+ },
+ .config = {0},
+ .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+struct nxp_spi_slave hal_spi2 = {
+ .hal_spi = {
+ .dev = SPI2,
+ .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+ .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+ .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+ .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+ .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+ .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+ .irqn = SPI2_IRQn,
+ .irq_handler = spi2_irq,
+ .txrx_cb = NULL,
+ .txrx_cb_arg = NULL,
+ .enabled = false,
+ .type = HAL_SPI_TYPE_SLAVE,
+ },
+ .config = {0},
+ .handle = {0},
+};
+#endif
+
+static struct nxp_hal_spi *spi_modules[NXP_HAL_SPI_MAX] = {
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+ (struct nxp_hal_spi *) &hal_spi0,
+#else
+ NULL,
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+ (struct nxp_hal_spi *) &hal_spi1,
+#else
+ NULL,
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+ (struct nxp_hal_spi *) &hal_spi2
+#else
+ NULL
+#endif
+};
+
+static struct nxp_hal_spi *
+hal_spi_resolve(int spi_num)
+{
+ if (spi_num >= NXP_HAL_SPI_MAX) {
+ return NULL;
+ }
+ return spi_modules[spi_num];
+}
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void
+spi0_irq(void)
+{
+#if MYNEWT_VAL(SPI_0_MASTER)
+ DSPI_MasterTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+ DSPI_SlaveTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void
+spi1_irq(void)
+{
+#if MYNEWT_VAL(SPI_1_MASTER)
+ DSPI_MasterTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+ DSPI_SlaveTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void
+spi2_irq(void)
+{
+#if MYNEWT_VAL(SPI_2_MASTER)
+ DSPI_MasterTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+ DSPI_SlaveTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#endif
+}
+#endif
+
+static void
+hal_spi_slave_xfer_cb(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData)
+{
+ struct nxp_hal_spi *spi = (struct nxp_hal_spi*) userData;
+
+ if (status == kStatus_Success) {
+ if (spi->txrx_cb) {
+ spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+ }
+ }
+}
+
+static void
+hal_spi_master_xfer_cb(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData)
+{
+ struct nxp_hal_spi *spi = (struct nxp_hal_spi*) userData;
+
+ if (status == kStatus_Success) {
+ if (spi->txrx_cb) {
+ spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+ }
+ }
+}
+
+static int
+hal_spi_init_master(struct nxp_hal_spi *spi,
+ const struct nxp_hal_spi_cfg *cfg)
+{
+ struct nxp_spi_master *master;
+
+ if (spi->type == HAL_SPI_TYPE_MASTER) {
+ master = (struct nxp_spi_master*) spi;
+ PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+ PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+ PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+ DSPI_MasterGetDefaultConfig(&master->config);
+ return 0;
+ }
+
+ return EINVAL;
+}
+
+static int
+hal_spi_init_slave(struct nxp_hal_spi *spi,
+ const struct nxp_hal_spi_cfg *cfg)
+{
+ struct nxp_spi_slave *slave;
+
+ if (spi->type == HAL_SPI_TYPE_SLAVE) {
+ slave = (struct nxp_spi_slave*) spi;
+ PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+ PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+ PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+ PORT_SetPinMux(spi->port, spi->pcs_pin, spi->mux);
+ DSPI_SlaveGetDefaultConfig(&slave->config);
+ return 0;
+ }
+
+ return EINVAL;
+}
+
+
+int
+hal_spi_init(int spi_num, void *cfg, uint8_t spi_type)
+{
+ struct nxp_hal_spi *spi;
+
+ /* cfg isn't implemented, change pin usage using mynewt vals for now. */
+ spi = hal_spi_resolve(spi_num);
+ if (!spi) {
+ return EINVAL;
+ }
+
+ if (spi_type != spi->type) {
+ return EINVAL;
+ }
+
+ if (spi_type == HAL_SPI_TYPE_MASTER) {
+ return hal_spi_init_master(spi, cfg);
+ } else {
+ return hal_spi_init_slave(spi, cfg);
+ }
+ return EINVAL;
+}
+
+int
+hal_spi_init_hw(uint8_t spi_num,
+ uint8_t spi_type,
+ const struct hal_spi_hw_settings *cfg)
+{
+ struct nxp_hal_spi_cfg hal_cfg;
+ hal_cfg.clk_pin = (uint8_t)cfg->pin_sck;
+ if (spi_type == HAL_SPI_TYPE_MASTER) {
+ hal_cfg.sout_pin = (uint8_t)cfg->pin_mosi;
+ hal_cfg.sin_pin = (uint8_t)cfg->pin_miso;
+ } else {
+ hal_cfg.sin_pin = (uint8_t)cfg->pin_mosi;
+ hal_cfg.sout_pin = (uint8_t)cfg->pin_miso;
+ }
+ hal_cfg.pcs_pin = (uint8_t)cfg->pin_ss;
+ return hal_spi_init(spi_num, &hal_cfg, spi_type);
+}
+
+int
+hal_spi_config(int spi_num, struct hal_spi_settings *settings)
+{
+ struct nxp_hal_spi *spi;
+ struct nxp_spi_master *master;
+ struct nxp_spi_slave *slave;
+ dspi_clock_polarity_t cpol;
+ dspi_clock_phase_t cpha;
+
+ spi = hal_spi_resolve(spi_num);
+ if (!spi) {
+ return EINVAL;
+ }
+
+ if (!settings) {
+ return EINVAL;
+ }
+
+ switch (settings->data_mode) {
+ case HAL_SPI_MODE0:
+ cpol = kDSPI_ClockPolarityActiveHigh;
+ cpha = kDSPI_ClockPhaseFirstEdge;
+ break;
+ case HAL_SPI_MODE1:
+ cpol = kDSPI_ClockPolarityActiveHigh;
+ cpha = kDSPI_ClockPhaseSecondEdge;
+ break;
+ case HAL_SPI_MODE2:
+ cpol = kDSPI_ClockPolarityActiveLow;
+ cpha = kDSPI_ClockPhaseFirstEdge;
+ break;
+ case HAL_SPI_MODE3:
+ cpol = kDSPI_ClockPolarityActiveLow;
+ cpha = kDSPI_ClockPhaseSecondEdge;
+ break;
+ default:
+ assert(0);
+ break;
+ }
+
+ if (spi->type == HAL_SPI_TYPE_MASTER) {
+ master = (struct nxp_spi_master*) spi;
+
+ master->config.ctarConfig.baudRate = settings->baudrate;
+ master->config.ctarConfig.pcsToSckDelayInNanoSec =
+ 1000000000U / master->config.ctarConfig.baudRate;
+ master->config.ctarConfig.lastSckToPcsDelayInNanoSec =
+ 1000000000U / master->config.ctarConfig.baudRate;
+ master->config.ctarConfig.betweenTransferDelayInNanoSec =
+ 1000000000U / master->config.ctarConfig.baudRate;
+ master->config.ctarConfig.direction =
+ (settings->data_order == HAL_SPI_MSB_FIRST) ?
+ kDSPI_MsbFirst :
+ kDSPI_LsbFirst;
+ master->config.ctarConfig.bitsPerFrame =
+ (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+ master->config.ctarConfig.cpol = cpol;
+ master->config.ctarConfig.cpha = cpha;
+ } else {
+ slave = (struct nxp_spi_slave*) spi;
+ slave->config.ctarConfig.bitsPerFrame =
+ (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+ slave->config.ctarConfig.cpol = cpol;
+ slave->config.ctarConfig.cpha = cpha;
+ }
+ return 0;
+}
+
+int
+hal_spi_enable(int spi_num)
+{
+ struct nxp_hal_spi *spi;
+ struct nxp_spi_master *master;
+ struct nxp_spi_slave *slave;
+ spi = hal_spi_resolve(spi_num);
+ if (!spi) {
+ return EINVAL;
+ }
+ if (spi->enabled) {
+ return 0;
+ }
+
+ if (spi->type == HAL_SPI_TYPE_MASTER) {
+ master = (struct nxp_spi_master*) spi;
+ DSPI_MasterInit(spi->dev,
+ &master->config,
+ CLOCK_GetFreq(kCLOCK_BusClk));
+ } else {
+ slave = (struct nxp_spi_slave*) spi;
+ DSPI_SlaveInit(spi->dev, &slave->config);
+ }
Review comment:
Addressed.
##########
File path: hw/mcu/nxp/kinetis/src/hal_qspi.c
##########
@@ -0,0 +1,410 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <assert.h>
+#include <stdint.h>
+#include "os/mynewt.h"
+#if MYNEWT_VAL(QSPI_ENABLE)
+#include <mcu/cmsis_nvic.h>
+#include <hal/hal_flash_int.h>
+
+#include <fsl_port.h>
+#include <fsl_qspi.h>
+#include <fsl_clock.h>
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) < 1
+#error QSPI_FLASH_SECTOR_SIZE must be set to the correct value in bsp syscfg.yml
+#endif
+
+#if MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) < 1
+#error QSPI_FLASH_SECTOR_COUNT must be set to the correct value in bsp syscfg.yml
+#endif
+
+/* #if MYNEWT_VAL(QSPI_PIN_CS) < 0 */
+/* #error QSPI_PIN_CS must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_SCK) < 0 */
+/* #error QSPI_PIN_SCK must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO0) < 0 */
+/* #error QSPI_PIN_DIO0 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO1) < 0 */
+/* #error QSPI_PIN_DIO1 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO2) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO2 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+
+/* #if MYNEWT_VAL(QSPI_PIN_DIO3) < 0 && (MYNEWT_VAL(QSPI_READOC) > 2 || MYNEWT_VAL(QSPI_WRITEOC) > 1) */
+/* #error QSPI_PIN_DIO3 must be set to the correct value in bsp syscfg.yml */
+/* #endif */
+uint32_t lut[FSL_FEATURE_QSPI_LUT_DEPTH] = {
+ /* Seq0 :Quad Read */
+ /* CMD: 0xEB - Quad Read, Single pad */
+ /* ADDR: 0x18 - 24bit address, Quad pads */
+ /* DUMMY: 0x06 - 6 clock cyles, Quad pads */
+ /* READ: 0x80 - Read 128 bytes, Quad pads */
+ /* JUMP_ON_CS: 0 */
+ [0] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0xEB, QSPI_ADDR, QSPI_PAD_4, 0x18),
+ [1] = QSPI_LUT_SEQ(QSPI_DUMMY, QSPI_PAD_4, 0x06, QSPI_READ, QSPI_PAD_4, 0x80),
+ [2] = QSPI_LUT_SEQ(QSPI_JMP_ON_CS, QSPI_PAD_1, 0x0, 0, 0, 0),
+
+ /* Seq1: Write Enable */
+ /* CMD: 0x06 - Write Enable, Single pad */
+ [4] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x06, 0, 0, 0),
+
+ /* Seq2: Erase All */
+ /* CMD: 0x60 - Erase All chip, Single pad */
+ [8] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x60, 0, 0, 0),
+
+ /* Seq3: Read Status */
+ /* CMD: 0x05 - Read Status, single pad */
+ /* READ: 0x01 - Read 1 byte */
+ [12] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x05, QSPI_READ, QSPI_PAD_1, 0x1),
+
+ /* Seq4: Page Program */
+ /* CMD: 0x02 - Page Program, Single pad */
+ /* ADDR: 0x18 - 24bit address, Single pad */
+ /* WRITE: 0x80 - Write 128 bytes at one pass, Single pad */
+ [16] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x02, QSPI_ADDR, QSPI_PAD_1, 0x18),
+ [17] = QSPI_LUT_SEQ(QSPI_WRITE, QSPI_PAD_1, 0x80, 0, 0, 0),
+
+ /* Seq5: Write Register */
+ /* CMD: 0x01 - Write Status Register, single pad */
+ /* WRITE: 0x01 - Write 1 byte of data, single pad */
+ [20] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x01, QSPI_WRITE, QSPI_PAD_1, 0x1),
+
+ /* Seq6: Read Config Register */
+ /* CMD: 0x15 - Read Config register, single pad */
+ /* READ: 0x01 - Read 1 byte */
+ [24] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x15, QSPI_READ, QSPI_PAD_1, 0x1),
+
+ /* Seq7: Erase Sector */
+ /* CMD: 0x20 - Sector Erase, single pad */
+ /* ADDR: 0x18 - 24 bit address, single pad */
+ [28] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x20, QSPI_ADDR, QSPI_PAD_1, 0x18),
+
+ /* Match MISRA rule */
+ [63] = 0};
+
+qspi_flash_config_t g_qspi_flash_cfg = {
+ .flashA1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+ .flashA2Size = 0,
+#if (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
+ .flashB1Size = MYNEWT_VAL(QSPI_FLASH_SECTOR_COUNT) * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE) / 2,
+ .flashB2Size = 0,
+#endif
+#if (!FSL_FEATURE_QSPI_HAS_NO_TDH)
+ .dataHoldTime = 0,
+#endif
+ .CSHoldTime = 0,
+ .CSSetupTime = 0,
+ .cloumnspace = 0,
+ .dataLearnValue = 0,
+ .endian = kQSPI_64LittleEndian,
+ .enableWordAddress = false
+};
+
+static void
+check_if_finished(void)
+{
+ uint32_t val = 0;
+ /* Check WIP bit */
+ do
+ {
+ while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+ {
+ }
+ QSPI_ClearFifo(QuadSPI0, kQSPI_RxFifo);
+ QSPI_ExecuteIPCommand(QuadSPI0, 12U);
+ while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+ {
+ }
+ val = QuadSPI0->RBDR[0];
+ /* Clear ARDB area */
+ QSPI_ClearErrorFlag(QuadSPI0, kQSPI_RxBufferDrain);
+ } while (val & 0x1);
+}
+
+static void
+cmd_write_enable()
+{
+ while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+ {
+ }
+ QSPI_ExecuteIPCommand(QuadSPI0, 4U);
+}
+
+static void
+read_page(uint32_t address, uint32_t* dst)
+{
+ int i;
+ for (i = 0; i < MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) / 4; i++)
+ {
+ dst[i] = ((uint32_t*)address)[i];
+ }
+}
+
+static int
+nxp_qspi_read(const struct hal_flash *dev,
+ uint32_t address,
+ void *dst,
+ uint32_t num_bytes)
+{
+ uint32_t npages;
+ if ((address % dev->hf_align) != 0) {
+ return OS_EINVAL;
+ }
+ if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+ return OS_EINVAL;
+ }
+
+ npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+ while (npages) {
+ read_page(address, dst);
+ npages--;
+ address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+ }
+ return 0;
+}
+
+static void
+write_page(uint32_t dest_addr, uint32_t *src_addr)
+{
+ uint32_t leftLongWords = 0;
+
+ while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+ {
+ }
+ QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+
+ QSPI_SetIPCommandAddress(QuadSPI0, dest_addr);
+ cmd_write_enable();
+ while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+ {
+ }
+
+ /* First write some data into TXFIFO to prevent from underrun */
+ QSPI_WriteBlocking(QuadSPI0, src_addr, FSL_FEATURE_QSPI_TXFIFO_DEPTH * 4);
+ src_addr += FSL_FEATURE_QSPI_TXFIFO_DEPTH;
+
+ /* Start the program */
+ QSPI_SetIPCommandSize(QuadSPI0, MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE));
+ QSPI_ExecuteIPCommand(QuadSPI0, 16U);
+
+ leftLongWords = MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) - 16 * sizeof(uint32_t);
+ QSPI_WriteBlocking(QuadSPI0, src_addr, leftLongWords);
+
+ /* Wait until flash finished program */
+ check_if_finished();
+ while (QSPI_GetStatusFlags(QuadSPI0) & (kQSPI_Busy | kQSPI_IPAccess))
+ {
+ }
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+ QSPI_ClearCache(QuadSPI0);
+#endif
+}
+
+static int
+nxp_qspi_write(const struct hal_flash *dev,
+ uint32_t address,
+ const void *src,
+ uint32_t num_bytes)
+{
+ uint32_t npages;
+ if ((address % dev->hf_align) != 0) {
+ return OS_EINVAL;
+ }
+ if ((num_bytes % MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE)) != 0) {
+ return OS_EINVAL;
+ }
+
+ npages = num_bytes / MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+ while (npages) {
+ write_page(address, (uint32_t*) src);
+ npages--;
+ address += MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+ }
+ return 0;
+}
+
+static int
+nxp_qspi_erase_sector(const struct hal_flash *dev,
+ uint32_t sector_address)
+{
+ sector_address = sector_address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+ sector_address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+ while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+ {
+ }
+ QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+ QSPI_SetIPCommandAddress(QuadSPI0, sector_address);
+ cmd_write_enable();
+ QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+ check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+ QSPI_ClearCache(QuadSPI0);
+#endif
+ return 0;
+}
+
+static int
+nxp_qspi_erase(const struct hal_flash *dev,
+ uint32_t address,
+ uint32_t size)
+{
+ uint32_t nsects;
+
+ address = address / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+ address *= MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+ nsects = size / MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+ nsects += size % MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+ while (nsects) {
+ while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+ {
+ }
+ QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+ QSPI_SetIPCommandAddress(QuadSPI0, address);
+ cmd_write_enable();
+ QSPI_ExecuteIPCommand(QuadSPI0, 28U);
+ check_if_finished();
+
+#if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && \
+ (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
+ QSPI_ClearCache(QuadSPI0);
+#endif
+ nsects--;
+ address += MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+ }
+ return 0;
+}
+
+static int
+nxp_qspi_sector_info(const struct hal_flash *dev,
+ int idx,
+ uint32_t *address,
+ uint32_t *sz)
+{
+ *address = idx * MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+ *sz = MYNEWT_VAL(QSPI_FLASH_SECTOR_SIZE);
+
+ return 0;
+}
+
+/* Enable Quad mode */
+static void
+enable_quad_mode(void)
+{
+ uint32_t val[4] = {0x40U, 0, 0, 0};
+
+ while (QSPI_GetStatusFlags(QuadSPI0) & kQSPI_Busy)
+ {
+ }
+ QSPI_SetIPCommandAddress(QuadSPI0, FSL_FEATURE_QSPI_AMBA_BASE);
+
+ /* Clear Tx FIFO */
+ QSPI_ClearFifo(QuadSPI0, kQSPI_TxFifo);
+
+ /* Write enable */
+ cmd_write_enable();
+
+ /* Write data into TX FIFO, needs to write at least 16 bytes of data */
+ QSPI_WriteBlocking(QuadSPI0, val, 16U);
+
+ /* Set seq id, write register */
+ QSPI_ExecuteIPCommand(QuadSPI0, 20);
+
+ /* Wait until finished */
+ check_if_finished();
+}
+
+static int
+nxp_qspi_init(const struct hal_flash *dev)
+{
+ qspi_config_t qspi_cfg = {0};
+
+ /*Get QSPI default settings and configure the qspi */
+ QSPI_GetDefaultQspiConfig(&qspi_cfg);
+
+ /*Set AHB buffer size for reading data through AHB bus */
+/* #if MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE) <= FSL_FEATURE_QSPI_AHB_BUFFER_SIZE */
+ qspi_cfg.AHBbufferSize[3] = MYNEWT_VAL(QSPI_FLASH_PAGE_SIZE);
+/* #else */
+/* qspi_cfg.AHBbufferSize[3] = FSL_FEATURE_QSPI_AHB_BUFFER_SIZE; */
+/* #endif */
Review comment:
Addressed.
##########
File path: hw/mcu/nxp/kinetis/src/hal_spi.c
##########
@@ -0,0 +1,624 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <errno.h>
+#include "syscfg/syscfg.h"
+#include "os/mynewt.h"
+#include "mcu/mcu.h"
+#include "mcu/kinetis_hal.h"
+#include "hal/hal_spi.h"
+
+#include <fsl_dspi.h>
+#include <fsl_port.h>
+#include <fsl_clock.h>
+
+/* The maximum number of SPI interfaces we will allow */
+#define NXP_HAL_SPI_MAX 3
+
+enum spi_type_t {
+ TYPE_MASTER = HAL_SPI_TYPE_MASTER,
+ TYPE_SLAVE = HAL_SPI_TYPE_SLAVE
+};
+
+struct nxp_hal_spi {
+ SPI_Type* dev;
+ uint32_t clk_pin;
+ uint32_t pcs_pin;
+ uint32_t sout_pin;
+ uint32_t sin_pin;
+ PORT_Type *port;
+ port_mux_t mux;
+ IRQn_Type irqn;
+ void (*irq_handler)(void);
+ hal_spi_txrx_cb txrx_cb;
+ void* txrx_cb_arg;
+ bool enabled;
+ enum spi_type_t type;
+};
+
+struct nxp_spi_master {
+ struct nxp_hal_spi hal_spi;
+ dspi_master_config_t config;
+ dspi_master_handle_t handle;
+};
+
+struct nxp_spi_slave {
+ struct nxp_hal_spi hal_spi;
+ dspi_slave_config_t config;
+ dspi_slave_handle_t handle;
+};
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void spi0_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void spi1_irq(void);
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void spi2_irq(void);
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+struct nxp_spi_master hal_spi0 = {
+ .hal_spi = {
+ .dev = SPI0,
+ .clk_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_SCK),
+ .pcs_pin = 0, /* unused */
+ .sout_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+ .sin_pin = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
+ .port = MYNEWT_VAL(SPI_0_MASTER_PORT),
+ .mux = MYNEWT_VAL(SPI_0_MASTER_MUX),
+ .irqn = SPI0_IRQn,
+ .irq_handler = spi0_irq,
+ .txrx_cb = NULL,
+ .txrx_cb_arg = NULL,
+ .enabled = false,
+ .type = HAL_SPI_TYPE_MASTER,
+ },
+ .config = {0},
+ .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+struct nxp_spi_slave hal_spi0 = {
+ .hal_spi = {
+ .dev = SPI0,
+ .clk_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SCK),
+ .pcs_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_SS),
+ .sout_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MISO),
+ .sin_pin = MYNEWT_VAL(SPI_0_SLAVE_PIN_MOSI),
+ .port = MYNEWT_VAL(SPI_0_SLAVE_PORT),
+ .mux = MYNEWT_VAL(SPI_0_SLAVE_MUX),
+ .irqn = SPI0_IRQn,
+ .irq_handler = spi0_irq,
+ .txrx_cb = NULL,
+ .txrx_cb_arg = NULL,
+ .enabled = false,
+ .type = HAL_SPI_TYPE_SLAVE,
+ },
+ .config = {0},
+ .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER)
+struct nxp_spi_master hal_spi1 = {
+ .hal_spi = {
+ .dev = SPI1,
+ .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+ .pcs_pin = 0, /* unused */
+ .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+ .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+ .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+ .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+ .irqn = SPI1_IRQn,
+ .irq_handler = spi1_irq,
+ .txrx_cb = NULL,
+ .txrx_cb_arg = NULL,
+ .enabled = false,
+ .type = HAL_SPI_TYPE_MASTER,
+ },
+ .config = {0},
+ .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+struct nxp_spi_slave hal_spi1 = {
+ .hal_spi = {
+ .dev = SPI1,
+ .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+ .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+ .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+ .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+ .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+ .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+ .irqn = SPI1_IRQn,
+ .irq_handler = spi1_irq,
+ .txrx_cb = NULL,
+ .txrx_cb_arg = NULL,
+ .enabled = false,
+ .type = HAL_SPI_TYPE_SLAVE,
+ },
+ .config = {0},
+ .handle = {0},
+};
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER)
+struct nxp_spi_master hal_spi2 = {
+ .hal_spi = {
+ .dev = SPI2,
+ .clk_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_SCK),
+ .pcs_pin = 0, /* unused */
+ .sout_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+ .sin_pin = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+ .port = MYNEWT_VAL(SPI_1_MASTER_PORT),
+ .mux = MYNEWT_VAL(SPI_1_MASTER_MUX),
+ .irqn = SPI2_IRQn,
+ .irq_handler = spi2_irq,
+ .txrx_cb = NULL,
+ .txrx_cb_arg = NULL,
+ .enabled = false,
+ .type = HAL_SPI_TYPE_MASTER,
+ },
+ .config = {0},
+ .handle = {0},
+};
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+struct nxp_spi_slave hal_spi2 = {
+ .hal_spi = {
+ .dev = SPI2,
+ .clk_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SCK),
+ .pcs_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_SS),
+ .sout_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MISO),
+ .sin_pin = MYNEWT_VAL(SPI_1_SLAVE_PIN_MOSI),
+ .port = MYNEWT_VAL(SPI_1_SLAVE_PORT),
+ .mux = MYNEWT_VAL(SPI_1_SLAVE_MUX),
+ .irqn = SPI2_IRQn,
+ .irq_handler = spi2_irq,
+ .txrx_cb = NULL,
+ .txrx_cb_arg = NULL,
+ .enabled = false,
+ .type = HAL_SPI_TYPE_SLAVE,
+ },
+ .config = {0},
+ .handle = {0},
+};
+#endif
+
+static struct nxp_hal_spi *spi_modules[NXP_HAL_SPI_MAX] = {
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+ (struct nxp_hal_spi *) &hal_spi0,
+#else
+ NULL,
+#endif
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+ (struct nxp_hal_spi *) &hal_spi1,
+#else
+ NULL,
+#endif
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+ (struct nxp_hal_spi *) &hal_spi2
+#else
+ NULL
+#endif
+};
+
+static struct nxp_hal_spi *
+hal_spi_resolve(int spi_num)
+{
+ if (spi_num >= NXP_HAL_SPI_MAX) {
+ return NULL;
+ }
+ return spi_modules[spi_num];
+}
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+static void
+spi0_irq(void)
+{
+#if MYNEWT_VAL(SPI_0_MASTER)
+ DSPI_MasterTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#elif MYNEWT_VAL(SPI_0_SLAVE)
+ DSPI_SlaveTransferHandleIRQ(hal_spi0.hal_spi.dev, &hal_spi0.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_1_MASTER) || MYNEWT_VAL(SPI_1_SLAVE)
+static void
+spi1_irq(void)
+{
+#if MYNEWT_VAL(SPI_1_MASTER)
+ DSPI_MasterTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#elif MYNEWT_VAL(SPI_1_SLAVE)
+ DSPI_SlaveTransferHandleIRQ(hal_spi1.hal_spi.dev, &hal_spi1.handle);
+#endif
+}
+#endif
+
+#if MYNEWT_VAL(SPI_2_MASTER) || MYNEWT_VAL(SPI_2_SLAVE)
+static void
+spi2_irq(void)
+{
+#if MYNEWT_VAL(SPI_2_MASTER)
+ DSPI_MasterTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#elif MYNEWT_VAL(SPI_2_SLAVE)
+ DSPI_SlaveTransferHandleIRQ(hal_spi2.hal_spi.dev, &hal_spi2.handle);
+#endif
+}
+#endif
+
+static void
+hal_spi_slave_xfer_cb(SPI_Type *base, dspi_slave_handle_t *handle, status_t status, void *userData)
+{
+ struct nxp_hal_spi *spi = (struct nxp_hal_spi*) userData;
+
+ if (status == kStatus_Success) {
+ if (spi->txrx_cb) {
+ spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+ }
+ }
+}
+
+static void
+hal_spi_master_xfer_cb(SPI_Type *base, dspi_master_handle_t *handle, status_t status, void *userData)
+{
+ struct nxp_hal_spi *spi = (struct nxp_hal_spi*) userData;
+
+ if (status == kStatus_Success) {
+ if (spi->txrx_cb) {
+ spi->txrx_cb(spi->txrx_cb_arg, handle->totalByteCount);
+ }
+ }
+}
+
+static int
+hal_spi_init_master(struct nxp_hal_spi *spi,
+ const struct nxp_hal_spi_cfg *cfg)
+{
+ struct nxp_spi_master *master;
+
+ if (spi->type == HAL_SPI_TYPE_MASTER) {
+ master = (struct nxp_spi_master*) spi;
+ PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+ PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+ PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+ DSPI_MasterGetDefaultConfig(&master->config);
+ return 0;
+ }
+
+ return EINVAL;
+}
+
+static int
+hal_spi_init_slave(struct nxp_hal_spi *spi,
+ const struct nxp_hal_spi_cfg *cfg)
+{
+ struct nxp_spi_slave *slave;
+
+ if (spi->type == HAL_SPI_TYPE_SLAVE) {
+ slave = (struct nxp_spi_slave*) spi;
+ PORT_SetPinMux(spi->port, spi->clk_pin, spi->mux);
+ PORT_SetPinMux(spi->port, spi->sin_pin, spi->mux);
+ PORT_SetPinMux(spi->port, spi->sout_pin, spi->mux);
+ PORT_SetPinMux(spi->port, spi->pcs_pin, spi->mux);
+ DSPI_SlaveGetDefaultConfig(&slave->config);
+ return 0;
+ }
+
+ return EINVAL;
+}
+
+
+int
+hal_spi_init(int spi_num, void *cfg, uint8_t spi_type)
+{
+ struct nxp_hal_spi *spi;
+
+ /* cfg isn't implemented, change pin usage using mynewt vals for now. */
+ spi = hal_spi_resolve(spi_num);
+ if (!spi) {
+ return EINVAL;
+ }
+
+ if (spi_type != spi->type) {
+ return EINVAL;
+ }
+
+ if (spi_type == HAL_SPI_TYPE_MASTER) {
+ return hal_spi_init_master(spi, cfg);
+ } else {
+ return hal_spi_init_slave(spi, cfg);
+ }
+ return EINVAL;
+}
+
+int
+hal_spi_init_hw(uint8_t spi_num,
+ uint8_t spi_type,
+ const struct hal_spi_hw_settings *cfg)
+{
+ struct nxp_hal_spi_cfg hal_cfg;
+ hal_cfg.clk_pin = (uint8_t)cfg->pin_sck;
+ if (spi_type == HAL_SPI_TYPE_MASTER) {
+ hal_cfg.sout_pin = (uint8_t)cfg->pin_mosi;
+ hal_cfg.sin_pin = (uint8_t)cfg->pin_miso;
+ } else {
+ hal_cfg.sin_pin = (uint8_t)cfg->pin_mosi;
+ hal_cfg.sout_pin = (uint8_t)cfg->pin_miso;
+ }
+ hal_cfg.pcs_pin = (uint8_t)cfg->pin_ss;
+ return hal_spi_init(spi_num, &hal_cfg, spi_type);
+}
+
+int
+hal_spi_config(int spi_num, struct hal_spi_settings *settings)
+{
+ struct nxp_hal_spi *spi;
+ struct nxp_spi_master *master;
+ struct nxp_spi_slave *slave;
+ dspi_clock_polarity_t cpol;
+ dspi_clock_phase_t cpha;
+
+ spi = hal_spi_resolve(spi_num);
+ if (!spi) {
+ return EINVAL;
+ }
+
+ if (!settings) {
+ return EINVAL;
+ }
+
+ switch (settings->data_mode) {
+ case HAL_SPI_MODE0:
+ cpol = kDSPI_ClockPolarityActiveHigh;
+ cpha = kDSPI_ClockPhaseFirstEdge;
+ break;
+ case HAL_SPI_MODE1:
+ cpol = kDSPI_ClockPolarityActiveHigh;
+ cpha = kDSPI_ClockPhaseSecondEdge;
+ break;
+ case HAL_SPI_MODE2:
+ cpol = kDSPI_ClockPolarityActiveLow;
+ cpha = kDSPI_ClockPhaseFirstEdge;
+ break;
+ case HAL_SPI_MODE3:
+ cpol = kDSPI_ClockPolarityActiveLow;
+ cpha = kDSPI_ClockPhaseSecondEdge;
+ break;
+ default:
+ assert(0);
+ break;
+ }
+
+ if (spi->type == HAL_SPI_TYPE_MASTER) {
+ master = (struct nxp_spi_master*) spi;
+
+ master->config.ctarConfig.baudRate = settings->baudrate;
+ master->config.ctarConfig.pcsToSckDelayInNanoSec =
+ 1000000000U / master->config.ctarConfig.baudRate;
+ master->config.ctarConfig.lastSckToPcsDelayInNanoSec =
+ 1000000000U / master->config.ctarConfig.baudRate;
+ master->config.ctarConfig.betweenTransferDelayInNanoSec =
+ 1000000000U / master->config.ctarConfig.baudRate;
+ master->config.ctarConfig.direction =
+ (settings->data_order == HAL_SPI_MSB_FIRST) ?
+ kDSPI_MsbFirst :
+ kDSPI_LsbFirst;
+ master->config.ctarConfig.bitsPerFrame =
+ (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+ master->config.ctarConfig.cpol = cpol;
+ master->config.ctarConfig.cpha = cpha;
+ } else {
+ slave = (struct nxp_spi_slave*) spi;
+ slave->config.ctarConfig.bitsPerFrame =
+ (settings->word_size == HAL_SPI_WORD_SIZE_8BIT) ? 8 : 9;
+ slave->config.ctarConfig.cpol = cpol;
+ slave->config.ctarConfig.cpha = cpha;
+ }
+ return 0;
+}
+
+int
+hal_spi_enable(int spi_num)
+{
+ struct nxp_hal_spi *spi;
+ struct nxp_spi_master *master;
+ struct nxp_spi_slave *slave;
+ spi = hal_spi_resolve(spi_num);
+ if (!spi) {
+ return EINVAL;
+ }
+ if (spi->enabled) {
+ return 0;
+ }
+
+ if (spi->type == HAL_SPI_TYPE_MASTER) {
+ master = (struct nxp_spi_master*) spi;
+ DSPI_MasterInit(spi->dev,
+ &master->config,
+ CLOCK_GetFreq(kCLOCK_BusClk));
+ } else {
+ slave = (struct nxp_spi_slave*) spi;
+ DSPI_SlaveInit(spi->dev, &slave->config);
+ }
+
+ spi->enabled = true;
+ NVIC_ClearPendingIRQ(spi->irqn);
+ NVIC_SetVector(spi->irqn, (uint32_t) spi->irq_handler);
+ NVIC_EnableIRQ(spi->irqn);
+ return 0;
+}
+
+int
+hal_spi_disable(int spi_num)
+{
+ struct nxp_hal_spi *spi;
+ spi = hal_spi_resolve(spi_num);
+ if (!spi) {
+ return EINVAL;
+ }
+ if (!spi->enabled) {
+ return 0;
+ }
+
+ DSPI_Deinit(spi->dev);
+
+ spi->enabled = false;
+ NVIC_ClearPendingIRQ(spi->irqn);
+ NVIC_DisableIRQ(spi->irqn);
+ return 0;
+}
+
+uint16_t
+hal_spi_tx_val(int spi_num, uint16_t val)
+{
+ struct nxp_hal_spi *spi;
+ dspi_transfer_t xfer;
+ uint16_t retval = 0;
+ spi = hal_spi_resolve(spi_num);
+ if (!spi) {
+ return EINVAL;
+ }
+
+ if (spi->type == HAL_SPI_TYPE_MASTER) {
+ xfer.txData = (uint8_t*) &val;
+ xfer.rxData = (uint8_t*) &retval;
+ xfer.dataSize = 1;
+ xfer.configFlags = kDSPI_MasterCtar0;
+ DSPI_MasterTransferBlocking(spi->dev, &xfer);
+ return retval;
+ }
+ return 0xFFFF; /* Invalid API. */
+}
+
+int
+hal_spi_txrx(int spi_num, void *txbuf, void *rxbuf, int len)
+{
+ struct nxp_hal_spi *spi;
+ dspi_transfer_t xfer;
+ status_t rc;
+ spi = hal_spi_resolve(spi_num);
+ if (!spi) {
+ return EINVAL;
+ }
+
+ if (spi->type == HAL_SPI_TYPE_MASTER) {
+ xfer.txData = (uint8_t*) txbuf;
+ xfer.rxData = (uint8_t*) rxbuf;
+ xfer.dataSize = len;
+ xfer.configFlags = kDSPI_MasterCtar0;
+ rc = DSPI_MasterTransferBlocking(spi->dev, &xfer);
+ return (rc == kStatus_Success) ? 0 : rc;
+ }
+ return -1;
+}
+
+int
+hal_spi_set_txrx_cb(int spi_num, hal_spi_txrx_cb txrx_cb, void *arg)
+{
+ struct nxp_hal_spi *spi;
+ spi = hal_spi_resolve(spi_num);
+ if (!spi) {
+ return EINVAL;
+ }
+
+ spi->txrx_cb = txrx_cb;
+ spi->txrx_cb_arg = arg;
+ return 0;
+}
+
+int
+hal_spi_txrx_noblock(int spi_num, void *txbuf, void *rxbuf, int len)
+{
+ struct nxp_hal_spi *spi;
+ struct nxp_spi_master *master;
+ struct nxp_spi_slave *slave;
+ dspi_transfer_t xfer;
+ status_t rc;
+ spi = hal_spi_resolve(spi_num);
+ if (!spi) {
+ return EINVAL;
+ }
+
+ if (spi->type == HAL_SPI_TYPE_MASTER) {
+ master = (struct nxp_spi_master*) spi;
+ //master->handle
Review comment:
Done
----------------------------------------------------------------
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.
For queries about this service, please contact Infrastructure at:
users@infra.apache.org