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Posted to commits@nuttx.apache.org by bt...@apache.org on 2020/12/29 09:52:27 UTC
[incubator-nuttx] 07/09: fix some code style
This is an automated email from the ASF dual-hosted git repository.
btashton pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit d354a2f19f10a8de2ebbc668230be7ea4a1157f9
Author: yangyue <yy...@bouffalolab.com>
AuthorDate: Tue Dec 22 17:41:41 2020 +0800
fix some code style
---
arch/risc-v/include/bl602/chip.h | 3 +
arch/risc-v/include/bl602/irq.h | 3 +
arch/risc-v/src/bl602/Make.defs | 10 +-
arch/risc-v/src/bl602/bl602_allocateheap.c | 3 +
arch/risc-v/src/bl602/bl602_boot2.h | 62 +-
arch/risc-v/src/bl602/bl602_config.h | 3 +
arch/risc-v/src/bl602/bl602_entry.S | 190 +-
arch/risc-v/src/bl602/bl602_glb.c | 46 +-
arch/risc-v/src/bl602/bl602_gpio.c | 59 +-
arch/risc-v/src/bl602/bl602_hbn.c | 19 +-
arch/risc-v/src/bl602/bl602_head.S | 4 +
arch/risc-v/src/bl602/bl602_idle.c | 4 +-
arch/risc-v/src/bl602/bl602_irq.c | 16 +-
arch/risc-v/src/bl602/bl602_irq_dispatch.c | 4 +-
arch/risc-v/src/bl602/bl602_lowputc.c | 187 +-
arch/risc-v/src/bl602/bl602_lowputc.h | 35 +-
arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.c | 57 +-
arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.h | 6 +-
arch/risc-v/src/bl602/bl602_serial.c | 99 +-
arch/risc-v/src/bl602/bl602_start.c | 28 +-
arch/risc-v/src/bl602/bl602_tim.c | 333 +-
arch/risc-v/src/bl602/bl602_tim_lowerhalf.c | 147 +-
arch/risc-v/src/bl602/bl602_tim_lowerhalf.h | 3 +
arch/risc-v/src/bl602/bl602_timerisr.c | 33 +-
arch/risc-v/src/bl602/bl602_vectors.S | 3 +
arch/risc-v/src/bl602/chip.h | 3 +
.../{bl602_vectors.S => hardware/bl602_clint.h} | 31 +-
arch/risc-v/src/bl602/hardware/bl602_common.h | 197 +-
arch/risc-v/src/bl602/hardware/bl602_glb.h | 5874 +++++++-------------
arch/risc-v/src/bl602/hardware/bl602_gpio.h | 107 +-
arch/risc-v/src/bl602/hardware/bl602_hbn.h | 975 ++--
arch/risc-v/src/bl602/hardware/bl602_timer.h | 192 +-
arch/risc-v/src/bl602/hardware/bl602_uart.h | 1005 ++--
arch/risc-v/src/bl602/hardware/clic.h | 7 +-
arch/risc-v/src/common/riscv_arch.h | 1 +
boards/risc-v/bl602/bl602evb/README.txt | 2 +-
boards/risc-v/bl602/bl602evb/configs/nsh/defconfig | 1160 +++-
boards/risc-v/bl602/bl602evb/include/board.h | 3 +
boards/risc-v/bl602/bl602evb/scripts/ld.script | 48 -
boards/risc-v/bl602/bl602evb/src/bl602_appinit.c | 3 +
boards/risc-v/bl602/bl602evb/src/bl602_boot.c | 3 +
boards/risc-v/bl602/bl602evb/src/bl602_bringup.c | 3 +
boards/risc-v/bl602/bl602evb/src/bl602evb.h | 3 +
43 files changed, 4939 insertions(+), 6035 deletions(-)
diff --git a/arch/risc-v/include/bl602/chip.h b/arch/risc-v/include/bl602/chip.h
index afc95b0..a0e7b26 100644
--- a/arch/risc-v/include/bl602/chip.h
+++ b/arch/risc-v/include/bl602/chip.h
@@ -1,6 +1,9 @@
/****************************************************************************
* arch/risc-v/include/bl602/chip.h
*
+ * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
diff --git a/arch/risc-v/include/bl602/irq.h b/arch/risc-v/include/bl602/irq.h
index aef5664..dd30c8f 100644
--- a/arch/risc-v/include/bl602/irq.h
+++ b/arch/risc-v/include/bl602/irq.h
@@ -1,6 +1,9 @@
/****************************************************************************
* arch/risc-v/include/bl602/irq.h
*
+ * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
diff --git a/arch/risc-v/src/bl602/Make.defs b/arch/risc-v/src/bl602/Make.defs
index f172c49..1d1b231 100644
--- a/arch/risc-v/src/bl602/Make.defs
+++ b/arch/risc-v/src/bl602/Make.defs
@@ -1,6 +1,9 @@
############################################################################
# arch/risc-v/src/bl602/Make.defs
#
+# Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+# Author: Gregory Nutt <gn...@nuttx.org>
+#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
@@ -46,11 +49,14 @@ endif
# Specify our C code within this directory to be included
CHIP_CSRCS = bl602_allocateheap.c
CHIP_CSRCS += bl602_idle.c bl602_irq.c bl602_irq_dispatch.c
-CHIP_CSRCS += bl602_serial.c bl602_lowputc.c
+CHIP_CSRCS += bl602_serial.c bl602_lowputc.c bl602_tim.c
CHIP_CSRCS += bl602_start.c bl602_timerisr.c
ifeq ($(CONFIG_TIMER),y)
-CHIP_CSRCS += bl602_tim.c bl602_tim_lowerhalf.c bl602_oneshot_lowerhalf.c
+CHIP_CSRCS += bl602_tim_lowerhalf.c
+endif
+ifeq ($(CONFIG_ONESHOT),y)
+CHIP_CSRCS += bl602_oneshot_lowerhalf.c
endif
CHIP_CSRCS += bl602_glb.c bl602_gpio.c bl602_hbn.c
diff --git a/arch/risc-v/src/bl602/bl602_allocateheap.c b/arch/risc-v/src/bl602/bl602_allocateheap.c
index 065c30c..be7d2f9 100644
--- a/arch/risc-v/src/bl602/bl602_allocateheap.c
+++ b/arch/risc-v/src/bl602/bl602_allocateheap.c
@@ -1,6 +1,9 @@
/****************************************************************************
* arch/risc-v/src/bl602/bl602_allocateheap.c
*
+ * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
diff --git a/arch/risc-v/src/bl602/bl602_boot2.h b/arch/risc-v/src/bl602/bl602_boot2.h
index e4611a7..cab98fc 100644
--- a/arch/risc-v/src/bl602/bl602_boot2.h
+++ b/arch/risc-v/src/bl602/bl602_boot2.h
@@ -1,6 +1,9 @@
/****************************************************************************
* arch/risc-v/src/bl602/bl602_boot2.h
*
+ * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
@@ -31,45 +34,42 @@
* Pre-processor Definitions
****************************************************************************/
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
/* Partition table error type definition */
-enum pt_table_error_e
-{
- PT_ERROR_SUCCESS, /* Partition table error type:success */
- PT_ERROR_TABLE_NOT_VALID, /* Partition table error type:entry not found */
- PT_ERROR_ENTRY_NOT_FOUND, /* Partition table error type:entry not found */
- PT_ERROR_ENTRY_UPDATE_FAIL, /* Partition table error type:entry update fail
- */
-
- PT_ERROR_CRC32, /* Partition table error type:crc32 error */
- PT_ERROR_PARAMETER, /* Partition table error type:input parameter error */
- PT_ERROR_FALSH_READ, /* Partition table error type:flash read error */
- PT_ERROR_FALSH_WRITE, /* Partition table error type:flash write error */
- PT_ERROR_FALSH_ERASE /* Partition table error type:flash erase error */
-};
+#define PT_ERROR_SUCCESS 0 /* Partition table error type:success */
+#define PT_ERROR_TABLE_NOT_VALID \
+ 1 /* Partition table error type:entry not found */
+#define PT_ERROR_ENTRY_NOT_FOUND \
+ 2 /* Partition table error type:entry not found */
+#define PT_ERROR_ENTRY_UPDATE_FAIL \
+ 3 /* Partition table error type:entry update fail */
+#define PT_ERROR_CRC32 4 /* Partition table error type:crc32 error */
+#define PT_ERROR_PARAMETER \
+ 5 /* Partition table error type:input parameter error */
+#define PT_ERROR_FALSH_READ \
+ 6 /* Partition table error type:flash read error */
+#define PT_ERROR_FALSH_WRITE \
+ 7 /* Partition table error type:flash write error */
+#define PT_ERROR_FALSH_ERASE \
+ 8 /* Partition table error type:flash erase error */
/* Partition id type definition */
-enum pt_table_id_e
-{
- PT_TABLE_ID_0, /* Partition table ID 0 */
- PT_TABLE_ID_1, /* Partition table ID 1 */
- PT_TABLE_ID_INVALID, /* Partition table ID invalid */
-};
+#define PT_TABLE_ID_0 0 /* Partition table ID 0 */
+#define PT_TABLE_ID_1 1 /* Partition table ID 1 */
+#define PT_TABLE_ID_INVALID 2 /* Partition table ID invalid */
/* Partition id type definition */
-enum pt_table_entry_type_e
-{
- PT_ENTRY_FW_CPU0, /* Partition entry type:CPU0 firmware */
- PT_ENTRY_FW_CPU1, /* Partition entry type:CPU1 firmware */
- PT_ENTRY_MAX = 16, /* Partition entry type:Max */
-};
+#define PT_ENTRY_FW_CPU0 0 /* Partition entry type:CPU0 firmware */
+#define PT_ENTRY_FW_CPU1 1 /* Partition entry type:CPU1 firmware */
+#define PT_ENTRY_MAX 16 /* Partition entry type:Max */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
/* Partition table config definition */
diff --git a/arch/risc-v/src/bl602/bl602_config.h b/arch/risc-v/src/bl602/bl602_config.h
index 74c199c..a5b9a12 100644
--- a/arch/risc-v/src/bl602/bl602_config.h
+++ b/arch/risc-v/src/bl602/bl602_config.h
@@ -1,6 +1,9 @@
/****************************************************************************
* arch/risc-v/src/bl602/bl602_config.h
*
+ * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
diff --git a/arch/risc-v/src/bl602/bl602_entry.S b/arch/risc-v/src/bl602/bl602_entry.S
index 6c0a659..a7e709f 100644
--- a/arch/risc-v/src/bl602/bl602_entry.S
+++ b/arch/risc-v/src/bl602/bl602_entry.S
@@ -1,6 +1,9 @@
/****************************************************************************
* arch/risc-v/src/bl602/bl602_entry.S
*
+ * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
@@ -24,121 +27,128 @@
#include <arch/csr.h>
- .section .init
- .globl bl602_start
- .globl __start
- .type bl602_start,@function
+ .section .init
+ .globl bl602_start
+ .globl __start
+ .type bl602_start,@function
__start:
bl602_start:
- .cfi_startproc
- .cfi_undefined ra
- .option push
- .option norelax
+ .cfi_startproc
+ .cfi_undefined ra
+ .option push
+ .option norelax
/*disable IRQ*/
- li t0, MSTATUS_MIE
- csrc mstatus, t0
+ li t0, MSTATUS_MIE
+ csrc mstatus, t0
- la gp, __global_pointer$
+ la gp, __global_pointer$
.option pop
- la sp, _sp_main
+ la sp, _sp_main
#ifndef RUN_IN_RAM
- /* Load boot2 partition address */
-
- la a0, __boot2_pt_addr_src
- la a1, __boot2_pt_addr_start
- la a2, __boot2_pt_addr_end
- bgeu a1, a2, 2f
-
-1:
- lw t0, (a0)
- sw t0, (a1)
- addi a0, a0, 4
- addi a1, a1, 4
- bltu a1, a2, 1b
-
-2:
- /* Load boot2 flashCfg address */
-
- jal boot2_get_flash_addr
- la a1, __boot2_flash_cfg_start
- la a2, __boot2_flash_cfg_end
- bgeu a1, a2, 2f
-
-1:
- lw t0, (a0)
- sw t0, (a1)
- addi a0, a0, 4
- addi a1, a1, 4
- bltu a1, a2, 1b
-
-2:
+
+ /* Load boot2 partition address */
+
+ la a0, __boot2_pt_addr_src
+ la a1, __boot2_pt_addr_start
+ la a2, __boot2_pt_addr_end
+ bgeu a1, a2, bl602_entry_load_boot2_partiton_address_end
+
+bl602_entry_load_boot2_partiton_address_loop:
+ lw t0, (a0)
+ sw t0, (a1)
+ addi a0, a0, 4
+ addi a1, a1, 4
+ bltu a1, a2, bl602_entry_load_boot2_partiton_address_loop
+
+bl602_entry_load_boot2_partiton_address_end:
+
+ /* Load boot2 flashCfg address */
+
+ jal boot2_get_flash_addr
+ la a1, __boot2_flash_cfg_start
+ la a2, __boot2_flash_cfg_end
+ bgeu a1, a2, bl602_entry_load_boot2_flashcfg_address_end
+
+bl602_entry_load_boot2_flashcfg_address_loop:
+ lw t0, (a0)
+ sw t0, (a1)
+ addi a0, a0, 4
+ addi a1, a1, 4
+ bltu a1, a2, bl602_entry_load_boot2_flashcfg_address_loop
+
+bl602_entry_load_boot2_flashcfg_address_end:
#endif
- /* Load data section */
- la a0, _data_load
- la a1, _data_run
- la a2, _data_run_end
- bgeu a1, a2, 2f
+ /* Load data section */
+
+ la a0, _data_load
+ la a1, _data_run
+ la a2, _data_run_end
+ bgeu a1, a2, bl602_entry_load_data_section_end
+
+bl602_entry_load_data_section_loop:
+ lw t0, (a0)
+ sw t0, (a1)
+ addi a0, a0, 4
+ addi a1, a1, 4
+ bltu a1, a2, bl602_entry_load_data_section_loop
-1:
- lw t0, (a0)
- sw t0, (a1)
- addi a0, a0, 4
- addi a1, a1, 4
- bltu a1, a2, 1b
+bl602_entry_load_data_section_end:
-2:
- /* Clear bss section */
+ /* Clear bss section */
- la a0, __bss_start
- la a1, __bss_end
- bgeu a0, a1, 3f
+ la a0, __bss_start
+ la a1, __bss_end
+ bgeu a0, a1, bl602_entry_zero_bss_end
-1:
- sw zero, (a0)
- addi a0, a0, 4
- bltu a0, a1, 1b
+bl602_entry_zero_bss_loop:
+ sw zero, (a0)
+ addi a0, a0, 4
+ bltu a0, a1, bl602_entry_zero_bss_loop
+bl602_entry_zero_bss_end:
- /* Clear bss section */
+ /* Clear bss section */
- la a0, __wifi_bss_start
- la a1, __wifi_bss_end
- bgeu a0, a1, 3f
+ la a0, __wifi_bss_start
+ la a1, __wifi_bss_end
+ bgeu a0, a1, bl602_entry_zero_wifi_bss_end
-1:
- sw zero, (a0)
- addi a0, a0, 4
- bltu a0, a1, 1b
+bl602_entry_zero_wifi_bss_loop:
+ sw zero, (a0)
+ addi a0, a0, 4
+ bltu a0, a1, bl602_entry_zero_wifi_bss_loop
+bl602_entry_zero_wifi_bss_end:
-3:
#ifndef __riscv_float_abi_soft
- /* Enable FPU */
- li t0, MSTATUS_FS
- csrs mstatus, t0
- csrr t1, mstatus
- and t1, t1, t0
- beqz t1, 1f
- fssr x0
-
-1:
+
+ /* Enable FPU */
+
+ li t0, MSTATUS_FS
+ csrs mstatus, t0
+ csrr t1, mstatus
+ and t1, t1, t0
+ beqz t1, bl602_entry_enable_fpu_end
+ fssr x0
+
+bl602_entry_enable_fpu_end:
#endif
- auipc ra, 0
- addi sp, sp, -16
- sw ra, 8(sp)
+ auipc ra, 0
+ addi sp, sp, -16
+ sw ra, 8(sp)
- /* argc = argv = 0 */
+ /* argc = argv = 0 */
- li a0, 0
- li a1, 0
- call bfl_main
+ li a0, 0
+ li a1, 0
+ call bfl_main
-1:
- j 1b
+bl602_entry_deadloop:
+ j bl602_entry_deadloop
- .cfi_endproc
+ .cfi_endproc
diff --git a/arch/risc-v/src/bl602/bl602_glb.c b/arch/risc-v/src/bl602/bl602_glb.c
index c517ba1..8ed11a3b 100644
--- a/arch/risc-v/src/bl602/bl602_glb.c
+++ b/arch/risc-v/src/bl602/bl602_glb.c
@@ -1,6 +1,9 @@
/****************************************************************************
* arch/risc-v/src/bl602/bl602_glb.c
*
+ * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
@@ -23,13 +26,14 @@
****************************************************************************/
#include "hardware/bl602_glb.h"
+#include "riscv_arch.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
- * Name: glb_uart_fun_sel
+ * Name: bl602_glb_uart_fun_sel
*
* Description:
* Select UART signal function.
@@ -43,12 +47,13 @@
*
****************************************************************************/
-void glb_uart_fun_sel(enum glb_uart_sig_e sig, enum glb_uart_sig_fun_e fun)
+void bl602_glb_uart_fun_sel(int sig, int fun)
{
uint32_t sig_pos = 0;
uint32_t tmp_val = 0;
- tmp_val = BL_RD_REG(GLB_BASE, GLB_UART_SIG_SEL_0);
+ tmp_val = getreg32(GLB_BASE + GLB_UART_SIG_SEL_0_OFFSET);
+
sig_pos = (sig * 4);
/* Clear original val */
@@ -58,11 +63,11 @@ void glb_uart_fun_sel(enum glb_uart_sig_e sig, enum glb_uart_sig_fun_e fun)
/* Set new value */
tmp_val = tmp_val | (fun << sig_pos);
- BL_WR_REG(GLB_BASE, GLB_UART_SIG_SEL_0, tmp_val);
+ putreg32(tmp_val, GLB_BASE + GLB_UART_SIG_SEL_0_OFFSET);
}
/****************************************************************************
- * Name: glb_ahb_slave1_reset
+ * Name: bl602_glb_ahb_slave1_reset
*
* Description:
* Select UART signal function.
@@ -76,20 +81,31 @@ void glb_uart_fun_sel(enum glb_uart_sig_e sig, enum glb_uart_sig_fun_e fun)
*
****************************************************************************/
-void glb_ahb_slave1_reset(enum bl_ahb_slave1_e slave1)
+void bl602_glb_ahb_slave1_reset(uint32_t slave1)
{
uint32_t tmp_val = 0;
- tmp_val = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1);
+ tmp_val = getreg32(GLB_BASE + GLB_SWRST_CFG1_OFFSET);
tmp_val &= (~(1 << slave1));
- BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmp_val);
- BL_DRV_DUMMY;
- tmp_val = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1);
+ putreg32(tmp_val, GLB_BASE + GLB_SWRST_CFG1_OFFSET);
+
+ /* It is to prevent glitch, which cannot be accessed via bus immediately
+ * after certain register operations, so some nop is added
+ */
+
+ BL_DRV_DUMMY();
+
+ tmp_val = getreg32(GLB_BASE + GLB_SWRST_CFG1_OFFSET);
tmp_val |= (1 << slave1);
- BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmp_val);
- BL_DRV_DUMMY;
- tmp_val = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1);
+ putreg32(tmp_val, GLB_BASE + GLB_SWRST_CFG1_OFFSET);
+
+ /* It is to prevent glitch, which cannot be accessed via bus immediately
+ * after certain register operations, so some nop is added
+ */
+
+ BL_DRV_DUMMY();
+
+ tmp_val = getreg32(GLB_BASE + GLB_SWRST_CFG1_OFFSET);
tmp_val &= (~(1 << slave1));
- BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmp_val);
+ putreg32(tmp_val, GLB_BASE + GLB_SWRST_CFG1_OFFSET);
}
-
diff --git a/arch/risc-v/src/bl602/bl602_gpio.c b/arch/risc-v/src/bl602/bl602_gpio.c
index 6c2fc29..dd2cc24 100644
--- a/arch/risc-v/src/bl602/bl602_gpio.c
+++ b/arch/risc-v/src/bl602/bl602_gpio.c
@@ -1,6 +1,9 @@
/****************************************************************************
* arch/risc-v/src/bl602/bl602_gpio.c
*
+ * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
@@ -25,13 +28,14 @@
#include <stdint.h>
#include "hardware/bl602_gpio.h"
#include "hardware/bl602_glb.h"
+#include "riscv_arch.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
- * Name: gpio_init
+ * Name: bl602_gpio_init
*
* Description:
* Init a gpio pin.
@@ -48,7 +52,7 @@
*
****************************************************************************/
-void gpio_init(struct gpio_cfg_s *cfg)
+void bl602_gpio_init(struct gpio_cfg_s *cfg)
{
uint8_t gpio_pin = cfg->gpio_pin;
uint32_t *p_out;
@@ -66,7 +70,7 @@ void gpio_init(struct gpio_cfg_s *cfg)
tmp_out &= (~(1 << pos));
*p_out = tmp_out;
- tmp_val = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpio_pin / 2 * 4);
+ tmp_val = getreg32(GLB_BASE + GLB_GPIO_OFFSET + gpio_pin / 2 * 4);
if (gpio_pin % 2 == 0)
{
@@ -74,32 +78,33 @@ void gpio_init(struct gpio_cfg_s *cfg)
if (cfg->gpio_mode == GPIO_MODE_OUTPUT)
{
- tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_REG_GPIO_0_IE);
+ tmp_val = tmp_val & GLB_REG_GPIO_0_IE_UMSK;
tmp_out |= (1 << pos);
}
else
{
- tmp_val = BL_SET_REG_BIT(tmp_val, GLB_REG_GPIO_0_IE);
+ tmp_val = tmp_val | (1 << GLB_REG_GPIO_0_IE_POS);
}
/* Set pull up or down */
- tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_REG_GPIO_0_PU);
- tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_REG_GPIO_0_PD);
+ tmp_val &= GLB_REG_GPIO_0_PU_UMSK;
+ tmp_val &= GLB_REG_GPIO_0_PD_UMSK;
if (cfg->pull_type == GPIO_PULL_UP)
{
- tmp_val = BL_SET_REG_BIT(tmp_val, GLB_REG_GPIO_0_PU);
+ tmp_val = tmp_val | (1 << GLB_REG_GPIO_0_PU_POS);
}
else if (cfg->pull_type == GPIO_PULL_DOWN)
{
- tmp_val = BL_SET_REG_BIT(tmp_val, GLB_REG_GPIO_0_PD);
+ tmp_val = tmp_val | (1 << GLB_REG_GPIO_0_PD_POS);
}
- tmp_val = BL_SET_REG_BITS_VAL(tmp_val, GLB_REG_GPIO_0_DRV, cfg->drive);
- tmp_val =
- BL_SET_REG_BITS_VAL(tmp_val, GLB_REG_GPIO_0_SMT, cfg->smt_ctrl);
- tmp_val =
- BL_SET_REG_BITS_VAL(tmp_val, GLB_REG_GPIO_0_FUNC_SEL, cfg->gpio_fun);
+ tmp_val = (tmp_val & GLB_REG_GPIO_0_DRV_UMSK) |
+ (cfg->drive << GLB_REG_GPIO_0_DRV_POS);
+ tmp_val = (tmp_val & GLB_REG_GPIO_0_SMT_UMSK) |
+ (cfg->smt_ctrl << GLB_REG_GPIO_0_SMT_POS);
+ tmp_val = (tmp_val & GLB_REG_GPIO_0_FUNC_SEL_UMSK) |
+ (cfg->gpio_fun << GLB_REG_GPIO_0_FUNC_SEL_POS);
}
else
{
@@ -107,36 +112,36 @@ void gpio_init(struct gpio_cfg_s *cfg)
if (cfg->gpio_mode == GPIO_MODE_OUTPUT)
{
- tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_REG_GPIO_1_IE);
+ tmp_val &= GLB_REG_GPIO_1_IE_UMSK;
tmp_out |= (1 << pos);
}
else
{
- tmp_val = BL_SET_REG_BIT(tmp_val, GLB_REG_GPIO_1_IE);
+ tmp_val = tmp_val | (1 << GLB_REG_GPIO_1_IE_POS);
}
/* Set pull up or down */
- tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_REG_GPIO_1_PU);
- tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_REG_GPIO_1_PD);
+ tmp_val &= GLB_REG_GPIO_1_PU_UMSK;
+ tmp_val &= GLB_REG_GPIO_1_PD_UMSK;
if (cfg->pull_type == GPIO_PULL_UP)
{
- tmp_val = BL_SET_REG_BIT(tmp_val, GLB_REG_GPIO_1_PU);
+ tmp_val = tmp_val | (1 << GLB_REG_GPIO_1_PU_POS);
}
else if (cfg->pull_type == GPIO_PULL_DOWN)
{
- tmp_val = BL_SET_REG_BIT(tmp_val, GLB_REG_GPIO_1_PD);
+ tmp_val = tmp_val | (1 << GLB_REG_GPIO_1_PD_POS);
}
- tmp_val = BL_SET_REG_BITS_VAL(tmp_val, GLB_REG_GPIO_1_DRV, cfg->drive);
- tmp_val =
- BL_SET_REG_BITS_VAL(tmp_val, GLB_REG_GPIO_1_SMT, cfg->smt_ctrl);
- tmp_val =
- BL_SET_REG_BITS_VAL(tmp_val, GLB_REG_GPIO_1_FUNC_SEL, cfg->gpio_fun);
+ tmp_val = (tmp_val & GLB_REG_GPIO_1_DRV_UMSK) |
+ (cfg->drive << GLB_REG_GPIO_1_DRV_POS);
+ tmp_val = (tmp_val & GLB_REG_GPIO_1_SMT_UMSK) |
+ (cfg->smt_ctrl << GLB_REG_GPIO_1_SMT_POS);
+ tmp_val = (tmp_val & GLB_REG_GPIO_1_FUNC_SEL_UMSK) |
+ (cfg->gpio_fun << GLB_REG_GPIO_1_FUNC_SEL_POS);
}
- BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpio_pin / 2 * 4, tmp_val);
+ putreg32(tmp_val, GLB_BASE + GLB_GPIO_OFFSET + gpio_pin / 2 * 4);
*p_out = tmp_out;
}
-
diff --git a/arch/risc-v/src/bl602/bl602_hbn.c b/arch/risc-v/src/bl602/bl602_hbn.c
index cb58d21..884353c 100644
--- a/arch/risc-v/src/bl602/bl602_hbn.c
+++ b/arch/risc-v/src/bl602/bl602_hbn.c
@@ -1,6 +1,8 @@
/****************************************************************************
- * <Relative path to the file>
- * <Optional one line file description>
+ * arch/risc-v/src/bl602/bl602_hbn.c
+ *
+ * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -24,13 +26,14 @@
****************************************************************************/
#include "hardware/bl602_hbn.h"
+#include "riscv_arch.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
- * Name: hbn_set_uart_clk_sel
+ * Name: bl602_hbn_set_uart_clk_sel
*
* Description:
* Select uart clock source.
@@ -47,12 +50,12 @@
*
****************************************************************************/
-void hbn_set_uart_clk_sel(enum hbn_uart_clk_type_e clk_sel)
+void bl602_hbn_set_uart_clk_sel(int clk_sel)
{
uint32_t tmp_val;
- tmp_val = BL_RD_REG(HBN_BASE, HBN_GLB);
- tmp_val = BL_SET_REG_BITS_VAL(tmp_val, HBN_UART_CLK_SEL, clk_sel);
- BL_WR_REG(HBN_BASE, HBN_GLB, tmp_val);
+ tmp_val = getreg32(HBN_BASE + HBN_GLB_OFFSET);
+ tmp_val &= ~(1 << 2);
+ tmp_val |= (clk_sel << 2);
+ putreg32(tmp_val, HBN_BASE + HBN_GLB_OFFSET);
}
-
diff --git a/arch/risc-v/src/bl602/bl602_head.S b/arch/risc-v/src/bl602/bl602_head.S
index 33b1703..3fc0ea6 100644
--- a/arch/risc-v/src/bl602/bl602_head.S
+++ b/arch/risc-v/src/bl602/bl602_head.S
@@ -1,6 +1,9 @@
/****************************************************************************
* arch/risc-v/src/bl602/bl602_head.S
*
+ * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
@@ -34,6 +37,7 @@
/****************************************************************************
* Name: exception_common
****************************************************************************/
+
.align 8
exception_common:
diff --git a/arch/risc-v/src/bl602/bl602_idle.c b/arch/risc-v/src/bl602/bl602_idle.c
index 36f096a..64f4f53 100644
--- a/arch/risc-v/src/bl602/bl602_idle.c
+++ b/arch/risc-v/src/bl602/bl602_idle.c
@@ -1,6 +1,9 @@
/****************************************************************************
* arch/risc-v/src/bl602/bl602_idle.c
*
+ * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
@@ -65,4 +68,3 @@ void up_idle(void)
#endif
}
-
diff --git a/arch/risc-v/src/bl602/bl602_irq.c b/arch/risc-v/src/bl602/bl602_irq.c
index 9b6d748..60e9291 100644
--- a/arch/risc-v/src/bl602/bl602_irq.c
+++ b/arch/risc-v/src/bl602/bl602_irq.c
@@ -1,6 +1,9 @@
/****************************************************************************
* arch/risc-v/src/bl602/bl602_irq.c
*
+ * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
@@ -46,22 +49,22 @@
static inline void bl_irq_enable(unsigned int source)
{
- *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIE + source) = 1;
+ putreg8(1, CLIC_HART0_ADDR + CLIC_INTIE + source);
}
static inline void bl_irq_disable(unsigned int source)
{
- *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIE + source) = 0;
+ putreg8(0, CLIC_HART0_ADDR + CLIC_INTIE + source);
}
static inline void bl_irq_pending_set(unsigned int source)
{
- *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + source) = 1;
+ putreg8(1, CLIC_HART0_ADDR + CLIC_INTIP + source);
}
static inline void bl_irq_pending_clear(unsigned int source)
{
- *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + source) = 0;
+ putreg8(0, CLIC_HART0_ADDR + CLIC_INTIP + source);
}
/****************************************************************************
@@ -122,7 +125,7 @@ void up_disable_irq(int irq)
}
else if (irq == BL602_IRQ_MTIMER)
{
- *(volatile uint8_t *)CLIC_TIMER_ENABLE_ADDRESS = 0;
+ putreg8(0, CLIC_TIMER_ENABLE_ADDRESS);
/* Read mstatus & clear machine timer interrupt enable in mie */
@@ -155,7 +158,7 @@ void up_enable_irq(int irq)
}
else if (irq == BL602_IRQ_MTIMER)
{
- *(volatile uint8_t *)CLIC_TIMER_ENABLE_ADDRESS = 1;
+ putreg8(1, CLIC_TIMER_ENABLE_ADDRESS);
/* Read mstatus & set machine timer interrupt enable in mie */
@@ -255,4 +258,3 @@ irqstate_t up_irq_enable(void)
asm volatile("csrrs %0, mstatus, %1" : "=r"(oldstat) : "r"(MSTATUS_MIE));
return oldstat;
}
-
diff --git a/arch/risc-v/src/bl602/bl602_irq_dispatch.c b/arch/risc-v/src/bl602/bl602_irq_dispatch.c
index bdc1452..60f71a6 100644
--- a/arch/risc-v/src/bl602/bl602_irq_dispatch.c
+++ b/arch/risc-v/src/bl602/bl602_irq_dispatch.c
@@ -1,6 +1,9 @@
/****************************************************************************
* arch/risc-v/src/bl602/bl602_irq_dispatch.c
*
+ * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
@@ -103,4 +106,3 @@ void *bl602_dispatch_irq(uint32_t vector, uint32_t *regs)
return regs;
}
-
diff --git a/arch/risc-v/src/bl602/bl602_lowputc.c b/arch/risc-v/src/bl602/bl602_lowputc.c
index 6e66b6b..66c4810 100644
--- a/arch/risc-v/src/bl602/bl602_lowputc.c
+++ b/arch/risc-v/src/bl602/bl602_lowputc.c
@@ -1,6 +1,9 @@
/****************************************************************************
* boards/risc-v/bl602/evb/src/bl602_lowputc.c
*
+ * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
@@ -54,6 +57,7 @@
****************************************************************************/
/* Select UART parameters for the selected console */
+
#ifdef HAVE_SERIAL_CONSOLE
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
#define BL602_CONSOLE_IDX 0
@@ -144,9 +148,9 @@ static void uart_gpio_init(uint8_t id,
uint8_t cts_pin,
uint8_t rts_pin)
{
- struct gpio_cfg_s cfg;
- enum glb_uart_sig_fun_e tx_sigfun;
- enum glb_uart_sig_fun_e rx_sigfun;
+ struct gpio_cfg_s cfg;
+ int tx_sigfun;
+ int rx_sigfun;
cfg.drive = 1;
cfg.smt_ctrl = 1;
@@ -155,12 +159,12 @@ static void uart_gpio_init(uint8_t id,
cfg.gpio_pin = rx_pin;
cfg.gpio_mode = GPIO_MODE_AF;
cfg.pull_type = GPIO_PULL_UP;
- gpio_init(&cfg);
+ bl602_gpio_init(&cfg);
cfg.gpio_pin = tx_pin;
cfg.gpio_mode = GPIO_MODE_AF;
cfg.pull_type = GPIO_PULL_UP;
- gpio_init(&cfg);
+ bl602_gpio_init(&cfg);
/* select uart gpio function */
@@ -175,61 +179,86 @@ static void uart_gpio_init(uint8_t id,
rx_sigfun = GLB_UART_SIG_FUN_UART1_RXD;
}
- glb_uart_fun_sel(tx_pin % 8, tx_sigfun);
- glb_uart_fun_sel(rx_pin % 8, rx_sigfun);
+ bl602_glb_uart_fun_sel(tx_pin % 8, tx_sigfun);
+ bl602_glb_uart_fun_sel(rx_pin % 8, rx_sigfun);
}
-static void bl602_enable_uart_clk(uint8_t enable,
- enum hbn_uart_clk_type_e clk_sel,
- uint8_t div)
+static void bl602_enable_uart_clk(uint8_t enable, int clk_sel, uint8_t div)
{
uint32_t tmp_val;
/* disable UART clock first */
- tmp_val = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
- tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_UART_CLK_EN);
- BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmp_val);
+ bl602_up_serialmodify(GLB_BASE, GLB_CLK_CFG2_OFFSET, (1 << 4), 0);
/* Set div */
- tmp_val = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
- tmp_val = BL_SET_REG_BITS_VAL(tmp_val, GLB_UART_CLK_DIV, div);
- BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmp_val);
+ bl602_up_serialmodify(GLB_BASE, GLB_CLK_CFG2_OFFSET, 0x7, div);
/* Select clock source for uart */
- hbn_set_uart_clk_sel(clk_sel);
+ bl602_hbn_set_uart_clk_sel(clk_sel);
/* Set enable or disable */
- tmp_val = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+ tmp_val = bl602_up_serialin(GLB_BASE, GLB_CLK_CFG2_OFFSET);
if (enable)
{
- tmp_val = BL_SET_REG_BIT(tmp_val, GLB_UART_CLK_EN);
+ tmp_val |= (1 << 4);
}
else
{
- tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_UART_CLK_EN);
+ tmp_val &= ~(1 << 4);
}
- BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmp_val);
+ bl602_up_serialout(GLB_BASE, GLB_CLK_CFG2_OFFSET, tmp_val);
}
/****************************************************************************
* Public Functions
****************************************************************************/
+uint32_t bl602_up_serialin(uint32_t reg_base, int offset)
+{
+ return getreg32(reg_base + offset);
+}
+
+void bl602_up_serialout(uint32_t reg_base, int offset, uint32_t value)
+{
+ putreg32(value, reg_base + offset);
+}
+
+void bl602_up_serialmodify(uint32_t reg_base,
+ int offset,
+ uint32_t clearbits,
+ uint32_t setbits)
+{
+ modifyreg32(reg_base + offset, clearbits, setbits);
+}
+
+/****************************************************************************
+ * Name: bl602_data_setbits
+ ****************************************************************************/
+
+static uint32_t bl602_data_setbits(uint32_t data,
+ uint32_t start,
+ uint32_t len,
+ uint32_t value)
+{
+ return (((data) & ~((~((~0) << (len))) << (start))) |
+ (((value) & ((~((~0) << (len))))) << (start)));
+}
+
void bl602_uart_configure(uint32_t uartbase,
const struct uart_config_s *config)
{
- uint32_t tmp_val;
- uint32_t div = 0;
- uint32_t fraction = 0;
- uint32_t tmp_tx_cfg = 0;
- uint32_t tmp_rx_cfg = 0;
- enum uart_databits_e data_bits;
- enum uart_stopbits_e stop_bits;
+ uint32_t tmp_val;
+ uint32_t div = 0;
+ uint32_t fraction = 0;
+ uint32_t tmp_tx_cfg = 0;
+ uint32_t tmp_rx_cfg = 0;
+ int data_bits;
+ int stop_bits;
bl602_enable_uart_clk(1, HBN_UART_CLK_160M, 3);
@@ -241,18 +270,12 @@ void bl602_uart_configure(uint32_t uartbase,
/* Disable all interrupt */
- tmp_val = BL_RD_REG(uartbase, UART_INT_MASK);
- tmp_val |= 0xff;
- BL_WR_REG(uartbase, UART_INT_MASK, tmp_val);
+ bl602_up_serialmodify(uartbase, UART_INT_MASK_OFFSET, 0, 0xff);
/* Disable uart before config */
- tmp_val = BL_RD_REG(uartbase, UART_UTX_CONFIG);
- BL_WR_REG(
- uartbase, UART_UTX_CONFIG, BL_CLR_REG_BIT(tmp_val, UART_CR_UTX_EN));
- tmp_val = BL_RD_REG(uartbase, UART_URX_CONFIG);
- BL_WR_REG(
- uartbase, UART_URX_CONFIG, BL_CLR_REG_BIT(tmp_val, UART_CR_URX_EN));
+ bl602_up_serialmodify(uartbase, UART_UTX_CONFIG_OFFSET, 1, 0);
+ bl602_up_serialmodify(uartbase, UART_URX_CONFIG_OFFSET, 1, 0);
/* cal the baud rate divisor */
@@ -265,31 +288,32 @@ void bl602_uart_configure(uint32_t uartbase,
/* set the baud rate register value */
- BL_WR_REG(
- uartbase, UART_BIT_PRD, ((div - 1) << 0x10) | ((div - 1) & 0xffff));
+ bl602_up_serialout(uartbase,
+ UART_BIT_PRD_OFFSET,
+ ((div - 1) << 0x10) | ((div - 1) & 0xffff));
/* configure parity type */
- tmp_tx_cfg = BL_RD_REG(uartbase, UART_UTX_CONFIG);
- tmp_rx_cfg = BL_RD_REG(uartbase, UART_URX_CONFIG);
+ tmp_tx_cfg = bl602_up_serialin(uartbase, UART_UTX_CONFIG_OFFSET);
+ tmp_rx_cfg = bl602_up_serialin(uartbase, UART_URX_CONFIG_OFFSET);
switch (config->parity)
{
case UART_PARITY_NONE:
- tmp_tx_cfg = BL_CLR_REG_BIT(tmp_tx_cfg, UART_CR_UTX_PRT_EN);
- tmp_rx_cfg = BL_CLR_REG_BIT(tmp_rx_cfg, UART_CR_URX_PRT_EN);
+ tmp_tx_cfg &= ~(1 << 4);
+ tmp_rx_cfg &= ~(1 << 4);
break;
case UART_PARITY_ODD:
- tmp_tx_cfg = BL_SET_REG_BIT(tmp_tx_cfg, UART_CR_UTX_PRT_EN);
- tmp_tx_cfg = BL_SET_REG_BIT(tmp_tx_cfg, UART_CR_UTX_PRT_SEL);
- tmp_rx_cfg = BL_SET_REG_BIT(tmp_rx_cfg, UART_CR_URX_PRT_EN);
- tmp_rx_cfg = BL_SET_REG_BIT(tmp_rx_cfg, UART_CR_URX_PRT_SEL);
+ tmp_tx_cfg |= 1 << 4;
+ tmp_tx_cfg |= 1 << 5;
+ tmp_rx_cfg |= 1 << 4;
+ tmp_rx_cfg |= 1 << 5;
break;
case UART_PARITY_EVEN:
- tmp_tx_cfg = BL_SET_REG_BIT(tmp_tx_cfg, UART_CR_UTX_PRT_EN);
- tmp_tx_cfg = BL_CLR_REG_BIT(tmp_tx_cfg, UART_CR_UTX_PRT_SEL);
- tmp_rx_cfg = BL_SET_REG_BIT(tmp_rx_cfg, UART_CR_URX_PRT_EN);
- tmp_rx_cfg = BL_CLR_REG_BIT(tmp_rx_cfg, UART_CR_URX_PRT_SEL);
+ tmp_tx_cfg |= 1 << 4;
+ tmp_tx_cfg &= ~(1 << 5);
+ tmp_rx_cfg |= 1 << 4;
+ tmp_rx_cfg &= ~(1 << 5);
break;
default:
break;
@@ -323,78 +347,61 @@ void bl602_uart_configure(uint32_t uartbase,
/* Configure data bits */
- tmp_tx_cfg =
- BL_SET_REG_BITS_VAL(tmp_tx_cfg, UART_CR_UTX_BIT_CNT_D, (data_bits + 4));
- tmp_rx_cfg =
- BL_SET_REG_BITS_VAL(tmp_rx_cfg, UART_CR_URX_BIT_CNT_D, (data_bits + 4));
+ tmp_tx_cfg = bl602_data_setbits(tmp_tx_cfg, 8, 3, (data_bits + 4));
+ tmp_rx_cfg = bl602_data_setbits(tmp_tx_cfg, 8, 3, (data_bits + 4));
/* Configure tx stop bits */
- tmp_tx_cfg =
- BL_SET_REG_BITS_VAL(tmp_tx_cfg, UART_CR_UTX_BIT_CNT_P, (stop_bits + 1));
+ tmp_tx_cfg = bl602_data_setbits(tmp_tx_cfg, 12, 2, (stop_bits + 1));
/* Configure tx cts flow control function */
if (config->oflow_ctl)
{
- tmp_tx_cfg = BL_SET_REG_BIT(tmp_tx_cfg, UART_CR_UTX_CTS_EN);
+ tmp_tx_cfg |= 1 << 1;
}
else
{
- tmp_tx_cfg = BL_CLR_REG_BIT(tmp_tx_cfg, UART_CR_UTX_CTS_EN);
+ tmp_tx_cfg &= ~(1 << 1);
}
/* Disable rx input de-glitch function */
- tmp_rx_cfg = BL_CLR_REG_BIT(tmp_rx_cfg, UART_CR_URX_DEG_EN);
+ tmp_rx_cfg &= ~(1 << 11);
if (config->iflow_ctl)
{
- tmp_tx_cfg = BL_SET_REG_BIT(tmp_tx_cfg, UART_CR_URX_RTS_SW_MODE);
+ tmp_rx_cfg |= 1 << 1;
}
else
{
- tmp_rx_cfg = BL_CLR_REG_BIT(tmp_rx_cfg, UART_CR_URX_RTS_SW_MODE);
+ tmp_rx_cfg &= ~(1 << 1);
}
/* Write back */
- BL_WR_REG(uartbase, UART_UTX_CONFIG, tmp_tx_cfg);
- BL_WR_REG(uartbase, UART_URX_CONFIG, tmp_rx_cfg);
+ bl602_up_serialout(uartbase, UART_UTX_CONFIG_OFFSET, tmp_tx_cfg);
+ bl602_up_serialout(uartbase, UART_URX_CONFIG_OFFSET, tmp_rx_cfg);
/* Configure LSB-first */
- tmp_tx_cfg = BL_RD_REG(uartbase, UART_DATA_CONFIG);
- tmp_tx_cfg = BL_CLR_REG_BIT(tmp_tx_cfg, UART_CR_UART_BIT_INV);
- BL_WR_REG(uartbase, UART_DATA_CONFIG, tmp_tx_cfg);
+ bl602_up_serialmodify(uartbase, UART_DATA_CONFIG_OFFSET, 1, 0);
/* Enable tx free run mode */
- tmp_val = BL_RD_REG(uartbase, UART_UTX_CONFIG);
- BL_WR_REG(
- uartbase, UART_UTX_CONFIG, BL_SET_REG_BIT(tmp_val, UART_CR_UTX_FRM_EN));
+ bl602_up_serialmodify(uartbase, UART_UTX_CONFIG_OFFSET, 0, 1 << 2);
/* Deal with uart fifo configure register */
- tmp_val = BL_RD_REG(uartbase, UART_FIFO_CONFIG_1);
-
- /* Configure dma tx fifo threshold */
-
- tmp_val = BL_SET_REG_BITS_VAL(tmp_val, UART_TX_FIFO_TH, 0x10 - 1);
-
- /* Configure dma rx fifo threshold */
-
- tmp_val = BL_SET_REG_BITS_VAL(tmp_val, UART_RX_FIFO_TH, 0x10 - 1);
- BL_WR_REG(uartbase, UART_FIFO_CONFIG_1, tmp_val);
+ tmp_val = bl602_up_serialin(uartbase, UART_FIFO_CONFIG_1_OFFSET);
+ tmp_val = bl602_data_setbits(tmp_val, UART_TX_FIFO_TH_POS, 5, 0x10 - 1);
+ tmp_val = bl602_data_setbits(tmp_val, UART_RX_FIFO_TH_POS, 5, 0x10 - 1);
+ bl602_up_serialout(uartbase, UART_FIFO_CONFIG_1_OFFSET, tmp_val);
/* Enable UART tx rx unit */
- tmp_val = BL_RD_REG(uartbase, UART_UTX_CONFIG);
- BL_WR_REG(
- uartbase, UART_UTX_CONFIG, BL_SET_REG_BIT(tmp_val, UART_CR_UTX_EN));
- tmp_val = BL_RD_REG(uartbase, UART_URX_CONFIG);
- BL_WR_REG(
- uartbase, UART_URX_CONFIG, BL_SET_REG_BIT(tmp_val, UART_CR_URX_EN));
+ bl602_up_serialmodify(uartbase, UART_UTX_CONFIG_OFFSET, 0, 1);
+ bl602_up_serialmodify(uartbase, UART_URX_CONFIG_OFFSET, 0, 1);
}
/****************************************************************************
@@ -411,11 +418,12 @@ void up_lowputc(char ch)
/* Wait for FIFO */
while (
- BL_GET_REG_BITS_VAL(BL_RD_REG(BL602_CONSOLE_BASE, UART_FIFO_CONFIG_1),
- UART_TX_FIFO_CNT) == 0)
+ ((bl602_up_serialin(BL602_CONSOLE_BASE, UART_FIFO_CONFIG_1_OFFSET)) >>
+ (UART_TX_FIFO_CNT_POS)) &
+ (~((~0) << (6))))
;
- BL_WR_BYTE(BL602_CONSOLE_BASE + UART_FIFO_WDATA_OFFSET, ch);
+ bl602_up_serialout(BL602_CONSOLE_BASE, UART_FIFO_WDATA_OFFSET, ch);
#endif /* HAVE_CONSOLE */
}
@@ -428,4 +436,3 @@ void bl602_lowsetup(void)
#endif /* HAVE_SERIAL_CONSOLE */
}
-
diff --git a/arch/risc-v/src/bl602/bl602_lowputc.h b/arch/risc-v/src/bl602/bl602_lowputc.h
index 07e728b..22d19ac 100644
--- a/arch/risc-v/src/bl602/bl602_lowputc.h
+++ b/arch/risc-v/src/bl602/bl602_lowputc.h
@@ -1,6 +1,9 @@
/**
* incubator-nuttx/arch/risc-v/src/bl602/bl602_lowputc.h
*
+ * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
@@ -31,15 +34,6 @@
#ifndef __ASSEMBLY__
-#undef EXTERN
-#if defined(__cplusplus)
-#define EXTERN extern "C"
-extern "C"
-{
-#else
-#define EXTERN extern
-#endif
-
struct uart_config_s
{
uint8_t idx; /* Uart idx */
@@ -55,13 +49,28 @@ struct uart_config_s
uint8_t rts_pin; /* RTS pin */
};
-/****************************************************************************
- * Name: bl602_lowsetup
- ****************************************************************************/
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+EXTERN uint32_t bl602_up_serialin(uint32_t reg_base, int offset);
+
+EXTERN void bl602_up_serialout(uint32_t reg_base, int offset,
+ uint32_t value);
+
+EXTERN void bl602_up_serialmodify(uint32_t reg_base,
+ int offset,
+ uint32_t clearbits,
+ uint32_t setbits);
EXTERN void bl602_lowsetup(void);
-EXTERN void bl602_uart_configure(uint32_t base_addr,
+EXTERN void bl602_uart_configure(uint32_t base_addr,
const struct uart_config_s *config);
#undef EXTERN
diff --git a/arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.c b/arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.c
index 535f59d..d652a06 100644
--- a/arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.c
+++ b/arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.c
@@ -1,8 +1,8 @@
/****************************************************************************
- * arch/arm/src/bl602/bl602_oneshot_lowerhalf.c
+ * arch/arm/src/bl602/bl602_oneshot_lowerhalf.c
*
- * Copyright (C) 2016 Gregory Nutt. All rights reserved.
- * Authors: Gregory Nutt <gn...@nuttx.org>
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt <gn...@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -48,9 +48,17 @@
#include <nuttx/kmalloc.h>
#include <nuttx/timers/oneshot.h>
+#include "riscv_arch.h"
+#include "riscv_internal.h"
+
#include <hardware/bl602_timer.h>
#include "bl602_oneshot_lowerhalf.h"
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Private definetions */
#define TIMER_MAX_VALUE (0xFFFFFFFF)
#define TIMER_CLK_DIV (160)
#define TIMER_CLK_FREQ (160000000UL / (TIMER_CLK_DIV))
@@ -142,15 +150,15 @@ static int bl602_oneshot_handler(int irq, FAR void *context, FAR void *arg)
uint32_t tmp_val;
uint32_t tmp_addr;
- int_id = BL_RD_WORD(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * priv->tim);
+ int_id = getreg32(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * priv->tim);
tmp_addr = TIMER_BASE + TIMER_TICR2_OFFSET + 4 * priv->tim;
- tmp_val = BL_RD_WORD(tmp_addr);
+ tmp_val = getreg32(tmp_addr);
/* Comparator 0 match interrupt */
- if (BL_IS_REG_BIT_SET(int_id, TIMER_TMSR_0))
+ if (((int_id) & (1 << (TIMER_TMSR_0_POS))) != 0)
{
- BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TCLR_0));
+ putreg32(tmp_val | (1 << TIMER_TCLR_0_POS), tmp_addr);
callback = priv->callback;
cbarg = priv->arg;
@@ -162,16 +170,16 @@ static int bl602_oneshot_handler(int irq, FAR void *context, FAR void *arg)
/* Comparator 1 match interrupt */
- if (BL_IS_REG_BIT_SET(int_id, TIMER_TMSR_1))
+ if (((int_id) & (1 << (TIMER_TMSR_1_POS))) != 0)
{
- BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TCLR_1));
+ putreg32(tmp_val | (1 << TIMER_TCLR_1_POS), tmp_addr);
}
/* Comparator 2 match interrupt */
- if (BL_IS_REG_BIT_SET(int_id, TIMER_TMSR_2))
+ if (((int_id) & (1 << (TIMER_TMSR_2_POS))) != 0)
{
- BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TCLR_2));
+ putreg32(tmp_val | (1 << TIMER_TCLR_2_POS), tmp_addr);
}
return 0;
@@ -265,14 +273,14 @@ static int bl602_start(FAR struct oneshot_lowerhalf_s *lower,
usec = (uint64_t)ts->tv_sec * USEC_PER_SEC +
(uint64_t)(ts->tv_nsec / NSEC_PER_USEC);
- timer_setcompvalue(
+ bl602_timer_setcompvalue(
priv->tim, TIMER_COMP_ID_0, usec / (TIMER_CLK_FREQ / priv->freq));
- timer_setpreloadvalue(priv->tim, 0);
+ bl602_timer_setpreloadvalue(priv->tim, 0);
irq_attach(priv->irq, bl602_oneshot_handler, (void *)priv);
up_enable_irq(priv->irq);
- timer_intmask(priv->tim, TIMER_INT_COMP_0, 0);
- timer_enable(priv->tim);
+ bl602_timer_intmask(priv->tim, TIMER_INT_COMP_0, 0);
+ bl602_timer_enable(priv->tim);
priv->started = true;
leave_critical_section(flags);
@@ -319,10 +327,10 @@ static int bl602_cancel(FAR struct oneshot_lowerhalf_s *lower,
{
flags = enter_critical_section();
- timer_disable(priv->tim);
+ bl602_timer_disable(priv->tim);
priv->started = false;
up_disable_irq(priv->irq);
- timer_intmask(priv->tim, TIMER_INT_COMP_0, 1);
+ bl602_timer_intmask(priv->tim, TIMER_INT_COMP_0, 1);
priv->callback = NULL;
priv->arg = NULL;
@@ -399,22 +407,21 @@ FAR struct oneshot_lowerhalf_s *oneshot_initialize(int chan,
timstr.count_mode = TIMER_COUNT_PRELOAD; /* Timer count mode */
timstr.clock_division =
- (TIMER_CLK_DIV * resolution) - 1; /* Timer clock divison value */
+ (TIMER_CLK_DIV * resolution) - 1; /* Timer clock divison value */
- timstr.match_val0 = TIMER_MAX_VALUE; /* Timer match 0 value 0 */
- timstr.match_val1 = TIMER_MAX_VALUE; /* Timer match 1 value 0 */
- timstr.match_val2 = TIMER_MAX_VALUE; /* Timer match 2 value 0 */
+ timstr.match_val0 = TIMER_MAX_VALUE; /* Timer match 0 value 0 */
+ timstr.match_val1 = TIMER_MAX_VALUE; /* Timer match 1 value 0 */
+ timstr.match_val2 = TIMER_MAX_VALUE; /* Timer match 2 value 0 */
timstr.pre_load_val = TIMER_MAX_VALUE; /* Timer preload value */
- timer_intmask(chan, TIMER_INT_ALL, 1);
+ bl602_timer_intmask(chan, TIMER_INT_ALL, 1);
/* timer disable */
- timer_disable(chan);
+ bl602_timer_disable(chan);
- timer_init(&timstr);
+ bl602_timer_init(&timstr);
return &priv->lh;
}
-
diff --git a/arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.h b/arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.h
index 3388d59..73a6205 100644
--- a/arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.h
+++ b/arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.h
@@ -1,8 +1,8 @@
/****************************************************************************
* arch/risc-v/src/bl602/bl602_oneshot.h
*
- * Copyright (C) 2016 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gn...@nuttx.org>
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -71,6 +71,7 @@
* Public Types
****************************************************************************/
+#ifndef __ASSEMBLY__
/* This describes the callback function that will be invoked when the oneshot
* timer expires. The oneshot fires, the client will receive:
*
@@ -208,5 +209,6 @@ int bl602_oneshot_cancel(struct bl602_oneshot_s *oneshot,
}
#endif
+#endif /* __ASSEMBLY__ */
#endif /* CONFIG_BL602_ONESHOT */
#endif /* __ARCH_ARM_SRC_BL602_ONESHOT_H */
diff --git a/arch/risc-v/src/bl602/bl602_serial.c b/arch/risc-v/src/bl602/bl602_serial.c
index 2c2e8fd..f5b8e83 100644
--- a/arch/risc-v/src/bl602/bl602_serial.c
+++ b/arch/risc-v/src/bl602/bl602_serial.c
@@ -1,6 +1,9 @@
/****************************************************************************
* arch/risc-v/src/bl602/bl602_serial.c
*
+ * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
@@ -312,15 +315,15 @@ static int __uart_interrupt(int irq, FAR void *context, FAR void *arg)
uint32_t tmp_val = 0;
uint32_t mask_val = 0;
- tmp_val = BL_RD_REG(uart_priv->uartbase, UART_INT_STS);
- mask_val = BL_RD_REG(uart_priv->uartbase, UART_INT_MASK);
+ tmp_val = bl602_up_serialin(uart_priv->uartbase, UART_INT_STS_OFFSET);
+ mask_val = bl602_up_serialin(uart_priv->uartbase, UART_INT_MASK_OFFSET);
/* Length of uart rx data transfer arrived interrupt */
- if (BL_IS_REG_BIT_SET(tmp_val, UART_URX_END_INT) &&
- !BL_IS_REG_BIT_SET(mask_val, UART_CR_URX_END_MASK))
+ if ((tmp_val & (1 << UART_URX_END_INT_POS)) &&
+ !(mask_val & (1 << UART_CR_URX_END_MASK_POS)))
{
- BL_WR_REG(uart_priv->uartbase, UART_INT_CLEAR, 0x2);
+ bl602_up_serialout(uart_priv->uartbase, UART_INT_CLEAR_OFFSET, 0x2);
/* Receive Data ready */
@@ -329,8 +332,8 @@ static int __uart_interrupt(int irq, FAR void *context, FAR void *arg)
/* Tx fifo ready interrupt,auto-cleared when data is pushed */
- if (BL_IS_REG_BIT_SET(tmp_val, UART_UTX_FIFO_INT) &&
- !BL_IS_REG_BIT_SET(mask_val, UART_CR_UTX_FIFO_MASK))
+ if ((tmp_val & (1 << UART_UTX_FIFO_INT_POS)) &&
+ !(mask_val & (1 << UART_CR_UTX_FIFO_MASK_POS)))
{
/* Transmit data request interrupt */
@@ -339,8 +342,8 @@ static int __uart_interrupt(int irq, FAR void *context, FAR void *arg)
/* Rx fifo ready interrupt,auto-cleared when data is popped */
- if (BL_IS_REG_BIT_SET(tmp_val, UART_URX_FIFO_INT) &&
- !BL_IS_REG_BIT_SET(mask_val, UART_CR_URX_FIFO_MASK))
+ if ((tmp_val & (1 << UART_URX_FIFO_INT_POS)) &&
+ !(mask_val & (1 << UART_CR_URX_FIFO_MASK_POS)))
{
/* Receive Data ready */
@@ -378,20 +381,12 @@ static int up_setup(struct uart_dev_s *dev)
static void up_shutdown(struct uart_dev_s *dev)
{
- uint32_t tmp_val;
struct up_dev_s *uart_priv = (struct up_dev_s *)dev->priv;
/* Disable uart before config */
- tmp_val = BL_RD_REG(uart_priv->uartbase, UART_UTX_CONFIG);
- BL_WR_REG(uart_priv->uartbase,
- UART_UTX_CONFIG,
- BL_CLR_REG_BIT(tmp_val, UART_CR_UTX_EN));
-
- tmp_val = BL_RD_REG(uart_priv->uartbase, UART_URX_CONFIG);
- BL_WR_REG(uart_priv->uartbase,
- UART_URX_CONFIG,
- BL_CLR_REG_BIT(tmp_val, UART_CR_URX_EN));
+ bl602_up_serialmodify(uart_priv->uartbase, UART_UTX_CONFIG_OFFSET, 1, 0);
+ bl602_up_serialmodify(uart_priv->uartbase, UART_URX_CONFIG_OFFSET, 1, 0);
}
/****************************************************************************
@@ -447,6 +442,16 @@ static void up_detach(struct uart_dev_s *dev)
}
/****************************************************************************
+ * Name: bl602_data_getbits
+ ****************************************************************************/
+
+static uint32_t
+bl602_data_getbits(uint32_t data, uint32_t start, uint32_t len)
+{
+ return (((data) >> (start)) & (~((~0) << (len))));
+}
+
+/****************************************************************************
* Name: up_ioctl
*
* Description:
@@ -613,9 +618,11 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
* implement TCSADRAIN / TCSAFLUSH
*/
- tmp_val = BL_RD_REG(priv->uartbase, UART_INT_MASK);
+ tmp_val =
+ bl602_up_serialin(priv->uartbase, UART_INT_MASK_OFFSET);
bl602_uart_configure(priv->uartbase, &config);
- BL_WR_REG(priv->uartbase, UART_INT_MASK, tmp_val);
+ bl602_up_serialout(
+ priv->uartbase, UART_INT_MASK_OFFSET, tmp_val);
}
}
while (0);
@@ -654,10 +661,12 @@ static int up_receive(struct uart_dev_s *dev, unsigned int *status)
/* if uart fifo cnts > 0 */
- if (BL_GET_REG_BITS_VAL(BL_RD_REG(priv->uartbase, UART_FIFO_CONFIG_1),
- UART_RX_FIFO_CNT) > 0)
+ if (bl602_data_getbits(
+ bl602_up_serialin(priv->uartbase, UART_FIFO_CONFIG_1_OFFSET),
+ UART_RX_FIFO_CNT_POS,
+ 6) > 0)
{
- rxdata = BL_RD_BYTE(priv->uartbase + UART_FIFO_RDATA_OFFSET);
+ rxdata = bl602_up_serialin(priv->uartbase, UART_FIFO_RDATA_OFFSET);
}
else
{
@@ -683,18 +692,18 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
if (enable)
{
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
- tmp_val = BL_RD_REG(priv->uartbase, UART_INT_MASK);
+ tmp_val = bl602_up_serialin(priv->uartbase, UART_INT_MASK_OFFSET);
tmp_val &= ~(1 << UART_INT_RX_FIFO_REQ);
tmp_val &= ~(1 << UART_INT_RX_END);
- BL_WR_REG(priv->uartbase, UART_INT_MASK, tmp_val);
+ bl602_up_serialout(priv->uartbase, UART_INT_MASK_OFFSET, tmp_val);
#endif
}
else
{
- tmp_val = BL_RD_REG(priv->uartbase, UART_INT_MASK);
+ tmp_val = bl602_up_serialin(priv->uartbase, UART_INT_MASK_OFFSET);
tmp_val |= (1 << UART_INT_RX_FIFO_REQ);
tmp_val |= (1 << UART_INT_RX_END);
- BL_WR_REG(priv->uartbase, UART_INT_MASK, tmp_val);
+ bl602_up_serialout(priv->uartbase, UART_INT_MASK_OFFSET, tmp_val);
}
leave_critical_section(flags);
@@ -714,8 +723,10 @@ static bool up_rxavailable(struct uart_dev_s *dev)
/* Return true is data is available in the receive data buffer */
- uint32_t rxcnt = BL_GET_REG_BITS_VAL(
- BL_RD_REG(priv->uartbase, UART_FIFO_CONFIG_1), UART_RX_FIFO_CNT);
+ uint32_t rxcnt = bl602_data_getbits(
+ bl602_up_serialin(priv->uartbase, UART_FIFO_CONFIG_1_OFFSET),
+ UART_RX_FIFO_CNT_POS,
+ 6);
return rxcnt != 0;
}
@@ -734,11 +745,13 @@ static void up_send(struct uart_dev_s *dev, int ch)
/* Wait for FIFO */
- while (BL_GET_REG_BITS_VAL(BL_RD_REG(priv->uartbase, UART_FIFO_CONFIG_1),
- UART_TX_FIFO_CNT) == 0)
+ while (bl602_data_getbits(
+ bl602_up_serialin(priv->uartbase, UART_FIFO_CONFIG_1_OFFSET),
+ UART_TX_FIFO_CNT_POS,
+ 6) == 0)
;
- BL_WR_BYTE(priv->uartbase + UART_FIFO_WDATA_OFFSET, ch);
+ bl602_up_serialout(priv->uartbase, UART_FIFO_WDATA_OFFSET, ch);
}
/****************************************************************************
@@ -762,9 +775,9 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
/* Enable the TX interrupt */
- tmp_val = BL_RD_REG(priv->uartbase, UART_INT_MASK);
+ tmp_val = bl602_up_serialin(priv->uartbase, UART_INT_MASK_OFFSET);
tmp_val &= ~(1 << UART_INT_TX_FIFO_REQ);
- BL_WR_REG(priv->uartbase, UART_INT_MASK, tmp_val);
+ bl602_up_serialout(priv->uartbase, UART_INT_MASK_OFFSET, tmp_val);
/* Fake a TX interrupt here by just calling uart_xmitchars() with
* interrupts disabled (note this may recurse).
@@ -777,9 +790,9 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
{
/* Disable the TX interrupt */
- tmp_val = BL_RD_REG(priv->uartbase, UART_INT_MASK);
+ tmp_val = bl602_up_serialin(priv->uartbase, UART_INT_MASK_OFFSET);
tmp_val |= (1 << UART_INT_TX_FIFO_REQ);
- BL_WR_REG(priv->uartbase, UART_INT_MASK, tmp_val);
+ bl602_up_serialout(priv->uartbase, UART_INT_MASK_OFFSET, tmp_val);
}
leave_critical_section(flags);
@@ -799,8 +812,9 @@ static bool up_txready(struct uart_dev_s *dev)
/* Return TRUE if the TX FIFO is not full */
- uint32_t txcnt = BL_GET_REG_BITS_VAL(
- BL_RD_REG(priv->uartbase, UART_FIFO_CONFIG_1), UART_TX_FIFO_CNT);
+ uint32_t txcnt =
+ bl602_up_serialin(priv->uartbase, UART_FIFO_CONFIG_1_OFFSET);
+ txcnt = (txcnt & UART_TX_FIFO_CNT_MSK) >> UART_TX_FIFO_CNT_POS;
return (txcnt != 0);
}
@@ -819,8 +833,10 @@ static bool up_txempty(struct uart_dev_s *dev)
/* Return TRUE if the TX is pending */
- uint32_t txcnt = BL_GET_REG_BITS_VAL(
- BL_RD_REG(priv->uartbase, UART_FIFO_CONFIG_1), UART_TX_FIFO_CNT);
+ uint32_t txcnt = bl602_data_getbits(
+ bl602_up_serialin(priv->uartbase, UART_FIFO_CONFIG_1_OFFSET),
+ UART_TX_FIFO_CNT_POS,
+ 6);
return (txcnt == 0);
}
@@ -983,4 +999,3 @@ int up_putc(int ch)
}
#endif /* USE_SERIALDRIVER */
-
diff --git a/arch/risc-v/src/bl602/bl602_start.c b/arch/risc-v/src/bl602/bl602_start.c
index 2aad898..7698bde 100644
--- a/arch/risc-v/src/bl602/bl602_start.c
+++ b/arch/risc-v/src/bl602/bl602_start.c
@@ -1,6 +1,9 @@
/****************************************************************************
* arch/risc-v/src/bl602/bl602_init.c
*
+ * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
@@ -29,6 +32,7 @@
#include <arch/board/board.h>
+#include "riscv_arch.h"
#include "riscv_internal.h"
#include "chip.h"
@@ -45,18 +49,6 @@
#define showprogress(c)
#endif
-#define PARTITION_BOOT2_RAM_ADDR_ACTIVE (0x42049C00)
-#define PARTITION_HEADER_BOOT2_RAM_ADDR (0x42049C04)
-#define PARTITION_BOOT2_FLASH_HEADER (0x42049d14)
-#define PARTITION_BOOT2_FLASH_CONFIG (0x42049d18)
-#define PARTITION_MAGIC (0x54504642)
-#define PARTITION_FW_PART_NAME "FW"
-#define PARTITION_FW_PART_HEADER_SIZE (0x1000)
-
-/* TODO use header file from project */
-
-#define FW_XIP_ADDRESS (0x23000000)
-
#define BL602_IDLESTACK_SIZE (CONFIG_IDLETHREAD_STACKSIZE & ~3)
/****************************************************************************
@@ -73,7 +65,7 @@
* address.
*/
-static uint8_t idle_stack[BL602_IDLESTACK_SIZE];
+static uint8_t g_idle_stack[BL602_IDLESTACK_SIZE];
/* Dont change the name of varaible, since we refer this
* boot2_partition_table in linker script
@@ -90,7 +82,7 @@ static struct
* Public Data
****************************************************************************/
-uint32_t g_idle_topstack = (uintptr_t)idle_stack + BL602_IDLESTACK_SIZE;
+uint32_t g_idle_topstack = (uintptr_t)g_idle_stack + BL602_IDLESTACK_SIZE;
/****************************************************************************
* Public Functions
@@ -131,9 +123,10 @@ void bfl_main(void)
/* HBN Config AON pad input and SMT */
- tmp_val = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
- tmp_val = BL_SET_REG_BITS_VAL(tmp_val, HBN_REG_AON_PAD_IE_SMT, 1);
- BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmp_val);
+ tmp_val = getreg32(HBN_BASE + HBN_IRQ_MODE_OFFSET);
+ tmp_val = (tmp_val & HBN_REG_AON_PAD_IE_SMT_UMSK) |
+ (1 << HBN_REG_AON_PAD_IE_SMT_POS);
+ putreg32(tmp_val, HBN_BASE + HBN_IRQ_MODE_OFFSET);
#ifdef USE_EARLYSERIALINIT
up_earlyserialinit();
@@ -152,4 +145,3 @@ void bfl_main(void)
while (1)
;
}
-
diff --git a/arch/risc-v/src/bl602/bl602_tim.c b/arch/risc-v/src/bl602/bl602_tim.c
index 53c4812..34ccea4 100644
--- a/arch/risc-v/src/bl602/bl602_tim.c
+++ b/arch/risc-v/src/bl602/bl602_tim.c
@@ -1,6 +1,9 @@
/****************************************************************************
* boards/risc-v/bl602/evb/src/bl602_tim.c
*
+ * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
@@ -23,6 +26,8 @@
****************************************************************************/
#include <hardware/bl602_timer.h>
+#include "riscv_arch.h"
+#include "riscv_internal.h"
/****************************************************************************
* Pre-processor Definitions
@@ -31,11 +36,52 @@
#define TIMER_MAX_MATCH 3
/****************************************************************************
+ * Static Functions
+ ****************************************************************************/
+
+static inline uint32_t bl602_up_tim_regin(uint32_t reg_addr)
+{
+ return getreg32(reg_addr);
+}
+
+static inline void bl602_up_tim_regout(uint32_t reg_addr, uint32_t value)
+{
+ putreg32(value, reg_addr);
+}
+
+/****************************************************************************
+ * Name: bl602_data_setbits
+ ****************************************************************************/
+
+static uint32_t bl602_data_setbits(uint32_t data,
+ uint32_t start,
+ uint32_t len,
+ uint32_t value)
+{
+ return (((data) & ~((~((~0) << (len))) << (start))) |
+ (((value) & ((~((~0) << (len))))) << (start)));
+}
+
+static void bl602_wdt_access(void)
+{
+ uint32_t tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_WFAR_OFFSET);
+
+ bl602_up_tim_regout(
+ TIMER_BASE + TIMER_WFAR_OFFSET,
+ bl602_data_setbits(tmp_val, TIMER_WFAR_POS, 16, 0xbaba));
+
+ tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_WSAR_OFFSET);
+ bl602_up_tim_regout(
+ TIMER_BASE + TIMER_WSAR_OFFSET,
+ bl602_data_setbits(tmp_val, TIMER_WSAR_POS, 16, 0xeb10));
+}
+
+/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
- * Name: timer_getcompvalue
+ * Name: bl602_timer_getcompvalue
*
* Description:
* Get the specified channel and match comparator value.
@@ -49,17 +95,17 @@
*
****************************************************************************/
-uint32_t timer_getcompvalue(timer_chan_t timer_ch, timer_comp_id_t cmp_no)
+uint32_t bl602_timer_getcompvalue(uint32_t timer_ch, uint32_t cmp_no)
{
uint32_t tmp_val;
- tmp_val = BL_RD_WORD(TIMER_BASE + TIMER_TMR2_0_OFFSET +
- 4 * (TIMER_MAX_MATCH * timer_ch + cmp_no));
+ tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_TMR2_0_OFFSET +
+ 4 * (TIMER_MAX_MATCH * timer_ch + cmp_no));
return tmp_val;
}
/****************************************************************************
- * Name: timer_setcompvalue
+ * Name: bl602_timer_setcompvalue
*
* Description:
* TIMER set specified channel and comparator compare value
@@ -74,17 +120,17 @@ uint32_t timer_getcompvalue(timer_chan_t timer_ch, timer_comp_id_t cmp_no)
*
****************************************************************************/
-void timer_setcompvalue(timer_chan_t timer_ch,
- timer_comp_id_t cmp_no,
- uint32_t val)
+void bl602_timer_setcompvalue(uint32_t timer_ch,
+ uint32_t cmp_no,
+ uint32_t val)
{
- BL_WR_WORD(TIMER_BASE + TIMER_TMR2_0_OFFSET +
- 4 * (TIMER_MAX_MATCH * timer_ch + cmp_no),
- val);
+ bl602_up_tim_regout(TIMER_BASE + TIMER_TMR2_0_OFFSET +
+ 4 * (TIMER_MAX_MATCH * timer_ch + cmp_no),
+ val);
}
/****************************************************************************
- * Name: timer_getcountervalue
+ * Name: bl602_timer_getcountervalue
*
* Description:
* TIMER get the specified channel count value.
@@ -97,7 +143,7 @@ void timer_setcompvalue(timer_chan_t timer_ch,
*
****************************************************************************/
-uint32_t timer_getcountervalue(timer_chan_t timer_ch)
+uint32_t bl602_timer_getcountervalue(uint32_t timer_ch)
{
uint32_t tmp_val;
uint32_t tmp_addr;
@@ -107,19 +153,19 @@ uint32_t timer_getcountervalue(timer_chan_t timer_ch)
*/
tmp_addr = TIMER_BASE + TIMER_TCVWR2_OFFSET + 4 * timer_ch;
- BL_WR_WORD(tmp_addr, 1);
+ bl602_up_tim_regout(tmp_addr, 1);
/* Need wait */
- tmp_val = BL_RD_WORD(tmp_addr);
- tmp_val = BL_RD_WORD(tmp_addr);
- tmp_val = BL_RD_WORD(tmp_addr);
+ tmp_val = bl602_up_tim_regin(tmp_addr);
+ tmp_val = bl602_up_tim_regin(tmp_addr);
+ tmp_val = bl602_up_tim_regin(tmp_addr);
return tmp_val;
}
/****************************************************************************
- * Name: timer_getmatchstatus
+ * Name: bl602_timer_getmatchstatus
*
* Description:
* TIMER get specified channel and comparator match status
@@ -133,22 +179,23 @@ uint32_t timer_getcountervalue(timer_chan_t timer_ch)
*
****************************************************************************/
-uint32_t timer_getmatchstatus(timer_chan_t timer_ch, timer_comp_id_t cmp_no)
+uint32_t bl602_timer_getmatchstatus(uint32_t timer_ch, uint32_t cmp_no)
{
uint32_t tmp_val;
uint32_t bit_status = 0;
- tmp_val = BL_RD_WORD(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * timer_ch);
+ tmp_val =
+ bl602_up_tim_regin(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * timer_ch);
switch (cmp_no)
{
case TIMER_COMP_ID_0:
- bit_status = BL_IS_REG_BIT_SET(tmp_val, TIMER_TMSR_0) ? 1 : 0;
+ bit_status = (((tmp_val) & (1 << (TIMER_TMSR_0_POS))) ? 1 : 0);
break;
case TIMER_COMP_ID_1:
- bit_status = BL_IS_REG_BIT_SET(tmp_val, TIMER_TMSR_1) ? 1 : 0;
+ bit_status = (((tmp_val) & (1 << (TIMER_TMSR_1_POS))) ? 1 : 0);
break;
case TIMER_COMP_ID_2:
- bit_status = BL_IS_REG_BIT_SET(tmp_val, TIMER_TMSR_2) ? 1 : 0;
+ bit_status = (((tmp_val) & (1 << (TIMER_TMSR_2_POS))) ? 1 : 0);
break;
default:
break;
@@ -158,7 +205,7 @@ uint32_t timer_getmatchstatus(timer_chan_t timer_ch, timer_comp_id_t cmp_no)
}
/****************************************************************************
- * Name: timer_getpreloadvalue
+ * Name: bl602_timer_getpreloadvalue
*
* Description:
* TIMER get specified channel preload value
@@ -171,16 +218,17 @@ uint32_t timer_getmatchstatus(timer_chan_t timer_ch, timer_comp_id_t cmp_no)
*
****************************************************************************/
-uint32_t timer_getpreloadvalue(timer_chan_t timer_ch)
+uint32_t bl602_timer_getpreloadvalue(uint32_t timer_ch)
{
uint32_t tmp_val;
- tmp_val = BL_RD_WORD(TIMER_BASE + TIMER_TPLVR2_OFFSET + 4 * timer_ch);
+ tmp_val =
+ bl602_up_tim_regin(TIMER_BASE + TIMER_TPLVR2_OFFSET + 4 * timer_ch);
return tmp_val;
}
/****************************************************************************
- * Name: timer_setpreloadvalue
+ * Name: bl602_timer_setpreloadvalue
*
* Description:
* TIMER set preload register low 32bits value
@@ -194,13 +242,13 @@ uint32_t timer_getpreloadvalue(timer_chan_t timer_ch)
*
****************************************************************************/
-void timer_setpreloadvalue(timer_chan_t timer_ch, uint32_t val)
+void bl602_timer_setpreloadvalue(uint32_t timer_ch, uint32_t val)
{
- BL_WR_WORD(TIMER_BASE + TIMER_TPLVR2_OFFSET + 4 * timer_ch, val);
+ bl602_up_tim_regout(TIMER_BASE + TIMER_TPLVR2_OFFSET + 4 * timer_ch, val);
}
/****************************************************************************
- * Name: timer_setpreloadtrigsrc
+ * Name: bl602_timer_setpreloadtrigsrc
*
* Description:
* TIMER set preload trigger source,COMP0,COMP1,COMP2 or None
@@ -214,14 +262,14 @@ void timer_setpreloadvalue(timer_chan_t timer_ch, uint32_t val)
*
****************************************************************************/
-void timer_setpreloadtrigsrc(timer_chan_t timer_ch,
- timer_preload_trig_t pl_src)
+void bl602_timer_setpreloadtrigsrc(uint32_t timer_ch, uint32_t pl_src)
{
- BL_WR_WORD(TIMER_BASE + TIMER_TPLCR2_OFFSET + 4 * timer_ch, pl_src);
+ bl602_up_tim_regout(TIMER_BASE + TIMER_TPLCR2_OFFSET + 4 * timer_ch,
+ pl_src);
}
/****************************************************************************
- * Name: timer_setcountmode
+ * Name: bl602_timer_setcountmode
*
* Description:
* TIMER set count mode:preload or free run
@@ -236,19 +284,19 @@ void timer_setpreloadtrigsrc(timer_chan_t timer_ch,
*
****************************************************************************/
-void timer_setcountmode(timer_chan_t timer_ch, timer_countmode_t count_mode)
+void bl602_timer_setcountmode(uint32_t timer_ch, uint32_t count_mode)
{
uint32_t tmpval;
- tmpval = BL_RD_WORD(TIMER_BASE + TIMER_TCMR_OFFSET);
+ tmpval = bl602_up_tim_regin(TIMER_BASE + TIMER_TCMR_OFFSET);
tmpval &= (~(1 << (timer_ch + 1)));
tmpval |= (count_mode << (timer_ch + 1));
- BL_WR_WORD(TIMER_BASE + TIMER_TCMR_OFFSET, tmpval);
+ bl602_up_tim_regout(TIMER_BASE + TIMER_TCMR_OFFSET, tmpval);
}
/****************************************************************************
- * Name: timer_clearintstatus
+ * Name: bl602_timer_clearintstatus
*
* Description:
* TIMER clear interrupt status
@@ -262,21 +310,21 @@ void timer_setcountmode(timer_chan_t timer_ch, timer_countmode_t count_mode)
*
****************************************************************************/
-void timer_clearintstatus(timer_chan_t timer_ch, timer_comp_id_t cmp_no)
+void bl602_timer_clearintstatus(uint32_t timer_ch, uint32_t cmp_no)
{
uint32_t tmp_addr;
uint32_t tmp_val;
tmp_addr = TIMER_BASE + TIMER_TICR2_OFFSET + 4 * timer_ch;
- tmp_val = BL_RD_WORD(tmp_addr);
+ tmp_val = bl602_up_tim_regin(tmp_addr);
tmp_val |= (1 << cmp_no);
- BL_WR_WORD(tmp_addr, tmp_val);
+ bl602_up_tim_regout(tmp_addr, tmp_val);
}
/****************************************************************************
- * Name: timer_init
+ * Name: bl602_timer_init
*
* Description:
* TIMER initialization function.
@@ -289,65 +337,67 @@ void timer_clearintstatus(timer_chan_t timer_ch, timer_comp_id_t cmp_no)
*
****************************************************************************/
-void timer_init(timer_cfg_t *timer_cfg)
+void bl602_timer_init(timer_cfg_t *timer_cfg)
{
- timer_chan_t timer_ch = timer_cfg->timer_ch;
- uint32_t tmp_val;
+ uint32_t timer_ch = timer_cfg->timer_ch;
+ uint32_t tmp_val;
/* Configure timer clock source */
- tmp_val = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
+ tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_TCCR_OFFSET);
if (timer_ch == TIMER_CH0)
{
- tmp_val = BL_SET_REG_BITS_VAL(tmp_val, TIMER_CS_1, timer_cfg->clk_src);
+ tmp_val =
+ bl602_data_setbits(tmp_val, TIMER_CS_1_POS, 2, timer_cfg->clk_src);
}
else
{
- tmp_val = BL_SET_REG_BITS_VAL(tmp_val, TIMER_CS_2, timer_cfg->clk_src);
+ tmp_val =
+ bl602_data_setbits(tmp_val, TIMER_CS_2_POS, 2, timer_cfg->clk_src);
}
- BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp_val);
+ bl602_up_tim_regout(TIMER_BASE + TIMER_TCCR_OFFSET, tmp_val);
/* Configure timer clock division */
- tmp_val = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
+ tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_TCDR_OFFSET);
if (timer_ch == TIMER_CH0)
{
- tmp_val =
- BL_SET_REG_BITS_VAL(tmp_val, TIMER_TCDR2, timer_cfg->clock_division);
+ tmp_val = bl602_data_setbits(
+ tmp_val, TIMER_TCDR2_POS, 8, timer_cfg->clock_division);
}
else
{
- tmp_val =
- BL_SET_REG_BITS_VAL(tmp_val, TIMER_TCDR3, timer_cfg->clock_division);
+ tmp_val = bl602_data_setbits(
+ tmp_val, TIMER_TCDR3_POS, 8, timer_cfg->clock_division);
}
- BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp_val);
+ bl602_up_tim_regout(TIMER_BASE + TIMER_TCDR_OFFSET, tmp_val);
/* Configure timer count mode: preload or free run */
- timer_setcountmode(timer_ch, timer_cfg->count_mode);
+ bl602_timer_setcountmode(timer_ch, timer_cfg->count_mode);
/* Configure timer preload trigger src */
- timer_setpreloadtrigsrc(timer_ch, timer_cfg->pl_trig_src);
+ bl602_timer_setpreloadtrigsrc(timer_ch, timer_cfg->pl_trig_src);
if (timer_cfg->count_mode == TIMER_COUNT_PRELOAD)
{
/* Configure timer preload value */
- timer_setpreloadvalue(timer_ch, timer_cfg->pre_load_val);
+ bl602_timer_setpreloadvalue(timer_ch, timer_cfg->pre_load_val);
}
/* Configure match compare values */
- timer_setcompvalue(timer_ch, TIMER_COMP_ID_0, timer_cfg->match_val0);
- timer_setcompvalue(timer_ch, TIMER_COMP_ID_1, timer_cfg->match_val1);
- timer_setcompvalue(timer_ch, TIMER_COMP_ID_2, timer_cfg->match_val2);
+ bl602_timer_setcompvalue(timer_ch, TIMER_COMP_ID_0, timer_cfg->match_val0);
+ bl602_timer_setcompvalue(timer_ch, TIMER_COMP_ID_1, timer_cfg->match_val1);
+ bl602_timer_setcompvalue(timer_ch, TIMER_COMP_ID_2, timer_cfg->match_val2);
}
/****************************************************************************
- * Name: timer_enable
+ * Name: bl602_timer_enable
*
* Description:
* TIMER enable one channel function.
@@ -360,18 +410,18 @@ void timer_init(timer_cfg_t *timer_cfg)
*
****************************************************************************/
-void timer_enable(timer_chan_t timer_ch)
+void bl602_timer_enable(uint32_t timer_ch)
{
uint32_t tmp_val;
- tmp_val = BL_RD_REG(TIMER_BASE, TIMER_TCER);
+ tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_TCER_OFFSET);
tmp_val |= (1 << (timer_ch + 1));
- BL_WR_REG(TIMER_BASE, TIMER_TCER, tmp_val);
+ bl602_up_tim_regout(TIMER_BASE + TIMER_TCER_OFFSET, tmp_val);
}
/****************************************************************************
- * Name: timer_disable
+ * Name: bl602_timer_disable
*
* Description:
* TIMER disable one channel function.
@@ -384,18 +434,18 @@ void timer_enable(timer_chan_t timer_ch)
*
****************************************************************************/
-void timer_disable(timer_chan_t timer_ch)
+void bl602_timer_disable(uint32_t timer_ch)
{
uint32_t tmp_val;
- tmp_val = BL_RD_REG(TIMER_BASE, TIMER_TCER);
+ tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_TCER_OFFSET);
tmp_val &= (~(1 << (timer_ch + 1)));
- BL_WR_REG(TIMER_BASE, TIMER_TCER, tmp_val);
+ bl602_up_tim_regout(TIMER_BASE + TIMER_TCER_OFFSET, tmp_val);
}
/****************************************************************************
- * Name: timer_intmask
+ * Name: bl602_timer_intmask
*
* Description:
* TIMER mask or unmask certain or all interrupt.
@@ -411,15 +461,15 @@ void timer_disable(timer_chan_t timer_ch)
*
****************************************************************************/
-void timer_intmask(timer_chan_t timer_ch,
- timer_int_t int_type,
- uint32_t int_mask)
+void bl602_timer_intmask(uint32_t timer_ch,
+ uint32_t int_type,
+ uint32_t int_mask)
{
uint32_t tmp_addr;
uint32_t tmp_val;
tmp_addr = TIMER_BASE + TIMER_TIER2_OFFSET + 4 * timer_ch;
- tmp_val = BL_RD_WORD(tmp_addr);
+ tmp_val = bl602_up_tim_regin(tmp_addr);
switch (int_type)
{
@@ -428,13 +478,13 @@ void timer_intmask(timer_chan_t timer_ch,
{
/* Enable this interrupt */
- BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TIER_0));
+ bl602_up_tim_regout(tmp_addr, tmp_val |= 1 << TIMER_TIER_0_POS);
}
else
{
/* Disable this interrupt */
- BL_WR_WORD(tmp_addr, BL_CLR_REG_BIT(tmp_val, TIMER_TIER_0));
+ bl602_up_tim_regout(tmp_addr, tmp_val &= ~(1 << TIMER_TIER_0_POS));
}
break;
@@ -444,13 +494,13 @@ void timer_intmask(timer_chan_t timer_ch,
{
/* Enable this interrupt */
- BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TIER_1));
+ bl602_up_tim_regout(tmp_addr, tmp_val |= 1 << TIMER_TIER_1_POS);
}
else
{
/* Disable this interrupt */
- BL_WR_WORD(tmp_addr, BL_CLR_REG_BIT(tmp_val, TIMER_TIER_1));
+ bl602_up_tim_regout(tmp_addr, tmp_val &= ~(1 << TIMER_TIER_1_POS));
}
break;
@@ -460,13 +510,13 @@ void timer_intmask(timer_chan_t timer_ch,
{
/* Enable this interrupt */
- BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TIER_2));
+ bl602_up_tim_regout(tmp_addr, tmp_val |= 1 << TIMER_TIER_2_POS);
}
else
{
/* Disable this interrupt */
- BL_WR_WORD(tmp_addr, BL_CLR_REG_BIT(tmp_val, TIMER_TIER_2));
+ bl602_up_tim_regout(tmp_addr, tmp_val &= ~(1 << TIMER_TIER_2_POS));
}
break;
@@ -476,17 +526,17 @@ void timer_intmask(timer_chan_t timer_ch,
{
/* Enable this interrupt */
- BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TIER_0));
- BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TIER_1));
- BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TIER_2));
+ bl602_up_tim_regout(tmp_addr, tmp_val |= 1 << TIMER_TIER_0_POS);
+ bl602_up_tim_regout(tmp_addr, tmp_val |= 1 << TIMER_TIER_1_POS);
+ bl602_up_tim_regout(tmp_addr, tmp_val |= 1 << TIMER_TIER_2_POS);
}
else
{
/* Disable this interrupt */
- BL_WR_WORD(tmp_addr, BL_CLR_REG_BIT(tmp_val, TIMER_TIER_0));
- BL_WR_WORD(tmp_addr, BL_CLR_REG_BIT(tmp_val, TIMER_TIER_1));
- BL_WR_WORD(tmp_addr, BL_CLR_REG_BIT(tmp_val, TIMER_TIER_2));
+ bl602_up_tim_regout(tmp_addr, tmp_val &= ~(1 << TIMER_TIER_0_POS));
+ bl602_up_tim_regout(tmp_addr, tmp_val &= ~(1 << TIMER_TIER_1_POS));
+ bl602_up_tim_regout(tmp_addr, tmp_val &= ~(1 << TIMER_TIER_2_POS));
}
break;
@@ -497,7 +547,7 @@ void timer_intmask(timer_chan_t timer_ch,
}
/****************************************************************************
- * Name: wdt_set_clock
+ * Name: bl602_wdt_set_clock
*
* Description:
* TIMER set watchdog clock source and clock division.
@@ -511,25 +561,25 @@ void timer_intmask(timer_chan_t timer_ch,
*
****************************************************************************/
-void wdt_set_clock(timer_clksrc_t clk_src, uint8_t div)
+void bl602_wdt_set_clock(uint32_t clk_src, uint8_t div)
{
uint32_t tmp_val;
/* Configure watchdog timer clock source */
- tmp_val = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
- tmp_val = BL_SET_REG_BITS_VAL(tmp_val, TIMER_CS_WDT, clk_src);
- BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp_val);
+ tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_TCCR_OFFSET);
+ tmp_val = bl602_data_setbits(tmp_val, TIMER_CS_WDT_POS, 2, clk_src);
+ bl602_up_tim_regout(TIMER_BASE + TIMER_TCCR_OFFSET, tmp_val);
/* Configure watchdog timer clock divison */
- tmp_val = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
- tmp_val = BL_SET_REG_BITS_VAL(tmp_val, TIMER_WCDR, div);
- BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp_val);
+ tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_TCDR_OFFSET);
+ tmp_val = bl602_data_setbits(tmp_val, TIMER_WCDR_POS, 8, div);
+ bl602_up_tim_regout(TIMER_BASE + TIMER_TCDR_OFFSET, tmp_val);
}
/****************************************************************************
- * Name: wdt_getmatchvalue
+ * Name: bl602_wdt_getmatchvalue
*
* Description:
* TIMER get watchdog match compare value.
@@ -542,21 +592,21 @@ void wdt_set_clock(timer_clksrc_t clk_src, uint8_t div)
*
****************************************************************************/
-uint32_t wdt_getmatchvalue(void)
+uint32_t bl602_wdt_getmatchvalue(void)
{
uint32_t tmp_val;
- WDT_ENABLE_ACCESS();
+ bl602_wdt_access();
/* Get watchdog timer match register value */
- tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WMR);
+ tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_WMR_OFFSET);
return tmp_val;
}
/****************************************************************************
- * Name: wdt_setcompvalue
+ * Name: bl602_wdt_setcompvalue
*
* Description:
* TIMER set watchdog match compare value.
@@ -569,17 +619,17 @@ uint32_t wdt_getmatchvalue(void)
*
****************************************************************************/
-void wdt_setcompvalue(uint16_t val)
+void bl602_wdt_setcompvalue(uint16_t val)
{
- WDT_ENABLE_ACCESS();
+ bl602_wdt_access();
/* Set watchdog timer match register value */
- BL_WR_REG(TIMER_BASE, TIMER_WMR, val);
+ bl602_up_tim_regout(TIMER_BASE + TIMER_WMR_OFFSET, val);
}
/****************************************************************************
- * Name: wdt_getcountervalue
+ * Name: bl602_wdt_getcountervalue
*
* Description:
* TIMER get watchdog count register value.
@@ -592,21 +642,21 @@ void wdt_setcompvalue(uint16_t val)
*
****************************************************************************/
-uint16_t wdt_getcountervalue(void)
+uint16_t bl602_wdt_getcountervalue(void)
{
uint32_t tmp_val;
- WDT_ENABLE_ACCESS();
+ bl602_wdt_access();
/* Get watchdog timer count register value */
- tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WVR);
+ tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_WVR_OFFSET);
return tmp_val;
}
/****************************************************************************
- * Name: wdt_resetcountervalue
+ * Name: bl602_wdt_resetcountervalue
*
* Description:
* TIMER reset watchdog count register value.
@@ -619,23 +669,24 @@ uint16_t wdt_getcountervalue(void)
*
****************************************************************************/
-void wdt_resetcountervalue(void)
+void bl602_wdt_resetcountervalue(void)
{
uint32_t tmp_val;
/* Reset watchdog timer count register value */
- WDT_ENABLE_ACCESS();
+ bl602_wdt_access();
- tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WCR);
+ tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_WCR_OFFSET);
/* Set watchdog counter reset register bit0 to 1 */
- BL_WR_REG(TIMER_BASE, TIMER_WCR, BL_SET_REG_BIT(tmp_val, TIMER_WCR));
+ bl602_up_tim_regout(TIMER_BASE + TIMER_WCR_OFFSET,
+ tmp_val |= 1 << TIMER_WCR_POS);
}
/****************************************************************************
- * Name: wdt_getresetstatus
+ * Name: bl602_wdt_getresetstatus
*
* Description:
* TIMER get watchdog reset status.
@@ -648,23 +699,23 @@ void wdt_resetcountervalue(void)
*
****************************************************************************/
-uint32_t wdt_getresetstatus(void)
+uint32_t bl602_wdt_getresetstatus(void)
{
uint32_t tmp_val;
uint32_t ret;
- WDT_ENABLE_ACCESS();
+ bl602_wdt_access();
/* Get watchdog status register */
- tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WSR);
+ tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_WSR_OFFSET);
- ret = (BL_IS_REG_BIT_SET(tmp_val, TIMER_WTS)) ? 1 : 0;
+ ret = (((tmp_val) & (1 << (TIMER_WTS_POS))) ? 1 : 0);
return ret;
}
/****************************************************************************
- * Name: wdt_clearresetstatus
+ * Name: bl602_wdt_clearresetstatus
*
* Description:
* TIMER clear watchdog reset status.
@@ -677,21 +728,22 @@ uint32_t wdt_getresetstatus(void)
*
****************************************************************************/
-void wdt_clearresetstatus(void)
+void bl602_wdt_clearresetstatus(void)
{
uint32_t tmp_val;
- WDT_ENABLE_ACCESS();
+ bl602_wdt_access();
- tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WSR);
+ tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_WSR_OFFSET);
/* Set watchdog status register */
- BL_WR_REG(TIMER_BASE, TIMER_WSR, BL_CLR_REG_BIT(tmp_val, TIMER_WTS));
+ bl602_up_tim_regout(TIMER_BASE + TIMER_WSR_OFFSET,
+ tmp_val &= ~(1 << TIMER_WTS_POS));
}
/****************************************************************************
- * Name: wdt_enable
+ * Name: bl602_wdt_enable
*
* Description:
* TIMER enable watchdog function.
@@ -704,19 +756,20 @@ void wdt_clearresetstatus(void)
*
****************************************************************************/
-void wdt_enable(void)
+void bl602_wdt_enable(void)
{
uint32_t tmp_val;
- WDT_ENABLE_ACCESS();
+ bl602_wdt_access();
- tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WMER);
+ tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_WMER_OFFSET);
- BL_WR_REG(TIMER_BASE, TIMER_WMER, BL_SET_REG_BIT(tmp_val, TIMER_WE));
+ bl602_up_tim_regout(TIMER_BASE + TIMER_WMER_OFFSET,
+ tmp_val |= 1 << TIMER_WE_POS);
}
/****************************************************************************
- * Name: wdt_disable
+ * Name: bl602_wdt_disable
*
* Description:
* Watchdog timer disable function.
@@ -729,19 +782,20 @@ void wdt_enable(void)
*
****************************************************************************/
-void wdt_disable(void)
+void bl602_wdt_disable(void)
{
uint32_t tmp_val;
- WDT_ENABLE_ACCESS();
+ bl602_wdt_access();
- tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WMER);
+ tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_WMER_OFFSET);
- BL_WR_REG(TIMER_BASE, TIMER_WMER, BL_CLR_REG_BIT(tmp_val, TIMER_WE));
+ bl602_up_tim_regout(TIMER_BASE + TIMER_WMER_OFFSET,
+ tmp_val &= ~(1 << TIMER_WE_POS));
}
/****************************************************************************
- * Name: wdt_intmask
+ * Name: bl602_wdt_intmask
*
* Description:
* Watchdog timer mask or unmask certain or all interrupt.
@@ -756,17 +810,17 @@ void wdt_disable(void)
*
****************************************************************************/
-void wdt_intmask(wdt_int_t int_type, uint32_t int_mask)
+void bl602_wdt_intmask(uint32_t int_type, uint32_t int_mask)
{
uint32_t tmp_val;
- WDT_ENABLE_ACCESS();
+ bl602_wdt_access();
/* Deal with watchdog match/interrupt enable register,WRIE:watchdog
* reset/interrupt enable
*/
- tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WMER);
+ tmp_val = bl602_up_tim_regin(TIMER_BASE + TIMER_WMER_OFFSET);
switch (int_type)
{
@@ -779,8 +833,8 @@ void wdt_intmask(wdt_int_t int_type, uint32_t int_mask)
* not generated
*/
- BL_WR_REG(
- TIMER_BASE, TIMER_WMER, BL_CLR_REG_BIT(tmp_val, TIMER_WRIE));
+ bl602_up_tim_regout(TIMER_BASE + TIMER_WMER_OFFSET,
+ tmp_val &= ~(1 << TIMER_WRIE_POS));
}
else
{
@@ -790,8 +844,8 @@ void wdt_intmask(wdt_int_t int_type, uint32_t int_mask)
* not generated
*/
- BL_WR_REG(
- TIMER_BASE, TIMER_WMER, BL_SET_REG_BIT(tmp_val, TIMER_WRIE));
+ bl602_up_tim_regout(TIMER_BASE + TIMER_WMER_OFFSET,
+ tmp_val |= 1 << TIMER_WRIE_POS);
}
break;
@@ -799,4 +853,3 @@ void wdt_intmask(wdt_int_t int_type, uint32_t int_mask)
break;
}
}
-
diff --git a/arch/risc-v/src/bl602/bl602_tim_lowerhalf.c b/arch/risc-v/src/bl602/bl602_tim_lowerhalf.c
index 390c666..ff01555 100644
--- a/arch/risc-v/src/bl602/bl602_tim_lowerhalf.c
+++ b/arch/risc-v/src/bl602/bl602_tim_lowerhalf.c
@@ -1,5 +1,8 @@
/****************************************************************************
- * boards/risc-v/bl602/evb/src/bl602_lowerhalf.c
+ * arch/risc-v/src/bl602/bl602_tim_lowerhalf.c
+ *
+ * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -35,6 +38,7 @@
#include <nuttx/timers/timer.h>
#include <arch/board/board.h>
+#include "riscv_arch.h"
#include <hardware/bl602_glb.h>
#include <hardware/bl602_timer.h>
@@ -50,7 +54,7 @@
* Private Types
****************************************************************************/
-struct bl602_lowerhalf_s
+struct bl602_tim_lowerhalf_s
{
FAR const struct timer_ops_s *ops; /* Lower half operations */
@@ -69,15 +73,15 @@ static int bl602_timer_handler(int irq, void *context, void *arg);
/* "Lower half" driver methods */
-static int bl602_start(FAR struct timer_lowerhalf_s *lower);
-static int bl602_stop(FAR struct timer_lowerhalf_s *lower);
-static int bl602_getstatus(FAR struct timer_lowerhalf_s *lower,
- FAR struct timer_status_s * status);
-static int bl602_settimeout(FAR struct timer_lowerhalf_s *lower,
- uint32_t timeout);
-static void bl602_setcallback(FAR struct timer_lowerhalf_s *lower,
- tccb_t callback,
- FAR void * arg);
+static int bl602_tim_start(FAR struct timer_lowerhalf_s *lower);
+static int bl602_tim_stop(FAR struct timer_lowerhalf_s *lower);
+static int bl602_tim_getstatus(FAR struct timer_lowerhalf_s *lower,
+ FAR struct timer_status_s * status);
+static int bl602_tim_settimeout(FAR struct timer_lowerhalf_s *lower,
+ uint32_t timeout);
+static void bl602_tim_setcallback(FAR struct timer_lowerhalf_s *lower,
+ tccb_t callback,
+ FAR void * arg);
/****************************************************************************
* Private Data
@@ -87,16 +91,16 @@ static void bl602_setcallback(FAR struct timer_lowerhalf_s *lower,
static const struct timer_ops_s g_timer_ops =
{
- .start = bl602_start,
- .stop = bl602_stop,
- .getstatus = bl602_getstatus,
- .settimeout = bl602_settimeout,
- .setcallback = bl602_setcallback,
+ .start = bl602_tim_start,
+ .stop = bl602_tim_stop,
+ .getstatus = bl602_tim_getstatus,
+ .settimeout = bl602_tim_settimeout,
+ .setcallback = bl602_tim_setcallback,
.ioctl = NULL,
};
#ifdef CONFIG_BL602_TIMER0
-static struct bl602_lowerhalf_s g_tim1_lowerhalf =
+static struct bl602_tim_lowerhalf_s g_tim1_lowerhalf =
{
.ops = &g_timer_ops,
.irq = BL602_IRQ_TIMER_CH0,
@@ -105,7 +109,7 @@ static struct bl602_lowerhalf_s g_tim1_lowerhalf =
#endif
#ifdef CONFIG_BL602_TIMER1
-static struct bl602_lowerhalf_s g_tim2_lowerhalf =
+static struct bl602_tim_lowerhalf_s g_tim2_lowerhalf =
{
.ops = &g_timer_ops,
.irq = BL602_IRQ_TIMER_CH1,
@@ -131,8 +135,9 @@ static struct bl602_lowerhalf_s g_tim2_lowerhalf =
static int bl602_timer_handler(int irq, void *context, void *arg)
{
- FAR struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)arg;
- uint32_t next_interval_us = 0;
+ FAR struct bl602_tim_lowerhalf_s *priv =
+ (FAR struct bl602_tim_lowerhalf_s *)arg;
+ uint32_t next_interval_us = 0;
/* Clear Interrupt Bits */
@@ -140,54 +145,54 @@ static int bl602_timer_handler(int irq, void *context, void *arg)
uint32_t tmp_val;
uint32_t tmp_addr;
- int_id = BL_RD_WORD(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * priv->tim);
+ int_id = getreg32(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * priv->tim);
tmp_addr = TIMER_BASE + TIMER_TICR2_OFFSET + 4 * priv->tim;
- tmp_val = BL_RD_WORD(tmp_addr);
+ tmp_val = getreg32(tmp_addr);
/* Comparator 0 match interrupt */
- if (BL_IS_REG_BIT_SET(int_id, TIMER_TMSR_0))
+ if (((int_id) & (1 << (TIMER_TMSR_0_POS))) != 0)
{
- BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TCLR_0));
+ putreg32(tmp_val | (1 << TIMER_TCLR_0_POS), tmp_addr);
if (priv->callback(&next_interval_us, priv->arg))
{
if (next_interval_us > 0)
{
/* Set a value to the alarm */
- timer_disable(priv->tim);
- timer_setcompvalue(
+ bl602_timer_disable(priv->tim);
+ bl602_timer_setcompvalue(
priv->tim, TIMER_COMP_ID_0, next_interval_us);
- timer_setpreloadvalue(priv->tim, 0);
- timer_enable(priv->tim);
+ bl602_timer_setpreloadvalue(priv->tim, 0);
+ bl602_timer_enable(priv->tim);
}
}
else
{
- timer_disable(priv->tim);
- timer_setpreloadvalue(priv->tim, 0);
+ bl602_timer_disable(priv->tim);
+ bl602_timer_setpreloadvalue(priv->tim, 0);
}
}
/* Comparator 1 match interrupt */
- if (BL_IS_REG_BIT_SET(int_id, TIMER_TMSR_1))
+ if (((int_id) & (1 << (TIMER_TMSR_1_POS))) != 0)
{
- BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TCLR_1));
+ putreg32(tmp_val | (1 << TIMER_TCLR_1_POS), tmp_addr);
}
/* Comparator 2 match interrupt */
- if (BL_IS_REG_BIT_SET(int_id, TIMER_TMSR_2))
+ if (((int_id) & (1 << (TIMER_TMSR_2_POS))) != 0)
{
- BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TCLR_2));
+ putreg32(tmp_val | (1 << TIMER_TCLR_2_POS), tmp_addr);
}
return OK;
}
/****************************************************************************
- * Name: bl602_start
+ * Name: bl602_tim_start
*
* Description:
* Start the timer, resetting the time to the current timeout,
@@ -201,9 +206,10 @@ static int bl602_timer_handler(int irq, void *context, void *arg)
*
****************************************************************************/
-static int bl602_start(FAR struct timer_lowerhalf_s *lower)
+static int bl602_tim_start(FAR struct timer_lowerhalf_s *lower)
{
- FAR struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)lower;
+ FAR struct bl602_tim_lowerhalf_s *priv =
+ (FAR struct bl602_tim_lowerhalf_s *)lower;
if (!priv->started)
{
@@ -212,11 +218,11 @@ static int bl602_start(FAR struct timer_lowerhalf_s *lower)
return -EPERM;
}
- timer_setpreloadvalue(priv->tim, 0);
+ bl602_timer_setpreloadvalue(priv->tim, 0);
irq_attach(priv->irq, bl602_timer_handler, (void *)priv);
up_enable_irq(priv->irq);
- timer_intmask(priv->tim, TIMER_INT_COMP_0, 0);
- timer_enable(priv->tim);
+ bl602_timer_intmask(priv->tim, TIMER_INT_COMP_0, 0);
+ bl602_timer_enable(priv->tim);
priv->started = true;
return OK;
}
@@ -227,7 +233,7 @@ static int bl602_start(FAR struct timer_lowerhalf_s *lower)
}
/****************************************************************************
- * Name: bl602_stop
+ * Name: bl602_tim_stop
*
* Description:
* Stop the timer
@@ -241,18 +247,19 @@ static int bl602_start(FAR struct timer_lowerhalf_s *lower)
*
****************************************************************************/
-static int bl602_stop(FAR struct timer_lowerhalf_s *lower)
+static int bl602_tim_stop(FAR struct timer_lowerhalf_s *lower)
{
- FAR struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)lower;
+ FAR struct bl602_tim_lowerhalf_s *priv =
+ (FAR struct bl602_tim_lowerhalf_s *)lower;
/* timer disable */
if (priv->started)
{
- timer_disable(priv->tim);
+ bl602_timer_disable(priv->tim);
priv->started = false;
up_disable_irq(priv->irq);
- timer_intmask(priv->tim, TIMER_INT_COMP_0, 1);
+ bl602_timer_intmask(priv->tim, TIMER_INT_COMP_0, 1);
return OK;
}
@@ -262,7 +269,7 @@ static int bl602_stop(FAR struct timer_lowerhalf_s *lower)
}
/****************************************************************************
- * Name: bl602_getstatus
+ * Name: bl602_tim_getstatus
*
* Description:
* get timer status
@@ -277,14 +284,15 @@ static int bl602_stop(FAR struct timer_lowerhalf_s *lower)
*
****************************************************************************/
-static int bl602_getstatus(FAR struct timer_lowerhalf_s *lower,
- FAR struct timer_status_s * status)
+static int bl602_tim_getstatus(FAR struct timer_lowerhalf_s *lower,
+ FAR struct timer_status_s * status)
{
- FAR struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)lower;
- uint32_t current_count;
+ FAR struct bl602_tim_lowerhalf_s *priv =
+ (FAR struct bl602_tim_lowerhalf_s *)lower;
+ uint32_t current_count;
status->timeout = timer_getcompvalue(priv->tim, TIMER_COMP_ID_0);
- current_count = timer_getcountervalue(priv->tim);
+ current_count = bl602_timer_getcountervalue(priv->tim);
if (current_count < status->timeout)
{
status->timeleft = status->timeout - current_count;
@@ -298,7 +306,7 @@ static int bl602_getstatus(FAR struct timer_lowerhalf_s *lower,
}
/****************************************************************************
- * Name: bl602_settimeout
+ * Name: bl602_tim_settimeout
*
* Description:
* Set a new timeout value (and reset the timer)
@@ -313,18 +321,19 @@ static int bl602_getstatus(FAR struct timer_lowerhalf_s *lower,
*
****************************************************************************/
-static int bl602_settimeout(FAR struct timer_lowerhalf_s *lower,
- uint32_t timeout)
+static int bl602_tim_settimeout(FAR struct timer_lowerhalf_s *lower,
+ uint32_t timeout)
{
- FAR struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)lower;
+ FAR struct bl602_tim_lowerhalf_s *priv =
+ (FAR struct bl602_tim_lowerhalf_s *)lower;
- timer_setcompvalue(priv->tim, TIMER_COMP_ID_0, timeout);
+ bl602_timer_setcompvalue(priv->tim, TIMER_COMP_ID_0, timeout);
return OK;
}
/****************************************************************************
- * Name: bl602_setcallback
+ * Name: bl602_tim_setcallback
*
* Description:
* Call this user provided timeout handler.
@@ -342,12 +351,13 @@ static int bl602_settimeout(FAR struct timer_lowerhalf_s *lower,
*
****************************************************************************/
-static void bl602_setcallback(FAR struct timer_lowerhalf_s *lower,
- tccb_t callback,
- FAR void * arg)
+static void bl602_tim_setcallback(FAR struct timer_lowerhalf_s *lower,
+ tccb_t callback,
+ FAR void * arg)
{
- struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)lower;
- irqstate_t flags = enter_critical_section();
+ struct bl602_tim_lowerhalf_s *priv =
+ (FAR struct bl602_tim_lowerhalf_s *)lower;
+ irqstate_t flags = enter_critical_section();
/* Save the new callback */
@@ -381,8 +391,8 @@ static void bl602_setcallback(FAR struct timer_lowerhalf_s *lower,
int bl602_timer_initialize(FAR const char *devpath, int timer)
{
- FAR struct bl602_lowerhalf_s *lower;
- timer_cfg_t timstr;
+ FAR struct bl602_tim_lowerhalf_s *lower;
+ timer_cfg_t timstr;
switch (timer)
{
@@ -413,15 +423,15 @@ int bl602_timer_initialize(FAR const char *devpath, int timer)
timstr.match_val2 = TIMER_MAX_VALUE; /* Timer match 2 value 0 */
timstr.pre_load_val = TIMER_MAX_VALUE; /* Timer preload value */
- glb_ahb_slave1_reset(BL_AHB_SLAVE1_TMR);
+ bl602_glb_ahb_slave1_reset(BL_AHB_SLAVE1_TMR);
- timer_intmask(lower->tim, TIMER_INT_ALL, 1);
+ bl602_timer_intmask(lower->tim, TIMER_INT_ALL, 1);
/* timer disable */
- timer_disable(lower->tim);
+ bl602_timer_disable(lower->tim);
- timer_init(&timstr);
+ bl602_timer_init(&timstr);
/* Initialize the elements of lower half state structure */
@@ -448,4 +458,3 @@ int bl602_timer_initialize(FAR const char *devpath, int timer)
return OK;
}
-
diff --git a/arch/risc-v/src/bl602/bl602_tim_lowerhalf.h b/arch/risc-v/src/bl602/bl602_tim_lowerhalf.h
index 9b9eaea..f330453 100644
--- a/arch/risc-v/src/bl602/bl602_tim_lowerhalf.h
+++ b/arch/risc-v/src/bl602/bl602_tim_lowerhalf.h
@@ -1,6 +1,9 @@
/**
* incubator-nuttx/arch/risc-v/src/bl602/bl602_lowerhalf.h
*
+ * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
diff --git a/arch/risc-v/src/bl602/bl602_timerisr.c b/arch/risc-v/src/bl602/bl602_timerisr.c
index b5e9e5d..c015b3d 100644
--- a/arch/risc-v/src/bl602/bl602_timerisr.c
+++ b/arch/risc-v/src/bl602/bl602_timerisr.c
@@ -1,6 +1,9 @@
/****************************************************************************
* arch/risc-v/src/bl602/bl602_timerisr.c
*
+ * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
@@ -31,7 +34,7 @@
#include <nuttx/arch.h>
#include <nuttx/clock.h>
#include <arch/board/board.h>
-
+#include "hardware/bl602_clint.h"
#include "riscv_arch.h"
#include "chip.h"
@@ -40,21 +43,14 @@
* Pre-processor Definitions
****************************************************************************/
-#define TICK_COUNT (10 * 1000 * 1000 / TICK_PER_SEC)
-#define CLINT_BASE_ADDRESS 0x02000000
-
-#define getreg64(a) (*(volatile uint64_t *)(a))
-#define putreg64(v, a) (*(volatile uint64_t *)(a) = (v))
+/* Private definetions: mtimer frequency */
+#define TICK_COUNT (10 * 1000 * 1000 / TICK_PER_SEC)
/****************************************************************************
* Private Data
****************************************************************************/
-static bool _b_tick_started = false;
-
-#define MTIMER_HIGH (CLINT_BASE_ADDRESS + 0xBFFC)
-#define MTIMER_LOW (CLINT_BASE_ADDRESS + 0xBFF8)
-#define MTIMER_CMP (CLINT_BASE_ADDRESS + 0x4000)
+static bool g_b_tick_started = false;
/****************************************************************************
* Private Functions
@@ -68,21 +64,21 @@ static bool _b_tick_started = false;
static inline uint64_t bl602_clint_time_read(void)
{
- uint64_t r = getreg32(MTIMER_HIGH);
+ uint64_t r = getreg32(BL602_MTIMER_HIGH);
r <<= 32;
- r |= getreg32(MTIMER_LOW);
+ r |= getreg32(BL602_MTIMER_LOW);
return r;
}
static inline uint64_t bl602_clint_time_cmp_read(void)
{
- return getreg64(MTIMER_CMP);
+ return getreg64(BL602_MTIMER_CMP);
}
static inline void bl602_clint_time_cmp_write(uint64_t v)
{
- putreg64(v, MTIMER_CMP);
+ putreg64(v, BL602_MTIMER_CMP);
}
/****************************************************************************
@@ -96,10 +92,10 @@ static void bl602_reload_mtimecmp(void)
uint64_t current;
uint64_t next;
- if (!_b_tick_started)
+ if (!g_b_tick_started)
{
- _b_tick_started = true;
- current = bl602_clint_time_read();
+ g_b_tick_started = true;
+ current = bl602_clint_time_read();
}
else
{
@@ -154,4 +150,3 @@ void up_timer_initialize(void)
up_enable_irq(BL602_IRQ_MTIMER);
}
-
diff --git a/arch/risc-v/src/bl602/bl602_vectors.S b/arch/risc-v/src/bl602/bl602_vectors.S
index 2c09068..523a698 100644
--- a/arch/risc-v/src/bl602/bl602_vectors.S
+++ b/arch/risc-v/src/bl602/bl602_vectors.S
@@ -1,6 +1,9 @@
/****************************************************************************
* arch/risc-v/src/bl602/bl602_vectors.S
*
+ * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
diff --git a/arch/risc-v/src/bl602/chip.h b/arch/risc-v/src/bl602/chip.h
index afc95b0..a0e7b26 100644
--- a/arch/risc-v/src/bl602/chip.h
+++ b/arch/risc-v/src/bl602/chip.h
@@ -1,6 +1,9 @@
/****************************************************************************
* arch/risc-v/include/bl602/chip.h
*
+ * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
diff --git a/arch/risc-v/src/bl602/bl602_vectors.S b/arch/risc-v/src/bl602/hardware/bl602_clint.h
similarity index 67%
copy from arch/risc-v/src/bl602/bl602_vectors.S
copy to arch/risc-v/src/bl602/hardware/bl602_clint.h
index 2c09068..c1b4e45 100644
--- a/arch/risc-v/src/bl602/bl602_vectors.S
+++ b/arch/risc-v/src/bl602/hardware/bl602_clint.h
@@ -1,5 +1,8 @@
/****************************************************************************
- * arch/risc-v/src/bl602/bl602_vectors.S
+ * arch/risc-v/src/bl602/hardware/bl602_clint.h
+ *
+ * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -18,25 +21,23 @@
*
****************************************************************************/
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
- .section .init
- .global __reset_vec
- .global __trap_vec
+#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CLINT_H
+#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CLINT_H
/****************************************************************************
- * Name: __reset_vec
+ * Included Files
****************************************************************************/
-__reset_vec:
- jal __start
+#include <stdint.h>
/****************************************************************************
- * Name: exception_common
+ * Pre-processor Definitions
****************************************************************************/
-__trap_vec:
- j exception_common
- nop
+#define BL602_CLINT_BASE (0x02000000)
+
+#define BL602_MTIMER_HIGH ((uint32_t *)(BL602_CLINT_BASE + 0xBFFC))
+#define BL602_MTIMER_LOW ((uint32_t *)(BL602_CLINT_BASE + 0xBFF8))
+#define BL602_MTIMER_CMP ((uint64_t *)(BL602_CLINT_BASE + 0x4000))
+
+#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_CLINT_H */
diff --git a/arch/risc-v/src/bl602/hardware/bl602_common.h b/arch/risc-v/src/bl602/hardware/bl602_common.h
index 7b41b64..6b48db0 100644
--- a/arch/risc-v/src/bl602/hardware/bl602_common.h
+++ b/arch/risc-v/src/bl602/hardware/bl602_common.h
@@ -1,6 +1,9 @@
/****************************************************************************
* arch/risc-v/src/bl602/hardware/bl602_common.h
*
+ * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
@@ -31,131 +34,126 @@
* Pre-processor Definitions
****************************************************************************/
-#define BL602_FLASH_XIP_BASE 0x23000000
+#define BL602_FLASH_XIP_BASE (0x23000000)
#define BL602_FLASH_XIP_END (0x23000000 + 16 * 1024 * 1024)
-#define BL602_FLASH_XIP_REMAP0_BASE 0x33000000
+#define BL602_FLASH_XIP_REMAP0_BASE (0x33000000)
#define BL602_FLASH_XIP_REMAP0_END (0x33000000 + 16 * 1024 * 1024)
-#define BL602_FLASH_XIP_REMAP1_BASE 0x43000000
+#define BL602_FLASH_XIP_REMAP1_BASE (0x43000000)
#define BL602_FLASH_XIP_REMAP1_END (0x43000000 + 16 * 1024 * 1024)
-#define BL602_FLASH_XIP_REMAP2_BASE 0x53000000
+#define BL602_FLASH_XIP_REMAP2_BASE (0x53000000)
#define BL602_FLASH_XIP_REMAP2_END (0x53000000 + 16 * 1024 * 1024)
-#define BL602_WRAM_BASE 0x42020000
+#define BL602_WRAM_BASE (0x42020000)
#define BL602_WRAM_END (0x42020000 + 176 * 1024)
-#define BL602_WRAM_REMAP0_BASE 0x22020000
+#define BL602_WRAM_REMAP0_BASE (0x22020000)
#define BL602_WRAM_REMAP0_END (0x22020000 + 176 * 1024)
-#define BL602_WRAM_REMAP1_BASE 0x32020000
+#define BL602_WRAM_REMAP1_BASE (0x32020000)
+
#define BL602_WRAM_REMAP1_END (0x32020000 + 176 * 1024)
-#define BL602_WRAM_REMAP2_BASE 0x52020000
+#define BL602_WRAM_REMAP2_BASE (0x52020000)
#define BL602_WRAM_REMAP2_END (0x52020000 + 176 * 1024)
-#define BL602_TCM_BASE 0x22008000
+#define BL602_TCM_BASE (0x22008000)
#define BL602_TCM_END (0x22008000 + (96 + 176) * 1024)
-#define BL602_TCM_REMAP0_BASE 0x32008000
+#define BL602_TCM_REMAP0_BASE (0x32008000)
#define BL602_TCM_REMAP0_END (0x32008000 + (96 + 176) * 1024)
-#define BL602_TCM_REMAP1_BASE 0x42008000
+#define BL602_TCM_REMAP1_BASE (0x42008000)
#define BL602_TCM_REMAP1_END (0x42008000 + (96 + 176) * 1024)
-#define BL602_TCM_REMAP2_BASE 0x52008000
+#define BL602_TCM_REMAP2_BASE (0x52008000)
#define BL602_TCM_REMAP2_END (0x52008000 + (96 + 176) * 1024)
/* BL602 peripherals base address */
-#define GLB_BASE ((uint32_t)0x40000000)
-#define RF_BASE ((uint32_t)0x40001000)
+#define GLB_BASE (0x40000000)
+#define RF_BASE (0x40001000)
/* AUX module base address */
-#define GPIP_BASE ((uint32_t)0x40002000)
+#define GPIP_BASE (0x40002000)
/* Security Debug module base address */
-#define SEC_DBG_BASE ((uint32_t)0x40003000)
+#define SEC_DBG_BASE (0x40003000)
/* Security Engine module base address */
-#define SEC_ENG_BASE ((uint32_t)0x40004000)
+#define SEC_ENG_BASE (0x40004000)
/* Trustzone control security base address */
-#define TZC_SEC_BASE ((uint32_t)0x40005000)
+#define TZC_SEC_BASE (0x40005000)
/* Trustzone control none-security base address */
-#define TZC_NSEC_BASE ((uint32_t)0x40006000)
-#define EF_DATA_BASE ((uint32_t)0x40007000)
-#define EF_CTRL_BASE ((uint32_t)0x40007000)
-#define CCI_BASE ((uint32_t)0x40008000)
+#define TZC_NSEC_BASE (0x40006000)
+#define EF_DATA_BASE (0x40007000)
+#define EF_CTRL_BASE (0x40007000)
+#define CCI_BASE (0x40008000)
/* L1 cache config base address */
-#define L1C_BASE ((uint32_t)0x40009000)
-#define UART0_BASE ((uint32_t)0x4000A000)
-#define UART1_BASE ((uint32_t)0x4000A100)
-#define SPI_BASE ((uint32_t)0x4000A200)
-#define I2C_BASE ((uint32_t)0x4000A300)
-#define PWM_BASE ((uint32_t)0x4000A400)
-#define TIMER_BASE ((uint32_t)0x4000A500)
-#define IR_BASE ((uint32_t)0x4000A600)
-#define SF_CTRL_BASE ((uint32_t)0x4000B000)
-#define SF_CTRL_BUF_BASE ((uint32_t)0x4000B700)
-#define DMA_BASE ((uint32_t)0x4000C000)
-#define SDU_BASE ((uint32_t)0x4000D000)
+#define L1C_BASE (0x40009000)
+#define UART0_BASE (0x4000A000)
+#define UART1_BASE (0x4000A100)
+#define SPI_BASE (0x4000A200)
+#define I2C_BASE (0x4000A300)
+#define PWM_BASE (0x4000A400)
+#define TIMER_BASE (0x4000A500)
+#define IR_BASE (0x4000A600)
+#define SF_CTRL_BASE (0x4000B000)
+#define SF_CTRL_BUF_BASE (0x4000B700)
+#define DMA_BASE (0x4000C000)
+#define SDU_BASE (0x4000D000)
/* Power down sleep module base address */
-#define PDS_BASE ((uint32_t)0x4000E000)
+#define PDS_BASE (0x4000E000)
/* Hibernate module base address */
-#define HBN_BASE ((uint32_t)0x4000F000)
+#define HBN_BASE (0x4000F000)
/* Always on module base address */
-#define AON_BASE ((uint32_t)0x4000F000)
-#define HBN_RAM_BASE ((uint32_t)0x40010000)
-
-#define BL_RD_WORD(addr) (*((volatile uint32_t *)(addr)))
-#define BL_WR_WORD(addr, val) ((*(volatile uint32_t *)(addr)) = (val))
-#define BL_RD_SHORT(addr) (*((volatile uint16_t *)(addr)))
-#define BL_WR_SHORT(addr, val) ((*(volatile uint16_t *)(addr)) = (val))
-#define BL_RD_BYTE(addr) (*((volatile uint8_t *)(addr)))
-#define BL_WR_BYTE(addr, val) ((*(volatile uint8_t *)(addr)) = (val))
-#define BL_RDWD_FRM_BYTEP(p) \
- ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0]))
-#define BL_WRWD_TO_BYTEP(p, val) \
- { \
- p[0] = val & 0xff; \
- p[1] = (val >> 8) & 0xff; \
- p[2] = (val >> 16) & 0xff; \
- p[3] = (val >> 24) & 0xff; \
- }
-/**
- * @brief Register access macro
- */
-#define BL_RD_REG16(addr, regname) BL_RD_SHORT(addr + regname##_OFFSET)
-#define BL_WR_REG16(addr, regname, val) \
- BL_WR_SHORT(addr + regname##_OFFSET, val)
-#define BL_RD_REG(addr, regname) BL_RD_WORD(addr + regname##_OFFSET)
-#define BL_WR_REG(addr, regname, val) BL_WR_WORD(addr + regname##_OFFSET, val)
-#define BL_SET_REG_BIT(val, bitname) ((val) | (1U << bitname##_POS))
-#define BL_CLR_REG_BIT(val, bitname) ((val)&bitname##_UMSK)
-#define BL_GET_REG_BITS_VAL(val, bitname) \
- (((val)&bitname##_MSK) >> bitname##_POS)
-#define BL_SET_REG_BITS_VAL(val, bitname, bitval) \
- (((val)&bitname##_UMSK) | ((uint32_t)(bitval) << bitname##_POS))
-#define BL_IS_REG_BIT_SET(val, bitname) \
- (((val) & (1U << (bitname##_POS))) != 0)
-#define __NOP() \
- __asm volatile("nop") /* This implementation generates debug information \
- */
-#define BL_DRV_DUMMY \
+#define AON_BASE (0x4000F000)
+#define HBN_RAM_BASE (0x40010000)
+
+/* Delay for a while */
+
+#define BL_DRV_DUMMY() \
{ \
- __NOP(); \
- __NOP(); \
- __NOP(); \
- __NOP(); \
+ __asm volatile("nop"); \
+ __asm volatile("nop"); \
+ __asm volatile("nop"); \
+ __asm volatile("nop"); \
}
+#define BL_AHB_SLAVE1_GLB 0x00
+#define BL_AHB_SLAVE1_RF 0x01
+#define BL_AHB_SLAVE1_GPIP_PHY_AGC 0x02
+#define BL_AHB_SLAVE1_SEC_DBG 0x03
+#define BL_AHB_SLAVE1_SEC 0x04
+#define BL_AHB_SLAVE1_TZ1 0x05
+#define BL_AHB_SLAVE1_TZ2 0x06
+#define BL_AHB_SLAVE1_EFUSE 0x07
+#define BL_AHB_SLAVE1_CCI 0x08
+#define BL_AHB_SLAVE1_L1C 0x09
+#define BL_AHB_SLAVE1_RSVD0A 0x0a
+#define BL_AHB_SLAVE1_SFC 0x0b
+#define BL_AHB_SLAVE1_DMA 0x0c
+#define BL_AHB_SLAVE1_SDU 0x0d
+#define BL_AHB_SLAVE1_PDS_HBN_AON_HBNRAM 0x0e
+#define BL_AHB_SLAVE1_RSVD0F 0x0f
+#define BL_AHB_SLAVE1_UART0 0x10
+#define BL_AHB_SLAVE1_UART1 0x11
+#define BL_AHB_SLAVE1_SPI 0x12
+#define BL_AHB_SLAVE1_I2C 0x13
+#define BL_AHB_SLAVE1_PWM 0x14
+#define BL_AHB_SLAVE1_TMR 0x15
+#define BL_AHB_SLAVE1_IRR 0x16
+#define BL_AHB_SLAVE1_CKS 0x17
+#define BL_AHB_SLAVE1_MAX 0x18
+
/* Std driver attribute macro */
#define ATTR_CLOCK_SECTION __attribute__((section(".sclock_rlt_code")))
@@ -164,8 +162,6 @@
#define ATTR_TCM_CONST_SECTION __attribute__((section(".tcm_const")))
#define ATTR_DTCM_SECTION __attribute__((section(".tcm_data")))
#define ATTR_HSRAM_SECTION __attribute__((section(".hsram_code")))
-#define SystemCoreClockSet(val) BL_WR_WORD(0x4000f108, val)
-#define SystemCoreClockGet(val) BL_RD_WORD(0x4000f108)
/****************************************************************************
* Public Types
@@ -173,39 +169,6 @@
#ifndef __ASSEMBLY__
-enum bl_ahb_slave1_e
-{
- BL_AHB_SLAVE1_GLB = 0x00,
- BL_AHB_SLAVE1_RF = 0x01,
- BL_AHB_SLAVE1_GPIP_PHY_AGC = 0x02,
- BL_AHB_SLAVE1_SEC_DBG = 0x03,
- BL_AHB_SLAVE1_SEC = 0x04,
- BL_AHB_SLAVE1_TZ1 = 0x05,
- BL_AHB_SLAVE1_TZ2 = 0x06,
- BL_AHB_SLAVE1_EFUSE = 0x07,
- BL_AHB_SLAVE1_CCI = 0x08,
- BL_AHB_SLAVE1_L1C = 0x09,
- BL_AHB_SLAVE1_RSVD0A = 0x0a,
- BL_AHB_SLAVE1_SFC = 0x0b,
- BL_AHB_SLAVE1_DMA = 0x0c,
- BL_AHB_SLAVE1_SDU = 0x0d,
- BL_AHB_SLAVE1_PDS_HBN_AON_HBNRAM = 0x0e,
- BL_AHB_SLAVE1_RSVD0F = 0x0f,
- BL_AHB_SLAVE1_UART0 = 0x10,
- BL_AHB_SLAVE1_UART1 = 0x11,
- BL_AHB_SLAVE1_SPI = 0x12,
- BL_AHB_SLAVE1_I2C = 0x13,
- BL_AHB_SLAVE1_PWM = 0x14,
- BL_AHB_SLAVE1_TMR = 0x15,
- BL_AHB_SLAVE1_IRR = 0x16,
- BL_AHB_SLAVE1_CKS = 0x17,
- BL_AHB_SLAVE1_MAX = 0x18,
-};
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
@@ -214,14 +177,6 @@ extern "C"
#define EXTERN extern
#endif
-/****************************************************************************
- * Inline Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
#undef EXTERN
#ifdef __cplusplus
}
diff --git a/arch/risc-v/src/bl602/hardware/bl602_glb.h b/arch/risc-v/src/bl602/hardware/bl602_glb.h
index d99514e..b689001 100644
--- a/arch/risc-v/src/bl602/hardware/bl602_glb.h
+++ b/arch/risc-v/src/bl602/hardware/bl602_glb.h
@@ -1,6 +1,9 @@
/****************************************************************************
* arch/risc-v/src/bl602/hardware/bl602_glb.h
*
+ * Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gn...@nuttx.org>
+ *
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
@@ -35,459 +38,459 @@
#define GLB_CLK_CFG0_OFFSET (0x0)
#define GLB_REG_PLL_EN GLB_REG_PLL_EN
-#define GLB_REG_PLL_EN_POS (0U)
-#define GLB_REG_PLL_EN_LEN (1U)
+#define GLB_REG_PLL_EN_POS (0)
+#define GLB_REG_PLL_EN_LEN (1)
#define GLB_REG_PLL_EN_MSK \
- (((1U << GLB_REG_PLL_EN_LEN) - 1) << GLB_REG_PLL_EN_POS)
+ (((1 << GLB_REG_PLL_EN_LEN) - 1) << GLB_REG_PLL_EN_POS)
#define GLB_REG_PLL_EN_UMSK \
- (~(((1U << GLB_REG_PLL_EN_LEN) - 1) << GLB_REG_PLL_EN_POS))
+ (~(((1 << GLB_REG_PLL_EN_LEN) - 1) << GLB_REG_PLL_EN_POS))
#define GLB_REG_FCLK_EN GLB_REG_FCLK_EN
-#define GLB_REG_FCLK_EN_POS (1U)
-#define GLB_REG_FCLK_EN_LEN (1U)
+#define GLB_REG_FCLK_EN_POS (1)
+#define GLB_REG_FCLK_EN_LEN (1)
#define GLB_REG_FCLK_EN_MSK \
- (((1U << GLB_REG_FCLK_EN_LEN) - 1) << GLB_REG_FCLK_EN_POS)
+ (((1 << GLB_REG_FCLK_EN_LEN) - 1) << GLB_REG_FCLK_EN_POS)
#define GLB_REG_FCLK_EN_UMSK \
- (~(((1U << GLB_REG_FCLK_EN_LEN) - 1) << GLB_REG_FCLK_EN_POS))
+ (~(((1 << GLB_REG_FCLK_EN_LEN) - 1) << GLB_REG_FCLK_EN_POS))
#define GLB_REG_HCLK_EN GLB_REG_HCLK_EN
-#define GLB_REG_HCLK_EN_POS (2U)
-#define GLB_REG_HCLK_EN_LEN (1U)
+#define GLB_REG_HCLK_EN_POS (2)
+#define GLB_REG_HCLK_EN_LEN (1)
#define GLB_REG_HCLK_EN_MSK \
- (((1U << GLB_REG_HCLK_EN_LEN) - 1) << GLB_REG_HCLK_EN_POS)
+ (((1 << GLB_REG_HCLK_EN_LEN) - 1) << GLB_REG_HCLK_EN_POS)
#define GLB_REG_HCLK_EN_UMSK \
- (~(((1U << GLB_REG_HCLK_EN_LEN) - 1) << GLB_REG_HCLK_EN_POS))
+ (~(((1 << GLB_REG_HCLK_EN_LEN) - 1) << GLB_REG_HCLK_EN_POS))
#define GLB_REG_BCLK_EN GLB_REG_BCLK_EN
-#define GLB_REG_BCLK_EN_POS (3U)
-#define GLB_REG_BCLK_EN_LEN (1U)
+#define GLB_REG_BCLK_EN_POS (3)
+#define GLB_REG_BCLK_EN_LEN (1)
#define GLB_REG_BCLK_EN_MSK \
- (((1U << GLB_REG_BCLK_EN_LEN) - 1) << GLB_REG_BCLK_EN_POS)
+ (((1 << GLB_REG_BCLK_EN_LEN) - 1) << GLB_REG_BCLK_EN_POS)
#define GLB_REG_BCLK_EN_UMSK \
- (~(((1U << GLB_REG_BCLK_EN_LEN) - 1) << GLB_REG_BCLK_EN_POS))
+ (~(((1 << GLB_REG_BCLK_EN_LEN) - 1) << GLB_REG_BCLK_EN_POS))
#define GLB_REG_PLL_SEL GLB_REG_PLL_SEL
-#define GLB_REG_PLL_SEL_POS (4U)
-#define GLB_REG_PLL_SEL_LEN (2U)
+#define GLB_REG_PLL_SEL_POS (4)
+#define GLB_REG_PLL_SEL_LEN (2)
#define GLB_REG_PLL_SEL_MSK \
- (((1U << GLB_REG_PLL_SEL_LEN) - 1) << GLB_REG_PLL_SEL_POS)
+ (((1 << GLB_REG_PLL_SEL_LEN) - 1) << GLB_REG_PLL_SEL_POS)
#define GLB_REG_PLL_SEL_UMSK \
- (~(((1U << GLB_REG_PLL_SEL_LEN) - 1) << GLB_REG_PLL_SEL_POS))
+ (~(((1 << GLB_REG_PLL_SEL_LEN) - 1) << GLB_REG_PLL_SEL_POS))
#define GLB_HBN_ROOT_CLK_SEL GLB_HBN_ROOT_CLK_SEL
-#define GLB_HBN_ROOT_CLK_SEL_POS (6U)
-#define GLB_HBN_ROOT_CLK_SEL_LEN (2U)
+#define GLB_HBN_ROOT_CLK_SEL_POS (6)
+#define GLB_HBN_ROOT_CLK_SEL_LEN (2)
#define GLB_HBN_ROOT_CLK_SEL_MSK \
- (((1U << GLB_HBN_ROOT_CLK_SEL_LEN) - 1) << GLB_HBN_ROOT_CLK_SEL_POS)
+ (((1 << GLB_HBN_ROOT_CLK_SEL_LEN) - 1) << GLB_HBN_ROOT_CLK_SEL_POS)
#define GLB_HBN_ROOT_CLK_SEL_UMSK \
- (~(((1U << GLB_HBN_ROOT_CLK_SEL_LEN) - 1) << GLB_HBN_ROOT_CLK_SEL_POS))
+ (~(((1 << GLB_HBN_ROOT_CLK_SEL_LEN) - 1) << GLB_HBN_ROOT_CLK_SEL_POS))
#define GLB_REG_HCLK_DIV GLB_REG_HCLK_DIV
-#define GLB_REG_HCLK_DIV_POS (8U)
-#define GLB_REG_HCLK_DIV_LEN (8U)
+#define GLB_REG_HCLK_DIV_POS (8)
+#define GLB_REG_HCLK_DIV_LEN (8)
#define GLB_REG_HCLK_DIV_MSK \
- (((1U << GLB_REG_HCLK_DIV_LEN) - 1) << GLB_REG_HCLK_DIV_POS)
+ (((1 << GLB_REG_HCLK_DIV_LEN) - 1) << GLB_REG_HCLK_DIV_POS)
#define GLB_REG_HCLK_DIV_UMSK \
- (~(((1U << GLB_REG_HCLK_DIV_LEN) - 1) << GLB_REG_HCLK_DIV_POS))
+ (~(((1 << GLB_REG_HCLK_DIV_LEN) - 1) << GLB_REG_HCLK_DIV_POS))
#define GLB_REG_BCLK_DIV GLB_REG_BCLK_DIV
-#define GLB_REG_BCLK_DIV_POS (16U)
-#define GLB_REG_BCLK_DIV_LEN (8U)
+#define GLB_REG_BCLK_DIV_POS (16)
+#define GLB_REG_BCLK_DIV_LEN (8)
#define GLB_REG_BCLK_DIV_MSK \
- (((1U << GLB_REG_BCLK_DIV_LEN) - 1) << GLB_REG_BCLK_DIV_POS)
+ (((1 << GLB_REG_BCLK_DIV_LEN) - 1) << GLB_REG_BCLK_DIV_POS)
#define GLB_REG_BCLK_DIV_UMSK \
- (~(((1U << GLB_REG_BCLK_DIV_LEN) - 1) << GLB_REG_BCLK_DIV_POS))
+ (~(((1 << GLB_REG_BCLK_DIV_LEN) - 1) << GLB_REG_BCLK_DIV_POS))
#define GLB_FCLK_SW_STATE GLB_FCLK_SW_STATE
-#define GLB_FCLK_SW_STATE_POS (24U)
-#define GLB_FCLK_SW_STATE_LEN (3U)
+#define GLB_FCLK_SW_STATE_POS (24)
+#define GLB_FCLK_SW_STATE_LEN (3)
#define GLB_FCLK_SW_STATE_MSK \
- (((1U << GLB_FCLK_SW_STATE_LEN) - 1) << GLB_FCLK_SW_STATE_POS)
+ (((1 << GLB_FCLK_SW_STATE_LEN) - 1) << GLB_FCLK_SW_STATE_POS)
#define GLB_FCLK_SW_STATE_UMSK \
- (~(((1U << GLB_FCLK_SW_STATE_LEN) - 1) << GLB_FCLK_SW_STATE_POS))
+ (~(((1 << GLB_FCLK_SW_STATE_LEN) - 1) << GLB_FCLK_SW_STATE_POS))
#define GLB_CHIP_RDY GLB_CHIP_RDY
-#define GLB_CHIP_RDY_POS (27U)
-#define GLB_CHIP_RDY_LEN (1U)
-#define GLB_CHIP_RDY_MSK (((1U << GLB_CHIP_RDY_LEN) - 1) << GLB_CHIP_RDY_POS)
+#define GLB_CHIP_RDY_POS (27)
+#define GLB_CHIP_RDY_LEN (1)
+#define GLB_CHIP_RDY_MSK (((1 << GLB_CHIP_RDY_LEN) - 1) << GLB_CHIP_RDY_POS)
#define GLB_CHIP_RDY_UMSK \
- (~(((1U << GLB_CHIP_RDY_LEN) - 1) << GLB_CHIP_RDY_POS))
+ (~(((1 << GLB_CHIP_RDY_LEN) - 1) << GLB_CHIP_RDY_POS))
#define GLB_ID GLB_ID
-#define GLB_ID_POS (28U)
-#define GLB_ID_LEN (4U)
-#define GLB_ID_MSK (((1U << GLB_ID_LEN) - 1) << GLB_ID_POS)
-#define GLB_ID_UMSK (~(((1U << GLB_ID_LEN) - 1) << GLB_ID_POS))
+#define GLB_ID_POS (28)
+#define GLB_ID_LEN (4)
+#define GLB_ID_MSK (((1 << GLB_ID_LEN) - 1) << GLB_ID_POS)
+#define GLB_ID_UMSK (~(((1 << GLB_ID_LEN) - 1) << GLB_ID_POS))
/* 0x4 : clk_cfg1 */
#define GLB_CLK_CFG1_OFFSET (0x4)
#define GLB_WIFI_MAC_CORE_DIV GLB_WIFI_MAC_CORE_DIV
-#define GLB_WIFI_MAC_CORE_DIV_POS (0U)
-#define GLB_WIFI_MAC_CORE_DIV_LEN (4U)
+#define GLB_WIFI_MAC_CORE_DIV_POS (0)
+#define GLB_WIFI_MAC_CORE_DIV_LEN (4)
#define GLB_WIFI_MAC_CORE_DIV_MSK \
- (((1U << GLB_WIFI_MAC_CORE_DIV_LEN) - 1) << GLB_WIFI_MAC_CORE_DIV_POS)
+ (((1 << GLB_WIFI_MAC_CORE_DIV_LEN) - 1) << GLB_WIFI_MAC_CORE_DIV_POS)
#define GLB_WIFI_MAC_CORE_DIV_UMSK \
- (~(((1U << GLB_WIFI_MAC_CORE_DIV_LEN) - 1) << GLB_WIFI_MAC_CORE_DIV_POS))
+ (~(((1 << GLB_WIFI_MAC_CORE_DIV_LEN) - 1) << GLB_WIFI_MAC_CORE_DIV_POS))
#define GLB_WIFI_MAC_WT_DIV GLB_WIFI_MAC_WT_DIV
-#define GLB_WIFI_MAC_WT_DIV_POS (4U)
-#define GLB_WIFI_MAC_WT_DIV_LEN (4U)
+#define GLB_WIFI_MAC_WT_DIV_POS (4)
+#define GLB_WIFI_MAC_WT_DIV_LEN (4)
#define GLB_WIFI_MAC_WT_DIV_MSK \
- (((1U << GLB_WIFI_MAC_WT_DIV_LEN) - 1) << GLB_WIFI_MAC_WT_DIV_POS)
+ (((1 << GLB_WIFI_MAC_WT_DIV_LEN) - 1) << GLB_WIFI_MAC_WT_DIV_POS)
#define GLB_WIFI_MAC_WT_DIV_UMSK \
- (~(((1U << GLB_WIFI_MAC_WT_DIV_LEN) - 1) << GLB_WIFI_MAC_WT_DIV_POS))
+ (~(((1 << GLB_WIFI_MAC_WT_DIV_LEN) - 1) << GLB_WIFI_MAC_WT_DIV_POS))
#define GLB_BLE_CLK_SEL GLB_BLE_CLK_SEL
-#define GLB_BLE_CLK_SEL_POS (16U)
-#define GLB_BLE_CLK_SEL_LEN (6U)
+#define GLB_BLE_CLK_SEL_POS (16)
+#define GLB_BLE_CLK_SEL_LEN (6)
#define GLB_BLE_CLK_SEL_MSK \
- (((1U << GLB_BLE_CLK_SEL_LEN) - 1) << GLB_BLE_CLK_SEL_POS)
+ (((1 << GLB_BLE_CLK_SEL_LEN) - 1) << GLB_BLE_CLK_SEL_POS)
#define GLB_BLE_CLK_SEL_UMSK \
- (~(((1U << GLB_BLE_CLK_SEL_LEN) - 1) << GLB_BLE_CLK_SEL_POS))
+ (~(((1 << GLB_BLE_CLK_SEL_LEN) - 1) << GLB_BLE_CLK_SEL_POS))
#define GLB_BLE_EN GLB_BLE_EN
-#define GLB_BLE_EN_POS (24U)
-#define GLB_BLE_EN_LEN (1U)
-#define GLB_BLE_EN_MSK (((1U << GLB_BLE_EN_LEN) - 1) << GLB_BLE_EN_POS)
-#define GLB_BLE_EN_UMSK (~(((1U << GLB_BLE_EN_LEN) - 1) << GLB_BLE_EN_POS))
+#define GLB_BLE_EN_POS (24)
+#define GLB_BLE_EN_LEN (1)
+#define GLB_BLE_EN_MSK (((1 << GLB_BLE_EN_LEN) - 1) << GLB_BLE_EN_POS)
+#define GLB_BLE_EN_UMSK (~(((1 << GLB_BLE_EN_LEN) - 1) << GLB_BLE_EN_POS))
/* 0x8 : clk_cfg2 */
#define GLB_CLK_CFG2_OFFSET (0x8)
#define GLB_UART_CLK_DIV GLB_UART_CLK_DIV
-#define GLB_UART_CLK_DIV_POS (0U)
-#define GLB_UART_CLK_DIV_LEN (3U)
+#define GLB_UART_CLK_DIV_POS (0)
+#define GLB_UART_CLK_DIV_LEN (3)
#define GLB_UART_CLK_DIV_MSK \
- (((1U << GLB_UART_CLK_DIV_LEN) - 1) << GLB_UART_CLK_DIV_POS)
+ (((1 << GLB_UART_CLK_DIV_LEN) - 1) << GLB_UART_CLK_DIV_POS)
#define GLB_UART_CLK_DIV_UMSK \
- (~(((1U << GLB_UART_CLK_DIV_LEN) - 1) << GLB_UART_CLK_DIV_POS))
+ (~(((1 << GLB_UART_CLK_DIV_LEN) - 1) << GLB_UART_CLK_DIV_POS))
#define GLB_UART_CLK_EN GLB_UART_CLK_EN
-#define GLB_UART_CLK_EN_POS (4U)
-#define GLB_UART_CLK_EN_LEN (1U)
+#define GLB_UART_CLK_EN_POS (4)
+#define GLB_UART_CLK_EN_LEN (1)
#define GLB_UART_CLK_EN_MSK \
- (((1U << GLB_UART_CLK_EN_LEN) - 1) << GLB_UART_CLK_EN_POS)
+ (((1 << GLB_UART_CLK_EN_LEN) - 1) << GLB_UART_CLK_EN_POS)
#define GLB_UART_CLK_EN_UMSK \
- (~(((1U << GLB_UART_CLK_EN_LEN) - 1) << GLB_UART_CLK_EN_POS))
+ (~(((1 << GLB_UART_CLK_EN_LEN) - 1) << GLB_UART_CLK_EN_POS))
#define GLB_HBN_UART_CLK_SEL GLB_HBN_UART_CLK_SEL
-#define GLB_HBN_UART_CLK_SEL_POS (7U)
-#define GLB_HBN_UART_CLK_SEL_LEN (1U)
+#define GLB_HBN_UART_CLK_SEL_POS (7)
+#define GLB_HBN_UART_CLK_SEL_LEN (1)
#define GLB_HBN_UART_CLK_SEL_MSK \
- (((1U << GLB_HBN_UART_CLK_SEL_LEN) - 1) << GLB_HBN_UART_CLK_SEL_POS)
+ (((1 << GLB_HBN_UART_CLK_SEL_LEN) - 1) << GLB_HBN_UART_CLK_SEL_POS)
#define GLB_HBN_UART_CLK_SEL_UMSK \
- (~(((1U << GLB_HBN_UART_CLK_SEL_LEN) - 1) << GLB_HBN_UART_CLK_SEL_POS))
+ (~(((1 << GLB_HBN_UART_CLK_SEL_LEN) - 1) << GLB_HBN_UART_CLK_SEL_POS))
#define GLB_SF_CLK_DIV GLB_SF_CLK_DIV
-#define GLB_SF_CLK_DIV_POS (8U)
-#define GLB_SF_CLK_DIV_LEN (3U)
+#define GLB_SF_CLK_DIV_POS (8)
+#define GLB_SF_CLK_DIV_LEN (3)
#define GLB_SF_CLK_DIV_MSK \
- (((1U << GLB_SF_CLK_DIV_LEN) - 1) << GLB_SF_CLK_DIV_POS)
+ (((1 << GLB_SF_CLK_DIV_LEN) - 1) << GLB_SF_CLK_DIV_POS)
#define GLB_SF_CLK_DIV_UMSK \
- (~(((1U << GLB_SF_CLK_DIV_LEN) - 1) << GLB_SF_CLK_DIV_POS))
+ (~(((1 << GLB_SF_CLK_DIV_LEN) - 1) << GLB_SF_CLK_DIV_POS))
#define GLB_SF_CLK_EN GLB_SF_CLK_EN
-#define GLB_SF_CLK_EN_POS (11U)
-#define GLB_SF_CLK_EN_LEN (1U)
+#define GLB_SF_CLK_EN_POS (11)
+#define GLB_SF_CLK_EN_LEN (1)
#define GLB_SF_CLK_EN_MSK \
- (((1U << GLB_SF_CLK_EN_LEN) - 1) << GLB_SF_CLK_EN_POS)
+ (((1 << GLB_SF_CLK_EN_LEN) - 1) << GLB_SF_CLK_EN_POS)
#define GLB_SF_CLK_EN_UMSK \
- (~(((1U << GLB_SF_CLK_EN_LEN) - 1) << GLB_SF_CLK_EN_POS))
+ (~(((1 << GLB_SF_CLK_EN_LEN) - 1) << GLB_SF_CLK_EN_POS))
#define GLB_SF_CLK_SEL GLB_SF_CLK_SEL
-#define GLB_SF_CLK_SEL_POS (12U)
-#define GLB_SF_CLK_SEL_LEN (2U)
+#define GLB_SF_CLK_SEL_POS (12)
+#define GLB_SF_CLK_SEL_LEN (2)
#define GLB_SF_CLK_SEL_MSK \
- (((1U << GLB_SF_CLK_SEL_LEN) - 1) << GLB_SF_CLK_SEL_POS)
+ (((1 << GLB_SF_CLK_SEL_LEN) - 1) << GLB_SF_CLK_SEL_POS)
#define GLB_SF_CLK_SEL_UMSK \
- (~(((1U << GLB_SF_CLK_SEL_LEN) - 1) << GLB_SF_CLK_SEL_POS))
+ (~(((1 << GLB_SF_CLK_SEL_LEN) - 1) << GLB_SF_CLK_SEL_POS))
#define GLB_SF_CLK_SEL2 GLB_SF_CLK_SEL2
-#define GLB_SF_CLK_SEL2_POS (14U)
-#define GLB_SF_CLK_SEL2_LEN (2U)
+#define GLB_SF_CLK_SEL2_POS (14)
+#define GLB_SF_CLK_SEL2_LEN (2)
#define GLB_SF_CLK_SEL2_MSK \
- (((1U << GLB_SF_CLK_SEL2_LEN) - 1) << GLB_SF_CLK_SEL2_POS)
+ (((1 << GLB_SF_CLK_SEL2_LEN) - 1) << GLB_SF_CLK_SEL2_POS)
#define GLB_SF_CLK_SEL2_UMSK \
- (~(((1U << GLB_SF_CLK_SEL2_LEN) - 1) << GLB_SF_CLK_SEL2_POS))
+ (~(((1 << GLB_SF_CLK_SEL2_LEN) - 1) << GLB_SF_CLK_SEL2_POS))
#define GLB_IR_CLK_DIV GLB_IR_CLK_DIV
-#define GLB_IR_CLK_DIV_POS (16U)
-#define GLB_IR_CLK_DIV_LEN (6U)
+#define GLB_IR_CLK_DIV_POS (16)
+#define GLB_IR_CLK_DIV_LEN (6)
#define GLB_IR_CLK_DIV_MSK \
- (((1U << GLB_IR_CLK_DIV_LEN) - 1) << GLB_IR_CLK_DIV_POS)
+ (((1 << GLB_IR_CLK_DIV_LEN) - 1) << GLB_IR_CLK_DIV_POS)
#define GLB_IR_CLK_DIV_UMSK \
- (~(((1U << GLB_IR_CLK_DIV_LEN) - 1) << GLB_IR_CLK_DIV_POS))
+ (~(((1 << GLB_IR_CLK_DIV_LEN) - 1) << GLB_IR_CLK_DIV_POS))
#define GLB_IR_CLK_EN GLB_IR_CLK_EN
-#define GLB_IR_CLK_EN_POS (23U)
-#define GLB_IR_CLK_EN_LEN (1U)
+#define GLB_IR_CLK_EN_POS (23)
+#define GLB_IR_CLK_EN_LEN (1)
#define GLB_IR_CLK_EN_MSK \
- (((1U << GLB_IR_CLK_EN_LEN) - 1) << GLB_IR_CLK_EN_POS)
+ (((1 << GLB_IR_CLK_EN_LEN) - 1) << GLB_IR_CLK_EN_POS)
#define GLB_IR_CLK_EN_UMSK \
- (~(((1U << GLB_IR_CLK_EN_LEN) - 1) << GLB_IR_CLK_EN_POS))
+ (~(((1 << GLB_IR_CLK_EN_LEN) - 1) << GLB_IR_CLK_EN_POS))
#define GLB_DMA_CLK_EN GLB_DMA_CLK_EN
-#define GLB_DMA_CLK_EN_POS (24U)
-#define GLB_DMA_CLK_EN_LEN (8U)
+#define GLB_DMA_CLK_EN_POS (24)
+#define GLB_DMA_CLK_EN_LEN (8)
#define GLB_DMA_CLK_EN_MSK \
- (((1U << GLB_DMA_CLK_EN_LEN) - 1) << GLB_DMA_CLK_EN_POS)
+ (((1 << GLB_DMA_CLK_EN_LEN) - 1) << GLB_DMA_CLK_EN_POS)
#define GLB_DMA_CLK_EN_UMSK \
- (~(((1U << GLB_DMA_CLK_EN_LEN) - 1) << GLB_DMA_CLK_EN_POS))
+ (~(((1 << GLB_DMA_CLK_EN_LEN) - 1) << GLB_DMA_CLK_EN_POS))
/* 0xC : clk_cfg3 */
#define GLB_CLK_CFG3_OFFSET (0xC)
#define GLB_SPI_CLK_DIV GLB_SPI_CLK_DIV
-#define GLB_SPI_CLK_DIV_POS (0U)
-#define GLB_SPI_CLK_DIV_LEN (5U)
+#define GLB_SPI_CLK_DIV_POS (0)
+#define GLB_SPI_CLK_DIV_LEN (5)
#define GLB_SPI_CLK_DIV_MSK \
- (((1U << GLB_SPI_CLK_DIV_LEN) - 1) << GLB_SPI_CLK_DIV_POS)
+ (((1 << GLB_SPI_CLK_DIV_LEN) - 1) << GLB_SPI_CLK_DIV_POS)
#define GLB_SPI_CLK_DIV_UMSK \
- (~(((1U << GLB_SPI_CLK_DIV_LEN) - 1) << GLB_SPI_CLK_DIV_POS))
+ (~(((1 << GLB_SPI_CLK_DIV_LEN) - 1) << GLB_SPI_CLK_DIV_POS))
#define GLB_SPI_CLK_EN GLB_SPI_CLK_EN
-#define GLB_SPI_CLK_EN_POS (8U)
-#define GLB_SPI_CLK_EN_LEN (1U)
+#define GLB_SPI_CLK_EN_POS (8)
+#define GLB_SPI_CLK_EN_LEN (1)
#define GLB_SPI_CLK_EN_MSK \
- (((1U << GLB_SPI_CLK_EN_LEN) - 1) << GLB_SPI_CLK_EN_POS)
+ (((1 << GLB_SPI_CLK_EN_LEN) - 1) << GLB_SPI_CLK_EN_POS)
#define GLB_SPI_CLK_EN_UMSK \
- (~(((1U << GLB_SPI_CLK_EN_LEN) - 1) << GLB_SPI_CLK_EN_POS))
+ (~(((1 << GLB_SPI_CLK_EN_LEN) - 1) << GLB_SPI_CLK_EN_POS))
#define GLB_I2C_CLK_DIV GLB_I2C_CLK_DIV
-#define GLB_I2C_CLK_DIV_POS (16U)
-#define GLB_I2C_CLK_DIV_LEN (8U)
+#define GLB_I2C_CLK_DIV_POS (16)
+#define GLB_I2C_CLK_DIV_LEN (8)
#define GLB_I2C_CLK_DIV_MSK \
- (((1U << GLB_I2C_CLK_DIV_LEN) - 1) << GLB_I2C_CLK_DIV_POS)
+ (((1 << GLB_I2C_CLK_DIV_LEN) - 1) << GLB_I2C_CLK_DIV_POS)
#define GLB_I2C_CLK_DIV_UMSK \
- (~(((1U << GLB_I2C_CLK_DIV_LEN) - 1) << GLB_I2C_CLK_DIV_POS))
+ (~(((1 << GLB_I2C_CLK_DIV_LEN) - 1) << GLB_I2C_CLK_DIV_POS))
#define GLB_I2C_CLK_EN GLB_I2C_CLK_EN
-#define GLB_I2C_CLK_EN_POS (24U)
-#define GLB_I2C_CLK_EN_LEN (1U)
+#define GLB_I2C_CLK_EN_POS (24)
+#define GLB_I2C_CLK_EN_LEN (1)
#define GLB_I2C_CLK_EN_MSK \
- (((1U << GLB_I2C_CLK_EN_LEN) - 1) << GLB_I2C_CLK_EN_POS)
+ (((1 << GLB_I2C_CLK_EN_LEN) - 1) << GLB_I2C_CLK_EN_POS)
#define GLB_I2C_CLK_EN_UMSK \
- (~(((1U << GLB_I2C_CLK_EN_LEN) - 1) << GLB_I2C_CLK_EN_POS))
+ (~(((1 << GLB_I2C_CLK_EN_LEN) - 1) << GLB_I2C_CLK_EN_POS))
/* 0x10 : swrst_cfg0 */
#define GLB_SWRST_CFG0_OFFSET (0x10)
#define GLB_SWRST_S00 GLB_SWRST_S00
-#define GLB_SWRST_S00_POS (0U)
-#define GLB_SWRST_S00_LEN (1U)
+#define GLB_SWRST_S00_POS (0)
+#define GLB_SWRST_S00_LEN (1)
#define GLB_SWRST_S00_MSK \
- (((1U << GLB_SWRST_S00_LEN) - 1) << GLB_SWRST_S00_POS)
+ (((1 << GLB_SWRST_S00_LEN) - 1) << GLB_SWRST_S00_POS)
#define GLB_SWRST_S00_UMSK \
- (~(((1U << GLB_SWRST_S00_LEN) - 1) << GLB_SWRST_S00_POS))
+ (~(((1 << GLB_SWRST_S00_LEN) - 1) << GLB_SWRST_S00_POS))
#define GLB_SWRST_S01 GLB_SWRST_S01
-#define GLB_SWRST_S01_POS (1U)
-#define GLB_SWRST_S01_LEN (1U)
+#define GLB_SWRST_S01_POS (1)
+#define GLB_SWRST_S01_LEN (1)
#define GLB_SWRST_S01_MSK \
- (((1U << GLB_SWRST_S01_LEN) - 1) << GLB_SWRST_S01_POS)
+ (((1 << GLB_SWRST_S01_LEN) - 1) << GLB_SWRST_S01_POS)
#define GLB_SWRST_S01_UMSK \
- (~(((1U << GLB_SWRST_S01_LEN) - 1) << GLB_SWRST_S01_POS))
+ (~(((1 << GLB_SWRST_S01_LEN) - 1) << GLB_SWRST_S01_POS))
#define GLB_SWRST_S20 GLB_SWRST_S20
-#define GLB_SWRST_S20_POS (4U)
-#define GLB_SWRST_S20_LEN (1U)
+#define GLB_SWRST_S20_POS (4)
+#define GLB_SWRST_S20_LEN (1)
#define GLB_SWRST_S20_MSK \
- (((1U << GLB_SWRST_S20_LEN) - 1) << GLB_SWRST_S20_POS)
+ (((1 << GLB_SWRST_S20_LEN) - 1) << GLB_SWRST_S20_POS)
#define GLB_SWRST_S20_UMSK \
- (~(((1U << GLB_SWRST_S20_LEN) - 1) << GLB_SWRST_S20_POS))
+ (~(((1 << GLB_SWRST_S20_LEN) - 1) << GLB_SWRST_S20_POS))
#define GLB_SWRST_S30 GLB_SWRST_S30
-#define GLB_SWRST_S30_POS (8U)
-#define GLB_SWRST_S30_LEN (1U)
+#define GLB_SWRST_S30_POS (8)
+#define GLB_SWRST_S30_LEN (1)
#define GLB_SWRST_S30_MSK \
- (((1U << GLB_SWRST_S30_LEN) - 1) << GLB_SWRST_S30_POS)
+ (((1 << GLB_SWRST_S30_LEN) - 1) << GLB_SWRST_S30_POS)
#define GLB_SWRST_S30_UMSK \
- (~(((1U << GLB_SWRST_S30_LEN) - 1) << GLB_SWRST_S30_POS))
+ (~(((1 << GLB_SWRST_S30_LEN) - 1) << GLB_SWRST_S30_POS))
/* 0x14 : swrst_cfg1 */
#define GLB_SWRST_CFG1_OFFSET (0x14)
#define GLB_SWRST_S10 GLB_SWRST_S10
-#define GLB_SWRST_S10_POS (0U)
-#define GLB_SWRST_S10_LEN (1U)
+#define GLB_SWRST_S10_POS (0)
+#define GLB_SWRST_S10_LEN (1)
#define GLB_SWRST_S10_MSK \
- (((1U << GLB_SWRST_S10_LEN) - 1) << GLB_SWRST_S10_POS)
+ (((1 << GLB_SWRST_S10_LEN) - 1) << GLB_SWRST_S10_POS)
#define GLB_SWRST_S10_UMSK \
- (~(((1U << GLB_SWRST_S10_LEN) - 1) << GLB_SWRST_S10_POS))
+ (~(((1 << GLB_SWRST_S10_LEN) - 1) << GLB_SWRST_S10_POS))
#define GLB_SWRST_S11 GLB_SWRST_S11
-#define GLB_SWRST_S11_POS (1U)
-#define GLB_SWRST_S11_LEN (1U)
+#define GLB_SWRST_S11_POS (1)
+#define GLB_SWRST_S11_LEN (1)
#define GLB_SWRST_S11_MSK \
- (((1U << GLB_SWRST_S11_LEN) - 1) << GLB_SWRST_S11_POS)
+ (((1 << GLB_SWRST_S11_LEN) - 1) << GLB_SWRST_S11_POS)
#define GLB_SWRST_S11_UMSK \
- (~(((1U << GLB_SWRST_S11_LEN) - 1) << GLB_SWRST_S11_POS))
+ (~(((1 << GLB_SWRST_S11_LEN) - 1) << GLB_SWRST_S11_POS))
#define GLB_SWRST_S12 GLB_SWRST_S12
-#define GLB_SWRST_S12_POS (2U)
-#define GLB_SWRST_S12_LEN (1U)
+#define GLB_SWRST_S12_POS (2)
+#define GLB_SWRST_S12_LEN (1)
#define GLB_SWRST_S12_MSK \
- (((1U << GLB_SWRST_S12_LEN) - 1) << GLB_SWRST_S12_POS)
+ (((1 << GLB_SWRST_S12_LEN) - 1) << GLB_SWRST_S12_POS)
#define GLB_SWRST_S12_UMSK \
- (~(((1U << GLB_SWRST_S12_LEN) - 1) << GLB_SWRST_S12_POS))
+ (~(((1 << GLB_SWRST_S12_LEN) - 1) << GLB_SWRST_S12_POS))
#define GLB_SWRST_S13 GLB_SWRST_S13
-#define GLB_SWRST_S13_POS (3U)
-#define GLB_SWRST_S13_LEN (1U)
+#define GLB_SWRST_S13_POS (3)
+#define GLB_SWRST_S13_LEN (1)
#define GLB_SWRST_S13_MSK \
- (((1U << GLB_SWRST_S13_LEN) - 1) << GLB_SWRST_S13_POS)
+ (((1 << GLB_SWRST_S13_LEN) - 1) << GLB_SWRST_S13_POS)
#define GLB_SWRST_S13_UMSK \
- (~(((1U << GLB_SWRST_S13_LEN) - 1) << GLB_SWRST_S13_POS))
+ (~(((1 << GLB_SWRST_S13_LEN) - 1) << GLB_SWRST_S13_POS))
#define GLB_SWRST_S14 GLB_SWRST_S14
-#define GLB_SWRST_S14_POS (4U)
-#define GLB_SWRST_S14_LEN (1U)
+#define GLB_SWRST_S14_POS (4)
+#define GLB_SWRST_S14_LEN (1)
#define GLB_SWRST_S14_MSK \
- (((1U << GLB_SWRST_S14_LEN) - 1) << GLB_SWRST_S14_POS)
+ (((1 << GLB_SWRST_S14_LEN) - 1) << GLB_SWRST_S14_POS)
#define GLB_SWRST_S14_UMSK \
- (~(((1U << GLB_SWRST_S14_LEN) - 1) << GLB_SWRST_S14_POS))
+ (~(((1 << GLB_SWRST_S14_LEN) - 1) << GLB_SWRST_S14_POS))
#define GLB_SWRST_S15 GLB_SWRST_S15
-#define GLB_SWRST_S15_POS (5U)
-#define GLB_SWRST_S15_LEN (1U)
+#define GLB_SWRST_S15_POS (5)
+#define GLB_SWRST_S15_LEN (1)
#define GLB_SWRST_S15_MSK \
- (((1U << GLB_SWRST_S15_LEN) - 1) << GLB_SWRST_S15_POS)
+ (((1 << GLB_SWRST_S15_LEN) - 1) << GLB_SWRST_S15_POS)
#define GLB_SWRST_S15_UMSK \
- (~(((1U << GLB_SWRST_S15_LEN) - 1) << GLB_SWRST_S15_POS))
+ (~(((1 << GLB_SWRST_S15_LEN) - 1) << GLB_SWRST_S15_POS))
#define GLB_SWRST_S16 GLB_SWRST_S16
-#define GLB_SWRST_S16_POS (6U)
-#define GLB_SWRST_S16_LEN (1U)
+#define GLB_SWRST_S16_POS (6)
+#define GLB_SWRST_S16_LEN (1)
#define GLB_SWRST_S16_MSK \
- (((1U << GLB_SWRST_S16_LEN) - 1) << GLB_SWRST_S16_POS)
+ (((1 << GLB_SWRST_S16_LEN) - 1) << GLB_SWRST_S16_POS)
#define GLB_SWRST_S16_UMSK \
- (~(((1U << GLB_SWRST_S16_LEN) - 1) << GLB_SWRST_S16_POS))
+ (~(((1 << GLB_SWRST_S16_LEN) - 1) << GLB_SWRST_S16_POS))
#define GLB_SWRST_S17 GLB_SWRST_S17
-#define GLB_SWRST_S17_POS (7U)
-#define GLB_SWRST_S17_LEN (1U)
+#define GLB_SWRST_S17_POS (7)
+#define GLB_SWRST_S17_LEN (1)
#define GLB_SWRST_S17_MSK \
- (((1U << GLB_SWRST_S17_LEN) - 1) << GLB_SWRST_S17_POS)
+ (((1 << GLB_SWRST_S17_LEN) - 1) << GLB_SWRST_S17_POS)
#define GLB_SWRST_S17_UMSK \
- (~(((1U << GLB_SWRST_S17_LEN) - 1) << GLB_SWRST_S17_POS))
+ (~(((1 << GLB_SWRST_S17_LEN) - 1) << GLB_SWRST_S17_POS))
#define GLB_SWRST_S18 GLB_SWRST_S18
-#define GLB_SWRST_S18_POS (8U)
-#define GLB_SWRST_S18_LEN (1U)
+#define GLB_SWRST_S18_POS (8)
+#define GLB_SWRST_S18_LEN (1)
#define GLB_SWRST_S18_MSK \
- (((1U << GLB_SWRST_S18_LEN) - 1) << GLB_SWRST_S18_POS)
+ (((1 << GLB_SWRST_S18_LEN) - 1) << GLB_SWRST_S18_POS)
#define GLB_SWRST_S18_UMSK \
- (~(((1U << GLB_SWRST_S18_LEN) - 1) << GLB_SWRST_S18_POS))
+ (~(((1 << GLB_SWRST_S18_LEN) - 1) << GLB_SWRST_S18_POS))
#define GLB_SWRST_S19 GLB_SWRST_S19
-#define GLB_SWRST_S19_POS (9U)
-#define GLB_SWRST_S19_LEN (1U)
+#define GLB_SWRST_S19_POS (9)
+#define GLB_SWRST_S19_LEN (1)
#define GLB_SWRST_S19_MSK \
- (((1U << GLB_SWRST_S19_LEN) - 1) << GLB_SWRST_S19_POS)
+ (((1 << GLB_SWRST_S19_LEN) - 1) << GLB_SWRST_S19_POS)
#define GLB_SWRST_S19_UMSK \
- (~(((1U << GLB_SWRST_S19_LEN) - 1) << GLB_SWRST_S19_POS))
+ (~(((1 << GLB_SWRST_S19_LEN) - 1) << GLB_SWRST_S19_POS))
#define GLB_SWRST_S1A GLB_SWRST_S1A
-#define GLB_SWRST_S1A_POS (10U)
-#define GLB_SWRST_S1A_LEN (1U)
+#define GLB_SWRST_S1A_POS (10)
+#define GLB_SWRST_S1A_LEN (1)
#define GLB_SWRST_S1A_MSK \
- (((1U << GLB_SWRST_S1A_LEN) - 1) << GLB_SWRST_S1A_POS)
+ (((1 << GLB_SWRST_S1A_LEN) - 1) << GLB_SWRST_S1A_POS)
#define GLB_SWRST_S1A_UMSK \
- (~(((1U << GLB_SWRST_S1A_LEN) - 1) << GLB_SWRST_S1A_POS))
+ (~(((1 << GLB_SWRST_S1A_LEN) - 1) << GLB_SWRST_S1A_POS))
#define GLB_SWRST_S1B GLB_SWRST_S1B
-#define GLB_SWRST_S1B_POS (11U)
-#define GLB_SWRST_S1B_LEN (1U)
+#define GLB_SWRST_S1B_POS (11)
+#define GLB_SWRST_S1B_LEN (1)
#define GLB_SWRST_S1B_MSK \
- (((1U << GLB_SWRST_S1B_LEN) - 1) << GLB_SWRST_S1B_POS)
+ (((1 << GLB_SWRST_S1B_LEN) - 1) << GLB_SWRST_S1B_POS)
#define GLB_SWRST_S1B_UMSK \
- (~(((1U << GLB_SWRST_S1B_LEN) - 1) << GLB_SWRST_S1B_POS))
+ (~(((1 << GLB_SWRST_S1B_LEN) - 1) << GLB_SWRST_S1B_POS))
#define GLB_SWRST_S1C GLB_SWRST_S1C
-#define GLB_SWRST_S1C_POS (12U)
-#define GLB_SWRST_S1C_LEN (1U)
+#define GLB_SWRST_S1C_POS (12)
+#define GLB_SWRST_S1C_LEN (1)
#define GLB_SWRST_S1C_MSK \
- (((1U << GLB_SWRST_S1C_LEN) - 1) << GLB_SWRST_S1C_POS)
+ (((1 << GLB_SWRST_S1C_LEN) - 1) << GLB_SWRST_S1C_POS)
#define GLB_SWRST_S1C_UMSK \
- (~(((1U << GLB_SWRST_S1C_LEN) - 1) << GLB_SWRST_S1C_POS))
+ (~(((1 << GLB_SWRST_S1C_LEN) - 1) << GLB_SWRST_S1C_POS))
#define GLB_SWRST_S1D GLB_SWRST_S1D
-#define GLB_SWRST_S1D_POS (13U)
-#define GLB_SWRST_S1D_LEN (1U)
+#define GLB_SWRST_S1D_POS (13)
+#define GLB_SWRST_S1D_LEN (1)
#define GLB_SWRST_S1D_MSK \
- (((1U << GLB_SWRST_S1D_LEN) - 1) << GLB_SWRST_S1D_POS)
+ (((1 << GLB_SWRST_S1D_LEN) - 1) << GLB_SWRST_S1D_POS)
#define GLB_SWRST_S1D_UMSK \
- (~(((1U << GLB_SWRST_S1D_LEN) - 1) << GLB_SWRST_S1D_POS))
+ (~(((1 << GLB_SWRST_S1D_LEN) - 1) << GLB_SWRST_S1D_POS))
#define GLB_SWRST_S1E GLB_SWRST_S1E
-#define GLB_SWRST_S1E_POS (14U)
-#define GLB_SWRST_S1E_LEN (1U)
+#define GLB_SWRST_S1E_POS (14)
+#define GLB_SWRST_S1E_LEN (1)
#define GLB_SWRST_S1E_MSK \
- (((1U << GLB_SWRST_S1E_LEN) - 1) << GLB_SWRST_S1E_POS)
+ (((1 << GLB_SWRST_S1E_LEN) - 1) << GLB_SWRST_S1E_POS)
#define GLB_SWRST_S1E_UMSK \
- (~(((1U << GLB_SWRST_S1E_LEN) - 1) << GLB_SWRST_S1E_POS))
+ (~(((1 << GLB_SWRST_S1E_LEN) - 1) << GLB_SWRST_S1E_POS))
#define GLB_SWRST_S1F GLB_SWRST_S1F
-#define GLB_SWRST_S1F_POS (15U)
-#define GLB_SWRST_S1F_LEN (1U)
+#define GLB_SWRST_S1F_POS (15)
+#define GLB_SWRST_S1F_LEN (1)
#define GLB_SWRST_S1F_MSK \
- (((1U << GLB_SWRST_S1F_LEN) - 1) << GLB_SWRST_S1F_POS)
+ (((1 << GLB_SWRST_S1F_LEN) - 1) << GLB_SWRST_S1F_POS)
#define GLB_SWRST_S1F_UMSK \
- (~(((1U << GLB_SWRST_S1F_LEN) - 1) << GLB_SWRST_S1F_POS))
+ (~(((1 << GLB_SWRST_S1F_LEN) - 1) << GLB_SWRST_S1F_POS))
#define GLB_SWRST_S1A0 GLB_SWRST_S1A0
-#define GLB_SWRST_S1A0_POS (16U)
-#define GLB_SWRST_S1A0_LEN (1U)
+#define GLB_SWRST_S1A0_POS (16)
+#define GLB_SWRST_S1A0_LEN (1)
#define GLB_SWRST_S1A0_MSK \
- (((1U << GLB_SWRST_S1A0_LEN) - 1) << GLB_SWRST_S1A0_POS)
+ (((1 << GLB_SWRST_S1A0_LEN) - 1) << GLB_SWRST_S1A0_POS)
#define GLB_SWRST_S1A0_UMSK \
- (~(((1U << GLB_SWRST_S1A0_LEN) - 1) << GLB_SWRST_S1A0_POS))
+ (~(((1 << GLB_SWRST_S1A0_LEN) - 1) << GLB_SWRST_S1A0_POS))
#define GLB_SWRST_S1A1 GLB_SWRST_S1A1
-#define GLB_SWRST_S1A1_POS (17U)
-#define GLB_SWRST_S1A1_LEN (1U)
+#define GLB_SWRST_S1A1_POS (17)
+#define GLB_SWRST_S1A1_LEN (1)
#define GLB_SWRST_S1A1_MSK \
- (((1U << GLB_SWRST_S1A1_LEN) - 1) << GLB_SWRST_S1A1_POS)
+ (((1 << GLB_SWRST_S1A1_LEN) - 1) << GLB_SWRST_S1A1_POS)
#define GLB_SWRST_S1A1_UMSK \
- (~(((1U << GLB_SWRST_S1A1_LEN) - 1) << GLB_SWRST_S1A1_POS))
+ (~(((1 << GLB_SWRST_S1A1_LEN) - 1) << GLB_SWRST_S1A1_POS))
#define GLB_SWRST_S1A2 GLB_SWRST_S1A2
-#define GLB_SWRST_S1A2_POS (18U)
-#define GLB_SWRST_S1A2_LEN (1U)
+#define GLB_SWRST_S1A2_POS (18)
+#define GLB_SWRST_S1A2_LEN (1)
#define GLB_SWRST_S1A2_MSK \
- (((1U << GLB_SWRST_S1A2_LEN) - 1) << GLB_SWRST_S1A2_POS)
+ (((1 << GLB_SWRST_S1A2_LEN) - 1) << GLB_SWRST_S1A2_POS)
#define GLB_SWRST_S1A2_UMSK \
- (~(((1U << GLB_SWRST_S1A2_LEN) - 1) << GLB_SWRST_S1A2_POS))
+ (~(((1 << GLB_SWRST_S1A2_LEN) - 1) << GLB_SWRST_S1A2_POS))
#define GLB_SWRST_S1A3 GLB_SWRST_S1A3
-#define GLB_SWRST_S1A3_POS (19U)
-#define GLB_SWRST_S1A3_LEN (1U)
+#define GLB_SWRST_S1A3_POS (19)
+#define GLB_SWRST_S1A3_LEN (1)
#define GLB_SWRST_S1A3_MSK \
- (((1U << GLB_SWRST_S1A3_LEN) - 1) << GLB_SWRST_S1A3_POS)
+ (((1 << GLB_SWRST_S1A3_LEN) - 1) << GLB_SWRST_S1A3_POS)
#define GLB_SWRST_S1A3_UMSK \
- (~(((1U << GLB_SWRST_S1A3_LEN) - 1) << GLB_SWRST_S1A3_POS))
+ (~(((1 << GLB_SWRST_S1A3_LEN) - 1) << GLB_SWRST_S1A3_POS))
#define GLB_SWRST_S1A4 GLB_SWRST_S1A4
-#define GLB_SWRST_S1A4_POS (20U)
-#define GLB_SWRST_S1A4_LEN (1U)
+#define GLB_SWRST_S1A4_POS (20)
+#define GLB_SWRST_S1A4_LEN (1)
#define GLB_SWRST_S1A4_MSK \
- (((1U << GLB_SWRST_S1A4_LEN) - 1) << GLB_SWRST_S1A4_POS)
+ (((1 << GLB_SWRST_S1A4_LEN) - 1) << GLB_SWRST_S1A4_POS)
#define GLB_SWRST_S1A4_UMSK \
- (~(((1U << GLB_SWRST_S1A4_LEN) - 1) << GLB_SWRST_S1A4_POS))
+ (~(((1 << GLB_SWRST_S1A4_LEN) - 1) << GLB_SWRST_S1A4_POS))
#define GLB_SWRST_S1A5 GLB_SWRST_S1A5
-#define GLB_SWRST_S1A5_POS (21U)
-#define GLB_SWRST_S1A5_LEN (1U)
+#define GLB_SWRST_S1A5_POS (21)
+#define GLB_SWRST_S1A5_LEN (1)
#define GLB_SWRST_S1A5_MSK \
- (((1U << GLB_SWRST_S1A5_LEN) - 1) << GLB_SWRST_S1A5_POS)
+ (((1 << GLB_SWRST_S1A5_LEN) - 1) << GLB_SWRST_S1A5_POS)
#define GLB_SWRST_S1A5_UMSK \
- (~(((1U << GLB_SWRST_S1A5_LEN) - 1) << GLB_SWRST_S1A5_POS))
+ (~(((1 << GLB_SWRST_S1A5_LEN) - 1) << GLB_SWRST_S1A5_POS))
#define GLB_SWRST_S1A6 GLB_SWRST_S1A6
-#define GLB_SWRST_S1A6_POS (22U)
-#define GLB_SWRST_S1A6_LEN (1U)
+#define GLB_SWRST_S1A6_POS (22)
+#define GLB_SWRST_S1A6_LEN (1)
#define GLB_SWRST_S1A6_MSK \
- (((1U << GLB_SWRST_S1A6_LEN) - 1) << GLB_SWRST_S1A6_POS)
+ (((1 << GLB_SWRST_S1A6_LEN) - 1) << GLB_SWRST_S1A6_POS)
#define GLB_SWRST_S1A6_UMSK \
- (~(((1U << GLB_SWRST_S1A6_LEN) - 1) << GLB_SWRST_S1A6_POS))
+ (~(((1 << GLB_SWRST_S1A6_LEN) - 1) << GLB_SWRST_S1A6_POS))
#define GLB_SWRST_S1A7 GLB_SWRST_S1A7
-#define GLB_SWRST_S1A7_POS (23U)
-#define GLB_SWRST_S1A7_LEN (1U)
+#define GLB_SWRST_S1A7_POS (23)
+#define GLB_SWRST_S1A7_LEN (1)
#define GLB_SWRST_S1A7_MSK \
- (((1U << GLB_SWRST_S1A7_LEN) - 1) << GLB_SWRST_S1A7_POS)
+ (((1 << GLB_SWRST_S1A7_LEN) - 1) << GLB_SWRST_S1A7_POS)
#define GLB_SWRST_S1A7_UMSK \
- (~(((1U << GLB_SWRST_S1A7_LEN) - 1) << GLB_SWRST_S1A7_POS))
+ (~(((1 << GLB_SWRST_S1A7_LEN) - 1) << GLB_SWRST_S1A7_POS))
/* 0x18 : swrst_cfg2 */
#define GLB_SWRST_CFG2_OFFSET (0x18)
#define GLB_REG_CTRL_PWRON_RST GLB_REG_CTRL_PWRON_RST
-#define GLB_REG_CTRL_PWRON_RST_POS (0U)
-#define GLB_REG_CTRL_PWRON_RST_LEN (1U)
+#define GLB_REG_CTRL_PWRON_RST_POS (0)
+#define GLB_REG_CTRL_PWRON_RST_LEN (1)
#define GLB_REG_CTRL_PWRON_RST_MSK \
- (((1U << GLB_REG_CTRL_PWRON_RST_LEN) - 1) << GLB_REG_CTRL_PWRON_RST_POS)
+ (((1 << GLB_REG_CTRL_PWRON_RST_LEN) - 1) << GLB_REG_CTRL_PWRON_RST_POS)
#define GLB_REG_CTRL_PWRON_RST_UMSK \
- (~(((1U << GLB_REG_CTRL_PWRON_RST_LEN) - 1) << GLB_REG_CTRL_PWRON_RST_POS))
+ (~(((1 << GLB_REG_CTRL_PWRON_RST_LEN) - 1) << GLB_REG_CTRL_PWRON_RST_POS))
#define GLB_REG_CTRL_CPU_RESET GLB_REG_CTRL_CPU_RESET
-#define GLB_REG_CTRL_CPU_RESET_POS (1U)
-#define GLB_REG_CTRL_CPU_RESET_LEN (1U)
+#define GLB_REG_CTRL_CPU_RESET_POS (1)
+#define GLB_REG_CTRL_CPU_RESET_LEN (1)
#define GLB_REG_CTRL_CPU_RESET_MSK \
- (((1U << GLB_REG_CTRL_CPU_RESET_LEN) - 1) << GLB_REG_CTRL_CPU_RESET_POS)
+ (((1 << GLB_REG_CTRL_CPU_RESET_LEN) - 1) << GLB_REG_CTRL_CPU_RESET_POS)
#define GLB_REG_CTRL_CPU_RESET_UMSK \
- (~(((1U << GLB_REG_CTRL_CPU_RESET_LEN) - 1) << GLB_REG_CTRL_CPU_RESET_POS))
+ (~(((1 << GLB_REG_CTRL_CPU_RESET_LEN) - 1) << GLB_REG_CTRL_CPU_RESET_POS))
#define GLB_REG_CTRL_SYS_RESET GLB_REG_CTRL_SYS_RESET
-#define GLB_REG_CTRL_SYS_RESET_POS (2U)
-#define GLB_REG_CTRL_SYS_RESET_LEN (1U)
+#define GLB_REG_CTRL_SYS_RESET_POS (2)
+#define GLB_REG_CTRL_SYS_RESET_LEN (1)
#define GLB_REG_CTRL_SYS_RESET_MSK \
- (((1U << GLB_REG_CTRL_SYS_RESET_LEN) - 1) << GLB_REG_CTRL_SYS_RESET_POS)
+ (((1 << GLB_REG_CTRL_SYS_RESET_LEN) - 1) << GLB_REG_CTRL_SYS_RESET_POS)
#define GLB_REG_CTRL_SYS_RESET_UMSK \
- (~(((1U << GLB_REG_CTRL_SYS_RESET_LEN) - 1) << GLB_REG_CTRL_SYS_RESET_POS))
+ (~(((1 << GLB_REG_CTRL_SYS_RESET_LEN) - 1) << GLB_REG_CTRL_SYS_RESET_POS))
#define GLB_REG_CTRL_RESET_DUMMY GLB_REG_CTRL_RESET_DUMMY
-#define GLB_REG_CTRL_RESET_DUMMY_POS (4U)
-#define GLB_REG_CTRL_RESET_DUMMY_LEN (4U)
+#define GLB_REG_CTRL_RESET_DUMMY_POS (4)
+#define GLB_REG_CTRL_RESET_DUMMY_LEN (4)
#define GLB_REG_CTRL_RESET_DUMMY_MSK \
- (((1U << GLB_REG_CTRL_RESET_DUMMY_LEN) - 1) << GLB_REG_CTRL_RESET_DUMMY_POS)
+ (((1 << GLB_REG_CTRL_RESET_DUMMY_LEN) - 1) << GLB_REG_CTRL_RESET_DUMMY_POS)
#define GLB_REG_CTRL_RESET_DUMMY_UMSK \
- (~(((1U << GLB_REG_CTRL_RESET_DUMMY_LEN) - 1) \
+ (~(((1 << GLB_REG_CTRL_RESET_DUMMY_LEN) - 1) \
<< GLB_REG_CTRL_RESET_DUMMY_POS))
#define GLB_PKA_CLK_SEL GLB_PKA_CLK_SEL
-#define GLB_PKA_CLK_SEL_POS (24U)
-#define GLB_PKA_CLK_SEL_LEN (1U)
+#define GLB_PKA_CLK_SEL_POS (24)
+#define GLB_PKA_CLK_SEL_LEN (1)
#define GLB_PKA_CLK_SEL_MSK \
- (((1U << GLB_PKA_CLK_SEL_LEN) - 1) << GLB_PKA_CLK_SEL_POS)
+ (((1 << GLB_PKA_CLK_SEL_LEN) - 1) << GLB_PKA_CLK_SEL_POS)
#define GLB_PKA_CLK_SEL_UMSK \
- (~(((1U << GLB_PKA_CLK_SEL_LEN) - 1) << GLB_PKA_CLK_SEL_POS))
+ (~(((1 << GLB_PKA_CLK_SEL_LEN) - 1) << GLB_PKA_CLK_SEL_POS))
/* 0x1C : swrst_cfg3 */
@@ -497,39 +500,39 @@
#define GLB_CGEN_CFG0_OFFSET (0x20)
#define GLB_CGEN_M GLB_CGEN_M
-#define GLB_CGEN_M_POS (0U)
-#define GLB_CGEN_M_LEN (8U)
-#define GLB_CGEN_M_MSK (((1U << GLB_CGEN_M_LEN) - 1) << GLB_CGEN_M_POS)
-#define GLB_CGEN_M_UMSK (~(((1U << GLB_CGEN_M_LEN) - 1) << GLB_CGEN_M_POS))
+#define GLB_CGEN_M_POS (0)
+#define GLB_CGEN_M_LEN (8)
+#define GLB_CGEN_M_MSK (((1 << GLB_CGEN_M_LEN) - 1) << GLB_CGEN_M_POS)
+#define GLB_CGEN_M_UMSK (~(((1 << GLB_CGEN_M_LEN) - 1) << GLB_CGEN_M_POS))
/* 0x24 : cgen_cfg1 */
#define GLB_CGEN_CFG1_OFFSET (0x24)
#define GLB_CGEN_S1 GLB_CGEN_S1
-#define GLB_CGEN_S1_POS (0U)
-#define GLB_CGEN_S1_LEN (16U)
-#define GLB_CGEN_S1_MSK (((1U << GLB_CGEN_S1_LEN) - 1) << GLB_CGEN_S1_POS)
-#define GLB_CGEN_S1_UMSK (~(((1U << GLB_CGEN_S1_LEN) - 1) << GLB_CGEN_S1_POS))
+#define GLB_CGEN_S1_POS (0)
+#define GLB_CGEN_S1_LEN (16)
+#define GLB_CGEN_S1_MSK (((1 << GLB_CGEN_S1_LEN) - 1) << GLB_CGEN_S1_POS)
+#define GLB_CGEN_S1_UMSK (~(((1 << GLB_CGEN_S1_LEN) - 1) << GLB_CGEN_S1_POS))
#define GLB_CGEN_S1A GLB_CGEN_S1A
-#define GLB_CGEN_S1A_POS (16U)
-#define GLB_CGEN_S1A_LEN (8U)
-#define GLB_CGEN_S1A_MSK (((1U << GLB_CGEN_S1A_LEN) - 1) << GLB_CGEN_S1A_POS)
+#define GLB_CGEN_S1A_POS (16)
+#define GLB_CGEN_S1A_LEN (8)
+#define GLB_CGEN_S1A_MSK (((1 << GLB_CGEN_S1A_LEN) - 1) << GLB_CGEN_S1A_POS)
#define GLB_CGEN_S1A_UMSK \
- (~(((1U << GLB_CGEN_S1A_LEN) - 1) << GLB_CGEN_S1A_POS))
+ (~(((1 << GLB_CGEN_S1A_LEN) - 1) << GLB_CGEN_S1A_POS))
/* 0x28 : cgen_cfg2 */
#define GLB_CGEN_CFG2_OFFSET (0x28)
#define GLB_CGEN_S2 GLB_CGEN_S2
-#define GLB_CGEN_S2_POS (0U)
-#define GLB_CGEN_S2_LEN (1U)
-#define GLB_CGEN_S2_MSK (((1U << GLB_CGEN_S2_LEN) - 1) << GLB_CGEN_S2_POS)
-#define GLB_CGEN_S2_UMSK (~(((1U << GLB_CGEN_S2_LEN) - 1) << GLB_CGEN_S2_POS))
+#define GLB_CGEN_S2_POS (0)
+#define GLB_CGEN_S2_LEN (1)
+#define GLB_CGEN_S2_MSK (((1 << GLB_CGEN_S2_LEN) - 1) << GLB_CGEN_S2_POS)
+#define GLB_CGEN_S2_UMSK (~(((1 << GLB_CGEN_S2_LEN) - 1) << GLB_CGEN_S2_POS))
#define GLB_CGEN_S3 GLB_CGEN_S3
-#define GLB_CGEN_S3_POS (4U)
-#define GLB_CGEN_S3_LEN (1U)
-#define GLB_CGEN_S3_MSK (((1U << GLB_CGEN_S3_LEN) - 1) << GLB_CGEN_S3_POS)
-#define GLB_CGEN_S3_UMSK (~(((1U << GLB_CGEN_S3_LEN) - 1) << GLB_CGEN_S3_POS))
+#define GLB_CGEN_S3_POS (4)
+#define GLB_CGEN_S3_LEN (1)
+#define GLB_CGEN_S3_MSK (((1 << GLB_CGEN_S3_LEN) - 1) << GLB_CGEN_S3_POS)
+#define GLB_CGEN_S3_UMSK (~(((1 << GLB_CGEN_S3_LEN) - 1) << GLB_CGEN_S3_POS))
/* 0x2C : cgen_cfg3 */
@@ -539,236 +542,235 @@
#define GLB_MBIST_CTL_OFFSET (0x30)
#define GLB_IROM_MBIST_MODE GLB_IROM_MBIST_MODE
-#define GLB_IROM_MBIST_MODE_POS (0U)
-#define GLB_IROM_MBIST_MODE_LEN (1U)
+#define GLB_IROM_MBIST_MODE_POS (0)
+#define GLB_IROM_MBIST_MODE_LEN (1)
#define GLB_IROM_MBIST_MODE_MSK \
- (((1U << GLB_IROM_MBIST_MODE_LEN) - 1) << GLB_IROM_MBIST_MODE_POS)
+ (((1 << GLB_IROM_MBIST_MODE_LEN) - 1) << GLB_IROM_MBIST_MODE_POS)
#define GLB_IROM_MBIST_MODE_UMSK \
- (~(((1U << GLB_IROM_MBIST_MODE_LEN) - 1) << GLB_IROM_MBIST_MODE_POS))
+ (~(((1 << GLB_IROM_MBIST_MODE_LEN) - 1) << GLB_IROM_MBIST_MODE_POS))
#define GLB_HSRAM_MBIST_MODE GLB_HSRAM_MBIST_MODE
-#define GLB_HSRAM_MBIST_MODE_POS (1U)
-#define GLB_HSRAM_MBIST_MODE_LEN (1U)
+#define GLB_HSRAM_MBIST_MODE_POS (1)
+#define GLB_HSRAM_MBIST_MODE_LEN (1)
#define GLB_HSRAM_MBIST_MODE_MSK \
- (((1U << GLB_HSRAM_MBIST_MODE_LEN) - 1) << GLB_HSRAM_MBIST_MODE_POS)
+ (((1 << GLB_HSRAM_MBIST_MODE_LEN) - 1) << GLB_HSRAM_MBIST_MODE_POS)
#define GLB_HSRAM_MBIST_MODE_UMSK \
- (~(((1U << GLB_HSRAM_MBIST_MODE_LEN) - 1) << GLB_HSRAM_MBIST_MODE_POS))
+ (~(((1 << GLB_HSRAM_MBIST_MODE_LEN) - 1) << GLB_HSRAM_MBIST_MODE_POS))
#define GLB_TAG_MBIST_MODE GLB_TAG_MBIST_MODE
-#define GLB_TAG_MBIST_MODE_POS (2U)
-#define GLB_TAG_MBIST_MODE_LEN (1U)
+#define GLB_TAG_MBIST_MODE_POS (2)
+#define GLB_TAG_MBIST_MODE_LEN (1)
#define GLB_TAG_MBIST_MODE_MSK \
- (((1U << GLB_TAG_MBIST_MODE_LEN) - 1) << GLB_TAG_MBIST_MODE_POS)
+ (((1 << GLB_TAG_MBIST_MODE_LEN) - 1) << GLB_TAG_MBIST_MODE_POS)
#define GLB_TAG_MBIST_MODE_UMSK \
- (~(((1U << GLB_TAG_MBIST_MODE_LEN) - 1) << GLB_TAG_MBIST_MODE_POS))
+ (~(((1 << GLB_TAG_MBIST_MODE_LEN) - 1) << GLB_TAG_MBIST_MODE_POS))
#define GLB_OCRAM_MBIST_MODE GLB_OCRAM_MBIST_MODE
-#define GLB_OCRAM_MBIST_MODE_POS (3U)
-#define GLB_OCRAM_MBIST_MODE_LEN (1U)
+#define GLB_OCRAM_MBIST_MODE_POS (3)
+#define GLB_OCRAM_MBIST_MODE_LEN (1)
#define GLB_OCRAM_MBIST_MODE_MSK \
- (((1U << GLB_OCRAM_MBIST_MODE_LEN) - 1) << GLB_OCRAM_MBIST_MODE_POS)
+ (((1 << GLB_OCRAM_MBIST_MODE_LEN) - 1) << GLB_OCRAM_MBIST_MODE_POS)
#define GLB_OCRAM_MBIST_MODE_UMSK \
- (~(((1U << GLB_OCRAM_MBIST_MODE_LEN) - 1) << GLB_OCRAM_MBIST_MODE_POS))
+ (~(((1 << GLB_OCRAM_MBIST_MODE_LEN) - 1) << GLB_OCRAM_MBIST_MODE_POS))
#define GLB_WIFI_MBIST_MODE GLB_WIFI_MBIST_MODE
-#define GLB_WIFI_MBIST_MODE_POS (4U)
-#define GLB_WIFI_MBIST_MODE_LEN (1U)
+#define GLB_WIFI_MBIST_MODE_POS (4)
+#define GLB_WIFI_MBIST_MODE_LEN (1)
#define GLB_WIFI_MBIST_MODE_MSK \
- (((1U << GLB_WIFI_MBIST_MODE_LEN) - 1) << GLB_WIFI_MBIST_MODE_POS)
+ (((1 << GLB_WIFI_MBIST_MODE_LEN) - 1) << GLB_WIFI_MBIST_MODE_POS)
#define GLB_WIFI_MBIST_MODE_UMSK \
- (~(((1U << GLB_WIFI_MBIST_MODE_LEN) - 1) << GLB_WIFI_MBIST_MODE_POS))
+ (~(((1 << GLB_WIFI_MBIST_MODE_LEN) - 1) << GLB_WIFI_MBIST_MODE_POS))
#define GLB_REG_MBIST_RST_N GLB_REG_MBIST_RST_N
-#define GLB_REG_MBIST_RST_N_POS (31U)
-#define GLB_REG_MBIST_RST_N_LEN (1U)
+#define GLB_REG_MBIST_RST_N_POS (31)
+#define GLB_REG_MBIST_RST_N_LEN (1)
#define GLB_REG_MBIST_RST_N_MSK \
- (((1U << GLB_REG_MBIST_RST_N_LEN) - 1) << GLB_REG_MBIST_RST_N_POS)
+ (((1 << GLB_REG_MBIST_RST_N_LEN) - 1) << GLB_REG_MBIST_RST_N_POS)
#define GLB_REG_MBIST_RST_N_UMSK \
- (~(((1U << GLB_REG_MBIST_RST_N_LEN) - 1) << GLB_REG_MBIST_RST_N_POS))
+ (~(((1 << GLB_REG_MBIST_RST_N_LEN) - 1) << GLB_REG_MBIST_RST_N_POS))
/* 0x34 : MBIST_STAT */
#define GLB_MBIST_STAT_OFFSET (0x34)
#define GLB_IROM_MBIST_DONE GLB_IROM_MBIST_DONE
-#define GLB_IROM_MBIST_DONE_POS (0U)
-#define GLB_IROM_MBIST_DONE_LEN (1U)
+#define GLB_IROM_MBIST_DONE_POS (0)
+#define GLB_IROM_MBIST_DONE_LEN (1)
#define GLB_IROM_MBIST_DONE_MSK \
- (((1U << GLB_IROM_MBIST_DONE_LEN) - 1) << GLB_IROM_MBIST_DONE_POS)
+ (((1 << GLB_IROM_MBIST_DONE_LEN) - 1) << GLB_IROM_MBIST_DONE_POS)
#define GLB_IROM_MBIST_DONE_UMSK \
- (~(((1U << GLB_IROM_MBIST_DONE_LEN) - 1) << GLB_IROM_MBIST_DONE_POS))
+ (~(((1 << GLB_IROM_MBIST_DONE_LEN) - 1) << GLB_IROM_MBIST_DONE_POS))
#define GLB_HSRAM_MBIST_DONE GLB_HSRAM_MBIST_DONE
-#define GLB_HSRAM_MBIST_DONE_POS (1U)
-#define GLB_HSRAM_MBIST_DONE_LEN (1U)
+#define GLB_HSRAM_MBIST_DONE_POS (1)
+#define GLB_HSRAM_MBIST_DONE_LEN (1)
#define GLB_HSRAM_MBIST_DONE_MSK \
- (((1U << GLB_HSRAM_MBIST_DONE_LEN) - 1) << GLB_HSRAM_MBIST_DONE_POS)
+ (((1 << GLB_HSRAM_MBIST_DONE_LEN) - 1) << GLB_HSRAM_MBIST_DONE_POS)
#define GLB_HSRAM_MBIST_DONE_UMSK \
- (~(((1U << GLB_HSRAM_MBIST_DONE_LEN) - 1) << GLB_HSRAM_MBIST_DONE_POS))
+ (~(((1 << GLB_HSRAM_MBIST_DONE_LEN) - 1) << GLB_HSRAM_MBIST_DONE_POS))
#define GLB_TAG_MBIST_DONE GLB_TAG_MBIST_DONE
-#define GLB_TAG_MBIST_DONE_POS (2U)
-#define GLB_TAG_MBIST_DONE_LEN (1U)
+#define GLB_TAG_MBIST_DONE_POS (2)
+#define GLB_TAG_MBIST_DONE_LEN (1)
#define GLB_TAG_MBIST_DONE_MSK \
- (((1U << GLB_TAG_MBIST_DONE_LEN) - 1) << GLB_TAG_MBIST_DONE_POS)
+ (((1 << GLB_TAG_MBIST_DONE_LEN) - 1) << GLB_TAG_MBIST_DONE_POS)
#define GLB_TAG_MBIST_DONE_UMSK \
- (~(((1U << GLB_TAG_MBIST_DONE_LEN) - 1) << GLB_TAG_MBIST_DONE_POS))
+ (~(((1 << GLB_TAG_MBIST_DONE_LEN) - 1) << GLB_TAG_MBIST_DONE_POS))
#define GLB_OCRAM_MBIST_DONE GLB_OCRAM_MBIST_DONE
-#define GLB_OCRAM_MBIST_DONE_POS (3U)
-#define GLB_OCRAM_MBIST_DONE_LEN (1U)
+#define GLB_OCRAM_MBIST_DONE_POS (3)
+#define GLB_OCRAM_MBIST_DONE_LEN (1)
#define GLB_OCRAM_MBIST_DONE_MSK \
- (((1U << GLB_OCRAM_MBIST_DONE_LEN) - 1) << GLB_OCRAM_MBIST_DONE_POS)
+ (((1 << GLB_OCRAM_MBIST_DONE_LEN) - 1) << GLB_OCRAM_MBIST_DONE_POS)
#define GLB_OCRAM_MBIST_DONE_UMSK \
- (~(((1U << GLB_OCRAM_MBIST_DONE_LEN) - 1) << GLB_OCRAM_MBIST_DONE_POS))
+ (~(((1 << GLB_OCRAM_MBIST_DONE_LEN) - 1) << GLB_OCRAM_MBIST_DONE_POS))
#define GLB_WIFI_MBIST_DONE GLB_WIFI_MBIST_DONE
-#define GLB_WIFI_MBIST_DONE_POS (4U)
-#define GLB_WIFI_MBIST_DONE_LEN (1U)
+#define GLB_WIFI_MBIST_DONE_POS (4)
+#define GLB_WIFI_MBIST_DONE_LEN (1)
#define GLB_WIFI_MBIST_DONE_MSK \
- (((1U << GLB_WIFI_MBIST_DONE_LEN) - 1) << GLB_WIFI_MBIST_DONE_POS)
+ (((1 << GLB_WIFI_MBIST_DONE_LEN) - 1) << GLB_WIFI_MBIST_DONE_POS)
#define GLB_WIFI_MBIST_DONE_UMSK \
- (~(((1U << GLB_WIFI_MBIST_DONE_LEN) - 1) << GLB_WIFI_MBIST_DONE_POS))
+ (~(((1 << GLB_WIFI_MBIST_DONE_LEN) - 1) << GLB_WIFI_MBIST_DONE_POS))
#define GLB_IROM_MBIST_FAIL GLB_IROM_MBIST_FAIL
-#define GLB_IROM_MBIST_FAIL_POS (16U)
-#define GLB_IROM_MBIST_FAIL_LEN (1U)
+#define GLB_IROM_MBIST_FAIL_POS (16)
+#define GLB_IROM_MBIST_FAIL_LEN (1)
#define GLB_IROM_MBIST_FAIL_MSK \
- (((1U << GLB_IROM_MBIST_FAIL_LEN) - 1) << GLB_IROM_MBIST_FAIL_POS)
+ (((1 << GLB_IROM_MBIST_FAIL_LEN) - 1) << GLB_IROM_MBIST_FAIL_POS)
#define GLB_IROM_MBIST_FAIL_UMSK \
- (~(((1U << GLB_IROM_MBIST_FAIL_LEN) - 1) << GLB_IROM_MBIST_FAIL_POS))
+ (~(((1 << GLB_IROM_MBIST_FAIL_LEN) - 1) << GLB_IROM_MBIST_FAIL_POS))
#define GLB_HSRAM_MBIST_FAIL GLB_HSRAM_MBIST_FAIL
-#define GLB_HSRAM_MBIST_FAIL_POS (17U)
-#define GLB_HSRAM_MBIST_FAIL_LEN (1U)
+#define GLB_HSRAM_MBIST_FAIL_POS (17)
+#define GLB_HSRAM_MBIST_FAIL_LEN (1)
#define GLB_HSRAM_MBIST_FAIL_MSK \
- (((1U << GLB_HSRAM_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_MBIST_FAIL_POS)
+ (((1 << GLB_HSRAM_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_MBIST_FAIL_POS)
#define GLB_HSRAM_MBIST_FAIL_UMSK \
- (~(((1U << GLB_HSRAM_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_MBIST_FAIL_POS))
+ (~(((1 << GLB_HSRAM_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_MBIST_FAIL_POS))
#define GLB_TAG_MBIST_FAIL GLB_TAG_MBIST_FAIL
-#define GLB_TAG_MBIST_FAIL_POS (18U)
-#define GLB_TAG_MBIST_FAIL_LEN (1U)
+#define GLB_TAG_MBIST_FAIL_POS (18)
+#define GLB_TAG_MBIST_FAIL_LEN (1)
#define GLB_TAG_MBIST_FAIL_MSK \
- (((1U << GLB_TAG_MBIST_FAIL_LEN) - 1) << GLB_TAG_MBIST_FAIL_POS)
+ (((1 << GLB_TAG_MBIST_FAIL_LEN) - 1) << GLB_TAG_MBIST_FAIL_POS)
#define GLB_TAG_MBIST_FAIL_UMSK \
- (~(((1U << GLB_TAG_MBIST_FAIL_LEN) - 1) << GLB_TAG_MBIST_FAIL_POS))
+ (~(((1 << GLB_TAG_MBIST_FAIL_LEN) - 1) << GLB_TAG_MBIST_FAIL_POS))
#define GLB_OCRAM_MBIST_FAIL GLB_OCRAM_MBIST_FAIL
-#define GLB_OCRAM_MBIST_FAIL_POS (19U)
-#define GLB_OCRAM_MBIST_FAIL_LEN (1U)
+#define GLB_OCRAM_MBIST_FAIL_POS (19)
+#define GLB_OCRAM_MBIST_FAIL_LEN (1)
#define GLB_OCRAM_MBIST_FAIL_MSK \
- (((1U << GLB_OCRAM_MBIST_FAIL_LEN) - 1) << GLB_OCRAM_MBIST_FAIL_POS)
+ (((1 << GLB_OCRAM_MBIST_FAIL_LEN) - 1) << GLB_OCRAM_MBIST_FAIL_POS)
#define GLB_OCRAM_MBIST_FAIL_UMSK \
- (~(((1U << GLB_OCRAM_MBIST_FAIL_LEN) - 1) << GLB_OCRAM_MBIST_FAIL_POS))
+ (~(((1 << GLB_OCRAM_MBIST_FAIL_LEN) - 1) << GLB_OCRAM_MBIST_FAIL_POS))
#define GLB_WIFI_MBIST_FAIL GLB_WIFI_MBIST_FAIL
-#define GLB_WIFI_MBIST_FAIL_POS (20U)
-#define GLB_WIFI_MBIST_FAIL_LEN (1U)
+#define GLB_WIFI_MBIST_FAIL_POS (20)
+#define GLB_WIFI_MBIST_FAIL_LEN (1)
#define GLB_WIFI_MBIST_FAIL_MSK \
- (((1U << GLB_WIFI_MBIST_FAIL_LEN) - 1) << GLB_WIFI_MBIST_FAIL_POS)
+ (((1 << GLB_WIFI_MBIST_FAIL_LEN) - 1) << GLB_WIFI_MBIST_FAIL_POS)
#define GLB_WIFI_MBIST_FAIL_UMSK \
- (~(((1U << GLB_WIFI_MBIST_FAIL_LEN) - 1) << GLB_WIFI_MBIST_FAIL_POS))
+ (~(((1 << GLB_WIFI_MBIST_FAIL_LEN) - 1) << GLB_WIFI_MBIST_FAIL_POS))
/* 0x50 : bmx_cfg1 */
#define GLB_BMX_CFG1_OFFSET (0x50)
#define GLB_BMX_TIMEOUT_EN GLB_BMX_TIMEOUT_EN
-#define GLB_BMX_TIMEOUT_EN_POS (0U)
-#define GLB_BMX_TIMEOUT_EN_LEN (4U)
+#define GLB_BMX_TIMEOUT_EN_POS (0)
+#define GLB_BMX_TIMEOUT_EN_LEN (4)
#define GLB_BMX_TIMEOUT_EN_MSK \
- (((1U << GLB_BMX_TIMEOUT_EN_LEN) - 1) << GLB_BMX_TIMEOUT_EN_POS)
+ (((1 << GLB_BMX_TIMEOUT_EN_LEN) - 1) << GLB_BMX_TIMEOUT_EN_POS)
#define GLB_BMX_TIMEOUT_EN_UMSK \
- (~(((1U << GLB_BMX_TIMEOUT_EN_LEN) - 1) << GLB_BMX_TIMEOUT_EN_POS))
+ (~(((1 << GLB_BMX_TIMEOUT_EN_LEN) - 1) << GLB_BMX_TIMEOUT_EN_POS))
#define GLB_BMX_ARB_MODE GLB_BMX_ARB_MODE
-#define GLB_BMX_ARB_MODE_POS (4U)
-#define GLB_BMX_ARB_MODE_LEN (2U)
+#define GLB_BMX_ARB_MODE_POS (4)
+#define GLB_BMX_ARB_MODE_LEN (2)
#define GLB_BMX_ARB_MODE_MSK \
- (((1U << GLB_BMX_ARB_MODE_LEN) - 1) << GLB_BMX_ARB_MODE_POS)
+ (((1 << GLB_BMX_ARB_MODE_LEN) - 1) << GLB_BMX_ARB_MODE_POS)
#define GLB_BMX_ARB_MODE_UMSK \
- (~(((1U << GLB_BMX_ARB_MODE_LEN) - 1) << GLB_BMX_ARB_MODE_POS))
+ (~(((1 << GLB_BMX_ARB_MODE_LEN) - 1) << GLB_BMX_ARB_MODE_POS))
#define GLB_BMX_ERR_EN GLB_BMX_ERR_EN
-#define GLB_BMX_ERR_EN_POS (8U)
-#define GLB_BMX_ERR_EN_LEN (1U)
+#define GLB_BMX_ERR_EN_POS (8)
+#define GLB_BMX_ERR_EN_LEN (1)
#define GLB_BMX_ERR_EN_MSK \
- (((1U << GLB_BMX_ERR_EN_LEN) - 1) << GLB_BMX_ERR_EN_POS)
+ (((1 << GLB_BMX_ERR_EN_LEN) - 1) << GLB_BMX_ERR_EN_POS)
#define GLB_BMX_ERR_EN_UMSK \
- (~(((1U << GLB_BMX_ERR_EN_LEN) - 1) << GLB_BMX_ERR_EN_POS))
+ (~(((1 << GLB_BMX_ERR_EN_LEN) - 1) << GLB_BMX_ERR_EN_POS))
#define GLB_BMX_BUSY_OPTION_DIS GLB_BMX_BUSY_OPTION_DIS
-#define GLB_BMX_BUSY_OPTION_DIS_POS (9U)
-#define GLB_BMX_BUSY_OPTION_DIS_LEN (1U)
+#define GLB_BMX_BUSY_OPTION_DIS_POS (9)
+#define GLB_BMX_BUSY_OPTION_DIS_LEN (1)
#define GLB_BMX_BUSY_OPTION_DIS_MSK \
- (((1U << GLB_BMX_BUSY_OPTION_DIS_LEN) - 1) << GLB_BMX_BUSY_OPTION_DIS_POS)
+ (((1 << GLB_BMX_BUSY_OPTION_DIS_LEN) - 1) << GLB_BMX_BUSY_OPTION_DIS_POS)
#define GLB_BMX_BUSY_OPTION_DIS_UMSK \
- (~(((1U << GLB_BMX_BUSY_OPTION_DIS_LEN) - 1) \
- << GLB_BMX_BUSY_OPTION_DIS_POS))
+ (~(((1 << GLB_BMX_BUSY_OPTION_DIS_LEN) - 1) << GLB_BMX_BUSY_OPTION_DIS_POS))
#define GLB_BMX_GATING_DIS GLB_BMX_GATING_DIS
-#define GLB_BMX_GATING_DIS_POS (10U)
-#define GLB_BMX_GATING_DIS_LEN (1U)
+#define GLB_BMX_GATING_DIS_POS (10)
+#define GLB_BMX_GATING_DIS_LEN (1)
#define GLB_BMX_GATING_DIS_MSK \
- (((1U << GLB_BMX_GATING_DIS_LEN) - 1) << GLB_BMX_GATING_DIS_POS)
+ (((1 << GLB_BMX_GATING_DIS_LEN) - 1) << GLB_BMX_GATING_DIS_POS)
#define GLB_BMX_GATING_DIS_UMSK \
- (~(((1U << GLB_BMX_GATING_DIS_LEN) - 1) << GLB_BMX_GATING_DIS_POS))
+ (~(((1 << GLB_BMX_GATING_DIS_LEN) - 1) << GLB_BMX_GATING_DIS_POS))
#define GLB_HSEL_OPTION GLB_HSEL_OPTION
-#define GLB_HSEL_OPTION_POS (12U)
-#define GLB_HSEL_OPTION_LEN (4U)
+#define GLB_HSEL_OPTION_POS (12)
+#define GLB_HSEL_OPTION_LEN (4)
#define GLB_HSEL_OPTION_MSK \
- (((1U << GLB_HSEL_OPTION_LEN) - 1) << GLB_HSEL_OPTION_POS)
+ (((1 << GLB_HSEL_OPTION_LEN) - 1) << GLB_HSEL_OPTION_POS)
#define GLB_HSEL_OPTION_UMSK \
- (~(((1U << GLB_HSEL_OPTION_LEN) - 1) << GLB_HSEL_OPTION_POS))
+ (~(((1 << GLB_HSEL_OPTION_LEN) - 1) << GLB_HSEL_OPTION_POS))
#define GLB_PDS_APB_CFG GLB_PDS_APB_CFG
-#define GLB_PDS_APB_CFG_POS (16U)
-#define GLB_PDS_APB_CFG_LEN (8U)
+#define GLB_PDS_APB_CFG_POS (16)
+#define GLB_PDS_APB_CFG_LEN (8)
#define GLB_PDS_APB_CFG_MSK \
- (((1U << GLB_PDS_APB_CFG_LEN) - 1) << GLB_PDS_APB_CFG_POS)
+ (((1 << GLB_PDS_APB_CFG_LEN) - 1) << GLB_PDS_APB_CFG_POS)
#define GLB_PDS_APB_CFG_UMSK \
- (~(((1U << GLB_PDS_APB_CFG_LEN) - 1) << GLB_PDS_APB_CFG_POS))
+ (~(((1 << GLB_PDS_APB_CFG_LEN) - 1) << GLB_PDS_APB_CFG_POS))
#define GLB_HBN_APB_CFG GLB_HBN_APB_CFG
-#define GLB_HBN_APB_CFG_POS (24U)
-#define GLB_HBN_APB_CFG_LEN (8U)
+#define GLB_HBN_APB_CFG_POS (24)
+#define GLB_HBN_APB_CFG_LEN (8)
#define GLB_HBN_APB_CFG_MSK \
- (((1U << GLB_HBN_APB_CFG_LEN) - 1) << GLB_HBN_APB_CFG_POS)
+ (((1 << GLB_HBN_APB_CFG_LEN) - 1) << GLB_HBN_APB_CFG_POS)
#define GLB_HBN_APB_CFG_UMSK \
- (~(((1U << GLB_HBN_APB_CFG_LEN) - 1) << GLB_HBN_APB_CFG_POS))
+ (~(((1 << GLB_HBN_APB_CFG_LEN) - 1) << GLB_HBN_APB_CFG_POS))
/* 0x54 : bmx_cfg2 */
#define GLB_BMX_CFG2_OFFSET (0x54)
#define GLB_BMX_ERR_ADDR_DIS GLB_BMX_ERR_ADDR_DIS
-#define GLB_BMX_ERR_ADDR_DIS_POS (0U)
-#define GLB_BMX_ERR_ADDR_DIS_LEN (1U)
+#define GLB_BMX_ERR_ADDR_DIS_POS (0)
+#define GLB_BMX_ERR_ADDR_DIS_LEN (1)
#define GLB_BMX_ERR_ADDR_DIS_MSK \
- (((1U << GLB_BMX_ERR_ADDR_DIS_LEN) - 1) << GLB_BMX_ERR_ADDR_DIS_POS)
+ (((1 << GLB_BMX_ERR_ADDR_DIS_LEN) - 1) << GLB_BMX_ERR_ADDR_DIS_POS)
#define GLB_BMX_ERR_ADDR_DIS_UMSK \
- (~(((1U << GLB_BMX_ERR_ADDR_DIS_LEN) - 1) << GLB_BMX_ERR_ADDR_DIS_POS))
+ (~(((1 << GLB_BMX_ERR_ADDR_DIS_LEN) - 1) << GLB_BMX_ERR_ADDR_DIS_POS))
#define GLB_BMX_ERR_DEC GLB_BMX_ERR_DEC
-#define GLB_BMX_ERR_DEC_POS (4U)
-#define GLB_BMX_ERR_DEC_LEN (1U)
+#define GLB_BMX_ERR_DEC_POS (4)
+#define GLB_BMX_ERR_DEC_LEN (1)
#define GLB_BMX_ERR_DEC_MSK \
- (((1U << GLB_BMX_ERR_DEC_LEN) - 1) << GLB_BMX_ERR_DEC_POS)
+ (((1 << GLB_BMX_ERR_DEC_LEN) - 1) << GLB_BMX_ERR_DEC_POS)
#define GLB_BMX_ERR_DEC_UMSK \
- (~(((1U << GLB_BMX_ERR_DEC_LEN) - 1) << GLB_BMX_ERR_DEC_POS))
+ (~(((1 << GLB_BMX_ERR_DEC_LEN) - 1) << GLB_BMX_ERR_DEC_POS))
#define GLB_BMX_ERR_TZ GLB_BMX_ERR_TZ
-#define GLB_BMX_ERR_TZ_POS (5U)
-#define GLB_BMX_ERR_TZ_LEN (1U)
+#define GLB_BMX_ERR_TZ_POS (5)
+#define GLB_BMX_ERR_TZ_LEN (1)
#define GLB_BMX_ERR_TZ_MSK \
- (((1U << GLB_BMX_ERR_TZ_LEN) - 1) << GLB_BMX_ERR_TZ_POS)
+ (((1 << GLB_BMX_ERR_TZ_LEN) - 1) << GLB_BMX_ERR_TZ_POS)
#define GLB_BMX_ERR_TZ_UMSK \
- (~(((1U << GLB_BMX_ERR_TZ_LEN) - 1) << GLB_BMX_ERR_TZ_POS))
+ (~(((1 << GLB_BMX_ERR_TZ_LEN) - 1) << GLB_BMX_ERR_TZ_POS))
#define GLB_BMX_DBG_SEL GLB_BMX_DBG_SEL
-#define GLB_BMX_DBG_SEL_POS (28U)
-#define GLB_BMX_DBG_SEL_LEN (4U)
+#define GLB_BMX_DBG_SEL_POS (28)
+#define GLB_BMX_DBG_SEL_LEN (4)
#define GLB_BMX_DBG_SEL_MSK \
- (((1U << GLB_BMX_DBG_SEL_LEN) - 1) << GLB_BMX_DBG_SEL_POS)
+ (((1 << GLB_BMX_DBG_SEL_LEN) - 1) << GLB_BMX_DBG_SEL_POS)
#define GLB_BMX_DBG_SEL_UMSK \
- (~(((1U << GLB_BMX_DBG_SEL_LEN) - 1) << GLB_BMX_DBG_SEL_POS))
+ (~(((1 << GLB_BMX_DBG_SEL_LEN) - 1) << GLB_BMX_DBG_SEL_POS))
/* 0x58 : bmx_err_addr */
#define GLB_BMX_ERR_ADDR_OFFSET (0x58)
#define GLB_BMX_ERR_ADDR GLB_BMX_ERR_ADDR
-#define GLB_BMX_ERR_ADDR_POS (0U)
-#define GLB_BMX_ERR_ADDR_LEN (32U)
+#define GLB_BMX_ERR_ADDR_POS (0)
+#define GLB_BMX_ERR_ADDR_LEN (32)
#define GLB_BMX_ERR_ADDR_MSK \
- (((1U << GLB_BMX_ERR_ADDR_LEN) - 1) << GLB_BMX_ERR_ADDR_POS)
+ (((1 << GLB_BMX_ERR_ADDR_LEN) - 1) << GLB_BMX_ERR_ADDR_POS)
#define GLB_BMX_ERR_ADDR_UMSK \
- (~(((1U << GLB_BMX_ERR_ADDR_LEN) - 1) << GLB_BMX_ERR_ADDR_POS))
+ (~(((1 << GLB_BMX_ERR_ADDR_LEN) - 1) << GLB_BMX_ERR_ADDR_POS))
/* 0x5C : bmx_dbg_out */
#define GLB_BMX_DBG_OUT_OFFSET (0x5C)
#define GLB_BMX_DBG_OUT GLB_BMX_DBG_OUT
-#define GLB_BMX_DBG_OUT_POS (0U)
-#define GLB_BMX_DBG_OUT_LEN (32U)
+#define GLB_BMX_DBG_OUT_POS (0)
+#define GLB_BMX_DBG_OUT_LEN (32)
#define GLB_BMX_DBG_OUT_MSK \
- (((1U << GLB_BMX_DBG_OUT_LEN) - 1) << GLB_BMX_DBG_OUT_POS)
+ (((1 << GLB_BMX_DBG_OUT_LEN) - 1) << GLB_BMX_DBG_OUT_POS)
#define GLB_BMX_DBG_OUT_UMSK \
- (~(((1U << GLB_BMX_DBG_OUT_LEN) - 1) << GLB_BMX_DBG_OUT_POS))
+ (~(((1 << GLB_BMX_DBG_OUT_LEN) - 1) << GLB_BMX_DBG_OUT_POS))
/* 0x60 : rsv0 */
@@ -790,1921 +792,1910 @@
#define GLB_SRAM_RET_OFFSET (0x70)
#define GLB_REG_SRAM_RET GLB_REG_SRAM_RET
-#define GLB_REG_SRAM_RET_POS (0U)
-#define GLB_REG_SRAM_RET_LEN (32U)
+#define GLB_REG_SRAM_RET_POS (0)
+#define GLB_REG_SRAM_RET_LEN (32)
#define GLB_REG_SRAM_RET_MSK \
- (((1U << GLB_REG_SRAM_RET_LEN) - 1) << GLB_REG_SRAM_RET_POS)
+ (((1 << GLB_REG_SRAM_RET_LEN) - 1) << GLB_REG_SRAM_RET_POS)
#define GLB_REG_SRAM_RET_UMSK \
- (~(((1U << GLB_REG_SRAM_RET_LEN) - 1) << GLB_REG_SRAM_RET_POS))
+ (~(((1 << GLB_REG_SRAM_RET_LEN) - 1) << GLB_REG_SRAM_RET_POS))
/* 0x74 : sram_slp */
#define GLB_SRAM_SLP_OFFSET (0x74)
#define GLB_REG_SRAM_SLP GLB_REG_SRAM_SLP
-#define GLB_REG_SRAM_SLP_POS (0U)
-#define GLB_REG_SRAM_SLP_LEN (32U)
+#define GLB_REG_SRAM_SLP_POS (0)
+#define GLB_REG_SRAM_SLP_LEN (32)
#define GLB_REG_SRAM_SLP_MSK \
- (((1U << GLB_REG_SRAM_SLP_LEN) - 1) << GLB_REG_SRAM_SLP_POS)
+ (((1 << GLB_REG_SRAM_SLP_LEN) - 1) << GLB_REG_SRAM_SLP_POS)
#define GLB_REG_SRAM_SLP_UMSK \
- (~(((1U << GLB_REG_SRAM_SLP_LEN) - 1) << GLB_REG_SRAM_SLP_POS))
+ (~(((1 << GLB_REG_SRAM_SLP_LEN) - 1) << GLB_REG_SRAM_SLP_POS))
/* 0x78 : sram_parm */
#define GLB_SRAM_PARM_OFFSET (0x78)
#define GLB_REG_SRAM_PARM GLB_REG_SRAM_PARM
-#define GLB_REG_SRAM_PARM_POS (0U)
-#define GLB_REG_SRAM_PARM_LEN (32U)
+#define GLB_REG_SRAM_PARM_POS (0)
+#define GLB_REG_SRAM_PARM_LEN (32)
#define GLB_REG_SRAM_PARM_MSK \
- (((1U << GLB_REG_SRAM_PARM_LEN) - 1) << GLB_REG_SRAM_PARM_POS)
+ (((1 << GLB_REG_SRAM_PARM_LEN) - 1) << GLB_REG_SRAM_PARM_POS)
#define GLB_REG_SRAM_PARM_UMSK \
- (~(((1U << GLB_REG_SRAM_PARM_LEN) - 1) << GLB_REG_SRAM_PARM_POS))
+ (~(((1 << GLB_REG_SRAM_PARM_LEN) - 1) << GLB_REG_SRAM_PARM_POS))
/* 0x7C : seam_misc */
#define GLB_SEAM_MISC_OFFSET (0x7C)
#define GLB_EM_SEL GLB_EM_SEL
-#define GLB_EM_SEL_POS (0U)
-#define GLB_EM_SEL_LEN (4U)
-#define GLB_EM_SEL_MSK (((1U << GLB_EM_SEL_LEN) - 1) << GLB_EM_SEL_POS)
-#define GLB_EM_SEL_UMSK (~(((1U << GLB_EM_SEL_LEN) - 1) << GLB_EM_SEL_POS))
+#define GLB_EM_SEL_POS (0)
+#define GLB_EM_SEL_LEN (4)
+#define GLB_EM_SEL_MSK (((1 << GLB_EM_SEL_LEN) - 1) << GLB_EM_SEL_POS)
+#define GLB_EM_SEL_UMSK (~(((1 << GLB_EM_SEL_LEN) - 1) << GLB_EM_SEL_POS))
/* 0x80 : glb_parm */
#define GLB_PARM_OFFSET (0x80)
#define GLB_REG_BD_EN GLB_REG_BD_EN
-#define GLB_REG_BD_EN_POS (0U)
-#define GLB_REG_BD_EN_LEN (1U)
+#define GLB_REG_BD_EN_POS (0)
+#define GLB_REG_BD_EN_LEN (1)
#define GLB_REG_BD_EN_MSK \
- (((1U << GLB_REG_BD_EN_LEN) - 1) << GLB_REG_BD_EN_POS)
+ (((1 << GLB_REG_BD_EN_LEN) - 1) << GLB_REG_BD_EN_POS)
#define GLB_REG_BD_EN_UMSK \
- (~(((1U << GLB_REG_BD_EN_LEN) - 1) << GLB_REG_BD_EN_POS))
+ (~(((1 << GLB_REG_BD_EN_LEN) - 1) << GLB_REG_BD_EN_POS))
#define GLB_REG_EXT_RST_SMT GLB_REG_EXT_RST_SMT
-#define GLB_REG_EXT_RST_SMT_POS (1U)
-#define GLB_REG_EXT_RST_SMT_LEN (1U)
+#define GLB_REG_EXT_RST_SMT_POS (1)
+#define GLB_REG_EXT_RST_SMT_LEN (1)
#define GLB_REG_EXT_RST_SMT_MSK \
- (((1U << GLB_REG_EXT_RST_SMT_LEN) - 1) << GLB_REG_EXT_RST_SMT_POS)
+ (((1 << GLB_REG_EXT_RST_SMT_LEN) - 1) << GLB_REG_EXT_RST_SMT_POS)
#define GLB_REG_EXT_RST_SMT_UMSK \
- (~(((1U << GLB_REG_EXT_RST_SMT_LEN) - 1) << GLB_REG_EXT_RST_SMT_POS))
+ (~(((1 << GLB_REG_EXT_RST_SMT_LEN) - 1) << GLB_REG_EXT_RST_SMT_POS))
#define GLB_JTAG_SWAP_SET GLB_JTAG_SWAP_SET
-#define GLB_JTAG_SWAP_SET_POS (2U)
-#define GLB_JTAG_SWAP_SET_LEN (6U)
+#define GLB_JTAG_SWAP_SET_POS (2)
+#define GLB_JTAG_SWAP_SET_LEN (6)
#define GLB_JTAG_SWAP_SET_MSK \
- (((1U << GLB_JTAG_SWAP_SET_LEN) - 1) << GLB_JTAG_SWAP_SET_POS)
+ (((1 << GLB_JTAG_SWAP_SET_LEN) - 1) << GLB_JTAG_SWAP_SET_POS)
#define GLB_JTAG_SWAP_SET_UMSK \
- (~(((1U << GLB_JTAG_SWAP_SET_LEN) - 1) << GLB_JTAG_SWAP_SET_POS))
+ (~(((1 << GLB_JTAG_SWAP_SET_LEN) - 1) << GLB_JTAG_SWAP_SET_POS))
#define GLB_SWAP_SFLASH_IO_3_IO_0 GLB_SWAP_SFLASH_IO_3_IO_0
-#define GLB_SWAP_SFLASH_IO_3_IO_0_POS (8U)
-#define GLB_SWAP_SFLASH_IO_3_IO_0_LEN (1U)
+#define GLB_SWAP_SFLASH_IO_3_IO_0_POS (8)
+#define GLB_SWAP_SFLASH_IO_3_IO_0_LEN (1)
#define GLB_SWAP_SFLASH_IO_3_IO_0_MSK \
- (((1U << GLB_SWAP_SFLASH_IO_3_IO_0_LEN) - 1) \
+ (((1 << GLB_SWAP_SFLASH_IO_3_IO_0_LEN) - 1) \
<< GLB_SWAP_SFLASH_IO_3_IO_0_POS)
#define GLB_SWAP_SFLASH_IO_3_IO_0_UMSK \
- (~(((1U << GLB_SWAP_SFLASH_IO_3_IO_0_LEN) - 1) \
+ (~(((1 << GLB_SWAP_SFLASH_IO_3_IO_0_LEN) - 1) \
<< GLB_SWAP_SFLASH_IO_3_IO_0_POS))
#define GLB_SEL_EMBEDDED_SFLASH GLB_SEL_EMBEDDED_SFLASH
-#define GLB_SEL_EMBEDDED_SFLASH_POS (9U)
-#define GLB_SEL_EMBEDDED_SFLASH_LEN (1U)
+#define GLB_SEL_EMBEDDED_SFLASH_POS (9)
+#define GLB_SEL_EMBEDDED_SFLASH_LEN (1)
#define GLB_SEL_EMBEDDED_SFLASH_MSK \
- (((1U << GLB_SEL_EMBEDDED_SFLASH_LEN) - 1) << GLB_SEL_EMBEDDED_SFLASH_POS)
+ (((1 << GLB_SEL_EMBEDDED_SFLASH_LEN) - 1) << GLB_SEL_EMBEDDED_SFLASH_POS)
#define GLB_SEL_EMBEDDED_SFLASH_UMSK \
- (~(((1U << GLB_SEL_EMBEDDED_SFLASH_LEN) - 1) \
- << GLB_SEL_EMBEDDED_SFLASH_POS))
+ (~(((1 << GLB_SEL_EMBEDDED_SFLASH_LEN) - 1) << GLB_SEL_EMBEDDED_SFLASH_POS))
#define GLB_REG_SPI_0_MASTER_MODE GLB_REG_SPI_0_MASTER_MODE
-#define GLB_REG_SPI_0_MASTER_MODE_POS (12U)
-#define GLB_REG_SPI_0_MASTER_MODE_LEN (1U)
+#define GLB_REG_SPI_0_MASTER_MODE_POS (12)
+#define GLB_REG_SPI_0_MASTER_MODE_LEN (1)
#define GLB_REG_SPI_0_MASTER_MODE_MSK \
- (((1U << GLB_REG_SPI_0_MASTER_MODE_LEN) - 1) \
+ (((1 << GLB_REG_SPI_0_MASTER_MODE_LEN) - 1) \
<< GLB_REG_SPI_0_MASTER_MODE_POS)
#define GLB_REG_SPI_0_MASTER_MODE_UMSK \
- (~(((1U << GLB_REG_SPI_0_MASTER_MODE_LEN) - 1) \
+ (~(((1 << GLB_REG_SPI_0_MASTER_MODE_LEN) - 1) \
<< GLB_REG_SPI_0_MASTER_MODE_POS))
#define GLB_REG_SPI_0_SWAP GLB_REG_SPI_0_SWAP
-#define GLB_REG_SPI_0_SWAP_POS (13U)
-#define GLB_REG_SPI_0_SWAP_LEN (1U)
+#define GLB_REG_SPI_0_SWAP_POS (13)
+#define GLB_REG_SPI_0_SWAP_LEN (1)
#define GLB_REG_SPI_0_SWAP_MSK \
- (((1U << GLB_REG_SPI_0_SWAP_LEN) - 1) << GLB_REG_SPI_0_SWAP_POS)
+ (((1 << GLB_REG_SPI_0_SWAP_LEN) - 1) << GLB_REG_SPI_0_SWAP_POS)
#define GLB_REG_SPI_0_SWAP_UMSK \
- (~(((1U << GLB_REG_SPI_0_SWAP_LEN) - 1) << GLB_REG_SPI_0_SWAP_POS))
+ (~(((1 << GLB_REG_SPI_0_SWAP_LEN) - 1) << GLB_REG_SPI_0_SWAP_POS))
#define GLB_REG_CCI_USE_JTAG_PIN GLB_REG_CCI_USE_JTAG_PIN
-#define GLB_REG_CCI_USE_JTAG_PIN_POS (15U)
-#define GLB_REG_CCI_USE_JTAG_PIN_LEN (1U)
+#define GLB_REG_CCI_USE_JTAG_PIN_POS (15)
+#define GLB_REG_CCI_USE_JTAG_PIN_LEN (1)
#define GLB_REG_CCI_USE_JTAG_PIN_MSK \
- (((1U << GLB_REG_CCI_USE_JTAG_PIN_LEN) - 1) << GLB_REG_CCI_USE_JTAG_PIN_POS)
+ (((1 << GLB_REG_CCI_USE_JTAG_PIN_LEN) - 1) << GLB_REG_CCI_USE_JTAG_PIN_POS)
#define GLB_REG_CCI_USE_JTAG_PIN_UMSK \
- (~(((1U << GLB_REG_CCI_USE_JTAG_PIN_LEN) - 1) \
+ (~(((1 << GLB_REG_CCI_USE_JTAG_PIN_LEN) - 1) \
<< GLB_REG_CCI_USE_JTAG_PIN_POS))
#define GLB_REG_CCI_USE_SDIO_PIN GLB_REG_CCI_USE_SDIO_PIN
-#define GLB_REG_CCI_USE_SDIO_PIN_POS (16U)
-#define GLB_REG_CCI_USE_SDIO_PIN_LEN (1U)
+#define GLB_REG_CCI_USE_SDIO_PIN_POS (16)
+#define GLB_REG_CCI_USE_SDIO_PIN_LEN (1)
#define GLB_REG_CCI_USE_SDIO_PIN_MSK \
- (((1U << GLB_REG_CCI_USE_SDIO_PIN_LEN) - 1) << GLB_REG_CCI_USE_SDIO_PIN_POS)
+ (((1 << GLB_REG_CCI_USE_SDIO_PIN_LEN) - 1) << GLB_REG_CCI_USE_SDIO_PIN_POS)
#define GLB_REG_CCI_USE_SDIO_PIN_UMSK \
- (~(((1U << GLB_REG_CCI_USE_SDIO_PIN_LEN) - 1) \
+ (~(((1 << GLB_REG_CCI_USE_SDIO_PIN_LEN) - 1) \
<< GLB_REG_CCI_USE_SDIO_PIN_POS))
#define GLB_P1_ADC_TEST_WITH_CCI GLB_P1_ADC_TEST_WITH_CCI
-#define GLB_P1_ADC_TEST_WITH_CCI_POS (17U)
-#define GLB_P1_ADC_TEST_WITH_CCI_LEN (1U)
+#define GLB_P1_ADC_TEST_WITH_CCI_POS (17)
+#define GLB_P1_ADC_TEST_WITH_CCI_LEN (1)
#define GLB_P1_ADC_TEST_WITH_CCI_MSK \
- (((1U << GLB_P1_ADC_TEST_WITH_CCI_LEN) - 1) << GLB_P1_ADC_TEST_WITH_CCI_POS)
+ (((1 << GLB_P1_ADC_TEST_WITH_CCI_LEN) - 1) << GLB_P1_ADC_TEST_WITH_CCI_POS)
#define GLB_P1_ADC_TEST_WITH_CCI_UMSK \
- (~(((1U << GLB_P1_ADC_TEST_WITH_CCI_LEN) - 1) \
+ (~(((1 << GLB_P1_ADC_TEST_WITH_CCI_LEN) - 1) \
<< GLB_P1_ADC_TEST_WITH_CCI_POS))
#define GLB_P2_DAC_TEST_WITH_CCI GLB_P2_DAC_TEST_WITH_CCI
-#define GLB_P2_DAC_TEST_WITH_CCI_POS (18U)
-#define GLB_P2_DAC_TEST_WITH_CCI_LEN (1U)
+#define GLB_P2_DAC_TEST_WITH_CCI_POS (18)
+#define GLB_P2_DAC_TEST_WITH_CCI_LEN (1)
#define GLB_P2_DAC_TEST_WITH_CCI_MSK \
- (((1U << GLB_P2_DAC_TEST_WITH_CCI_LEN) - 1) << GLB_P2_DAC_TEST_WITH_CCI_POS)
+ (((1 << GLB_P2_DAC_TEST_WITH_CCI_LEN) - 1) << GLB_P2_DAC_TEST_WITH_CCI_POS)
#define GLB_P2_DAC_TEST_WITH_CCI_UMSK \
- (~(((1U << GLB_P2_DAC_TEST_WITH_CCI_LEN) - 1) \
+ (~(((1 << GLB_P2_DAC_TEST_WITH_CCI_LEN) - 1) \
<< GLB_P2_DAC_TEST_WITH_CCI_POS))
#define GLB_P3_CCI_USE_IO_2_5 GLB_P3_CCI_USE_IO_2_5
-#define GLB_P3_CCI_USE_IO_2_5_POS (19U)
-#define GLB_P3_CCI_USE_IO_2_5_LEN (1U)
+#define GLB_P3_CCI_USE_IO_2_5_POS (19)
+#define GLB_P3_CCI_USE_IO_2_5_LEN (1)
#define GLB_P3_CCI_USE_IO_2_5_MSK \
- (((1U << GLB_P3_CCI_USE_IO_2_5_LEN) - 1) << GLB_P3_CCI_USE_IO_2_5_POS)
+ (((1 << GLB_P3_CCI_USE_IO_2_5_LEN) - 1) << GLB_P3_CCI_USE_IO_2_5_POS)
#define GLB_P3_CCI_USE_IO_2_5_UMSK \
- (~(((1U << GLB_P3_CCI_USE_IO_2_5_LEN) - 1) << GLB_P3_CCI_USE_IO_2_5_POS))
+ (~(((1 << GLB_P3_CCI_USE_IO_2_5_LEN) - 1) << GLB_P3_CCI_USE_IO_2_5_POS))
#define GLB_P4_ADC_TEST_WITH_JTAG GLB_P4_ADC_TEST_WITH_JTAG
-#define GLB_P4_ADC_TEST_WITH_JTAG_POS (20U)
-#define GLB_P4_ADC_TEST_WITH_JTAG_LEN (1U)
+#define GLB_P4_ADC_TEST_WITH_JTAG_POS (20)
+#define GLB_P4_ADC_TEST_WITH_JTAG_LEN (1)
#define GLB_P4_ADC_TEST_WITH_JTAG_MSK \
- (((1U << GLB_P4_ADC_TEST_WITH_JTAG_LEN) - 1) \
+ (((1 << GLB_P4_ADC_TEST_WITH_JTAG_LEN) - 1) \
<< GLB_P4_ADC_TEST_WITH_JTAG_POS)
#define GLB_P4_ADC_TEST_WITH_JTAG_UMSK \
- (~(((1U << GLB_P4_ADC_TEST_WITH_JTAG_LEN) - 1) \
+ (~(((1 << GLB_P4_ADC_TEST_WITH_JTAG_LEN) - 1) \
<< GLB_P4_ADC_TEST_WITH_JTAG_POS))
#define GLB_P5_DAC_TEST_WITH_JTAG GLB_P5_DAC_TEST_WITH_JTAG
-#define GLB_P5_DAC_TEST_WITH_JTAG_POS (21U)
-#define GLB_P5_DAC_TEST_WITH_JTAG_LEN (1U)
+#define GLB_P5_DAC_TEST_WITH_JTAG_POS (21)
+#define GLB_P5_DAC_TEST_WITH_JTAG_LEN (1)
#define GLB_P5_DAC_TEST_WITH_JTAG_MSK \
- (((1U << GLB_P5_DAC_TEST_WITH_JTAG_LEN) - 1) \
+ (((1 << GLB_P5_DAC_TEST_WITH_JTAG_LEN) - 1) \
<< GLB_P5_DAC_TEST_WITH_JTAG_POS)
#define GLB_P5_DAC_TEST_WITH_JTAG_UMSK \
- (~(((1U << GLB_P5_DAC_TEST_WITH_JTAG_LEN) - 1) \
+ (~(((1 << GLB_P5_DAC_TEST_WITH_JTAG_LEN) - 1) \
<< GLB_P5_DAC_TEST_WITH_JTAG_POS))
#define GLB_P6_SDIO_USE_IO_0_5 GLB_P6_SDIO_USE_IO_0_5
-#define GLB_P6_SDIO_USE_IO_0_5_POS (22U)
-#define GLB_P6_SDIO_USE_IO_0_5_LEN (1U)
+#define GLB_P6_SDIO_USE_IO_0_5_POS (22)
+#define GLB_P6_SDIO_USE_IO_0_5_LEN (1)
#define GLB_P6_SDIO_USE_IO_0_5_MSK \
- (((1U << GLB_P6_SDIO_USE_IO_0_5_LEN) - 1) << GLB_P6_SDIO_USE_IO_0_5_POS)
+ (((1 << GLB_P6_SDIO_USE_IO_0_5_LEN) - 1) << GLB_P6_SDIO_USE_IO_0_5_POS)
#define GLB_P6_SDIO_USE_IO_0_5_UMSK \
- (~(((1U << GLB_P6_SDIO_USE_IO_0_5_LEN) - 1) << GLB_P6_SDIO_USE_IO_0_5_POS))
+ (~(((1 << GLB_P6_SDIO_USE_IO_0_5_LEN) - 1) << GLB_P6_SDIO_USE_IO_0_5_POS))
#define GLB_P7_JTAG_USE_IO_2_5 GLB_P7_JTAG_USE_IO_2_5
-#define GLB_P7_JTAG_USE_IO_2_5_POS (23U)
-#define GLB_P7_JTAG_USE_IO_2_5_LEN (1U)
+#define GLB_P7_JTAG_USE_IO_2_5_POS (23)
+#define GLB_P7_JTAG_USE_IO_2_5_LEN (1)
#define GLB_P7_JTAG_USE_IO_2_5_MSK \
- (((1U << GLB_P7_JTAG_USE_IO_2_5_LEN) - 1) << GLB_P7_JTAG_USE_IO_2_5_POS)
+ (((1 << GLB_P7_JTAG_USE_IO_2_5_LEN) - 1) << GLB_P7_JTAG_USE_IO_2_5_POS)
#define GLB_P7_JTAG_USE_IO_2_5_UMSK \
- (~(((1U << GLB_P7_JTAG_USE_IO_2_5_LEN) - 1) << GLB_P7_JTAG_USE_IO_2_5_POS))
+ (~(((1 << GLB_P7_JTAG_USE_IO_2_5_LEN) - 1) << GLB_P7_JTAG_USE_IO_2_5_POS))
#define GLB_UART_SWAP_SET GLB_UART_SWAP_SET
-#define GLB_UART_SWAP_SET_POS (24U)
-#define GLB_UART_SWAP_SET_LEN (3U)
+#define GLB_UART_SWAP_SET_POS (24)
+#define GLB_UART_SWAP_SET_LEN (3)
#define GLB_UART_SWAP_SET_MSK \
- (((1U << GLB_UART_SWAP_SET_LEN) - 1) << GLB_UART_SWAP_SET_POS)
+ (((1 << GLB_UART_SWAP_SET_LEN) - 1) << GLB_UART_SWAP_SET_POS)
#define GLB_UART_SWAP_SET_UMSK \
- (~(((1U << GLB_UART_SWAP_SET_LEN) - 1) << GLB_UART_SWAP_SET_POS))
+ (~(((1 << GLB_UART_SWAP_SET_LEN) - 1) << GLB_UART_SWAP_SET_POS))
/* 0x90 : CPU_CLK_CFG */
#define GLB_CPU_CLK_CFG_OFFSET (0x90)
#define GLB_CPU_RTC_DIV GLB_CPU_RTC_DIV
-#define GLB_CPU_RTC_DIV_POS (0U)
-#define GLB_CPU_RTC_DIV_LEN (17U)
+#define GLB_CPU_RTC_DIV_POS (0)
+#define GLB_CPU_RTC_DIV_LEN (17)
#define GLB_CPU_RTC_DIV_MSK \
- (((1U << GLB_CPU_RTC_DIV_LEN) - 1) << GLB_CPU_RTC_DIV_POS)
+ (((1 << GLB_CPU_RTC_DIV_LEN) - 1) << GLB_CPU_RTC_DIV_POS)
#define GLB_CPU_RTC_DIV_UMSK \
- (~(((1U << GLB_CPU_RTC_DIV_LEN) - 1) << GLB_CPU_RTC_DIV_POS))
+ (~(((1 << GLB_CPU_RTC_DIV_LEN) - 1) << GLB_CPU_RTC_DIV_POS))
#define GLB_CPU_RTC_EN GLB_CPU_RTC_EN
-#define GLB_CPU_RTC_EN_POS (18U)
-#define GLB_CPU_RTC_EN_LEN (1U)
+#define GLB_CPU_RTC_EN_POS (18)
+#define GLB_CPU_RTC_EN_LEN (1)
#define GLB_CPU_RTC_EN_MSK \
- (((1U << GLB_CPU_RTC_EN_LEN) - 1) << GLB_CPU_RTC_EN_POS)
+ (((1 << GLB_CPU_RTC_EN_LEN) - 1) << GLB_CPU_RTC_EN_POS)
#define GLB_CPU_RTC_EN_UMSK \
- (~(((1U << GLB_CPU_RTC_EN_LEN) - 1) << GLB_CPU_RTC_EN_POS))
+ (~(((1 << GLB_CPU_RTC_EN_LEN) - 1) << GLB_CPU_RTC_EN_POS))
#define GLB_CPU_RTC_SEL GLB_CPU_RTC_SEL
-#define GLB_CPU_RTC_SEL_POS (19U)
-#define GLB_CPU_RTC_SEL_LEN (1U)
+#define GLB_CPU_RTC_SEL_POS (19)
+#define GLB_CPU_RTC_SEL_LEN (1)
#define GLB_CPU_RTC_SEL_MSK \
- (((1U << GLB_CPU_RTC_SEL_LEN) - 1) << GLB_CPU_RTC_SEL_POS)
+ (((1 << GLB_CPU_RTC_SEL_LEN) - 1) << GLB_CPU_RTC_SEL_POS)
#define GLB_CPU_RTC_SEL_UMSK \
- (~(((1U << GLB_CPU_RTC_SEL_LEN) - 1) << GLB_CPU_RTC_SEL_POS))
+ (~(((1 << GLB_CPU_RTC_SEL_LEN) - 1) << GLB_CPU_RTC_SEL_POS))
#define GLB_DEBUG_NDRESET_GATE GLB_DEBUG_NDRESET_GATE
-#define GLB_DEBUG_NDRESET_GATE_POS (20U)
-#define GLB_DEBUG_NDRESET_GATE_LEN (1U)
+#define GLB_DEBUG_NDRESET_GATE_POS (20)
+#define GLB_DEBUG_NDRESET_GATE_LEN (1)
#define GLB_DEBUG_NDRESET_GATE_MSK \
- (((1U << GLB_DEBUG_NDRESET_GATE_LEN) - 1) << GLB_DEBUG_NDRESET_GATE_POS)
+ (((1 << GLB_DEBUG_NDRESET_GATE_LEN) - 1) << GLB_DEBUG_NDRESET_GATE_POS)
#define GLB_DEBUG_NDRESET_GATE_UMSK \
- (~(((1U << GLB_DEBUG_NDRESET_GATE_LEN) - 1) << GLB_DEBUG_NDRESET_GATE_POS))
+ (~(((1 << GLB_DEBUG_NDRESET_GATE_LEN) - 1) << GLB_DEBUG_NDRESET_GATE_POS))
/* 0xA4 : GPADC_32M_SRC_CTRL */
#define GLB_GPADC_32M_SRC_CTRL_OFFSET (0xA4)
#define GLB_GPADC_32M_CLK_DIV GLB_GPADC_32M_CLK_DIV
-#define GLB_GPADC_32M_CLK_DIV_POS (0U)
-#define GLB_GPADC_32M_CLK_DIV_LEN (6U)
+#define GLB_GPADC_32M_CLK_DIV_POS (0)
+#define GLB_GPADC_32M_CLK_DIV_LEN (6)
#define GLB_GPADC_32M_CLK_DIV_MSK \
- (((1U << GLB_GPADC_32M_CLK_DIV_LEN) - 1) << GLB_GPADC_32M_CLK_DIV_POS)
+ (((1 << GLB_GPADC_32M_CLK_DIV_LEN) - 1) << GLB_GPADC_32M_CLK_DIV_POS)
#define GLB_GPADC_32M_CLK_DIV_UMSK \
- (~(((1U << GLB_GPADC_32M_CLK_DIV_LEN) - 1) << GLB_GPADC_32M_CLK_DIV_POS))
+ (~(((1 << GLB_GPADC_32M_CLK_DIV_LEN) - 1) << GLB_GPADC_32M_CLK_DIV_POS))
#define GLB_GPADC_32M_CLK_SEL GLB_GPADC_32M_CLK_SEL
-#define GLB_GPADC_32M_CLK_SEL_POS (7U)
-#define GLB_GPADC_32M_CLK_SEL_LEN (1U)
+#define GLB_GPADC_32M_CLK_SEL_POS (7)
+#define GLB_GPADC_32M_CLK_SEL_LEN (1)
#define GLB_GPADC_32M_CLK_SEL_MSK \
- (((1U << GLB_GPADC_32M_CLK_SEL_LEN) - 1) << GLB_GPADC_32M_CLK_SEL_POS)
+ (((1 << GLB_GPADC_32M_CLK_SEL_LEN) - 1) << GLB_GPADC_32M_CLK_SEL_POS)
#define GLB_GPADC_32M_CLK_SEL_UMSK \
- (~(((1U << GLB_GPADC_32M_CLK_SEL_LEN) - 1) << GLB_GPADC_32M_CLK_SEL_POS))
+ (~(((1 << GLB_GPADC_32M_CLK_SEL_LEN) - 1) << GLB_GPADC_32M_CLK_SEL_POS))
#define GLB_GPADC_32M_DIV_EN GLB_GPADC_32M_DIV_EN
-#define GLB_GPADC_32M_DIV_EN_POS (8U)
-#define GLB_GPADC_32M_DIV_EN_LEN (1U)
+#define GLB_GPADC_32M_DIV_EN_POS (8)
+#define GLB_GPADC_32M_DIV_EN_LEN (1)
#define GLB_GPADC_32M_DIV_EN_MSK \
- (((1U << GLB_GPADC_32M_DIV_EN_LEN) - 1) << GLB_GPADC_32M_DIV_EN_POS)
+ (((1 << GLB_GPADC_32M_DIV_EN_LEN) - 1) << GLB_GPADC_32M_DIV_EN_POS)
#define GLB_GPADC_32M_DIV_EN_UMSK \
- (~(((1U << GLB_GPADC_32M_DIV_EN_LEN) - 1) << GLB_GPADC_32M_DIV_EN_POS))
+ (~(((1 << GLB_GPADC_32M_DIV_EN_LEN) - 1) << GLB_GPADC_32M_DIV_EN_POS))
/* 0xA8 : DIG32K_WAKEUP_CTRL */
#define GLB_DIG32K_WAKEUP_CTRL_OFFSET (0xA8)
#define GLB_DIG_32K_DIV GLB_DIG_32K_DIV
-#define GLB_DIG_32K_DIV_POS (0U)
-#define GLB_DIG_32K_DIV_LEN (11U)
+#define GLB_DIG_32K_DIV_POS (0)
+#define GLB_DIG_32K_DIV_LEN (11)
#define GLB_DIG_32K_DIV_MSK \
- (((1U << GLB_DIG_32K_DIV_LEN) - 1) << GLB_DIG_32K_DIV_POS)
+ (((1 << GLB_DIG_32K_DIV_LEN) - 1) << GLB_DIG_32K_DIV_POS)
#define GLB_DIG_32K_DIV_UMSK \
- (~(((1U << GLB_DIG_32K_DIV_LEN) - 1) << GLB_DIG_32K_DIV_POS))
+ (~(((1 << GLB_DIG_32K_DIV_LEN) - 1) << GLB_DIG_32K_DIV_POS))
#define GLB_DIG_32K_EN GLB_DIG_32K_EN
-#define GLB_DIG_32K_EN_POS (12U)
-#define GLB_DIG_32K_EN_LEN (1U)
+#define GLB_DIG_32K_EN_POS (12)
+#define GLB_DIG_32K_EN_LEN (1)
#define GLB_DIG_32K_EN_MSK \
- (((1U << GLB_DIG_32K_EN_LEN) - 1) << GLB_DIG_32K_EN_POS)
+ (((1 << GLB_DIG_32K_EN_LEN) - 1) << GLB_DIG_32K_EN_POS)
#define GLB_DIG_32K_EN_UMSK \
- (~(((1U << GLB_DIG_32K_EN_LEN) - 1) << GLB_DIG_32K_EN_POS))
+ (~(((1 << GLB_DIG_32K_EN_LEN) - 1) << GLB_DIG_32K_EN_POS))
#define GLB_DIG_32K_COMP GLB_DIG_32K_COMP
-#define GLB_DIG_32K_COMP_POS (13U)
-#define GLB_DIG_32K_COMP_LEN (1U)
+#define GLB_DIG_32K_COMP_POS (13)
+#define GLB_DIG_32K_COMP_LEN (1)
#define GLB_DIG_32K_COMP_MSK \
- (((1U << GLB_DIG_32K_COMP_LEN) - 1) << GLB_DIG_32K_COMP_POS)
+ (((1 << GLB_DIG_32K_COMP_LEN) - 1) << GLB_DIG_32K_COMP_POS)
#define GLB_DIG_32K_COMP_UMSK \
- (~(((1U << GLB_DIG_32K_COMP_LEN) - 1) << GLB_DIG_32K_COMP_POS))
+ (~(((1 << GLB_DIG_32K_COMP_LEN) - 1) << GLB_DIG_32K_COMP_POS))
#define GLB_DIG_512K_DIV GLB_DIG_512K_DIV
-#define GLB_DIG_512K_DIV_POS (16U)
-#define GLB_DIG_512K_DIV_LEN (7U)
+#define GLB_DIG_512K_DIV_POS (16)
+#define GLB_DIG_512K_DIV_LEN (7)
#define GLB_DIG_512K_DIV_MSK \
- (((1U << GLB_DIG_512K_DIV_LEN) - 1) << GLB_DIG_512K_DIV_POS)
+ (((1 << GLB_DIG_512K_DIV_LEN) - 1) << GLB_DIG_512K_DIV_POS)
#define GLB_DIG_512K_DIV_UMSK \
- (~(((1U << GLB_DIG_512K_DIV_LEN) - 1) << GLB_DIG_512K_DIV_POS))
+ (~(((1 << GLB_DIG_512K_DIV_LEN) - 1) << GLB_DIG_512K_DIV_POS))
#define GLB_DIG_512K_EN GLB_DIG_512K_EN
-#define GLB_DIG_512K_EN_POS (24U)
-#define GLB_DIG_512K_EN_LEN (1U)
+#define GLB_DIG_512K_EN_POS (24)
+#define GLB_DIG_512K_EN_LEN (1)
#define GLB_DIG_512K_EN_MSK \
- (((1U << GLB_DIG_512K_EN_LEN) - 1) << GLB_DIG_512K_EN_POS)
+ (((1 << GLB_DIG_512K_EN_LEN) - 1) << GLB_DIG_512K_EN_POS)
#define GLB_DIG_512K_EN_UMSK \
- (~(((1U << GLB_DIG_512K_EN_LEN) - 1) << GLB_DIG_512K_EN_POS))
+ (~(((1 << GLB_DIG_512K_EN_LEN) - 1) << GLB_DIG_512K_EN_POS))
#define GLB_DIG_512K_COMP GLB_DIG_512K_COMP
-#define GLB_DIG_512K_COMP_POS (25U)
-#define GLB_DIG_512K_COMP_LEN (1U)
+#define GLB_DIG_512K_COMP_POS (25)
+#define GLB_DIG_512K_COMP_LEN (1)
#define GLB_DIG_512K_COMP_MSK \
- (((1U << GLB_DIG_512K_COMP_LEN) - 1) << GLB_DIG_512K_COMP_POS)
+ (((1 << GLB_DIG_512K_COMP_LEN) - 1) << GLB_DIG_512K_COMP_POS)
#define GLB_DIG_512K_COMP_UMSK \
- (~(((1U << GLB_DIG_512K_COMP_LEN) - 1) << GLB_DIG_512K_COMP_POS))
+ (~(((1 << GLB_DIG_512K_COMP_LEN) - 1) << GLB_DIG_512K_COMP_POS))
#define GLB_DIG_CLK_SRC_SEL GLB_DIG_CLK_SRC_SEL
-#define GLB_DIG_CLK_SRC_SEL_POS (28U)
-#define GLB_DIG_CLK_SRC_SEL_LEN (1U)
+#define GLB_DIG_CLK_SRC_SEL_POS (28)
+#define GLB_DIG_CLK_SRC_SEL_LEN (1)
#define GLB_DIG_CLK_SRC_SEL_MSK \
- (((1U << GLB_DIG_CLK_SRC_SEL_LEN) - 1) << GLB_DIG_CLK_SRC_SEL_POS)
+ (((1 << GLB_DIG_CLK_SRC_SEL_LEN) - 1) << GLB_DIG_CLK_SRC_SEL_POS)
#define GLB_DIG_CLK_SRC_SEL_UMSK \
- (~(((1U << GLB_DIG_CLK_SRC_SEL_LEN) - 1) << GLB_DIG_CLK_SRC_SEL_POS))
+ (~(((1 << GLB_DIG_CLK_SRC_SEL_LEN) - 1) << GLB_DIG_CLK_SRC_SEL_POS))
#define GLB_REG_EN_PLATFORM_WAKEUP GLB_REG_EN_PLATFORM_WAKEUP
-#define GLB_REG_EN_PLATFORM_WAKEUP_POS (31U)
-#define GLB_REG_EN_PLATFORM_WAKEUP_LEN (1U)
+#define GLB_REG_EN_PLATFORM_WAKEUP_POS (31)
+#define GLB_REG_EN_PLATFORM_WAKEUP_LEN (1)
#define GLB_REG_EN_PLATFORM_WAKEUP_MSK \
- (((1U << GLB_REG_EN_PLATFORM_WAKEUP_LEN) - 1) \
+ (((1 << GLB_REG_EN_PLATFORM_WAKEUP_LEN) - 1) \
<< GLB_REG_EN_PLATFORM_WAKEUP_POS)
#define GLB_REG_EN_PLATFORM_WAKEUP_UMSK \
- (~(((1U << GLB_REG_EN_PLATFORM_WAKEUP_LEN) - 1) \
+ (~(((1 << GLB_REG_EN_PLATFORM_WAKEUP_LEN) - 1) \
<< GLB_REG_EN_PLATFORM_WAKEUP_POS))
/* 0xAC : WIFI_BT_COEX_CTRL */
#define GLB_WIFI_BT_COEX_CTRL_OFFSET (0xAC)
#define GLB_COEX_BT_CHANNEL GLB_COEX_BT_CHANNEL
-#define GLB_COEX_BT_CHANNEL_POS (0U)
-#define GLB_COEX_BT_CHANNEL_LEN (7U)
+#define GLB_COEX_BT_CHANNEL_POS (0)
+#define GLB_COEX_BT_CHANNEL_LEN (7)
#define GLB_COEX_BT_CHANNEL_MSK \
- (((1U << GLB_COEX_BT_CHANNEL_LEN) - 1) << GLB_COEX_BT_CHANNEL_POS)
+ (((1 << GLB_COEX_BT_CHANNEL_LEN) - 1) << GLB_COEX_BT_CHANNEL_POS)
#define GLB_COEX_BT_CHANNEL_UMSK \
- (~(((1U << GLB_COEX_BT_CHANNEL_LEN) - 1) << GLB_COEX_BT_CHANNEL_POS))
+ (~(((1 << GLB_COEX_BT_CHANNEL_LEN) - 1) << GLB_COEX_BT_CHANNEL_POS))
#define GLB_COEX_BT_PTI GLB_COEX_BT_PTI
-#define GLB_COEX_BT_PTI_POS (7U)
-#define GLB_COEX_BT_PTI_LEN (4U)
+#define GLB_COEX_BT_PTI_POS (7)
+#define GLB_COEX_BT_PTI_LEN (4)
#define GLB_COEX_BT_PTI_MSK \
- (((1U << GLB_COEX_BT_PTI_LEN) - 1) << GLB_COEX_BT_PTI_POS)
+ (((1 << GLB_COEX_BT_PTI_LEN) - 1) << GLB_COEX_BT_PTI_POS)
#define GLB_COEX_BT_PTI_UMSK \
- (~(((1U << GLB_COEX_BT_PTI_LEN) - 1) << GLB_COEX_BT_PTI_POS))
+ (~(((1 << GLB_COEX_BT_PTI_LEN) - 1) << GLB_COEX_BT_PTI_POS))
#define GLB_COEX_BT_BW GLB_COEX_BT_BW
-#define GLB_COEX_BT_BW_POS (11U)
-#define GLB_COEX_BT_BW_LEN (1U)
+#define GLB_COEX_BT_BW_POS (11)
+#define GLB_COEX_BT_BW_LEN (1)
#define GLB_COEX_BT_BW_MSK \
- (((1U << GLB_COEX_BT_BW_LEN) - 1) << GLB_COEX_BT_BW_POS)
+ (((1 << GLB_COEX_BT_BW_LEN) - 1) << GLB_COEX_BT_BW_POS)
#define GLB_COEX_BT_BW_UMSK \
- (~(((1U << GLB_COEX_BT_BW_LEN) - 1) << GLB_COEX_BT_BW_POS))
+ (~(((1 << GLB_COEX_BT_BW_LEN) - 1) << GLB_COEX_BT_BW_POS))
#define GLB_EN_GPIO_BT_COEX GLB_EN_GPIO_BT_COEX
-#define GLB_EN_GPIO_BT_COEX_POS (12U)
-#define GLB_EN_GPIO_BT_COEX_LEN (1U)
+#define GLB_EN_GPIO_BT_COEX_POS (12)
+#define GLB_EN_GPIO_BT_COEX_LEN (1)
#define GLB_EN_GPIO_BT_COEX_MSK \
- (((1U << GLB_EN_GPIO_BT_COEX_LEN) - 1) << GLB_EN_GPIO_BT_COEX_POS)
+ (((1 << GLB_EN_GPIO_BT_COEX_LEN) - 1) << GLB_EN_GPIO_BT_COEX_POS)
#define GLB_EN_GPIO_BT_COEX_UMSK \
- (~(((1U << GLB_EN_GPIO_BT_COEX_LEN) - 1) << GLB_EN_GPIO_BT_COEX_POS))
+ (~(((1 << GLB_EN_GPIO_BT_COEX_LEN) - 1) << GLB_EN_GPIO_BT_COEX_POS))
/* 0xC0 : UART_SIG_SEL_0 */
#define GLB_UART_SIG_SEL_0_OFFSET (0xC0)
#define GLB_UART_SIG_0_SEL GLB_UART_SIG_0_SEL
-#define GLB_UART_SIG_0_SEL_POS (0U)
-#define GLB_UART_SIG_0_SEL_LEN (4U)
+#define GLB_UART_SIG_0_SEL_POS (0)
+#define GLB_UART_SIG_0_SEL_LEN (4)
#define GLB_UART_SIG_0_SEL_MSK \
- (((1U << GLB_UART_SIG_0_SEL_LEN) - 1) << GLB_UART_SIG_0_SEL_POS)
+ (((1 << GLB_UART_SIG_0_SEL_LEN) - 1) << GLB_UART_SIG_0_SEL_POS)
#define GLB_UART_SIG_0_SEL_UMSK \
- (~(((1U << GLB_UART_SIG_0_SEL_LEN) - 1) << GLB_UART_SIG_0_SEL_POS))
+ (~(((1 << GLB_UART_SIG_0_SEL_LEN) - 1) << GLB_UART_SIG_0_SEL_POS))
#define GLB_UART_SIG_1_SEL GLB_UART_SIG_1_SEL
-#define GLB_UART_SIG_1_SEL_POS (4U)
-#define GLB_UART_SIG_1_SEL_LEN (4U)
+#define GLB_UART_SIG_1_SEL_POS (4)
+#define GLB_UART_SIG_1_SEL_LEN (4)
#define GLB_UART_SIG_1_SEL_MSK \
- (((1U << GLB_UART_SIG_1_SEL_LEN) - 1) << GLB_UART_SIG_1_SEL_POS)
+ (((1 << GLB_UART_SIG_1_SEL_LEN) - 1) << GLB_UART_SIG_1_SEL_POS)
#define GLB_UART_SIG_1_SEL_UMSK \
- (~(((1U << GLB_UART_SIG_1_SEL_LEN) - 1) << GLB_UART_SIG_1_SEL_POS))
+ (~(((1 << GLB_UART_SIG_1_SEL_LEN) - 1) << GLB_UART_SIG_1_SEL_POS))
#define GLB_UART_SIG_2_SEL GLB_UART_SIG_2_SEL
-#define GLB_UART_SIG_2_SEL_POS (8U)
-#define GLB_UART_SIG_2_SEL_LEN (4U)
+#define GLB_UART_SIG_2_SEL_POS (8)
+#define GLB_UART_SIG_2_SEL_LEN (4)
#define GLB_UART_SIG_2_SEL_MSK \
- (((1U << GLB_UART_SIG_2_SEL_LEN) - 1) << GLB_UART_SIG_2_SEL_POS)
+ (((1 << GLB_UART_SIG_2_SEL_LEN) - 1) << GLB_UART_SIG_2_SEL_POS)
#define GLB_UART_SIG_2_SEL_UMSK \
- (~(((1U << GLB_UART_SIG_2_SEL_LEN) - 1) << GLB_UART_SIG_2_SEL_POS))
+ (~(((1 << GLB_UART_SIG_2_SEL_LEN) - 1) << GLB_UART_SIG_2_SEL_POS))
#define GLB_UART_SIG_3_SEL GLB_UART_SIG_3_SEL
-#define GLB_UART_SIG_3_SEL_POS (12U)
-#define GLB_UART_SIG_3_SEL_LEN (4U)
+#define GLB_UART_SIG_3_SEL_POS (12)
+#define GLB_UART_SIG_3_SEL_LEN (4)
#define GLB_UART_SIG_3_SEL_MSK \
- (((1U << GLB_UART_SIG_3_SEL_LEN) - 1) << GLB_UART_SIG_3_SEL_POS)
+ (((1 << GLB_UART_SIG_3_SEL_LEN) - 1) << GLB_UART_SIG_3_SEL_POS)
#define GLB_UART_SIG_3_SEL_UMSK \
- (~(((1U << GLB_UART_SIG_3_SEL_LEN) - 1) << GLB_UART_SIG_3_SEL_POS))
+ (~(((1 << GLB_UART_SIG_3_SEL_LEN) - 1) << GLB_UART_SIG_3_SEL_POS))
#define GLB_UART_SIG_4_SEL GLB_UART_SIG_4_SEL
-#define GLB_UART_SIG_4_SEL_POS (16U)
-#define GLB_UART_SIG_4_SEL_LEN (4U)
+#define GLB_UART_SIG_4_SEL_POS (16)
+#define GLB_UART_SIG_4_SEL_LEN (4)
#define GLB_UART_SIG_4_SEL_MSK \
- (((1U << GLB_UART_SIG_4_SEL_LEN) - 1) << GLB_UART_SIG_4_SEL_POS)
+ (((1 << GLB_UART_SIG_4_SEL_LEN) - 1) << GLB_UART_SIG_4_SEL_POS)
#define GLB_UART_SIG_4_SEL_UMSK \
- (~(((1U << GLB_UART_SIG_4_SEL_LEN) - 1) << GLB_UART_SIG_4_SEL_POS))
+ (~(((1 << GLB_UART_SIG_4_SEL_LEN) - 1) << GLB_UART_SIG_4_SEL_POS))
#define GLB_UART_SIG_5_SEL GLB_UART_SIG_5_SEL
-#define GLB_UART_SIG_5_SEL_POS (20U)
-#define GLB_UART_SIG_5_SEL_LEN (4U)
+#define GLB_UART_SIG_5_SEL_POS (20)
+#define GLB_UART_SIG_5_SEL_LEN (4)
#define GLB_UART_SIG_5_SEL_MSK \
- (((1U << GLB_UART_SIG_5_SEL_LEN) - 1) << GLB_UART_SIG_5_SEL_POS)
+ (((1 << GLB_UART_SIG_5_SEL_LEN) - 1) << GLB_UART_SIG_5_SEL_POS)
#define GLB_UART_SIG_5_SEL_UMSK \
- (~(((1U << GLB_UART_SIG_5_SEL_LEN) - 1) << GLB_UART_SIG_5_SEL_POS))
+ (~(((1 << GLB_UART_SIG_5_SEL_LEN) - 1) << GLB_UART_SIG_5_SEL_POS))
#define GLB_UART_SIG_6_SEL GLB_UART_SIG_6_SEL
-#define GLB_UART_SIG_6_SEL_POS (24U)
-#define GLB_UART_SIG_6_SEL_LEN (4U)
+#define GLB_UART_SIG_6_SEL_POS (24)
+#define GLB_UART_SIG_6_SEL_LEN (4)
#define GLB_UART_SIG_6_SEL_MSK \
- (((1U << GLB_UART_SIG_6_SEL_LEN) - 1) << GLB_UART_SIG_6_SEL_POS)
+ (((1 << GLB_UART_SIG_6_SEL_LEN) - 1) << GLB_UART_SIG_6_SEL_POS)
#define GLB_UART_SIG_6_SEL_UMSK \
- (~(((1U << GLB_UART_SIG_6_SEL_LEN) - 1) << GLB_UART_SIG_6_SEL_POS))
+ (~(((1 << GLB_UART_SIG_6_SEL_LEN) - 1) << GLB_UART_SIG_6_SEL_POS))
#define GLB_UART_SIG_7_SEL GLB_UART_SIG_7_SEL
-#define GLB_UART_SIG_7_SEL_POS (28U)
-#define GLB_UART_SIG_7_SEL_LEN (4U)
+#define GLB_UART_SIG_7_SEL_POS (28)
+#define GLB_UART_SIG_7_SEL_LEN (4)
#define GLB_UART_SIG_7_SEL_MSK \
- (((1U << GLB_UART_SIG_7_SEL_LEN) - 1) << GLB_UART_SIG_7_SEL_POS)
+ (((1 << GLB_UART_SIG_7_SEL_LEN) - 1) << GLB_UART_SIG_7_SEL_POS)
#define GLB_UART_SIG_7_SEL_UMSK \
- (~(((1U << GLB_UART_SIG_7_SEL_LEN) - 1) << GLB_UART_SIG_7_SEL_POS))
+ (~(((1 << GLB_UART_SIG_7_SEL_LEN) - 1) << GLB_UART_SIG_7_SEL_POS))
/* 0xD0 : DBG_SEL_LL */
#define GLB_DBG_SEL_LL_OFFSET (0xD0)
#define GLB_REG_DBG_LL_CTRL GLB_REG_DBG_LL_CTRL
-#define GLB_REG_DBG_LL_CTRL_POS (0U)
-#define GLB_REG_DBG_LL_CTRL_LEN (32U)
+#define GLB_REG_DBG_LL_CTRL_POS (0)
+#define GLB_REG_DBG_LL_CTRL_LEN (32)
#define GLB_REG_DBG_LL_CTRL_MSK \
- (((1U << GLB_REG_DBG_LL_CTRL_LEN) - 1) << GLB_REG_DBG_LL_CTRL_POS)
+ (((1 << GLB_REG_DBG_LL_CTRL_LEN) - 1) << GLB_REG_DBG_LL_CTRL_POS)
#define GLB_REG_DBG_LL_CTRL_UMSK \
- (~(((1U << GLB_REG_DBG_LL_CTRL_LEN) - 1) << GLB_REG_DBG_LL_CTRL_POS))
+ (~(((1 << GLB_REG_DBG_LL_CTRL_LEN) - 1) << GLB_REG_DBG_LL_CTRL_POS))
/* 0xD4 : DBG_SEL_LH */
#define GLB_DBG_SEL_LH_OFFSET (0xD4)
#define GLB_REG_DBG_LH_CTRL GLB_REG_DBG_LH_CTRL
-#define GLB_REG_DBG_LH_CTRL_POS (0U)
-#define GLB_REG_DBG_LH_CTRL_LEN (32U)
+#define GLB_REG_DBG_LH_CTRL_POS (0)
+#define GLB_REG_DBG_LH_CTRL_LEN (32)
#define GLB_REG_DBG_LH_CTRL_MSK \
- (((1U << GLB_REG_DBG_LH_CTRL_LEN) - 1) << GLB_REG_DBG_LH_CTRL_POS)
+ (((1 << GLB_REG_DBG_LH_CTRL_LEN) - 1) << GLB_REG_DBG_LH_CTRL_POS)
#define GLB_REG_DBG_LH_CTRL_UMSK \
- (~(((1U << GLB_REG_DBG_LH_CTRL_LEN) - 1) << GLB_REG_DBG_LH_CTRL_POS))
+ (~(((1 << GLB_REG_DBG_LH_CTRL_LEN) - 1) << GLB_REG_DBG_LH_CTRL_POS))
/* 0xD8 : DBG_SEL_HL */
#define GLB_DBG_SEL_HL_OFFSET (0xD8)
#define GLB_REG_DBG_HL_CTRL GLB_REG_DBG_HL_CTRL
-#define GLB_REG_DBG_HL_CTRL_POS (0U)
-#define GLB_REG_DBG_HL_CTRL_LEN (32U)
+#define GLB_REG_DBG_HL_CTRL_POS (0)
+#define GLB_REG_DBG_HL_CTRL_LEN (32)
#define GLB_REG_DBG_HL_CTRL_MSK \
- (((1U << GLB_REG_DBG_HL_CTRL_LEN) - 1) << GLB_REG_DBG_HL_CTRL_POS)
+ (((1 << GLB_REG_DBG_HL_CTRL_LEN) - 1) << GLB_REG_DBG_HL_CTRL_POS)
#define GLB_REG_DBG_HL_CTRL_UMSK \
- (~(((1U << GLB_REG_DBG_HL_CTRL_LEN) - 1) << GLB_REG_DBG_HL_CTRL_POS))
+ (~(((1 << GLB_REG_DBG_HL_CTRL_LEN) - 1) << GLB_REG_DBG_HL_CTRL_POS))
/* 0xDC : DBG_SEL_HH */
#define GLB_DBG_SEL_HH_OFFSET (0xDC)
#define GLB_REG_DBG_HH_CTRL GLB_REG_DBG_HH_CTRL
-#define GLB_REG_DBG_HH_CTRL_POS (0U)
-#define GLB_REG_DBG_HH_CTRL_LEN (32U)
+#define GLB_REG_DBG_HH_CTRL_POS (0)
+#define GLB_REG_DBG_HH_CTRL_LEN (32)
#define GLB_REG_DBG_HH_CTRL_MSK \
- (((1U << GLB_REG_DBG_HH_CTRL_LEN) - 1) << GLB_REG_DBG_HH_CTRL_POS)
+ (((1 << GLB_REG_DBG_HH_CTRL_LEN) - 1) << GLB_REG_DBG_HH_CTRL_POS)
#define GLB_REG_DBG_HH_CTRL_UMSK \
- (~(((1U << GLB_REG_DBG_HH_CTRL_LEN) - 1) << GLB_REG_DBG_HH_CTRL_POS))
+ (~(((1 << GLB_REG_DBG_HH_CTRL_LEN) - 1) << GLB_REG_DBG_HH_CTRL_POS))
/* 0xE0 : debug */
#define GLB_DEBUG_OFFSET (0xE0)
#define GLB_DEBUG_OE GLB_DEBUG_OE
-#define GLB_DEBUG_OE_POS (0U)
-#define GLB_DEBUG_OE_LEN (1U)
-#define GLB_DEBUG_OE_MSK (((1U << GLB_DEBUG_OE_LEN) - 1) << GLB_DEBUG_OE_POS)
+#define GLB_DEBUG_OE_POS (0)
+#define GLB_DEBUG_OE_LEN (1)
+#define GLB_DEBUG_OE_MSK (((1 << GLB_DEBUG_OE_LEN) - 1) << GLB_DEBUG_OE_POS)
#define GLB_DEBUG_OE_UMSK \
- (~(((1U << GLB_DEBUG_OE_LEN) - 1) << GLB_DEBUG_OE_POS))
+ (~(((1 << GLB_DEBUG_OE_LEN) - 1) << GLB_DEBUG_OE_POS))
#define GLB_DEBUG_I GLB_DEBUG_I
-#define GLB_DEBUG_I_POS (1U)
-#define GLB_DEBUG_I_LEN (31U)
-#define GLB_DEBUG_I_MSK (((1U << GLB_DEBUG_I_LEN) - 1) << GLB_DEBUG_I_POS)
-#define GLB_DEBUG_I_UMSK (~(((1U << GLB_DEBUG_I_LEN) - 1) << GLB_DEBUG_I_POS))
+#define GLB_DEBUG_I_POS (1)
+#define GLB_DEBUG_I_LEN (31)
+#define GLB_DEBUG_I_MSK (((1 << GLB_DEBUG_I_LEN) - 1) << GLB_DEBUG_I_POS)
+#define GLB_DEBUG_I_UMSK (~(((1 << GLB_DEBUG_I_LEN) - 1) << GLB_DEBUG_I_POS))
/* 0x100 : GPIO_CFGCTL0 */
#define GLB_GPIO_CFGCTL0_OFFSET (0x100)
#define GLB_REG_GPIO_0_IE GLB_REG_GPIO_0_IE
-#define GLB_REG_GPIO_0_IE_POS (0U)
-#define GLB_REG_GPIO_0_IE_LEN (1U)
+#define GLB_REG_GPIO_0_IE_POS (0)
+#define GLB_REG_GPIO_0_IE_LEN (1)
#define GLB_REG_GPIO_0_IE_MSK \
- (((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS)
+ (((1 << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS)
#define GLB_REG_GPIO_0_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS))
+ (~(((1 << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS))
#define GLB_REG_GPIO_0_SMT GLB_REG_GPIO_0_SMT
-#define GLB_REG_GPIO_0_SMT_POS (1U)
-#define GLB_REG_GPIO_0_SMT_LEN (1U)
+#define GLB_REG_GPIO_0_SMT_POS (1)
+#define GLB_REG_GPIO_0_SMT_LEN (1)
#define GLB_REG_GPIO_0_SMT_MSK \
- (((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS)
+ (((1 << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS)
#define GLB_REG_GPIO_0_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS))
#define GLB_REG_GPIO_0_DRV GLB_REG_GPIO_0_DRV
-#define GLB_REG_GPIO_0_DRV_POS (2U)
-#define GLB_REG_GPIO_0_DRV_LEN (2U)
+#define GLB_REG_GPIO_0_DRV_POS (2)
+#define GLB_REG_GPIO_0_DRV_LEN (2)
#define GLB_REG_GPIO_0_DRV_MSK \
- (((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS)
+ (((1 << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS)
#define GLB_REG_GPIO_0_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS))
#define GLB_REG_GPIO_0_PU GLB_REG_GPIO_0_PU
-#define GLB_REG_GPIO_0_PU_POS (4U)
-#define GLB_REG_GPIO_0_PU_LEN (1U)
+#define GLB_REG_GPIO_0_PU_POS (4)
+#define GLB_REG_GPIO_0_PU_LEN (1)
#define GLB_REG_GPIO_0_PU_MSK \
- (((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS)
+ (((1 << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS)
#define GLB_REG_GPIO_0_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS))
+ (~(((1 << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS))
#define GLB_REG_GPIO_0_PD GLB_REG_GPIO_0_PD
-#define GLB_REG_GPIO_0_PD_POS (5U)
-#define GLB_REG_GPIO_0_PD_LEN (1U)
+#define GLB_REG_GPIO_0_PD_POS (5)
+#define GLB_REG_GPIO_0_PD_LEN (1)
#define GLB_REG_GPIO_0_PD_MSK \
- (((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS)
+ (((1 << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS)
#define GLB_REG_GPIO_0_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS))
+ (~(((1 << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS))
#define GLB_REG_GPIO_0_FUNC_SEL GLB_REG_GPIO_0_FUNC_SEL
-#define GLB_REG_GPIO_0_FUNC_SEL_POS (8U)
-#define GLB_REG_GPIO_0_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_0_FUNC_SEL_POS (8)
+#define GLB_REG_GPIO_0_FUNC_SEL_LEN (4)
#define GLB_REG_GPIO_0_FUNC_SEL_MSK \
- (((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS)
+ (((1 << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS)
#define GLB_REG_GPIO_0_FUNC_SEL_UMSK \
- (~(((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) \
- << GLB_REG_GPIO_0_FUNC_SEL_POS))
+ (~(((1 << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS))
#define GLB_REAL_GPIO_0_FUNC_SEL GLB_REAL_GPIO_0_FUNC_SEL
-#define GLB_REAL_GPIO_0_FUNC_SEL_POS (12U)
-#define GLB_REAL_GPIO_0_FUNC_SEL_LEN (4U)
+#define GLB_REAL_GPIO_0_FUNC_SEL_POS (12)
+#define GLB_REAL_GPIO_0_FUNC_SEL_LEN (4)
#define GLB_REAL_GPIO_0_FUNC_SEL_MSK \
- (((1U << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_0_FUNC_SEL_POS)
+ (((1 << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_0_FUNC_SEL_POS)
#define GLB_REAL_GPIO_0_FUNC_SEL_UMSK \
- (~(((1U << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) \
+ (~(((1 << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) \
<< GLB_REAL_GPIO_0_FUNC_SEL_POS))
#define GLB_REG_GPIO_1_IE GLB_REG_GPIO_1_IE
-#define GLB_REG_GPIO_1_IE_POS (16U)
-#define GLB_REG_GPIO_1_IE_LEN (1U)
+#define GLB_REG_GPIO_1_IE_POS (16)
+#define GLB_REG_GPIO_1_IE_LEN (1)
#define GLB_REG_GPIO_1_IE_MSK \
- (((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS)
+ (((1 << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS)
#define GLB_REG_GPIO_1_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS))
+ (~(((1 << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS))
#define GLB_REG_GPIO_1_SMT GLB_REG_GPIO_1_SMT
-#define GLB_REG_GPIO_1_SMT_POS (17U)
-#define GLB_REG_GPIO_1_SMT_LEN (1U)
+#define GLB_REG_GPIO_1_SMT_POS (17)
+#define GLB_REG_GPIO_1_SMT_LEN (1)
#define GLB_REG_GPIO_1_SMT_MSK \
- (((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS)
+ (((1 << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS)
#define GLB_REG_GPIO_1_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS))
#define GLB_REG_GPIO_1_DRV GLB_REG_GPIO_1_DRV
-#define GLB_REG_GPIO_1_DRV_POS (18U)
-#define GLB_REG_GPIO_1_DRV_LEN (2U)
+#define GLB_REG_GPIO_1_DRV_POS (18)
+#define GLB_REG_GPIO_1_DRV_LEN (2)
#define GLB_REG_GPIO_1_DRV_MSK \
- (((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS)
+ (((1 << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS)
#define GLB_REG_GPIO_1_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS))
#define GLB_REG_GPIO_1_PU GLB_REG_GPIO_1_PU
-#define GLB_REG_GPIO_1_PU_POS (20U)
-#define GLB_REG_GPIO_1_PU_LEN (1U)
+#define GLB_REG_GPIO_1_PU_POS (20)
+#define GLB_REG_GPIO_1_PU_LEN (1)
#define GLB_REG_GPIO_1_PU_MSK \
- (((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS)
+ (((1 << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS)
#define GLB_REG_GPIO_1_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS))
+ (~(((1 << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS))
#define GLB_REG_GPIO_1_PD GLB_REG_GPIO_1_PD
-#define GLB_REG_GPIO_1_PD_POS (21U)
-#define GLB_REG_GPIO_1_PD_LEN (1U)
+#define GLB_REG_GPIO_1_PD_POS (21)
+#define GLB_REG_GPIO_1_PD_LEN (1)
#define GLB_REG_GPIO_1_PD_MSK \
- (((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS)
+ (((1 << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS)
#define GLB_REG_GPIO_1_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS))
+ (~(((1 << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS))
#define GLB_REG_GPIO_1_FUNC_SEL GLB_REG_GPIO_1_FUNC_SEL
-#define GLB_REG_GPIO_1_FUNC_SEL_POS (24U)
-#define GLB_REG_GPIO_1_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_1_FUNC_SEL_POS (24)
+#define GLB_REG_GPIO_1_FUNC_SEL_LEN (4)
#define GLB_REG_GPIO_1_FUNC_SEL_MSK \
- (((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS)
+ (((1 << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS)
#define GLB_REG_GPIO_1_FUNC_SEL_UMSK \
- (~(((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) \
- << GLB_REG_GPIO_1_FUNC_SEL_POS))
+ (~(((1 << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS))
#define GLB_REAL_GPIO_1_FUNC_SEL GLB_REAL_GPIO_1_FUNC_SEL
-#define GLB_REAL_GPIO_1_FUNC_SEL_POS (28U)
-#define GLB_REAL_GPIO_1_FUNC_SEL_LEN (4U)
+#define GLB_REAL_GPIO_1_FUNC_SEL_POS (28)
+#define GLB_REAL_GPIO_1_FUNC_SEL_LEN (4)
#define GLB_REAL_GPIO_1_FUNC_SEL_MSK \
- (((1U << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_1_FUNC_SEL_POS)
+ (((1 << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_1_FUNC_SEL_POS)
#define GLB_REAL_GPIO_1_FUNC_SEL_UMSK \
- (~(((1U << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) \
+ (~(((1 << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) \
<< GLB_REAL_GPIO_1_FUNC_SEL_POS))
/* 0x104 : GPIO_CFGCTL1 */
#define GLB_GPIO_CFGCTL1_OFFSET (0x104)
#define GLB_REG_GPIO_2_IE GLB_REG_GPIO_2_IE
-#define GLB_REG_GPIO_2_IE_POS (0U)
-#define GLB_REG_GPIO_2_IE_LEN (1U)
+#define GLB_REG_GPIO_2_IE_POS (0)
+#define GLB_REG_GPIO_2_IE_LEN (1)
#define GLB_REG_GPIO_2_IE_MSK \
- (((1U << GLB_REG_GPIO_2_IE_LEN) - 1) << GLB_REG_GPIO_2_IE_POS)
+ (((1 << GLB_REG_GPIO_2_IE_LEN) - 1) << GLB_REG_GPIO_2_IE_POS)
#define GLB_REG_GPIO_2_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_2_IE_LEN) - 1) << GLB_REG_GPIO_2_IE_POS))
+ (~(((1 << GLB_REG_GPIO_2_IE_LEN) - 1) << GLB_REG_GPIO_2_IE_POS))
#define GLB_REG_GPIO_2_SMT GLB_REG_GPIO_2_SMT
-#define GLB_REG_GPIO_2_SMT_POS (1U)
-#define GLB_REG_GPIO_2_SMT_LEN (1U)
+#define GLB_REG_GPIO_2_SMT_POS (1)
+#define GLB_REG_GPIO_2_SMT_LEN (1)
#define GLB_REG_GPIO_2_SMT_MSK \
- (((1U << GLB_REG_GPIO_2_SMT_LEN) - 1) << GLB_REG_GPIO_2_SMT_POS)
+ (((1 << GLB_REG_GPIO_2_SMT_LEN) - 1) << GLB_REG_GPIO_2_SMT_POS)
#define GLB_REG_GPIO_2_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_2_SMT_LEN) - 1) << GLB_REG_GPIO_2_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_2_SMT_LEN) - 1) << GLB_REG_GPIO_2_SMT_POS))
#define GLB_REG_GPIO_2_DRV GLB_REG_GPIO_2_DRV
-#define GLB_REG_GPIO_2_DRV_POS (2U)
-#define GLB_REG_GPIO_2_DRV_LEN (2U)
+#define GLB_REG_GPIO_2_DRV_POS (2)
+#define GLB_REG_GPIO_2_DRV_LEN (2)
#define GLB_REG_GPIO_2_DRV_MSK \
- (((1U << GLB_REG_GPIO_2_DRV_LEN) - 1) << GLB_REG_GPIO_2_DRV_POS)
+ (((1 << GLB_REG_GPIO_2_DRV_LEN) - 1) << GLB_REG_GPIO_2_DRV_POS)
#define GLB_REG_GPIO_2_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_2_DRV_LEN) - 1) << GLB_REG_GPIO_2_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_2_DRV_LEN) - 1) << GLB_REG_GPIO_2_DRV_POS))
#define GLB_REG_GPIO_2_PU GLB_REG_GPIO_2_PU
-#define GLB_REG_GPIO_2_PU_POS (4U)
-#define GLB_REG_GPIO_2_PU_LEN (1U)
+#define GLB_REG_GPIO_2_PU_POS (4)
+#define GLB_REG_GPIO_2_PU_LEN (1)
#define GLB_REG_GPIO_2_PU_MSK \
- (((1U << GLB_REG_GPIO_2_PU_LEN) - 1) << GLB_REG_GPIO_2_PU_POS)
+ (((1 << GLB_REG_GPIO_2_PU_LEN) - 1) << GLB_REG_GPIO_2_PU_POS)
#define GLB_REG_GPIO_2_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_2_PU_LEN) - 1) << GLB_REG_GPIO_2_PU_POS))
+ (~(((1 << GLB_REG_GPIO_2_PU_LEN) - 1) << GLB_REG_GPIO_2_PU_POS))
#define GLB_REG_GPIO_2_PD GLB_REG_GPIO_2_PD
-#define GLB_REG_GPIO_2_PD_POS (5U)
-#define GLB_REG_GPIO_2_PD_LEN (1U)
+#define GLB_REG_GPIO_2_PD_POS (5)
+#define GLB_REG_GPIO_2_PD_LEN (1)
#define GLB_REG_GPIO_2_PD_MSK \
- (((1U << GLB_REG_GPIO_2_PD_LEN) - 1) << GLB_REG_GPIO_2_PD_POS)
+ (((1 << GLB_REG_GPIO_2_PD_LEN) - 1) << GLB_REG_GPIO_2_PD_POS)
#define GLB_REG_GPIO_2_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_2_PD_LEN) - 1) << GLB_REG_GPIO_2_PD_POS))
+ (~(((1 << GLB_REG_GPIO_2_PD_LEN) - 1) << GLB_REG_GPIO_2_PD_POS))
#define GLB_REG_GPIO_2_FUNC_SEL GLB_REG_GPIO_2_FUNC_SEL
-#define GLB_REG_GPIO_2_FUNC_SEL_POS (8U)
-#define GLB_REG_GPIO_2_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_2_FUNC_SEL_POS (8)
+#define GLB_REG_GPIO_2_FUNC_SEL_LEN (4)
#define GLB_REG_GPIO_2_FUNC_SEL_MSK \
- (((1U << GLB_REG_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_2_FUNC_SEL_POS)
+ (((1 << GLB_REG_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_2_FUNC_SEL_POS)
#define GLB_REG_GPIO_2_FUNC_SEL_UMSK \
- (~(((1U << GLB_REG_GPIO_2_FUNC_SEL_LEN) - 1) \
- << GLB_REG_GPIO_2_FUNC_SEL_POS))
+ (~(((1 << GLB_REG_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_2_FUNC_SEL_POS))
#define GLB_REAL_GPIO_2_FUNC_SEL GLB_REAL_GPIO_2_FUNC_SEL
-#define GLB_REAL_GPIO_2_FUNC_SEL_POS (12U)
-#define GLB_REAL_GPIO_2_FUNC_SEL_LEN (4U)
+#define GLB_REAL_GPIO_2_FUNC_SEL_POS (12)
+#define GLB_REAL_GPIO_2_FUNC_SEL_LEN (4)
#define GLB_REAL_GPIO_2_FUNC_SEL_MSK \
- (((1U << GLB_REAL_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_2_FUNC_SEL_POS)
+ (((1 << GLB_REAL_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_2_FUNC_SEL_POS)
#define GLB_REAL_GPIO_2_FUNC_SEL_UMSK \
- (~(((1U << GLB_REAL_GPIO_2_FUNC_SEL_LEN) - 1) \
+ (~(((1 << GLB_REAL_GPIO_2_FUNC_SEL_LEN) - 1) \
<< GLB_REAL_GPIO_2_FUNC_SEL_POS))
#define GLB_REG_GPIO_3_IE GLB_REG_GPIO_3_IE
-#define GLB_REG_GPIO_3_IE_POS (16U)
-#define GLB_REG_GPIO_3_IE_LEN (1U)
+#define GLB_REG_GPIO_3_IE_POS (16)
+#define GLB_REG_GPIO_3_IE_LEN (1)
#define GLB_REG_GPIO_3_IE_MSK \
- (((1U << GLB_REG_GPIO_3_IE_LEN) - 1) << GLB_REG_GPIO_3_IE_POS)
+ (((1 << GLB_REG_GPIO_3_IE_LEN) - 1) << GLB_REG_GPIO_3_IE_POS)
#define GLB_REG_GPIO_3_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_3_IE_LEN) - 1) << GLB_REG_GPIO_3_IE_POS))
+ (~(((1 << GLB_REG_GPIO_3_IE_LEN) - 1) << GLB_REG_GPIO_3_IE_POS))
#define GLB_REG_GPIO_3_SMT GLB_REG_GPIO_3_SMT
-#define GLB_REG_GPIO_3_SMT_POS (17U)
-#define GLB_REG_GPIO_3_SMT_LEN (1U)
+#define GLB_REG_GPIO_3_SMT_POS (17)
+#define GLB_REG_GPIO_3_SMT_LEN (1)
#define GLB_REG_GPIO_3_SMT_MSK \
- (((1U << GLB_REG_GPIO_3_SMT_LEN) - 1) << GLB_REG_GPIO_3_SMT_POS)
+ (((1 << GLB_REG_GPIO_3_SMT_LEN) - 1) << GLB_REG_GPIO_3_SMT_POS)
#define GLB_REG_GPIO_3_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_3_SMT_LEN) - 1) << GLB_REG_GPIO_3_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_3_SMT_LEN) - 1) << GLB_REG_GPIO_3_SMT_POS))
#define GLB_REG_GPIO_3_DRV GLB_REG_GPIO_3_DRV
-#define GLB_REG_GPIO_3_DRV_POS (18U)
-#define GLB_REG_GPIO_3_DRV_LEN (2U)
+#define GLB_REG_GPIO_3_DRV_POS (18)
+#define GLB_REG_GPIO_3_DRV_LEN (2)
#define GLB_REG_GPIO_3_DRV_MSK \
- (((1U << GLB_REG_GPIO_3_DRV_LEN) - 1) << GLB_REG_GPIO_3_DRV_POS)
+ (((1 << GLB_REG_GPIO_3_DRV_LEN) - 1) << GLB_REG_GPIO_3_DRV_POS)
#define GLB_REG_GPIO_3_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_3_DRV_LEN) - 1) << GLB_REG_GPIO_3_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_3_DRV_LEN) - 1) << GLB_REG_GPIO_3_DRV_POS))
#define GLB_REG_GPIO_3_PU GLB_REG_GPIO_3_PU
-#define GLB_REG_GPIO_3_PU_POS (20U)
-#define GLB_REG_GPIO_3_PU_LEN (1U)
+#define GLB_REG_GPIO_3_PU_POS (20)
+#define GLB_REG_GPIO_3_PU_LEN (1)
#define GLB_REG_GPIO_3_PU_MSK \
- (((1U << GLB_REG_GPIO_3_PU_LEN) - 1) << GLB_REG_GPIO_3_PU_POS)
+ (((1 << GLB_REG_GPIO_3_PU_LEN) - 1) << GLB_REG_GPIO_3_PU_POS)
#define GLB_REG_GPIO_3_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_3_PU_LEN) - 1) << GLB_REG_GPIO_3_PU_POS))
+ (~(((1 << GLB_REG_GPIO_3_PU_LEN) - 1) << GLB_REG_GPIO_3_PU_POS))
#define GLB_REG_GPIO_3_PD GLB_REG_GPIO_3_PD
-#define GLB_REG_GPIO_3_PD_POS (21U)
-#define GLB_REG_GPIO_3_PD_LEN (1U)
+#define GLB_REG_GPIO_3_PD_POS (21)
+#define GLB_REG_GPIO_3_PD_LEN (1)
#define GLB_REG_GPIO_3_PD_MSK \
- (((1U << GLB_REG_GPIO_3_PD_LEN) - 1) << GLB_REG_GPIO_3_PD_POS)
+ (((1 << GLB_REG_GPIO_3_PD_LEN) - 1) << GLB_REG_GPIO_3_PD_POS)
#define GLB_REG_GPIO_3_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_3_PD_LEN) - 1) << GLB_REG_GPIO_3_PD_POS))
+ (~(((1 << GLB_REG_GPIO_3_PD_LEN) - 1) << GLB_REG_GPIO_3_PD_POS))
#define GLB_REG_GPIO_3_FUNC_SEL GLB_REG_GPIO_3_FUNC_SEL
-#define GLB_REG_GPIO_3_FUNC_SEL_POS (24U)
-#define GLB_REG_GPIO_3_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_3_FUNC_SEL_POS (24)
+#define GLB_REG_GPIO_3_FUNC_SEL_LEN (4)
#define GLB_REG_GPIO_3_FUNC_SEL_MSK \
- (((1U << GLB_REG_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_3_FUNC_SEL_POS)
+ (((1 << GLB_REG_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_3_FUNC_SEL_POS)
#define GLB_REG_GPIO_3_FUNC_SEL_UMSK \
- (~(((1U << GLB_REG_GPIO_3_FUNC_SEL_LEN) - 1) \
- << GLB_REG_GPIO_3_FUNC_SEL_POS))
+ (~(((1 << GLB_REG_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_3_FUNC_SEL_POS))
#define GLB_REAL_GPIO_3_FUNC_SEL GLB_REAL_GPIO_3_FUNC_SEL
-#define GLB_REAL_GPIO_3_FUNC_SEL_POS (28U)
-#define GLB_REAL_GPIO_3_FUNC_SEL_LEN (4U)
+#define GLB_REAL_GPIO_3_FUNC_SEL_POS (28)
+#define GLB_REAL_GPIO_3_FUNC_SEL_LEN (4)
#define GLB_REAL_GPIO_3_FUNC_SEL_MSK \
- (((1U << GLB_REAL_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_3_FUNC_SEL_POS)
+ (((1 << GLB_REAL_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_3_FUNC_SEL_POS)
#define GLB_REAL_GPIO_3_FUNC_SEL_UMSK \
- (~(((1U << GLB_REAL_GPIO_3_FUNC_SEL_LEN) - 1) \
+ (~(((1 << GLB_REAL_GPIO_3_FUNC_SEL_LEN) - 1) \
<< GLB_REAL_GPIO_3_FUNC_SEL_POS))
/* 0x108 : GPIO_CFGCTL2 */
#define GLB_GPIO_CFGCTL2_OFFSET (0x108)
#define GLB_REG_GPIO_4_IE GLB_REG_GPIO_4_IE
-#define GLB_REG_GPIO_4_IE_POS (0U)
-#define GLB_REG_GPIO_4_IE_LEN (1U)
+#define GLB_REG_GPIO_4_IE_POS (0)
+#define GLB_REG_GPIO_4_IE_LEN (1)
#define GLB_REG_GPIO_4_IE_MSK \
- (((1U << GLB_REG_GPIO_4_IE_LEN) - 1) << GLB_REG_GPIO_4_IE_POS)
+ (((1 << GLB_REG_GPIO_4_IE_LEN) - 1) << GLB_REG_GPIO_4_IE_POS)
#define GLB_REG_GPIO_4_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_4_IE_LEN) - 1) << GLB_REG_GPIO_4_IE_POS))
+ (~(((1 << GLB_REG_GPIO_4_IE_LEN) - 1) << GLB_REG_GPIO_4_IE_POS))
#define GLB_REG_GPIO_4_SMT GLB_REG_GPIO_4_SMT
-#define GLB_REG_GPIO_4_SMT_POS (1U)
-#define GLB_REG_GPIO_4_SMT_LEN (1U)
+#define GLB_REG_GPIO_4_SMT_POS (1)
+#define GLB_REG_GPIO_4_SMT_LEN (1)
#define GLB_REG_GPIO_4_SMT_MSK \
- (((1U << GLB_REG_GPIO_4_SMT_LEN) - 1) << GLB_REG_GPIO_4_SMT_POS)
+ (((1 << GLB_REG_GPIO_4_SMT_LEN) - 1) << GLB_REG_GPIO_4_SMT_POS)
#define GLB_REG_GPIO_4_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_4_SMT_LEN) - 1) << GLB_REG_GPIO_4_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_4_SMT_LEN) - 1) << GLB_REG_GPIO_4_SMT_POS))
#define GLB_REG_GPIO_4_DRV GLB_REG_GPIO_4_DRV
-#define GLB_REG_GPIO_4_DRV_POS (2U)
-#define GLB_REG_GPIO_4_DRV_LEN (2U)
+#define GLB_REG_GPIO_4_DRV_POS (2)
+#define GLB_REG_GPIO_4_DRV_LEN (2)
#define GLB_REG_GPIO_4_DRV_MSK \
- (((1U << GLB_REG_GPIO_4_DRV_LEN) - 1) << GLB_REG_GPIO_4_DRV_POS)
+ (((1 << GLB_REG_GPIO_4_DRV_LEN) - 1) << GLB_REG_GPIO_4_DRV_POS)
#define GLB_REG_GPIO_4_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_4_DRV_LEN) - 1) << GLB_REG_GPIO_4_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_4_DRV_LEN) - 1) << GLB_REG_GPIO_4_DRV_POS))
#define GLB_REG_GPIO_4_PU GLB_REG_GPIO_4_PU
-#define GLB_REG_GPIO_4_PU_POS (4U)
-#define GLB_REG_GPIO_4_PU_LEN (1U)
+#define GLB_REG_GPIO_4_PU_POS (4)
+#define GLB_REG_GPIO_4_PU_LEN (1)
#define GLB_REG_GPIO_4_PU_MSK \
- (((1U << GLB_REG_GPIO_4_PU_LEN) - 1) << GLB_REG_GPIO_4_PU_POS)
+ (((1 << GLB_REG_GPIO_4_PU_LEN) - 1) << GLB_REG_GPIO_4_PU_POS)
#define GLB_REG_GPIO_4_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_4_PU_LEN) - 1) << GLB_REG_GPIO_4_PU_POS))
+ (~(((1 << GLB_REG_GPIO_4_PU_LEN) - 1) << GLB_REG_GPIO_4_PU_POS))
#define GLB_REG_GPIO_4_PD GLB_REG_GPIO_4_PD
-#define GLB_REG_GPIO_4_PD_POS (5U)
-#define GLB_REG_GPIO_4_PD_LEN (1U)
+#define GLB_REG_GPIO_4_PD_POS (5)
+#define GLB_REG_GPIO_4_PD_LEN (1)
#define GLB_REG_GPIO_4_PD_MSK \
- (((1U << GLB_REG_GPIO_4_PD_LEN) - 1) << GLB_REG_GPIO_4_PD_POS)
+ (((1 << GLB_REG_GPIO_4_PD_LEN) - 1) << GLB_REG_GPIO_4_PD_POS)
#define GLB_REG_GPIO_4_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_4_PD_LEN) - 1) << GLB_REG_GPIO_4_PD_POS))
+ (~(((1 << GLB_REG_GPIO_4_PD_LEN) - 1) << GLB_REG_GPIO_4_PD_POS))
#define GLB_REG_GPIO_4_FUNC_SEL GLB_REG_GPIO_4_FUNC_SEL
-#define GLB_REG_GPIO_4_FUNC_SEL_POS (8U)
-#define GLB_REG_GPIO_4_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_4_FUNC_SEL_POS (8)
+#define GLB_REG_GPIO_4_FUNC_SEL_LEN (4)
#define GLB_REG_GPIO_4_FUNC_SEL_MSK \
- (((1U << GLB_REG_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_4_FUNC_SEL_POS)
+ (((1 << GLB_REG_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_4_FUNC_SEL_POS)
#define GLB_REG_GPIO_4_FUNC_SEL_UMSK \
- (~(((1U << GLB_REG_GPIO_4_FUNC_SEL_LEN) - 1) \
- << GLB_REG_GPIO_4_FUNC_SEL_POS))
+ (~(((1 << GLB_REG_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_4_FUNC_SEL_POS))
#define GLB_REAL_GPIO_4_FUNC_SEL GLB_REAL_GPIO_4_FUNC_SEL
-#define GLB_REAL_GPIO_4_FUNC_SEL_POS (12U)
-#define GLB_REAL_GPIO_4_FUNC_SEL_LEN (4U)
+#define GLB_REAL_GPIO_4_FUNC_SEL_POS (12)
+#define GLB_REAL_GPIO_4_FUNC_SEL_LEN (4)
#define GLB_REAL_GPIO_4_FUNC_SEL_MSK \
- (((1U << GLB_REAL_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_4_FUNC_SEL_POS)
+ (((1 << GLB_REAL_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_4_FUNC_SEL_POS)
#define GLB_REAL_GPIO_4_FUNC_SEL_UMSK \
- (~(((1U << GLB_REAL_GPIO_4_FUNC_SEL_LEN) - 1) \
+ (~(((1 << GLB_REAL_GPIO_4_FUNC_SEL_LEN) - 1) \
<< GLB_REAL_GPIO_4_FUNC_SEL_POS))
#define GLB_REG_GPIO_5_IE GLB_REG_GPIO_5_IE
-#define GLB_REG_GPIO_5_IE_POS (16U)
-#define GLB_REG_GPIO_5_IE_LEN (1U)
+#define GLB_REG_GPIO_5_IE_POS (16)
+#define GLB_REG_GPIO_5_IE_LEN (1)
#define GLB_REG_GPIO_5_IE_MSK \
- (((1U << GLB_REG_GPIO_5_IE_LEN) - 1) << GLB_REG_GPIO_5_IE_POS)
+ (((1 << GLB_REG_GPIO_5_IE_LEN) - 1) << GLB_REG_GPIO_5_IE_POS)
#define GLB_REG_GPIO_5_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_5_IE_LEN) - 1) << GLB_REG_GPIO_5_IE_POS))
+ (~(((1 << GLB_REG_GPIO_5_IE_LEN) - 1) << GLB_REG_GPIO_5_IE_POS))
#define GLB_REG_GPIO_5_SMT GLB_REG_GPIO_5_SMT
-#define GLB_REG_GPIO_5_SMT_POS (17U)
-#define GLB_REG_GPIO_5_SMT_LEN (1U)
+#define GLB_REG_GPIO_5_SMT_POS (17)
+#define GLB_REG_GPIO_5_SMT_LEN (1)
#define GLB_REG_GPIO_5_SMT_MSK \
- (((1U << GLB_REG_GPIO_5_SMT_LEN) - 1) << GLB_REG_GPIO_5_SMT_POS)
+ (((1 << GLB_REG_GPIO_5_SMT_LEN) - 1) << GLB_REG_GPIO_5_SMT_POS)
#define GLB_REG_GPIO_5_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_5_SMT_LEN) - 1) << GLB_REG_GPIO_5_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_5_SMT_LEN) - 1) << GLB_REG_GPIO_5_SMT_POS))
#define GLB_REG_GPIO_5_DRV GLB_REG_GPIO_5_DRV
-#define GLB_REG_GPIO_5_DRV_POS (18U)
-#define GLB_REG_GPIO_5_DRV_LEN (2U)
+#define GLB_REG_GPIO_5_DRV_POS (18)
+#define GLB_REG_GPIO_5_DRV_LEN (2)
#define GLB_REG_GPIO_5_DRV_MSK \
- (((1U << GLB_REG_GPIO_5_DRV_LEN) - 1) << GLB_REG_GPIO_5_DRV_POS)
+ (((1 << GLB_REG_GPIO_5_DRV_LEN) - 1) << GLB_REG_GPIO_5_DRV_POS)
#define GLB_REG_GPIO_5_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_5_DRV_LEN) - 1) << GLB_REG_GPIO_5_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_5_DRV_LEN) - 1) << GLB_REG_GPIO_5_DRV_POS))
#define GLB_REG_GPIO_5_PU GLB_REG_GPIO_5_PU
-#define GLB_REG_GPIO_5_PU_POS (20U)
-#define GLB_REG_GPIO_5_PU_LEN (1U)
+#define GLB_REG_GPIO_5_PU_POS (20)
+#define GLB_REG_GPIO_5_PU_LEN (1)
#define GLB_REG_GPIO_5_PU_MSK \
- (((1U << GLB_REG_GPIO_5_PU_LEN) - 1) << GLB_REG_GPIO_5_PU_POS)
+ (((1 << GLB_REG_GPIO_5_PU_LEN) - 1) << GLB_REG_GPIO_5_PU_POS)
#define GLB_REG_GPIO_5_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_5_PU_LEN) - 1) << GLB_REG_GPIO_5_PU_POS))
+ (~(((1 << GLB_REG_GPIO_5_PU_LEN) - 1) << GLB_REG_GPIO_5_PU_POS))
#define GLB_REG_GPIO_5_PD GLB_REG_GPIO_5_PD
-#define GLB_REG_GPIO_5_PD_POS (21U)
-#define GLB_REG_GPIO_5_PD_LEN (1U)
+#define GLB_REG_GPIO_5_PD_POS (21)
+#define GLB_REG_GPIO_5_PD_LEN (1)
#define GLB_REG_GPIO_5_PD_MSK \
- (((1U << GLB_REG_GPIO_5_PD_LEN) - 1) << GLB_REG_GPIO_5_PD_POS)
+ (((1 << GLB_REG_GPIO_5_PD_LEN) - 1) << GLB_REG_GPIO_5_PD_POS)
#define GLB_REG_GPIO_5_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_5_PD_LEN) - 1) << GLB_REG_GPIO_5_PD_POS))
+ (~(((1 << GLB_REG_GPIO_5_PD_LEN) - 1) << GLB_REG_GPIO_5_PD_POS))
#define GLB_REG_GPIO_5_FUNC_SEL GLB_REG_GPIO_5_FUNC_SEL
-#define GLB_REG_GPIO_5_FUNC_SEL_POS (24U)
-#define GLB_REG_GPIO_5_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_5_FUNC_SEL_POS (24)
+#define GLB_REG_GPIO_5_FUNC_SEL_LEN (4)
#define GLB_REG_GPIO_5_FUNC_SEL_MSK \
- (((1U << GLB_REG_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_5_FUNC_SEL_POS)
+ (((1 << GLB_REG_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_5_FUNC_SEL_POS)
#define GLB_REG_GPIO_5_FUNC_SEL_UMSK \
- (~(((1U << GLB_REG_GPIO_5_FUNC_SEL_LEN) - 1) \
- << GLB_REG_GPIO_5_FUNC_SEL_POS))
+ (~(((1 << GLB_REG_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_5_FUNC_SEL_POS))
#define GLB_REAL_GPIO_5_FUNC_SEL GLB_REAL_GPIO_5_FUNC_SEL
-#define GLB_REAL_GPIO_5_FUNC_SEL_POS (28U)
-#define GLB_REAL_GPIO_5_FUNC_SEL_LEN (4U)
+#define GLB_REAL_GPIO_5_FUNC_SEL_POS (28)
+#define GLB_REAL_GPIO_5_FUNC_SEL_LEN (4)
#define GLB_REAL_GPIO_5_FUNC_SEL_MSK \
- (((1U << GLB_REAL_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_5_FUNC_SEL_POS)
+ (((1 << GLB_REAL_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_5_FUNC_SEL_POS)
#define GLB_REAL_GPIO_5_FUNC_SEL_UMSK \
- (~(((1U << GLB_REAL_GPIO_5_FUNC_SEL_LEN) - 1) \
+ (~(((1 << GLB_REAL_GPIO_5_FUNC_SEL_LEN) - 1) \
<< GLB_REAL_GPIO_5_FUNC_SEL_POS))
/* 0x10C : GPIO_CFGCTL3 */
#define GLB_GPIO_CFGCTL3_OFFSET (0x10C)
#define GLB_REG_GPIO_6_IE GLB_REG_GPIO_6_IE
-#define GLB_REG_GPIO_6_IE_POS (0U)
-#define GLB_REG_GPIO_6_IE_LEN (1U)
+#define GLB_REG_GPIO_6_IE_POS (0)
+#define GLB_REG_GPIO_6_IE_LEN (1)
#define GLB_REG_GPIO_6_IE_MSK \
- (((1U << GLB_REG_GPIO_6_IE_LEN) - 1) << GLB_REG_GPIO_6_IE_POS)
+ (((1 << GLB_REG_GPIO_6_IE_LEN) - 1) << GLB_REG_GPIO_6_IE_POS)
#define GLB_REG_GPIO_6_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_6_IE_LEN) - 1) << GLB_REG_GPIO_6_IE_POS))
+ (~(((1 << GLB_REG_GPIO_6_IE_LEN) - 1) << GLB_REG_GPIO_6_IE_POS))
#define GLB_REG_GPIO_6_SMT GLB_REG_GPIO_6_SMT
-#define GLB_REG_GPIO_6_SMT_POS (1U)
-#define GLB_REG_GPIO_6_SMT_LEN (1U)
+#define GLB_REG_GPIO_6_SMT_POS (1)
+#define GLB_REG_GPIO_6_SMT_LEN (1)
#define GLB_REG_GPIO_6_SMT_MSK \
- (((1U << GLB_REG_GPIO_6_SMT_LEN) - 1) << GLB_REG_GPIO_6_SMT_POS)
+ (((1 << GLB_REG_GPIO_6_SMT_LEN) - 1) << GLB_REG_GPIO_6_SMT_POS)
#define GLB_REG_GPIO_6_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_6_SMT_LEN) - 1) << GLB_REG_GPIO_6_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_6_SMT_LEN) - 1) << GLB_REG_GPIO_6_SMT_POS))
#define GLB_REG_GPIO_6_DRV GLB_REG_GPIO_6_DRV
-#define GLB_REG_GPIO_6_DRV_POS (2U)
-#define GLB_REG_GPIO_6_DRV_LEN (2U)
+#define GLB_REG_GPIO_6_DRV_POS (2)
+#define GLB_REG_GPIO_6_DRV_LEN (2)
#define GLB_REG_GPIO_6_DRV_MSK \
- (((1U << GLB_REG_GPIO_6_DRV_LEN) - 1) << GLB_REG_GPIO_6_DRV_POS)
+ (((1 << GLB_REG_GPIO_6_DRV_LEN) - 1) << GLB_REG_GPIO_6_DRV_POS)
#define GLB_REG_GPIO_6_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_6_DRV_LEN) - 1) << GLB_REG_GPIO_6_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_6_DRV_LEN) - 1) << GLB_REG_GPIO_6_DRV_POS))
#define GLB_REG_GPIO_6_PU GLB_REG_GPIO_6_PU
-#define GLB_REG_GPIO_6_PU_POS (4U)
-#define GLB_REG_GPIO_6_PU_LEN (1U)
+#define GLB_REG_GPIO_6_PU_POS (4)
+#define GLB_REG_GPIO_6_PU_LEN (1)
#define GLB_REG_GPIO_6_PU_MSK \
- (((1U << GLB_REG_GPIO_6_PU_LEN) - 1) << GLB_REG_GPIO_6_PU_POS)
+ (((1 << GLB_REG_GPIO_6_PU_LEN) - 1) << GLB_REG_GPIO_6_PU_POS)
#define GLB_REG_GPIO_6_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_6_PU_LEN) - 1) << GLB_REG_GPIO_6_PU_POS))
+ (~(((1 << GLB_REG_GPIO_6_PU_LEN) - 1) << GLB_REG_GPIO_6_PU_POS))
#define GLB_REG_GPIO_6_PD GLB_REG_GPIO_6_PD
-#define GLB_REG_GPIO_6_PD_POS (5U)
-#define GLB_REG_GPIO_6_PD_LEN (1U)
+#define GLB_REG_GPIO_6_PD_POS (5)
+#define GLB_REG_GPIO_6_PD_LEN (1)
#define GLB_REG_GPIO_6_PD_MSK \
- (((1U << GLB_REG_GPIO_6_PD_LEN) - 1) << GLB_REG_GPIO_6_PD_POS)
+ (((1 << GLB_REG_GPIO_6_PD_LEN) - 1) << GLB_REG_GPIO_6_PD_POS)
#define GLB_REG_GPIO_6_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_6_PD_LEN) - 1) << GLB_REG_GPIO_6_PD_POS))
+ (~(((1 << GLB_REG_GPIO_6_PD_LEN) - 1) << GLB_REG_GPIO_6_PD_POS))
#define GLB_REG_GPIO_6_FUNC_SEL GLB_REG_GPIO_6_FUNC_SEL
-#define GLB_REG_GPIO_6_FUNC_SEL_POS (8U)
-#define GLB_REG_GPIO_6_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_6_FUNC_SEL_POS (8)
+#define GLB_REG_GPIO_6_FUNC_SEL_LEN (4)
#define GLB_REG_GPIO_6_FUNC_SEL_MSK \
- (((1U << GLB_REG_GPIO_6_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_6_FUNC_SEL_POS)
+ (((1 << GLB_REG_GPIO_6_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_6_FUNC_SEL_POS)
#define GLB_REG_GPIO_6_FUNC_SEL_UMSK \
- (~(((1U << GLB_REG_GPIO_6_FUNC_SEL_LEN) - 1) \
- << GLB_REG_GPIO_6_FUNC_SEL_POS))
+ (~(((1 << GLB_REG_GPIO_6_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_6_FUNC_SEL_POS))
#define GLB_REG_GPIO_7_IE GLB_REG_GPIO_7_IE
-#define GLB_REG_GPIO_7_IE_POS (16U)
-#define GLB_REG_GPIO_7_IE_LEN (1U)
+#define GLB_REG_GPIO_7_IE_POS (16)
+#define GLB_REG_GPIO_7_IE_LEN (1)
#define GLB_REG_GPIO_7_IE_MSK \
- (((1U << GLB_REG_GPIO_7_IE_LEN) - 1) << GLB_REG_GPIO_7_IE_POS)
+ (((1 << GLB_REG_GPIO_7_IE_LEN) - 1) << GLB_REG_GPIO_7_IE_POS)
#define GLB_REG_GPIO_7_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_7_IE_LEN) - 1) << GLB_REG_GPIO_7_IE_POS))
+ (~(((1 << GLB_REG_GPIO_7_IE_LEN) - 1) << GLB_REG_GPIO_7_IE_POS))
#define GLB_REG_GPIO_7_SMT GLB_REG_GPIO_7_SMT
-#define GLB_REG_GPIO_7_SMT_POS (17U)
-#define GLB_REG_GPIO_7_SMT_LEN (1U)
+#define GLB_REG_GPIO_7_SMT_POS (17)
+#define GLB_REG_GPIO_7_SMT_LEN (1)
#define GLB_REG_GPIO_7_SMT_MSK \
- (((1U << GLB_REG_GPIO_7_SMT_LEN) - 1) << GLB_REG_GPIO_7_SMT_POS)
+ (((1 << GLB_REG_GPIO_7_SMT_LEN) - 1) << GLB_REG_GPIO_7_SMT_POS)
#define GLB_REG_GPIO_7_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_7_SMT_LEN) - 1) << GLB_REG_GPIO_7_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_7_SMT_LEN) - 1) << GLB_REG_GPIO_7_SMT_POS))
#define GLB_REG_GPIO_7_DRV GLB_REG_GPIO_7_DRV
-#define GLB_REG_GPIO_7_DRV_POS (18U)
-#define GLB_REG_GPIO_7_DRV_LEN (2U)
+#define GLB_REG_GPIO_7_DRV_POS (18)
+#define GLB_REG_GPIO_7_DRV_LEN (2)
#define GLB_REG_GPIO_7_DRV_MSK \
- (((1U << GLB_REG_GPIO_7_DRV_LEN) - 1) << GLB_REG_GPIO_7_DRV_POS)
+ (((1 << GLB_REG_GPIO_7_DRV_LEN) - 1) << GLB_REG_GPIO_7_DRV_POS)
#define GLB_REG_GPIO_7_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_7_DRV_LEN) - 1) << GLB_REG_GPIO_7_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_7_DRV_LEN) - 1) << GLB_REG_GPIO_7_DRV_POS))
#define GLB_REG_GPIO_7_PU GLB_REG_GPIO_7_PU
-#define GLB_REG_GPIO_7_PU_POS (20U)
-#define GLB_REG_GPIO_7_PU_LEN (1U)
+#define GLB_REG_GPIO_7_PU_POS (20)
+#define GLB_REG_GPIO_7_PU_LEN (1)
#define GLB_REG_GPIO_7_PU_MSK \
- (((1U << GLB_REG_GPIO_7_PU_LEN) - 1) << GLB_REG_GPIO_7_PU_POS)
+ (((1 << GLB_REG_GPIO_7_PU_LEN) - 1) << GLB_REG_GPIO_7_PU_POS)
#define GLB_REG_GPIO_7_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_7_PU_LEN) - 1) << GLB_REG_GPIO_7_PU_POS))
+ (~(((1 << GLB_REG_GPIO_7_PU_LEN) - 1) << GLB_REG_GPIO_7_PU_POS))
#define GLB_REG_GPIO_7_PD GLB_REG_GPIO_7_PD
-#define GLB_REG_GPIO_7_PD_POS (21U)
-#define GLB_REG_GPIO_7_PD_LEN (1U)
+#define GLB_REG_GPIO_7_PD_POS (21)
+#define GLB_REG_GPIO_7_PD_LEN (1)
#define GLB_REG_GPIO_7_PD_MSK \
- (((1U << GLB_REG_GPIO_7_PD_LEN) - 1) << GLB_REG_GPIO_7_PD_POS)
+ (((1 << GLB_REG_GPIO_7_PD_LEN) - 1) << GLB_REG_GPIO_7_PD_POS)
#define GLB_REG_GPIO_7_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_7_PD_LEN) - 1) << GLB_REG_GPIO_7_PD_POS))
+ (~(((1 << GLB_REG_GPIO_7_PD_LEN) - 1) << GLB_REG_GPIO_7_PD_POS))
#define GLB_REG_GPIO_7_FUNC_SEL GLB_REG_GPIO_7_FUNC_SEL
-#define GLB_REG_GPIO_7_FUNC_SEL_POS (24U)
-#define GLB_REG_GPIO_7_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_7_FUNC_SEL_POS (24)
+#define GLB_REG_GPIO_7_FUNC_SEL_LEN (4)
#define GLB_REG_GPIO_7_FUNC_SEL_MSK \
- (((1U << GLB_REG_GPIO_7_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_7_FUNC_SEL_POS)
+ (((1 << GLB_REG_GPIO_7_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_7_FUNC_SEL_POS)
#define GLB_REG_GPIO_7_FUNC_SEL_UMSK \
- (~(((1U << GLB_REG_GPIO_7_FUNC_SEL_LEN) - 1) \
- << GLB_REG_GPIO_7_FUNC_SEL_POS))
+ (~(((1 << GLB_REG_GPIO_7_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_7_FUNC_SEL_POS))
/* 0x110 : GPIO_CFGCTL4 */
#define GLB_GPIO_CFGCTL4_OFFSET (0x110)
#define GLB_REG_GPIO_8_IE GLB_REG_GPIO_8_IE
-#define GLB_REG_GPIO_8_IE_POS (0U)
-#define GLB_REG_GPIO_8_IE_LEN (1U)
+#define GLB_REG_GPIO_8_IE_POS (0)
+#define GLB_REG_GPIO_8_IE_LEN (1)
#define GLB_REG_GPIO_8_IE_MSK \
- (((1U << GLB_REG_GPIO_8_IE_LEN) - 1) << GLB_REG_GPIO_8_IE_POS)
+ (((1 << GLB_REG_GPIO_8_IE_LEN) - 1) << GLB_REG_GPIO_8_IE_POS)
#define GLB_REG_GPIO_8_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_8_IE_LEN) - 1) << GLB_REG_GPIO_8_IE_POS))
+ (~(((1 << GLB_REG_GPIO_8_IE_LEN) - 1) << GLB_REG_GPIO_8_IE_POS))
#define GLB_REG_GPIO_8_SMT GLB_REG_GPIO_8_SMT
-#define GLB_REG_GPIO_8_SMT_POS (1U)
-#define GLB_REG_GPIO_8_SMT_LEN (1U)
+#define GLB_REG_GPIO_8_SMT_POS (1)
+#define GLB_REG_GPIO_8_SMT_LEN (1)
#define GLB_REG_GPIO_8_SMT_MSK \
- (((1U << GLB_REG_GPIO_8_SMT_LEN) - 1) << GLB_REG_GPIO_8_SMT_POS)
+ (((1 << GLB_REG_GPIO_8_SMT_LEN) - 1) << GLB_REG_GPIO_8_SMT_POS)
#define GLB_REG_GPIO_8_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_8_SMT_LEN) - 1) << GLB_REG_GPIO_8_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_8_SMT_LEN) - 1) << GLB_REG_GPIO_8_SMT_POS))
#define GLB_REG_GPIO_8_DRV GLB_REG_GPIO_8_DRV
-#define GLB_REG_GPIO_8_DRV_POS (2U)
-#define GLB_REG_GPIO_8_DRV_LEN (2U)
+#define GLB_REG_GPIO_8_DRV_POS (2)
+#define GLB_REG_GPIO_8_DRV_LEN (2)
#define GLB_REG_GPIO_8_DRV_MSK \
- (((1U << GLB_REG_GPIO_8_DRV_LEN) - 1) << GLB_REG_GPIO_8_DRV_POS)
+ (((1 << GLB_REG_GPIO_8_DRV_LEN) - 1) << GLB_REG_GPIO_8_DRV_POS)
#define GLB_REG_GPIO_8_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_8_DRV_LEN) - 1) << GLB_REG_GPIO_8_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_8_DRV_LEN) - 1) << GLB_REG_GPIO_8_DRV_POS))
#define GLB_REG_GPIO_8_PU GLB_REG_GPIO_8_PU
-#define GLB_REG_GPIO_8_PU_POS (4U)
-#define GLB_REG_GPIO_8_PU_LEN (1U)
+#define GLB_REG_GPIO_8_PU_POS (4)
+#define GLB_REG_GPIO_8_PU_LEN (1)
#define GLB_REG_GPIO_8_PU_MSK \
- (((1U << GLB_REG_GPIO_8_PU_LEN) - 1) << GLB_REG_GPIO_8_PU_POS)
+ (((1 << GLB_REG_GPIO_8_PU_LEN) - 1) << GLB_REG_GPIO_8_PU_POS)
#define GLB_REG_GPIO_8_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_8_PU_LEN) - 1) << GLB_REG_GPIO_8_PU_POS))
+ (~(((1 << GLB_REG_GPIO_8_PU_LEN) - 1) << GLB_REG_GPIO_8_PU_POS))
#define GLB_REG_GPIO_8_PD GLB_REG_GPIO_8_PD
-#define GLB_REG_GPIO_8_PD_POS (5U)
-#define GLB_REG_GPIO_8_PD_LEN (1U)
+#define GLB_REG_GPIO_8_PD_POS (5)
+#define GLB_REG_GPIO_8_PD_LEN (1)
#define GLB_REG_GPIO_8_PD_MSK \
- (((1U << GLB_REG_GPIO_8_PD_LEN) - 1) << GLB_REG_GPIO_8_PD_POS)
+ (((1 << GLB_REG_GPIO_8_PD_LEN) - 1) << GLB_REG_GPIO_8_PD_POS)
#define GLB_REG_GPIO_8_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_8_PD_LEN) - 1) << GLB_REG_GPIO_8_PD_POS))
+ (~(((1 << GLB_REG_GPIO_8_PD_LEN) - 1) << GLB_REG_GPIO_8_PD_POS))
#define GLB_REG_GPIO_8_FUNC_SEL GLB_REG_GPIO_8_FUNC_SEL
-#define GLB_REG_GPIO_8_FUNC_SEL_POS (8U)
-#define GLB_REG_GPIO_8_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_8_FUNC_SEL_POS (8)
+#define GLB_REG_GPIO_8_FUNC_SEL_LEN (4)
#define GLB_REG_GPIO_8_FUNC_SEL_MSK \
- (((1U << GLB_REG_GPIO_8_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_8_FUNC_SEL_POS)
+ (((1 << GLB_REG_GPIO_8_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_8_FUNC_SEL_POS)
#define GLB_REG_GPIO_8_FUNC_SEL_UMSK \
- (~(((1U << GLB_REG_GPIO_8_FUNC_SEL_LEN) - 1) \
- << GLB_REG_GPIO_8_FUNC_SEL_POS))
+ (~(((1 << GLB_REG_GPIO_8_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_8_FUNC_SEL_POS))
#define GLB_REG_GPIO_9_IE GLB_REG_GPIO_9_IE
-#define GLB_REG_GPIO_9_IE_POS (16U)
-#define GLB_REG_GPIO_9_IE_LEN (1U)
+#define GLB_REG_GPIO_9_IE_POS (16)
+#define GLB_REG_GPIO_9_IE_LEN (1)
#define GLB_REG_GPIO_9_IE_MSK \
- (((1U << GLB_REG_GPIO_9_IE_LEN) - 1) << GLB_REG_GPIO_9_IE_POS)
+ (((1 << GLB_REG_GPIO_9_IE_LEN) - 1) << GLB_REG_GPIO_9_IE_POS)
#define GLB_REG_GPIO_9_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_9_IE_LEN) - 1) << GLB_REG_GPIO_9_IE_POS))
+ (~(((1 << GLB_REG_GPIO_9_IE_LEN) - 1) << GLB_REG_GPIO_9_IE_POS))
#define GLB_REG_GPIO_9_SMT GLB_REG_GPIO_9_SMT
-#define GLB_REG_GPIO_9_SMT_POS (17U)
-#define GLB_REG_GPIO_9_SMT_LEN (1U)
+#define GLB_REG_GPIO_9_SMT_POS (17)
+#define GLB_REG_GPIO_9_SMT_LEN (1)
#define GLB_REG_GPIO_9_SMT_MSK \
- (((1U << GLB_REG_GPIO_9_SMT_LEN) - 1) << GLB_REG_GPIO_9_SMT_POS)
+ (((1 << GLB_REG_GPIO_9_SMT_LEN) - 1) << GLB_REG_GPIO_9_SMT_POS)
#define GLB_REG_GPIO_9_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_9_SMT_LEN) - 1) << GLB_REG_GPIO_9_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_9_SMT_LEN) - 1) << GLB_REG_GPIO_9_SMT_POS))
#define GLB_REG_GPIO_9_DRV GLB_REG_GPIO_9_DRV
-#define GLB_REG_GPIO_9_DRV_POS (18U)
-#define GLB_REG_GPIO_9_DRV_LEN (2U)
+#define GLB_REG_GPIO_9_DRV_POS (18)
+#define GLB_REG_GPIO_9_DRV_LEN (2)
#define GLB_REG_GPIO_9_DRV_MSK \
- (((1U << GLB_REG_GPIO_9_DRV_LEN) - 1) << GLB_REG_GPIO_9_DRV_POS)
+ (((1 << GLB_REG_GPIO_9_DRV_LEN) - 1) << GLB_REG_GPIO_9_DRV_POS)
#define GLB_REG_GPIO_9_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_9_DRV_LEN) - 1) << GLB_REG_GPIO_9_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_9_DRV_LEN) - 1) << GLB_REG_GPIO_9_DRV_POS))
#define GLB_REG_GPIO_9_PU GLB_REG_GPIO_9_PU
-#define GLB_REG_GPIO_9_PU_POS (20U)
-#define GLB_REG_GPIO_9_PU_LEN (1U)
+#define GLB_REG_GPIO_9_PU_POS (20)
+#define GLB_REG_GPIO_9_PU_LEN (1)
#define GLB_REG_GPIO_9_PU_MSK \
- (((1U << GLB_REG_GPIO_9_PU_LEN) - 1) << GLB_REG_GPIO_9_PU_POS)
+ (((1 << GLB_REG_GPIO_9_PU_LEN) - 1) << GLB_REG_GPIO_9_PU_POS)
#define GLB_REG_GPIO_9_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_9_PU_LEN) - 1) << GLB_REG_GPIO_9_PU_POS))
+ (~(((1 << GLB_REG_GPIO_9_PU_LEN) - 1) << GLB_REG_GPIO_9_PU_POS))
#define GLB_REG_GPIO_9_PD GLB_REG_GPIO_9_PD
-#define GLB_REG_GPIO_9_PD_POS (21U)
-#define GLB_REG_GPIO_9_PD_LEN (1U)
+#define GLB_REG_GPIO_9_PD_POS (21)
+#define GLB_REG_GPIO_9_PD_LEN (1)
#define GLB_REG_GPIO_9_PD_MSK \
- (((1U << GLB_REG_GPIO_9_PD_LEN) - 1) << GLB_REG_GPIO_9_PD_POS)
+ (((1 << GLB_REG_GPIO_9_PD_LEN) - 1) << GLB_REG_GPIO_9_PD_POS)
#define GLB_REG_GPIO_9_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_9_PD_LEN) - 1) << GLB_REG_GPIO_9_PD_POS))
+ (~(((1 << GLB_REG_GPIO_9_PD_LEN) - 1) << GLB_REG_GPIO_9_PD_POS))
#define GLB_REG_GPIO_9_FUNC_SEL GLB_REG_GPIO_9_FUNC_SEL
-#define GLB_REG_GPIO_9_FUNC_SEL_POS (24U)
-#define GLB_REG_GPIO_9_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_9_FUNC_SEL_POS (24)
+#define GLB_REG_GPIO_9_FUNC_SEL_LEN (4)
#define GLB_REG_GPIO_9_FUNC_SEL_MSK \
- (((1U << GLB_REG_GPIO_9_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_9_FUNC_SEL_POS)
+ (((1 << GLB_REG_GPIO_9_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_9_FUNC_SEL_POS)
#define GLB_REG_GPIO_9_FUNC_SEL_UMSK \
- (~(((1U << GLB_REG_GPIO_9_FUNC_SEL_LEN) - 1) \
- << GLB_REG_GPIO_9_FUNC_SEL_POS))
+ (~(((1 << GLB_REG_GPIO_9_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_9_FUNC_SEL_POS))
/* 0x114 : GPIO_CFGCTL5 */
#define GLB_GPIO_CFGCTL5_OFFSET (0x114)
#define GLB_REG_GPIO_10_IE GLB_REG_GPIO_10_IE
-#define GLB_REG_GPIO_10_IE_POS (0U)
-#define GLB_REG_GPIO_10_IE_LEN (1U)
+#define GLB_REG_GPIO_10_IE_POS (0)
+#define GLB_REG_GPIO_10_IE_LEN (1)
#define GLB_REG_GPIO_10_IE_MSK \
- (((1U << GLB_REG_GPIO_10_IE_LEN) - 1) << GLB_REG_GPIO_10_IE_POS)
+ (((1 << GLB_REG_GPIO_10_IE_LEN) - 1) << GLB_REG_GPIO_10_IE_POS)
#define GLB_REG_GPIO_10_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_10_IE_LEN) - 1) << GLB_REG_GPIO_10_IE_POS))
+ (~(((1 << GLB_REG_GPIO_10_IE_LEN) - 1) << GLB_REG_GPIO_10_IE_POS))
#define GLB_REG_GPIO_10_SMT GLB_REG_GPIO_10_SMT
-#define GLB_REG_GPIO_10_SMT_POS (1U)
-#define GLB_REG_GPIO_10_SMT_LEN (1U)
+#define GLB_REG_GPIO_10_SMT_POS (1)
+#define GLB_REG_GPIO_10_SMT_LEN (1)
#define GLB_REG_GPIO_10_SMT_MSK \
- (((1U << GLB_REG_GPIO_10_SMT_LEN) - 1) << GLB_REG_GPIO_10_SMT_POS)
+ (((1 << GLB_REG_GPIO_10_SMT_LEN) - 1) << GLB_REG_GPIO_10_SMT_POS)
#define GLB_REG_GPIO_10_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_10_SMT_LEN) - 1) << GLB_REG_GPIO_10_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_10_SMT_LEN) - 1) << GLB_REG_GPIO_10_SMT_POS))
#define GLB_REG_GPIO_10_DRV GLB_REG_GPIO_10_DRV
-#define GLB_REG_GPIO_10_DRV_POS (2U)
-#define GLB_REG_GPIO_10_DRV_LEN (2U)
+#define GLB_REG_GPIO_10_DRV_POS (2)
+#define GLB_REG_GPIO_10_DRV_LEN (2)
#define GLB_REG_GPIO_10_DRV_MSK \
- (((1U << GLB_REG_GPIO_10_DRV_LEN) - 1) << GLB_REG_GPIO_10_DRV_POS)
+ (((1 << GLB_REG_GPIO_10_DRV_LEN) - 1) << GLB_REG_GPIO_10_DRV_POS)
#define GLB_REG_GPIO_10_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_10_DRV_LEN) - 1) << GLB_REG_GPIO_10_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_10_DRV_LEN) - 1) << GLB_REG_GPIO_10_DRV_POS))
#define GLB_REG_GPIO_10_PU GLB_REG_GPIO_10_PU
-#define GLB_REG_GPIO_10_PU_POS (4U)
-#define GLB_REG_GPIO_10_PU_LEN (1U)
+#define GLB_REG_GPIO_10_PU_POS (4)
+#define GLB_REG_GPIO_10_PU_LEN (1)
#define GLB_REG_GPIO_10_PU_MSK \
- (((1U << GLB_REG_GPIO_10_PU_LEN) - 1) << GLB_REG_GPIO_10_PU_POS)
+ (((1 << GLB_REG_GPIO_10_PU_LEN) - 1) << GLB_REG_GPIO_10_PU_POS)
#define GLB_REG_GPIO_10_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_10_PU_LEN) - 1) << GLB_REG_GPIO_10_PU_POS))
+ (~(((1 << GLB_REG_GPIO_10_PU_LEN) - 1) << GLB_REG_GPIO_10_PU_POS))
#define GLB_REG_GPIO_10_PD GLB_REG_GPIO_10_PD
-#define GLB_REG_GPIO_10_PD_POS (5U)
-#define GLB_REG_GPIO_10_PD_LEN (1U)
+#define GLB_REG_GPIO_10_PD_POS (5)
+#define GLB_REG_GPIO_10_PD_LEN (1)
#define GLB_REG_GPIO_10_PD_MSK \
- (((1U << GLB_REG_GPIO_10_PD_LEN) - 1) << GLB_REG_GPIO_10_PD_POS)
+ (((1 << GLB_REG_GPIO_10_PD_LEN) - 1) << GLB_REG_GPIO_10_PD_POS)
#define GLB_REG_GPIO_10_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_10_PD_LEN) - 1) << GLB_REG_GPIO_10_PD_POS))
+ (~(((1 << GLB_REG_GPIO_10_PD_LEN) - 1) << GLB_REG_GPIO_10_PD_POS))
#define GLB_REG_GPIO_10_FUNC_SEL GLB_REG_GPIO_10_FUNC_SEL
-#define GLB_REG_GPIO_10_FUNC_SEL_POS (8U)
-#define GLB_REG_GPIO_10_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_10_FUNC_SEL_POS (8)
+#define GLB_REG_GPIO_10_FUNC_SEL_LEN (4)
#define GLB_REG_GPIO_10_FUNC_SEL_MSK \
- (((1U << GLB_REG_GPIO_10_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_10_FUNC_SEL_POS)
+ (((1 << GLB_REG_GPIO_10_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_10_FUNC_SEL_POS)
#define GLB_REG_GPIO_10_FUNC_SEL_UMSK \
- (~(((1U << GLB_REG_GPIO_10_FUNC_SEL_LEN) - 1) \
+ (~(((1 << GLB_REG_GPIO_10_FUNC_SEL_LEN) - 1) \
<< GLB_REG_GPIO_10_FUNC_SEL_POS))
#define GLB_REG_GPIO_11_IE GLB_REG_GPIO_11_IE
-#define GLB_REG_GPIO_11_IE_POS (16U)
-#define GLB_REG_GPIO_11_IE_LEN (1U)
+#define GLB_REG_GPIO_11_IE_POS (16)
+#define GLB_REG_GPIO_11_IE_LEN (1)
#define GLB_REG_GPIO_11_IE_MSK \
- (((1U << GLB_REG_GPIO_11_IE_LEN) - 1) << GLB_REG_GPIO_11_IE_POS)
+ (((1 << GLB_REG_GPIO_11_IE_LEN) - 1) << GLB_REG_GPIO_11_IE_POS)
#define GLB_REG_GPIO_11_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_11_IE_LEN) - 1) << GLB_REG_GPIO_11_IE_POS))
+ (~(((1 << GLB_REG_GPIO_11_IE_LEN) - 1) << GLB_REG_GPIO_11_IE_POS))
#define GLB_REG_GPIO_11_SMT GLB_REG_GPIO_11_SMT
-#define GLB_REG_GPIO_11_SMT_POS (17U)
-#define GLB_REG_GPIO_11_SMT_LEN (1U)
+#define GLB_REG_GPIO_11_SMT_POS (17)
+#define GLB_REG_GPIO_11_SMT_LEN (1)
#define GLB_REG_GPIO_11_SMT_MSK \
- (((1U << GLB_REG_GPIO_11_SMT_LEN) - 1) << GLB_REG_GPIO_11_SMT_POS)
+ (((1 << GLB_REG_GPIO_11_SMT_LEN) - 1) << GLB_REG_GPIO_11_SMT_POS)
#define GLB_REG_GPIO_11_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_11_SMT_LEN) - 1) << GLB_REG_GPIO_11_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_11_SMT_LEN) - 1) << GLB_REG_GPIO_11_SMT_POS))
#define GLB_REG_GPIO_11_DRV GLB_REG_GPIO_11_DRV
-#define GLB_REG_GPIO_11_DRV_POS (18U)
-#define GLB_REG_GPIO_11_DRV_LEN (2U)
+#define GLB_REG_GPIO_11_DRV_POS (18)
+#define GLB_REG_GPIO_11_DRV_LEN (2)
#define GLB_REG_GPIO_11_DRV_MSK \
- (((1U << GLB_REG_GPIO_11_DRV_LEN) - 1) << GLB_REG_GPIO_11_DRV_POS)
+ (((1 << GLB_REG_GPIO_11_DRV_LEN) - 1) << GLB_REG_GPIO_11_DRV_POS)
#define GLB_REG_GPIO_11_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_11_DRV_LEN) - 1) << GLB_REG_GPIO_11_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_11_DRV_LEN) - 1) << GLB_REG_GPIO_11_DRV_POS))
#define GLB_REG_GPIO_11_PU GLB_REG_GPIO_11_PU
-#define GLB_REG_GPIO_11_PU_POS (20U)
-#define GLB_REG_GPIO_11_PU_LEN (1U)
+#define GLB_REG_GPIO_11_PU_POS (20)
+#define GLB_REG_GPIO_11_PU_LEN (1)
#define GLB_REG_GPIO_11_PU_MSK \
- (((1U << GLB_REG_GPIO_11_PU_LEN) - 1) << GLB_REG_GPIO_11_PU_POS)
+ (((1 << GLB_REG_GPIO_11_PU_LEN) - 1) << GLB_REG_GPIO_11_PU_POS)
#define GLB_REG_GPIO_11_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_11_PU_LEN) - 1) << GLB_REG_GPIO_11_PU_POS))
+ (~(((1 << GLB_REG_GPIO_11_PU_LEN) - 1) << GLB_REG_GPIO_11_PU_POS))
#define GLB_REG_GPIO_11_PD GLB_REG_GPIO_11_PD
-#define GLB_REG_GPIO_11_PD_POS (21U)
-#define GLB_REG_GPIO_11_PD_LEN (1U)
+#define GLB_REG_GPIO_11_PD_POS (21)
+#define GLB_REG_GPIO_11_PD_LEN (1)
#define GLB_REG_GPIO_11_PD_MSK \
- (((1U << GLB_REG_GPIO_11_PD_LEN) - 1) << GLB_REG_GPIO_11_PD_POS)
+ (((1 << GLB_REG_GPIO_11_PD_LEN) - 1) << GLB_REG_GPIO_11_PD_POS)
#define GLB_REG_GPIO_11_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_11_PD_LEN) - 1) << GLB_REG_GPIO_11_PD_POS))
+ (~(((1 << GLB_REG_GPIO_11_PD_LEN) - 1) << GLB_REG_GPIO_11_PD_POS))
#define GLB_REG_GPIO_11_FUNC_SEL GLB_REG_GPIO_11_FUNC_SEL
-#define GLB_REG_GPIO_11_FUNC_SEL_POS (24U)
-#define GLB_REG_GPIO_11_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_11_FUNC_SEL_POS (24)
+#define GLB_REG_GPIO_11_FUNC_SEL_LEN (4)
#define GLB_REG_GPIO_11_FUNC_SEL_MSK \
- (((1U << GLB_REG_GPIO_11_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_11_FUNC_SEL_POS)
+ (((1 << GLB_REG_GPIO_11_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_11_FUNC_SEL_POS)
#define GLB_REG_GPIO_11_FUNC_SEL_UMSK \
- (~(((1U << GLB_REG_GPIO_11_FUNC_SEL_LEN) - 1) \
+ (~(((1 << GLB_REG_GPIO_11_FUNC_SEL_LEN) - 1) \
<< GLB_REG_GPIO_11_FUNC_SEL_POS))
/* 0x118 : GPIO_CFGCTL6 */
#define GLB_GPIO_CFGCTL6_OFFSET (0x118)
#define GLB_REG_GPIO_12_IE GLB_REG_GPIO_12_IE
-#define GLB_REG_GPIO_12_IE_POS (0U)
-#define GLB_REG_GPIO_12_IE_LEN (1U)
+#define GLB_REG_GPIO_12_IE_POS (0)
+#define GLB_REG_GPIO_12_IE_LEN (1)
#define GLB_REG_GPIO_12_IE_MSK \
- (((1U << GLB_REG_GPIO_12_IE_LEN) - 1) << GLB_REG_GPIO_12_IE_POS)
+ (((1 << GLB_REG_GPIO_12_IE_LEN) - 1) << GLB_REG_GPIO_12_IE_POS)
#define GLB_REG_GPIO_12_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_12_IE_LEN) - 1) << GLB_REG_GPIO_12_IE_POS))
+ (~(((1 << GLB_REG_GPIO_12_IE_LEN) - 1) << GLB_REG_GPIO_12_IE_POS))
#define GLB_REG_GPIO_12_SMT GLB_REG_GPIO_12_SMT
-#define GLB_REG_GPIO_12_SMT_POS (1U)
-#define GLB_REG_GPIO_12_SMT_LEN (1U)
+#define GLB_REG_GPIO_12_SMT_POS (1)
+#define GLB_REG_GPIO_12_SMT_LEN (1)
#define GLB_REG_GPIO_12_SMT_MSK \
- (((1U << GLB_REG_GPIO_12_SMT_LEN) - 1) << GLB_REG_GPIO_12_SMT_POS)
+ (((1 << GLB_REG_GPIO_12_SMT_LEN) - 1) << GLB_REG_GPIO_12_SMT_POS)
#define GLB_REG_GPIO_12_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_12_SMT_LEN) - 1) << GLB_REG_GPIO_12_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_12_SMT_LEN) - 1) << GLB_REG_GPIO_12_SMT_POS))
#define GLB_REG_GPIO_12_DRV GLB_REG_GPIO_12_DRV
-#define GLB_REG_GPIO_12_DRV_POS (2U)
-#define GLB_REG_GPIO_12_DRV_LEN (2U)
+#define GLB_REG_GPIO_12_DRV_POS (2)
+#define GLB_REG_GPIO_12_DRV_LEN (2)
#define GLB_REG_GPIO_12_DRV_MSK \
- (((1U << GLB_REG_GPIO_12_DRV_LEN) - 1) << GLB_REG_GPIO_12_DRV_POS)
+ (((1 << GLB_REG_GPIO_12_DRV_LEN) - 1) << GLB_REG_GPIO_12_DRV_POS)
#define GLB_REG_GPIO_12_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_12_DRV_LEN) - 1) << GLB_REG_GPIO_12_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_12_DRV_LEN) - 1) << GLB_REG_GPIO_12_DRV_POS))
#define GLB_REG_GPIO_12_PU GLB_REG_GPIO_12_PU
-#define GLB_REG_GPIO_12_PU_POS (4U)
-#define GLB_REG_GPIO_12_PU_LEN (1U)
+#define GLB_REG_GPIO_12_PU_POS (4)
+#define GLB_REG_GPIO_12_PU_LEN (1)
#define GLB_REG_GPIO_12_PU_MSK \
- (((1U << GLB_REG_GPIO_12_PU_LEN) - 1) << GLB_REG_GPIO_12_PU_POS)
+ (((1 << GLB_REG_GPIO_12_PU_LEN) - 1) << GLB_REG_GPIO_12_PU_POS)
#define GLB_REG_GPIO_12_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_12_PU_LEN) - 1) << GLB_REG_GPIO_12_PU_POS))
+ (~(((1 << GLB_REG_GPIO_12_PU_LEN) - 1) << GLB_REG_GPIO_12_PU_POS))
#define GLB_REG_GPIO_12_PD GLB_REG_GPIO_12_PD
-#define GLB_REG_GPIO_12_PD_POS (5U)
-#define GLB_REG_GPIO_12_PD_LEN (1U)
+#define GLB_REG_GPIO_12_PD_POS (5)
+#define GLB_REG_GPIO_12_PD_LEN (1)
#define GLB_REG_GPIO_12_PD_MSK \
- (((1U << GLB_REG_GPIO_12_PD_LEN) - 1) << GLB_REG_GPIO_12_PD_POS)
+ (((1 << GLB_REG_GPIO_12_PD_LEN) - 1) << GLB_REG_GPIO_12_PD_POS)
#define GLB_REG_GPIO_12_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_12_PD_LEN) - 1) << GLB_REG_GPIO_12_PD_POS))
+ (~(((1 << GLB_REG_GPIO_12_PD_LEN) - 1) << GLB_REG_GPIO_12_PD_POS))
#define GLB_REG_GPIO_12_FUNC_SEL GLB_REG_GPIO_12_FUNC_SEL
-#define GLB_REG_GPIO_12_FUNC_SEL_POS (8U)
-#define GLB_REG_GPIO_12_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_12_FUNC_SEL_POS (8)
+#define GLB_REG_GPIO_12_FUNC_SEL_LEN (4)
#define GLB_REG_GPIO_12_FUNC_SEL_MSK \
- (((1U << GLB_REG_GPIO_12_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_12_FUNC_SEL_POS)
+ (((1 << GLB_REG_GPIO_12_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_12_FUNC_SEL_POS)
#define GLB_REG_GPIO_12_FUNC_SEL_UMSK \
- (~(((1U << GLB_REG_GPIO_12_FUNC_SEL_LEN) - 1) \
+ (~(((1 << GLB_REG_GPIO_12_FUNC_SEL_LEN) - 1) \
<< GLB_REG_GPIO_12_FUNC_SEL_POS))
#define GLB_REG_GPIO_13_IE GLB_REG_GPIO_13_IE
-#define GLB_REG_GPIO_13_IE_POS (16U)
-#define GLB_REG_GPIO_13_IE_LEN (1U)
+#define GLB_REG_GPIO_13_IE_POS (16)
+#define GLB_REG_GPIO_13_IE_LEN (1)
#define GLB_REG_GPIO_13_IE_MSK \
- (((1U << GLB_REG_GPIO_13_IE_LEN) - 1) << GLB_REG_GPIO_13_IE_POS)
+ (((1 << GLB_REG_GPIO_13_IE_LEN) - 1) << GLB_REG_GPIO_13_IE_POS)
#define GLB_REG_GPIO_13_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_13_IE_LEN) - 1) << GLB_REG_GPIO_13_IE_POS))
+ (~(((1 << GLB_REG_GPIO_13_IE_LEN) - 1) << GLB_REG_GPIO_13_IE_POS))
#define GLB_REG_GPIO_13_SMT GLB_REG_GPIO_13_SMT
-#define GLB_REG_GPIO_13_SMT_POS (17U)
-#define GLB_REG_GPIO_13_SMT_LEN (1U)
+#define GLB_REG_GPIO_13_SMT_POS (17)
+#define GLB_REG_GPIO_13_SMT_LEN (1)
#define GLB_REG_GPIO_13_SMT_MSK \
- (((1U << GLB_REG_GPIO_13_SMT_LEN) - 1) << GLB_REG_GPIO_13_SMT_POS)
+ (((1 << GLB_REG_GPIO_13_SMT_LEN) - 1) << GLB_REG_GPIO_13_SMT_POS)
#define GLB_REG_GPIO_13_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_13_SMT_LEN) - 1) << GLB_REG_GPIO_13_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_13_SMT_LEN) - 1) << GLB_REG_GPIO_13_SMT_POS))
#define GLB_REG_GPIO_13_DRV GLB_REG_GPIO_13_DRV
-#define GLB_REG_GPIO_13_DRV_POS (18U)
-#define GLB_REG_GPIO_13_DRV_LEN (2U)
+#define GLB_REG_GPIO_13_DRV_POS (18)
+#define GLB_REG_GPIO_13_DRV_LEN (2)
#define GLB_REG_GPIO_13_DRV_MSK \
- (((1U << GLB_REG_GPIO_13_DRV_LEN) - 1) << GLB_REG_GPIO_13_DRV_POS)
+ (((1 << GLB_REG_GPIO_13_DRV_LEN) - 1) << GLB_REG_GPIO_13_DRV_POS)
#define GLB_REG_GPIO_13_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_13_DRV_LEN) - 1) << GLB_REG_GPIO_13_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_13_DRV_LEN) - 1) << GLB_REG_GPIO_13_DRV_POS))
#define GLB_REG_GPIO_13_PU GLB_REG_GPIO_13_PU
-#define GLB_REG_GPIO_13_PU_POS (20U)
-#define GLB_REG_GPIO_13_PU_LEN (1U)
+#define GLB_REG_GPIO_13_PU_POS (20)
+#define GLB_REG_GPIO_13_PU_LEN (1)
#define GLB_REG_GPIO_13_PU_MSK \
- (((1U << GLB_REG_GPIO_13_PU_LEN) - 1) << GLB_REG_GPIO_13_PU_POS)
+ (((1 << GLB_REG_GPIO_13_PU_LEN) - 1) << GLB_REG_GPIO_13_PU_POS)
#define GLB_REG_GPIO_13_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_13_PU_LEN) - 1) << GLB_REG_GPIO_13_PU_POS))
+ (~(((1 << GLB_REG_GPIO_13_PU_LEN) - 1) << GLB_REG_GPIO_13_PU_POS))
#define GLB_REG_GPIO_13_PD GLB_REG_GPIO_13_PD
-#define GLB_REG_GPIO_13_PD_POS (21U)
-#define GLB_REG_GPIO_13_PD_LEN (1U)
+#define GLB_REG_GPIO_13_PD_POS (21)
+#define GLB_REG_GPIO_13_PD_LEN (1)
#define GLB_REG_GPIO_13_PD_MSK \
- (((1U << GLB_REG_GPIO_13_PD_LEN) - 1) << GLB_REG_GPIO_13_PD_POS)
+ (((1 << GLB_REG_GPIO_13_PD_LEN) - 1) << GLB_REG_GPIO_13_PD_POS)
#define GLB_REG_GPIO_13_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_13_PD_LEN) - 1) << GLB_REG_GPIO_13_PD_POS))
+ (~(((1 << GLB_REG_GPIO_13_PD_LEN) - 1) << GLB_REG_GPIO_13_PD_POS))
#define GLB_REG_GPIO_13_FUNC_SEL GLB_REG_GPIO_13_FUNC_SEL
-#define GLB_REG_GPIO_13_FUNC_SEL_POS (24U)
-#define GLB_REG_GPIO_13_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_13_FUNC_SEL_POS (24)
+#define GLB_REG_GPIO_13_FUNC_SEL_LEN (4)
#define GLB_REG_GPIO_13_FUNC_SEL_MSK \
- (((1U << GLB_REG_GPIO_13_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_13_FUNC_SEL_POS)
+ (((1 << GLB_REG_GPIO_13_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_13_FUNC_SEL_POS)
#define GLB_REG_GPIO_13_FUNC_SEL_UMSK \
- (~(((1U << GLB_REG_GPIO_13_FUNC_SEL_LEN) - 1) \
+ (~(((1 << GLB_REG_GPIO_13_FUNC_SEL_LEN) - 1) \
<< GLB_REG_GPIO_13_FUNC_SEL_POS))
/* 0x11C : GPIO_CFGCTL7 */
#define GLB_GPIO_CFGCTL7_OFFSET (0x11C)
#define GLB_REG_GPIO_14_IE GLB_REG_GPIO_14_IE
-#define GLB_REG_GPIO_14_IE_POS (0U)
-#define GLB_REG_GPIO_14_IE_LEN (1U)
+#define GLB_REG_GPIO_14_IE_POS (0)
+#define GLB_REG_GPIO_14_IE_LEN (1)
#define GLB_REG_GPIO_14_IE_MSK \
- (((1U << GLB_REG_GPIO_14_IE_LEN) - 1) << GLB_REG_GPIO_14_IE_POS)
+ (((1 << GLB_REG_GPIO_14_IE_LEN) - 1) << GLB_REG_GPIO_14_IE_POS)
#define GLB_REG_GPIO_14_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_14_IE_LEN) - 1) << GLB_REG_GPIO_14_IE_POS))
+ (~(((1 << GLB_REG_GPIO_14_IE_LEN) - 1) << GLB_REG_GPIO_14_IE_POS))
#define GLB_REG_GPIO_14_SMT GLB_REG_GPIO_14_SMT
-#define GLB_REG_GPIO_14_SMT_POS (1U)
-#define GLB_REG_GPIO_14_SMT_LEN (1U)
+#define GLB_REG_GPIO_14_SMT_POS (1)
+#define GLB_REG_GPIO_14_SMT_LEN (1)
#define GLB_REG_GPIO_14_SMT_MSK \
- (((1U << GLB_REG_GPIO_14_SMT_LEN) - 1) << GLB_REG_GPIO_14_SMT_POS)
+ (((1 << GLB_REG_GPIO_14_SMT_LEN) - 1) << GLB_REG_GPIO_14_SMT_POS)
#define GLB_REG_GPIO_14_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_14_SMT_LEN) - 1) << GLB_REG_GPIO_14_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_14_SMT_LEN) - 1) << GLB_REG_GPIO_14_SMT_POS))
#define GLB_REG_GPIO_14_DRV GLB_REG_GPIO_14_DRV
-#define GLB_REG_GPIO_14_DRV_POS (2U)
-#define GLB_REG_GPIO_14_DRV_LEN (2U)
+#define GLB_REG_GPIO_14_DRV_POS (2)
+#define GLB_REG_GPIO_14_DRV_LEN (2)
#define GLB_REG_GPIO_14_DRV_MSK \
- (((1U << GLB_REG_GPIO_14_DRV_LEN) - 1) << GLB_REG_GPIO_14_DRV_POS)
+ (((1 << GLB_REG_GPIO_14_DRV_LEN) - 1) << GLB_REG_GPIO_14_DRV_POS)
#define GLB_REG_GPIO_14_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_14_DRV_LEN) - 1) << GLB_REG_GPIO_14_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_14_DRV_LEN) - 1) << GLB_REG_GPIO_14_DRV_POS))
#define GLB_REG_GPIO_14_PU GLB_REG_GPIO_14_PU
-#define GLB_REG_GPIO_14_PU_POS (4U)
-#define GLB_REG_GPIO_14_PU_LEN (1U)
+#define GLB_REG_GPIO_14_PU_POS (4)
+#define GLB_REG_GPIO_14_PU_LEN (1)
#define GLB_REG_GPIO_14_PU_MSK \
- (((1U << GLB_REG_GPIO_14_PU_LEN) - 1) << GLB_REG_GPIO_14_PU_POS)
+ (((1 << GLB_REG_GPIO_14_PU_LEN) - 1) << GLB_REG_GPIO_14_PU_POS)
#define GLB_REG_GPIO_14_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_14_PU_LEN) - 1) << GLB_REG_GPIO_14_PU_POS))
+ (~(((1 << GLB_REG_GPIO_14_PU_LEN) - 1) << GLB_REG_GPIO_14_PU_POS))
#define GLB_REG_GPIO_14_PD GLB_REG_GPIO_14_PD
-#define GLB_REG_GPIO_14_PD_POS (5U)
-#define GLB_REG_GPIO_14_PD_LEN (1U)
+#define GLB_REG_GPIO_14_PD_POS (5)
+#define GLB_REG_GPIO_14_PD_LEN (1)
#define GLB_REG_GPIO_14_PD_MSK \
- (((1U << GLB_REG_GPIO_14_PD_LEN) - 1) << GLB_REG_GPIO_14_PD_POS)
+ (((1 << GLB_REG_GPIO_14_PD_LEN) - 1) << GLB_REG_GPIO_14_PD_POS)
#define GLB_REG_GPIO_14_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_14_PD_LEN) - 1) << GLB_REG_GPIO_14_PD_POS))
+ (~(((1 << GLB_REG_GPIO_14_PD_LEN) - 1) << GLB_REG_GPIO_14_PD_POS))
#define GLB_REG_GPIO_14_FUNC_SEL GLB_REG_GPIO_14_FUNC_SEL
-#define GLB_REG_GPIO_14_FUNC_SEL_POS (8U)
-#define GLB_REG_GPIO_14_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_14_FUNC_SEL_POS (8)
+#define GLB_REG_GPIO_14_FUNC_SEL_LEN (4)
#define GLB_REG_GPIO_14_FUNC_SEL_MSK \
- (((1U << GLB_REG_GPIO_14_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_14_FUNC_SEL_POS)
+ (((1 << GLB_REG_GPIO_14_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_14_FUNC_SEL_POS)
#define GLB_REG_GPIO_14_FUNC_SEL_UMSK \
- (~(((1U << GLB_REG_GPIO_14_FUNC_SEL_LEN) - 1) \
+ (~(((1 << GLB_REG_GPIO_14_FUNC_SEL_LEN) - 1) \
<< GLB_REG_GPIO_14_FUNC_SEL_POS))
#define GLB_REG_GPIO_15_IE GLB_REG_GPIO_15_IE
-#define GLB_REG_GPIO_15_IE_POS (16U)
-#define GLB_REG_GPIO_15_IE_LEN (1U)
+#define GLB_REG_GPIO_15_IE_POS (16)
+#define GLB_REG_GPIO_15_IE_LEN (1)
#define GLB_REG_GPIO_15_IE_MSK \
- (((1U << GLB_REG_GPIO_15_IE_LEN) - 1) << GLB_REG_GPIO_15_IE_POS)
+ (((1 << GLB_REG_GPIO_15_IE_LEN) - 1) << GLB_REG_GPIO_15_IE_POS)
#define GLB_REG_GPIO_15_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_15_IE_LEN) - 1) << GLB_REG_GPIO_15_IE_POS))
+ (~(((1 << GLB_REG_GPIO_15_IE_LEN) - 1) << GLB_REG_GPIO_15_IE_POS))
#define GLB_REG_GPIO_15_SMT GLB_REG_GPIO_15_SMT
-#define GLB_REG_GPIO_15_SMT_POS (17U)
-#define GLB_REG_GPIO_15_SMT_LEN (1U)
+#define GLB_REG_GPIO_15_SMT_POS (17)
+#define GLB_REG_GPIO_15_SMT_LEN (1)
#define GLB_REG_GPIO_15_SMT_MSK \
- (((1U << GLB_REG_GPIO_15_SMT_LEN) - 1) << GLB_REG_GPIO_15_SMT_POS)
+ (((1 << GLB_REG_GPIO_15_SMT_LEN) - 1) << GLB_REG_GPIO_15_SMT_POS)
#define GLB_REG_GPIO_15_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_15_SMT_LEN) - 1) << GLB_REG_GPIO_15_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_15_SMT_LEN) - 1) << GLB_REG_GPIO_15_SMT_POS))
#define GLB_REG_GPIO_15_DRV GLB_REG_GPIO_15_DRV
-#define GLB_REG_GPIO_15_DRV_POS (18U)
-#define GLB_REG_GPIO_15_DRV_LEN (2U)
+#define GLB_REG_GPIO_15_DRV_POS (18)
+#define GLB_REG_GPIO_15_DRV_LEN (2)
#define GLB_REG_GPIO_15_DRV_MSK \
- (((1U << GLB_REG_GPIO_15_DRV_LEN) - 1) << GLB_REG_GPIO_15_DRV_POS)
+ (((1 << GLB_REG_GPIO_15_DRV_LEN) - 1) << GLB_REG_GPIO_15_DRV_POS)
#define GLB_REG_GPIO_15_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_15_DRV_LEN) - 1) << GLB_REG_GPIO_15_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_15_DRV_LEN) - 1) << GLB_REG_GPIO_15_DRV_POS))
#define GLB_REG_GPIO_15_PU GLB_REG_GPIO_15_PU
-#define GLB_REG_GPIO_15_PU_POS (20U)
-#define GLB_REG_GPIO_15_PU_LEN (1U)
+#define GLB_REG_GPIO_15_PU_POS (20)
+#define GLB_REG_GPIO_15_PU_LEN (1)
#define GLB_REG_GPIO_15_PU_MSK \
- (((1U << GLB_REG_GPIO_15_PU_LEN) - 1) << GLB_REG_GPIO_15_PU_POS)
+ (((1 << GLB_REG_GPIO_15_PU_LEN) - 1) << GLB_REG_GPIO_15_PU_POS)
#define GLB_REG_GPIO_15_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_15_PU_LEN) - 1) << GLB_REG_GPIO_15_PU_POS))
+ (~(((1 << GLB_REG_GPIO_15_PU_LEN) - 1) << GLB_REG_GPIO_15_PU_POS))
#define GLB_REG_GPIO_15_PD GLB_REG_GPIO_15_PD
-#define GLB_REG_GPIO_15_PD_POS (21U)
-#define GLB_REG_GPIO_15_PD_LEN (1U)
+#define GLB_REG_GPIO_15_PD_POS (21)
+#define GLB_REG_GPIO_15_PD_LEN (1)
#define GLB_REG_GPIO_15_PD_MSK \
- (((1U << GLB_REG_GPIO_15_PD_LEN) - 1) << GLB_REG_GPIO_15_PD_POS)
+ (((1 << GLB_REG_GPIO_15_PD_LEN) - 1) << GLB_REG_GPIO_15_PD_POS)
#define GLB_REG_GPIO_15_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_15_PD_LEN) - 1) << GLB_REG_GPIO_15_PD_POS))
+ (~(((1 << GLB_REG_GPIO_15_PD_LEN) - 1) << GLB_REG_GPIO_15_PD_POS))
#define GLB_REG_GPIO_15_FUNC_SEL GLB_REG_GPIO_15_FUNC_SEL
-#define GLB_REG_GPIO_15_FUNC_SEL_POS (24U)
-#define GLB_REG_GPIO_15_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_15_FUNC_SEL_POS (24)
+#define GLB_REG_GPIO_15_FUNC_SEL_LEN (4)
#define GLB_REG_GPIO_15_FUNC_SEL_MSK \
- (((1U << GLB_REG_GPIO_15_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_15_FUNC_SEL_POS)
+ (((1 << GLB_REG_GPIO_15_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_15_FUNC_SEL_POS)
#define GLB_REG_GPIO_15_FUNC_SEL_UMSK \
- (~(((1U << GLB_REG_GPIO_15_FUNC_SEL_LEN) - 1) \
+ (~(((1 << GLB_REG_GPIO_15_FUNC_SEL_LEN) - 1) \
<< GLB_REG_GPIO_15_FUNC_SEL_POS))
/* 0x120 : GPIO_CFGCTL8 */
#define GLB_GPIO_CFGCTL8_OFFSET (0x120)
#define GLB_REG_GPIO_16_IE GLB_REG_GPIO_16_IE
-#define GLB_REG_GPIO_16_IE_POS (0U)
-#define GLB_REG_GPIO_16_IE_LEN (1U)
+#define GLB_REG_GPIO_16_IE_POS (0)
+#define GLB_REG_GPIO_16_IE_LEN (1)
#define GLB_REG_GPIO_16_IE_MSK \
- (((1U << GLB_REG_GPIO_16_IE_LEN) - 1) << GLB_REG_GPIO_16_IE_POS)
+ (((1 << GLB_REG_GPIO_16_IE_LEN) - 1) << GLB_REG_GPIO_16_IE_POS)
#define GLB_REG_GPIO_16_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_16_IE_LEN) - 1) << GLB_REG_GPIO_16_IE_POS))
+ (~(((1 << GLB_REG_GPIO_16_IE_LEN) - 1) << GLB_REG_GPIO_16_IE_POS))
#define GLB_REG_GPIO_16_SMT GLB_REG_GPIO_16_SMT
-#define GLB_REG_GPIO_16_SMT_POS (1U)
-#define GLB_REG_GPIO_16_SMT_LEN (1U)
+#define GLB_REG_GPIO_16_SMT_POS (1)
+#define GLB_REG_GPIO_16_SMT_LEN (1)
#define GLB_REG_GPIO_16_SMT_MSK \
- (((1U << GLB_REG_GPIO_16_SMT_LEN) - 1) << GLB_REG_GPIO_16_SMT_POS)
+ (((1 << GLB_REG_GPIO_16_SMT_LEN) - 1) << GLB_REG_GPIO_16_SMT_POS)
#define GLB_REG_GPIO_16_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_16_SMT_LEN) - 1) << GLB_REG_GPIO_16_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_16_SMT_LEN) - 1) << GLB_REG_GPIO_16_SMT_POS))
#define GLB_REG_GPIO_16_DRV GLB_REG_GPIO_16_DRV
-#define GLB_REG_GPIO_16_DRV_POS (2U)
-#define GLB_REG_GPIO_16_DRV_LEN (2U)
+#define GLB_REG_GPIO_16_DRV_POS (2)
+#define GLB_REG_GPIO_16_DRV_LEN (2)
#define GLB_REG_GPIO_16_DRV_MSK \
- (((1U << GLB_REG_GPIO_16_DRV_LEN) - 1) << GLB_REG_GPIO_16_DRV_POS)
+ (((1 << GLB_REG_GPIO_16_DRV_LEN) - 1) << GLB_REG_GPIO_16_DRV_POS)
#define GLB_REG_GPIO_16_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_16_DRV_LEN) - 1) << GLB_REG_GPIO_16_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_16_DRV_LEN) - 1) << GLB_REG_GPIO_16_DRV_POS))
#define GLB_REG_GPIO_16_PU GLB_REG_GPIO_16_PU
-#define GLB_REG_GPIO_16_PU_POS (4U)
-#define GLB_REG_GPIO_16_PU_LEN (1U)
+#define GLB_REG_GPIO_16_PU_POS (4)
+#define GLB_REG_GPIO_16_PU_LEN (1)
#define GLB_REG_GPIO_16_PU_MSK \
- (((1U << GLB_REG_GPIO_16_PU_LEN) - 1) << GLB_REG_GPIO_16_PU_POS)
+ (((1 << GLB_REG_GPIO_16_PU_LEN) - 1) << GLB_REG_GPIO_16_PU_POS)
#define GLB_REG_GPIO_16_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_16_PU_LEN) - 1) << GLB_REG_GPIO_16_PU_POS))
+ (~(((1 << GLB_REG_GPIO_16_PU_LEN) - 1) << GLB_REG_GPIO_16_PU_POS))
#define GLB_REG_GPIO_16_PD GLB_REG_GPIO_16_PD
-#define GLB_REG_GPIO_16_PD_POS (5U)
-#define GLB_REG_GPIO_16_PD_LEN (1U)
+#define GLB_REG_GPIO_16_PD_POS (5)
+#define GLB_REG_GPIO_16_PD_LEN (1)
#define GLB_REG_GPIO_16_PD_MSK \
- (((1U << GLB_REG_GPIO_16_PD_LEN) - 1) << GLB_REG_GPIO_16_PD_POS)
+ (((1 << GLB_REG_GPIO_16_PD_LEN) - 1) << GLB_REG_GPIO_16_PD_POS)
#define GLB_REG_GPIO_16_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_16_PD_LEN) - 1) << GLB_REG_GPIO_16_PD_POS))
+ (~(((1 << GLB_REG_GPIO_16_PD_LEN) - 1) << GLB_REG_GPIO_16_PD_POS))
#define GLB_REG_GPIO_16_FUNC_SEL GLB_REG_GPIO_16_FUNC_SEL
-#define GLB_REG_GPIO_16_FUNC_SEL_POS (8U)
-#define GLB_REG_GPIO_16_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_16_FUNC_SEL_POS (8)
+#define GLB_REG_GPIO_16_FUNC_SEL_LEN (4)
#define GLB_REG_GPIO_16_FUNC_SEL_MSK \
- (((1U << GLB_REG_GPIO_16_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_16_FUNC_SEL_POS)
+ (((1 << GLB_REG_GPIO_16_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_16_FUNC_SEL_POS)
#define GLB_REG_GPIO_16_FUNC_SEL_UMSK \
- (~(((1U << GLB_REG_GPIO_16_FUNC_SEL_LEN) - 1) \
+ (~(((1 << GLB_REG_GPIO_16_FUNC_SEL_LEN) - 1) \
<< GLB_REG_GPIO_16_FUNC_SEL_POS))
#define GLB_REG_GPIO_17_IE GLB_REG_GPIO_17_IE
-#define GLB_REG_GPIO_17_IE_POS (16U)
-#define GLB_REG_GPIO_17_IE_LEN (1U)
+#define GLB_REG_GPIO_17_IE_POS (16)
+#define GLB_REG_GPIO_17_IE_LEN (1)
#define GLB_REG_GPIO_17_IE_MSK \
- (((1U << GLB_REG_GPIO_17_IE_LEN) - 1) << GLB_REG_GPIO_17_IE_POS)
+ (((1 << GLB_REG_GPIO_17_IE_LEN) - 1) << GLB_REG_GPIO_17_IE_POS)
#define GLB_REG_GPIO_17_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_17_IE_LEN) - 1) << GLB_REG_GPIO_17_IE_POS))
+ (~(((1 << GLB_REG_GPIO_17_IE_LEN) - 1) << GLB_REG_GPIO_17_IE_POS))
#define GLB_REG_GPIO_17_SMT GLB_REG_GPIO_17_SMT
-#define GLB_REG_GPIO_17_SMT_POS (17U)
-#define GLB_REG_GPIO_17_SMT_LEN (1U)
+#define GLB_REG_GPIO_17_SMT_POS (17)
+#define GLB_REG_GPIO_17_SMT_LEN (1)
#define GLB_REG_GPIO_17_SMT_MSK \
- (((1U << GLB_REG_GPIO_17_SMT_LEN) - 1) << GLB_REG_GPIO_17_SMT_POS)
+ (((1 << GLB_REG_GPIO_17_SMT_LEN) - 1) << GLB_REG_GPIO_17_SMT_POS)
#define GLB_REG_GPIO_17_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_17_SMT_LEN) - 1) << GLB_REG_GPIO_17_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_17_SMT_LEN) - 1) << GLB_REG_GPIO_17_SMT_POS))
#define GLB_REG_GPIO_17_DRV GLB_REG_GPIO_17_DRV
-#define GLB_REG_GPIO_17_DRV_POS (18U)
-#define GLB_REG_GPIO_17_DRV_LEN (2U)
+#define GLB_REG_GPIO_17_DRV_POS (18)
+#define GLB_REG_GPIO_17_DRV_LEN (2)
#define GLB_REG_GPIO_17_DRV_MSK \
- (((1U << GLB_REG_GPIO_17_DRV_LEN) - 1) << GLB_REG_GPIO_17_DRV_POS)
+ (((1 << GLB_REG_GPIO_17_DRV_LEN) - 1) << GLB_REG_GPIO_17_DRV_POS)
#define GLB_REG_GPIO_17_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_17_DRV_LEN) - 1) << GLB_REG_GPIO_17_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_17_DRV_LEN) - 1) << GLB_REG_GPIO_17_DRV_POS))
#define GLB_REG_GPIO_17_PU GLB_REG_GPIO_17_PU
-#define GLB_REG_GPIO_17_PU_POS (20U)
-#define GLB_REG_GPIO_17_PU_LEN (1U)
+#define GLB_REG_GPIO_17_PU_POS (20)
+#define GLB_REG_GPIO_17_PU_LEN (1)
#define GLB_REG_GPIO_17_PU_MSK \
- (((1U << GLB_REG_GPIO_17_PU_LEN) - 1) << GLB_REG_GPIO_17_PU_POS)
+ (((1 << GLB_REG_GPIO_17_PU_LEN) - 1) << GLB_REG_GPIO_17_PU_POS)
#define GLB_REG_GPIO_17_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_17_PU_LEN) - 1) << GLB_REG_GPIO_17_PU_POS))
+ (~(((1 << GLB_REG_GPIO_17_PU_LEN) - 1) << GLB_REG_GPIO_17_PU_POS))
#define GLB_REG_GPIO_17_PD GLB_REG_GPIO_17_PD
-#define GLB_REG_GPIO_17_PD_POS (21U)
-#define GLB_REG_GPIO_17_PD_LEN (1U)
+#define GLB_REG_GPIO_17_PD_POS (21)
+#define GLB_REG_GPIO_17_PD_LEN (1)
#define GLB_REG_GPIO_17_PD_MSK \
- (((1U << GLB_REG_GPIO_17_PD_LEN) - 1) << GLB_REG_GPIO_17_PD_POS)
+ (((1 << GLB_REG_GPIO_17_PD_LEN) - 1) << GLB_REG_GPIO_17_PD_POS)
#define GLB_REG_GPIO_17_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_17_PD_LEN) - 1) << GLB_REG_GPIO_17_PD_POS))
+ (~(((1 << GLB_REG_GPIO_17_PD_LEN) - 1) << GLB_REG_GPIO_17_PD_POS))
#define GLB_REG_GPIO_17_FUNC_SEL GLB_REG_GPIO_17_FUNC_SEL
-#define GLB_REG_GPIO_17_FUNC_SEL_POS (24U)
-#define GLB_REG_GPIO_17_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_17_FUNC_SEL_POS (24)
+#define GLB_REG_GPIO_17_FUNC_SEL_LEN (4)
#define GLB_REG_GPIO_17_FUNC_SEL_MSK \
- (((1U << GLB_REG_GPIO_17_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_17_FUNC_SEL_POS)
+ (((1 << GLB_REG_GPIO_17_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_17_FUNC_SEL_POS)
#define GLB_REG_GPIO_17_FUNC_SEL_UMSK \
- (~(((1U << GLB_REG_GPIO_17_FUNC_SEL_LEN) - 1) \
+ (~(((1 << GLB_REG_GPIO_17_FUNC_SEL_LEN) - 1) \
<< GLB_REG_GPIO_17_FUNC_SEL_POS))
/* 0x124 : GPIO_CFGCTL9 */
#define GLB_GPIO_CFGCTL9_OFFSET (0x124)
#define GLB_REG_GPIO_18_IE GLB_REG_GPIO_18_IE
-#define GLB_REG_GPIO_18_IE_POS (0U)
-#define GLB_REG_GPIO_18_IE_LEN (1U)
+#define GLB_REG_GPIO_18_IE_POS (0)
+#define GLB_REG_GPIO_18_IE_LEN (1)
#define GLB_REG_GPIO_18_IE_MSK \
- (((1U << GLB_REG_GPIO_18_IE_LEN) - 1) << GLB_REG_GPIO_18_IE_POS)
+ (((1 << GLB_REG_GPIO_18_IE_LEN) - 1) << GLB_REG_GPIO_18_IE_POS)
#define GLB_REG_GPIO_18_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_18_IE_LEN) - 1) << GLB_REG_GPIO_18_IE_POS))
+ (~(((1 << GLB_REG_GPIO_18_IE_LEN) - 1) << GLB_REG_GPIO_18_IE_POS))
#define GLB_REG_GPIO_18_SMT GLB_REG_GPIO_18_SMT
-#define GLB_REG_GPIO_18_SMT_POS (1U)
-#define GLB_REG_GPIO_18_SMT_LEN (1U)
+#define GLB_REG_GPIO_18_SMT_POS (1)
+#define GLB_REG_GPIO_18_SMT_LEN (1)
#define GLB_REG_GPIO_18_SMT_MSK \
- (((1U << GLB_REG_GPIO_18_SMT_LEN) - 1) << GLB_REG_GPIO_18_SMT_POS)
+ (((1 << GLB_REG_GPIO_18_SMT_LEN) - 1) << GLB_REG_GPIO_18_SMT_POS)
#define GLB_REG_GPIO_18_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_18_SMT_LEN) - 1) << GLB_REG_GPIO_18_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_18_SMT_LEN) - 1) << GLB_REG_GPIO_18_SMT_POS))
#define GLB_REG_GPIO_18_DRV GLB_REG_GPIO_18_DRV
-#define GLB_REG_GPIO_18_DRV_POS (2U)
-#define GLB_REG_GPIO_18_DRV_LEN (2U)
+#define GLB_REG_GPIO_18_DRV_POS (2)
+#define GLB_REG_GPIO_18_DRV_LEN (2)
#define GLB_REG_GPIO_18_DRV_MSK \
- (((1U << GLB_REG_GPIO_18_DRV_LEN) - 1) << GLB_REG_GPIO_18_DRV_POS)
+ (((1 << GLB_REG_GPIO_18_DRV_LEN) - 1) << GLB_REG_GPIO_18_DRV_POS)
#define GLB_REG_GPIO_18_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_18_DRV_LEN) - 1) << GLB_REG_GPIO_18_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_18_DRV_LEN) - 1) << GLB_REG_GPIO_18_DRV_POS))
#define GLB_REG_GPIO_18_PU GLB_REG_GPIO_18_PU
-#define GLB_REG_GPIO_18_PU_POS (4U)
-#define GLB_REG_GPIO_18_PU_LEN (1U)
+#define GLB_REG_GPIO_18_PU_POS (4)
+#define GLB_REG_GPIO_18_PU_LEN (1)
#define GLB_REG_GPIO_18_PU_MSK \
- (((1U << GLB_REG_GPIO_18_PU_LEN) - 1) << GLB_REG_GPIO_18_PU_POS)
+ (((1 << GLB_REG_GPIO_18_PU_LEN) - 1) << GLB_REG_GPIO_18_PU_POS)
#define GLB_REG_GPIO_18_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_18_PU_LEN) - 1) << GLB_REG_GPIO_18_PU_POS))
+ (~(((1 << GLB_REG_GPIO_18_PU_LEN) - 1) << GLB_REG_GPIO_18_PU_POS))
#define GLB_REG_GPIO_18_PD GLB_REG_GPIO_18_PD
-#define GLB_REG_GPIO_18_PD_POS (5U)
-#define GLB_REG_GPIO_18_PD_LEN (1U)
+#define GLB_REG_GPIO_18_PD_POS (5)
+#define GLB_REG_GPIO_18_PD_LEN (1)
#define GLB_REG_GPIO_18_PD_MSK \
- (((1U << GLB_REG_GPIO_18_PD_LEN) - 1) << GLB_REG_GPIO_18_PD_POS)
+ (((1 << GLB_REG_GPIO_18_PD_LEN) - 1) << GLB_REG_GPIO_18_PD_POS)
#define GLB_REG_GPIO_18_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_18_PD_LEN) - 1) << GLB_REG_GPIO_18_PD_POS))
+ (~(((1 << GLB_REG_GPIO_18_PD_LEN) - 1) << GLB_REG_GPIO_18_PD_POS))
#define GLB_REG_GPIO_18_FUNC_SEL GLB_REG_GPIO_18_FUNC_SEL
-#define GLB_REG_GPIO_18_FUNC_SEL_POS (8U)
-#define GLB_REG_GPIO_18_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_18_FUNC_SEL_POS (8)
+#define GLB_REG_GPIO_18_FUNC_SEL_LEN (4)
#define GLB_REG_GPIO_18_FUNC_SEL_MSK \
- (((1U << GLB_REG_GPIO_18_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_18_FUNC_SEL_POS)
+ (((1 << GLB_REG_GPIO_18_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_18_FUNC_SEL_POS)
#define GLB_REG_GPIO_18_FUNC_SEL_UMSK \
- (~(((1U << GLB_REG_GPIO_18_FUNC_SEL_LEN) - 1) \
+ (~(((1 << GLB_REG_GPIO_18_FUNC_SEL_LEN) - 1) \
<< GLB_REG_GPIO_18_FUNC_SEL_POS))
#define GLB_REG_GPIO_19_IE GLB_REG_GPIO_19_IE
-#define GLB_REG_GPIO_19_IE_POS (16U)
-#define GLB_REG_GPIO_19_IE_LEN (1U)
+#define GLB_REG_GPIO_19_IE_POS (16)
+#define GLB_REG_GPIO_19_IE_LEN (1)
#define GLB_REG_GPIO_19_IE_MSK \
- (((1U << GLB_REG_GPIO_19_IE_LEN) - 1) << GLB_REG_GPIO_19_IE_POS)
+ (((1 << GLB_REG_GPIO_19_IE_LEN) - 1) << GLB_REG_GPIO_19_IE_POS)
#define GLB_REG_GPIO_19_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_19_IE_LEN) - 1) << GLB_REG_GPIO_19_IE_POS))
+ (~(((1 << GLB_REG_GPIO_19_IE_LEN) - 1) << GLB_REG_GPIO_19_IE_POS))
#define GLB_REG_GPIO_19_SMT GLB_REG_GPIO_19_SMT
-#define GLB_REG_GPIO_19_SMT_POS (17U)
-#define GLB_REG_GPIO_19_SMT_LEN (1U)
+#define GLB_REG_GPIO_19_SMT_POS (17)
+#define GLB_REG_GPIO_19_SMT_LEN (1)
#define GLB_REG_GPIO_19_SMT_MSK \
- (((1U << GLB_REG_GPIO_19_SMT_LEN) - 1) << GLB_REG_GPIO_19_SMT_POS)
+ (((1 << GLB_REG_GPIO_19_SMT_LEN) - 1) << GLB_REG_GPIO_19_SMT_POS)
#define GLB_REG_GPIO_19_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_19_SMT_LEN) - 1) << GLB_REG_GPIO_19_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_19_SMT_LEN) - 1) << GLB_REG_GPIO_19_SMT_POS))
#define GLB_REG_GPIO_19_DRV GLB_REG_GPIO_19_DRV
-#define GLB_REG_GPIO_19_DRV_POS (18U)
-#define GLB_REG_GPIO_19_DRV_LEN (2U)
+#define GLB_REG_GPIO_19_DRV_POS (18)
+#define GLB_REG_GPIO_19_DRV_LEN (2)
#define GLB_REG_GPIO_19_DRV_MSK \
- (((1U << GLB_REG_GPIO_19_DRV_LEN) - 1) << GLB_REG_GPIO_19_DRV_POS)
+ (((1 << GLB_REG_GPIO_19_DRV_LEN) - 1) << GLB_REG_GPIO_19_DRV_POS)
#define GLB_REG_GPIO_19_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_19_DRV_LEN) - 1) << GLB_REG_GPIO_19_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_19_DRV_LEN) - 1) << GLB_REG_GPIO_19_DRV_POS))
#define GLB_REG_GPIO_19_PU GLB_REG_GPIO_19_PU
-#define GLB_REG_GPIO_19_PU_POS (20U)
-#define GLB_REG_GPIO_19_PU_LEN (1U)
+#define GLB_REG_GPIO_19_PU_POS (20)
+#define GLB_REG_GPIO_19_PU_LEN (1)
#define GLB_REG_GPIO_19_PU_MSK \
- (((1U << GLB_REG_GPIO_19_PU_LEN) - 1) << GLB_REG_GPIO_19_PU_POS)
+ (((1 << GLB_REG_GPIO_19_PU_LEN) - 1) << GLB_REG_GPIO_19_PU_POS)
#define GLB_REG_GPIO_19_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_19_PU_LEN) - 1) << GLB_REG_GPIO_19_PU_POS))
+ (~(((1 << GLB_REG_GPIO_19_PU_LEN) - 1) << GLB_REG_GPIO_19_PU_POS))
#define GLB_REG_GPIO_19_PD GLB_REG_GPIO_19_PD
-#define GLB_REG_GPIO_19_PD_POS (21U)
-#define GLB_REG_GPIO_19_PD_LEN (1U)
+#define GLB_REG_GPIO_19_PD_POS (21)
+#define GLB_REG_GPIO_19_PD_LEN (1)
#define GLB_REG_GPIO_19_PD_MSK \
- (((1U << GLB_REG_GPIO_19_PD_LEN) - 1) << GLB_REG_GPIO_19_PD_POS)
+ (((1 << GLB_REG_GPIO_19_PD_LEN) - 1) << GLB_REG_GPIO_19_PD_POS)
#define GLB_REG_GPIO_19_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_19_PD_LEN) - 1) << GLB_REG_GPIO_19_PD_POS))
+ (~(((1 << GLB_REG_GPIO_19_PD_LEN) - 1) << GLB_REG_GPIO_19_PD_POS))
#define GLB_REG_GPIO_19_FUNC_SEL GLB_REG_GPIO_19_FUNC_SEL
-#define GLB_REG_GPIO_19_FUNC_SEL_POS (24U)
-#define GLB_REG_GPIO_19_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_19_FUNC_SEL_POS (24)
+#define GLB_REG_GPIO_19_FUNC_SEL_LEN (4)
#define GLB_REG_GPIO_19_FUNC_SEL_MSK \
- (((1U << GLB_REG_GPIO_19_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_19_FUNC_SEL_POS)
+ (((1 << GLB_REG_GPIO_19_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_19_FUNC_SEL_POS)
#define GLB_REG_GPIO_19_FUNC_SEL_UMSK \
- (~(((1U << GLB_REG_GPIO_19_FUNC_SEL_LEN) - 1) \
+ (~(((1 << GLB_REG_GPIO_19_FUNC_SEL_LEN) - 1) \
<< GLB_REG_GPIO_19_FUNC_SEL_POS))
/* 0x128 : GPIO_CFGCTL10 */
#define GLB_GPIO_CFGCTL10_OFFSET (0x128)
#define GLB_REG_GPIO_20_IE GLB_REG_GPIO_20_IE
-#define GLB_REG_GPIO_20_IE_POS (0U)
-#define GLB_REG_GPIO_20_IE_LEN (1U)
+#define GLB_REG_GPIO_20_IE_POS (0)
+#define GLB_REG_GPIO_20_IE_LEN (1)
#define GLB_REG_GPIO_20_IE_MSK \
- (((1U << GLB_REG_GPIO_20_IE_LEN) - 1) << GLB_REG_GPIO_20_IE_POS)
+ (((1 << GLB_REG_GPIO_20_IE_LEN) - 1) << GLB_REG_GPIO_20_IE_POS)
#define GLB_REG_GPIO_20_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_20_IE_LEN) - 1) << GLB_REG_GPIO_20_IE_POS))
+ (~(((1 << GLB_REG_GPIO_20_IE_LEN) - 1) << GLB_REG_GPIO_20_IE_POS))
#define GLB_REG_GPIO_20_SMT GLB_REG_GPIO_20_SMT
-#define GLB_REG_GPIO_20_SMT_POS (1U)
-#define GLB_REG_GPIO_20_SMT_LEN (1U)
+#define GLB_REG_GPIO_20_SMT_POS (1)
+#define GLB_REG_GPIO_20_SMT_LEN (1)
#define GLB_REG_GPIO_20_SMT_MSK \
- (((1U << GLB_REG_GPIO_20_SMT_LEN) - 1) << GLB_REG_GPIO_20_SMT_POS)
+ (((1 << GLB_REG_GPIO_20_SMT_LEN) - 1) << GLB_REG_GPIO_20_SMT_POS)
#define GLB_REG_GPIO_20_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_20_SMT_LEN) - 1) << GLB_REG_GPIO_20_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_20_SMT_LEN) - 1) << GLB_REG_GPIO_20_SMT_POS))
#define GLB_REG_GPIO_20_DRV GLB_REG_GPIO_20_DRV
-#define GLB_REG_GPIO_20_DRV_POS (2U)
-#define GLB_REG_GPIO_20_DRV_LEN (2U)
+#define GLB_REG_GPIO_20_DRV_POS (2)
+#define GLB_REG_GPIO_20_DRV_LEN (2)
#define GLB_REG_GPIO_20_DRV_MSK \
- (((1U << GLB_REG_GPIO_20_DRV_LEN) - 1) << GLB_REG_GPIO_20_DRV_POS)
+ (((1 << GLB_REG_GPIO_20_DRV_LEN) - 1) << GLB_REG_GPIO_20_DRV_POS)
#define GLB_REG_GPIO_20_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_20_DRV_LEN) - 1) << GLB_REG_GPIO_20_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_20_DRV_LEN) - 1) << GLB_REG_GPIO_20_DRV_POS))
#define GLB_REG_GPIO_20_PU GLB_REG_GPIO_20_PU
-#define GLB_REG_GPIO_20_PU_POS (4U)
-#define GLB_REG_GPIO_20_PU_LEN (1U)
+#define GLB_REG_GPIO_20_PU_POS (4)
+#define GLB_REG_GPIO_20_PU_LEN (1)
#define GLB_REG_GPIO_20_PU_MSK \
- (((1U << GLB_REG_GPIO_20_PU_LEN) - 1) << GLB_REG_GPIO_20_PU_POS)
+ (((1 << GLB_REG_GPIO_20_PU_LEN) - 1) << GLB_REG_GPIO_20_PU_POS)
#define GLB_REG_GPIO_20_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_20_PU_LEN) - 1) << GLB_REG_GPIO_20_PU_POS))
+ (~(((1 << GLB_REG_GPIO_20_PU_LEN) - 1) << GLB_REG_GPIO_20_PU_POS))
#define GLB_REG_GPIO_20_PD GLB_REG_GPIO_20_PD
-#define GLB_REG_GPIO_20_PD_POS (5U)
-#define GLB_REG_GPIO_20_PD_LEN (1U)
+#define GLB_REG_GPIO_20_PD_POS (5)
+#define GLB_REG_GPIO_20_PD_LEN (1)
#define GLB_REG_GPIO_20_PD_MSK \
- (((1U << GLB_REG_GPIO_20_PD_LEN) - 1) << GLB_REG_GPIO_20_PD_POS)
+ (((1 << GLB_REG_GPIO_20_PD_LEN) - 1) << GLB_REG_GPIO_20_PD_POS)
#define GLB_REG_GPIO_20_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_20_PD_LEN) - 1) << GLB_REG_GPIO_20_PD_POS))
+ (~(((1 << GLB_REG_GPIO_20_PD_LEN) - 1) << GLB_REG_GPIO_20_PD_POS))
#define GLB_REG_GPIO_20_FUNC_SEL GLB_REG_GPIO_20_FUNC_SEL
-#define GLB_REG_GPIO_20_FUNC_SEL_POS (8U)
-#define GLB_REG_GPIO_20_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_20_FUNC_SEL_POS (8)
+#define GLB_REG_GPIO_20_FUNC_SEL_LEN (4)
#define GLB_REG_GPIO_20_FUNC_SEL_MSK \
- (((1U << GLB_REG_GPIO_20_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_20_FUNC_SEL_POS)
+ (((1 << GLB_REG_GPIO_20_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_20_FUNC_SEL_POS)
#define GLB_REG_GPIO_20_FUNC_SEL_UMSK \
- (~(((1U << GLB_REG_GPIO_20_FUNC_SEL_LEN) - 1) \
+ (~(((1 << GLB_REG_GPIO_20_FUNC_SEL_LEN) - 1) \
<< GLB_REG_GPIO_20_FUNC_SEL_POS))
#define GLB_REG_GPIO_21_IE GLB_REG_GPIO_21_IE
-#define GLB_REG_GPIO_21_IE_POS (16U)
-#define GLB_REG_GPIO_21_IE_LEN (1U)
+#define GLB_REG_GPIO_21_IE_POS (16)
+#define GLB_REG_GPIO_21_IE_LEN (1)
#define GLB_REG_GPIO_21_IE_MSK \
- (((1U << GLB_REG_GPIO_21_IE_LEN) - 1) << GLB_REG_GPIO_21_IE_POS)
+ (((1 << GLB_REG_GPIO_21_IE_LEN) - 1) << GLB_REG_GPIO_21_IE_POS)
#define GLB_REG_GPIO_21_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_21_IE_LEN) - 1) << GLB_REG_GPIO_21_IE_POS))
+ (~(((1 << GLB_REG_GPIO_21_IE_LEN) - 1) << GLB_REG_GPIO_21_IE_POS))
#define GLB_REG_GPIO_21_SMT GLB_REG_GPIO_21_SMT
-#define GLB_REG_GPIO_21_SMT_POS (17U)
-#define GLB_REG_GPIO_21_SMT_LEN (1U)
+#define GLB_REG_GPIO_21_SMT_POS (17)
+#define GLB_REG_GPIO_21_SMT_LEN (1)
#define GLB_REG_GPIO_21_SMT_MSK \
- (((1U << GLB_REG_GPIO_21_SMT_LEN) - 1) << GLB_REG_GPIO_21_SMT_POS)
+ (((1 << GLB_REG_GPIO_21_SMT_LEN) - 1) << GLB_REG_GPIO_21_SMT_POS)
#define GLB_REG_GPIO_21_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_21_SMT_LEN) - 1) << GLB_REG_GPIO_21_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_21_SMT_LEN) - 1) << GLB_REG_GPIO_21_SMT_POS))
#define GLB_REG_GPIO_21_DRV GLB_REG_GPIO_21_DRV
-#define GLB_REG_GPIO_21_DRV_POS (18U)
-#define GLB_REG_GPIO_21_DRV_LEN (2U)
+#define GLB_REG_GPIO_21_DRV_POS (18)
+#define GLB_REG_GPIO_21_DRV_LEN (2)
#define GLB_REG_GPIO_21_DRV_MSK \
- (((1U << GLB_REG_GPIO_21_DRV_LEN) - 1) << GLB_REG_GPIO_21_DRV_POS)
+ (((1 << GLB_REG_GPIO_21_DRV_LEN) - 1) << GLB_REG_GPIO_21_DRV_POS)
#define GLB_REG_GPIO_21_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_21_DRV_LEN) - 1) << GLB_REG_GPIO_21_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_21_DRV_LEN) - 1) << GLB_REG_GPIO_21_DRV_POS))
#define GLB_REG_GPIO_21_PU GLB_REG_GPIO_21_PU
-#define GLB_REG_GPIO_21_PU_POS (20U)
-#define GLB_REG_GPIO_21_PU_LEN (1U)
+#define GLB_REG_GPIO_21_PU_POS (20)
+#define GLB_REG_GPIO_21_PU_LEN (1)
#define GLB_REG_GPIO_21_PU_MSK \
- (((1U << GLB_REG_GPIO_21_PU_LEN) - 1) << GLB_REG_GPIO_21_PU_POS)
+ (((1 << GLB_REG_GPIO_21_PU_LEN) - 1) << GLB_REG_GPIO_21_PU_POS)
#define GLB_REG_GPIO_21_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_21_PU_LEN) - 1) << GLB_REG_GPIO_21_PU_POS))
+ (~(((1 << GLB_REG_GPIO_21_PU_LEN) - 1) << GLB_REG_GPIO_21_PU_POS))
#define GLB_REG_GPIO_21_PD GLB_REG_GPIO_21_PD
-#define GLB_REG_GPIO_21_PD_POS (21U)
-#define GLB_REG_GPIO_21_PD_LEN (1U)
+#define GLB_REG_GPIO_21_PD_POS (21)
+#define GLB_REG_GPIO_21_PD_LEN (1)
#define GLB_REG_GPIO_21_PD_MSK \
- (((1U << GLB_REG_GPIO_21_PD_LEN) - 1) << GLB_REG_GPIO_21_PD_POS)
+ (((1 << GLB_REG_GPIO_21_PD_LEN) - 1) << GLB_REG_GPIO_21_PD_POS)
#define GLB_REG_GPIO_21_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_21_PD_LEN) - 1) << GLB_REG_GPIO_21_PD_POS))
+ (~(((1 << GLB_REG_GPIO_21_PD_LEN) - 1) << GLB_REG_GPIO_21_PD_POS))
#define GLB_REG_GPIO_21_FUNC_SEL GLB_REG_GPIO_21_FUNC_SEL
-#define GLB_REG_GPIO_21_FUNC_SEL_POS (24U)
-#define GLB_REG_GPIO_21_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_21_FUNC_SEL_POS (24)
+#define GLB_REG_GPIO_21_FUNC_SEL_LEN (4)
#define GLB_REG_GPIO_21_FUNC_SEL_MSK \
- (((1U << GLB_REG_GPIO_21_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_21_FUNC_SEL_POS)
+ (((1 << GLB_REG_GPIO_21_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_21_FUNC_SEL_POS)
#define GLB_REG_GPIO_21_FUNC_SEL_UMSK \
- (~(((1U << GLB_REG_GPIO_21_FUNC_SEL_LEN) - 1) \
+ (~(((1 << GLB_REG_GPIO_21_FUNC_SEL_LEN) - 1) \
<< GLB_REG_GPIO_21_FUNC_SEL_POS))
/* 0x12C : GPIO_CFGCTL11 */
#define GLB_GPIO_CFGCTL11_OFFSET (0x12C)
#define GLB_REG_GPIO_22_IE GLB_REG_GPIO_22_IE
-#define GLB_REG_GPIO_22_IE_POS (0U)
-#define GLB_REG_GPIO_22_IE_LEN (1U)
+#define GLB_REG_GPIO_22_IE_POS (0)
+#define GLB_REG_GPIO_22_IE_LEN (1)
#define GLB_REG_GPIO_22_IE_MSK \
- (((1U << GLB_REG_GPIO_22_IE_LEN) - 1) << GLB_REG_GPIO_22_IE_POS)
+ (((1 << GLB_REG_GPIO_22_IE_LEN) - 1) << GLB_REG_GPIO_22_IE_POS)
#define GLB_REG_GPIO_22_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_22_IE_LEN) - 1) << GLB_REG_GPIO_22_IE_POS))
+ (~(((1 << GLB_REG_GPIO_22_IE_LEN) - 1) << GLB_REG_GPIO_22_IE_POS))
#define GLB_REG_GPIO_22_SMT GLB_REG_GPIO_22_SMT
-#define GLB_REG_GPIO_22_SMT_POS (1U)
-#define GLB_REG_GPIO_22_SMT_LEN (1U)
+#define GLB_REG_GPIO_22_SMT_POS (1)
+#define GLB_REG_GPIO_22_SMT_LEN (1)
#define GLB_REG_GPIO_22_SMT_MSK \
- (((1U << GLB_REG_GPIO_22_SMT_LEN) - 1) << GLB_REG_GPIO_22_SMT_POS)
+ (((1 << GLB_REG_GPIO_22_SMT_LEN) - 1) << GLB_REG_GPIO_22_SMT_POS)
#define GLB_REG_GPIO_22_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_22_SMT_LEN) - 1) << GLB_REG_GPIO_22_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_22_SMT_LEN) - 1) << GLB_REG_GPIO_22_SMT_POS))
#define GLB_REG_GPIO_22_DRV GLB_REG_GPIO_22_DRV
-#define GLB_REG_GPIO_22_DRV_POS (2U)
-#define GLB_REG_GPIO_22_DRV_LEN (2U)
+#define GLB_REG_GPIO_22_DRV_POS (2)
+#define GLB_REG_GPIO_22_DRV_LEN (2)
#define GLB_REG_GPIO_22_DRV_MSK \
- (((1U << GLB_REG_GPIO_22_DRV_LEN) - 1) << GLB_REG_GPIO_22_DRV_POS)
+ (((1 << GLB_REG_GPIO_22_DRV_LEN) - 1) << GLB_REG_GPIO_22_DRV_POS)
#define GLB_REG_GPIO_22_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_22_DRV_LEN) - 1) << GLB_REG_GPIO_22_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_22_DRV_LEN) - 1) << GLB_REG_GPIO_22_DRV_POS))
#define GLB_REG_GPIO_22_PU GLB_REG_GPIO_22_PU
-#define GLB_REG_GPIO_22_PU_POS (4U)
-#define GLB_REG_GPIO_22_PU_LEN (1U)
+#define GLB_REG_GPIO_22_PU_POS (4)
+#define GLB_REG_GPIO_22_PU_LEN (1)
#define GLB_REG_GPIO_22_PU_MSK \
- (((1U << GLB_REG_GPIO_22_PU_LEN) - 1) << GLB_REG_GPIO_22_PU_POS)
+ (((1 << GLB_REG_GPIO_22_PU_LEN) - 1) << GLB_REG_GPIO_22_PU_POS)
#define GLB_REG_GPIO_22_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_22_PU_LEN) - 1) << GLB_REG_GPIO_22_PU_POS))
+ (~(((1 << GLB_REG_GPIO_22_PU_LEN) - 1) << GLB_REG_GPIO_22_PU_POS))
#define GLB_REG_GPIO_22_PD GLB_REG_GPIO_22_PD
-#define GLB_REG_GPIO_22_PD_POS (5U)
-#define GLB_REG_GPIO_22_PD_LEN (1U)
+#define GLB_REG_GPIO_22_PD_POS (5)
+#define GLB_REG_GPIO_22_PD_LEN (1)
#define GLB_REG_GPIO_22_PD_MSK \
- (((1U << GLB_REG_GPIO_22_PD_LEN) - 1) << GLB_REG_GPIO_22_PD_POS)
+ (((1 << GLB_REG_GPIO_22_PD_LEN) - 1) << GLB_REG_GPIO_22_PD_POS)
#define GLB_REG_GPIO_22_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_22_PD_LEN) - 1) << GLB_REG_GPIO_22_PD_POS))
+ (~(((1 << GLB_REG_GPIO_22_PD_LEN) - 1) << GLB_REG_GPIO_22_PD_POS))
#define GLB_REG_GPIO_22_FUNC_SEL GLB_REG_GPIO_22_FUNC_SEL
-#define GLB_REG_GPIO_22_FUNC_SEL_POS (8U)
-#define GLB_REG_GPIO_22_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_22_FUNC_SEL_POS (8)
+#define GLB_REG_GPIO_22_FUNC_SEL_LEN (4)
#define GLB_REG_GPIO_22_FUNC_SEL_MSK \
- (((1U << GLB_REG_GPIO_22_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_22_FUNC_SEL_POS)
+ (((1 << GLB_REG_GPIO_22_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_22_FUNC_SEL_POS)
#define GLB_REG_GPIO_22_FUNC_SEL_UMSK \
- (~(((1U << GLB_REG_GPIO_22_FUNC_SEL_LEN) - 1) \
+ (~(((1 << GLB_REG_GPIO_22_FUNC_SEL_LEN) - 1) \
<< GLB_REG_GPIO_22_FUNC_SEL_POS))
#define GLB_REG_GPIO_23_IE GLB_REG_GPIO_23_IE
-#define GLB_REG_GPIO_23_IE_POS (16U)
-#define GLB_REG_GPIO_23_IE_LEN (1U)
+#define GLB_REG_GPIO_23_IE_POS (16)
+#define GLB_REG_GPIO_23_IE_LEN (1)
#define GLB_REG_GPIO_23_IE_MSK \
- (((1U << GLB_REG_GPIO_23_IE_LEN) - 1) << GLB_REG_GPIO_23_IE_POS)
+ (((1 << GLB_REG_GPIO_23_IE_LEN) - 1) << GLB_REG_GPIO_23_IE_POS)
#define GLB_REG_GPIO_23_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_23_IE_LEN) - 1) << GLB_REG_GPIO_23_IE_POS))
+ (~(((1 << GLB_REG_GPIO_23_IE_LEN) - 1) << GLB_REG_GPIO_23_IE_POS))
#define GLB_REG_GPIO_23_SMT GLB_REG_GPIO_23_SMT
-#define GLB_REG_GPIO_23_SMT_POS (17U)
-#define GLB_REG_GPIO_23_SMT_LEN (1U)
+#define GLB_REG_GPIO_23_SMT_POS (17)
+#define GLB_REG_GPIO_23_SMT_LEN (1)
#define GLB_REG_GPIO_23_SMT_MSK \
- (((1U << GLB_REG_GPIO_23_SMT_LEN) - 1) << GLB_REG_GPIO_23_SMT_POS)
+ (((1 << GLB_REG_GPIO_23_SMT_LEN) - 1) << GLB_REG_GPIO_23_SMT_POS)
#define GLB_REG_GPIO_23_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_23_SMT_LEN) - 1) << GLB_REG_GPIO_23_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_23_SMT_LEN) - 1) << GLB_REG_GPIO_23_SMT_POS))
#define GLB_REG_GPIO_23_DRV GLB_REG_GPIO_23_DRV
-#define GLB_REG_GPIO_23_DRV_POS (18U)
-#define GLB_REG_GPIO_23_DRV_LEN (2U)
+#define GLB_REG_GPIO_23_DRV_POS (18)
+#define GLB_REG_GPIO_23_DRV_LEN (2)
#define GLB_REG_GPIO_23_DRV_MSK \
- (((1U << GLB_REG_GPIO_23_DRV_LEN) - 1) << GLB_REG_GPIO_23_DRV_POS)
+ (((1 << GLB_REG_GPIO_23_DRV_LEN) - 1) << GLB_REG_GPIO_23_DRV_POS)
#define GLB_REG_GPIO_23_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_23_DRV_LEN) - 1) << GLB_REG_GPIO_23_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_23_DRV_LEN) - 1) << GLB_REG_GPIO_23_DRV_POS))
#define GLB_REG_GPIO_23_PU GLB_REG_GPIO_23_PU
-#define GLB_REG_GPIO_23_PU_POS (20U)
-#define GLB_REG_GPIO_23_PU_LEN (1U)
+#define GLB_REG_GPIO_23_PU_POS (20)
+#define GLB_REG_GPIO_23_PU_LEN (1)
#define GLB_REG_GPIO_23_PU_MSK \
- (((1U << GLB_REG_GPIO_23_PU_LEN) - 1) << GLB_REG_GPIO_23_PU_POS)
+ (((1 << GLB_REG_GPIO_23_PU_LEN) - 1) << GLB_REG_GPIO_23_PU_POS)
#define GLB_REG_GPIO_23_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_23_PU_LEN) - 1) << GLB_REG_GPIO_23_PU_POS))
+ (~(((1 << GLB_REG_GPIO_23_PU_LEN) - 1) << GLB_REG_GPIO_23_PU_POS))
#define GLB_REG_GPIO_23_PD GLB_REG_GPIO_23_PD
-#define GLB_REG_GPIO_23_PD_POS (21U)
-#define GLB_REG_GPIO_23_PD_LEN (1U)
+#define GLB_REG_GPIO_23_PD_POS (21)
+#define GLB_REG_GPIO_23_PD_LEN (1)
#define GLB_REG_GPIO_23_PD_MSK \
- (((1U << GLB_REG_GPIO_23_PD_LEN) - 1) << GLB_REG_GPIO_23_PD_POS)
+ (((1 << GLB_REG_GPIO_23_PD_LEN) - 1) << GLB_REG_GPIO_23_PD_POS)
#define GLB_REG_GPIO_23_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_23_PD_LEN) - 1) << GLB_REG_GPIO_23_PD_POS))
+ (~(((1 << GLB_REG_GPIO_23_PD_LEN) - 1) << GLB_REG_GPIO_23_PD_POS))
/* 0x130 : GPIO_CFGCTL12 */
#define GLB_GPIO_CFGCTL12_OFFSET (0x130)
#define GLB_REG_GPIO_24_IE GLB_REG_GPIO_24_IE
-#define GLB_REG_GPIO_24_IE_POS (0U)
-#define GLB_REG_GPIO_24_IE_LEN (1U)
+#define GLB_REG_GPIO_24_IE_POS (0)
+#define GLB_REG_GPIO_24_IE_LEN (1)
#define GLB_REG_GPIO_24_IE_MSK \
- (((1U << GLB_REG_GPIO_24_IE_LEN) - 1) << GLB_REG_GPIO_24_IE_POS)
+ (((1 << GLB_REG_GPIO_24_IE_LEN) - 1) << GLB_REG_GPIO_24_IE_POS)
#define GLB_REG_GPIO_24_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_24_IE_LEN) - 1) << GLB_REG_GPIO_24_IE_POS))
+ (~(((1 << GLB_REG_GPIO_24_IE_LEN) - 1) << GLB_REG_GPIO_24_IE_POS))
#define GLB_REG_GPIO_24_SMT GLB_REG_GPIO_24_SMT
-#define GLB_REG_GPIO_24_SMT_POS (1U)
-#define GLB_REG_GPIO_24_SMT_LEN (1U)
+#define GLB_REG_GPIO_24_SMT_POS (1)
+#define GLB_REG_GPIO_24_SMT_LEN (1)
#define GLB_REG_GPIO_24_SMT_MSK \
- (((1U << GLB_REG_GPIO_24_SMT_LEN) - 1) << GLB_REG_GPIO_24_SMT_POS)
+ (((1 << GLB_REG_GPIO_24_SMT_LEN) - 1) << GLB_REG_GPIO_24_SMT_POS)
#define GLB_REG_GPIO_24_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_24_SMT_LEN) - 1) << GLB_REG_GPIO_24_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_24_SMT_LEN) - 1) << GLB_REG_GPIO_24_SMT_POS))
#define GLB_REG_GPIO_24_DRV GLB_REG_GPIO_24_DRV
-#define GLB_REG_GPIO_24_DRV_POS (2U)
-#define GLB_REG_GPIO_24_DRV_LEN (2U)
+#define GLB_REG_GPIO_24_DRV_POS (2)
+#define GLB_REG_GPIO_24_DRV_LEN (2)
#define GLB_REG_GPIO_24_DRV_MSK \
- (((1U << GLB_REG_GPIO_24_DRV_LEN) - 1) << GLB_REG_GPIO_24_DRV_POS)
+ (((1 << GLB_REG_GPIO_24_DRV_LEN) - 1) << GLB_REG_GPIO_24_DRV_POS)
#define GLB_REG_GPIO_24_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_24_DRV_LEN) - 1) << GLB_REG_GPIO_24_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_24_DRV_LEN) - 1) << GLB_REG_GPIO_24_DRV_POS))
#define GLB_REG_GPIO_24_PU GLB_REG_GPIO_24_PU
-#define GLB_REG_GPIO_24_PU_POS (4U)
-#define GLB_REG_GPIO_24_PU_LEN (1U)
+#define GLB_REG_GPIO_24_PU_POS (4)
+#define GLB_REG_GPIO_24_PU_LEN (1)
#define GLB_REG_GPIO_24_PU_MSK \
- (((1U << GLB_REG_GPIO_24_PU_LEN) - 1) << GLB_REG_GPIO_24_PU_POS)
+ (((1 << GLB_REG_GPIO_24_PU_LEN) - 1) << GLB_REG_GPIO_24_PU_POS)
#define GLB_REG_GPIO_24_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_24_PU_LEN) - 1) << GLB_REG_GPIO_24_PU_POS))
+ (~(((1 << GLB_REG_GPIO_24_PU_LEN) - 1) << GLB_REG_GPIO_24_PU_POS))
#define GLB_REG_GPIO_24_PD GLB_REG_GPIO_24_PD
-#define GLB_REG_GPIO_24_PD_POS (5U)
-#define GLB_REG_GPIO_24_PD_LEN (1U)
+#define GLB_REG_GPIO_24_PD_POS (5)
+#define GLB_REG_GPIO_24_PD_LEN (1)
#define GLB_REG_GPIO_24_PD_MSK \
- (((1U << GLB_REG_GPIO_24_PD_LEN) - 1) << GLB_REG_GPIO_24_PD_POS)
+ (((1 << GLB_REG_GPIO_24_PD_LEN) - 1) << GLB_REG_GPIO_24_PD_POS)
#define GLB_REG_GPIO_24_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_24_PD_LEN) - 1) << GLB_REG_GPIO_24_PD_POS))
+ (~(((1 << GLB_REG_GPIO_24_PD_LEN) - 1) << GLB_REG_GPIO_24_PD_POS))
#define GLB_REG_GPIO_25_IE GLB_REG_GPIO_25_IE
-#define GLB_REG_GPIO_25_IE_POS (16U)
-#define GLB_REG_GPIO_25_IE_LEN (1U)
+#define GLB_REG_GPIO_25_IE_POS (16)
+#define GLB_REG_GPIO_25_IE_LEN (1)
#define GLB_REG_GPIO_25_IE_MSK \
- (((1U << GLB_REG_GPIO_25_IE_LEN) - 1) << GLB_REG_GPIO_25_IE_POS)
+ (((1 << GLB_REG_GPIO_25_IE_LEN) - 1) << GLB_REG_GPIO_25_IE_POS)
#define GLB_REG_GPIO_25_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_25_IE_LEN) - 1) << GLB_REG_GPIO_25_IE_POS))
+ (~(((1 << GLB_REG_GPIO_25_IE_LEN) - 1) << GLB_REG_GPIO_25_IE_POS))
#define GLB_REG_GPIO_25_SMT GLB_REG_GPIO_25_SMT
-#define GLB_REG_GPIO_25_SMT_POS (17U)
-#define GLB_REG_GPIO_25_SMT_LEN (1U)
+#define GLB_REG_GPIO_25_SMT_POS (17)
+#define GLB_REG_GPIO_25_SMT_LEN (1)
#define GLB_REG_GPIO_25_SMT_MSK \
- (((1U << GLB_REG_GPIO_25_SMT_LEN) - 1) << GLB_REG_GPIO_25_SMT_POS)
+ (((1 << GLB_REG_GPIO_25_SMT_LEN) - 1) << GLB_REG_GPIO_25_SMT_POS)
#define GLB_REG_GPIO_25_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_25_SMT_LEN) - 1) << GLB_REG_GPIO_25_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_25_SMT_LEN) - 1) << GLB_REG_GPIO_25_SMT_POS))
#define GLB_REG_GPIO_25_DRV GLB_REG_GPIO_25_DRV
-#define GLB_REG_GPIO_25_DRV_POS (18U)
-#define GLB_REG_GPIO_25_DRV_LEN (2U)
+#define GLB_REG_GPIO_25_DRV_POS (18)
+#define GLB_REG_GPIO_25_DRV_LEN (2)
#define GLB_REG_GPIO_25_DRV_MSK \
- (((1U << GLB_REG_GPIO_25_DRV_LEN) - 1) << GLB_REG_GPIO_25_DRV_POS)
+ (((1 << GLB_REG_GPIO_25_DRV_LEN) - 1) << GLB_REG_GPIO_25_DRV_POS)
#define GLB_REG_GPIO_25_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_25_DRV_LEN) - 1) << GLB_REG_GPIO_25_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_25_DRV_LEN) - 1) << GLB_REG_GPIO_25_DRV_POS))
#define GLB_REG_GPIO_25_PU GLB_REG_GPIO_25_PU
-#define GLB_REG_GPIO_25_PU_POS (20U)
-#define GLB_REG_GPIO_25_PU_LEN (1U)
+#define GLB_REG_GPIO_25_PU_POS (20)
+#define GLB_REG_GPIO_25_PU_LEN (1)
#define GLB_REG_GPIO_25_PU_MSK \
- (((1U << GLB_REG_GPIO_25_PU_LEN) - 1) << GLB_REG_GPIO_25_PU_POS)
+ (((1 << GLB_REG_GPIO_25_PU_LEN) - 1) << GLB_REG_GPIO_25_PU_POS)
#define GLB_REG_GPIO_25_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_25_PU_LEN) - 1) << GLB_REG_GPIO_25_PU_POS))
+ (~(((1 << GLB_REG_GPIO_25_PU_LEN) - 1) << GLB_REG_GPIO_25_PU_POS))
#define GLB_REG_GPIO_25_PD GLB_REG_GPIO_25_PD
-#define GLB_REG_GPIO_25_PD_POS (21U)
-#define GLB_REG_GPIO_25_PD_LEN (1U)
+#define GLB_REG_GPIO_25_PD_POS (21)
+#define GLB_REG_GPIO_25_PD_LEN (1)
#define GLB_REG_GPIO_25_PD_MSK \
- (((1U << GLB_REG_GPIO_25_PD_LEN) - 1) << GLB_REG_GPIO_25_PD_POS)
+ (((1 << GLB_REG_GPIO_25_PD_LEN) - 1) << GLB_REG_GPIO_25_PD_POS)
#define GLB_REG_GPIO_25_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_25_PD_LEN) - 1) << GLB_REG_GPIO_25_PD_POS))
+ (~(((1 << GLB_REG_GPIO_25_PD_LEN) - 1) << GLB_REG_GPIO_25_PD_POS))
/* 0x134 : GPIO_CFGCTL13 */
#define GLB_GPIO_CFGCTL13_OFFSET (0x134)
#define GLB_REG_GPIO_26_IE GLB_REG_GPIO_26_IE
-#define GLB_REG_GPIO_26_IE_POS (0U)
-#define GLB_REG_GPIO_26_IE_LEN (1U)
+#define GLB_REG_GPIO_26_IE_POS (0)
+#define GLB_REG_GPIO_26_IE_LEN (1)
#define GLB_REG_GPIO_26_IE_MSK \
- (((1U << GLB_REG_GPIO_26_IE_LEN) - 1) << GLB_REG_GPIO_26_IE_POS)
+ (((1 << GLB_REG_GPIO_26_IE_LEN) - 1) << GLB_REG_GPIO_26_IE_POS)
#define GLB_REG_GPIO_26_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_26_IE_LEN) - 1) << GLB_REG_GPIO_26_IE_POS))
+ (~(((1 << GLB_REG_GPIO_26_IE_LEN) - 1) << GLB_REG_GPIO_26_IE_POS))
#define GLB_REG_GPIO_26_SMT GLB_REG_GPIO_26_SMT
-#define GLB_REG_GPIO_26_SMT_POS (1U)
-#define GLB_REG_GPIO_26_SMT_LEN (1U)
+#define GLB_REG_GPIO_26_SMT_POS (1)
+#define GLB_REG_GPIO_26_SMT_LEN (1)
#define GLB_REG_GPIO_26_SMT_MSK \
- (((1U << GLB_REG_GPIO_26_SMT_LEN) - 1) << GLB_REG_GPIO_26_SMT_POS)
+ (((1 << GLB_REG_GPIO_26_SMT_LEN) - 1) << GLB_REG_GPIO_26_SMT_POS)
#define GLB_REG_GPIO_26_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_26_SMT_LEN) - 1) << GLB_REG_GPIO_26_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_26_SMT_LEN) - 1) << GLB_REG_GPIO_26_SMT_POS))
#define GLB_REG_GPIO_26_DRV GLB_REG_GPIO_26_DRV
-#define GLB_REG_GPIO_26_DRV_POS (2U)
-#define GLB_REG_GPIO_26_DRV_LEN (2U)
+#define GLB_REG_GPIO_26_DRV_POS (2)
+#define GLB_REG_GPIO_26_DRV_LEN (2)
#define GLB_REG_GPIO_26_DRV_MSK \
- (((1U << GLB_REG_GPIO_26_DRV_LEN) - 1) << GLB_REG_GPIO_26_DRV_POS)
+ (((1 << GLB_REG_GPIO_26_DRV_LEN) - 1) << GLB_REG_GPIO_26_DRV_POS)
#define GLB_REG_GPIO_26_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_26_DRV_LEN) - 1) << GLB_REG_GPIO_26_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_26_DRV_LEN) - 1) << GLB_REG_GPIO_26_DRV_POS))
#define GLB_REG_GPIO_26_PU GLB_REG_GPIO_26_PU
-#define GLB_REG_GPIO_26_PU_POS (4U)
-#define GLB_REG_GPIO_26_PU_LEN (1U)
+#define GLB_REG_GPIO_26_PU_POS (4)
+#define GLB_REG_GPIO_26_PU_LEN (1)
#define GLB_REG_GPIO_26_PU_MSK \
- (((1U << GLB_REG_GPIO_26_PU_LEN) - 1) << GLB_REG_GPIO_26_PU_POS)
+ (((1 << GLB_REG_GPIO_26_PU_LEN) - 1) << GLB_REG_GPIO_26_PU_POS)
#define GLB_REG_GPIO_26_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_26_PU_LEN) - 1) << GLB_REG_GPIO_26_PU_POS))
+ (~(((1 << GLB_REG_GPIO_26_PU_LEN) - 1) << GLB_REG_GPIO_26_PU_POS))
#define GLB_REG_GPIO_26_PD GLB_REG_GPIO_26_PD
-#define GLB_REG_GPIO_26_PD_POS (5U)
-#define GLB_REG_GPIO_26_PD_LEN (1U)
+#define GLB_REG_GPIO_26_PD_POS (5)
+#define GLB_REG_GPIO_26_PD_LEN (1)
#define GLB_REG_GPIO_26_PD_MSK \
- (((1U << GLB_REG_GPIO_26_PD_LEN) - 1) << GLB_REG_GPIO_26_PD_POS)
+ (((1 << GLB_REG_GPIO_26_PD_LEN) - 1) << GLB_REG_GPIO_26_PD_POS)
#define GLB_REG_GPIO_26_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_26_PD_LEN) - 1) << GLB_REG_GPIO_26_PD_POS))
+ (~(((1 << GLB_REG_GPIO_26_PD_LEN) - 1) << GLB_REG_GPIO_26_PD_POS))
#define GLB_REG_GPIO_27_IE GLB_REG_GPIO_27_IE
-#define GLB_REG_GPIO_27_IE_POS (16U)
-#define GLB_REG_GPIO_27_IE_LEN (1U)
+#define GLB_REG_GPIO_27_IE_POS (16)
+#define GLB_REG_GPIO_27_IE_LEN (1)
#define GLB_REG_GPIO_27_IE_MSK \
- (((1U << GLB_REG_GPIO_27_IE_LEN) - 1) << GLB_REG_GPIO_27_IE_POS)
+ (((1 << GLB_REG_GPIO_27_IE_LEN) - 1) << GLB_REG_GPIO_27_IE_POS)
#define GLB_REG_GPIO_27_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_27_IE_LEN) - 1) << GLB_REG_GPIO_27_IE_POS))
+ (~(((1 << GLB_REG_GPIO_27_IE_LEN) - 1) << GLB_REG_GPIO_27_IE_POS))
#define GLB_REG_GPIO_27_SMT GLB_REG_GPIO_27_SMT
-#define GLB_REG_GPIO_27_SMT_POS (17U)
-#define GLB_REG_GPIO_27_SMT_LEN (1U)
+#define GLB_REG_GPIO_27_SMT_POS (17)
+#define GLB_REG_GPIO_27_SMT_LEN (1)
#define GLB_REG_GPIO_27_SMT_MSK \
- (((1U << GLB_REG_GPIO_27_SMT_LEN) - 1) << GLB_REG_GPIO_27_SMT_POS)
+ (((1 << GLB_REG_GPIO_27_SMT_LEN) - 1) << GLB_REG_GPIO_27_SMT_POS)
#define GLB_REG_GPIO_27_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_27_SMT_LEN) - 1) << GLB_REG_GPIO_27_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_27_SMT_LEN) - 1) << GLB_REG_GPIO_27_SMT_POS))
#define GLB_REG_GPIO_27_DRV GLB_REG_GPIO_27_DRV
-#define GLB_REG_GPIO_27_DRV_POS (18U)
-#define GLB_REG_GPIO_27_DRV_LEN (2U)
+#define GLB_REG_GPIO_27_DRV_POS (18)
+#define GLB_REG_GPIO_27_DRV_LEN (2)
#define GLB_REG_GPIO_27_DRV_MSK \
- (((1U << GLB_REG_GPIO_27_DRV_LEN) - 1) << GLB_REG_GPIO_27_DRV_POS)
+ (((1 << GLB_REG_GPIO_27_DRV_LEN) - 1) << GLB_REG_GPIO_27_DRV_POS)
#define GLB_REG_GPIO_27_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_27_DRV_LEN) - 1) << GLB_REG_GPIO_27_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_27_DRV_LEN) - 1) << GLB_REG_GPIO_27_DRV_POS))
#define GLB_REG_GPIO_27_PU GLB_REG_GPIO_27_PU
-#define GLB_REG_GPIO_27_PU_POS (20U)
-#define GLB_REG_GPIO_27_PU_LEN (1U)
+#define GLB_REG_GPIO_27_PU_POS (20)
+#define GLB_REG_GPIO_27_PU_LEN (1)
#define GLB_REG_GPIO_27_PU_MSK \
- (((1U << GLB_REG_GPIO_27_PU_LEN) - 1) << GLB_REG_GPIO_27_PU_POS)
+ (((1 << GLB_REG_GPIO_27_PU_LEN) - 1) << GLB_REG_GPIO_27_PU_POS)
#define GLB_REG_GPIO_27_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_27_PU_LEN) - 1) << GLB_REG_GPIO_27_PU_POS))
+ (~(((1 << GLB_REG_GPIO_27_PU_LEN) - 1) << GLB_REG_GPIO_27_PU_POS))
#define GLB_REG_GPIO_27_PD GLB_REG_GPIO_27_PD
-#define GLB_REG_GPIO_27_PD_POS (21U)
-#define GLB_REG_GPIO_27_PD_LEN (1U)
+#define GLB_REG_GPIO_27_PD_POS (21)
+#define GLB_REG_GPIO_27_PD_LEN (1)
#define GLB_REG_GPIO_27_PD_MSK \
- (((1U << GLB_REG_GPIO_27_PD_LEN) - 1) << GLB_REG_GPIO_27_PD_POS)
+ (((1 << GLB_REG_GPIO_27_PD_LEN) - 1) << GLB_REG_GPIO_27_PD_POS)
#define GLB_REG_GPIO_27_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_27_PD_LEN) - 1) << GLB_REG_GPIO_27_PD_POS))
+ (~(((1 << GLB_REG_GPIO_27_PD_LEN) - 1) << GLB_REG_GPIO_27_PD_POS))
/* 0x138 : GPIO_CFGCTL14 */
#define GLB_GPIO_CFGCTL14_OFFSET (0x138)
#define GLB_REG_GPIO_28_IE GLB_REG_GPIO_28_IE
-#define GLB_REG_GPIO_28_IE_POS (0U)
-#define GLB_REG_GPIO_28_IE_LEN (1U)
+#define GLB_REG_GPIO_28_IE_POS (0)
+#define GLB_REG_GPIO_28_IE_LEN (1)
#define GLB_REG_GPIO_28_IE_MSK \
- (((1U << GLB_REG_GPIO_28_IE_LEN) - 1) << GLB_REG_GPIO_28_IE_POS)
+ (((1 << GLB_REG_GPIO_28_IE_LEN) - 1) << GLB_REG_GPIO_28_IE_POS)
#define GLB_REG_GPIO_28_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_28_IE_LEN) - 1) << GLB_REG_GPIO_28_IE_POS))
+ (~(((1 << GLB_REG_GPIO_28_IE_LEN) - 1) << GLB_REG_GPIO_28_IE_POS))
#define GLB_REG_GPIO_28_SMT GLB_REG_GPIO_28_SMT
-#define GLB_REG_GPIO_28_SMT_POS (1U)
-#define GLB_REG_GPIO_28_SMT_LEN (1U)
+#define GLB_REG_GPIO_28_SMT_POS (1)
+#define GLB_REG_GPIO_28_SMT_LEN (1)
#define GLB_REG_GPIO_28_SMT_MSK \
- (((1U << GLB_REG_GPIO_28_SMT_LEN) - 1) << GLB_REG_GPIO_28_SMT_POS)
+ (((1 << GLB_REG_GPIO_28_SMT_LEN) - 1) << GLB_REG_GPIO_28_SMT_POS)
#define GLB_REG_GPIO_28_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_28_SMT_LEN) - 1) << GLB_REG_GPIO_28_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_28_SMT_LEN) - 1) << GLB_REG_GPIO_28_SMT_POS))
#define GLB_REG_GPIO_28_DRV GLB_REG_GPIO_28_DRV
-#define GLB_REG_GPIO_28_DRV_POS (2U)
-#define GLB_REG_GPIO_28_DRV_LEN (2U)
+#define GLB_REG_GPIO_28_DRV_POS (2)
+#define GLB_REG_GPIO_28_DRV_LEN (2)
#define GLB_REG_GPIO_28_DRV_MSK \
- (((1U << GLB_REG_GPIO_28_DRV_LEN) - 1) << GLB_REG_GPIO_28_DRV_POS)
+ (((1 << GLB_REG_GPIO_28_DRV_LEN) - 1) << GLB_REG_GPIO_28_DRV_POS)
#define GLB_REG_GPIO_28_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_28_DRV_LEN) - 1) << GLB_REG_GPIO_28_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_28_DRV_LEN) - 1) << GLB_REG_GPIO_28_DRV_POS))
#define GLB_REG_GPIO_28_PU GLB_REG_GPIO_28_PU
-#define GLB_REG_GPIO_28_PU_POS (4U)
-#define GLB_REG_GPIO_28_PU_LEN (1U)
+#define GLB_REG_GPIO_28_PU_POS (4)
+#define GLB_REG_GPIO_28_PU_LEN (1)
#define GLB_REG_GPIO_28_PU_MSK \
- (((1U << GLB_REG_GPIO_28_PU_LEN) - 1) << GLB_REG_GPIO_28_PU_POS)
+ (((1 << GLB_REG_GPIO_28_PU_LEN) - 1) << GLB_REG_GPIO_28_PU_POS)
#define GLB_REG_GPIO_28_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_28_PU_LEN) - 1) << GLB_REG_GPIO_28_PU_POS))
+ (~(((1 << GLB_REG_GPIO_28_PU_LEN) - 1) << GLB_REG_GPIO_28_PU_POS))
#define GLB_REG_GPIO_28_PD GLB_REG_GPIO_28_PD
-#define GLB_REG_GPIO_28_PD_POS (5U)
-#define GLB_REG_GPIO_28_PD_LEN (1U)
+#define GLB_REG_GPIO_28_PD_POS (5)
+#define GLB_REG_GPIO_28_PD_LEN (1)
#define GLB_REG_GPIO_28_PD_MSK \
- (((1U << GLB_REG_GPIO_28_PD_LEN) - 1) << GLB_REG_GPIO_28_PD_POS)
+ (((1 << GLB_REG_GPIO_28_PD_LEN) - 1) << GLB_REG_GPIO_28_PD_POS)
#define GLB_REG_GPIO_28_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_28_PD_LEN) - 1) << GLB_REG_GPIO_28_PD_POS))
+ (~(((1 << GLB_REG_GPIO_28_PD_LEN) - 1) << GLB_REG_GPIO_28_PD_POS))
/* 0x180 : GPIO_CFGCTL30 */
#define GLB_GPIO_CFGCTL30_OFFSET (0x180)
#define GLB_REG_GPIO_0_I GLB_REG_GPIO_0_I
-#define GLB_REG_GPIO_0_I_POS (0U)
-#define GLB_REG_GPIO_0_I_LEN (1U)
+#define GLB_REG_GPIO_0_I_POS (0)
+#define GLB_REG_GPIO_0_I_LEN (1)
#define GLB_REG_GPIO_0_I_MSK \
- (((1U << GLB_REG_GPIO_0_I_LEN) - 1) << GLB_REG_GPIO_0_I_POS)
+ (((1 << GLB_REG_GPIO_0_I_LEN) - 1) << GLB_REG_GPIO_0_I_POS)
#define GLB_REG_GPIO_0_I_UMSK \
- (~(((1U << GLB_REG_GPIO_0_I_LEN) - 1) << GLB_REG_GPIO_0_I_POS))
+ (~(((1 << GLB_REG_GPIO_0_I_LEN) - 1) << GLB_REG_GPIO_0_I_POS))
#define GLB_REG_GPIO_1_I GLB_REG_GPIO_1_I
-#define GLB_REG_GPIO_1_I_POS (1U)
-#define GLB_REG_GPIO_1_I_LEN (1U)
+#define GLB_REG_GPIO_1_I_POS (1)
+#define GLB_REG_GPIO_1_I_LEN (1)
#define GLB_REG_GPIO_1_I_MSK \
- (((1U << GLB_REG_GPIO_1_I_LEN) - 1) << GLB_REG_GPIO_1_I_POS)
+ (((1 << GLB_REG_GPIO_1_I_LEN) - 1) << GLB_REG_GPIO_1_I_POS)
#define GLB_REG_GPIO_1_I_UMSK \
- (~(((1U << GLB_REG_GPIO_1_I_LEN) - 1) << GLB_REG_GPIO_1_I_POS))
+ (~(((1 << GLB_REG_GPIO_1_I_LEN) - 1) << GLB_REG_GPIO_1_I_POS))
#define GLB_REG_GPIO_2_I GLB_REG_GPIO_2_I
-#define GLB_REG_GPIO_2_I_POS (2U)
-#define GLB_REG_GPIO_2_I_LEN (1U)
+#define GLB_REG_GPIO_2_I_POS (2)
+#define GLB_REG_GPIO_2_I_LEN (1)
#define GLB_REG_GPIO_2_I_MSK \
- (((1U << GLB_REG_GPIO_2_I_LEN) - 1) << GLB_REG_GPIO_2_I_POS)
+ (((1 << GLB_REG_GPIO_2_I_LEN) - 1) << GLB_REG_GPIO_2_I_POS)
#define GLB_REG_GPIO_2_I_UMSK \
- (~(((1U << GLB_REG_GPIO_2_I_LEN) - 1) << GLB_REG_GPIO_2_I_POS))
+ (~(((1 << GLB_REG_GPIO_2_I_LEN) - 1) << GLB_REG_GPIO_2_I_POS))
#define GLB_REG_GPIO_3_I GLB_REG_GPIO_3_I
-#define GLB_REG_GPIO_3_I_POS (3U)
-#define GLB_REG_GPIO_3_I_LEN (1U)
+#define GLB_REG_GPIO_3_I_POS (3)
+#define GLB_REG_GPIO_3_I_LEN (1)
#define GLB_REG_GPIO_3_I_MSK \
- (((1U << GLB_REG_GPIO_3_I_LEN) - 1) << GLB_REG_GPIO_3_I_POS)
+ (((1 << GLB_REG_GPIO_3_I_LEN) - 1) << GLB_REG_GPIO_3_I_POS)
#define GLB_REG_GPIO_3_I_UMSK \
- (~(((1U << GLB_REG_GPIO_3_I_LEN) - 1) << GLB_REG_GPIO_3_I_POS))
+ (~(((1 << GLB_REG_GPIO_3_I_LEN) - 1) << GLB_REG_GPIO_3_I_POS))
#define GLB_REG_GPIO_4_I GLB_REG_GPIO_4_I
-#define GLB_REG_GPIO_4_I_POS (4U)
-#define GLB_REG_GPIO_4_I_LEN (1U)
+#define GLB_REG_GPIO_4_I_POS (4)
+#define GLB_REG_GPIO_4_I_LEN (1)
#define GLB_REG_GPIO_4_I_MSK \
- (((1U << GLB_REG_GPIO_4_I_LEN) - 1) << GLB_REG_GPIO_4_I_POS)
+ (((1 << GLB_REG_GPIO_4_I_LEN) - 1) << GLB_REG_GPIO_4_I_POS)
#define GLB_REG_GPIO_4_I_UMSK \
- (~(((1U << GLB_REG_GPIO_4_I_LEN) - 1) << GLB_REG_GPIO_4_I_POS))
+ (~(((1 << GLB_REG_GPIO_4_I_LEN) - 1) << GLB_REG_GPIO_4_I_POS))
#define GLB_REG_GPIO_5_I GLB_REG_GPIO_5_I
-#define GLB_REG_GPIO_5_I_POS (5U)
-#define GLB_REG_GPIO_5_I_LEN (1U)
+#define GLB_REG_GPIO_5_I_POS (5)
+#define GLB_REG_GPIO_5_I_LEN (1)
#define GLB_REG_GPIO_5_I_MSK \
- (((1U << GLB_REG_GPIO_5_I_LEN) - 1) << GLB_REG_GPIO_5_I_POS)
+ (((1 << GLB_REG_GPIO_5_I_LEN) - 1) << GLB_REG_GPIO_5_I_POS)
#define GLB_REG_GPIO_5_I_UMSK \
- (~(((1U << GLB_REG_GPIO_5_I_LEN) - 1) << GLB_REG_GPIO_5_I_POS))
+ (~(((1 << GLB_REG_GPIO_5_I_LEN) - 1) << GLB_REG_GPIO_5_I_POS))
#define GLB_REG_GPIO_6_I GLB_REG_GPIO_6_I
-#define GLB_REG_GPIO_6_I_POS (6U)
-#define GLB_REG_GPIO_6_I_LEN (1U)
+#define GLB_REG_GPIO_6_I_POS (6)
+#define GLB_REG_GPIO_6_I_LEN (1)
#define GLB_REG_GPIO_6_I_MSK \
- (((1U << GLB_REG_GPIO_6_I_LEN) - 1) << GLB_REG_GPIO_6_I_POS)
+ (((1 << GLB_REG_GPIO_6_I_LEN) - 1) << GLB_REG_GPIO_6_I_POS)
#define GLB_REG_GPIO_6_I_UMSK \
- (~(((1U << GLB_REG_GPIO_6_I_LEN) - 1) << GLB_REG_GPIO_6_I_POS))
+ (~(((1 << GLB_REG_GPIO_6_I_LEN) - 1) << GLB_REG_GPIO_6_I_POS))
#define GLB_REG_GPIO_7_I GLB_REG_GPIO_7_I
-#define GLB_REG_GPIO_7_I_POS (7U)
-#define GLB_REG_GPIO_7_I_LEN (1U)
+#define GLB_REG_GPIO_7_I_POS (7)
+#define GLB_REG_GPIO_7_I_LEN (1)
#define GLB_REG_GPIO_7_I_MSK \
- (((1U << GLB_REG_GPIO_7_I_LEN) - 1) << GLB_REG_GPIO_7_I_POS)
+ (((1 << GLB_REG_GPIO_7_I_LEN) - 1) << GLB_REG_GPIO_7_I_POS)
#define GLB_REG_GPIO_7_I_UMSK \
- (~(((1U << GLB_REG_GPIO_7_I_LEN) - 1) << GLB_REG_GPIO_7_I_POS))
+ (~(((1 << GLB_REG_GPIO_7_I_LEN) - 1) << GLB_REG_GPIO_7_I_POS))
#define GLB_REG_GPIO_8_I GLB_REG_GPIO_8_I
-#define GLB_REG_GPIO_8_I_POS (8U)
-#define GLB_REG_GPIO_8_I_LEN (1U)
+#define GLB_REG_GPIO_8_I_POS (8)
+#define GLB_REG_GPIO_8_I_LEN (1)
#define GLB_REG_GPIO_8_I_MSK \
- (((1U << GLB_REG_GPIO_8_I_LEN) - 1) << GLB_REG_GPIO_8_I_POS)
+ (((1 << GLB_REG_GPIO_8_I_LEN) - 1) << GLB_REG_GPIO_8_I_POS)
#define GLB_REG_GPIO_8_I_UMSK \
- (~(((1U << GLB_REG_GPIO_8_I_LEN) - 1) << GLB_REG_GPIO_8_I_POS))
+ (~(((1 << GLB_REG_GPIO_8_I_LEN) - 1) << GLB_REG_GPIO_8_I_POS))
#define GLB_REG_GPIO_9_I GLB_REG_GPIO_9_I
-#define GLB_REG_GPIO_9_I_POS (9U)
-#define GLB_REG_GPIO_9_I_LEN (1U)
+#define GLB_REG_GPIO_9_I_POS (9)
+#define GLB_REG_GPIO_9_I_LEN (1)
#define GLB_REG_GPIO_9_I_MSK \
- (((1U << GLB_REG_GPIO_9_I_LEN) - 1) << GLB_REG_GPIO_9_I_POS)
+ (((1 << GLB_REG_GPIO_9_I_LEN) - 1) << GLB_REG_GPIO_9_I_POS)
#define GLB_REG_GPIO_9_I_UMSK \
- (~(((1U << GLB_REG_GPIO_9_I_LEN) - 1) << GLB_REG_GPIO_9_I_POS))
+ (~(((1 << GLB_REG_GPIO_9_I_LEN) - 1) << GLB_REG_GPIO_9_I_POS))
#define GLB_REG_GPIO_10_I GLB_REG_GPIO_10_I
-#define GLB_REG_GPIO_10_I_POS (10U)
-#define GLB_REG_GPIO_10_I_LEN (1U)
+#define GLB_REG_GPIO_10_I_POS (10)
+#define GLB_REG_GPIO_10_I_LEN (1)
#define GLB_REG_GPIO_10_I_MSK \
- (((1U << GLB_REG_GPIO_10_I_LEN) - 1) << GLB_REG_GPIO_10_I_POS)
+ (((1 << GLB_REG_GPIO_10_I_LEN) - 1) << GLB_REG_GPIO_10_I_POS)
#define GLB_REG_GPIO_10_I_UMSK \
- (~(((1U << GLB_REG_GPIO_10_I_LEN) - 1) << GLB_REG_GPIO_10_I_POS))
+ (~(((1 << GLB_REG_GPIO_10_I_LEN) - 1) << GLB_REG_GPIO_10_I_POS))
#define GLB_REG_GPIO_11_I GLB_REG_GPIO_11_I
-#define GLB_REG_GPIO_11_I_POS (11U)
-#define GLB_REG_GPIO_11_I_LEN (1U)
+#define GLB_REG_GPIO_11_I_POS (11)
+#define GLB_REG_GPIO_11_I_LEN (1)
#define GLB_REG_GPIO_11_I_MSK \
- (((1U << GLB_REG_GPIO_11_I_LEN) - 1) << GLB_REG_GPIO_11_I_POS)
+ (((1 << GLB_REG_GPIO_11_I_LEN) - 1) << GLB_REG_GPIO_11_I_POS)
#define GLB_REG_GPIO_11_I_UMSK \
- (~(((1U << GLB_REG_GPIO_11_I_LEN) - 1) << GLB_REG_GPIO_11_I_POS))
+ (~(((1 << GLB_REG_GPIO_11_I_LEN) - 1) << GLB_REG_GPIO_11_I_POS))
#define GLB_REG_GPIO_12_I GLB_REG_GPIO_12_I
-#define GLB_REG_GPIO_12_I_POS (12U)
-#define GLB_REG_GPIO_12_I_LEN (1U)
+#define GLB_REG_GPIO_12_I_POS (12)
+#define GLB_REG_GPIO_12_I_LEN (1)
#define GLB_REG_GPIO_12_I_MSK \
- (((1U << GLB_REG_GPIO_12_I_LEN) - 1) << GLB_REG_GPIO_12_I_POS)
+ (((1 << GLB_REG_GPIO_12_I_LEN) - 1) << GLB_REG_GPIO_12_I_POS)
#define GLB_REG_GPIO_12_I_UMSK \
- (~(((1U << GLB_REG_GPIO_12_I_LEN) - 1) << GLB_REG_GPIO_12_I_POS))
+ (~(((1 << GLB_REG_GPIO_12_I_LEN) - 1) << GLB_REG_GPIO_12_I_POS))
#define GLB_REG_GPIO_13_I GLB_REG_GPIO_13_I
-#define GLB_REG_GPIO_13_I_POS (13U)
-#define GLB_REG_GPIO_13_I_LEN (1U)
+#define GLB_REG_GPIO_13_I_POS (13)
+#define GLB_REG_GPIO_13_I_LEN (1)
#define GLB_REG_GPIO_13_I_MSK \
- (((1U << GLB_REG_GPIO_13_I_LEN) - 1) << GLB_REG_GPIO_13_I_POS)
+ (((1 << GLB_REG_GPIO_13_I_LEN) - 1) << GLB_REG_GPIO_13_I_POS)
#define GLB_REG_GPIO_13_I_UMSK \
- (~(((1U << GLB_REG_GPIO_13_I_LEN) - 1) << GLB_REG_GPIO_13_I_POS))
+ (~(((1 << GLB_REG_GPIO_13_I_LEN) - 1) << GLB_REG_GPIO_13_I_POS))
#define GLB_REG_GPIO_14_I GLB_REG_GPIO_14_I
-#define GLB_REG_GPIO_14_I_POS (14U)
-#define GLB_REG_GPIO_14_I_LEN (1U)
+#define GLB_REG_GPIO_14_I_POS (14)
+#define GLB_REG_GPIO_14_I_LEN (1)
#define GLB_REG_GPIO_14_I_MSK \
- (((1U << GLB_REG_GPIO_14_I_LEN) - 1) << GLB_REG_GPIO_14_I_POS)
+ (((1 << GLB_REG_GPIO_14_I_LEN) - 1) << GLB_REG_GPIO_14_I_POS)
#define GLB_REG_GPIO_14_I_UMSK \
- (~(((1U << GLB_REG_GPIO_14_I_LEN) - 1) << GLB_REG_GPIO_14_I_POS))
+ (~(((1 << GLB_REG_GPIO_14_I_LEN) - 1) << GLB_REG_GPIO_14_I_POS))
#define GLB_REG_GPIO_15_I GLB_REG_GPIO_15_I
-#define GLB_REG_GPIO_15_I_POS (15U)
-#define GLB_REG_GPIO_15_I_LEN (1U)
+#define GLB_REG_GPIO_15_I_POS (15)
+#define GLB_REG_GPIO_15_I_LEN (1)
#define GLB_REG_GPIO_15_I_MSK \
- (((1U << GLB_REG_GPIO_15_I_LEN) - 1) << GLB_REG_GPIO_15_I_POS)
+ (((1 << GLB_REG_GPIO_15_I_LEN) - 1) << GLB_REG_GPIO_15_I_POS)
#define GLB_REG_GPIO_15_I_UMSK \
- (~(((1U << GLB_REG_GPIO_15_I_LEN) - 1) << GLB_REG_GPIO_15_I_POS))
+ (~(((1 << GLB_REG_GPIO_15_I_LEN) - 1) << GLB_REG_GPIO_15_I_POS))
#define GLB_REG_GPIO_16_I GLB_REG_GPIO_16_I
-#define GLB_REG_GPIO_16_I_POS (16U)
-#define GLB_REG_GPIO_16_I_LEN (1U)
+#define GLB_REG_GPIO_16_I_POS (16)
+#define GLB_REG_GPIO_16_I_LEN (1)
#define GLB_REG_GPIO_16_I_MSK \
- (((1U << GLB_REG_GPIO_16_I_LEN) - 1) << GLB_REG_GPIO_16_I_POS)
+ (((1 << GLB_REG_GPIO_16_I_LEN) - 1) << GLB_REG_GPIO_16_I_POS)
#define GLB_REG_GPIO_16_I_UMSK \
- (~(((1U << GLB_REG_GPIO_16_I_LEN) - 1) << GLB_REG_GPIO_16_I_POS))
+ (~(((1 << GLB_REG_GPIO_16_I_LEN) - 1) << GLB_REG_GPIO_16_I_POS))
#define GLB_REG_GPIO_17_I GLB_REG_GPIO_17_I
-#define GLB_REG_GPIO_17_I_POS (17U)
-#define GLB_REG_GPIO_17_I_LEN (1U)
+#define GLB_REG_GPIO_17_I_POS (17)
+#define GLB_REG_GPIO_17_I_LEN (1)
#define GLB_REG_GPIO_17_I_MSK \
- (((1U << GLB_REG_GPIO_17_I_LEN) - 1) << GLB_REG_GPIO_17_I_POS)
+ (((1 << GLB_REG_GPIO_17_I_LEN) - 1) << GLB_REG_GPIO_17_I_POS)
#define GLB_REG_GPIO_17_I_UMSK \
- (~(((1U << GLB_REG_GPIO_17_I_LEN) - 1) << GLB_REG_GPIO_17_I_POS))
+ (~(((1 << GLB_REG_GPIO_17_I_LEN) - 1) << GLB_REG_GPIO_17_I_POS))
#define GLB_REG_GPIO_18_I GLB_REG_GPIO_18_I
-#define GLB_REG_GPIO_18_I_POS (18U)
-#define GLB_REG_GPIO_18_I_LEN (1U)
+#define GLB_REG_GPIO_18_I_POS (18)
+#define GLB_REG_GPIO_18_I_LEN (1)
#define GLB_REG_GPIO_18_I_MSK \
- (((1U << GLB_REG_GPIO_18_I_LEN) - 1) << GLB_REG_GPIO_18_I_POS)
+ (((1 << GLB_REG_GPIO_18_I_LEN) - 1) << GLB_REG_GPIO_18_I_POS)
#define GLB_REG_GPIO_18_I_UMSK \
- (~(((1U << GLB_REG_GPIO_18_I_LEN) - 1) << GLB_REG_GPIO_18_I_POS))
+ (~(((1 << GLB_REG_GPIO_18_I_LEN) - 1) << GLB_REG_GPIO_18_I_POS))
#define GLB_REG_GPIO_19_I GLB_REG_GPIO_19_I
-#define GLB_REG_GPIO_19_I_POS (19U)
-#define GLB_REG_GPIO_19_I_LEN (1U)
+#define GLB_REG_GPIO_19_I_POS (19)
+#define GLB_REG_GPIO_19_I_LEN (1)
#define GLB_REG_GPIO_19_I_MSK \
- (((1U << GLB_REG_GPIO_19_I_LEN) - 1) << GLB_REG_GPIO_19_I_POS)
+ (((1 << GLB_REG_GPIO_19_I_LEN) - 1) << GLB_REG_GPIO_19_I_POS)
#define GLB_REG_GPIO_19_I_UMSK \
- (~(((1U << GLB_REG_GPIO_19_I_LEN) - 1) << GLB_REG_GPIO_19_I_POS))
+ (~(((1 << GLB_REG_GPIO_19_I_LEN) - 1) << GLB_REG_GPIO_19_I_POS))
#define GLB_REG_GPIO_20_I GLB_REG_GPIO_20_I
-#define GLB_REG_GPIO_20_I_POS (20U)
-#define GLB_REG_GPIO_20_I_LEN (1U)
+#define GLB_REG_GPIO_20_I_POS (20)
+#define GLB_REG_GPIO_20_I_LEN (1)
#define GLB_REG_GPIO_20_I_MSK \
- (((1U << GLB_REG_GPIO_20_I_LEN) - 1) << GLB_REG_GPIO_20_I_POS)
+ (((1 << GLB_REG_GPIO_20_I_LEN) - 1) << GLB_REG_GPIO_20_I_POS)
#define GLB_REG_GPIO_20_I_UMSK \
- (~(((1U << GLB_REG_GPIO_20_I_LEN) - 1) << GLB_REG_GPIO_20_I_POS))
+ (~(((1 << GLB_REG_GPIO_20_I_LEN) - 1) << GLB_REG_GPIO_20_I_POS))
#define GLB_REG_GPIO_21_I GLB_REG_GPIO_21_I
-#define GLB_REG_GPIO_21_I_POS (21U)
-#define GLB_REG_GPIO_21_I_LEN (1U)
+#define GLB_REG_GPIO_21_I_POS (21)
+#define GLB_REG_GPIO_21_I_LEN (1)
#define GLB_REG_GPIO_21_I_MSK \
- (((1U << GLB_REG_GPIO_21_I_LEN) - 1) << GLB_REG_GPIO_21_I_POS)
+ (((1 << GLB_REG_GPIO_21_I_LEN) - 1) << GLB_REG_GPIO_21_I_POS)
#define GLB_REG_GPIO_21_I_UMSK \
- (~(((1U << GLB_REG_GPIO_21_I_LEN) - 1) << GLB_REG_GPIO_21_I_POS))
+ (~(((1 << GLB_REG_GPIO_21_I_LEN) - 1) << GLB_REG_GPIO_21_I_POS))
#define GLB_REG_GPIO_22_I GLB_REG_GPIO_22_I
-#define GLB_REG_GPIO_22_I_POS (22U)
-#define GLB_REG_GPIO_22_I_LEN (1U)
+#define GLB_REG_GPIO_22_I_POS (22)
+#define GLB_REG_GPIO_22_I_LEN (1)
#define GLB_REG_GPIO_22_I_MSK \
- (((1U << GLB_REG_GPIO_22_I_LEN) - 1) << GLB_REG_GPIO_22_I_POS)
+ (((1 << GLB_REG_GPIO_22_I_LEN) - 1) << GLB_REG_GPIO_22_I_POS)
#define GLB_REG_GPIO_22_I_UMSK \
- (~(((1U << GLB_REG_GPIO_22_I_LEN) - 1) << GLB_REG_GPIO_22_I_POS))
+ (~(((1 << GLB_REG_GPIO_22_I_LEN) - 1) << GLB_REG_GPIO_22_I_POS))
/* 0x184 : GPIO_CFGCTL31 */
@@ -2714,166 +2705,166 @@
#define GLB_GPIO_CFGCTL32_OFFSET (0x188)
#define GLB_REG_GPIO_0_O GLB_REG_GPIO_0_O
-#define GLB_REG_GPIO_0_O_POS (0U)
-#define GLB_REG_GPIO_0_O_LEN (1U)
+#define GLB_REG_GPIO_0_O_POS (0)
+#define GLB_REG_GPIO_0_O_LEN (1)
#define GLB_REG_GPIO_0_O_MSK \
- (((1U << GLB_REG_GPIO_0_O_LEN) - 1) << GLB_REG_GPIO_0_O_POS)
+ (((1 << GLB_REG_GPIO_0_O_LEN) - 1) << GLB_REG_GPIO_0_O_POS)
#define GLB_REG_GPIO_0_O_UMSK \
- (~(((1U << GLB_REG_GPIO_0_O_LEN) - 1) << GLB_REG_GPIO_0_O_POS))
+ (~(((1 << GLB_REG_GPIO_0_O_LEN) - 1) << GLB_REG_GPIO_0_O_POS))
#define GLB_REG_GPIO_1_O GLB_REG_GPIO_1_O
-#define GLB_REG_GPIO_1_O_POS (1U)
-#define GLB_REG_GPIO_1_O_LEN (1U)
+#define GLB_REG_GPIO_1_O_POS (1)
+#define GLB_REG_GPIO_1_O_LEN (1)
#define GLB_REG_GPIO_1_O_MSK \
- (((1U << GLB_REG_GPIO_1_O_LEN) - 1) << GLB_REG_GPIO_1_O_POS)
+ (((1 << GLB_REG_GPIO_1_O_LEN) - 1) << GLB_REG_GPIO_1_O_POS)
#define GLB_REG_GPIO_1_O_UMSK \
- (~(((1U << GLB_REG_GPIO_1_O_LEN) - 1) << GLB_REG_GPIO_1_O_POS))
+ (~(((1 << GLB_REG_GPIO_1_O_LEN) - 1) << GLB_REG_GPIO_1_O_POS))
#define GLB_REG_GPIO_2_O GLB_REG_GPIO_2_O
-#define GLB_REG_GPIO_2_O_POS (2U)
-#define GLB_REG_GPIO_2_O_LEN (1U)
+#define GLB_REG_GPIO_2_O_POS (2)
+#define GLB_REG_GPIO_2_O_LEN (1)
#define GLB_REG_GPIO_2_O_MSK \
- (((1U << GLB_REG_GPIO_2_O_LEN) - 1) << GLB_REG_GPIO_2_O_POS)
+ (((1 << GLB_REG_GPIO_2_O_LEN) - 1) << GLB_REG_GPIO_2_O_POS)
#define GLB_REG_GPIO_2_O_UMSK \
- (~(((1U << GLB_REG_GPIO_2_O_LEN) - 1) << GLB_REG_GPIO_2_O_POS))
+ (~(((1 << GLB_REG_GPIO_2_O_LEN) - 1) << GLB_REG_GPIO_2_O_POS))
#define GLB_REG_GPIO_3_O GLB_REG_GPIO_3_O
-#define GLB_REG_GPIO_3_O_POS (3U)
-#define GLB_REG_GPIO_3_O_LEN (1U)
+#define GLB_REG_GPIO_3_O_POS (3)
+#define GLB_REG_GPIO_3_O_LEN (1)
#define GLB_REG_GPIO_3_O_MSK \
- (((1U << GLB_REG_GPIO_3_O_LEN) - 1) << GLB_REG_GPIO_3_O_POS)
+ (((1 << GLB_REG_GPIO_3_O_LEN) - 1) << GLB_REG_GPIO_3_O_POS)
#define GLB_REG_GPIO_3_O_UMSK \
- (~(((1U << GLB_REG_GPIO_3_O_LEN) - 1) << GLB_REG_GPIO_3_O_POS))
+ (~(((1 << GLB_REG_GPIO_3_O_LEN) - 1) << GLB_REG_GPIO_3_O_POS))
#define GLB_REG_GPIO_4_O GLB_REG_GPIO_4_O
-#define GLB_REG_GPIO_4_O_POS (4U)
-#define GLB_REG_GPIO_4_O_LEN (1U)
+#define GLB_REG_GPIO_4_O_POS (4)
+#define GLB_REG_GPIO_4_O_LEN (1)
#define GLB_REG_GPIO_4_O_MSK \
- (((1U << GLB_REG_GPIO_4_O_LEN) - 1) << GLB_REG_GPIO_4_O_POS)
+ (((1 << GLB_REG_GPIO_4_O_LEN) - 1) << GLB_REG_GPIO_4_O_POS)
#define GLB_REG_GPIO_4_O_UMSK \
- (~(((1U << GLB_REG_GPIO_4_O_LEN) - 1) << GLB_REG_GPIO_4_O_POS))
+ (~(((1 << GLB_REG_GPIO_4_O_LEN) - 1) << GLB_REG_GPIO_4_O_POS))
#define GLB_REG_GPIO_5_O GLB_REG_GPIO_5_O
-#define GLB_REG_GPIO_5_O_POS (5U)
-#define GLB_REG_GPIO_5_O_LEN (1U)
+#define GLB_REG_GPIO_5_O_POS (5)
+#define GLB_REG_GPIO_5_O_LEN (1)
#define GLB_REG_GPIO_5_O_MSK \
- (((1U << GLB_REG_GPIO_5_O_LEN) - 1) << GLB_REG_GPIO_5_O_POS)
+ (((1 << GLB_REG_GPIO_5_O_LEN) - 1) << GLB_REG_GPIO_5_O_POS)
#define GLB_REG_GPIO_5_O_UMSK \
- (~(((1U << GLB_REG_GPIO_5_O_LEN) - 1) << GLB_REG_GPIO_5_O_POS))
+ (~(((1 << GLB_REG_GPIO_5_O_LEN) - 1) << GLB_REG_GPIO_5_O_POS))
#define GLB_REG_GPIO_6_O GLB_REG_GPIO_6_O
-#define GLB_REG_GPIO_6_O_POS (6U)
-#define GLB_REG_GPIO_6_O_LEN (1U)
+#define GLB_REG_GPIO_6_O_POS (6)
+#define GLB_REG_GPIO_6_O_LEN (1)
#define GLB_REG_GPIO_6_O_MSK \
- (((1U << GLB_REG_GPIO_6_O_LEN) - 1) << GLB_REG_GPIO_6_O_POS)
+ (((1 << GLB_REG_GPIO_6_O_LEN) - 1) << GLB_REG_GPIO_6_O_POS)
#define GLB_REG_GPIO_6_O_UMSK \
- (~(((1U << GLB_REG_GPIO_6_O_LEN) - 1) << GLB_REG_GPIO_6_O_POS))
+ (~(((1 << GLB_REG_GPIO_6_O_LEN) - 1) << GLB_REG_GPIO_6_O_POS))
#define GLB_REG_GPIO_7_O GLB_REG_GPIO_7_O
-#define GLB_REG_GPIO_7_O_POS (7U)
-#define GLB_REG_GPIO_7_O_LEN (1U)
+#define GLB_REG_GPIO_7_O_POS (7)
+#define GLB_REG_GPIO_7_O_LEN (1)
#define GLB_REG_GPIO_7_O_MSK \
- (((1U << GLB_REG_GPIO_7_O_LEN) - 1) << GLB_REG_GPIO_7_O_POS)
+ (((1 << GLB_REG_GPIO_7_O_LEN) - 1) << GLB_REG_GPIO_7_O_POS)
#define GLB_REG_GPIO_7_O_UMSK \
- (~(((1U << GLB_REG_GPIO_7_O_LEN) - 1) << GLB_REG_GPIO_7_O_POS))
+ (~(((1 << GLB_REG_GPIO_7_O_LEN) - 1) << GLB_REG_GPIO_7_O_POS))
#define GLB_REG_GPIO_8_O GLB_REG_GPIO_8_O
-#define GLB_REG_GPIO_8_O_POS (8U)
-#define GLB_REG_GPIO_8_O_LEN (1U)
+#define GLB_REG_GPIO_8_O_POS (8)
+#define GLB_REG_GPIO_8_O_LEN (1)
#define GLB_REG_GPIO_8_O_MSK \
- (((1U << GLB_REG_GPIO_8_O_LEN) - 1) << GLB_REG_GPIO_8_O_POS)
+ (((1 << GLB_REG_GPIO_8_O_LEN) - 1) << GLB_REG_GPIO_8_O_POS)
#define GLB_REG_GPIO_8_O_UMSK \
- (~(((1U << GLB_REG_GPIO_8_O_LEN) - 1) << GLB_REG_GPIO_8_O_POS))
+ (~(((1 << GLB_REG_GPIO_8_O_LEN) - 1) << GLB_REG_GPIO_8_O_POS))
#define GLB_REG_GPIO_9_O GLB_REG_GPIO_9_O
-#define GLB_REG_GPIO_9_O_POS (9U)
-#define GLB_REG_GPIO_9_O_LEN (1U)
+#define GLB_REG_GPIO_9_O_POS (9)
+#define GLB_REG_GPIO_9_O_LEN (1)
#define GLB_REG_GPIO_9_O_MSK \
- (((1U << GLB_REG_GPIO_9_O_LEN) - 1) << GLB_REG_GPIO_9_O_POS)
+ (((1 << GLB_REG_GPIO_9_O_LEN) - 1) << GLB_REG_GPIO_9_O_POS)
#define GLB_REG_GPIO_9_O_UMSK \
- (~(((1U << GLB_REG_GPIO_9_O_LEN) - 1) << GLB_REG_GPIO_9_O_POS))
+ (~(((1 << GLB_REG_GPIO_9_O_LEN) - 1) << GLB_REG_GPIO_9_O_POS))
#define GLB_REG_GPIO_10_O GLB_REG_GPIO_10_O
-#define GLB_REG_GPIO_10_O_POS (10U)
-#define GLB_REG_GPIO_10_O_LEN (1U)
+#define GLB_REG_GPIO_10_O_POS (10)
+#define GLB_REG_GPIO_10_O_LEN (1)
#define GLB_REG_GPIO_10_O_MSK \
- (((1U << GLB_REG_GPIO_10_O_LEN) - 1) << GLB_REG_GPIO_10_O_POS)
+ (((1 << GLB_REG_GPIO_10_O_LEN) - 1) << GLB_REG_GPIO_10_O_POS)
#define GLB_REG_GPIO_10_O_UMSK \
- (~(((1U << GLB_REG_GPIO_10_O_LEN) - 1) << GLB_REG_GPIO_10_O_POS))
+ (~(((1 << GLB_REG_GPIO_10_O_LEN) - 1) << GLB_REG_GPIO_10_O_POS))
#define GLB_REG_GPIO_11_O GLB_REG_GPIO_11_O
-#define GLB_REG_GPIO_11_O_POS (11U)
-#define GLB_REG_GPIO_11_O_LEN (1U)
+#define GLB_REG_GPIO_11_O_POS (11)
+#define GLB_REG_GPIO_11_O_LEN (1)
#define GLB_REG_GPIO_11_O_MSK \
- (((1U << GLB_REG_GPIO_11_O_LEN) - 1) << GLB_REG_GPIO_11_O_POS)
+ (((1 << GLB_REG_GPIO_11_O_LEN) - 1) << GLB_REG_GPIO_11_O_POS)
#define GLB_REG_GPIO_11_O_UMSK \
- (~(((1U << GLB_REG_GPIO_11_O_LEN) - 1) << GLB_REG_GPIO_11_O_POS))
+ (~(((1 << GLB_REG_GPIO_11_O_LEN) - 1) << GLB_REG_GPIO_11_O_POS))
#define GLB_REG_GPIO_12_O GLB_REG_GPIO_12_O
-#define GLB_REG_GPIO_12_O_POS (12U)
-#define GLB_REG_GPIO_12_O_LEN (1U)
+#define GLB_REG_GPIO_12_O_POS (12)
+#define GLB_REG_GPIO_12_O_LEN (1)
#define GLB_REG_GPIO_12_O_MSK \
- (((1U << GLB_REG_GPIO_12_O_LEN) - 1) << GLB_REG_GPIO_12_O_POS)
+ (((1 << GLB_REG_GPIO_12_O_LEN) - 1) << GLB_REG_GPIO_12_O_POS)
#define GLB_REG_GPIO_12_O_UMSK \
- (~(((1U << GLB_REG_GPIO_12_O_LEN) - 1) << GLB_REG_GPIO_12_O_POS))
+ (~(((1 << GLB_REG_GPIO_12_O_LEN) - 1) << GLB_REG_GPIO_12_O_POS))
#define GLB_REG_GPIO_13_O GLB_REG_GPIO_13_O
-#define GLB_REG_GPIO_13_O_POS (13U)
-#define GLB_REG_GPIO_13_O_LEN (1U)
+#define GLB_REG_GPIO_13_O_POS (13)
+#define GLB_REG_GPIO_13_O_LEN (1)
#define GLB_REG_GPIO_13_O_MSK \
- (((1U << GLB_REG_GPIO_13_O_LEN) - 1) << GLB_REG_GPIO_13_O_POS)
+ (((1 << GLB_REG_GPIO_13_O_LEN) - 1) << GLB_REG_GPIO_13_O_POS)
#define GLB_REG_GPIO_13_O_UMSK \
- (~(((1U << GLB_REG_GPIO_13_O_LEN) - 1) << GLB_REG_GPIO_13_O_POS))
+ (~(((1 << GLB_REG_GPIO_13_O_LEN) - 1) << GLB_REG_GPIO_13_O_POS))
#define GLB_REG_GPIO_14_O GLB_REG_GPIO_14_O
-#define GLB_REG_GPIO_14_O_POS (14U)
-#define GLB_REG_GPIO_14_O_LEN (1U)
+#define GLB_REG_GPIO_14_O_POS (14)
+#define GLB_REG_GPIO_14_O_LEN (1)
#define GLB_REG_GPIO_14_O_MSK \
- (((1U << GLB_REG_GPIO_14_O_LEN) - 1) << GLB_REG_GPIO_14_O_POS)
+ (((1 << GLB_REG_GPIO_14_O_LEN) - 1) << GLB_REG_GPIO_14_O_POS)
#define GLB_REG_GPIO_14_O_UMSK \
- (~(((1U << GLB_REG_GPIO_14_O_LEN) - 1) << GLB_REG_GPIO_14_O_POS))
+ (~(((1 << GLB_REG_GPIO_14_O_LEN) - 1) << GLB_REG_GPIO_14_O_POS))
#define GLB_REG_GPIO_15_O GLB_REG_GPIO_15_O
-#define GLB_REG_GPIO_15_O_POS (15U)
-#define GLB_REG_GPIO_15_O_LEN (1U)
+#define GLB_REG_GPIO_15_O_POS (15)
+#define GLB_REG_GPIO_15_O_LEN (1)
#define GLB_REG_GPIO_15_O_MSK \
- (((1U << GLB_REG_GPIO_15_O_LEN) - 1) << GLB_REG_GPIO_15_O_POS)
+ (((1 << GLB_REG_GPIO_15_O_LEN) - 1) << GLB_REG_GPIO_15_O_POS)
#define GLB_REG_GPIO_15_O_UMSK \
- (~(((1U << GLB_REG_GPIO_15_O_LEN) - 1) << GLB_REG_GPIO_15_O_POS))
+ (~(((1 << GLB_REG_GPIO_15_O_LEN) - 1) << GLB_REG_GPIO_15_O_POS))
#define GLB_REG_GPIO_16_O GLB_REG_GPIO_16_O
-#define GLB_REG_GPIO_16_O_POS (16U)
-#define GLB_REG_GPIO_16_O_LEN (1U)
+#define GLB_REG_GPIO_16_O_POS (16)
+#define GLB_REG_GPIO_16_O_LEN (1)
#define GLB_REG_GPIO_16_O_MSK \
- (((1U << GLB_REG_GPIO_16_O_LEN) - 1) << GLB_REG_GPIO_16_O_POS)
+ (((1 << GLB_REG_GPIO_16_O_LEN) - 1) << GLB_REG_GPIO_16_O_POS)
#define GLB_REG_GPIO_16_O_UMSK \
- (~(((1U << GLB_REG_GPIO_16_O_LEN) - 1) << GLB_REG_GPIO_16_O_POS))
+ (~(((1 << GLB_REG_GPIO_16_O_LEN) - 1) << GLB_REG_GPIO_16_O_POS))
#define GLB_REG_GPIO_17_O GLB_REG_GPIO_17_O
-#define GLB_REG_GPIO_17_O_POS (17U)
-#define GLB_REG_GPIO_17_O_LEN (1U)
+#define GLB_REG_GPIO_17_O_POS (17)
+#define GLB_REG_GPIO_17_O_LEN (1)
#define GLB_REG_GPIO_17_O_MSK \
- (((1U << GLB_REG_GPIO_17_O_LEN) - 1) << GLB_REG_GPIO_17_O_POS)
+ (((1 << GLB_REG_GPIO_17_O_LEN) - 1) << GLB_REG_GPIO_17_O_POS)
#define GLB_REG_GPIO_17_O_UMSK \
- (~(((1U << GLB_REG_GPIO_17_O_LEN) - 1) << GLB_REG_GPIO_17_O_POS))
+ (~(((1 << GLB_REG_GPIO_17_O_LEN) - 1) << GLB_REG_GPIO_17_O_POS))
#define GLB_REG_GPIO_18_O GLB_REG_GPIO_18_O
-#define GLB_REG_GPIO_18_O_POS (18U)
-#define GLB_REG_GPIO_18_O_LEN (1U)
+#define GLB_REG_GPIO_18_O_POS (18)
+#define GLB_REG_GPIO_18_O_LEN (1)
#define GLB_REG_GPIO_18_O_MSK \
- (((1U << GLB_REG_GPIO_18_O_LEN) - 1) << GLB_REG_GPIO_18_O_POS)
+ (((1 << GLB_REG_GPIO_18_O_LEN) - 1) << GLB_REG_GPIO_18_O_POS)
#define GLB_REG_GPIO_18_O_UMSK \
- (~(((1U << GLB_REG_GPIO_18_O_LEN) - 1) << GLB_REG_GPIO_18_O_POS))
+ (~(((1 << GLB_REG_GPIO_18_O_LEN) - 1) << GLB_REG_GPIO_18_O_POS))
#define GLB_REG_GPIO_19_O GLB_REG_GPIO_19_O
-#define GLB_REG_GPIO_19_O_POS (19U)
-#define GLB_REG_GPIO_19_O_LEN (1U)
+#define GLB_REG_GPIO_19_O_POS (19)
+#define GLB_REG_GPIO_19_O_LEN (1)
#define GLB_REG_GPIO_19_O_MSK \
- (((1U << GLB_REG_GPIO_19_O_LEN) - 1) << GLB_REG_GPIO_19_O_POS)
+ (((1 << GLB_REG_GPIO_19_O_LEN) - 1) << GLB_REG_GPIO_19_O_POS)
#define GLB_REG_GPIO_19_O_UMSK \
- (~(((1U << GLB_REG_GPIO_19_O_LEN) - 1) << GLB_REG_GPIO_19_O_POS))
+ (~(((1 << GLB_REG_GPIO_19_O_LEN) - 1) << GLB_REG_GPIO_19_O_POS))
#define GLB_REG_GPIO_20_O GLB_REG_GPIO_20_O
-#define GLB_REG_GPIO_20_O_POS (20U)
-#define GLB_REG_GPIO_20_O_LEN (1U)
+#define GLB_REG_GPIO_20_O_POS (20)
+#define GLB_REG_GPIO_20_O_LEN (1)
#define GLB_REG_GPIO_20_O_MSK \
- (((1U << GLB_REG_GPIO_20_O_LEN) - 1) << GLB_REG_GPIO_20_O_POS)
+ (((1 << GLB_REG_GPIO_20_O_LEN) - 1) << GLB_REG_GPIO_20_O_POS)
#define GLB_REG_GPIO_20_O_UMSK \
- (~(((1U << GLB_REG_GPIO_20_O_LEN) - 1) << GLB_REG_GPIO_20_O_POS))
+ (~(((1 << GLB_REG_GPIO_20_O_LEN) - 1) << GLB_REG_GPIO_20_O_POS))
#define GLB_REG_GPIO_21_O GLB_REG_GPIO_21_O
-#define GLB_REG_GPIO_21_O_POS (21U)
-#define GLB_REG_GPIO_21_O_LEN (1U)
+#define GLB_REG_GPIO_21_O_POS (21)
+#define GLB_REG_GPIO_21_O_LEN (1)
#define GLB_REG_GPIO_21_O_MSK \
- (((1U << GLB_REG_GPIO_21_O_LEN) - 1) << GLB_REG_GPIO_21_O_POS)
+ (((1 << GLB_REG_GPIO_21_O_LEN) - 1) << GLB_REG_GPIO_21_O_POS)
#define GLB_REG_GPIO_21_O_UMSK \
- (~(((1U << GLB_REG_GPIO_21_O_LEN) - 1) << GLB_REG_GPIO_21_O_POS))
+ (~(((1 << GLB_REG_GPIO_21_O_LEN) - 1) << GLB_REG_GPIO_21_O_POS))
#define GLB_REG_GPIO_22_O GLB_REG_GPIO_22_O
-#define GLB_REG_GPIO_22_O_POS (22U)
-#define GLB_REG_GPIO_22_O_LEN (1U)
+#define GLB_REG_GPIO_22_O_POS (22)
+#define GLB_REG_GPIO_22_O_LEN (1)
#define GLB_REG_GPIO_22_O_MSK \
- (((1U << GLB_REG_GPIO_22_O_LEN) - 1) << GLB_REG_GPIO_22_O_POS)
+ (((1 << GLB_REG_GPIO_22_O_LEN) - 1) << GLB_REG_GPIO_22_O_POS)
#define GLB_REG_GPIO_22_O_UMSK \
- (~(((1U << GLB_REG_GPIO_22_O_LEN) - 1) << GLB_REG_GPIO_22_O_POS))
+ (~(((1 << GLB_REG_GPIO_22_O_LEN) - 1) << GLB_REG_GPIO_22_O_POS))
/* 0x18C : GPIO_CFGCTL33 */
@@ -2883,166 +2874,166 @@
#define GLB_GPIO_CFGCTL34_OFFSET (0x190)
#define GLB_REG_GPIO_0_OE GLB_REG_GPIO_0_OE
-#define GLB_REG_GPIO_0_OE_POS (0U)
-#define GLB_REG_GPIO_0_OE_LEN (1U)
+#define GLB_REG_GPIO_0_OE_POS (0)
+#define GLB_REG_GPIO_0_OE_LEN (1)
#define GLB_REG_GPIO_0_OE_MSK \
- (((1U << GLB_REG_GPIO_0_OE_LEN) - 1) << GLB_REG_GPIO_0_OE_POS)
+ (((1 << GLB_REG_GPIO_0_OE_LEN) - 1) << GLB_REG_GPIO_0_OE_POS)
#define GLB_REG_GPIO_0_OE_UMSK \
- (~(((1U << GLB_REG_GPIO_0_OE_LEN) - 1) << GLB_REG_GPIO_0_OE_POS))
+ (~(((1 << GLB_REG_GPIO_0_OE_LEN) - 1) << GLB_REG_GPIO_0_OE_POS))
#define GLB_REG_GPIO_1_OE GLB_REG_GPIO_1_OE
-#define GLB_REG_GPIO_1_OE_POS (1U)
-#define GLB_REG_GPIO_1_OE_LEN (1U)
+#define GLB_REG_GPIO_1_OE_POS (1)
+#define GLB_REG_GPIO_1_OE_LEN (1)
#define GLB_REG_GPIO_1_OE_MSK \
- (((1U << GLB_REG_GPIO_1_OE_LEN) - 1) << GLB_REG_GPIO_1_OE_POS)
+ (((1 << GLB_REG_GPIO_1_OE_LEN) - 1) << GLB_REG_GPIO_1_OE_POS)
#define GLB_REG_GPIO_1_OE_UMSK \
- (~(((1U << GLB_REG_GPIO_1_OE_LEN) - 1) << GLB_REG_GPIO_1_OE_POS))
+ (~(((1 << GLB_REG_GPIO_1_OE_LEN) - 1) << GLB_REG_GPIO_1_OE_POS))
#define GLB_REG_GPIO_2_OE GLB_REG_GPIO_2_OE
-#define GLB_REG_GPIO_2_OE_POS (2U)
-#define GLB_REG_GPIO_2_OE_LEN (1U)
+#define GLB_REG_GPIO_2_OE_POS (2)
+#define GLB_REG_GPIO_2_OE_LEN (1)
#define GLB_REG_GPIO_2_OE_MSK \
- (((1U << GLB_REG_GPIO_2_OE_LEN) - 1) << GLB_REG_GPIO_2_OE_POS)
+ (((1 << GLB_REG_GPIO_2_OE_LEN) - 1) << GLB_REG_GPIO_2_OE_POS)
#define GLB_REG_GPIO_2_OE_UMSK \
- (~(((1U << GLB_REG_GPIO_2_OE_LEN) - 1) << GLB_REG_GPIO_2_OE_POS))
+ (~(((1 << GLB_REG_GPIO_2_OE_LEN) - 1) << GLB_REG_GPIO_2_OE_POS))
#define GLB_REG_GPIO_3_OE GLB_REG_GPIO_3_OE
-#define GLB_REG_GPIO_3_OE_POS (3U)
-#define GLB_REG_GPIO_3_OE_LEN (1U)
+#define GLB_REG_GPIO_3_OE_POS (3)
+#define GLB_REG_GPIO_3_OE_LEN (1)
#define GLB_REG_GPIO_3_OE_MSK \
- (((1U << GLB_REG_GPIO_3_OE_LEN) - 1) << GLB_REG_GPIO_3_OE_POS)
+ (((1 << GLB_REG_GPIO_3_OE_LEN) - 1) << GLB_REG_GPIO_3_OE_POS)
#define GLB_REG_GPIO_3_OE_UMSK \
- (~(((1U << GLB_REG_GPIO_3_OE_LEN) - 1) << GLB_REG_GPIO_3_OE_POS))
+ (~(((1 << GLB_REG_GPIO_3_OE_LEN) - 1) << GLB_REG_GPIO_3_OE_POS))
#define GLB_REG_GPIO_4_OE GLB_REG_GPIO_4_OE
-#define GLB_REG_GPIO_4_OE_POS (4U)
-#define GLB_REG_GPIO_4_OE_LEN (1U)
+#define GLB_REG_GPIO_4_OE_POS (4)
+#define GLB_REG_GPIO_4_OE_LEN (1)
#define GLB_REG_GPIO_4_OE_MSK \
- (((1U << GLB_REG_GPIO_4_OE_LEN) - 1) << GLB_REG_GPIO_4_OE_POS)
+ (((1 << GLB_REG_GPIO_4_OE_LEN) - 1) << GLB_REG_GPIO_4_OE_POS)
#define GLB_REG_GPIO_4_OE_UMSK \
- (~(((1U << GLB_REG_GPIO_4_OE_LEN) - 1) << GLB_REG_GPIO_4_OE_POS))
+ (~(((1 << GLB_REG_GPIO_4_OE_LEN) - 1) << GLB_REG_GPIO_4_OE_POS))
#define GLB_REG_GPIO_5_OE GLB_REG_GPIO_5_OE
-#define GLB_REG_GPIO_5_OE_POS (5U)
-#define GLB_REG_GPIO_5_OE_LEN (1U)
+#define GLB_REG_GPIO_5_OE_POS (5)
+#define GLB_REG_GPIO_5_OE_LEN (1)
#define GLB_REG_GPIO_5_OE_MSK \
- (((1U << GLB_REG_GPIO_5_OE_LEN) - 1) << GLB_REG_GPIO_5_OE_POS)
+ (((1 << GLB_REG_GPIO_5_OE_LEN) - 1) << GLB_REG_GPIO_5_OE_POS)
#define GLB_REG_GPIO_5_OE_UMSK \
- (~(((1U << GLB_REG_GPIO_5_OE_LEN) - 1) << GLB_REG_GPIO_5_OE_POS))
+ (~(((1 << GLB_REG_GPIO_5_OE_LEN) - 1) << GLB_REG_GPIO_5_OE_POS))
#define GLB_REG_GPIO_6_OE GLB_REG_GPIO_6_OE
-#define GLB_REG_GPIO_6_OE_POS (6U)
-#define GLB_REG_GPIO_6_OE_LEN (1U)
+#define GLB_REG_GPIO_6_OE_POS (6)
+#define GLB_REG_GPIO_6_OE_LEN (1)
#define GLB_REG_GPIO_6_OE_MSK \
- (((1U << GLB_REG_GPIO_6_OE_LEN) - 1) << GLB_REG_GPIO_6_OE_POS)
+ (((1 << GLB_REG_GPIO_6_OE_LEN) - 1) << GLB_REG_GPIO_6_OE_POS)
#define GLB_REG_GPIO_6_OE_UMSK \
- (~(((1U << GLB_REG_GPIO_6_OE_LEN) - 1) << GLB_REG_GPIO_6_OE_POS))
+ (~(((1 << GLB_REG_GPIO_6_OE_LEN) - 1) << GLB_REG_GPIO_6_OE_POS))
#define GLB_REG_GPIO_7_OE GLB_REG_GPIO_7_OE
-#define GLB_REG_GPIO_7_OE_POS (7U)
-#define GLB_REG_GPIO_7_OE_LEN (1U)
+#define GLB_REG_GPIO_7_OE_POS (7)
+#define GLB_REG_GPIO_7_OE_LEN (1)
#define GLB_REG_GPIO_7_OE_MSK \
- (((1U << GLB_REG_GPIO_7_OE_LEN) - 1) << GLB_REG_GPIO_7_OE_POS)
+ (((1 << GLB_REG_GPIO_7_OE_LEN) - 1) << GLB_REG_GPIO_7_OE_POS)
#define GLB_REG_GPIO_7_OE_UMSK \
- (~(((1U << GLB_REG_GPIO_7_OE_LEN) - 1) << GLB_REG_GPIO_7_OE_POS))
+ (~(((1 << GLB_REG_GPIO_7_OE_LEN) - 1) << GLB_REG_GPIO_7_OE_POS))
#define GLB_REG_GPIO_8_OE GLB_REG_GPIO_8_OE
-#define GLB_REG_GPIO_8_OE_POS (8U)
-#define GLB_REG_GPIO_8_OE_LEN (1U)
+#define GLB_REG_GPIO_8_OE_POS (8)
+#define GLB_REG_GPIO_8_OE_LEN (1)
#define GLB_REG_GPIO_8_OE_MSK \
- (((1U << GLB_REG_GPIO_8_OE_LEN) - 1) << GLB_REG_GPIO_8_OE_POS)
+ (((1 << GLB_REG_GPIO_8_OE_LEN) - 1) << GLB_REG_GPIO_8_OE_POS)
#define GLB_REG_GPIO_8_OE_UMSK \
- (~(((1U << GLB_REG_GPIO_8_OE_LEN) - 1) << GLB_REG_GPIO_8_OE_POS))
+ (~(((1 << GLB_REG_GPIO_8_OE_LEN) - 1) << GLB_REG_GPIO_8_OE_POS))
#define GLB_REG_GPIO_9_OE GLB_REG_GPIO_9_OE
-#define GLB_REG_GPIO_9_OE_POS (9U)
-#define GLB_REG_GPIO_9_OE_LEN (1U)
+#define GLB_REG_GPIO_9_OE_POS (9)
+#define GLB_REG_GPIO_9_OE_LEN (1)
#define GLB_REG_GPIO_9_OE_MSK \
- (((1U << GLB_REG_GPIO_9_OE_LEN) - 1) << GLB_REG_GPIO_9_OE_POS)
+ (((1 << GLB_REG_GPIO_9_OE_LEN) - 1) << GLB_REG_GPIO_9_OE_POS)
#define GLB_REG_GPIO_9_OE_UMSK \
- (~(((1U << GLB_REG_GPIO_9_OE_LEN) - 1) << GLB_REG_GPIO_9_OE_POS))
+ (~(((1 << GLB_REG_GPIO_9_OE_LEN) - 1) << GLB_REG_GPIO_9_OE_POS))
#define GLB_REG_GPIO_10_OE GLB_REG_GPIO_10_OE
-#define GLB_REG_GPIO_10_OE_POS (10U)
-#define GLB_REG_GPIO_10_OE_LEN (1U)
+#define GLB_REG_GPIO_10_OE_POS (10)
+#define GLB_REG_GPIO_10_OE_LEN (1)
#define GLB_REG_GPIO_10_OE_MSK \
- (((1U << GLB_REG_GPIO_10_OE_LEN) - 1) << GLB_REG_GPIO_10_OE_POS)
+ (((1 << GLB_REG_GPIO_10_OE_LEN) - 1) << GLB_REG_GPIO_10_OE_POS)
#define GLB_REG_GPIO_10_OE_UMSK \
- (~(((1U << GLB_REG_GPIO_10_OE_LEN) - 1) << GLB_REG_GPIO_10_OE_POS))
+ (~(((1 << GLB_REG_GPIO_10_OE_LEN) - 1) << GLB_REG_GPIO_10_OE_POS))
#define GLB_REG_GPIO_11_OE GLB_REG_GPIO_11_OE
-#define GLB_REG_GPIO_11_OE_POS (11U)
-#define GLB_REG_GPIO_11_OE_LEN (1U)
+#define GLB_REG_GPIO_11_OE_POS (11)
+#define GLB_REG_GPIO_11_OE_LEN (1)
#define GLB_REG_GPIO_11_OE_MSK \
- (((1U << GLB_REG_GPIO_11_OE_LEN) - 1) << GLB_REG_GPIO_11_OE_POS)
+ (((1 << GLB_REG_GPIO_11_OE_LEN) - 1) << GLB_REG_GPIO_11_OE_POS)
#define GLB_REG_GPIO_11_OE_UMSK \
- (~(((1U << GLB_REG_GPIO_11_OE_LEN) - 1) << GLB_REG_GPIO_11_OE_POS))
+ (~(((1 << GLB_REG_GPIO_11_OE_LEN) - 1) << GLB_REG_GPIO_11_OE_POS))
#define GLB_REG_GPIO_12_OE GLB_REG_GPIO_12_OE
-#define GLB_REG_GPIO_12_OE_POS (12U)
-#define GLB_REG_GPIO_12_OE_LEN (1U)
+#define GLB_REG_GPIO_12_OE_POS (12)
+#define GLB_REG_GPIO_12_OE_LEN (1)
#define GLB_REG_GPIO_12_OE_MSK \
- (((1U << GLB_REG_GPIO_12_OE_LEN) - 1) << GLB_REG_GPIO_12_OE_POS)
+ (((1 << GLB_REG_GPIO_12_OE_LEN) - 1) << GLB_REG_GPIO_12_OE_POS)
#define GLB_REG_GPIO_12_OE_UMSK \
- (~(((1U << GLB_REG_GPIO_12_OE_LEN) - 1) << GLB_REG_GPIO_12_OE_POS))
+ (~(((1 << GLB_REG_GPIO_12_OE_LEN) - 1) << GLB_REG_GPIO_12_OE_POS))
#define GLB_REG_GPIO_13_OE GLB_REG_GPIO_13_OE
-#define GLB_REG_GPIO_13_OE_POS (13U)
-#define GLB_REG_GPIO_13_OE_LEN (1U)
+#define GLB_REG_GPIO_13_OE_POS (13)
+#define GLB_REG_GPIO_13_OE_LEN (1)
#define GLB_REG_GPIO_13_OE_MSK \
- (((1U << GLB_REG_GPIO_13_OE_LEN) - 1) << GLB_REG_GPIO_13_OE_POS)
+ (((1 << GLB_REG_GPIO_13_OE_LEN) - 1) << GLB_REG_GPIO_13_OE_POS)
#define GLB_REG_GPIO_13_OE_UMSK \
- (~(((1U << GLB_REG_GPIO_13_OE_LEN) - 1) << GLB_REG_GPIO_13_OE_POS))
+ (~(((1 << GLB_REG_GPIO_13_OE_LEN) - 1) << GLB_REG_GPIO_13_OE_POS))
#define GLB_REG_GPIO_14_OE GLB_REG_GPIO_14_OE
-#define GLB_REG_GPIO_14_OE_POS (14U)
-#define GLB_REG_GPIO_14_OE_LEN (1U)
+#define GLB_REG_GPIO_14_OE_POS (14)
+#define GLB_REG_GPIO_14_OE_LEN (1)
#define GLB_REG_GPIO_14_OE_MSK \
- (((1U << GLB_REG_GPIO_14_OE_LEN) - 1) << GLB_REG_GPIO_14_OE_POS)
+ (((1 << GLB_REG_GPIO_14_OE_LEN) - 1) << GLB_REG_GPIO_14_OE_POS)
#define GLB_REG_GPIO_14_OE_UMSK \
- (~(((1U << GLB_REG_GPIO_14_OE_LEN) - 1) << GLB_REG_GPIO_14_OE_POS))
+ (~(((1 << GLB_REG_GPIO_14_OE_LEN) - 1) << GLB_REG_GPIO_14_OE_POS))
#define GLB_REG_GPIO_15_OE GLB_REG_GPIO_15_OE
-#define GLB_REG_GPIO_15_OE_POS (15U)
-#define GLB_REG_GPIO_15_OE_LEN (1U)
+#define GLB_REG_GPIO_15_OE_POS (15)
+#define GLB_REG_GPIO_15_OE_LEN (1)
#define GLB_REG_GPIO_15_OE_MSK \
- (((1U << GLB_REG_GPIO_15_OE_LEN) - 1) << GLB_REG_GPIO_15_OE_POS)
+ (((1 << GLB_REG_GPIO_15_OE_LEN) - 1) << GLB_REG_GPIO_15_OE_POS)
#define GLB_REG_GPIO_15_OE_UMSK \
- (~(((1U << GLB_REG_GPIO_15_OE_LEN) - 1) << GLB_REG_GPIO_15_OE_POS))
+ (~(((1 << GLB_REG_GPIO_15_OE_LEN) - 1) << GLB_REG_GPIO_15_OE_POS))
#define GLB_REG_GPIO_16_OE GLB_REG_GPIO_16_OE
-#define GLB_REG_GPIO_16_OE_POS (16U)
-#define GLB_REG_GPIO_16_OE_LEN (1U)
+#define GLB_REG_GPIO_16_OE_POS (16)
+#define GLB_REG_GPIO_16_OE_LEN (1)
#define GLB_REG_GPIO_16_OE_MSK \
- (((1U << GLB_REG_GPIO_16_OE_LEN) - 1) << GLB_REG_GPIO_16_OE_POS)
+ (((1 << GLB_REG_GPIO_16_OE_LEN) - 1) << GLB_REG_GPIO_16_OE_POS)
#define GLB_REG_GPIO_16_OE_UMSK \
- (~(((1U << GLB_REG_GPIO_16_OE_LEN) - 1) << GLB_REG_GPIO_16_OE_POS))
+ (~(((1 << GLB_REG_GPIO_16_OE_LEN) - 1) << GLB_REG_GPIO_16_OE_POS))
#define GLB_REG_GPIO_17_OE GLB_REG_GPIO_17_OE
-#define GLB_REG_GPIO_17_OE_POS (17U)
-#define GLB_REG_GPIO_17_OE_LEN (1U)
+#define GLB_REG_GPIO_17_OE_POS (17)
+#define GLB_REG_GPIO_17_OE_LEN (1)
#define GLB_REG_GPIO_17_OE_MSK \
- (((1U << GLB_REG_GPIO_17_OE_LEN) - 1) << GLB_REG_GPIO_17_OE_POS)
+ (((1 << GLB_REG_GPIO_17_OE_LEN) - 1) << GLB_REG_GPIO_17_OE_POS)
#define GLB_REG_GPIO_17_OE_UMSK \
- (~(((1U << GLB_REG_GPIO_17_OE_LEN) - 1) << GLB_REG_GPIO_17_OE_POS))
+ (~(((1 << GLB_REG_GPIO_17_OE_LEN) - 1) << GLB_REG_GPIO_17_OE_POS))
#define GLB_REG_GPIO_18_OE GLB_REG_GPIO_18_OE
-#define GLB_REG_GPIO_18_OE_POS (18U)
-#define GLB_REG_GPIO_18_OE_LEN (1U)
+#define GLB_REG_GPIO_18_OE_POS (18)
+#define GLB_REG_GPIO_18_OE_LEN (1)
#define GLB_REG_GPIO_18_OE_MSK \
- (((1U << GLB_REG_GPIO_18_OE_LEN) - 1) << GLB_REG_GPIO_18_OE_POS)
+ (((1 << GLB_REG_GPIO_18_OE_LEN) - 1) << GLB_REG_GPIO_18_OE_POS)
#define GLB_REG_GPIO_18_OE_UMSK \
- (~(((1U << GLB_REG_GPIO_18_OE_LEN) - 1) << GLB_REG_GPIO_18_OE_POS))
+ (~(((1 << GLB_REG_GPIO_18_OE_LEN) - 1) << GLB_REG_GPIO_18_OE_POS))
#define GLB_REG_GPIO_19_OE GLB_REG_GPIO_19_OE
-#define GLB_REG_GPIO_19_OE_POS (19U)
-#define GLB_REG_GPIO_19_OE_LEN (1U)
+#define GLB_REG_GPIO_19_OE_POS (19)
+#define GLB_REG_GPIO_19_OE_LEN (1)
#define GLB_REG_GPIO_19_OE_MSK \
- (((1U << GLB_REG_GPIO_19_OE_LEN) - 1) << GLB_REG_GPIO_19_OE_POS)
+ (((1 << GLB_REG_GPIO_19_OE_LEN) - 1) << GLB_REG_GPIO_19_OE_POS)
#define GLB_REG_GPIO_19_OE_UMSK \
- (~(((1U << GLB_REG_GPIO_19_OE_LEN) - 1) << GLB_REG_GPIO_19_OE_POS))
+ (~(((1 << GLB_REG_GPIO_19_OE_LEN) - 1) << GLB_REG_GPIO_19_OE_POS))
#define GLB_REG_GPIO_20_OE GLB_REG_GPIO_20_OE
-#define GLB_REG_GPIO_20_OE_POS (20U)
-#define GLB_REG_GPIO_20_OE_LEN (1U)
+#define GLB_REG_GPIO_20_OE_POS (20)
+#define GLB_REG_GPIO_20_OE_LEN (1)
#define GLB_REG_GPIO_20_OE_MSK \
- (((1U << GLB_REG_GPIO_20_OE_LEN) - 1) << GLB_REG_GPIO_20_OE_POS)
+ (((1 << GLB_REG_GPIO_20_OE_LEN) - 1) << GLB_REG_GPIO_20_OE_POS)
#define GLB_REG_GPIO_20_OE_UMSK \
- (~(((1U << GLB_REG_GPIO_20_OE_LEN) - 1) << GLB_REG_GPIO_20_OE_POS))
+ (~(((1 << GLB_REG_GPIO_20_OE_LEN) - 1) << GLB_REG_GPIO_20_OE_POS))
#define GLB_REG_GPIO_21_OE GLB_REG_GPIO_21_OE
-#define GLB_REG_GPIO_21_OE_POS (21U)
-#define GLB_REG_GPIO_21_OE_LEN (1U)
+#define GLB_REG_GPIO_21_OE_POS (21)
+#define GLB_REG_GPIO_21_OE_LEN (1)
#define GLB_REG_GPIO_21_OE_MSK \
- (((1U << GLB_REG_GPIO_21_OE_LEN) - 1) << GLB_REG_GPIO_21_OE_POS)
+ (((1 << GLB_REG_GPIO_21_OE_LEN) - 1) << GLB_REG_GPIO_21_OE_POS)
#define GLB_REG_GPIO_21_OE_UMSK \
- (~(((1U << GLB_REG_GPIO_21_OE_LEN) - 1) << GLB_REG_GPIO_21_OE_POS))
+ (~(((1 << GLB_REG_GPIO_21_OE_LEN) - 1) << GLB_REG_GPIO_21_OE_POS))
#define GLB_REG_GPIO_22_OE GLB_REG_GPIO_22_OE
-#define GLB_REG_GPIO_22_OE_POS (22U)
-#define GLB_REG_GPIO_22_OE_LEN (1U)
+#define GLB_REG_GPIO_22_OE_POS (22)
+#define GLB_REG_GPIO_22_OE_LEN (1)
#define GLB_REG_GPIO_22_OE_MSK \
- (((1U << GLB_REG_GPIO_22_OE_LEN) - 1) << GLB_REG_GPIO_22_OE_POS)
+ (((1 << GLB_REG_GPIO_22_OE_LEN) - 1) << GLB_REG_GPIO_22_OE_POS)
#define GLB_REG_GPIO_22_OE_UMSK \
- (~(((1U << GLB_REG_GPIO_22_OE_LEN) - 1) << GLB_REG_GPIO_22_OE_POS))
+ (~(((1 << GLB_REG_GPIO_22_OE_LEN) - 1) << GLB_REG_GPIO_22_OE_POS))
/* 0x194 : GPIO_CFGCTL35 */
@@ -3052,891 +3043,881 @@
#define GLB_GPIO_INT_MASK1_OFFSET (0x1A0)
#define GLB_REG_GPIO_INT_MASK1 GLB_REG_GPIO_INT_MASK1
-#define GLB_REG_GPIO_INT_MASK1_POS (0U)
-#define GLB_REG_GPIO_INT_MASK1_LEN (32U)
+#define GLB_REG_GPIO_INT_MASK1_POS (0)
+#define GLB_REG_GPIO_INT_MASK1_LEN (32)
#define GLB_REG_GPIO_INT_MASK1_MSK \
- (((1U << GLB_REG_GPIO_INT_MASK1_LEN) - 1) << GLB_REG_GPIO_INT_MASK1_POS)
+ (((1 << GLB_REG_GPIO_INT_MASK1_LEN) - 1) << GLB_REG_GPIO_INT_MASK1_POS)
#define GLB_REG_GPIO_INT_MASK1_UMSK \
- (~(((1U << GLB_REG_GPIO_INT_MASK1_LEN) - 1) << GLB_REG_GPIO_INT_MASK1_POS))
+ (~(((1 << GLB_REG_GPIO_INT_MASK1_LEN) - 1) << GLB_REG_GPIO_INT_MASK1_POS))
/* 0x1A8 : GPIO_INT_STAT1 */
#define GLB_GPIO_INT_STAT1_OFFSET (0x1A8)
#define GLB_GPIO_INT_STAT1 GLB_GPIO_INT_STAT1
-#define GLB_GPIO_INT_STAT1_POS (0U)
-#define GLB_GPIO_INT_STAT1_LEN (32U)
+#define GLB_GPIO_INT_STAT1_POS (0)
+#define GLB_GPIO_INT_STAT1_LEN (32)
#define GLB_GPIO_INT_STAT1_MSK \
- (((1U << GLB_GPIO_INT_STAT1_LEN) - 1) << GLB_GPIO_INT_STAT1_POS)
+ (((1 << GLB_GPIO_INT_STAT1_LEN) - 1) << GLB_GPIO_INT_STAT1_POS)
#define GLB_GPIO_INT_STAT1_UMSK \
- (~(((1U << GLB_GPIO_INT_STAT1_LEN) - 1) << GLB_GPIO_INT_STAT1_POS))
+ (~(((1 << GLB_GPIO_INT_STAT1_LEN) - 1) << GLB_GPIO_INT_STAT1_POS))
/* 0x1B0 : GPIO_INT_CLR1 */
#define GLB_GPIO_INT_CLR1_OFFSET (0x1B0)
#define GLB_REG_GPIO_INT_CLR1 GLB_REG_GPIO_INT_CLR1
-#define GLB_REG_GPIO_INT_CLR1_POS (0U)
-#define GLB_REG_GPIO_INT_CLR1_LEN (32U)
+#define GLB_REG_GPIO_INT_CLR1_POS (0)
+#define GLB_REG_GPIO_INT_CLR1_LEN (32)
#define GLB_REG_GPIO_INT_CLR1_MSK \
- (((1U << GLB_REG_GPIO_INT_CLR1_LEN) - 1) << GLB_REG_GPIO_INT_CLR1_POS)
+ (((1 << GLB_REG_GPIO_INT_CLR1_LEN) - 1) << GLB_REG_GPIO_INT_CLR1_POS)
#define GLB_REG_GPIO_INT_CLR1_UMSK \
- (~(((1U << GLB_REG_GPIO_INT_CLR1_LEN) - 1) << GLB_REG_GPIO_INT_CLR1_POS))
+ (~(((1 << GLB_REG_GPIO_INT_CLR1_LEN) - 1) << GLB_REG_GPIO_INT_CLR1_POS))
/* 0x1C0 : GPIO_INT_MODE_SET1 */
#define GLB_GPIO_INT_MODE_SET1_OFFSET (0x1C0)
#define GLB_REG_GPIO_INT_MODE_SET1 GLB_REG_GPIO_INT_MODE_SET1
-#define GLB_REG_GPIO_INT_MODE_SET1_POS (0U)
-#define GLB_REG_GPIO_INT_MODE_SET1_LEN (32U)
+#define GLB_REG_GPIO_INT_MODE_SET1_POS (0)
+#define GLB_REG_GPIO_INT_MODE_SET1_LEN (32)
#define GLB_REG_GPIO_INT_MODE_SET1_MSK \
- (((1U << GLB_REG_GPIO_INT_MODE_SET1_LEN) - 1) \
+ (((1 << GLB_REG_GPIO_INT_MODE_SET1_LEN) - 1) \
<< GLB_REG_GPIO_INT_MODE_SET1_POS)
#define GLB_REG_GPIO_INT_MODE_SET1_UMSK \
- (~(((1U << GLB_REG_GPIO_INT_MODE_SET1_LEN) - 1) \
+ (~(((1 << GLB_REG_GPIO_INT_MODE_SET1_LEN) - 1) \
<< GLB_REG_GPIO_INT_MODE_SET1_POS))
/* 0x1C4 : GPIO_INT_MODE_SET2 */
#define GLB_GPIO_INT_MODE_SET2_OFFSET (0x1C4)
#define GLB_REG_GPIO_INT_MODE_SET2 GLB_REG_GPIO_INT_MODE_SET2
-#define GLB_REG_GPIO_INT_MODE_SET2_POS (0U)
-#define GLB_REG_GPIO_INT_MODE_SET2_LEN (32U)
+#define GLB_REG_GPIO_INT_MODE_SET2_POS (0)
+#define GLB_REG_GPIO_INT_MODE_SET2_LEN (32)
#define GLB_REG_GPIO_INT_MODE_SET2_MSK \
- (((1U << GLB_REG_GPIO_INT_MODE_SET2_LEN) - 1) \
+ (((1 << GLB_REG_GPIO_INT_MODE_SET2_LEN) - 1) \
<< GLB_REG_GPIO_INT_MODE_SET2_POS)
#define GLB_REG_GPIO_INT_MODE_SET2_UMSK \
- (~(((1U << GLB_REG_GPIO_INT_MODE_SET2_LEN) - 1) \
+ (~(((1 << GLB_REG_GPIO_INT_MODE_SET2_LEN) - 1) \
<< GLB_REG_GPIO_INT_MODE_SET2_POS))
/* 0x1C8 : GPIO_INT_MODE_SET3 */
#define GLB_GPIO_INT_MODE_SET3_OFFSET (0x1C8)
#define GLB_REG_GPIO_INT_MODE_SET3 GLB_REG_GPIO_INT_MODE_SET3
-#define GLB_REG_GPIO_INT_MODE_SET3_POS (0U)
-#define GLB_REG_GPIO_INT_MODE_SET3_LEN (32U)
+#define GLB_REG_GPIO_INT_MODE_SET3_POS (0)
+#define GLB_REG_GPIO_INT_MODE_SET3_LEN (32)
#define GLB_REG_GPIO_INT_MODE_SET3_MSK \
- (((1U << GLB_REG_GPIO_INT_MODE_SET3_LEN) - 1) \
+ (((1 << GLB_REG_GPIO_INT_MODE_SET3_LEN) - 1) \
<< GLB_REG_GPIO_INT_MODE_SET3_POS)
#define GLB_REG_GPIO_INT_MODE_SET3_UMSK \
- (~(((1U << GLB_REG_GPIO_INT_MODE_SET3_LEN) - 1) \
+ (~(((1 << GLB_REG_GPIO_INT_MODE_SET3_LEN) - 1) \
<< GLB_REG_GPIO_INT_MODE_SET3_POS))
/* 0x224 : led_driver */
#define GLB_LED_DRIVER_OFFSET (0x224)
#define GLB_LED_DIN_REG GLB_LED_DIN_REG
-#define GLB_LED_DIN_REG_POS (0U)
-#define GLB_LED_DIN_REG_LEN (1U)
+#define GLB_LED_DIN_REG_POS (0)
+#define GLB_LED_DIN_REG_LEN (1)
#define GLB_LED_DIN_REG_MSK \
- (((1U << GLB_LED_DIN_REG_LEN) - 1) << GLB_LED_DIN_REG_POS)
+ (((1 << GLB_LED_DIN_REG_LEN) - 1) << GLB_LED_DIN_REG_POS)
#define GLB_LED_DIN_REG_UMSK \
- (~(((1U << GLB_LED_DIN_REG_LEN) - 1) << GLB_LED_DIN_REG_POS))
+ (~(((1 << GLB_LED_DIN_REG_LEN) - 1) << GLB_LED_DIN_REG_POS))
#define GLB_LED_DIN_SEL GLB_LED_DIN_SEL
-#define GLB_LED_DIN_SEL_POS (1U)
-#define GLB_LED_DIN_SEL_LEN (1U)
+#define GLB_LED_DIN_SEL_POS (1)
+#define GLB_LED_DIN_SEL_LEN (1)
#define GLB_LED_DIN_SEL_MSK \
- (((1U << GLB_LED_DIN_SEL_LEN) - 1) << GLB_LED_DIN_SEL_POS)
+ (((1 << GLB_LED_DIN_SEL_LEN) - 1) << GLB_LED_DIN_SEL_POS)
#define GLB_LED_DIN_SEL_UMSK \
- (~(((1U << GLB_LED_DIN_SEL_LEN) - 1) << GLB_LED_DIN_SEL_POS))
+ (~(((1 << GLB_LED_DIN_SEL_LEN) - 1) << GLB_LED_DIN_SEL_POS))
#define GLB_LED_DIN_POLARITY_SEL GLB_LED_DIN_POLARITY_SEL
-#define GLB_LED_DIN_POLARITY_SEL_POS (2U)
-#define GLB_LED_DIN_POLARITY_SEL_LEN (1U)
+#define GLB_LED_DIN_POLARITY_SEL_POS (2)
+#define GLB_LED_DIN_POLARITY_SEL_LEN (1)
#define GLB_LED_DIN_POLARITY_SEL_MSK \
- (((1U << GLB_LED_DIN_POLARITY_SEL_LEN) - 1) << GLB_LED_DIN_POLARITY_SEL_POS)
+ (((1 << GLB_LED_DIN_POLARITY_SEL_LEN) - 1) << GLB_LED_DIN_POLARITY_SEL_POS)
#define GLB_LED_DIN_POLARITY_SEL_UMSK \
- (~(((1U << GLB_LED_DIN_POLARITY_SEL_LEN) - 1) \
+ (~(((1 << GLB_LED_DIN_POLARITY_SEL_LEN) - 1) \
<< GLB_LED_DIN_POLARITY_SEL_POS))
#define GLB_LEDDRV_IBIAS GLB_LEDDRV_IBIAS
-#define GLB_LEDDRV_IBIAS_POS (4U)
-#define GLB_LEDDRV_IBIAS_LEN (4U)
+#define GLB_LEDDRV_IBIAS_POS (4)
+#define GLB_LEDDRV_IBIAS_LEN (4)
#define GLB_LEDDRV_IBIAS_MSK \
- (((1U << GLB_LEDDRV_IBIAS_LEN) - 1) << GLB_LEDDRV_IBIAS_POS)
+ (((1 << GLB_LEDDRV_IBIAS_LEN) - 1) << GLB_LEDDRV_IBIAS_POS)
#define GLB_LEDDRV_IBIAS_UMSK \
- (~(((1U << GLB_LEDDRV_IBIAS_LEN) - 1) << GLB_LEDDRV_IBIAS_POS))
+ (~(((1 << GLB_LEDDRV_IBIAS_LEN) - 1) << GLB_LEDDRV_IBIAS_POS))
#define GLB_IR_RX_GPIO_SEL GLB_IR_RX_GPIO_SEL
-#define GLB_IR_RX_GPIO_SEL_POS (8U)
-#define GLB_IR_RX_GPIO_SEL_LEN (2U)
+#define GLB_IR_RX_GPIO_SEL_POS (8)
+#define GLB_IR_RX_GPIO_SEL_LEN (2)
#define GLB_IR_RX_GPIO_SEL_MSK \
- (((1U << GLB_IR_RX_GPIO_SEL_LEN) - 1) << GLB_IR_RX_GPIO_SEL_POS)
+ (((1 << GLB_IR_RX_GPIO_SEL_LEN) - 1) << GLB_IR_RX_GPIO_SEL_POS)
#define GLB_IR_RX_GPIO_SEL_UMSK \
- (~(((1U << GLB_IR_RX_GPIO_SEL_LEN) - 1) << GLB_IR_RX_GPIO_SEL_POS))
+ (~(((1 << GLB_IR_RX_GPIO_SEL_LEN) - 1) << GLB_IR_RX_GPIO_SEL_POS))
#define GLB_PU_LEDDRV GLB_PU_LEDDRV
-#define GLB_PU_LEDDRV_POS (31U)
-#define GLB_PU_LEDDRV_LEN (1U)
+#define GLB_PU_LEDDRV_POS (31)
+#define GLB_PU_LEDDRV_LEN (1)
#define GLB_PU_LEDDRV_MSK \
- (((1U << GLB_PU_LEDDRV_LEN) - 1) << GLB_PU_LEDDRV_POS)
+ (((1 << GLB_PU_LEDDRV_LEN) - 1) << GLB_PU_LEDDRV_POS)
#define GLB_PU_LEDDRV_UMSK \
- (~(((1U << GLB_PU_LEDDRV_LEN) - 1) << GLB_PU_LEDDRV_POS))
+ (~(((1 << GLB_PU_LEDDRV_LEN) - 1) << GLB_PU_LEDDRV_POS))
/* 0x308 : gpdac_ctrl */
#define GLB_GPDAC_CTRL_OFFSET (0x308)
#define GLB_GPDACA_RSTN_ANA GLB_GPDACA_RSTN_ANA
-#define GLB_GPDACA_RSTN_ANA_POS (0U)
-#define GLB_GPDACA_RSTN_ANA_LEN (1U)
+#define GLB_GPDACA_RSTN_ANA_POS (0)
+#define GLB_GPDACA_RSTN_ANA_LEN (1)
#define GLB_GPDACA_RSTN_ANA_MSK \
- (((1U << GLB_GPDACA_RSTN_ANA_LEN) - 1) << GLB_GPDACA_RSTN_ANA_POS)
+ (((1 << GLB_GPDACA_RSTN_ANA_LEN) - 1) << GLB_GPDACA_RSTN_ANA_POS)
#define GLB_GPDACA_RSTN_ANA_UMSK \
- (~(((1U << GLB_GPDACA_RSTN_ANA_LEN) - 1) << GLB_GPDACA_RSTN_ANA_POS))
+ (~(((1 << GLB_GPDACA_RSTN_ANA_LEN) - 1) << GLB_GPDACA_RSTN_ANA_POS))
#define GLB_GPDACB_RSTN_ANA GLB_GPDACB_RSTN_ANA
-#define GLB_GPDACB_RSTN_ANA_POS (1U)
-#define GLB_GPDACB_RSTN_ANA_LEN (1U)
+#define GLB_GPDACB_RSTN_ANA_POS (1)
+#define GLB_GPDACB_RSTN_ANA_LEN (1)
#define GLB_GPDACB_RSTN_ANA_MSK \
- (((1U << GLB_GPDACB_RSTN_ANA_LEN) - 1) << GLB_GPDACB_RSTN_ANA_POS)
+ (((1 << GLB_GPDACB_RSTN_ANA_LEN) - 1) << GLB_GPDACB_RSTN_ANA_POS)
#define GLB_GPDACB_RSTN_ANA_UMSK \
- (~(((1U << GLB_GPDACB_RSTN_ANA_LEN) - 1) << GLB_GPDACB_RSTN_ANA_POS))
+ (~(((1 << GLB_GPDACB_RSTN_ANA_LEN) - 1) << GLB_GPDACB_RSTN_ANA_POS))
#define GLB_GPDAC_TEST_EN GLB_GPDAC_TEST_EN
-#define GLB_GPDAC_TEST_EN_POS (7U)
-#define GLB_GPDAC_TEST_EN_LEN (1U)
+#define GLB_GPDAC_TEST_EN_POS (7)
+#define GLB_GPDAC_TEST_EN_LEN (1)
#define GLB_GPDAC_TEST_EN_MSK \
- (((1U << GLB_GPDAC_TEST_EN_LEN) - 1) << GLB_GPDAC_TEST_EN_POS)
+ (((1 << GLB_GPDAC_TEST_EN_LEN) - 1) << GLB_GPDAC_TEST_EN_POS)
#define GLB_GPDAC_TEST_EN_UMSK \
- (~(((1U << GLB_GPDAC_TEST_EN_LEN) - 1) << GLB_GPDAC_TEST_EN_POS))
+ (~(((1 << GLB_GPDAC_TEST_EN_LEN) - 1) << GLB_GPDAC_TEST_EN_POS))
#define GLB_GPDAC_REF_SEL GLB_GPDAC_REF_SEL
-#define GLB_GPDAC_REF_SEL_POS (8U)
-#define GLB_GPDAC_REF_SEL_LEN (1U)
+#define GLB_GPDAC_REF_SEL_POS (8)
+#define GLB_GPDAC_REF_SEL_LEN (1)
#define GLB_GPDAC_REF_SEL_MSK \
- (((1U << GLB_GPDAC_REF_SEL_LEN) - 1) << GLB_GPDAC_REF_SEL_POS)
+ (((1 << GLB_GPDAC_REF_SEL_LEN) - 1) << GLB_GPDAC_REF_SEL_POS)
#define GLB_GPDAC_REF_SEL_UMSK \
- (~(((1U << GLB_GPDAC_REF_SEL_LEN) - 1) << GLB_GPDAC_REF_SEL_POS))
+ (~(((1 << GLB_GPDAC_REF_SEL_LEN) - 1) << GLB_GPDAC_REF_SEL_POS))
#define GLB_GPDAC_TEST_SEL GLB_GPDAC_TEST_SEL
-#define GLB_GPDAC_TEST_SEL_POS (9U)
-#define GLB_GPDAC_TEST_SEL_LEN (3U)
+#define GLB_GPDAC_TEST_SEL_POS (9)
+#define GLB_GPDAC_TEST_SEL_LEN (3)
#define GLB_GPDAC_TEST_SEL_MSK \
- (((1U << GLB_GPDAC_TEST_SEL_LEN) - 1) << GLB_GPDAC_TEST_SEL_POS)
+ (((1 << GLB_GPDAC_TEST_SEL_LEN) - 1) << GLB_GPDAC_TEST_SEL_POS)
#define GLB_GPDAC_TEST_SEL_UMSK \
- (~(((1U << GLB_GPDAC_TEST_SEL_LEN) - 1) << GLB_GPDAC_TEST_SEL_POS))
+ (~(((1 << GLB_GPDAC_TEST_SEL_LEN) - 1) << GLB_GPDAC_TEST_SEL_POS))
#define GLB_GPDAC_RESERVED GLB_GPDAC_RESERVED
-#define GLB_GPDAC_RESERVED_POS (24U)
-#define GLB_GPDAC_RESERVED_LEN (8U)
+#define GLB_GPDAC_RESERVED_POS (24)
+#define GLB_GPDAC_RESERVED_LEN (8)
#define GLB_GPDAC_RESERVED_MSK \
- (((1U << GLB_GPDAC_RESERVED_LEN) - 1) << GLB_GPDAC_RESERVED_POS)
+ (((1 << GLB_GPDAC_RESERVED_LEN) - 1) << GLB_GPDAC_RESERVED_POS)
#define GLB_GPDAC_RESERVED_UMSK \
- (~(((1U << GLB_GPDAC_RESERVED_LEN) - 1) << GLB_GPDAC_RESERVED_POS))
+ (~(((1 << GLB_GPDAC_RESERVED_LEN) - 1) << GLB_GPDAC_RESERVED_POS))
/* 0x30C : gpdac_actrl */
#define GLB_GPDAC_ACTRL_OFFSET (0x30C)
#define GLB_GPDAC_A_EN GLB_GPDAC_A_EN
-#define GLB_GPDAC_A_EN_POS (0U)
-#define GLB_GPDAC_A_EN_LEN (1U)
+#define GLB_GPDAC_A_EN_POS (0)
+#define GLB_GPDAC_A_EN_LEN (1)
#define GLB_GPDAC_A_EN_MSK \
- (((1U << GLB_GPDAC_A_EN_LEN) - 1) << GLB_GPDAC_A_EN_POS)
+ (((1 << GLB_GPDAC_A_EN_LEN) - 1) << GLB_GPDAC_A_EN_POS)
#define GLB_GPDAC_A_EN_UMSK \
- (~(((1U << GLB_GPDAC_A_EN_LEN) - 1) << GLB_GPDAC_A_EN_POS))
+ (~(((1 << GLB_GPDAC_A_EN_LEN) - 1) << GLB_GPDAC_A_EN_POS))
#define GLB_GPDAC_IOA_EN GLB_GPDAC_IOA_EN
-#define GLB_GPDAC_IOA_EN_POS (1U)
-#define GLB_GPDAC_IOA_EN_LEN (1U)
+#define GLB_GPDAC_IOA_EN_POS (1)
+#define GLB_GPDAC_IOA_EN_LEN (1)
#define GLB_GPDAC_IOA_EN_MSK \
- (((1U << GLB_GPDAC_IOA_EN_LEN) - 1) << GLB_GPDAC_IOA_EN_POS)
+ (((1 << GLB_GPDAC_IOA_EN_LEN) - 1) << GLB_GPDAC_IOA_EN_POS)
#define GLB_GPDAC_IOA_EN_UMSK \
- (~(((1U << GLB_GPDAC_IOA_EN_LEN) - 1) << GLB_GPDAC_IOA_EN_POS))
+ (~(((1 << GLB_GPDAC_IOA_EN_LEN) - 1) << GLB_GPDAC_IOA_EN_POS))
#define GLB_GPDAC_A_RNG GLB_GPDAC_A_RNG
-#define GLB_GPDAC_A_RNG_POS (18U)
-#define GLB_GPDAC_A_RNG_LEN (2U)
+#define GLB_GPDAC_A_RNG_POS (18)
+#define GLB_GPDAC_A_RNG_LEN (2)
#define GLB_GPDAC_A_RNG_MSK \
- (((1U << GLB_GPDAC_A_RNG_LEN) - 1) << GLB_GPDAC_A_RNG_POS)
+ (((1 << GLB_GPDAC_A_RNG_LEN) - 1) << GLB_GPDAC_A_RNG_POS)
#define GLB_GPDAC_A_RNG_UMSK \
- (~(((1U << GLB_GPDAC_A_RNG_LEN) - 1) << GLB_GPDAC_A_RNG_POS))
+ (~(((1 << GLB_GPDAC_A_RNG_LEN) - 1) << GLB_GPDAC_A_RNG_POS))
#define GLB_GPDAC_A_OUTMUX GLB_GPDAC_A_OUTMUX
-#define GLB_GPDAC_A_OUTMUX_POS (20U)
-#define GLB_GPDAC_A_OUTMUX_LEN (3U)
+#define GLB_GPDAC_A_OUTMUX_POS (20)
+#define GLB_GPDAC_A_OUTMUX_LEN (3)
#define GLB_GPDAC_A_OUTMUX_MSK \
- (((1U << GLB_GPDAC_A_OUTMUX_LEN) - 1) << GLB_GPDAC_A_OUTMUX_POS)
+ (((1 << GLB_GPDAC_A_OUTMUX_LEN) - 1) << GLB_GPDAC_A_OUTMUX_POS)
#define GLB_GPDAC_A_OUTMUX_UMSK \
- (~(((1U << GLB_GPDAC_A_OUTMUX_LEN) - 1) << GLB_GPDAC_A_OUTMUX_POS))
+ (~(((1 << GLB_GPDAC_A_OUTMUX_LEN) - 1) << GLB_GPDAC_A_OUTMUX_POS))
/* 0x310 : gpdac_bctrl */
#define GLB_GPDAC_BCTRL_OFFSET (0x310)
#define GLB_GPDAC_B_EN GLB_GPDAC_B_EN
-#define GLB_GPDAC_B_EN_POS (0U)
-#define GLB_GPDAC_B_EN_LEN (1U)
+#define GLB_GPDAC_B_EN_POS (0)
+#define GLB_GPDAC_B_EN_LEN (1)
#define GLB_GPDAC_B_EN_MSK \
- (((1U << GLB_GPDAC_B_EN_LEN) - 1) << GLB_GPDAC_B_EN_POS)
+ (((1 << GLB_GPDAC_B_EN_LEN) - 1) << GLB_GPDAC_B_EN_POS)
#define GLB_GPDAC_B_EN_UMSK \
- (~(((1U << GLB_GPDAC_B_EN_LEN) - 1) << GLB_GPDAC_B_EN_POS))
+ (~(((1 << GLB_GPDAC_B_EN_LEN) - 1) << GLB_GPDAC_B_EN_POS))
#define GLB_GPDAC_IOB_EN GLB_GPDAC_IOB_EN
-#define GLB_GPDAC_IOB_EN_POS (1U)
-#define GLB_GPDAC_IOB_EN_LEN (1U)
+#define GLB_GPDAC_IOB_EN_POS (1)
+#define GLB_GPDAC_IOB_EN_LEN (1)
#define GLB_GPDAC_IOB_EN_MSK \
- (((1U << GLB_GPDAC_IOB_EN_LEN) - 1) << GLB_GPDAC_IOB_EN_POS)
+ (((1 << GLB_GPDAC_IOB_EN_LEN) - 1) << GLB_GPDAC_IOB_EN_POS)
#define GLB_GPDAC_IOB_EN_UMSK \
- (~(((1U << GLB_GPDAC_IOB_EN_LEN) - 1) << GLB_GPDAC_IOB_EN_POS))
+ (~(((1 << GLB_GPDAC_IOB_EN_LEN) - 1) << GLB_GPDAC_IOB_EN_POS))
#define GLB_GPDAC_B_RNG GLB_GPDAC_B_RNG
-#define GLB_GPDAC_B_RNG_POS (18U)
-#define GLB_GPDAC_B_RNG_LEN (2U)
+#define GLB_GPDAC_B_RNG_POS (18)
+#define GLB_GPDAC_B_RNG_LEN (2)
#define GLB_GPDAC_B_RNG_MSK \
- (((1U << GLB_GPDAC_B_RNG_LEN) - 1) << GLB_GPDAC_B_RNG_POS)
+ (((1 << GLB_GPDAC_B_RNG_LEN) - 1) << GLB_GPDAC_B_RNG_POS)
#define GLB_GPDAC_B_RNG_UMSK \
- (~(((1U << GLB_GPDAC_B_RNG_LEN) - 1) << GLB_GPDAC_B_RNG_POS))
+ (~(((1 << GLB_GPDAC_B_RNG_LEN) - 1) << GLB_GPDAC_B_RNG_POS))
#define GLB_GPDAC_B_OUTMUX GLB_GPDAC_B_OUTMUX
-#define GLB_GPDAC_B_OUTMUX_POS (20U)
-#define GLB_GPDAC_B_OUTMUX_LEN (3U)
+#define GLB_GPDAC_B_OUTMUX_POS (20)
+#define GLB_GPDAC_B_OUTMUX_LEN (3)
#define GLB_GPDAC_B_OUTMUX_MSK \
- (((1U << GLB_GPDAC_B_OUTMUX_LEN) - 1) << GLB_GPDAC_B_OUTMUX_POS)
+ (((1 << GLB_GPDAC_B_OUTMUX_LEN) - 1) << GLB_GPDAC_B_OUTMUX_POS)
#define GLB_GPDAC_B_OUTMUX_UMSK \
- (~(((1U << GLB_GPDAC_B_OUTMUX_LEN) - 1) << GLB_GPDAC_B_OUTMUX_POS))
+ (~(((1 << GLB_GPDAC_B_OUTMUX_LEN) - 1) << GLB_GPDAC_B_OUTMUX_POS))
/* 0x314 : gpdac_data */
#define GLB_GPDAC_DATA_OFFSET (0x314)
#define GLB_GPDAC_B_DATA GLB_GPDAC_B_DATA
-#define GLB_GPDAC_B_DATA_POS (0U)
-#define GLB_GPDAC_B_DATA_LEN (10U)
+#define GLB_GPDAC_B_DATA_POS (0)
+#define GLB_GPDAC_B_DATA_LEN (10)
#define GLB_GPDAC_B_DATA_MSK \
- (((1U << GLB_GPDAC_B_DATA_LEN) - 1) << GLB_GPDAC_B_DATA_POS)
+ (((1 << GLB_GPDAC_B_DATA_LEN) - 1) << GLB_GPDAC_B_DATA_POS)
#define GLB_GPDAC_B_DATA_UMSK \
- (~(((1U << GLB_GPDAC_B_DATA_LEN) - 1) << GLB_GPDAC_B_DATA_POS))
+ (~(((1 << GLB_GPDAC_B_DATA_LEN) - 1) << GLB_GPDAC_B_DATA_POS))
#define GLB_GPDAC_A_DATA GLB_GPDAC_A_DATA
-#define GLB_GPDAC_A_DATA_POS (16U)
-#define GLB_GPDAC_A_DATA_LEN (10U)
+#define GLB_GPDAC_A_DATA_POS (16)
+#define GLB_GPDAC_A_DATA_LEN (10)
#define GLB_GPDAC_A_DATA_MSK \
- (((1U << GLB_GPDAC_A_DATA_LEN) - 1) << GLB_GPDAC_A_DATA_POS)
+ (((1 << GLB_GPDAC_A_DATA_LEN) - 1) << GLB_GPDAC_A_DATA_POS)
#define GLB_GPDAC_A_DATA_UMSK \
- (~(((1U << GLB_GPDAC_A_DATA_LEN) - 1) << GLB_GPDAC_A_DATA_POS))
+ (~(((1 << GLB_GPDAC_A_DATA_LEN) - 1) << GLB_GPDAC_A_DATA_POS))
/* 0xF00 : tzc_glb_ctrl_0 */
#define GLB_TZC_GLB_CTRL_0_OFFSET (0xF00)
#define GLB_TZC_GLB_SWRST_S00_LOCK GLB_TZC_GLB_SWRST_S00_LOCK
-#define GLB_TZC_GLB_SWRST_S00_LOCK_POS (0U)
-#define GLB_TZC_GLB_SWRST_S00_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S00_LOCK_POS (0)
+#define GLB_TZC_GLB_SWRST_S00_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S00_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S00_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S00_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S00_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S00_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S00_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S00_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S00_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S01_LOCK GLB_TZC_GLB_SWRST_S01_LOCK
-#define GLB_TZC_GLB_SWRST_S01_LOCK_POS (1U)
-#define GLB_TZC_GLB_SWRST_S01_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S01_LOCK_POS (1)
+#define GLB_TZC_GLB_SWRST_S01_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S01_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S01_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S01_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S01_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S01_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S01_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S01_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S01_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S30_LOCK GLB_TZC_GLB_SWRST_S30_LOCK
-#define GLB_TZC_GLB_SWRST_S30_LOCK_POS (8U)
-#define GLB_TZC_GLB_SWRST_S30_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S30_LOCK_POS (8)
+#define GLB_TZC_GLB_SWRST_S30_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S30_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S30_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S30_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S30_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S30_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S30_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S30_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S30_LOCK_POS))
#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK GLB_TZC_GLB_CTRL_PWRON_RST_LOCK
-#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS (12U)
-#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN (1U)
+#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS (12)
+#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN (1)
#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_MSK \
- (((1U << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS)
#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS))
#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK GLB_TZC_GLB_CTRL_CPU_RESET_LOCK
-#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS (13U)
-#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN (1U)
+#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS (13)
+#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN (1)
#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_MSK \
- (((1U << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS)
#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS))
#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK GLB_TZC_GLB_CTRL_SYS_RESET_LOCK
-#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS (14U)
-#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN (1U)
+#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS (14)
+#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN (1)
#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_MSK \
- (((1U << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS)
#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS))
#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK
-#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS (15U)
-#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN (1U)
+#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS (15)
+#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN (1)
#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_MSK \
- (((1U << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS)
#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS))
#define GLB_TZC_GLB_MISC_LOCK GLB_TZC_GLB_MISC_LOCK
-#define GLB_TZC_GLB_MISC_LOCK_POS (25U)
-#define GLB_TZC_GLB_MISC_LOCK_LEN (1U)
+#define GLB_TZC_GLB_MISC_LOCK_POS (25)
+#define GLB_TZC_GLB_MISC_LOCK_LEN (1)
#define GLB_TZC_GLB_MISC_LOCK_MSK \
- (((1U << GLB_TZC_GLB_MISC_LOCK_LEN) - 1) << GLB_TZC_GLB_MISC_LOCK_POS)
+ (((1 << GLB_TZC_GLB_MISC_LOCK_LEN) - 1) << GLB_TZC_GLB_MISC_LOCK_POS)
#define GLB_TZC_GLB_MISC_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_MISC_LOCK_LEN) - 1) << GLB_TZC_GLB_MISC_LOCK_POS))
+ (~(((1 << GLB_TZC_GLB_MISC_LOCK_LEN) - 1) << GLB_TZC_GLB_MISC_LOCK_POS))
#define GLB_TZC_GLB_SRAM_LOCK GLB_TZC_GLB_SRAM_LOCK
-#define GLB_TZC_GLB_SRAM_LOCK_POS (26U)
-#define GLB_TZC_GLB_SRAM_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SRAM_LOCK_POS (26)
+#define GLB_TZC_GLB_SRAM_LOCK_LEN (1)
#define GLB_TZC_GLB_SRAM_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SRAM_LOCK_LEN) - 1) << GLB_TZC_GLB_SRAM_LOCK_POS)
+ (((1 << GLB_TZC_GLB_SRAM_LOCK_LEN) - 1) << GLB_TZC_GLB_SRAM_LOCK_POS)
#define GLB_TZC_GLB_SRAM_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SRAM_LOCK_LEN) - 1) << GLB_TZC_GLB_SRAM_LOCK_POS))
+ (~(((1 << GLB_TZC_GLB_SRAM_LOCK_LEN) - 1) << GLB_TZC_GLB_SRAM_LOCK_POS))
#define GLB_TZC_GLB_L2C_LOCK GLB_TZC_GLB_L2C_LOCK
-#define GLB_TZC_GLB_L2C_LOCK_POS (27U)
-#define GLB_TZC_GLB_L2C_LOCK_LEN (1U)
+#define GLB_TZC_GLB_L2C_LOCK_POS (27)
+#define GLB_TZC_GLB_L2C_LOCK_LEN (1)
#define GLB_TZC_GLB_L2C_LOCK_MSK \
- (((1U << GLB_TZC_GLB_L2C_LOCK_LEN) - 1) << GLB_TZC_GLB_L2C_LOCK_POS)
+ (((1 << GLB_TZC_GLB_L2C_LOCK_LEN) - 1) << GLB_TZC_GLB_L2C_LOCK_POS)
#define GLB_TZC_GLB_L2C_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_L2C_LOCK_LEN) - 1) << GLB_TZC_GLB_L2C_LOCK_POS))
+ (~(((1 << GLB_TZC_GLB_L2C_LOCK_LEN) - 1) << GLB_TZC_GLB_L2C_LOCK_POS))
#define GLB_TZC_GLB_BMX_LOCK GLB_TZC_GLB_BMX_LOCK
-#define GLB_TZC_GLB_BMX_LOCK_POS (28U)
-#define GLB_TZC_GLB_BMX_LOCK_LEN (1U)
+#define GLB_TZC_GLB_BMX_LOCK_POS (28)
+#define GLB_TZC_GLB_BMX_LOCK_LEN (1)
#define GLB_TZC_GLB_BMX_LOCK_MSK \
- (((1U << GLB_TZC_GLB_BMX_LOCK_LEN) - 1) << GLB_TZC_GLB_BMX_LOCK_POS)
+ (((1 << GLB_TZC_GLB_BMX_LOCK_LEN) - 1) << GLB_TZC_GLB_BMX_LOCK_POS)
#define GLB_TZC_GLB_BMX_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_BMX_LOCK_LEN) - 1) << GLB_TZC_GLB_BMX_LOCK_POS))
+ (~(((1 << GLB_TZC_GLB_BMX_LOCK_LEN) - 1) << GLB_TZC_GLB_BMX_LOCK_POS))
#define GLB_TZC_GLB_DBG_LOCK GLB_TZC_GLB_DBG_LOCK
-#define GLB_TZC_GLB_DBG_LOCK_POS (29U)
-#define GLB_TZC_GLB_DBG_LOCK_LEN (1U)
+#define GLB_TZC_GLB_DBG_LOCK_POS (29)
+#define GLB_TZC_GLB_DBG_LOCK_LEN (1)
#define GLB_TZC_GLB_DBG_LOCK_MSK \
- (((1U << GLB_TZC_GLB_DBG_LOCK_LEN) - 1) << GLB_TZC_GLB_DBG_LOCK_POS)
+ (((1 << GLB_TZC_GLB_DBG_LOCK_LEN) - 1) << GLB_TZC_GLB_DBG_LOCK_POS)
#define GLB_TZC_GLB_DBG_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_DBG_LOCK_LEN) - 1) << GLB_TZC_GLB_DBG_LOCK_POS))
+ (~(((1 << GLB_TZC_GLB_DBG_LOCK_LEN) - 1) << GLB_TZC_GLB_DBG_LOCK_POS))
#define GLB_TZC_GLB_MBIST_LOCK GLB_TZC_GLB_MBIST_LOCK
-#define GLB_TZC_GLB_MBIST_LOCK_POS (30U)
-#define GLB_TZC_GLB_MBIST_LOCK_LEN (1U)
+#define GLB_TZC_GLB_MBIST_LOCK_POS (30)
+#define GLB_TZC_GLB_MBIST_LOCK_LEN (1)
#define GLB_TZC_GLB_MBIST_LOCK_MSK \
- (((1U << GLB_TZC_GLB_MBIST_LOCK_LEN) - 1) << GLB_TZC_GLB_MBIST_LOCK_POS)
+ (((1 << GLB_TZC_GLB_MBIST_LOCK_LEN) - 1) << GLB_TZC_GLB_MBIST_LOCK_POS)
#define GLB_TZC_GLB_MBIST_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_MBIST_LOCK_LEN) - 1) << GLB_TZC_GLB_MBIST_LOCK_POS))
+ (~(((1 << GLB_TZC_GLB_MBIST_LOCK_LEN) - 1) << GLB_TZC_GLB_MBIST_LOCK_POS))
#define GLB_TZC_GLB_CLK_LOCK GLB_TZC_GLB_CLK_LOCK
-#define GLB_TZC_GLB_CLK_LOCK_POS (31U)
-#define GLB_TZC_GLB_CLK_LOCK_LEN (1U)
+#define GLB_TZC_GLB_CLK_LOCK_POS (31)
+#define GLB_TZC_GLB_CLK_LOCK_LEN (1)
#define GLB_TZC_GLB_CLK_LOCK_MSK \
- (((1U << GLB_TZC_GLB_CLK_LOCK_LEN) - 1) << GLB_TZC_GLB_CLK_LOCK_POS)
+ (((1 << GLB_TZC_GLB_CLK_LOCK_LEN) - 1) << GLB_TZC_GLB_CLK_LOCK_POS)
#define GLB_TZC_GLB_CLK_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_CLK_LOCK_LEN) - 1) << GLB_TZC_GLB_CLK_LOCK_POS))
+ (~(((1 << GLB_TZC_GLB_CLK_LOCK_LEN) - 1) << GLB_TZC_GLB_CLK_LOCK_POS))
/* 0xF04 : tzc_glb_ctrl_1 */
#define GLB_TZC_GLB_CTRL_1_OFFSET (0xF04)
#define GLB_TZC_GLB_SWRST_S20_LOCK GLB_TZC_GLB_SWRST_S20_LOCK
-#define GLB_TZC_GLB_SWRST_S20_LOCK_POS (0U)
-#define GLB_TZC_GLB_SWRST_S20_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S20_LOCK_POS (0)
+#define GLB_TZC_GLB_SWRST_S20_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S20_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S20_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S20_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S20_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S20_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S20_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S20_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S20_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S21_LOCK GLB_TZC_GLB_SWRST_S21_LOCK
-#define GLB_TZC_GLB_SWRST_S21_LOCK_POS (1U)
-#define GLB_TZC_GLB_SWRST_S21_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S21_LOCK_POS (1)
+#define GLB_TZC_GLB_SWRST_S21_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S21_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S21_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S21_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S21_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S21_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S21_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S21_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S21_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S22_LOCK GLB_TZC_GLB_SWRST_S22_LOCK
-#define GLB_TZC_GLB_SWRST_S22_LOCK_POS (2U)
-#define GLB_TZC_GLB_SWRST_S22_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S22_LOCK_POS (2)
+#define GLB_TZC_GLB_SWRST_S22_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S22_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S22_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S22_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S22_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S22_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S22_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S22_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S22_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S23_LOCK GLB_TZC_GLB_SWRST_S23_LOCK
-#define GLB_TZC_GLB_SWRST_S23_LOCK_POS (3U)
-#define GLB_TZC_GLB_SWRST_S23_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S23_LOCK_POS (3)
+#define GLB_TZC_GLB_SWRST_S23_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S23_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S23_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S23_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S23_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S23_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S23_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S23_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S23_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S24_LOCK GLB_TZC_GLB_SWRST_S24_LOCK
-#define GLB_TZC_GLB_SWRST_S24_LOCK_POS (4U)
-#define GLB_TZC_GLB_SWRST_S24_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S24_LOCK_POS (4)
+#define GLB_TZC_GLB_SWRST_S24_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S24_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S24_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S24_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S24_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S24_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S24_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S24_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S24_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S25_LOCK GLB_TZC_GLB_SWRST_S25_LOCK
-#define GLB_TZC_GLB_SWRST_S25_LOCK_POS (5U)
-#define GLB_TZC_GLB_SWRST_S25_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S25_LOCK_POS (5)
+#define GLB_TZC_GLB_SWRST_S25_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S25_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S25_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S25_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S25_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S25_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S25_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S25_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S25_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S26_LOCK GLB_TZC_GLB_SWRST_S26_LOCK
-#define GLB_TZC_GLB_SWRST_S26_LOCK_POS (6U)
-#define GLB_TZC_GLB_SWRST_S26_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S26_LOCK_POS (6)
+#define GLB_TZC_GLB_SWRST_S26_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S26_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S26_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S26_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S26_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S26_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S26_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S26_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S26_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S27_LOCK GLB_TZC_GLB_SWRST_S27_LOCK
-#define GLB_TZC_GLB_SWRST_S27_LOCK_POS (7U)
-#define GLB_TZC_GLB_SWRST_S27_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S27_LOCK_POS (7)
+#define GLB_TZC_GLB_SWRST_S27_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S27_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S27_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S27_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S27_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S27_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S27_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S27_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S27_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S28_LOCK GLB_TZC_GLB_SWRST_S28_LOCK
-#define GLB_TZC_GLB_SWRST_S28_LOCK_POS (8U)
-#define GLB_TZC_GLB_SWRST_S28_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S28_LOCK_POS (8)
+#define GLB_TZC_GLB_SWRST_S28_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S28_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S28_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S28_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S28_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S28_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S28_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S28_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S28_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S29_LOCK GLB_TZC_GLB_SWRST_S29_LOCK
-#define GLB_TZC_GLB_SWRST_S29_LOCK_POS (9U)
-#define GLB_TZC_GLB_SWRST_S29_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S29_LOCK_POS (9)
+#define GLB_TZC_GLB_SWRST_S29_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S29_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S29_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S29_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S29_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S29_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S29_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S29_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S29_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S2A_LOCK GLB_TZC_GLB_SWRST_S2A_LOCK
-#define GLB_TZC_GLB_SWRST_S2A_LOCK_POS (10U)
-#define GLB_TZC_GLB_SWRST_S2A_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S2A_LOCK_POS (10)
+#define GLB_TZC_GLB_SWRST_S2A_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S2A_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S2A_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S2A_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S2A_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S2A_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S2A_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S2A_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S2A_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S2B_LOCK GLB_TZC_GLB_SWRST_S2B_LOCK
-#define GLB_TZC_GLB_SWRST_S2B_LOCK_POS (11U)
-#define GLB_TZC_GLB_SWRST_S2B_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S2B_LOCK_POS (11)
+#define GLB_TZC_GLB_SWRST_S2B_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S2B_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S2B_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S2B_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S2B_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S2B_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S2B_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S2B_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S2B_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S2C_LOCK GLB_TZC_GLB_SWRST_S2C_LOCK
-#define GLB_TZC_GLB_SWRST_S2C_LOCK_POS (12U)
-#define GLB_TZC_GLB_SWRST_S2C_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S2C_LOCK_POS (12)
+#define GLB_TZC_GLB_SWRST_S2C_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S2C_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S2C_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S2C_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S2C_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S2C_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S2C_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S2C_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S2C_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S2D_LOCK GLB_TZC_GLB_SWRST_S2D_LOCK
-#define GLB_TZC_GLB_SWRST_S2D_LOCK_POS (13U)
-#define GLB_TZC_GLB_SWRST_S2D_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S2D_LOCK_POS (13)
+#define GLB_TZC_GLB_SWRST_S2D_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S2D_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S2D_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S2D_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S2D_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S2D_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S2D_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S2D_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S2D_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S2E_LOCK GLB_TZC_GLB_SWRST_S2E_LOCK
-#define GLB_TZC_GLB_SWRST_S2E_LOCK_POS (14U)
-#define GLB_TZC_GLB_SWRST_S2E_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S2E_LOCK_POS (14)
+#define GLB_TZC_GLB_SWRST_S2E_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S2E_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S2E_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S2E_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S2E_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S2E_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S2E_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S2E_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S2E_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S2F_LOCK GLB_TZC_GLB_SWRST_S2F_LOCK
-#define GLB_TZC_GLB_SWRST_S2F_LOCK_POS (15U)
-#define GLB_TZC_GLB_SWRST_S2F_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S2F_LOCK_POS (15)
+#define GLB_TZC_GLB_SWRST_S2F_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S2F_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S2F_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S2F_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S2F_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S2F_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S2F_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S2F_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S2F_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S10_LOCK GLB_TZC_GLB_SWRST_S10_LOCK
-#define GLB_TZC_GLB_SWRST_S10_LOCK_POS (16U)
-#define GLB_TZC_GLB_SWRST_S10_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S10_LOCK_POS (16)
+#define GLB_TZC_GLB_SWRST_S10_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S10_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S10_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S10_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S10_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S10_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S10_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S10_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S10_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S11_LOCK GLB_TZC_GLB_SWRST_S11_LOCK
-#define GLB_TZC_GLB_SWRST_S11_LOCK_POS (17U)
-#define GLB_TZC_GLB_SWRST_S11_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S11_LOCK_POS (17)
+#define GLB_TZC_GLB_SWRST_S11_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S11_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S11_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S11_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S11_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S11_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S11_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S11_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S11_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S12_LOCK GLB_TZC_GLB_SWRST_S12_LOCK
-#define GLB_TZC_GLB_SWRST_S12_LOCK_POS (18U)
-#define GLB_TZC_GLB_SWRST_S12_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S12_LOCK_POS (18)
+#define GLB_TZC_GLB_SWRST_S12_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S12_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S12_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S12_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S12_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S12_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S12_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S12_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S12_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S13_LOCK GLB_TZC_GLB_SWRST_S13_LOCK
-#define GLB_TZC_GLB_SWRST_S13_LOCK_POS (19U)
-#define GLB_TZC_GLB_SWRST_S13_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S13_LOCK_POS (19)
+#define GLB_TZC_GLB_SWRST_S13_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S13_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S13_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S13_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S13_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S13_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S13_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S13_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S13_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S14_LOCK GLB_TZC_GLB_SWRST_S14_LOCK
-#define GLB_TZC_GLB_SWRST_S14_LOCK_POS (20U)
-#define GLB_TZC_GLB_SWRST_S14_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S14_LOCK_POS (20)
+#define GLB_TZC_GLB_SWRST_S14_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S14_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S14_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S14_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S14_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S14_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S14_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S14_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S14_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S15_LOCK GLB_TZC_GLB_SWRST_S15_LOCK
-#define GLB_TZC_GLB_SWRST_S15_LOCK_POS (21U)
-#define GLB_TZC_GLB_SWRST_S15_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S15_LOCK_POS (21)
+#define GLB_TZC_GLB_SWRST_S15_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S15_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S15_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S15_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S15_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S15_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S15_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S15_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S15_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S16_LOCK GLB_TZC_GLB_SWRST_S16_LOCK
-#define GLB_TZC_GLB_SWRST_S16_LOCK_POS (22U)
-#define GLB_TZC_GLB_SWRST_S16_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S16_LOCK_POS (22)
+#define GLB_TZC_GLB_SWRST_S16_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S16_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S16_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S16_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S16_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S16_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S16_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S16_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S16_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S17_LOCK GLB_TZC_GLB_SWRST_S17_LOCK
-#define GLB_TZC_GLB_SWRST_S17_LOCK_POS (23U)
-#define GLB_TZC_GLB_SWRST_S17_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S17_LOCK_POS (23)
+#define GLB_TZC_GLB_SWRST_S17_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S17_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S17_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S17_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S17_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S17_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S17_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S17_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S17_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S18_LOCK GLB_TZC_GLB_SWRST_S18_LOCK
-#define GLB_TZC_GLB_SWRST_S18_LOCK_POS (24U)
-#define GLB_TZC_GLB_SWRST_S18_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S18_LOCK_POS (24)
+#define GLB_TZC_GLB_SWRST_S18_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S18_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S18_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S18_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S18_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S18_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S18_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S18_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S18_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S19_LOCK GLB_TZC_GLB_SWRST_S19_LOCK
-#define GLB_TZC_GLB_SWRST_S19_LOCK_POS (25U)
-#define GLB_TZC_GLB_SWRST_S19_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S19_LOCK_POS (25)
+#define GLB_TZC_GLB_SWRST_S19_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S19_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S19_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S19_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S19_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S19_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S19_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S19_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S19_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S1A_LOCK GLB_TZC_GLB_SWRST_S1A_LOCK
-#define GLB_TZC_GLB_SWRST_S1A_LOCK_POS (26U)
-#define GLB_TZC_GLB_SWRST_S1A_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S1A_LOCK_POS (26)
+#define GLB_TZC_GLB_SWRST_S1A_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S1A_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S1A_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S1A_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S1A_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S1A_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S1A_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S1A_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S1A_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S1B_LOCK GLB_TZC_GLB_SWRST_S1B_LOCK
-#define GLB_TZC_GLB_SWRST_S1B_LOCK_POS (27U)
-#define GLB_TZC_GLB_SWRST_S1B_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S1B_LOCK_POS (27)
+#define GLB_TZC_GLB_SWRST_S1B_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S1B_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S1B_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S1B_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S1B_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S1B_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S1B_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S1B_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S1B_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S1C_LOCK GLB_TZC_GLB_SWRST_S1C_LOCK
-#define GLB_TZC_GLB_SWRST_S1C_LOCK_POS (28U)
-#define GLB_TZC_GLB_SWRST_S1C_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S1C_LOCK_POS (28)
+#define GLB_TZC_GLB_SWRST_S1C_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S1C_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S1C_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S1C_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S1C_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S1C_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S1C_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S1C_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S1C_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S1D_LOCK GLB_TZC_GLB_SWRST_S1D_LOCK
-#define GLB_TZC_GLB_SWRST_S1D_LOCK_POS (29U)
-#define GLB_TZC_GLB_SWRST_S1D_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S1D_LOCK_POS (29)
+#define GLB_TZC_GLB_SWRST_S1D_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S1D_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S1D_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S1D_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S1D_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S1D_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S1D_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S1D_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S1D_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S1E_LOCK GLB_TZC_GLB_SWRST_S1E_LOCK
-#define GLB_TZC_GLB_SWRST_S1E_LOCK_POS (30U)
-#define GLB_TZC_GLB_SWRST_S1E_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S1E_LOCK_POS (30)
+#define GLB_TZC_GLB_SWRST_S1E_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S1E_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S1E_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S1E_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S1E_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S1E_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S1E_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S1E_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S1E_LOCK_POS))
#define GLB_TZC_GLB_SWRST_S1F_LOCK GLB_TZC_GLB_SWRST_S1F_LOCK
-#define GLB_TZC_GLB_SWRST_S1F_LOCK_POS (31U)
-#define GLB_TZC_GLB_SWRST_S1F_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S1F_LOCK_POS (31)
+#define GLB_TZC_GLB_SWRST_S1F_LOCK_LEN (1)
#define GLB_TZC_GLB_SWRST_S1F_LOCK_MSK \
- (((1U << GLB_TZC_GLB_SWRST_S1F_LOCK_LEN) - 1) \
+ (((1 << GLB_TZC_GLB_SWRST_S1F_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S1F_LOCK_POS)
#define GLB_TZC_GLB_SWRST_S1F_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_SWRST_S1F_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_SWRST_S1F_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_SWRST_S1F_LOCK_POS))
/* 0xF08 : tzc_glb_ctrl_2 */
#define GLB_TZC_GLB_CTRL_2_OFFSET (0xF08)
#define GLB_TZC_GLB_GPIO_0_LOCK GLB_TZC_GLB_GPIO_0_LOCK
-#define GLB_TZC_GLB_GPIO_0_LOCK_POS (0U)
-#define GLB_TZC_GLB_GPIO_0_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_0_LOCK_POS (0)
+#define GLB_TZC_GLB_GPIO_0_LOCK_LEN (1)
#define GLB_TZC_GLB_GPIO_0_LOCK_MSK \
- (((1U << GLB_TZC_GLB_GPIO_0_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_0_LOCK_POS)
+ (((1 << GLB_TZC_GLB_GPIO_0_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_0_LOCK_POS)
#define GLB_TZC_GLB_GPIO_0_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_GPIO_0_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_GPIO_0_LOCK_POS))
+ (~(((1 << GLB_TZC_GLB_GPIO_0_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_0_LOCK_POS))
#define GLB_TZC_GLB_GPIO_1_LOCK GLB_TZC_GLB_GPIO_1_LOCK
-#define GLB_TZC_GLB_GPIO_1_LOCK_POS (1U)
-#define GLB_TZC_GLB_GPIO_1_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_1_LOCK_POS (1)
+#define GLB_TZC_GLB_GPIO_1_LOCK_LEN (1)
#define GLB_TZC_GLB_GPIO_1_LOCK_MSK \
- (((1U << GLB_TZC_GLB_GPIO_1_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_1_LOCK_POS)
+ (((1 << GLB_TZC_GLB_GPIO_1_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_1_LOCK_POS)
#define GLB_TZC_GLB_GPIO_1_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_GPIO_1_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_GPIO_1_LOCK_POS))
+ (~(((1 << GLB_TZC_GLB_GPIO_1_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_1_LOCK_POS))
#define GLB_TZC_GLB_GPIO_2_LOCK GLB_TZC_GLB_GPIO_2_LOCK
-#define GLB_TZC_GLB_GPIO_2_LOCK_POS (2U)
-#define GLB_TZC_GLB_GPIO_2_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_2_LOCK_POS (2)
+#define GLB_TZC_GLB_GPIO_2_LOCK_LEN (1)
#define GLB_TZC_GLB_GPIO_2_LOCK_MSK \
- (((1U << GLB_TZC_GLB_GPIO_2_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_2_LOCK_POS)
+ (((1 << GLB_TZC_GLB_GPIO_2_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_2_LOCK_POS)
#define GLB_TZC_GLB_GPIO_2_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_GPIO_2_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_GPIO_2_LOCK_POS))
+ (~(((1 << GLB_TZC_GLB_GPIO_2_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_2_LOCK_POS))
#define GLB_TZC_GLB_GPIO_3_LOCK GLB_TZC_GLB_GPIO_3_LOCK
-#define GLB_TZC_GLB_GPIO_3_LOCK_POS (3U)
-#define GLB_TZC_GLB_GPIO_3_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_3_LOCK_POS (3)
+#define GLB_TZC_GLB_GPIO_3_LOCK_LEN (1)
#define GLB_TZC_GLB_GPIO_3_LOCK_MSK \
- (((1U << GLB_TZC_GLB_GPIO_3_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_3_LOCK_POS)
+ (((1 << GLB_TZC_GLB_GPIO_3_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_3_LOCK_POS)
#define GLB_TZC_GLB_GPIO_3_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_GPIO_3_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_GPIO_3_LOCK_POS))
+ (~(((1 << GLB_TZC_GLB_GPIO_3_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_3_LOCK_POS))
#define GLB_TZC_GLB_GPIO_4_LOCK GLB_TZC_GLB_GPIO_4_LOCK
-#define GLB_TZC_GLB_GPIO_4_LOCK_POS (4U)
-#define GLB_TZC_GLB_GPIO_4_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_4_LOCK_POS (4)
+#define GLB_TZC_GLB_GPIO_4_LOCK_LEN (1)
#define GLB_TZC_GLB_GPIO_4_LOCK_MSK \
- (((1U << GLB_TZC_GLB_GPIO_4_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_4_LOCK_POS)
+ (((1 << GLB_TZC_GLB_GPIO_4_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_4_LOCK_POS)
#define GLB_TZC_GLB_GPIO_4_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_GPIO_4_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_GPIO_4_LOCK_POS))
+ (~(((1 << GLB_TZC_GLB_GPIO_4_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_4_LOCK_POS))
#define GLB_TZC_GLB_GPIO_5_LOCK GLB_TZC_GLB_GPIO_5_LOCK
-#define GLB_TZC_GLB_GPIO_5_LOCK_POS (5U)
-#define GLB_TZC_GLB_GPIO_5_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_5_LOCK_POS (5)
+#define GLB_TZC_GLB_GPIO_5_LOCK_LEN (1)
#define GLB_TZC_GLB_GPIO_5_LOCK_MSK \
- (((1U << GLB_TZC_GLB_GPIO_5_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_5_LOCK_POS)
+ (((1 << GLB_TZC_GLB_GPIO_5_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_5_LOCK_POS)
#define GLB_TZC_GLB_GPIO_5_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_GPIO_5_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_GPIO_5_LOCK_POS))
+ (~(((1 << GLB_TZC_GLB_GPIO_5_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_5_LOCK_POS))
#define GLB_TZC_GLB_GPIO_6_LOCK GLB_TZC_GLB_GPIO_6_LOCK
-#define GLB_TZC_GLB_GPIO_6_LOCK_POS (6U)
-#define GLB_TZC_GLB_GPIO_6_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_6_LOCK_POS (6)
+#define GLB_TZC_GLB_GPIO_6_LOCK_LEN (1)
#define GLB_TZC_GLB_GPIO_6_LOCK_MSK \
- (((1U << GLB_TZC_GLB_GPIO_6_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_6_LOCK_POS)
+ (((1 << GLB_TZC_GLB_GPIO_6_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_6_LOCK_POS)
#define GLB_TZC_GLB_GPIO_6_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_GPIO_6_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_GPIO_6_LOCK_POS))
+ (~(((1 << GLB_TZC_GLB_GPIO_6_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_6_LOCK_POS))
#define GLB_TZC_GLB_GPIO_7_LOCK GLB_TZC_GLB_GPIO_7_LOCK
-#define GLB_TZC_GLB_GPIO_7_LOCK_POS (7U)
-#define GLB_TZC_GLB_GPIO_7_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_7_LOCK_POS (7)
+#define GLB_TZC_GLB_GPIO_7_LOCK_LEN (1)
#define GLB_TZC_GLB_GPIO_7_LOCK_MSK \
- (((1U << GLB_TZC_GLB_GPIO_7_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_7_LOCK_POS)
+ (((1 << GLB_TZC_GLB_GPIO_7_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_7_LOCK_POS)
#define GLB_TZC_GLB_GPIO_7_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_GPIO_7_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_GPIO_7_LOCK_POS))
+ (~(((1 << GLB_TZC_GLB_GPIO_7_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_7_LOCK_POS))
#define GLB_TZC_GLB_GPIO_8_LOCK GLB_TZC_GLB_GPIO_8_LOCK
-#define GLB_TZC_GLB_GPIO_8_LOCK_POS (8U)
-#define GLB_TZC_GLB_GPIO_8_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_8_LOCK_POS (8)
+#define GLB_TZC_GLB_GPIO_8_LOCK_LEN (1)
#define GLB_TZC_GLB_GPIO_8_LOCK_MSK \
- (((1U << GLB_TZC_GLB_GPIO_8_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_8_LOCK_POS)
+ (((1 << GLB_TZC_GLB_GPIO_8_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_8_LOCK_POS)
#define GLB_TZC_GLB_GPIO_8_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_GPIO_8_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_GPIO_8_LOCK_POS))
+ (~(((1 << GLB_TZC_GLB_GPIO_8_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_8_LOCK_POS))
#define GLB_TZC_GLB_GPIO_9_LOCK GLB_TZC_GLB_GPIO_9_LOCK
-#define GLB_TZC_GLB_GPIO_9_LOCK_POS (9U)
-#define GLB_TZC_GLB_GPIO_9_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_9_LOCK_POS (9)
+#define GLB_TZC_GLB_GPIO_9_LOCK_LEN (1)
#define GLB_TZC_GLB_GPIO_9_LOCK_MSK \
- (((1U << GLB_TZC_GLB_GPIO_9_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_9_LOCK_POS)
+ (((1 << GLB_TZC_GLB_GPIO_9_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_9_LOCK_POS)
#define GLB_TZC_GLB_GPIO_9_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_GPIO_9_LOCK_LEN) - 1) \
- << GLB_TZC_GLB_GPIO_9_LOCK_POS))
+ (~(((1 << GLB_TZC_GLB_GPIO_9_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_9_LOCK_POS))
#define GLB_TZC_GLB_GPIO_10_LOCK GLB_TZC_GLB_GPIO_10_LOCK
-#define GLB_TZC_GLB_GPIO_10_LOCK_POS (10U)
-#define GLB_TZC_GLB_GPIO_10_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_10_LOCK_POS (10)
+#define GLB_TZC_GLB_GPIO_10_LOCK_LEN (1)
#define GLB_TZC_GLB_GPIO_10_LOCK_MSK \
- (((1U << GLB_TZC_GLB_GPIO_10_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_10_LOCK_POS)
+ (((1 << GLB_TZC_GLB_GPIO_10_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_10_LOCK_POS)
#define GLB_TZC_GLB_GPIO_10_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_GPIO_10_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_GPIO_10_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_GPIO_10_LOCK_POS))
#define GLB_TZC_GLB_GPIO_11_LOCK GLB_TZC_GLB_GPIO_11_LOCK
-#define GLB_TZC_GLB_GPIO_11_LOCK_POS (11U)
-#define GLB_TZC_GLB_GPIO_11_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_11_LOCK_POS (11)
+#define GLB_TZC_GLB_GPIO_11_LOCK_LEN (1)
#define GLB_TZC_GLB_GPIO_11_LOCK_MSK \
- (((1U << GLB_TZC_GLB_GPIO_11_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_11_LOCK_POS)
+ (((1 << GLB_TZC_GLB_GPIO_11_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_11_LOCK_POS)
#define GLB_TZC_GLB_GPIO_11_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_GPIO_11_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_GPIO_11_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_GPIO_11_LOCK_POS))
#define GLB_TZC_GLB_GPIO_12_LOCK GLB_TZC_GLB_GPIO_12_LOCK
-#define GLB_TZC_GLB_GPIO_12_LOCK_POS (12U)
-#define GLB_TZC_GLB_GPIO_12_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_12_LOCK_POS (12)
+#define GLB_TZC_GLB_GPIO_12_LOCK_LEN (1)
#define GLB_TZC_GLB_GPIO_12_LOCK_MSK \
- (((1U << GLB_TZC_GLB_GPIO_12_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_12_LOCK_POS)
+ (((1 << GLB_TZC_GLB_GPIO_12_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_12_LOCK_POS)
#define GLB_TZC_GLB_GPIO_12_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_GPIO_12_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_GPIO_12_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_GPIO_12_LOCK_POS))
#define GLB_TZC_GLB_GPIO_13_LOCK GLB_TZC_GLB_GPIO_13_LOCK
-#define GLB_TZC_GLB_GPIO_13_LOCK_POS (13U)
-#define GLB_TZC_GLB_GPIO_13_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_13_LOCK_POS (13)
+#define GLB_TZC_GLB_GPIO_13_LOCK_LEN (1)
#define GLB_TZC_GLB_GPIO_13_LOCK_MSK \
- (((1U << GLB_TZC_GLB_GPIO_13_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_13_LOCK_POS)
+ (((1 << GLB_TZC_GLB_GPIO_13_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_13_LOCK_POS)
#define GLB_TZC_GLB_GPIO_13_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_GPIO_13_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_GPIO_13_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_GPIO_13_LOCK_POS))
#define GLB_TZC_GLB_GPIO_14_LOCK GLB_TZC_GLB_GPIO_14_LOCK
-#define GLB_TZC_GLB_GPIO_14_LOCK_POS (14U)
-#define GLB_TZC_GLB_GPIO_14_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_14_LOCK_POS (14)
+#define GLB_TZC_GLB_GPIO_14_LOCK_LEN (1)
#define GLB_TZC_GLB_GPIO_14_LOCK_MSK \
- (((1U << GLB_TZC_GLB_GPIO_14_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_14_LOCK_POS)
+ (((1 << GLB_TZC_GLB_GPIO_14_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_14_LOCK_POS)
#define GLB_TZC_GLB_GPIO_14_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_GPIO_14_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_GPIO_14_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_GPIO_14_LOCK_POS))
#define GLB_TZC_GLB_GPIO_15_LOCK GLB_TZC_GLB_GPIO_15_LOCK
-#define GLB_TZC_GLB_GPIO_15_LOCK_POS (15U)
-#define GLB_TZC_GLB_GPIO_15_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_15_LOCK_POS (15)
+#define GLB_TZC_GLB_GPIO_15_LOCK_LEN (1)
#define GLB_TZC_GLB_GPIO_15_LOCK_MSK \
- (((1U << GLB_TZC_GLB_GPIO_15_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_15_LOCK_POS)
+ (((1 << GLB_TZC_GLB_GPIO_15_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_15_LOCK_POS)
#define GLB_TZC_GLB_GPIO_15_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_GPIO_15_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_GPIO_15_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_GPIO_15_LOCK_POS))
#define GLB_TZC_GLB_GPIO_16_LOCK GLB_TZC_GLB_GPIO_16_LOCK
-#define GLB_TZC_GLB_GPIO_16_LOCK_POS (16U)
-#define GLB_TZC_GLB_GPIO_16_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_16_LOCK_POS (16)
+#define GLB_TZC_GLB_GPIO_16_LOCK_LEN (1)
#define GLB_TZC_GLB_GPIO_16_LOCK_MSK \
- (((1U << GLB_TZC_GLB_GPIO_16_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_16_LOCK_POS)
+ (((1 << GLB_TZC_GLB_GPIO_16_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_16_LOCK_POS)
#define GLB_TZC_GLB_GPIO_16_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_GPIO_16_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_GPIO_16_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_GPIO_16_LOCK_POS))
#define GLB_TZC_GLB_GPIO_17_LOCK GLB_TZC_GLB_GPIO_17_LOCK
-#define GLB_TZC_GLB_GPIO_17_LOCK_POS (17U)
-#define GLB_TZC_GLB_GPIO_17_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_17_LOCK_POS (17)
+#define GLB_TZC_GLB_GPIO_17_LOCK_LEN (1)
#define GLB_TZC_GLB_GPIO_17_LOCK_MSK \
- (((1U << GLB_TZC_GLB_GPIO_17_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_17_LOCK_POS)
+ (((1 << GLB_TZC_GLB_GPIO_17_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_17_LOCK_POS)
#define GLB_TZC_GLB_GPIO_17_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_GPIO_17_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_GPIO_17_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_GPIO_17_LOCK_POS))
#define GLB_TZC_GLB_GPIO_18_LOCK GLB_TZC_GLB_GPIO_18_LOCK
-#define GLB_TZC_GLB_GPIO_18_LOCK_POS (18U)
-#define GLB_TZC_GLB_GPIO_18_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_18_LOCK_POS (18)
+#define GLB_TZC_GLB_GPIO_18_LOCK_LEN (1)
#define GLB_TZC_GLB_GPIO_18_LOCK_MSK \
- (((1U << GLB_TZC_GLB_GPIO_18_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_18_LOCK_POS)
+ (((1 << GLB_TZC_GLB_GPIO_18_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_18_LOCK_POS)
#define GLB_TZC_GLB_GPIO_18_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_GPIO_18_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_GPIO_18_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_GPIO_18_LOCK_POS))
#define GLB_TZC_GLB_GPIO_19_LOCK GLB_TZC_GLB_GPIO_19_LOCK
-#define GLB_TZC_GLB_GPIO_19_LOCK_POS (19U)
-#define GLB_TZC_GLB_GPIO_19_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_19_LOCK_POS (19)
+#define GLB_TZC_GLB_GPIO_19_LOCK_LEN (1)
#define GLB_TZC_GLB_GPIO_19_LOCK_MSK \
- (((1U << GLB_TZC_GLB_GPIO_19_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_19_LOCK_POS)
+ (((1 << GLB_TZC_GLB_GPIO_19_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_19_LOCK_POS)
#define GLB_TZC_GLB_GPIO_19_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_GPIO_19_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_GPIO_19_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_GPIO_19_LOCK_POS))
#define GLB_TZC_GLB_GPIO_20_LOCK GLB_TZC_GLB_GPIO_20_LOCK
-#define GLB_TZC_GLB_GPIO_20_LOCK_POS (20U)
-#define GLB_TZC_GLB_GPIO_20_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_20_LOCK_POS (20)
+#define GLB_TZC_GLB_GPIO_20_LOCK_LEN (1)
#define GLB_TZC_GLB_GPIO_20_LOCK_MSK \
- (((1U << GLB_TZC_GLB_GPIO_20_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_20_LOCK_POS)
+ (((1 << GLB_TZC_GLB_GPIO_20_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_20_LOCK_POS)
#define GLB_TZC_GLB_GPIO_20_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_GPIO_20_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_GPIO_20_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_GPIO_20_LOCK_POS))
#define GLB_TZC_GLB_GPIO_21_LOCK GLB_TZC_GLB_GPIO_21_LOCK
-#define GLB_TZC_GLB_GPIO_21_LOCK_POS (21U)
-#define GLB_TZC_GLB_GPIO_21_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_21_LOCK_POS (21)
+#define GLB_TZC_GLB_GPIO_21_LOCK_LEN (1)
#define GLB_TZC_GLB_GPIO_21_LOCK_MSK \
- (((1U << GLB_TZC_GLB_GPIO_21_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_21_LOCK_POS)
+ (((1 << GLB_TZC_GLB_GPIO_21_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_21_LOCK_POS)
#define GLB_TZC_GLB_GPIO_21_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_GPIO_21_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_GPIO_21_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_GPIO_21_LOCK_POS))
#define GLB_TZC_GLB_GPIO_22_LOCK GLB_TZC_GLB_GPIO_22_LOCK
-#define GLB_TZC_GLB_GPIO_22_LOCK_POS (22U)
-#define GLB_TZC_GLB_GPIO_22_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_22_LOCK_POS (22)
+#define GLB_TZC_GLB_GPIO_22_LOCK_LEN (1)
#define GLB_TZC_GLB_GPIO_22_LOCK_MSK \
- (((1U << GLB_TZC_GLB_GPIO_22_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_22_LOCK_POS)
+ (((1 << GLB_TZC_GLB_GPIO_22_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_22_LOCK_POS)
#define GLB_TZC_GLB_GPIO_22_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_GPIO_22_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_GPIO_22_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_GPIO_22_LOCK_POS))
#define GLB_TZC_GLB_GPIO_23_LOCK GLB_TZC_GLB_GPIO_23_LOCK
-#define GLB_TZC_GLB_GPIO_23_LOCK_POS (23U)
-#define GLB_TZC_GLB_GPIO_23_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_23_LOCK_POS (23)
+#define GLB_TZC_GLB_GPIO_23_LOCK_LEN (1)
#define GLB_TZC_GLB_GPIO_23_LOCK_MSK \
- (((1U << GLB_TZC_GLB_GPIO_23_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_23_LOCK_POS)
+ (((1 << GLB_TZC_GLB_GPIO_23_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_23_LOCK_POS)
#define GLB_TZC_GLB_GPIO_23_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_GPIO_23_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_GPIO_23_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_GPIO_23_LOCK_POS))
#define GLB_TZC_GLB_GPIO_24_LOCK GLB_TZC_GLB_GPIO_24_LOCK
-#define GLB_TZC_GLB_GPIO_24_LOCK_POS (24U)
-#define GLB_TZC_GLB_GPIO_24_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_24_LOCK_POS (24)
+#define GLB_TZC_GLB_GPIO_24_LOCK_LEN (1)
#define GLB_TZC_GLB_GPIO_24_LOCK_MSK \
- (((1U << GLB_TZC_GLB_GPIO_24_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_24_LOCK_POS)
+ (((1 << GLB_TZC_GLB_GPIO_24_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_24_LOCK_POS)
#define GLB_TZC_GLB_GPIO_24_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_GPIO_24_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_GPIO_24_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_GPIO_24_LOCK_POS))
#define GLB_TZC_GLB_GPIO_25_LOCK GLB_TZC_GLB_GPIO_25_LOCK
-#define GLB_TZC_GLB_GPIO_25_LOCK_POS (25U)
-#define GLB_TZC_GLB_GPIO_25_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_25_LOCK_POS (25)
+#define GLB_TZC_GLB_GPIO_25_LOCK_LEN (1)
#define GLB_TZC_GLB_GPIO_25_LOCK_MSK \
- (((1U << GLB_TZC_GLB_GPIO_25_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_25_LOCK_POS)
+ (((1 << GLB_TZC_GLB_GPIO_25_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_25_LOCK_POS)
#define GLB_TZC_GLB_GPIO_25_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_GPIO_25_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_GPIO_25_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_GPIO_25_LOCK_POS))
#define GLB_TZC_GLB_GPIO_26_LOCK GLB_TZC_GLB_GPIO_26_LOCK
-#define GLB_TZC_GLB_GPIO_26_LOCK_POS (26U)
-#define GLB_TZC_GLB_GPIO_26_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_26_LOCK_POS (26)
+#define GLB_TZC_GLB_GPIO_26_LOCK_LEN (1)
#define GLB_TZC_GLB_GPIO_26_LOCK_MSK \
- (((1U << GLB_TZC_GLB_GPIO_26_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_26_LOCK_POS)
+ (((1 << GLB_TZC_GLB_GPIO_26_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_26_LOCK_POS)
#define GLB_TZC_GLB_GPIO_26_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_GPIO_26_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_GPIO_26_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_GPIO_26_LOCK_POS))
#define GLB_TZC_GLB_GPIO_27_LOCK GLB_TZC_GLB_GPIO_27_LOCK
-#define GLB_TZC_GLB_GPIO_27_LOCK_POS (27U)
-#define GLB_TZC_GLB_GPIO_27_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_27_LOCK_POS (27)
+#define GLB_TZC_GLB_GPIO_27_LOCK_LEN (1)
#define GLB_TZC_GLB_GPIO_27_LOCK_MSK \
- (((1U << GLB_TZC_GLB_GPIO_27_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_27_LOCK_POS)
+ (((1 << GLB_TZC_GLB_GPIO_27_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_27_LOCK_POS)
#define GLB_TZC_GLB_GPIO_27_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_GPIO_27_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_GPIO_27_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_GPIO_27_LOCK_POS))
#define GLB_TZC_GLB_GPIO_28_LOCK GLB_TZC_GLB_GPIO_28_LOCK
-#define GLB_TZC_GLB_GPIO_28_LOCK_POS (28U)
-#define GLB_TZC_GLB_GPIO_28_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_28_LOCK_POS (28)
+#define GLB_TZC_GLB_GPIO_28_LOCK_LEN (1)
#define GLB_TZC_GLB_GPIO_28_LOCK_MSK \
- (((1U << GLB_TZC_GLB_GPIO_28_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_28_LOCK_POS)
+ (((1 << GLB_TZC_GLB_GPIO_28_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_28_LOCK_POS)
#define GLB_TZC_GLB_GPIO_28_LOCK_UMSK \
- (~(((1U << GLB_TZC_GLB_GPIO_28_LOCK_LEN) - 1) \
+ (~(((1 << GLB_TZC_GLB_GPIO_28_LOCK_LEN) - 1) \
<< GLB_TZC_GLB_GPIO_28_LOCK_POS))
/* 0xF0C : tzc_glb_ctrl_3 */
@@ -3947,106 +3928,104 @@
#define GLB_GPIO_CFGCTL_OFFSET (0x0)
#define GLB_REG_GPIO_0_IE GLB_REG_GPIO_0_IE
-#define GLB_REG_GPIO_0_IE_POS (0U)
-#define GLB_REG_GPIO_0_IE_LEN (1U)
+#define GLB_REG_GPIO_0_IE_POS (0)
+#define GLB_REG_GPIO_0_IE_LEN (1)
#define GLB_REG_GPIO_0_IE_MSK \
- (((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS)
+ (((1 << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS)
#define GLB_REG_GPIO_0_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS))
+ (~(((1 << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS))
#define GLB_REG_GPIO_0_SMT GLB_REG_GPIO_0_SMT
-#define GLB_REG_GPIO_0_SMT_POS (1U)
-#define GLB_REG_GPIO_0_SMT_LEN (1U)
+#define GLB_REG_GPIO_0_SMT_POS (1)
+#define GLB_REG_GPIO_0_SMT_LEN (1)
#define GLB_REG_GPIO_0_SMT_MSK \
- (((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS)
+ (((1 << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS)
#define GLB_REG_GPIO_0_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS))
#define GLB_REG_GPIO_0_DRV GLB_REG_GPIO_0_DRV
-#define GLB_REG_GPIO_0_DRV_POS (2U)
-#define GLB_REG_GPIO_0_DRV_LEN (2U)
+#define GLB_REG_GPIO_0_DRV_POS (2)
+#define GLB_REG_GPIO_0_DRV_LEN (2)
#define GLB_REG_GPIO_0_DRV_MSK \
- (((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS)
+ (((1 << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS)
#define GLB_REG_GPIO_0_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS))
#define GLB_REG_GPIO_0_PU GLB_REG_GPIO_0_PU
-#define GLB_REG_GPIO_0_PU_POS (4U)
-#define GLB_REG_GPIO_0_PU_LEN (1U)
+#define GLB_REG_GPIO_0_PU_POS (4)
+#define GLB_REG_GPIO_0_PU_LEN (1)
#define GLB_REG_GPIO_0_PU_MSK \
- (((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS)
+ (((1 << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS)
#define GLB_REG_GPIO_0_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS))
+ (~(((1 << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS))
#define GLB_REG_GPIO_0_PD GLB_REG_GPIO_0_PD
-#define GLB_REG_GPIO_0_PD_POS (5U)
-#define GLB_REG_GPIO_0_PD_LEN (1U)
+#define GLB_REG_GPIO_0_PD_POS (5)
+#define GLB_REG_GPIO_0_PD_LEN (1)
#define GLB_REG_GPIO_0_PD_MSK \
- (((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS)
+ (((1 << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS)
#define GLB_REG_GPIO_0_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS))
+ (~(((1 << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS))
#define GLB_REG_GPIO_0_FUNC_SEL GLB_REG_GPIO_0_FUNC_SEL
-#define GLB_REG_GPIO_0_FUNC_SEL_POS (8U)
-#define GLB_REG_GPIO_0_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_0_FUNC_SEL_POS (8)
+#define GLB_REG_GPIO_0_FUNC_SEL_LEN (4)
#define GLB_REG_GPIO_0_FUNC_SEL_MSK \
- (((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS)
+ (((1 << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS)
#define GLB_REG_GPIO_0_FUNC_SEL_UMSK \
- (~(((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) \
- << GLB_REG_GPIO_0_FUNC_SEL_POS))
+ (~(((1 << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS))
#define GLB_REAL_GPIO_0_FUNC_SEL GLB_REAL_GPIO_0_FUNC_SEL
-#define GLB_REAL_GPIO_0_FUNC_SEL_POS (12U)
-#define GLB_REAL_GPIO_0_FUNC_SEL_LEN (4U)
+#define GLB_REAL_GPIO_0_FUNC_SEL_POS (12)
+#define GLB_REAL_GPIO_0_FUNC_SEL_LEN (4)
#define GLB_REAL_GPIO_0_FUNC_SEL_MSK \
- (((1U << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_0_FUNC_SEL_POS)
+ (((1 << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_0_FUNC_SEL_POS)
#define GLB_REAL_GPIO_0_FUNC_SEL_UMSK \
- (~(((1U << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) \
+ (~(((1 << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) \
<< GLB_REAL_GPIO_0_FUNC_SEL_POS))
#define GLB_REG_GPIO_1_IE GLB_REG_GPIO_1_IE
-#define GLB_REG_GPIO_1_IE_POS (16U)
-#define GLB_REG_GPIO_1_IE_LEN (1U)
+#define GLB_REG_GPIO_1_IE_POS (16)
+#define GLB_REG_GPIO_1_IE_LEN (1)
#define GLB_REG_GPIO_1_IE_MSK \
- (((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS)
+ (((1 << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS)
#define GLB_REG_GPIO_1_IE_UMSK \
- (~(((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS))
+ (~(((1 << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS))
#define GLB_REG_GPIO_1_SMT GLB_REG_GPIO_1_SMT
-#define GLB_REG_GPIO_1_SMT_POS (17U)
-#define GLB_REG_GPIO_1_SMT_LEN (1U)
+#define GLB_REG_GPIO_1_SMT_POS (17)
+#define GLB_REG_GPIO_1_SMT_LEN (1)
#define GLB_REG_GPIO_1_SMT_MSK \
- (((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS)
+ (((1 << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS)
#define GLB_REG_GPIO_1_SMT_UMSK \
- (~(((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS))
+ (~(((1 << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS))
#define GLB_REG_GPIO_1_DRV GLB_REG_GPIO_1_DRV
-#define GLB_REG_GPIO_1_DRV_POS (18U)
-#define GLB_REG_GPIO_1_DRV_LEN (2U)
+#define GLB_REG_GPIO_1_DRV_POS (18)
+#define GLB_REG_GPIO_1_DRV_LEN (2)
#define GLB_REG_GPIO_1_DRV_MSK \
- (((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS)
+ (((1 << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS)
#define GLB_REG_GPIO_1_DRV_UMSK \
- (~(((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS))
+ (~(((1 << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS))
#define GLB_REG_GPIO_1_PU GLB_REG_GPIO_1_PU
-#define GLB_REG_GPIO_1_PU_POS (20U)
-#define GLB_REG_GPIO_1_PU_LEN (1U)
+#define GLB_REG_GPIO_1_PU_POS (20)
+#define GLB_REG_GPIO_1_PU_LEN (1)
#define GLB_REG_GPIO_1_PU_MSK \
- (((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS)
+ (((1 << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS)
#define GLB_REG_GPIO_1_PU_UMSK \
- (~(((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS))
+ (~(((1 << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS))
#define GLB_REG_GPIO_1_PD GLB_REG_GPIO_1_PD
-#define GLB_REG_GPIO_1_PD_POS (21U)
-#define GLB_REG_GPIO_1_PD_LEN (1U)
+#define GLB_REG_GPIO_1_PD_POS (21)
+#define GLB_REG_GPIO_1_PD_LEN (1)
#define GLB_REG_GPIO_1_PD_MSK \
- (((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS)
+ (((1 << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS)
#define GLB_REG_GPIO_1_PD_UMSK \
- (~(((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS))
+ (~(((1 << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS))
#define GLB_REG_GPIO_1_FUNC_SEL GLB_REG_GPIO_1_FUNC_SEL
-#define GLB_REG_GPIO_1_FUNC_SEL_POS (24U)
-#define GLB_REG_GPIO_1_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_1_FUNC_SEL_POS (24)
+#define GLB_REG_GPIO_1_FUNC_SEL_LEN (4)
#define GLB_REG_GPIO_1_FUNC_SEL_MSK \
- (((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS)
+ (((1 << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS)
#define GLB_REG_GPIO_1_FUNC_SEL_UMSK \
- (~(((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) \
- << GLB_REG_GPIO_1_FUNC_SEL_POS))
+ (~(((1 << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS))
#define GLB_REAL_GPIO_1_FUNC_SEL GLB_REAL_GPIO_1_FUNC_SEL
-#define GLB_REAL_GPIO_1_FUNC_SEL_POS (28U)
-#define GLB_REAL_GPIO_1_FUNC_SEL_LEN (4U)
+#define GLB_REAL_GPIO_1_FUNC_SEL_POS (28)
+#define GLB_REAL_GPIO_1_FUNC_SEL_LEN (4)
#define GLB_REAL_GPIO_1_FUNC_SEL_MSK \
- (((1U << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_1_FUNC_SEL_POS)
+ (((1 << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_1_FUNC_SEL_POS)
#define GLB_REAL_GPIO_1_FUNC_SEL_UMSK \
- (~(((1U << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) \
+ (~(((1 << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) \
<< GLB_REAL_GPIO_1_FUNC_SEL_POS))
#define GLB_GPIO_OFFSET 0x100
@@ -4054,1705 +4033,187 @@
#define GLB_GPIO_OUTPUT_OFFSET 0x188
#define GLB_GPIO_OUTPUT_EN_OFFSET 0x190
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
/* GLB root clock type definition */
-enum glb_root_clk_e
-{
- GLB_ROOT_CLK_RC32M, /* root clock select RC32M */
- GLB_ROOT_CLK_XTAL, /* root clock select XTAL */
- GLB_ROOT_CLK_PLL /* root clock select PLL others */
-};
+#define GLB_ROOT_CLK_RC32M 0 /* root clock select RC32M */
+#define GLB_ROOT_CLK_XTAL 1 /* root clock select XTAL */
+#define GLB_ROOT_CLK_PLL 2 /* root clock select PLL others */
/* GLB system clock type definition */
-enum glb_sys_clk_e
-{
- GLB_SYS_CLK_RC32M, /* use RC32M as system clock frequency */
- GLB_SYS_CLK_XTAL, /* use XTAL as system clock */
- GLB_SYS_CLK_PLL48M, /* use PLL output 48M as system clock */
- GLB_SYS_CLK_PLL120M, /* use PLL output 120M as system clock */
- GLB_SYS_CLK_PLL160M, /* use PLL output 160M as system clock */
- GLB_SYS_CLK_PLL192M /* use PLL output 192M as system clock */
-};
+#define GLB_SYS_CLK_RC32M 0 /* use RC32M as system clock frequency */
+#define GLB_SYS_CLK_XTAL 1 /* use XTAL as system clock */
+#define GLB_SYS_CLK_PLL48M 2 /* use PLL output 48M as system clock */
+#define GLB_SYS_CLK_PLL120M 3 /* use PLL output 120M as system clock */
+#define GLB_SYS_CLK_PLL160M 4 /* use PLL output 160M as system clock */
+#define GLB_SYS_CLK_PLL192M 5 /* use PLL output 192M as system clock */
/* GLB DMA clock ID type definition */
-enum glb_dma_clk_id_e
-{
- GLB_DMA_CLK_DMA0_CH0, /* DMA clock ID:channel 0 */
- GLB_DMA_CLK_DMA0_CH1, /* DMA clock ID:channel 1 */
- GLB_DMA_CLK_DMA0_CH2, /* DMA clock ID:channel 2 */
- GLB_DMA_CLK_DMA0_CH3 /* DMA clock ID:channel 3 */
-};
+#define GLB_DMA_CLK_DMA0_CH0 0 /* DMA clock ID:channel 0 */
+#define GLB_DMA_CLK_DMA0_CH1 1 /* DMA clock ID:channel 1 */
+#define GLB_DMA_CLK_DMA0_CH2 2 /* DMA clock ID:channel 2 */
+#define GLB_DMA_CLK_DMA0_CH3 3 /* DMA clock ID:channel 3 */
/* GLB clock source type definition */
-enum glb_ir_clk_src_e
-{
- GLB_IR_CLK_SRC_XCLK /* IR clock source select XCLK */
-};
+#define GLB_IR_CLK_SRC_XCLK 0 /* IR clock source select XCLK */
/* GLB flash clock type definition */
-enum glb_sflash_clk_e
-{
- GLB_SFLASH_CLK_120M, /* Select 120M as flash clock */
- GLB_SFLASH_CLK_XTAL, /* Select XTAL as flash clock */
- GLB_SFLASH_CLK_48M, /* Select 48M as flash clock */
- GLB_SFLASH_CLK_80M, /* Select 80M as flash clock */
- GLB_SFLASH_CLK_BCLK, /* Select BCLK as flash clock */
- GLB_SFLASH_CLK_96M /* Select 96M as flash clock */
-};
+#define GLB_SFLASH_CLK_120M 0 /* Select 120M as flash clock */
+#define GLB_SFLASH_CLK_XTAL 1 /* Select XTAL as flash clock */
+#define GLB_SFLASH_CLK_48M 2 /* Select 48M as flash clock */
+#define GLB_SFLASH_CLK_80M 3 /* Select 80M as flash clock */
+#define GLB_SFLASH_CLK_BCLK 4 /* Select BCLK as flash clock */
+#define GLB_SFLASH_CLK_96M 5 /* Select 96M as flash clock */
/* GLB SPI pad action type definition */
-enum glb_spi_pad_act_as_e
-{
- GLB_SPI_PAD_ACT_AS_SLAVE, /* SPI pad act as slave */
- GLB_SPI_PAD_ACT_AS_MASTER /* SPI pad act as master */
-};
+#define GLB_SPI_PAD_ACT_AS_SLAVE 0 /* SPI pad act as slave */
+#define GLB_SPI_PAD_ACT_AS_MASTER 1 /* SPI pad act as master */
/* GLB PKA clock type definition */
-enum glb_pka_clk_type_e
-{
- GLB_PKA_CLK_HCLK, /* Select HCLK as PKA clock */
- GLB_PKA_CLK_PLL120M /* Select PLL 120M as PKA clock */
-};
+#define GLB_PKA_CLK_HCLK 0 /* Select HCLK as PKA clock */
+#define GLB_PKA_CLK_PLL120M 1 /* Select PLL 120M as PKA clock */
/* BMX arb mode type definition */
-enum bmx_arb_type_e
-{
- BMX_ARB_FIX, /* 0->fix */
- BMX_ARB_ROUND_ROBIN, /* 2->round-robin */
- BMX_ARB_RANDOM /* 3->random */
-};
-
-/* BMX configuration structure type definition */
-
-struct bmx_cfg_type_s
-{
- /* Bus timeout enable: detect slave no reaponse in 1024 cycles */
-
- uint8_t timeout_en;
- void * err_en; /* Bus error response enable */
- enum bmx_arb_type_e arb_mod; /* 0->fix, 2->round-robin, 3->random */
-};
+#define BMX_ARB_FIX 0 /* 0->fix */
+#define BMX_ARB_ROUND_ROBIN 1 /* 2->round-robin */
+#define BMX_ARB_RANDOM 2 /* 3->random */
/* BMX bus err type definition */
-enum bmx_bus_err_type_e
-{
- BMX_BUS_ERR_TRUSTZONE_DECODE, /* Bus trustzone decode error */
- BMX_BUS_ERR_ADDR_DECODE /* Bus addr decode error */
-};
+#define BMX_BUS_ERR_TRUSTZONE_DECODE 0 /* Bus trustzone decode error */
+#define BMX_BUS_ERR_ADDR_DECODE 1 /* Bus addr decode error */
/* BMX bus err interrupt type definition */
-enum bmx_err_int_type_e
-{
- BMX_ERR_INT_ERR, /* BMX bus err interrupt */
- BMX_ERR_INT_ALL /* BMX bus err interrupt max num */
-};
+#define BMX_ERR_INT_ERR 0 /* BMX bus err interrupt */
+#define BMX_ERR_INT_ALL 1 /* BMX bus err interrupt max num */
/* BMX time out interrupt type definition */
-enum bmx_to_int_type_e
-{
- BMX_TO_INT_TIMEOUT, /* BMX timeout interrupt */
- BMX_TO_INT_ALL /* BMX timeout interrupt max num */
-};
+#define BMX_TO_INT_TIMEOUT 0 /* BMX timeout interrupt */
+#define BMX_TO_INT_ALL 1 /* BMX timeout interrupt max num */
/* GLB EM type definition */
-enum glb_em_type_e
-{
- GLB_EM_0KB = 0x0, /* 0x0 --> 0KB */
- GLB_EM_8KB = 0x3, /* 0x3 --> 8KB */
- GLB_EM_16KB = 0xf /* 0xF --> 16KB */
-};
+#define GLB_EM_0KB 0x0 /* 0x0 --> 0KB */
+#define GLB_EM_8KB 0x3 /* 0x3 --> 8KB */
+#define GLB_EM_16KB 0xF /* 0xF --> 16KB */
/* GLB RTC clock type definition */
-enum glb_mtimer_clk_e
-{
- GLB_MTIMER_CLK_BCLK, /* BUS clock */
- GLB_MTIMER_CLK_32K /* 32KHz */
-};
+#define GLB_MTIMER_CLK_BCLK 0 /* BUS clock */
+#define GLB_MTIMER_CLK_32K 1 /* 32KHz */
/* GLB ADC clock type definition */
-enum glb_adc_clk_e
-{
- GLB_ADC_CLK_96M, /* use 96M as ADC clock */
- GLB_ADC_CLK_XCLK /* use XCLK as ADC clock */
-};
+#define GLB_ADC_CLK_96M 0 /* use 96M as ADC clock */
+#define GLB_ADC_CLK_XCLK 1 /* use XCLK as ADC clock */
/* GLB DAC clock type definition */
-enum glb_dac_clk_e
-{
- GLB_DAC_CLK_32M, /* use 32M as DAC clock */
- GLB_DAC_CLK_XCLK /* use XCLK as DAC clock */
-};
+#define GLB_DAC_CLK_32M 0 /* use 32M as DAC clock */
+#define GLB_DAC_CLK_XCLK 1 /* use XCLK as DAC clock */
/* GLB DIG clock source select type definition */
-enum glb_dig_clk_e
-{
- GLB_DIG_CLK_PLL_32M, /* select PLL 32M as DIG clock source */
- GLB_DIG_CLK_XCLK /* select XCLK as DIG clock source */
-};
+#define GLB_DIG_CLK_PLL_32M 0 /* select PLL 32M as DIG clock source */
+#define GLB_DIG_CLK_XCLK 1 /* select XCLK as DIG clock source */
/* GLB 512K clock out select type definition */
-enum glb_512k_clk_out_e
-{
- GLB_512K_CLK_OUT_512K, /* select 512K clock out */
- GLB_512K_CLK_OUT_256K, /* select 256K clock out */
- GLB_512K_CLK_OUT_128K /* select 128K clock out */
-};
+#define GLB_512K_CLK_OUT_512K 0 /* select 512K clock out */
+#define GLB_512K_CLK_OUT_256K 1 /* select 256K clock out */
+#define GLB_512K_CLK_OUT_128K 2 /* select 128K clock out */
/* GLB BT bandwidth type definition */
-enum glb_bt_bandwidth_e
-{
- GLB_BT_BANDWIDTH_1M, /* BT bandwidth 1MHz */
- GLB_BT_BANDWIDTH_2M /* BT bandwidth 2MHz */
-};
+#define GLB_BT_BANDWIDTH_1M 0 /* BT bandwidth 1MHz */
+#define GLB_BT_BANDWIDTH_2M 1 /* BT bandwidth 2MHz */
/* GLB UART signal type definition */
-enum glb_uart_sig_e
-{
- GLB_UART_SIG_0, /* UART signal 0 */
- GLB_UART_SIG_1, /* UART signal 1 */
- GLB_UART_SIG_2, /* UART signal 2 */
- GLB_UART_SIG_3, /* UART signal 3 */
- GLB_UART_SIG_4, /* UART signal 4 */
- GLB_UART_SIG_5, /* UART signal 5 */
- GLB_UART_SIG_6, /* UART signal 6 */
- GLB_UART_SIG_7 /* UART signal 7 */
-};
+#define GLB_UART_SIG_0 0 /* UART signal 0 */
+#define GLB_UART_SIG_1 1 /* UART signal 1 */
+#define GLB_UART_SIG_2 2 /* UART signal 2 */
+#define GLB_UART_SIG_3 3 /* UART signal 3 */
+#define GLB_UART_SIG_4 4 /* UART signal 4 */
+#define GLB_UART_SIG_5 5 /* UART signal 5 */
+#define GLB_UART_SIG_6 6 /* UART signal 6 */
+#define GLB_UART_SIG_7 7 /* UART signal 7 */
/* GLB UART signal function type definition */
-enum glb_uart_sig_fun_e
-{
- GLB_UART_SIG_FUN_UART0_RTS, /* UART funtion: UART 0 RTS */
- GLB_UART_SIG_FUN_UART0_CTS, /* UART funtion: UART 0 CTS */
- GLB_UART_SIG_FUN_UART0_TXD, /* UART funtion: UART 0 TXD */
- GLB_UART_SIG_FUN_UART0_RXD, /* UART funtion: UART 0 RXD */
- GLB_UART_SIG_FUN_UART1_RTS, /* UART funtion: UART 1 RTS */
- GLB_UART_SIG_FUN_UART1_CTS, /* UART funtion: UART 1 CTS */
- GLB_UART_SIG_FUN_UART1_TXD, /* UART funtion: UART 1 TXD */
- GLB_UART_SIG_FUN_UART1_RXD /* UART funtion: UART 1 RXD */
-};
+#define GLB_UART_SIG_FUN_UART0_RTS 0 /* UART funtion: UART 0 RTS */
+#define GLB_UART_SIG_FUN_UART0_CTS 1 /* UART funtion: UART 0 CTS */
+#define GLB_UART_SIG_FUN_UART0_TXD 2 /* UART funtion: UART 0 TXD */
+#define GLB_UART_SIG_FUN_UART0_RXD 3 /* UART funtion: UART 0 RXD */
+#define GLB_UART_SIG_FUN_UART1_RTS 4 /* UART funtion: UART 1 RTS */
+#define GLB_UART_SIG_FUN_UART1_CTS 5 /* UART funtion: UART 1 CTS */
+#define GLB_UART_SIG_FUN_UART1_TXD 6 /* UART funtion: UART 1 TXD */
+#define GLB_UART_SIG_FUN_UART1_RXD 7 /* UART funtion: UART 1 RXD */
/* GLB GPIO real mode type definition */
-enum glb_gpio_real_mode_e
-{
- /* GPIO real function is reg_gpio_x_func_sel */
+#define GLB_GPIO_REAL_MODE_REG \
+ 0 /* GPIO real function is reg_gpio_x_func_sel */
- GLB_GPIO_REAL_MODE_REG = 0x0,
- GLB_GPIO_REAL_MODE_SDIO = 0x1, /* GPIO real function is SDIO */
- GLB_GPIO_REAL_MODE_RF = 0xc, /* GPIO real function is RF */
- GLB_GPIO_REAL_MODE_JTAG = 0xe, /* GPIO real function is JTAG */
- GLB_GPIO_REAL_MODE_CCI = 0xf /* GPIO real function is CCI */
-};
+#define GLB_GPIO_REAL_MODE_SDIO 1 /* GPIO real function is SDIO */
+#define GLB_GPIO_REAL_MODE_RF 2 /* GPIO real function is RF */
+#define GLB_GPIO_REAL_MODE_JTAG 3 /* GPIO real function is JTAG */
+#define GLB_GPIO_REAL_MODE_CCI 4 /* GPIO real function is CCI */
/* GLB GPIO interrupt trigger mode type definition */
-enum glb_gpio_int_trig_e
-{
- GLB_GPIO_INT_TRIG_NEG_PULSE, /* GPIO negedge pulse trigger interrupt */
- GLB_GPIO_INT_TRIG_POS_PULSE, /* GPIO posedge pulse trigger interrupt */
-
- /* GPIO negedge level trigger interrupt (32k 3T) */
+#define GLB_GPIO_INT_TRIG_NEG_PULSE \
+ 0 /* GPIO negedge pulse trigger interrupt */
- GLB_GPIO_INT_TRIG_NEG_LEVEL,
+#define GLB_GPIO_INT_TRIG_POS_PULSE \
+ 1 /* GPIO posedge pulse trigger interrupt */
- /* GPIO posedge level trigger interrupt (32k 3T) */
+#define GLB_GPIO_INT_TRIG_NEG_LEVEL \
+ 2 /* GPIO negedge level trigger interrupt (32k 3T) */
- GLB_GPIO_INT_TRIG_POS_LEVEL
-};
+#define GLB_GPIO_INT_TRIG_POS_LEVEL \
+ 3 /* GPIO posedge level trigger interrupt (32k 3T) */
/* GLB GPIO interrupt control mode type definition */
-enum glb_gpio_int_control_e
-{
- GLB_GPIO_INT_CONTROL_SYNC, /* GPIO interrupt sync mode */
- GLB_GPIO_INT_CONTROL_ASYNC /* GPIO interrupt async mode */
-};
+#define GLB_GPIO_INT_CONTROL_SYNC 0 /* GPIO interrupt sync mode */
+#define GLB_GPIO_INT_CONTROL_ASYNC 1 /* GPIO interrupt async mode */
/* PLL XTAL type definition */
-enum glb_pll_xtal_e
-{
- GLB_PLL_XTAL_NONE, /* XTAL is none */
- GLB_PLL_XTAL_24M, /* XTAL is 24M */
- GLB_PLL_XTAL_32M, /* XTAL is 32M */
- GLB_PLL_XTAL_38P4M, /* XTAL is 38.4M */
- GLB_PLL_XTAL_40M, /* XTAL is 40M */
- GLB_PLL_XTAL_26M, /* XTAL is 26M */
- GLB_PLL_XTAL_RC32M /* XTAL is RC32M */
-};
+#define GLB_PLL_XTAL_NONE 0 /* XTAL is none */
+#define GLB_PLL_XTAL_24M 1 /* XTAL is 24M */
+#define GLB_PLL_XTAL_32M 2 /* XTAL is 32M */
+#define GLB_PLL_XTAL_38P4M 3 /* XTAL is 38.4M */
+#define GLB_PLL_XTAL_40M 4 /* XTAL is 40M */
+#define GLB_PLL_XTAL_26M 5 /* XTAL is 26M */
+#define GLB_PLL_XTAL_RC32M 6 /* XTAL is RC32M */
/* PLL output clock type definition */
-enum glb_pll_clk_e
-{
- GLB_PLL_CLK_480M, /* PLL output clock:480M */
- GLB_PLL_CLK_240M, /* PLL output clock:240M */
- GLB_PLL_CLK_192M, /* PLL output clock:192M */
- GLB_PLL_CLK_160M, /* PLL output clock:160M */
- GLB_PLL_CLK_120M, /* PLL output clock:120M */
- GLB_PLL_CLK_96M, /* PLL output clock:96M */
- GLB_PLL_CLK_80M, /* PLL output clock:80M */
- GLB_PLL_CLK_48M, /* PLL output clock:48M */
- GLB_PLL_CLK_32M /* PLL output clock:32M */
-};
-
-struct glb_reg_s
-{
- /* 0x0 : clk_cfg0 */
-
- union
- {
- struct
- {
- uint32_t reg_pll_en : 1; /* [ 0], r/w, 0x1 */
- uint32_t reg_fclk_en : 1; /* [ 1], r/w, 0x1 */
- uint32_t reg_hclk_en : 1; /* [ 2], r/w, 0x1 */
- uint32_t reg_bclk_en : 1; /* [ 3], r/w, 0x1 */
- uint32_t reg_pll_sel : 2; /* [ 5: 4], r/w, 0x0 */
- uint32_t hbn_root_clk_sel : 2; /* [ 7: 6], r, 0x0 */
- uint32_t reg_hclk_div : 8; /* [15: 8], r/w, 0x0 */
- uint32_t reg_bclk_div : 8; /* [23:16], r/w, 0x0 */
- uint32_t fclk_sw_state : 3; /* [26:24], r, 0x0 */
- uint32_t chip_rdy : 1; /* [ 27], r, 0x0 */
- uint32_t glb_id : 4; /* [31:28], r, 0x6 */
- } bf;
- uint32_t word;
- } clk_cfg0;
-
- /* 0x4 : clk_cfg1 */
-
- union
- {
- struct
- {
- uint32_t wifi_mac_core_div : 4; /* [ 3: 0], r/w, 0x1 */
- uint32_t wifi_mac_wt_div : 4; /* [ 7: 4], r/w, 0x0 */
- uint32_t reserved_8_15 : 8; /* [15: 8], rsvd, 0x0 */
- uint32_t ble_clk_sel : 6; /* [21:16], r/w, 0x10 */
- uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
- uint32_t ble_en : 1; /* [ 24], r/w, 0x1 */
- uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */
- } bf;
- uint32_t word;
- } clk_cfg1;
-
- /* 0x8 : clk_cfg2 */
-
- union
- {
- struct
- {
- uint32_t uart_clk_div : 3; /* [ 2: 0], r/w, 0x7 */
- uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
- uint32_t uart_clk_en : 1; /* [ 4], r/w, 0x1 */
- uint32_t reserved_5_6 : 2; /* [ 6: 5], rsvd, 0x0 */
- uint32_t hbn_uart_clk_sel : 1; /* [ 7], r, 0x0 */
- uint32_t sf_clk_div : 3; /* [10: 8], r/w, 0x3 */
- uint32_t sf_clk_en : 1; /* [ 11], r/w, 0x1 */
- uint32_t sf_clk_sel : 2; /* [13:12], r/w, 0x2 */
- uint32_t sf_clk_sel2 : 2; /* [15:14], r/w, 0x0 */
- uint32_t ir_clk_div : 6; /* [21:16], r/w, 0xf */
- uint32_t reserved_22 : 1; /* [ 22], rsvd, 0x0 */
- uint32_t ir_clk_en : 1; /* [ 23], r/w, 0x1 */
- uint32_t dma_clk_en : 8; /* [31:24], r/w, 0xff */
- } bf;
- uint32_t word;
- } clk_cfg2;
-
- /* 0xC : clk_cfg3 */
-
- union
- {
- struct
- {
- uint32_t spi_clk_div : 5; /* [ 4: 0], r/w, 0x3 */
- uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */
- uint32_t spi_clk_en : 1; /* [ 8], r/w, 0x1 */
- uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */
- uint32_t i2c_clk_div : 8; /* [23:16], r/w, 0xff */
- uint32_t i2c_clk_en : 1; /* [ 24], r/w, 0x1 */
- uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */
- } bf;
- uint32_t word;
- } clk_cfg3;
-
- /* 0x10 : swrst_cfg0 */
-
- union
- {
- struct
- {
- uint32_t swrst_s00 : 1; /* [ 0], r/w, 0x0 */
- uint32_t swrst_s01 : 1; /* [ 1], r/w, 0x0 */
- uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */
- uint32_t swrst_s20 : 1; /* [ 4], r/w, 0x0 */
- uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */
- uint32_t swrst_s30 : 1; /* [ 8], r/w, 0x0 */
- uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */
- } bf;
- uint32_t word;
- } swrst_cfg0;
-
- /* 0x14 : swrst_cfg1 */
-
- union
- {
- struct
- {
- uint32_t swrst_s10 : 1; /* [ 0], r/w, 0x0 */
- uint32_t swrst_s11 : 1; /* [ 1], r/w, 0x0 */
- uint32_t swrst_s12 : 1; /* [ 2], r/w, 0x0 */
- uint32_t swrst_s13 : 1; /* [ 3], r/w, 0x0 */
- uint32_t swrst_s14 : 1; /* [ 4], r/w, 0x0 */
- uint32_t swrst_s15 : 1; /* [ 5], r/w, 0x0 */
- uint32_t swrst_s16 : 1; /* [ 6], r/w, 0x0 */
- uint32_t swrst_s17 : 1; /* [ 7], r/w, 0x0 */
- uint32_t swrst_s18 : 1; /* [ 8], r/w, 0x0 */
- uint32_t swrst_s19 : 1; /* [ 9], r/w, 0x0 */
- uint32_t swrst_s1a : 1; /* [ 10], r/w, 0x0 */
- uint32_t swrst_s1b : 1; /* [ 11], r/w, 0x0 */
- uint32_t swrst_s1c : 1; /* [ 12], r/w, 0x0 */
- uint32_t swrst_s1d : 1; /* [ 13], r/w, 0x0 */
- uint32_t swrst_s1e : 1; /* [ 14], r/w, 0x0 */
- uint32_t swrst_s1f : 1; /* [ 15], r/w, 0x0 */
- uint32_t swrst_s1a0 : 1; /* [ 16], r/w, 0x0 */
- uint32_t swrst_s1a1 : 1; /* [ 17], r/w, 0x0 */
- uint32_t swrst_s1a2 : 1; /* [ 18], r/w, 0x0 */
- uint32_t swrst_s1a3 : 1; /* [ 19], r/w, 0x0 */
- uint32_t swrst_s1a4 : 1; /* [ 20], r/w, 0x0 */
- uint32_t swrst_s1a5 : 1; /* [ 21], r/w, 0x0 */
- uint32_t swrst_s1a6 : 1; /* [ 22], r/w, 0x0 */
- uint32_t swrst_s1a7 : 1; /* [ 23], r/w, 0x0 */
- uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */
- } bf;
- uint32_t word;
- } swrst_cfg1;
-
- /* 0x18 : swrst_cfg2 */
-
- union
- {
- struct
- {
- uint32_t reg_ctrl_pwron_rst : 1; /* [ 0], r/w, 0x0 */
- uint32_t reg_ctrl_cpu_reset : 1; /* [ 1], r/w, 0x0 */
- uint32_t reg_ctrl_sys_reset : 1; /* [ 2], r/w, 0x0 */
- uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
- uint32_t reg_ctrl_reset_dummy : 4; /* [ 7: 4], r/w, 0x0 */
- uint32_t reserved_8_23 : 16; /* [23: 8], rsvd, 0x0 */
- uint32_t pka_clk_sel : 1; /* [ 24], r/w, 0x0 */
- uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */
- } bf;
- uint32_t word;
- } swrst_cfg2;
-
- /* 0x1C : swrst_cfg3 */
-
- union
- {
- struct
- {
- uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
- } bf;
- uint32_t word;
- } swrst_cfg3;
-
- /* 0x20 : cgen_cfg0 */
-
- union
- {
- struct
- {
- uint32_t cgen_m : 8; /* [ 7: 0], r/w, 0xff */
- uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
... 5787 lines suppressed ...