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Posted to commits@nuttx.apache.org by da...@apache.org on 2020/09/16 13:57:39 UTC
[incubator-nuttx] branch master updated (5fec619 -> 1475309)
This is an automated email from the ASF dual-hosted git repository.
davids5 pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git.
from 5fec619 boards: spresense: Update rndis/defconfig
new bf7399a arch: Initialize idle thread stack information
new 1475309 Fix nxstyle warning
The 2 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
TODO | 55 ++++------------------
arch/arm/src/arm/arm_assert.c | 12 +----
arch/arm/src/arm/arm_initialstate.c | 20 ++++----
arch/arm/src/armv6-m/arm_assert.c | 12 +----
arch/arm/src/armv6-m/arm_initialstate.c | 20 ++++----
arch/arm/src/armv7-a/arm_assert.c | 12 +----
arch/arm/src/armv7-a/arm_initialstate.c | 8 ++++
arch/arm/src/armv7-m/arm_assert.c | 12 +----
arch/arm/src/armv7-m/arm_initialstate.c | 8 ++++
arch/arm/src/armv7-r/arm_assert.c | 12 +----
arch/arm/src/armv7-r/arm_initialstate.c | 20 ++++----
arch/arm/src/armv8-m/arm_assert.c | 12 +----
arch/arm/src/armv8-m/arm_initialstate.c | 8 ++++
arch/arm/src/common/arm_usestack.c | 7 ++-
arch/arm/src/efm32/efm32_start.c | 8 ++--
arch/arm/src/efm32/efm32_start.h | 18 +------
arch/arm/src/imxrt/imxrt_start.c | 3 +-
arch/arm/src/imxrt/imxrt_start.h | 11 -----
arch/arm/src/kinetis/kinetis_start.c | 14 +++---
arch/arm/src/kinetis/kinetis_start.h | 16 -------
arch/arm/src/lc823450/lc823450_start.h | 16 -------
arch/arm/src/lpc17xx_40xx/lpc17_40_start.c | 9 ++--
arch/arm/src/lpc17xx_40xx/lpc17_40_start.h | 24 ++--------
arch/arm/src/lpc54xx/lpc54_start.h | 15 ------
arch/arm/src/max326xx/max326_start.h | 15 ------
arch/arm/src/nrf52/nrf52_start.h | 15 ------
arch/arm/src/s32k1xx/s32k1xx_start.h | 11 -----
arch/arm/src/sam34/sam_start.c | 9 ++--
arch/arm/src/sam34/sam_start.h | 16 -------
arch/arm/src/samd5e5/sam_start.c | 9 ++--
arch/arm/src/samd5e5/sam_start.h | 16 -------
arch/arm/src/samv7/sam_start.c | 14 +++---
arch/arm/src/samv7/sam_start.h | 27 -----------
arch/arm/src/stm32/stm32_start.c | 9 ++--
arch/arm/src/stm32/stm32_start.h | 16 -------
arch/arm/src/stm32f7/stm32_start.c | 13 ++---
arch/arm/src/stm32f7/stm32_start.h | 15 ------
arch/arm/src/stm32h7/stm32_start.c | 13 ++---
arch/arm/src/stm32h7/stm32_start.h | 15 ------
arch/arm/src/stm32l4/stm32l4_start.c | 13 ++---
arch/arm/src/tiva/tiva_start.h | 18 +------
arch/arm/src/tms570/tms570_boot.h | 27 -----------
arch/avr/src/avr/up_dumpstate.c | 12 +----
arch/avr/src/avr/up_initialstate.c | 8 ++++
arch/avr/src/avr/up_usestack.c | 13 ++---
arch/avr/src/avr32/up_dumpstate.c | 12 +----
arch/avr/src/avr32/up_initialstate.c | 20 ++++----
arch/avr/src/avr32/up_usestack.c | 13 ++---
arch/hc/src/common/up_usestack.c | 19 ++++----
arch/hc/src/m9s12/m9s12_assert.c | 12 +----
arch/hc/src/m9s12/m9s12_initialstate.c | 22 ++++-----
arch/mips/src/common/mips_usestack.c | 19 ++++----
arch/mips/src/mips32/mips_dumpstate.c | 12 +----
arch/mips/src/mips32/mips_initialstate.c | 8 ++++
arch/misoc/src/lm32/Make.defs | 2 +-
arch/misoc/src/lm32/lm32_dumpstate.c | 12 +----
arch/misoc/src/lm32/lm32_initialstate.c | 20 ++++----
.../src/lm32/lm32_usestack.c} | 38 ++++++++-------
arch/misoc/src/minerva/Make.defs | 2 +-
arch/misoc/src/minerva/minerva_dumpstate.c | 12 +----
arch/misoc/src/minerva/minerva_initialstate.c | 8 ++++
.../src/minerva/minerva_usestack.c} | 38 ++++++++-------
arch/or1k/src/common/up_assert.c | 12 +----
arch/or1k/src/common/up_initialstate.c | 8 ++++
.../src/common/up_usestack.c} | 38 ++++++++-------
arch/or1k/src/mor1kx/Make.defs | 1 +
arch/renesas/src/common/up_usestack.c | 19 ++++----
arch/renesas/src/m16c/chip.h | 2 +-
arch/renesas/src/m16c/m16c_dumpstate.c | 12 +----
arch/renesas/src/m16c/m16c_initialstate.c | 14 +++++-
arch/renesas/src/rx65n/rx65n_dumpstate.c | 12 +----
arch/renesas/src/rx65n/rx65n_initialstate.c | 8 ++++
arch/renesas/src/sh1/sh1_dumpstate.c | 12 +----
arch/renesas/src/sh1/sh1_initialstate.c | 16 +++----
arch/risc-v/src/common/riscv_initialize.c | 9 ----
arch/risc-v/src/common/riscv_usestack.c | 17 +++----
arch/risc-v/src/rv32im/riscv_assert.c | 12 +----
arch/risc-v/src/rv32im/riscv_initialstate.c | 8 ++++
arch/risc-v/src/rv64gc/riscv_assert.c | 12 +----
arch/risc-v/src/rv64gc/riscv_initialstate.c | 8 ++++
arch/sim/src/sim/up_initialstate.c | 6 +++
arch/sim/src/sim/up_usestack.c | 9 ++--
arch/x86/src/common/up_assert.c | 12 +----
arch/x86/src/i486/up_initialstate.c | 20 ++++----
arch/x86/src/i486/up_usestack.c | 19 ++++----
arch/x86_64/src/common/up_assert.c | 14 ++----
arch/x86_64/src/common/up_initialize.c | 6 ---
arch/x86_64/src/intel64/up_initialstate.c | 20 ++++----
arch/x86_64/src/intel64/up_usestack.c | 19 ++++----
arch/xtensa/src/common/xtensa_dumpstate.c | 12 +----
arch/xtensa/src/common/xtensa_initialstate.c | 7 +++
arch/xtensa/src/common/xtensa_usestack.c | 9 ++--
arch/z16/src/common/z16_usestack.c | 19 ++++----
arch/z80/src/common/z80_stackframe.c | 4 +-
arch/z80/src/common/z80_usestack.c | 19 ++++----
arch/z80/src/z180/z180_initialstate.c | 20 ++++----
arch/z80/src/z80/z80_initialstate.c | 20 ++++----
boards/arm/cxd56xx/common/src/cxd56_crashdump.c | 12 +----
boards/arm/stm32/nucleo-f429zi/src/stm32_bbsram.c | 12 +----
boards/arm/stm32f7/nucleo-144/src/stm32_bbsram.c | 14 ++----
.../renesas/rx65n/rx65n-grrose/src/rx65n_sbram.c | 12 +----
.../renesas/rx65n/rx65n-rsk2mb/src/rx65n_sbram.c | 12 +----
102 files changed, 498 insertions(+), 944 deletions(-)
copy arch/{z80/src/common/z80_usestack.c => misoc/src/lm32/lm32_usestack.c} (81%)
copy arch/{z80/src/common/z80_usestack.c => misoc/src/minerva/minerva_usestack.c} (81%)
copy arch/{z80/src/common/z80_usestack.c => or1k/src/common/up_usestack.c} (81%)
[incubator-nuttx] 02/02: Fix nxstyle warning
Posted by da...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
davids5 pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 1475309c5b1c704e0b95c523e276996d6e601bd6
Author: Xiang Xiao <xi...@xiaomi.com>
AuthorDate: Sun Jul 5 15:10:40 2020 +0800
Fix nxstyle warning
Signed-off-by: Xiang Xiao <xi...@xiaomi.com>
---
arch/arm/src/efm32/efm32_start.c | 8 ++++----
arch/arm/src/efm32/efm32_start.h | 2 +-
arch/arm/src/imxrt/imxrt_start.c | 3 ++-
arch/arm/src/kinetis/kinetis_start.c | 14 +++++++-------
arch/arm/src/lpc17xx_40xx/lpc17_40_start.c | 9 +++++----
arch/arm/src/lpc17xx_40xx/lpc17_40_start.h | 8 ++++----
arch/arm/src/sam34/sam_start.c | 9 +++++----
arch/arm/src/samd5e5/sam_start.c | 9 +++++----
arch/arm/src/samv7/sam_start.c | 14 ++++++++------
arch/arm/src/stm32/stm32_start.c | 9 +++++----
arch/arm/src/stm32f7/stm32_start.c | 13 +++++++------
arch/arm/src/stm32h7/stm32_start.c | 13 +++++++------
arch/arm/src/stm32l4/stm32l4_start.c | 13 +++++++------
arch/arm/src/tiva/tiva_start.h | 2 +-
arch/hc/src/m9s12/m9s12_initialstate.c | 2 +-
arch/renesas/src/m16c/chip.h | 1 +
arch/renesas/src/m16c/m16c_initialstate.c | 6 ++++--
boards/arm/stm32f7/nucleo-144/src/stm32_bbsram.c | 2 +-
18 files changed, 75 insertions(+), 62 deletions(-)
diff --git a/arch/arm/src/efm32/efm32_start.c b/arch/arm/src/efm32/efm32_start.c
index c683f11..a38e35b 100644
--- a/arch/arm/src/efm32/efm32_start.c
+++ b/arch/arm/src/efm32/efm32_start.c
@@ -98,7 +98,7 @@ static inline void efm32_fpuconfig(void);
#endif
#ifdef CONFIG_STACK_COLORATION
static void go_nx_start(void *pv, unsigned int nbytes)
- __attribute__ ((naked,no_instrument_function,noreturn));
+ __attribute__ ((naked, no_instrument_function, noreturn));
#endif
/****************************************************************************
@@ -141,7 +141,7 @@ static void go_nx_start(void *pv, unsigned int nbytes)
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
- * Software must not change the value of the ASPEN bit or LSPEN bit while either:
+ * Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
@@ -175,7 +175,7 @@ static inline void efm32_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
- regval |= ((3 << (2*10)) | (3 << (2*11)));
+ regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@@ -205,7 +205,7 @@ static inline void efm32_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
- regval |= ((3 << (2*10)) | (3 << (2*11)));
+ regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
diff --git a/arch/arm/src/efm32/efm32_start.h b/arch/arm/src/efm32/efm32_start.h
index 693f3a4..730618b 100644
--- a/arch/arm/src/efm32/efm32_start.h
+++ b/arch/arm/src/efm32/efm32_start.h
@@ -43,7 +43,7 @@
#include <nuttx/config.h>
/****************************************************************************
- * Public Functions
+ * Public Function Prototypes
****************************************************************************/
/****************************************************************************
diff --git a/arch/arm/src/imxrt/imxrt_start.c b/arch/arm/src/imxrt/imxrt_start.c
index 5e2c181..d661adf 100644
--- a/arch/arm/src/imxrt/imxrt_start.c
+++ b/arch/arm/src/imxrt/imxrt_start.c
@@ -305,7 +305,8 @@ void __start(void)
#ifdef CONFIG_ARMV7M_STACKCHECK
/* Set the stack limit before we attempt to call any functions */
- __asm__ volatile ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) : );
+ __asm__ volatile("sub r10, sp, %0" : :
+ "r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :);
#endif
#ifdef CONFIG_BOOT_RUNFROMISRAM
diff --git a/arch/arm/src/kinetis/kinetis_start.c b/arch/arm/src/kinetis/kinetis_start.c
index c7d9c63..feb2b6e 100644
--- a/arch/arm/src/kinetis/kinetis_start.c
+++ b/arch/arm/src/kinetis/kinetis_start.c
@@ -75,8 +75,8 @@ static void go_nx_start(void *pv, unsigned int nbytes)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
-/* Memory Map ***************************************************************/
-/*
+
+/* Memory Map ***************************************************************
* 0x0000:0000 - Beginning of the internal FLASH. Address of vectors.
* Mapped as boot memory address 0x0000:0000 at reset.
* 0x07ff:ffff - End of flash region (assuming the max of 2MiB of FLASH).
@@ -116,7 +116,6 @@ const uintptr_t g_idle_topstack = HEAP_BASE;
* Private Functions
****************************************************************************/
-
#ifdef CONFIG_ARMV7M_STACKCHECK
/* we need to get r10 set before we can allow instrumentation calls */
@@ -139,7 +138,7 @@ void __start(void) __attribute__ ((no_instrument_function));
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
- * Software must not change the value of the ASPEN bit or LSPEN bit while either:
+ * Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
@@ -173,7 +172,7 @@ static inline void kinetis_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
- regval |= ((3 << (2*10)) | (3 << (2*11)));
+ regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@@ -203,7 +202,7 @@ static inline void kinetis_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
- regval |= ((3 << (2*10)) | (3 << (2*11)));
+ regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@@ -276,7 +275,8 @@ void __start(void)
#ifdef CONFIG_ARMV7M_STACKCHECK
/* Set the stack limit before we attempt to call any functions */
- __asm__ volatile ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) : );
+ __asm__ volatile("sub r10, sp, %0" : :
+ "r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :);
#endif
/* Disable the watchdog timer */
diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_start.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_start.c
index 1b13e3d..6c5096d 100644
--- a/arch/arm/src/lpc17xx_40xx/lpc17_40_start.c
+++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_start.c
@@ -121,7 +121,7 @@ const uintptr_t g_idle_topstack = HEAP_BASE;
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
- * Software must not change the value of the ASPEN bit or LSPEN bit while either:
+ * Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
@@ -155,7 +155,7 @@ static inline void lpc17_40_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
- regval |= ((3 << (2*10)) | (3 << (2*11)));
+ regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@@ -185,7 +185,7 @@ static inline void lpc17_40_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
- regval |= ((3 << (2*10)) | (3 << (2*11)));
+ regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@@ -225,7 +225,8 @@ void __start(void)
#ifdef CONFIG_ARMV7M_STACKCHECK
/* Set the stack limit before we attempt to call any functions */
- __asm__ volatile ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) : );
+ __asm__ volatile("sub r10, sp, %0" : :
+ "r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :);
#endif
/* Configure the uart so that we can get debug output as soon as possible */
diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_start.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_start.h
index 94f29aa..6180e4b 100644
--- a/arch/arm/src/lpc17xx_40xx/lpc17_40_start.h
+++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_start.h
@@ -50,10 +50,10 @@
* Name: lpc17_40_boardinitialize
*
* Description:
- * All LPC17xx/LPC40xx architectures must provide the following entry point. This entry
- * point is called early in the initialization -- after clocking and memory have
- * been configured but before caches have been enabled and before any devices have
- * been initialized.
+ * All LPC17xx/LPC40xx architectures must provide the following entry point. This
+ * entry point is called early in the initialization -- after clocking and memory
+ * have been configured but before caches have been enabled and before any devices
+ * have been initialized.
*
************************************************************************************/
diff --git a/arch/arm/src/sam34/sam_start.c b/arch/arm/src/sam34/sam_start.c
index 7afabe3..52275d3 100644
--- a/arch/arm/src/sam34/sam_start.c
+++ b/arch/arm/src/sam34/sam_start.c
@@ -138,7 +138,7 @@ void __start(void) __attribute__ ((no_instrument_function));
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
- * Software must not change the value of the ASPEN bit or LSPEN bit while either:
+ * Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
@@ -172,7 +172,7 @@ static inline void sam_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
- regval |= ((3 << (2*10)) | (3 << (2*11)));
+ regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@@ -202,7 +202,7 @@ static inline void sam_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
- regval |= ((3 << (2*10)) | (3 << (2*11)));
+ regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@@ -280,7 +280,8 @@ void __start(void)
#ifdef CONFIG_ARMV7M_STACKCHECK
/* Set the stack limit before we attempt to call any functions */
- __asm__ volatile ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) : );
+ __asm__ volatile("sub r10, sp, %0" : :
+ "r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :);
#endif
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
diff --git a/arch/arm/src/samd5e5/sam_start.c b/arch/arm/src/samd5e5/sam_start.c
index c3bdc2f..58d9677 100644
--- a/arch/arm/src/samd5e5/sam_start.c
+++ b/arch/arm/src/samd5e5/sam_start.c
@@ -139,7 +139,7 @@ void __start(void) __attribute__ ((no_instrument_function));
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
- * Software must not change the value of the ASPEN bit or LSPEN bit while either:
+ * Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
@@ -173,7 +173,7 @@ static inline void sam_fpu_configure(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
- regval |= ((3 << (2*10)) | (3 << (2*11)));
+ regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@@ -203,7 +203,7 @@ static inline void sam_fpu_configure(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
- regval |= ((3 << (2*10)) | (3 << (2*11)));
+ regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@@ -276,7 +276,8 @@ void __start(void)
#ifdef CONFIG_ARMV7M_STACKCHECK
/* Set the stack limit before we attempt to call any functions */
- __asm__ volatile ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) : );
+ __asm__ volatile("sub r10, sp, %0" : :
+ "r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :);
#endif
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
diff --git a/arch/arm/src/samv7/sam_start.c b/arch/arm/src/samv7/sam_start.c
index d11d876..3d54b4d 100644
--- a/arch/arm/src/samv7/sam_start.c
+++ b/arch/arm/src/samv7/sam_start.c
@@ -61,8 +61,9 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
-/* Memory Map ***************************************************************/
-/* 0x0400:0000 - Beginning of the internal FLASH. Address of vectors.
+
+/* Memory Map ***************************************************************
+ * 0x0400:0000 - Beginning of the internal FLASH. Address of vectors.
* Mapped as boot memory address 0x0000:0000 at reset.
* 0x041f:ffff - End of flash region (assuming the max of 2MiB of FLASH).
* 0x2000:0000 - Start of internal SRAM and start of .data (_sdata)
@@ -132,7 +133,7 @@ void __start(void) __attribute__ ((no_instrument_function));
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
- * Software must not change the value of the ASPEN bit or LSPEN bit while either:
+ * Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
@@ -166,7 +167,7 @@ static inline void sam_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
- regval |= ((3 << (2*10)) | (3 << (2*11)));
+ regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@@ -196,7 +197,7 @@ static inline void sam_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
- regval |= ((3 << (2*10)) | (3 << (2*11)));
+ regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@@ -316,7 +317,8 @@ void __start(void)
#ifdef CONFIG_ARMV7M_STACKCHECK
/* Set the stack limit before we attempt to call any functions */
- __asm__ volatile ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) : );
+ __asm__ volatile("sub r10, sp, %0" : :
+ "r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :);
#endif
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
diff --git a/arch/arm/src/stm32/stm32_start.c b/arch/arm/src/stm32/stm32_start.c
index bd53c0e..36af088 100644
--- a/arch/arm/src/stm32/stm32_start.c
+++ b/arch/arm/src/stm32/stm32_start.c
@@ -140,7 +140,7 @@ void __start(void) __attribute__ ((no_instrument_function));
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
- * Software must not change the value of the ASPEN bit or LSPEN bit while either:
+ * Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
@@ -174,7 +174,7 @@ static inline void stm32_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
- regval |= ((3 << (2*10)) | (3 << (2*11)));
+ regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@@ -204,7 +204,7 @@ static inline void stm32_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
- regval |= ((3 << (2*10)) | (3 << (2*11)));
+ regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@@ -275,7 +275,8 @@ void __start(void)
#ifdef CONFIG_ARMV7M_STACKCHECK
/* Set the stack limit before we attempt to call any functions */
- __asm__ volatile ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) : );
+ __asm__ volatile("sub r10, sp, %0" : :
+ "r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :);
#endif
/* Configure the UART so that we can get debug output as soon as possible */
diff --git a/arch/arm/src/stm32f7/stm32_start.c b/arch/arm/src/stm32f7/stm32_start.c
index dc7b033..a13ded6 100644
--- a/arch/arm/src/stm32f7/stm32_start.c
+++ b/arch/arm/src/stm32f7/stm32_start.c
@@ -62,8 +62,8 @@
****************************************************************************/
/* Memory Map ***************************************************************/
-/*
- * 0x0400:0000 - Beginning of the internal FLASH. Address of vectors.
+
+/* 0x0400:0000 - Beginning of the internal FLASH. Address of vectors.
* Mapped as boot memory address 0x0000:0000 at reset.
* 0x041f:ffff - End of flash region (assuming the max of 2MiB of FLASH).
* 0x2000:0000 - Start of internal SRAM and start of .data (_sdata)
@@ -133,7 +133,7 @@ void __start(void) __attribute__ ((no_instrument_function));
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
- * Software must not change the value of the ASPEN bit or LSPEN bit while either:
+ * Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
@@ -167,7 +167,7 @@ static inline void stm32_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
- regval |= ((3 << (2*10)) | (3 << (2*11)));
+ regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@@ -197,7 +197,7 @@ static inline void stm32_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
- regval |= ((3 << (2*10)) | (3 << (2*11)));
+ regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@@ -318,7 +318,8 @@ void __start(void)
#ifdef CONFIG_ARMV7M_STACKCHECK
/* Set the stack limit before we attempt to call any functions */
- __asm__ volatile ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) : );
+ __asm__ volatile("sub r10, sp, %0" : :
+ "r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :);
#endif
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
diff --git a/arch/arm/src/stm32h7/stm32_start.c b/arch/arm/src/stm32h7/stm32_start.c
index a999ca7..7c283d8 100644
--- a/arch/arm/src/stm32h7/stm32_start.c
+++ b/arch/arm/src/stm32h7/stm32_start.c
@@ -62,8 +62,8 @@
****************************************************************************/
/* Memory Map ***************************************************************/
-/*
- * TODO: Fix this
+
+/* TODO: Fix this
* 0x0400:0000 - Beginning of the internal FLASH. Address of vectors.
* Mapped as boot memory address 0x0000:0000 at reset.
* 0x041f:ffff - End of flash region (assuming the max of 2MiB of FLASH).
@@ -148,7 +148,7 @@ void __start(void) __attribute__ ((no_instrument_function));
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
- * Software must not change the value of the ASPEN bit or LSPEN bit while either:
+ * Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
@@ -182,7 +182,7 @@ static inline void stm32_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
- regval |= ((3 << (2*10)) | (3 << (2*11)));
+ regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@@ -212,7 +212,7 @@ static inline void stm32_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
- regval |= ((3 << (2*10)) | (3 << (2*11)));
+ regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@@ -333,7 +333,8 @@ void __start(void)
#ifdef CONFIG_ARMV7M_STACKCHECK
/* Set the stack limit before we attempt to call any functions */
- __asm__ volatile ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) : );
+ __asm__ volatile("sub r10, sp, %0" : :
+ "r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :);
#endif
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
diff --git a/arch/arm/src/stm32l4/stm32l4_start.c b/arch/arm/src/stm32l4/stm32l4_start.c
index c95f435..f51109b 100644
--- a/arch/arm/src/stm32l4/stm32l4_start.c
+++ b/arch/arm/src/stm32l4/stm32l4_start.c
@@ -60,8 +60,8 @@
****************************************************************************/
/* Memory Map ***************************************************************/
-/*
- * 0x0800:0000 - Beginning of the internal FLASH. Address of vectors.
+
+/* 0x0800:0000 - Beginning of the internal FLASH. Address of vectors.
* Mapped as boot memory address 0x0000:0000 at reset.
* 0x080f:ffff - End of flash region (assuming the max of 2MiB of FLASH).
* 0x1000:0000 - Start of internal SRAM2
@@ -148,7 +148,7 @@ void __start(void) __attribute__ ((no_instrument_function));
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
- * Software must not change the value of the ASPEN bit or LSPEN bit while either:
+ * Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
@@ -182,7 +182,7 @@ static inline void stm32l4_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
- regval |= ((3 << (2*10)) | (3 << (2*11)));
+ regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@@ -212,7 +212,7 @@ static inline void stm32l4_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
- regval |= ((3 << (2*10)) | (3 << (2*11)));
+ regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
putreg32(regval, NVIC_CPACR);
}
@@ -283,7 +283,8 @@ void __start(void)
#ifdef CONFIG_ARMV7M_STACKCHECK
/* Set the stack limit before we attempt to call any functions */
- __asm__ volatile ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) : );
+ __asm__ volatile("sub r10, sp, %0" : :
+ "r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :);
#endif
#ifdef CONFIG_STM32L4_SRAM2_INIT
diff --git a/arch/arm/src/tiva/tiva_start.h b/arch/arm/src/tiva/tiva_start.h
index 1a2bb83..a926841 100644
--- a/arch/arm/src/tiva/tiva_start.h
+++ b/arch/arm/src/tiva/tiva_start.h
@@ -43,7 +43,7 @@
#include <nuttx/config.h>
/****************************************************************************
- * Public Functions
+ * Public Function Prototypes
****************************************************************************/
/****************************************************************************
diff --git a/arch/hc/src/m9s12/m9s12_initialstate.c b/arch/hc/src/m9s12/m9s12_initialstate.c
index 2bd6931..4359cb4 100644
--- a/arch/hc/src/m9s12/m9s12_initialstate.c
+++ b/arch/hc/src/m9s12/m9s12_initialstate.c
@@ -111,7 +111,7 @@ void up_initial_state(struct tcb_s *tcb)
# ifdef CONFIG_SUPPRESS_INTERRUPTS
/* Disable STOP, Mask I- and Z- interrupts */
- xcp->regs[REG_CCR] = HCS12_CCR_S|HCS12_CCR_X|HCS12_CCR_I;
+ xcp->regs[REG_CCR] = HCS12_CCR_S | HCS12_CCR_X | HCS12_CCR_I;
# else
/* Disable STOP, Enable I- and Z-interrupts */
diff --git a/arch/renesas/src/m16c/chip.h b/arch/renesas/src/m16c/chip.h
index cc08d4c..3c38278 100644
--- a/arch/renesas/src/m16c/chip.h
+++ b/arch/renesas/src/m16c/chip.h
@@ -62,6 +62,7 @@
/* Bits 8-11: Reserved */
#define M16C_FLG_IPLMASK 0x7000 /* Bits 12:14: Processor interrupt priority level */
/* Bit 15: Reserved */
+
/* Memory Map */
/* Memory-mapped special function registers begin at address 0x00000 */
diff --git a/arch/renesas/src/m16c/m16c_initialstate.c b/arch/renesas/src/m16c/m16c_initialstate.c
index 03953b0..f77d618 100644
--- a/arch/renesas/src/m16c/m16c_initialstate.c
+++ b/arch/renesas/src/m16c/m16c_initialstate.c
@@ -82,7 +82,9 @@ void up_initial_state(FAR struct tcb_s *tcb)
memset(xcp, 0, sizeof(struct xcptcontext));
- /* Offset 0: FLG (bits 12-14) PC (bits 16-19) as would be present by an interrupt */
+ /* Offset 0: FLG (bits 12-14) PC (bits 16-19) as would be present by an
+ * interrupt
+ */
*regs++ = ((M16C_DEFAULT_IPL << 4) | ((uint32_t)tcb->start >> 16));
@@ -101,7 +103,7 @@ void up_initial_state(FAR struct tcb_s *tcb)
/* Offset 18-20: User stack pointer */
- regs = &xcp->regs[REG_SP];
+ regs = &xcp->regs[REG_SP];
*regs++ = (uint32_t)tcb->adj_stack_ptr >> 8; /* Bits 8-15 of SP */
*regs = (uint32_t)tcb->adj_stack_ptr; /* Bits 0-7 of SP */
}
diff --git a/boards/arm/stm32f7/nucleo-144/src/stm32_bbsram.c b/boards/arm/stm32f7/nucleo-144/src/stm32_bbsram.c
index 51589ad..783cf09 100644
--- a/boards/arm/stm32f7/nucleo-144/src/stm32_bbsram.c
+++ b/boards/arm/stm32f7/nucleo-144/src/stm32_bbsram.c
@@ -364,7 +364,7 @@ int stm32_bbsram_int(void)
state = (desc.lastwrite.tv_sec || desc.lastwrite.tv_nsec) ? OK : 1;
syslog(LOG_INFO, "Fault Log info File No %d Length %d flags:0x%02x "
- "state:%d\n", (unsigned int)desc.fileno, (unsigned int) desc.len,
+ "state:%d\n", (unsigned int)desc.fileno, (unsigned int)desc.len,
(unsigned int)desc.flags, state);
if (state == OK)
[incubator-nuttx] 01/02: arch: Initialize idle thread stack
information
Posted by da...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
davids5 pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit bf7399a982b15708bdddcb351390ddb4bfac7eb9
Author: Xiang Xiao <xi...@xiaomi.com>
AuthorDate: Sun Jul 5 13:37:48 2020 +0800
arch: Initialize idle thread stack information
and remove the special handling in the stack dump
Signed-off-by: Xiang Xiao <xi...@xiaomi.com>
Change-Id: Ia1ef9a427bd4c7f6cee9838d0445f29cfaca3998
---
TODO | 55 ++++------------------
arch/arm/src/arm/arm_assert.c | 12 +----
arch/arm/src/arm/arm_initialstate.c | 20 ++++----
arch/arm/src/armv6-m/arm_assert.c | 12 +----
arch/arm/src/armv6-m/arm_initialstate.c | 20 ++++----
arch/arm/src/armv7-a/arm_assert.c | 12 +----
arch/arm/src/armv7-a/arm_initialstate.c | 8 ++++
arch/arm/src/armv7-m/arm_assert.c | 12 +----
arch/arm/src/armv7-m/arm_initialstate.c | 8 ++++
arch/arm/src/armv7-r/arm_assert.c | 12 +----
arch/arm/src/armv7-r/arm_initialstate.c | 20 ++++----
arch/arm/src/armv8-m/arm_assert.c | 12 +----
arch/arm/src/armv8-m/arm_initialstate.c | 8 ++++
arch/arm/src/common/arm_usestack.c | 7 ++-
arch/arm/src/efm32/efm32_start.h | 16 -------
arch/arm/src/imxrt/imxrt_start.h | 11 -----
arch/arm/src/kinetis/kinetis_start.h | 16 -------
arch/arm/src/lc823450/lc823450_start.h | 16 -------
arch/arm/src/lpc17xx_40xx/lpc17_40_start.h | 16 -------
arch/arm/src/lpc54xx/lpc54_start.h | 15 ------
arch/arm/src/max326xx/max326_start.h | 15 ------
arch/arm/src/nrf52/nrf52_start.h | 15 ------
arch/arm/src/s32k1xx/s32k1xx_start.h | 11 -----
arch/arm/src/sam34/sam_start.h | 16 -------
arch/arm/src/samd5e5/sam_start.h | 16 -------
arch/arm/src/samv7/sam_start.h | 27 -----------
arch/arm/src/stm32/stm32_start.h | 16 -------
arch/arm/src/stm32f7/stm32_start.h | 15 ------
arch/arm/src/stm32h7/stm32_start.h | 15 ------
arch/arm/src/tiva/tiva_start.h | 16 -------
arch/arm/src/tms570/tms570_boot.h | 27 -----------
arch/avr/src/avr/up_dumpstate.c | 12 +----
arch/avr/src/avr/up_initialstate.c | 8 ++++
arch/avr/src/avr/up_usestack.c | 13 ++---
arch/avr/src/avr32/up_dumpstate.c | 12 +----
arch/avr/src/avr32/up_initialstate.c | 20 ++++----
arch/avr/src/avr32/up_usestack.c | 13 ++---
arch/hc/src/common/up_usestack.c | 19 ++++----
arch/hc/src/m9s12/m9s12_assert.c | 12 +----
arch/hc/src/m9s12/m9s12_initialstate.c | 20 ++++----
arch/mips/src/common/mips_usestack.c | 19 ++++----
arch/mips/src/mips32/mips_dumpstate.c | 12 +----
arch/mips/src/mips32/mips_initialstate.c | 8 ++++
arch/misoc/src/lm32/Make.defs | 2 +-
arch/misoc/src/lm32/lm32_dumpstate.c | 12 +----
arch/misoc/src/lm32/lm32_initialstate.c | 20 ++++----
.../src/lm32/lm32_usestack.c} | 38 ++++++++-------
arch/misoc/src/minerva/Make.defs | 2 +-
arch/misoc/src/minerva/minerva_dumpstate.c | 12 +----
arch/misoc/src/minerva/minerva_initialstate.c | 8 ++++
.../src/minerva/minerva_usestack.c} | 38 ++++++++-------
arch/or1k/src/common/up_assert.c | 12 +----
arch/or1k/src/common/up_initialstate.c | 8 ++++
.../src/common/up_usestack.c} | 38 ++++++++-------
arch/or1k/src/mor1kx/Make.defs | 1 +
arch/renesas/src/common/up_usestack.c | 19 ++++----
arch/renesas/src/m16c/chip.h | 1 -
arch/renesas/src/m16c/m16c_dumpstate.c | 12 +----
arch/renesas/src/m16c/m16c_initialstate.c | 8 ++++
arch/renesas/src/rx65n/rx65n_dumpstate.c | 12 +----
arch/renesas/src/rx65n/rx65n_initialstate.c | 8 ++++
arch/renesas/src/sh1/sh1_dumpstate.c | 12 +----
arch/renesas/src/sh1/sh1_initialstate.c | 16 +++----
arch/risc-v/src/common/riscv_initialize.c | 9 ----
arch/risc-v/src/common/riscv_usestack.c | 17 +++----
arch/risc-v/src/rv32im/riscv_assert.c | 12 +----
arch/risc-v/src/rv32im/riscv_initialstate.c | 8 ++++
arch/risc-v/src/rv64gc/riscv_assert.c | 12 +----
arch/risc-v/src/rv64gc/riscv_initialstate.c | 8 ++++
arch/sim/src/sim/up_initialstate.c | 6 +++
arch/sim/src/sim/up_usestack.c | 9 ++--
arch/x86/src/common/up_assert.c | 12 +----
arch/x86/src/i486/up_initialstate.c | 20 ++++----
arch/x86/src/i486/up_usestack.c | 19 ++++----
arch/x86_64/src/common/up_assert.c | 14 ++----
arch/x86_64/src/common/up_initialize.c | 6 ---
arch/x86_64/src/intel64/up_initialstate.c | 20 ++++----
arch/x86_64/src/intel64/up_usestack.c | 19 ++++----
arch/xtensa/src/common/xtensa_dumpstate.c | 12 +----
arch/xtensa/src/common/xtensa_initialstate.c | 7 +++
arch/xtensa/src/common/xtensa_usestack.c | 9 ++--
arch/z16/src/common/z16_usestack.c | 19 ++++----
arch/z80/src/common/z80_stackframe.c | 4 +-
arch/z80/src/common/z80_usestack.c | 19 ++++----
arch/z80/src/z180/z180_initialstate.c | 20 ++++----
arch/z80/src/z80/z80_initialstate.c | 20 ++++----
boards/arm/cxd56xx/common/src/cxd56_crashdump.c | 12 +----
boards/arm/stm32/nucleo-f429zi/src/stm32_bbsram.c | 12 +----
boards/arm/stm32f7/nucleo-144/src/stm32_bbsram.c | 12 +----
.../renesas/rx65n/rx65n-grrose/src/rx65n_sbram.c | 12 +----
.../renesas/rx65n/rx65n-rsk2mb/src/rx65n_sbram.c | 12 +----
91 files changed, 423 insertions(+), 882 deletions(-)
diff --git a/TODO b/TODO
index 8fd88f0..e03e408 100644
--- a/TODO
+++ b/TODO
@@ -1,4 +1,4 @@
-NuttX TODO List (Last updated July 2, 2020)
+NuttX TODO List (Last updated July 19, 2020)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This file summarizes known NuttX bugs, limitations, inconsistencies with
@@ -295,49 +295,10 @@ o Task/Scheduler (sched/)
Task: IDLE THREAD TCB SETUP
Description: There are issues with setting IDLE thread stacks:
- 1. One problem is stack-related data in the IDLE threads TCB.
- A solution might be to standardize the use of g_idle_topstack.
- That you could add initialization like this in nx_start:
-
- @@ -344,6 +347,11 @@ void nx_start(void)
- g_idleargv[1] = NULL;
- g_idletcb.argv = g_idleargv;
-
- + /* Set the IDLE task stack size */
- +
- + g_idletcb.cmn.adj_stack_size = CONFIG_IDLETHREAD_STACKSIZE;
- + g_idletcb.cmn.stack_alloc_ptr = (void *)(g_idle_topstack - CONFIG_IDLETHREAD_STACKSIZE);
- +
- /* Then add the idle task's TCB to the head of the ready to run list */
-
- dq_addfirst((FAR dq_entry_t *)&g_idletcb, (FAR dq_queue_t *)&g_readytorun);
-
- The g_idle_topstack variable is available for almost all architectures:
-
- $ find . -name *.h | xargs grep g_idle_top
- ./arm/src/common/up_internal.h:EXTERN const uint32_t g_idle_topstack;
- ./avr/src/avr/avr.h:extern uint16_t g_idle_topstack;
- ./avr/src/avr32/avr32.h:extern uint32_t g_idle_topstack;
- ./hc/src/common/up_internal.h:extern uint16_t g_idle_topstack;
- ./mips/src/common/up_internal.h:extern uint32_t g_idle_topstack;
- ./misoc/src/lm32/lm32.h:extern uint32_t g_idle_topstack;
- ./renesas/src/common/up_internal.h:extern uint32_t g_idle_topstack;
- ./renesas/src/m16c/chip.h:extern uint32_t g_idle_topstack; /* Start of the heap */
- ./risc-v/src/common/up_internal.h:EXTERN uint32_t g_idle_topstack;
- ./x86/src/common/up_internal.h:extern uint32_t g_idle_topstack;
-
- That omits these architectures: sh1, sim, xtensa, z16, z80,
- ez80, and z8. All would have to support this common
- global variable.
-
- Also, the stack itself may be 8-, 16-, or 32-bits wide,
- depending upon the architecture and do have differing
- alignment requirements.
-
- 2. Another problem is colorizing that stack to use with
- stack usage monitoring logic. There is logic in some
- start functions to do this in a function called go_nx_start.
- It is available in these architectures:
+ The problem is colorizing that stack to use with stack usage
+ monitoring logic. There is logic in some start functions to
+ do this in a function called go_nx_start.
+ It is available in these architectures:
./arm/src/efm32/efm32_start.c:static void go_nx_start(void *pv, unsigned int nbytes)
./arm/src/kinetis/kinetis_start.c:static void go_nx_start(void *pv, unsigned int nbytes)
@@ -349,9 +310,9 @@ o Task/Scheduler (sched/)
./arm/src/tms570/tms570_boot.c:static void go_nx_start(void *pv, unsigned int nbytes)
./arm/src/xmc4/xmc4_start.c:static void go_nx_start(void *pv, unsigned int nbytes)
- But no others.
- Status: Open
- Priority: Low, only needed for more complete debug.
+ But no others.
+ Status: Open
+ Priority: Low, only needed for more complete debug.
Title: PRIORITY INHERITANCE WITH SPORADIC SCHEDULER
Description: The sporadic scheduler manages CPU utilization by a task by
diff --git a/arch/arm/src/arm/arm_assert.c b/arch/arm/src/arm/arm_assert.c
index 71e1512..e4f445b 100644
--- a/arch/arm/src/arm/arm_assert.c
+++ b/arch/arm/src/arm/arm_assert.c
@@ -187,16 +187,8 @@ static void up_dumpstate(void)
/* Get the limits on the user stack memory */
- if (rtcb->pid == 0) /* Check for CPU0 IDLE thread */
- {
- ustackbase = g_idle_topstack - 4;
- ustacksize = CONFIG_IDLETHREAD_STACKSIZE;
- }
- else
- {
- ustackbase = (uint32_t)rtcb->adj_stack_ptr;
- ustacksize = (uint32_t)rtcb->adj_stack_size;
- }
+ ustackbase = (uint32_t)rtcb->adj_stack_ptr;
+ ustacksize = (uint32_t)rtcb->adj_stack_size;
/* Get the limits on the interrupt stack memory */
diff --git a/arch/arm/src/arm/arm_initialstate.c b/arch/arm/src/arm/arm_initialstate.c
index d18aa6b..13c9c92 100644
--- a/arch/arm/src/arm/arm_initialstate.c
+++ b/arch/arm/src/arm/arm_initialstate.c
@@ -49,18 +49,6 @@
#include "arm_arch.h"
/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
* Public Functions
****************************************************************************/
@@ -83,6 +71,14 @@ void up_initial_state(struct tcb_s *tcb)
struct xcptcontext *xcp = &tcb->xcp;
uint32_t cpsr;
+ /* Initialize the idle thread stack */
+
+ if (tcb->pid == 0)
+ {
+ up_use_stack(tcb, (void *)(g_idle_topstack -
+ CONFIG_IDLETHREAD_STACKSIZE), CONFIG_IDLETHREAD_STACKSIZE);
+ }
+
/* Initialize the initial exception register context structure */
memset(xcp, 0, sizeof(struct xcptcontext));
diff --git a/arch/arm/src/armv6-m/arm_assert.c b/arch/arm/src/armv6-m/arm_assert.c
index bbc1e41..382a039 100644
--- a/arch/arm/src/armv6-m/arm_assert.c
+++ b/arch/arm/src/armv6-m/arm_assert.c
@@ -224,16 +224,8 @@ static void up_dumpstate(void)
/* Get the limits on the user stack memory */
- if (rtcb->pid == 0) /* Check for CPU0 IDLE thread */
- {
- ustackbase = g_idle_topstack - 4;
- ustacksize = CONFIG_IDLETHREAD_STACKSIZE;
- }
- else
- {
- ustackbase = (uint32_t)rtcb->adj_stack_ptr;
- ustacksize = (uint32_t)rtcb->adj_stack_size;
- }
+ ustackbase = (uint32_t)rtcb->adj_stack_ptr;
+ ustacksize = (uint32_t)rtcb->adj_stack_size;
/* Get the limits on the interrupt stack memory */
diff --git a/arch/arm/src/armv6-m/arm_initialstate.c b/arch/arm/src/armv6-m/arm_initialstate.c
index 263d502..25ccafa 100644
--- a/arch/arm/src/armv6-m/arm_initialstate.c
+++ b/arch/arm/src/armv6-m/arm_initialstate.c
@@ -52,18 +52,6 @@
#include "exc_return.h"
/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
* Public Functions
****************************************************************************/
@@ -85,6 +73,14 @@ void up_initial_state(struct tcb_s *tcb)
{
struct xcptcontext *xcp = &tcb->xcp;
+ /* Initialize the idle thread stack */
+
+ if (tcb->pid == 0)
+ {
+ up_use_stack(tcb, (void *)(g_idle_topstack -
+ CONFIG_IDLETHREAD_STACKSIZE), CONFIG_IDLETHREAD_STACKSIZE);
+ }
+
/* Initialize the initial exception register context structure */
memset(xcp, 0, sizeof(struct xcptcontext));
diff --git a/arch/arm/src/armv7-a/arm_assert.c b/arch/arm/src/armv7-a/arm_assert.c
index 3e5e48a..683264e 100644
--- a/arch/arm/src/armv7-a/arm_assert.c
+++ b/arch/arm/src/armv7-a/arm_assert.c
@@ -212,16 +212,8 @@ static void up_dumpstate(void)
/* Get the limits on the user stack memory */
- if (rtcb->pid == 0) /* Check for CPU0 IDLE thread */
- {
- ustackbase = g_idle_topstack - 4;
- ustacksize = CONFIG_IDLETHREAD_STACKSIZE;
- }
- else
- {
- ustackbase = (uint32_t)rtcb->adj_stack_ptr;
- ustacksize = (uint32_t)rtcb->adj_stack_size;
- }
+ ustackbase = (uint32_t)rtcb->adj_stack_ptr;
+ ustacksize = (uint32_t)rtcb->adj_stack_size;
_alert("Current sp: %08x\n", sp);
diff --git a/arch/arm/src/armv7-a/arm_initialstate.c b/arch/arm/src/armv7-a/arm_initialstate.c
index 97b3c0a..65af4b0 100644
--- a/arch/arm/src/armv7-a/arm_initialstate.c
+++ b/arch/arm/src/armv7-a/arm_initialstate.c
@@ -71,6 +71,14 @@ void up_initial_state(struct tcb_s *tcb)
struct xcptcontext *xcp = &tcb->xcp;
uint32_t cpsr;
+ /* Initialize the idle thread stack */
+
+ if (tcb->pid == 0)
+ {
+ up_use_stack(tcb, (void *)(g_idle_topstack -
+ CONFIG_IDLETHREAD_STACKSIZE), CONFIG_IDLETHREAD_STACKSIZE);
+ }
+
/* Initialize the initial exception register context structure */
memset(xcp, 0, sizeof(struct xcptcontext));
diff --git a/arch/arm/src/armv7-m/arm_assert.c b/arch/arm/src/armv7-m/arm_assert.c
index aae1da4..382297f 100644
--- a/arch/arm/src/armv7-m/arm_assert.c
+++ b/arch/arm/src/armv7-m/arm_assert.c
@@ -217,16 +217,8 @@ static void up_dumpstate(void)
/* Get the limits on the user stack memory */
- if (rtcb->pid == 0) /* Check for CPU0 IDLE thread */
- {
- ustackbase = g_idle_topstack - 4;
- ustacksize = CONFIG_IDLETHREAD_STACKSIZE;
- }
- else
- {
- ustackbase = (uint32_t)rtcb->adj_stack_ptr;
- ustacksize = (uint32_t)rtcb->adj_stack_size;
- }
+ ustackbase = (uint32_t)rtcb->adj_stack_ptr;
+ ustacksize = (uint32_t)rtcb->adj_stack_size;
#if CONFIG_ARCH_INTERRUPTSTACK > 7
/* Get the limits on the interrupt stack memory */
diff --git a/arch/arm/src/armv7-m/arm_initialstate.c b/arch/arm/src/armv7-m/arm_initialstate.c
index b014b18..0a02a4c 100644
--- a/arch/arm/src/armv7-m/arm_initialstate.c
+++ b/arch/arm/src/armv7-m/arm_initialstate.c
@@ -59,6 +59,14 @@ void up_initial_state(struct tcb_s *tcb)
{
struct xcptcontext *xcp = &tcb->xcp;
+ /* Initialize the idle thread stack */
+
+ if (tcb->pid == 0)
+ {
+ up_use_stack(tcb, (void *)(g_idle_topstack -
+ CONFIG_IDLETHREAD_STACKSIZE), CONFIG_IDLETHREAD_STACKSIZE);
+ }
+
/* Initialize the initial exception register context structure */
memset(xcp, 0, sizeof(struct xcptcontext));
diff --git a/arch/arm/src/armv7-r/arm_assert.c b/arch/arm/src/armv7-r/arm_assert.c
index ae4c719..4c65ad5 100644
--- a/arch/arm/src/armv7-r/arm_assert.c
+++ b/arch/arm/src/armv7-r/arm_assert.c
@@ -209,16 +209,8 @@ static void up_dumpstate(void)
/* Get the limits on the user stack memory */
- if (rtcb->pid == 0) /* Check for CPU0 IDLE thread */
- {
- ustackbase = g_idle_topstack - 4;
- ustacksize = CONFIG_IDLETHREAD_STACKSIZE;
- }
- else
- {
- ustackbase = (uint32_t)rtcb->adj_stack_ptr;
- ustacksize = (uint32_t)rtcb->adj_stack_size;
- }
+ ustackbase = (uint32_t)rtcb->adj_stack_ptr;
+ ustacksize = (uint32_t)rtcb->adj_stack_size;
_alert("Current sp: %08x\n", sp);
diff --git a/arch/arm/src/armv7-r/arm_initialstate.c b/arch/arm/src/armv7-r/arm_initialstate.c
index edd7c6d..edbf811 100644
--- a/arch/arm/src/armv7-r/arm_initialstate.c
+++ b/arch/arm/src/armv7-r/arm_initialstate.c
@@ -49,18 +49,6 @@
#include "arm_arch.h"
/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
* Public Functions
****************************************************************************/
@@ -83,6 +71,14 @@ void up_initial_state(struct tcb_s *tcb)
struct xcptcontext *xcp = &tcb->xcp;
uint32_t cpsr;
+ /* Initialize the idle thread stack */
+
+ if (tcb->pid == 0)
+ {
+ up_use_stack(tcb, (void *)(g_idle_topstack -
+ CONFIG_IDLETHREAD_STACKSIZE), CONFIG_IDLETHREAD_STACKSIZE);
+ }
+
/* Initialize the initial exception register context structure */
memset(xcp, 0, sizeof(struct xcptcontext));
diff --git a/arch/arm/src/armv8-m/arm_assert.c b/arch/arm/src/armv8-m/arm_assert.c
index 4477964..ac0b9b7 100644
--- a/arch/arm/src/armv8-m/arm_assert.c
+++ b/arch/arm/src/armv8-m/arm_assert.c
@@ -217,16 +217,8 @@ static void up_dumpstate(void)
/* Get the limits on the user stack memory */
- if (rtcb->pid == 0) /* Check for CPU0 IDLE thread */
- {
- ustackbase = g_idle_topstack - 4;
- ustacksize = CONFIG_IDLETHREAD_STACKSIZE;
- }
- else
- {
- ustackbase = (uint32_t)rtcb->adj_stack_ptr;
- ustacksize = (uint32_t)rtcb->adj_stack_size;
- }
+ ustackbase = (uint32_t)rtcb->adj_stack_ptr;
+ ustacksize = (uint32_t)rtcb->adj_stack_size;
#if CONFIG_ARCH_INTERRUPTSTACK > 7
/* Get the limits on the interrupt stack memory */
diff --git a/arch/arm/src/armv8-m/arm_initialstate.c b/arch/arm/src/armv8-m/arm_initialstate.c
index 969c9be..4593039 100644
--- a/arch/arm/src/armv8-m/arm_initialstate.c
+++ b/arch/arm/src/armv8-m/arm_initialstate.c
@@ -59,6 +59,14 @@ void up_initial_state(struct tcb_s *tcb)
{
struct xcptcontext *xcp = &tcb->xcp;
+ /* Initialize the idle thread stack */
+
+ if (tcb->pid == 0)
+ {
+ up_use_stack(tcb, (void *)(g_idle_topstack -
+ CONFIG_IDLETHREAD_STACKSIZE), CONFIG_IDLETHREAD_STACKSIZE);
+ }
+
/* Initialize the initial exception register context structure */
memset(xcp, 0, sizeof(struct xcptcontext));
diff --git a/arch/arm/src/common/arm_usestack.c b/arch/arm/src/common/arm_usestack.c
index 2fda891..e0e03b4 100644
--- a/arch/arm/src/common/arm_usestack.c
+++ b/arch/arm/src/common/arm_usestack.c
@@ -146,8 +146,11 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
* water marks.
*/
- arm_stack_color((FAR void *)((uintptr_t)tcb->adj_stack_ptr -
- tcb->adj_stack_size), tcb->adj_stack_size);
+ if (tcb->pid != 0)
+ {
+ arm_stack_color((FAR void *)((uintptr_t)tcb->adj_stack_ptr -
+ tcb->adj_stack_size), tcb->adj_stack_size);
+ }
#endif /* CONFIG_STACK_COLORATION */
return OK;
diff --git a/arch/arm/src/efm32/efm32_start.h b/arch/arm/src/efm32/efm32_start.h
index f63ff36..693f3a4 100644
--- a/arch/arm/src/efm32/efm32_start.h
+++ b/arch/arm/src/efm32/efm32_start.h
@@ -43,22 +43,6 @@
#include <nuttx/config.h>
/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
- * linker script. _ebss lies at the end of the BSS region. The idle task
- * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
- * The IDLE thread is the thread that the system boots on and, eventually,
- * becomes the IDLE, do nothing task that runs only when there is nothing
- * else to run. The heap continues from there until the end of memory.
- * g_idle_topstack is a read-only variable the provides this computed
- * address.
- */
-
-extern const uintptr_t g_idle_topstack;
-
-/****************************************************************************
* Public Functions
****************************************************************************/
diff --git a/arch/arm/src/imxrt/imxrt_start.h b/arch/arm/src/imxrt/imxrt_start.h
index b8e0b51..59e19af 100644
--- a/arch/arm/src/imxrt/imxrt_start.h
+++ b/arch/arm/src/imxrt/imxrt_start.h
@@ -77,17 +77,6 @@ extern "C"
#define EXTERN extern
#endif
-/* g_idle_topstack: _sbss is the start of the BSS region as defined by the linker
- * script. _ebss lies at the end of the BSS region. The idle task stack starts at
- * the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE thread is
- * the thread that the system boots on and, eventually, becomes the IDLE, do
- * nothing task that runs only when there is nothing else to run. The heap
- * continues from there until the end of memory. g_idle_topstack is a read-only
- * variable the provides this computed address.
- */
-
-EXTERN const uintptr_t g_idle_topstack;
-
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
diff --git a/arch/arm/src/kinetis/kinetis_start.h b/arch/arm/src/kinetis/kinetis_start.h
index e37361b..6c2eb7b 100644
--- a/arch/arm/src/kinetis/kinetis_start.h
+++ b/arch/arm/src/kinetis/kinetis_start.h
@@ -43,22 +43,6 @@
#include <nuttx/config.h>
/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
- * linker script. _ebss lies at the end of the BSS region. The idle task
- * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
- * The IDLE thread is the thread that the system boots on and, eventually,
- * becomes the IDLE, do nothing task that runs only when there is nothing
- * else to run. The heap continues from there until the end of memory.
- * g_idle_topstack is a read-only variable the provides this computed
- * address.
- */
-
-extern const uintptr_t g_idle_topstack;
-
-/************************************************************************************
* Public Function Prototypes
************************************************************************************/
diff --git a/arch/arm/src/lc823450/lc823450_start.h b/arch/arm/src/lc823450/lc823450_start.h
index a3836c8..9f7d2d2 100644
--- a/arch/arm/src/lc823450/lc823450_start.h
+++ b/arch/arm/src/lc823450/lc823450_start.h
@@ -43,22 +43,6 @@
#include <nuttx/config.h>
/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
- * linker script. _ebss lies at the end of the BSS region. The idle task
- * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
- * The IDLE thread is the thread that the system boots on and, eventually,
- * becomes the IDLE, do nothing task that runs only when there is nothing
- * else to run. The heap continues from there until the end of memory.
- * g_idle_topstack is a read-only variable the provides this computed
- * address.
- */
-
-extern const uintptr_t g_idle_topstack;
-
-/************************************************************************************
* Public Function Prototypes
************************************************************************************/
diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_start.h b/arch/arm/src/lpc17xx_40xx/lpc17_40_start.h
index 3bcbf3a..94f29aa 100644
--- a/arch/arm/src/lpc17xx_40xx/lpc17_40_start.h
+++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_start.h
@@ -43,22 +43,6 @@
#include <nuttx/config.h>
/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
- * linker script. _ebss lies at the end of the BSS region. The idle task
- * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
- * The IDLE thread is the thread that the system boots on and, eventually,
- * becomes the IDLE, do nothing task that runs only when there is nothing
- * else to run. The heap continues from there until the end of memory.
- * g_idle_topstack is a read-only variable the provides this computed
- * address.
- */
-
-extern const uintptr_t g_idle_topstack;
-
-/************************************************************************************
* Public Function Prototypes
************************************************************************************/
diff --git a/arch/arm/src/lpc54xx/lpc54_start.h b/arch/arm/src/lpc54xx/lpc54_start.h
index 00e0cfa..5933205 100644
--- a/arch/arm/src/lpc54xx/lpc54_start.h
+++ b/arch/arm/src/lpc54xx/lpc54_start.h
@@ -50,23 +50,8 @@
#include "arm_internal.h"
#include "chip.h"
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
#ifndef __ASSEMBLY__
-/* g_idle_topstack: _sbss is the start of the BSS region as defined by the linker
- * script. _ebss lies at the end of the BSS region. The idle task stack starts at
- * the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE thread is
- * the thread that the system boots on and, eventually, becomes the IDLE, do
- * nothing task that runs only when there is nothing else to run. The heap
- * continues from there until the end of memory. g_idle_topstack is a read-only
- * variable the provides this computed address.
- */
-
-extern const uintptr_t g_idle_topstack;
-
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
diff --git a/arch/arm/src/max326xx/max326_start.h b/arch/arm/src/max326xx/max326_start.h
index feb0be7..0c2c297 100644
--- a/arch/arm/src/max326xx/max326_start.h
+++ b/arch/arm/src/max326xx/max326_start.h
@@ -50,23 +50,8 @@
#include "arm_internal.h"
#include "chip.h"
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
#ifndef __ASSEMBLY__
-/* g_idle_topstack: _sbss is the start of the BSS region as defined by the linker
- * script. _ebss lies at the end of the BSS region. The idle task stack starts at
- * the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE thread is
- * the thread that the system boots on and, eventually, becomes the IDLE, do
- * nothing task that runs only when there is nothing else to run. The heap
- * continues from there until the end of memory. g_idle_topstack is a read-only
- * variable the provides this computed address.
- */
-
-extern const uintptr_t g_idle_topstack;
-
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
diff --git a/arch/arm/src/nrf52/nrf52_start.h b/arch/arm/src/nrf52/nrf52_start.h
index 4b26bdc..519a3af 100644
--- a/arch/arm/src/nrf52/nrf52_start.h
+++ b/arch/arm/src/nrf52/nrf52_start.h
@@ -50,23 +50,8 @@
#include "arm_internal.h"
#include "chip.h"
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
#ifndef __ASSEMBLY__
-/* g_idle_topstack: _sbss is the start of the BSS region as defined by the linker
- * script. _ebss lies at the end of the BSS region. The idle task stack starts at
- * the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE thread is
- * the thread that the system boots on and, eventually, becomes the IDLE, do
- * nothing task that runs only when there is nothing else to run. The heap
- * continues from there until the end of memory. g_idle_topstack is a read-only
- * variable the provides this computed address.
- */
-
-extern const uintptr_t g_idle_topstack;
-
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
diff --git a/arch/arm/src/s32k1xx/s32k1xx_start.h b/arch/arm/src/s32k1xx/s32k1xx_start.h
index cc708d7..45d212e 100644
--- a/arch/arm/src/s32k1xx/s32k1xx_start.h
+++ b/arch/arm/src/s32k1xx/s32k1xx_start.h
@@ -56,17 +56,6 @@
#ifndef __ASSEMBLY__
-/* g_idle_topstack: _sbss is the start of the BSS region as defined by the linker
- * script. _ebss lies at the end of the BSS region. The idle task stack starts at
- * the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE thread is
- * the thread that the system boots on and, eventually, becomes the IDLE, do
- * nothing task that runs only when there is nothing else to run. The heap
- * continues from there until the end of memory. g_idle_topstack is a read-only
- * variable the provides this computed address.
- */
-
-extern const uintptr_t g_idle_topstack;
-
/* Each S32K1xx board must provide the following initialized structure. This is
* needed to establish the initial board clocking.
*/
diff --git a/arch/arm/src/sam34/sam_start.h b/arch/arm/src/sam34/sam_start.h
index 05644ef..b39cbbb 100644
--- a/arch/arm/src/sam34/sam_start.h
+++ b/arch/arm/src/sam34/sam_start.h
@@ -43,22 +43,6 @@
#include <nuttx/config.h>
/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
- * linker script. _ebss lies at the end of the BSS region. The idle task
- * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
- * The IDLE thread is the thread that the system boots on and, eventually,
- * becomes the IDLE, do nothing task that runs only when there is nothing
- * else to run. The heap continues from there until the end of memory.
- * g_idle_topstack is a read-only variable the provides this computed
- * address.
- */
-
-extern const uintptr_t g_idle_topstack;
-
-/************************************************************************************
* Public Function Prototypes
************************************************************************************/
diff --git a/arch/arm/src/samd5e5/sam_start.h b/arch/arm/src/samd5e5/sam_start.h
index 3e44fb3..96ed7ac 100644
--- a/arch/arm/src/samd5e5/sam_start.h
+++ b/arch/arm/src/samd5e5/sam_start.h
@@ -43,22 +43,6 @@
#include <nuttx/config.h>
/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
- * linker script. _ebss lies at the end of the BSS region. The idle task
- * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
- * The IDLE thread is the thread that the system boots on and, eventually,
- * becomes the IDLE, do nothing task that runs only when there is nothing
- * else to run. The heap continues from there until the end of memory.
- * g_idle_topstack is a read-only variable the provides this computed
- * address.
- */
-
-extern const uintptr_t g_idle_topstack;
-
-/************************************************************************************
* Public Function Prototypes
************************************************************************************/
diff --git a/arch/arm/src/samv7/sam_start.h b/arch/arm/src/samv7/sam_start.h
index 2ca8804..4a33cf4 100644
--- a/arch/arm/src/samv7/sam_start.h
+++ b/arch/arm/src/samv7/sam_start.h
@@ -50,24 +50,8 @@
#include "arm_internal.h"
#include "chip.h"
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Inline Functions
- ************************************************************************************/
-
#ifndef __ASSEMBLY__
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
@@ -77,17 +61,6 @@ extern "C"
#define EXTERN extern
#endif
-/* g_idle_topstack: _sbss is the start of the BSS region as defined by the linker
- * script. _ebss lies at the end of the BSS region. The idle task stack starts at
- * the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE thread is
- * the thread that the system boots on and, eventually, becomes the IDLE, do
- * nothing task that runs only when there is nothing else to run. The heap
- * continues from there until the end of memory. g_idle_topstack is a read-only
- * variable the provides this computed address.
- */
-
-EXTERN const uintptr_t g_idle_topstack;
-
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
diff --git a/arch/arm/src/stm32/stm32_start.h b/arch/arm/src/stm32/stm32_start.h
index ac6b90b..9111426 100644
--- a/arch/arm/src/stm32/stm32_start.h
+++ b/arch/arm/src/stm32/stm32_start.h
@@ -43,22 +43,6 @@
#include <nuttx/config.h>
/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
- * linker script. _ebss lies at the end of the BSS region. The idle task
- * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
- * The IDLE thread is the thread that the system boots on and, eventually,
- * becomes the IDLE, do nothing task that runs only when there is nothing
- * else to run. The heap continues from there until the end of memory.
- * g_idle_topstack is a read-only variable the provides this computed
- * address.
- */
-
-extern const uintptr_t g_idle_topstack;
-
-/************************************************************************************
* Public Function Prototypes
************************************************************************************/
diff --git a/arch/arm/src/stm32f7/stm32_start.h b/arch/arm/src/stm32f7/stm32_start.h
index df85f59..35c2802 100644
--- a/arch/arm/src/stm32f7/stm32_start.h
+++ b/arch/arm/src/stm32f7/stm32_start.h
@@ -50,10 +50,6 @@
#include "arm_internal.h"
#include "chip.h"
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
#ifndef __ASSEMBLY__
#undef EXTERN
@@ -65,17 +61,6 @@ extern "C"
#define EXTERN extern
#endif
-/* g_idle_topstack: _sbss is the start of the BSS region as defined by the linker
- * script. _ebss lies at the end of the BSS region. The idle task stack starts at
- * the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE thread is
- * the thread that the system boots on and, eventually, becomes the IDLE, do
- * nothing task that runs only when there is nothing else to run. The heap
- * continues from there until the end of memory. g_idle_topstack is a read-only
- * variable the provides this computed address.
- */
-
-EXTERN const uintptr_t g_idle_topstack;
-
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
diff --git a/arch/arm/src/stm32h7/stm32_start.h b/arch/arm/src/stm32h7/stm32_start.h
index afae133..7972586 100644
--- a/arch/arm/src/stm32h7/stm32_start.h
+++ b/arch/arm/src/stm32h7/stm32_start.h
@@ -50,10 +50,6 @@
#include "arm_internal.h"
#include "chip.h"
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
#ifndef __ASSEMBLY__
#undef EXTERN
@@ -65,17 +61,6 @@ extern "C"
#define EXTERN extern
#endif
-/* g_idle_topstack: _sbss is the start of the BSS region as defined by the linker
- * script. _ebss lies at the end of the BSS region. The idle task stack starts at
- * the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE thread is
- * the thread that the system boots on and, eventually, becomes the IDLE, do
- * nothing task that runs only when there is nothing else to run. The heap
- * continues from there until the end of memory. g_idle_topstack is a read-only
- * variable the provides this computed address.
- */
-
-EXTERN const uintptr_t g_idle_topstack;
-
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
diff --git a/arch/arm/src/tiva/tiva_start.h b/arch/arm/src/tiva/tiva_start.h
index 64c449d..1a2bb83 100644
--- a/arch/arm/src/tiva/tiva_start.h
+++ b/arch/arm/src/tiva/tiva_start.h
@@ -43,22 +43,6 @@
#include <nuttx/config.h>
/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
- * linker script. _ebss lies at the end of the BSS region. The idle task
- * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
- * The IDLE thread is the thread that the system boots on and, eventually,
- * becomes the IDLE, do nothing task that runs only when there is nothing
- * else to run. The heap continues from there until the end of memory.
- * g_idle_topstack is a read-only variable the provides this computed
- * address.
- */
-
-extern const uintptr_t g_idle_topstack;
-
-/****************************************************************************
* Public Functions
****************************************************************************/
diff --git a/arch/arm/src/tms570/tms570_boot.h b/arch/arm/src/tms570/tms570_boot.h
index 83ead3d..9f4307c 100644
--- a/arch/arm/src/tms570/tms570_boot.h
+++ b/arch/arm/src/tms570/tms570_boot.h
@@ -50,24 +50,8 @@
#include "arm_internal.h"
#include "chip.h"
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Inline Functions
- ************************************************************************************/
-
#ifndef __ASSEMBLY__
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
@@ -77,17 +61,6 @@ extern "C"
#define EXTERN extern
#endif
-/* g_idle_topstack: _sbss is the start of the BSS region as defined by the linker
- * script. _ebss lies at the end of the BSS region. The idle task stack starts at
- * the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE thread is
- * the thread that the system boots on and, eventually, becomes the IDLE, do
- * nothing task that runs only when there is nothing else to run. The heap
- * continues from there until the end of memory. g_idle_topstack is a read-only
- * variable the provides this computed address.
- */
-
-EXTERN const uintptr_t g_idle_topstack;
-
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
diff --git a/arch/avr/src/avr/up_dumpstate.c b/arch/avr/src/avr/up_dumpstate.c
index 0dc4c69..def4699 100644
--- a/arch/avr/src/avr/up_dumpstate.c
+++ b/arch/avr/src/avr/up_dumpstate.c
@@ -154,16 +154,8 @@ void up_dumpstate(void)
/* Get the limits on the user stack memory */
- if (rtcb->pid == 0) /* Check for CPU0 IDLE thread */
- {
- ustackbase = g_idle_topstack - 1;
- ustacksize = CONFIG_IDLETHREAD_STACKSIZE;
- }
- else
- {
- ustackbase = (uint16_t)rtcb->adj_stack_ptr;
- ustacksize = (uint16_t)rtcb->adj_stack_size;
- }
+ ustackbase = (uint16_t)rtcb->adj_stack_ptr;
+ ustacksize = (uint16_t)rtcb->adj_stack_size;
/* Get the limits on the interrupt stack memory */
diff --git a/arch/avr/src/avr/up_initialstate.c b/arch/avr/src/avr/up_initialstate.c
index 5c63f23..9f97513 100644
--- a/arch/avr/src/avr/up_initialstate.c
+++ b/arch/avr/src/avr/up_initialstate.c
@@ -71,6 +71,14 @@ void up_initial_state(struct tcb_s *tcb)
{
struct xcptcontext *xcp = &tcb->xcp;
+ /* Initialize the idle thread stack */
+
+ if (tcb->pid == 0)
+ {
+ up_use_stack(tcb, (void *)(g_idle_topstack -
+ CONFIG_IDLETHREAD_STACKSIZE), CONFIG_IDLETHREAD_STACKSIZE);
+ }
+
/* Initialize the initial exception register context structure. Zeroing
* all registers is a good debug helper, but should not be necessary.
*/
diff --git a/arch/avr/src/avr/up_usestack.c b/arch/avr/src/avr/up_usestack.c
index 0721160..6a4eee6 100644
--- a/arch/avr/src/avr/up_usestack.c
+++ b/arch/avr/src/avr/up_usestack.c
@@ -52,14 +52,6 @@
#include "up_internal.h"
/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
* Public Functions
****************************************************************************/
@@ -119,7 +111,10 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
*/
#ifdef CONFIG_STACK_COLORATION
- memset(tcb->stack_alloc_ptr, STACK_COLOR, stack_size);
+ if (tcb->pid != 0)
+ {
+ memset(tcb->stack_alloc_ptr, STACK_COLOR, stack_size);
+ }
#endif
/* The AVR uses a push-down stack: the stack grows toward loweraddresses
diff --git a/arch/avr/src/avr32/up_dumpstate.c b/arch/avr/src/avr32/up_dumpstate.c
index f818041..c98d912 100644
--- a/arch/avr/src/avr32/up_dumpstate.c
+++ b/arch/avr/src/avr32/up_dumpstate.c
@@ -124,16 +124,8 @@ void up_dumpstate(void)
/* Get the limits on the user stack memory */
- if (rtcb->pid == 0) /* Check for CPU0 IDLE thread */
- {
- ustackbase = g_idle_topstack - 4;
- ustacksize = CONFIG_IDLETHREAD_STACKSIZE;
- }
- else
- {
- ustackbase = (uint32_t)rtcb->adj_stack_ptr;
- ustacksize = (uint32_t)rtcb->adj_stack_size;
- }
+ ustackbase = (uint32_t)rtcb->adj_stack_ptr;
+ ustacksize = (uint32_t)rtcb->adj_stack_size;
/* Get the limits on the interrupt stack memory */
diff --git a/arch/avr/src/avr32/up_initialstate.c b/arch/avr/src/avr32/up_initialstate.c
index 2d47382..4383a2f 100644
--- a/arch/avr/src/avr32/up_initialstate.c
+++ b/arch/avr/src/avr32/up_initialstate.c
@@ -49,18 +49,6 @@
#include "up_arch.h"
/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
* Public Functions
****************************************************************************/
@@ -81,6 +69,14 @@ void up_initial_state(struct tcb_s *tcb)
{
struct xcptcontext *xcp = &tcb->xcp;
+ /* Initialize the idle thread stack */
+
+ if (tcb->pid == 0)
+ {
+ up_use_stack(tcb, (void *)(g_idle_topstack -
+ CONFIG_IDLETHREAD_STACKSIZE), CONFIG_IDLETHREAD_STACKSIZE);
+ }
+
/* Initialize the initial exception register context structure. Zeroing
* all registers is a good debug helper, but should not be necessary.
*/
diff --git a/arch/avr/src/avr32/up_usestack.c b/arch/avr/src/avr32/up_usestack.c
index 19d8137..c30163e 100644
--- a/arch/avr/src/avr32/up_usestack.c
+++ b/arch/avr/src/avr32/up_usestack.c
@@ -51,14 +51,6 @@
#include "up_internal.h"
/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
* Public Functions
****************************************************************************/
@@ -119,7 +111,10 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
*/
#ifdef CONFIG_STACK_COLORATION
- memset(tcb->stack_alloc_ptr, STACK_COLOR, stack_size);
+ if (tcb->pid != 0)
+ {
+ memset(tcb->stack_alloc_ptr, STACK_COLOR, stack_size);
+ }
#endif
/* The AVR32 uses a push-down stack: the stack grows
diff --git a/arch/hc/src/common/up_usestack.c b/arch/hc/src/common/up_usestack.c
index 59b0188..beaf299 100644
--- a/arch/hc/src/common/up_usestack.c
+++ b/arch/hc/src/common/up_usestack.c
@@ -50,14 +50,6 @@
#include "up_internal.h"
/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
* Public Functions
****************************************************************************/
@@ -113,6 +105,17 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
tcb->stack_alloc_ptr = stack;
+ /* If stack debug is enabled, then fill the stack with a recognizable value
+ * that we can use later to test for high water marks.
+ */
+
+#ifdef CONFIG_STACK_COLORATION
+ if (tcb->pid != 0)
+ {
+ memset(tcb->stack_alloc_ptr, 0xaa, stack_size);
+ }
+#endif
+
/* The CPU12 uses a push-down stack: the stack grows
* toward lower addresses in memory. Because the CPU12 stack
* operates as a decrement then store stack, the value assigned
diff --git a/arch/hc/src/m9s12/m9s12_assert.c b/arch/hc/src/m9s12/m9s12_assert.c
index 487031c..7e1696b 100644
--- a/arch/hc/src/m9s12/m9s12_assert.c
+++ b/arch/hc/src/m9s12/m9s12_assert.c
@@ -199,16 +199,8 @@ static void up_dumpstate(void)
/* Get the limits on the user stack memory */
- if (rtcb->pid == 0) /* Check for CPU0 IDLE thread */
- {
- ustackbase = g_idle_topstack - 4;
- ustacksize = CONFIG_IDLETHREAD_STACKSIZE;
- }
- else
- {
- ustackbase = (uint16_t)rtcb->adj_stack_ptr;
- ustacksize = (uint16_t)rtcb->adj_stack_size;
- }
+ ustackbase = (uint16_t)rtcb->adj_stack_ptr;
+ ustacksize = (uint16_t)rtcb->adj_stack_size;
/* Get the limits on the interrupt stack memory */
diff --git a/arch/hc/src/m9s12/m9s12_initialstate.c b/arch/hc/src/m9s12/m9s12_initialstate.c
index 89e2ac9..2bd6931 100644
--- a/arch/hc/src/m9s12/m9s12_initialstate.c
+++ b/arch/hc/src/m9s12/m9s12_initialstate.c
@@ -47,18 +47,6 @@
#include "up_internal.h"
/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
* Public Functions
****************************************************************************/
@@ -80,6 +68,14 @@ void up_initial_state(struct tcb_s *tcb)
{
struct xcptcontext *xcp = &tcb->xcp;
+ /* Initialize the idle thread stack */
+
+ if (tcb->pid == 0)
+ {
+ up_use_stack(tcb, (void *)(g_idle_topstack -
+ CONFIG_IDLETHREAD_STACKSIZE), CONFIG_IDLETHREAD_STACKSIZE);
+ }
+
/* Initialize the initial exception register context structure */
memset(xcp, 0, sizeof(struct xcptcontext));
diff --git a/arch/mips/src/common/mips_usestack.c b/arch/mips/src/common/mips_usestack.c
index 30a6a7e..aa7071d 100644
--- a/arch/mips/src/common/mips_usestack.c
+++ b/arch/mips/src/common/mips_usestack.c
@@ -71,14 +71,6 @@
#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
* Public Functions
****************************************************************************/
@@ -134,6 +126,17 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
tcb->stack_alloc_ptr = stack;
+ /* If stack debug is enabled, then fill the stack with a recognizable value
+ * that we can use later to test for high water marks.
+ */
+
+#ifdef CONFIG_STACK_COLORATION
+ if (tcb->pid != 0)
+ {
+ memset(tcb->stack_alloc_ptr, 0xaa, stack_size);
+ }
+#endif
+
/* MIPS uses a push-down stack: the stack grows toward loweraddresses in
* memory. The stack pointer register, points to the lowest, valid work
* address (the "top" of the stack). Items on the stack are referenced
diff --git a/arch/mips/src/mips32/mips_dumpstate.c b/arch/mips/src/mips32/mips_dumpstate.c
index 58c3da6..9005001 100644
--- a/arch/mips/src/mips32/mips_dumpstate.c
+++ b/arch/mips/src/mips32/mips_dumpstate.c
@@ -144,16 +144,8 @@ void up_dumpstate(void)
/* Get the limits on the user stack memory */
- if (rtcb->pid == 0) /* Check for CPU0 IDLE thread */
- {
- ustackbase = g_idle_topstack - 4;
- ustacksize = CONFIG_IDLETHREAD_STACKSIZE;
- }
- else
- {
- ustackbase = (uint32_t)rtcb->adj_stack_ptr;
- ustacksize = (uint32_t)rtcb->adj_stack_size;
- }
+ ustackbase = (uint32_t)rtcb->adj_stack_ptr;
+ ustacksize = (uint32_t)rtcb->adj_stack_size;
/* Get the limits on the interrupt stack memory */
diff --git a/arch/mips/src/mips32/mips_initialstate.c b/arch/mips/src/mips32/mips_initialstate.c
index 7a7c242..9b02f5b 100644
--- a/arch/mips/src/mips32/mips_initialstate.c
+++ b/arch/mips/src/mips32/mips_initialstate.c
@@ -73,6 +73,14 @@ void up_initial_state(struct tcb_s *tcb)
struct xcptcontext *xcp = &tcb->xcp;
uint32_t regval;
+ /* Initialize the idle thread stack */
+
+ if (tcb->pid == 0)
+ {
+ up_use_stack(tcb, (void *)(g_idle_topstack -
+ CONFIG_IDLETHREAD_STACKSIZE), CONFIG_IDLETHREAD_STACKSIZE);
+ }
+
/* Initialize the initial exception register context structure */
memset(xcp, 0, sizeof(struct xcptcontext));
diff --git a/arch/misoc/src/lm32/Make.defs b/arch/misoc/src/lm32/Make.defs
index b8f21a0..15ec51f 100644
--- a/arch/misoc/src/lm32/Make.defs
+++ b/arch/misoc/src/lm32/Make.defs
@@ -50,4 +50,4 @@ CHIP_CSRCS += lm32_initialize.c lm32_initialstate.c lm32_interruptcontext.c
CHIP_CSRCS += lm32_irq.c lm32_releasepending.c lm32_releasestack.c
CHIP_CSRCS += lm32_stackframe.c lm32_swint.c lm32_unblocktask.c
CHIP_CSRCS += lm32_reprioritizertr.c lm32_schedulesigaction.c lm32_sigdeliver.c
-CHIP_CSRCS += lm32_flushcache.c
+CHIP_CSRCS += lm32_flushcache.c lm32_usetack.c
diff --git a/arch/misoc/src/lm32/lm32_dumpstate.c b/arch/misoc/src/lm32/lm32_dumpstate.c
index f6ff679..9274b2a 100644
--- a/arch/misoc/src/lm32/lm32_dumpstate.c
+++ b/arch/misoc/src/lm32/lm32_dumpstate.c
@@ -141,16 +141,8 @@ void lm32_dumpstate(void)
/* Get the limits on the user stack memory */
- if (rtcb->pid == 0) /* Check for CPU0 IDLE thread */
- {
- ustackbase = g_idle_topstack - 4;
- ustacksize = CONFIG_IDLETHREAD_STACKSIZE;
- }
- else
- {
- ustackbase = (uint32_t)rtcb->adj_stack_ptr;
- ustacksize = (uint32_t)rtcb->adj_stack_size;
- }
+ ustackbase = (uint32_t)rtcb->adj_stack_ptr;
+ ustacksize = (uint32_t)rtcb->adj_stack_size;
/* Get the limits on the interrupt stack memory */
diff --git a/arch/misoc/src/lm32/lm32_initialstate.c b/arch/misoc/src/lm32/lm32_initialstate.c
index f76c82e..9a9c000 100644
--- a/arch/misoc/src/lm32/lm32_initialstate.c
+++ b/arch/misoc/src/lm32/lm32_initialstate.c
@@ -50,18 +50,6 @@
#include "lm32.h"
/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
* Public Functions
****************************************************************************/
@@ -83,6 +71,14 @@ void up_initial_state(struct tcb_s *tcb)
{
struct xcptcontext *xcp = &tcb->xcp;
+ /* Initialize the idle thread stack */
+
+ if (tcb->pid == 0)
+ {
+ up_use_stack(tcb, (void *)(g_idle_topstack -
+ CONFIG_IDLETHREAD_STACKSIZE), CONFIG_IDLETHREAD_STACKSIZE);
+ }
+
/* Initialize the initial exception register context structure */
memset(xcp, 0, sizeof(struct xcptcontext));
diff --git a/arch/z80/src/common/z80_usestack.c b/arch/misoc/src/lm32/lm32_usestack.c
similarity index 81%
copy from arch/z80/src/common/z80_usestack.c
copy to arch/misoc/src/lm32/lm32_usestack.c
index 2ce1829..ee4189c 100644
--- a/arch/z80/src/common/z80_usestack.c
+++ b/arch/misoc/src/lm32/lm32_usestack.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/z80/src/common/z80_usestack.c
+ * arch/misoc/src/lm32/lm32_usestack.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -28,20 +28,11 @@
#include <stdint.h>
#include <sched.h>
#include <debug.h>
+
#include <nuttx/kmalloc.h>
#include <nuttx/arch.h>
#include <nuttx/tls.h>
-#include "z80_internal.h"
-
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -98,16 +89,27 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
tcb->stack_alloc_ptr = stack;
- /* The Z80 uses a push-down stack: the stack grows toward lower
- * addresses in memory. The stack pointer register, points to the
- * lowest, valid work address (the "top" of the stack). Items on
- * the stack are* referenced as positive word offsets from sp.
+ /* If stack debug is enabled, then fill the stack with a recognizable value
+ * that we can use later to test for high water marks.
+ */
+
+#ifdef CONFIG_STACK_COLORATION
+ if (tcb->pid != 0)
+ {
+ memset(tcb->stack_alloc_ptr, 0xaa, stack_size);
+ }
+#endif
+
+ /* The i486 uses a push-down stack: the stack grows toward loweraddresses
+ * in memory. The stack pointer register, points to the lowest, valid work
+ * address (the "top" of the stack). Items on the stack are referenced as
+ * positive word offsets from sp.
*/
top_of_stack = (uint32_t)tcb->stack_alloc_ptr + stack_size - 4;
- /* The Z80 stack does not need to be aligned. Here is is aligned at
- * word (4 byte) boundary.
+ /* The i486 stack must be aligned at word (4 byte) boundaries. If necessary
+ * top_of_stack must be rounded down to the next boundary
*/
top_of_stack &= ~3;
@@ -115,7 +117,7 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
/* Save the adjusted stack values in the struct tcb_s */
- tcb->adj_stack_size = top_of_stack;
+ tcb->adj_stack_ptr = (uint32_t *)top_of_stack;
tcb->adj_stack_size = size_of_stack;
/* Initialize the TLS data structure */
diff --git a/arch/misoc/src/minerva/Make.defs b/arch/misoc/src/minerva/Make.defs
index ed7fdcf..dd80adf 100644
--- a/arch/misoc/src/minerva/Make.defs
+++ b/arch/misoc/src/minerva/Make.defs
@@ -50,4 +50,4 @@ CHIP_CSRCS += minerva_initialize.c minerva_initialstate.c minerva_interruptconte
CHIP_CSRCS += minerva_irq.c minerva_releasepending.c minerva_releasestack.c
CHIP_CSRCS += minerva_stackframe.c minerva_swint.c minerva_unblocktask.c
CHIP_CSRCS += minerva_reprioritizertr.c minerva_schedulesigaction.c minerva_sigdeliver.c
-CHIP_CSRCS += minerva_flushcache.c minerva_doexceptions.c
+CHIP_CSRCS += minerva_flushcache.c minerva_doexceptions.c minerva_usetack.c
diff --git a/arch/misoc/src/minerva/minerva_dumpstate.c b/arch/misoc/src/minerva/minerva_dumpstate.c
index 6bd5548..99228e7 100644
--- a/arch/misoc/src/minerva/minerva_dumpstate.c
+++ b/arch/misoc/src/minerva/minerva_dumpstate.c
@@ -148,16 +148,8 @@ void minerva_dumpstate(void)
* == NULL)
*/
- if (rtcb->flink == NULL)
- {
- ustackbase = g_idle_topstack - 4;
- ustacksize = CONFIG_IDLETHREAD_STACKSIZE;
- }
- else
- {
- ustackbase = (uint32_t) rtcb->adj_stack_ptr;
- ustacksize = (uint32_t) rtcb->adj_stack_size;
- }
+ ustackbase = (uint32_t) rtcb->adj_stack_ptr;
+ ustacksize = (uint32_t) rtcb->adj_stack_size;
/* Get the limits on the interrupt stack memory */
diff --git a/arch/misoc/src/minerva/minerva_initialstate.c b/arch/misoc/src/minerva/minerva_initialstate.c
index b4ae097..bcc0621 100644
--- a/arch/misoc/src/minerva/minerva_initialstate.c
+++ b/arch/misoc/src/minerva/minerva_initialstate.c
@@ -75,6 +75,14 @@ void up_initial_state(struct tcb_s *tcb)
uint32_t regval;
struct xcptcontext *xcp = &tcb->xcp;
+ /* Initialize the idle thread stack */
+
+ if (tcb->pid == 0)
+ {
+ up_use_stack(tcb, (void *)(g_idle_topstack -
+ CONFIG_IDLETHREAD_STACKSIZE), CONFIG_IDLETHREAD_STACKSIZE);
+ }
+
/* Initialize the initial exception register context structure */
memset(xcp, 0, sizeof(struct xcptcontext));
diff --git a/arch/z80/src/common/z80_usestack.c b/arch/misoc/src/minerva/minerva_usestack.c
similarity index 81%
copy from arch/z80/src/common/z80_usestack.c
copy to arch/misoc/src/minerva/minerva_usestack.c
index 2ce1829..782177d 100644
--- a/arch/z80/src/common/z80_usestack.c
+++ b/arch/misoc/src/minerva/minerva_usestack.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/z80/src/common/z80_usestack.c
+ * arch/misoc/src/minerva/minerva_usestack.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -28,20 +28,11 @@
#include <stdint.h>
#include <sched.h>
#include <debug.h>
+
#include <nuttx/kmalloc.h>
#include <nuttx/arch.h>
#include <nuttx/tls.h>
-#include "z80_internal.h"
-
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -98,16 +89,27 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
tcb->stack_alloc_ptr = stack;
- /* The Z80 uses a push-down stack: the stack grows toward lower
- * addresses in memory. The stack pointer register, points to the
- * lowest, valid work address (the "top" of the stack). Items on
- * the stack are* referenced as positive word offsets from sp.
+ /* If stack debug is enabled, then fill the stack with a recognizable value
+ * that we can use later to test for high water marks.
+ */
+
+#ifdef CONFIG_STACK_COLORATION
+ if (tcb->pid != 0)
+ {
+ memset(tcb->stack_alloc_ptr, 0xaa, stack_size);
+ }
+#endif
+
+ /* The i486 uses a push-down stack: the stack grows toward loweraddresses
+ * in memory. The stack pointer register, points to the lowest, valid work
+ * address (the "top" of the stack). Items on the stack are referenced as
+ * positive word offsets from sp.
*/
top_of_stack = (uint32_t)tcb->stack_alloc_ptr + stack_size - 4;
- /* The Z80 stack does not need to be aligned. Here is is aligned at
- * word (4 byte) boundary.
+ /* The i486 stack must be aligned at word (4 byte) boundaries. If necessary
+ * top_of_stack must be rounded down to the next boundary
*/
top_of_stack &= ~3;
@@ -115,7 +117,7 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
/* Save the adjusted stack values in the struct tcb_s */
- tcb->adj_stack_size = top_of_stack;
+ tcb->adj_stack_ptr = (uint32_t *)top_of_stack;
tcb->adj_stack_size = size_of_stack;
/* Initialize the TLS data structure */
diff --git a/arch/or1k/src/common/up_assert.c b/arch/or1k/src/common/up_assert.c
index d7abb50..6a81ae8 100644
--- a/arch/or1k/src/common/up_assert.c
+++ b/arch/or1k/src/common/up_assert.c
@@ -224,16 +224,8 @@ static void up_dumpstate(void)
/* Get the limits on the user stack memory */
- if (rtcb->pid == 0) /* Check for CPU0 IDLE thread */
- {
- ustackbase = g_idle_topstack - 4;
- ustacksize = CONFIG_IDLETHREAD_STACKSIZE;
- }
- else
- {
- ustackbase = (uint32_t)rtcb->adj_stack_ptr;
- ustacksize = (uint32_t)rtcb->adj_stack_size;
- }
+ ustackbase = (uint32_t)rtcb->adj_stack_ptr;
+ ustacksize = (uint32_t)rtcb->adj_stack_size;
/* Get the limits on the interrupt stack memory */
diff --git a/arch/or1k/src/common/up_initialstate.c b/arch/or1k/src/common/up_initialstate.c
index 8754b3f..667a7cf 100644
--- a/arch/or1k/src/common/up_initialstate.c
+++ b/arch/or1k/src/common/up_initialstate.c
@@ -73,6 +73,14 @@ void up_initial_state(struct tcb_s *tcb)
struct xcptcontext *xcp = &tcb->xcp;
uint32_t sr;
+ /* Initialize the idle thread stack */
+
+ if (tcb->pid == 0)
+ {
+ up_use_stack(tcb, (void *)(g_idle_topstack -
+ CONFIG_IDLETHREAD_STACKSIZE), CONFIG_IDLETHREAD_STACKSIZE);
+ }
+
/* Initialize the initial exception register context structure */
memset(xcp, 0, sizeof(struct xcptcontext));
diff --git a/arch/z80/src/common/z80_usestack.c b/arch/or1k/src/common/up_usestack.c
similarity index 81%
copy from arch/z80/src/common/z80_usestack.c
copy to arch/or1k/src/common/up_usestack.c
index 2ce1829..782177d 100644
--- a/arch/z80/src/common/z80_usestack.c
+++ b/arch/or1k/src/common/up_usestack.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/z80/src/common/z80_usestack.c
+ * arch/misoc/src/minerva/minerva_usestack.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -28,20 +28,11 @@
#include <stdint.h>
#include <sched.h>
#include <debug.h>
+
#include <nuttx/kmalloc.h>
#include <nuttx/arch.h>
#include <nuttx/tls.h>
-#include "z80_internal.h"
-
-/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -98,16 +89,27 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
tcb->stack_alloc_ptr = stack;
- /* The Z80 uses a push-down stack: the stack grows toward lower
- * addresses in memory. The stack pointer register, points to the
- * lowest, valid work address (the "top" of the stack). Items on
- * the stack are* referenced as positive word offsets from sp.
+ /* If stack debug is enabled, then fill the stack with a recognizable value
+ * that we can use later to test for high water marks.
+ */
+
+#ifdef CONFIG_STACK_COLORATION
+ if (tcb->pid != 0)
+ {
+ memset(tcb->stack_alloc_ptr, 0xaa, stack_size);
+ }
+#endif
+
+ /* The i486 uses a push-down stack: the stack grows toward loweraddresses
+ * in memory. The stack pointer register, points to the lowest, valid work
+ * address (the "top" of the stack). Items on the stack are referenced as
+ * positive word offsets from sp.
*/
top_of_stack = (uint32_t)tcb->stack_alloc_ptr + stack_size - 4;
- /* The Z80 stack does not need to be aligned. Here is is aligned at
- * word (4 byte) boundary.
+ /* The i486 stack must be aligned at word (4 byte) boundaries. If necessary
+ * top_of_stack must be rounded down to the next boundary
*/
top_of_stack &= ~3;
@@ -115,7 +117,7 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
/* Save the adjusted stack values in the struct tcb_s */
- tcb->adj_stack_size = top_of_stack;
+ tcb->adj_stack_ptr = (uint32_t *)top_of_stack;
tcb->adj_stack_size = size_of_stack;
/* Initialize the TLS data structure */
diff --git a/arch/or1k/src/mor1kx/Make.defs b/arch/or1k/src/mor1kx/Make.defs
index 1210b53..d272b4d 100644
--- a/arch/or1k/src/mor1kx/Make.defs
+++ b/arch/or1k/src/mor1kx/Make.defs
@@ -41,6 +41,7 @@ CMN_CSRCS = up_initialize.c \
up_interruptcontext.c \
up_allocateheap.c \
up_createstack.c \
+ up_usestack.c \
up_releasestack.c \
up_stackframe.c \
up_initialstate.c \
diff --git a/arch/renesas/src/common/up_usestack.c b/arch/renesas/src/common/up_usestack.c
index aa44e61..e11f7cc 100644
--- a/arch/renesas/src/common/up_usestack.c
+++ b/arch/renesas/src/common/up_usestack.c
@@ -51,14 +51,6 @@
#include "up_internal.h"
/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
* Public Functions
****************************************************************************/
@@ -114,6 +106,17 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
tcb->stack_alloc_ptr = stack;
+ /* If stack debug is enabled, then fill the stack with a recognizable value
+ * that we can use later to test for high water marks.
+ */
+
+#ifdef CONFIG_STACK_COLORATION
+ if (tcb->pid != 0)
+ {
+ memset(tcb->stack_alloc_ptr, 0xaa, stack_size);
+ }
+#endif
+
/* The SH family uses a push-down stack: the stack grows toward lower
* addresses in memory. The stack pointer register, points to the
* lowest, valid work address (the "top" of the stack). Items on the
diff --git a/arch/renesas/src/m16c/chip.h b/arch/renesas/src/m16c/chip.h
index 292e956..cc08d4c 100644
--- a/arch/renesas/src/m16c/chip.h
+++ b/arch/renesas/src/m16c/chip.h
@@ -266,7 +266,6 @@ extern uint32_t g_enronly; /* Start of relocated read-only data in FLASH *
extern uint32_t g_efronly; /* Start of relocated read-only data in FLASH */
#endif
extern uint32_t g_svarvect; /* Start of variable vectors */
-extern uint32_t g_idle_topstack; /* Start of the heap */
/* Address of the saved user stack pointer */
diff --git a/arch/renesas/src/m16c/m16c_dumpstate.c b/arch/renesas/src/m16c/m16c_dumpstate.c
index f76e566..f5f6c11 100644
--- a/arch/renesas/src/m16c/m16c_dumpstate.c
+++ b/arch/renesas/src/m16c/m16c_dumpstate.c
@@ -151,16 +151,8 @@ void up_dumpstate(void)
/* Get the limits on the user stack memory */
- if (rtcb->pid == 0) /* Check for CPU0 IDLE thread */
- {
- ustackbase = g_idle_topstack - 1;
- ustacksize = CONFIG_IDLETHREAD_STACKSIZE;
- }
- else
- {
- ustackbase = (uint16_t)rtcb->adj_stack_ptr;
- ustacksize = (uint16_t)rtcb->adj_stack_size;
- }
+ ustackbase = (uint16_t)rtcb->adj_stack_ptr;
+ ustacksize = (uint16_t)rtcb->adj_stack_size;
/* Get the limits on the interrupt stack memory.
* The near RAM memory map is as follows:
diff --git a/arch/renesas/src/m16c/m16c_initialstate.c b/arch/renesas/src/m16c/m16c_initialstate.c
index ac64f95..03953b0 100644
--- a/arch/renesas/src/m16c/m16c_initialstate.c
+++ b/arch/renesas/src/m16c/m16c_initialstate.c
@@ -70,6 +70,14 @@ void up_initial_state(FAR struct tcb_s *tcb)
FAR struct xcptcontext *xcp = &tcb->xcp;
FAR uint8_t *regs = xcp->regs;
+ /* Initialize the idle thread stack */
+
+ if (tcb->pid == 0)
+ {
+ up_use_stack(tcb, (FAR void *)(g_idle_topstack -
+ CONFIG_IDLETHREAD_STACKSIZE), CONFIG_IDLETHREAD_STACKSIZE);
+ }
+
/* Initialize the initial exception register context structure */
memset(xcp, 0, sizeof(struct xcptcontext));
diff --git a/arch/renesas/src/rx65n/rx65n_dumpstate.c b/arch/renesas/src/rx65n/rx65n_dumpstate.c
index ed4d4a6..a17896c 100644
--- a/arch/renesas/src/rx65n/rx65n_dumpstate.c
+++ b/arch/renesas/src/rx65n/rx65n_dumpstate.c
@@ -142,16 +142,8 @@ void up_dumpstate(void)
/* Get the limits on the user stack memory */
- if (rtcb->pid == 0) /* Check for CPU0 IDLE thread */
- {
- ustackbase = g_idle_topstack - 1;
- ustacksize = CONFIG_IDLETHREAD_STACKSIZE;
- }
- else
- {
- ustackbase = (uint32_t)rtcb->adj_stack_ptr;
- ustacksize = (uint16_t)rtcb->adj_stack_size;
- }
+ ustackbase = (uint32_t)rtcb->adj_stack_ptr;
+ ustacksize = (uint16_t)rtcb->adj_stack_size;
#if CONFIG_ARCH_INTERRUPTSTACK > 3
istackbase = ebss; /* check how to declare ebss, as of now declared in chip.h */
diff --git a/arch/renesas/src/rx65n/rx65n_initialstate.c b/arch/renesas/src/rx65n/rx65n_initialstate.c
index 98d66ae..6bb18cd 100644
--- a/arch/renesas/src/rx65n/rx65n_initialstate.c
+++ b/arch/renesas/src/rx65n/rx65n_initialstate.c
@@ -61,6 +61,14 @@ void up_initial_state(struct tcb_s *tcb)
{
struct xcptcontext *xcp = &tcb->xcp;
+ /* Initialize the idle thread stack */
+
+ if (tcb->pid == 0)
+ {
+ up_use_stack(tcb, (void *)(g_idle_topstack -
+ CONFIG_IDLETHREAD_STACKSIZE), CONFIG_IDLETHREAD_STACKSIZE);
+ }
+
/* Initialize the initial exception register context structure */
memset(xcp, 0, sizeof(struct xcptcontext));
diff --git a/arch/renesas/src/sh1/sh1_dumpstate.c b/arch/renesas/src/sh1/sh1_dumpstate.c
index 1028202..55b53ed 100644
--- a/arch/renesas/src/sh1/sh1_dumpstate.c
+++ b/arch/renesas/src/sh1/sh1_dumpstate.c
@@ -138,16 +138,8 @@ void up_dumpstate(void)
/* Get the limits on the user stack memory */
- if (rtcb->pid == 0) /* Check for CPU0 IDLE thread */
- {
- ustackbase = g_idle_topstack - 4;
- ustacksize = CONFIG_IDLETHREAD_STACKSIZE;
- }
- else
- {
- ustackbase = (uint32_t)rtcb->adj_stack_ptr;
- ustacksize = (uint32_t)rtcb->adj_stack_size;
- }
+ ustackbase = (uint32_t)rtcb->adj_stack_ptr;
+ ustacksize = (uint32_t)rtcb->adj_stack_size;
/* Get the limits on the interrupt stack memory */
diff --git a/arch/renesas/src/sh1/sh1_initialstate.c b/arch/renesas/src/sh1/sh1_initialstate.c
index 552db9f..045a997 100644
--- a/arch/renesas/src/sh1/sh1_initialstate.c
+++ b/arch/renesas/src/sh1/sh1_initialstate.c
@@ -45,14 +45,6 @@
#include "up_arch.h"
/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
* Private Functions
****************************************************************************/
@@ -96,6 +88,14 @@ void up_initial_state(struct tcb_s *tcb)
{
struct xcptcontext *xcp = &tcb->xcp;
+ /* Initialize the idle thread stack */
+
+ if (tcb->pid == 0)
+ {
+ up_use_stack(tcb, (void *)(g_idle_topstack -
+ CONFIG_IDLETHREAD_STACKSIZE), CONFIG_IDLETHREAD_STACKSIZE);
+ }
+
/* Initialize the initial exception register context structure */
memset(xcp, 0, sizeof(struct xcptcontext));
diff --git a/arch/risc-v/src/common/riscv_initialize.c b/arch/risc-v/src/common/riscv_initialize.c
index aefee0c..1fb5bc1 100644
--- a/arch/risc-v/src/common/riscv_initialize.c
+++ b/arch/risc-v/src/common/riscv_initialize.c
@@ -108,8 +108,6 @@ static inline void up_color_intstack(void)
void up_initialize(void)
{
- FAR struct tcb_s *idle;
-
/* Colorize the interrupt stack */
up_color_intstack();
@@ -118,13 +116,6 @@ void up_initialize(void)
up_addregion();
- /* Initialize the idle task stack info */
-
- idle = this_task(); /* It should be idle task */
- idle->stack_alloc_ptr = _END_BSS;
- idle->adj_stack_ptr = (FAR void *)g_idle_topstack;
- idle->adj_stack_size = CONFIG_IDLETHREAD_STACKSIZE;
-
#ifdef CONFIG_PM
/* Initialize the power management subsystem. This MCU-specific function
* must be called *very* early in the initialization sequence *before* any
diff --git a/arch/risc-v/src/common/riscv_usestack.c b/arch/risc-v/src/common/riscv_usestack.c
index a0bc0d0..81dffd0 100644
--- a/arch/risc-v/src/common/riscv_usestack.c
+++ b/arch/risc-v/src/common/riscv_usestack.c
@@ -71,14 +71,6 @@
#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK)
/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
* Public Functions
****************************************************************************/
@@ -165,9 +157,12 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
* water marks.
*/
- up_stack_color((FAR void *)((uintptr_t)tcb->stack_alloc_ptr +
- sizeof(struct tls_info_s)),
- tcb->adj_stack_size - sizeof(struct tls_info_s));
+ if (tcb->pid != 0)
+ {
+ up_stack_color((FAR void *)((uintptr_t)tcb->stack_alloc_ptr +
+ sizeof(struct tls_info_s)),
+ size_of_stack - sizeof(struct tls_info_s));
+ }
#endif
return OK;
diff --git a/arch/risc-v/src/rv32im/riscv_assert.c b/arch/risc-v/src/rv32im/riscv_assert.c
index bcf85b3..2dfe3c5 100644
--- a/arch/risc-v/src/rv32im/riscv_assert.c
+++ b/arch/risc-v/src/rv32im/riscv_assert.c
@@ -199,16 +199,8 @@ static void up_dumpstate(void)
/* Get the limits on the user stack memory */
- if (rtcb->pid == 0) /* Check for CPU0 IDLE thread */
- {
- ustackbase = g_idle_topstack - 4;
- ustacksize = CONFIG_IDLETHREAD_STACKSIZE;
- }
- else
- {
- ustackbase = (uint32_t)rtcb->adj_stack_ptr;
- ustacksize = (uint32_t)rtcb->adj_stack_size;
- }
+ ustackbase = (uint32_t)rtcb->adj_stack_ptr;
+ ustacksize = (uint32_t)rtcb->adj_stack_size;
/* Get the limits on the interrupt stack memory */
diff --git a/arch/risc-v/src/rv32im/riscv_initialstate.c b/arch/risc-v/src/rv32im/riscv_initialstate.c
index 5f0ae55..0aad94d 100644
--- a/arch/risc-v/src/rv32im/riscv_initialstate.c
+++ b/arch/risc-v/src/rv32im/riscv_initialstate.c
@@ -72,6 +72,14 @@ void up_initial_state(struct tcb_s *tcb)
struct xcptcontext *xcp = &tcb->xcp;
uint32_t regval;
+ /* Initialize the idle thread stack */
+
+ if (tcb->pid == 0)
+ {
+ up_use_stack(tcb, (void *)(g_idle_topstack -
+ CONFIG_IDLETHREAD_STACKSIZE), CONFIG_IDLETHREAD_STACKSIZE);
+ }
+
/* Initialize the initial exception register context structure */
memset(xcp, 0, sizeof(struct xcptcontext));
diff --git a/arch/risc-v/src/rv64gc/riscv_assert.c b/arch/risc-v/src/rv64gc/riscv_assert.c
index b23db62..67071da 100644
--- a/arch/risc-v/src/rv64gc/riscv_assert.c
+++ b/arch/risc-v/src/rv64gc/riscv_assert.c
@@ -210,16 +210,8 @@ static void up_dumpstate(void)
/* Get the limits on the user stack memory */
- if (rtcb->pid == 0) /* Check for CPU0 IDLE thread */
- {
- ustackbase = g_idle_topstack - 8;
- ustacksize = CONFIG_IDLETHREAD_STACKSIZE;
- }
- else
- {
- ustackbase = (uintptr_t)rtcb->adj_stack_ptr;
- ustacksize = (uintptr_t)rtcb->adj_stack_size;
- }
+ ustackbase = (uintptr_t)rtcb->adj_stack_ptr;
+ ustacksize = (uintptr_t)rtcb->adj_stack_size;
/* Get the limits on the interrupt stack memory */
diff --git a/arch/risc-v/src/rv64gc/riscv_initialstate.c b/arch/risc-v/src/rv64gc/riscv_initialstate.c
index caa0c37..b0ebd1d 100644
--- a/arch/risc-v/src/rv64gc/riscv_initialstate.c
+++ b/arch/risc-v/src/rv64gc/riscv_initialstate.c
@@ -72,6 +72,14 @@ void up_initial_state(struct tcb_s *tcb)
struct xcptcontext *xcp = &tcb->xcp;
uint64_t regval;
+ /* Initialize the idle thread stack */
+
+ if (tcb->pid == 0)
+ {
+ up_use_stack(tcb, (void *)(g_idle_topstack -
+ CONFIG_IDLETHREAD_STACKSIZE), CONFIG_IDLETHREAD_STACKSIZE);
+ }
+
/* Initialize the initial exception register context structure */
memset(xcp, 0, sizeof(struct xcptcontext));
diff --git a/arch/sim/src/sim/up_initialstate.c b/arch/sim/src/sim/up_initialstate.c
index 129d3be..03e5a35 100644
--- a/arch/sim/src/sim/up_initialstate.c
+++ b/arch/sim/src/sim/up_initialstate.c
@@ -66,6 +66,12 @@
void up_initial_state(struct tcb_s *tcb)
{
+ if (tcb->pid == 0)
+ {
+ up_use_stack(tcb, (void *)(sim_getsp() -
+ CONFIG_IDLETHREAD_STACKSIZE), CONFIG_IDLETHREAD_STACKSIZE);
+ }
+
memset(&tcb->xcp, 0, sizeof(struct xcptcontext));
tcb->xcp.regs[JB_SP] = (xcpt_reg_t)tcb->adj_stack_ptr - sizeof(xcpt_reg_t);
tcb->xcp.regs[JB_PC] = (xcpt_reg_t)tcb->start;
diff --git a/arch/sim/src/sim/up_usestack.c b/arch/sim/src/sim/up_usestack.c
index 1c21d81..b6e8480 100644
--- a/arch/sim/src/sim/up_usestack.c
+++ b/arch/sim/src/sim/up_usestack.c
@@ -136,9 +136,12 @@ int up_use_stack(FAR struct tcb_s *tcb, FAR void *stack, size_t stack_size)
* water marks.
*/
- up_stack_color((FAR void *)((uintptr_t)tcb->stack_alloc_ptr +
- sizeof(struct tls_info_s)),
- tcb->adj_stack_size - sizeof(struct tls_info_s));
+ if (tcb->pid != 0)
+ {
+ up_stack_color((FAR void *)((uintptr_t)tcb->stack_alloc_ptr +
+ sizeof(struct tls_info_s)),
+ adj_stack_size - sizeof(struct tls_info_s));
+ }
#endif
return OK;
diff --git a/arch/x86/src/common/up_assert.c b/arch/x86/src/common/up_assert.c
index 7dcb30f..620b55c 100644
--- a/arch/x86/src/common/up_assert.c
+++ b/arch/x86/src/common/up_assert.c
@@ -160,16 +160,8 @@ static void up_dumpstate(void)
/* Get the limits on the user stack memory */
- if (rtcb->pid == 0) /* Check for CPU0 IDLE thread */
- {
- ustackbase = g_idle_topstack - 4;
- ustacksize = CONFIG_IDLETHREAD_STACKSIZE;
- }
- else
- {
- ustackbase = (uint32_t)rtcb->adj_stack_ptr;
- ustacksize = (uint32_t)rtcb->adj_stack_size;
- }
+ ustackbase = (uint32_t)rtcb->adj_stack_ptr;
+ ustacksize = (uint32_t)rtcb->adj_stack_size;
/* Get the limits on the interrupt stack memory */
diff --git a/arch/x86/src/i486/up_initialstate.c b/arch/x86/src/i486/up_initialstate.c
index d1c94b32..2a78809 100644
--- a/arch/x86/src/i486/up_initialstate.c
+++ b/arch/x86/src/i486/up_initialstate.c
@@ -49,18 +49,6 @@
#include "up_arch.h"
/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
* Public Functions
****************************************************************************/
@@ -81,6 +69,14 @@ void up_initial_state(struct tcb_s *tcb)
{
struct xcptcontext *xcp = &tcb->xcp;
+ /* Initialize the idle thread stack */
+
+ if (tcb->pid == 0)
+ {
+ up_use_stack(tcb, (void *)(g_idle_topstack -
+ CONFIG_IDLETHREAD_STACKSIZE), CONFIG_IDLETHREAD_STACKSIZE);
+ }
+
/* Initialize the initial exception register context structure */
memset(xcp, 0, sizeof(struct xcptcontext));
diff --git a/arch/x86/src/i486/up_usestack.c b/arch/x86/src/i486/up_usestack.c
index 71f94cc..89760e8 100644
--- a/arch/x86/src/i486/up_usestack.c
+++ b/arch/x86/src/i486/up_usestack.c
@@ -51,14 +51,6 @@
#include "up_internal.h"
/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
* Public Functions
****************************************************************************/
@@ -114,6 +106,17 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
tcb->stack_alloc_ptr = stack;
+ /* If stack debug is enabled, then fill the stack with a recognizable value
+ * that we can use later to test for high water marks.
+ */
+
+#ifdef CONFIG_STACK_COLORATION
+ if (tcb->pid != 0)
+ {
+ memset(tcb->stack_alloc_ptr, 0xaa, stack_size);
+ }
+#endif
+
/* The i486 uses a push-down stack: the stack grows toward loweraddresses
* in memory. The stack pointer register, points to the lowest, valid work
* address (the "top" of the stack). Items on the stack are referenced as
diff --git a/arch/x86_64/src/common/up_assert.c b/arch/x86_64/src/common/up_assert.c
index b092a27..8e76edc 100644
--- a/arch/x86_64/src/common/up_assert.c
+++ b/arch/x86_64/src/common/up_assert.c
@@ -123,16 +123,8 @@ static void up_dumpstate(void)
/* Get the limits on the user stack memory */
- if (rtcb->pid == 0)
- {
- ustackbase = g_idle_topstack - 8;
- ustacksize = CONFIG_IDLETHREAD_STACKSIZE;
- }
- else
- {
- ustackbase = (uint64_t)rtcb->adj_stack_ptr;
- ustacksize = (uint64_t)rtcb->adj_stack_size;
- }
+ ustackbase = (uint64_t)rtcb->adj_stack_ptr;
+ ustacksize = (uint64_t)rtcb->adj_stack_size;
/* Get the limits on the interrupt stack memory */
@@ -216,7 +208,7 @@ static void _up_assert(void)
{
/* Are we in an interrupt handler or the idle task? */
- if (g_current_regs || (this_task())->pid == 0)
+ if (g_current_regs || (running_task())->flink == NULL)
{
(void)up_irq_save();
for (; ; )
diff --git a/arch/x86_64/src/common/up_initialize.c b/arch/x86_64/src/common/up_initialize.c
index 6e0759c..8d29988 100644
--- a/arch/x86_64/src/common/up_initialize.c
+++ b/arch/x86_64/src/common/up_initialize.c
@@ -101,12 +101,6 @@ static void up_calibratedelay(void)
void up_initialize(void)
{
- struct tcb_s *rtcb = this_task();
-
- rtcb->adj_stack_size = CONFIG_IDLETHREAD_STACKSIZE;
- rtcb->stack_alloc_ptr =
- (void *)(g_idle_topstack - CONFIG_IDLETHREAD_STACKSIZE);
-
/* Initialize global variables */
g_current_regs = NULL;
diff --git a/arch/x86_64/src/intel64/up_initialstate.c b/arch/x86_64/src/intel64/up_initialstate.c
index a727b9b..caa7de3 100644
--- a/arch/x86_64/src/intel64/up_initialstate.c
+++ b/arch/x86_64/src/intel64/up_initialstate.c
@@ -35,18 +35,6 @@
#include "sched/sched.h"
/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
* Public Functions
****************************************************************************/
@@ -70,6 +58,14 @@ void up_initial_state(struct tcb_s *tcb)
struct xcptcontext *xcp = &tcb->xcp;
struct tcb_s *rtcb;
+ /* Initialize the idle thread stack */
+
+ if (tcb->pid == 0)
+ {
+ up_use_stack(tcb, (void *)(g_idle_topstack -
+ CONFIG_IDLETHREAD_STACKSIZE), CONFIG_IDLETHREAD_STACKSIZE);
+ }
+
/* Initialize the initial exception register context structure */
memset(xcp, 0, sizeof(struct xcptcontext));
diff --git a/arch/x86_64/src/intel64/up_usestack.c b/arch/x86_64/src/intel64/up_usestack.c
index bf3977f..eb5d727 100644
--- a/arch/x86_64/src/intel64/up_usestack.c
+++ b/arch/x86_64/src/intel64/up_usestack.c
@@ -36,14 +36,6 @@
#include "up_internal.h"
/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
* Public Functions
****************************************************************************/
@@ -99,6 +91,17 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
tcb->stack_alloc_ptr = stack;
+ /* If stack debug is enabled, then fill the stack with a recognizable value
+ * that we can use later to test for high water marks.
+ */
+
+#ifdef CONFIG_STACK_COLORATION
+ if (tcb->pid != 0)
+ {
+ memset(tcb->stack_alloc_ptr, 0xaa, stack_size);
+ }
+#endif
+
/* The intel64 uses a push-down stack: the stack grows toward lower
* addresses in memory. The stack pointer register, points to the lowest,
* valid work address (the "top" of the stack). Items on the stack are
diff --git a/arch/xtensa/src/common/xtensa_dumpstate.c b/arch/xtensa/src/common/xtensa_dumpstate.c
index cc21343..04109a0 100644
--- a/arch/xtensa/src/common/xtensa_dumpstate.c
+++ b/arch/xtensa/src/common/xtensa_dumpstate.c
@@ -180,16 +180,8 @@ void xtensa_dumpstate(void)
/* Get the limits on the user stack memory */
- if (rtcb->pid == 0) /* Check for CPU0 IDLE thread */
- {
- ustackbase = (uint32_t)&g_idlestack[IDLETHREAD_STACKWORDS - 1];
- ustacksize = IDLETHREAD_STACKSIZE;
- }
- else
- {
- ustackbase = (uint32_t)rtcb->adj_stack_ptr;
- ustacksize = (uint32_t)rtcb->adj_stack_size;
- }
+ ustackbase = (uint32_t)rtcb->adj_stack_ptr;
+ ustacksize = (uint32_t)rtcb->adj_stack_size;
/* Get the limits on the interrupt stack memory */
diff --git a/arch/xtensa/src/common/xtensa_initialstate.c b/arch/xtensa/src/common/xtensa_initialstate.c
index be63bb9..a6cc3c7 100644
--- a/arch/xtensa/src/common/xtensa_initialstate.c
+++ b/arch/xtensa/src/common/xtensa_initialstate.c
@@ -73,6 +73,13 @@ void up_initial_state(struct tcb_s *tcb)
{
struct xcptcontext *xcp = &tcb->xcp;
+ /* Initialize the idle thread stack */
+
+ if (tcb->pid == 0)
+ {
+ up_use_stack(tcb, g_idlestack, IDLETHREAD_STACKSIZE);
+ }
+
/* Initialize the initial exception register context structure */
memset(xcp, 0, sizeof(struct xcptcontext));
diff --git a/arch/xtensa/src/common/xtensa_usestack.c b/arch/xtensa/src/common/xtensa_usestack.c
index f599004..c43d78b 100644
--- a/arch/xtensa/src/common/xtensa_usestack.c
+++ b/arch/xtensa/src/common/xtensa_usestack.c
@@ -157,9 +157,12 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
* water marks.
*/
- up_stack_color((FAR void *)((uintptr_t)tcb->stack_alloc_ptr +
- sizeof(struct tls_info_s)),
- tcb->adj_stack_size - sizeof(struct tls_info_s));
+ if (tcb->pid != 0)
+ {
+ up_stack_color((FAR void *)((uintptr_t)tcb->stack_alloc_ptr +
+ sizeof(struct tls_info_s)),
+ size_of_stack - sizeof(struct tls_info_s));
+ }
#endif
return OK;
diff --git a/arch/z16/src/common/z16_usestack.c b/arch/z16/src/common/z16_usestack.c
index 7553e43..3c56125 100644
--- a/arch/z16/src/common/z16_usestack.c
+++ b/arch/z16/src/common/z16_usestack.c
@@ -36,14 +36,6 @@
#include "z16_internal.h"
/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
* Public Functions
****************************************************************************/
@@ -99,6 +91,17 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
tcb->stack_alloc_ptr = stack;
+ /* If stack debug is enabled, then fill the stack with a recognizable value
+ * that we can use later to test for high water marks.
+ */
+
+#ifdef CONFIG_STACK_COLORATION
+ if (tcb->pid != 0)
+ {
+ memset(tcb->stack_alloc_ptr, 0xaa, stack_size);
+ }
+#endif
+
/* The ZNEO uses a push-down stack: the stack grows toward lower
* addresses in memory. The stack pointer register, points to the
* lowest, valid work address (the "top" of the stack). Items on
diff --git a/arch/z80/src/common/z80_stackframe.c b/arch/z80/src/common/z80_stackframe.c
index d01d937..25d6ba4 100644
--- a/arch/z80/src/common/z80_stackframe.c
+++ b/arch/z80/src/common/z80_stackframe.c
@@ -103,9 +103,9 @@ FAR void *up_stack_frame(FAR struct tcb_s *tcb, size_t frame_size)
tcb->adj_stack_ptr = (uint8_t *)tcb->adj_stack_ptr - frame_size;
tcb->adj_stack_size -= frame_size;
- /* Reset the initial state */
+ /* Reset the initial stack pointer */
- up_initial_state(tcb);
+ tcb->xcp.regs[REG_RSP] = (chipreg_t)tcb->adj_stack_ptr;
/* And return a pointer to the allocated memory */
diff --git a/arch/z80/src/common/z80_usestack.c b/arch/z80/src/common/z80_usestack.c
index 2ce1829..a3fb4eb 100644
--- a/arch/z80/src/common/z80_usestack.c
+++ b/arch/z80/src/common/z80_usestack.c
@@ -35,14 +35,6 @@
#include "z80_internal.h"
/****************************************************************************
- * Private Types
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
* Public Functions
****************************************************************************/
@@ -98,6 +90,17 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
tcb->stack_alloc_ptr = stack;
+ /* If stack debug is enabled, then fill the stack with a recognizable value
+ * that we can use later to test for high water marks.
+ */
+
+#ifdef CONFIG_STACK_COLORATION
+ if (tcb->pid != 0)
+ {
+ memset(tcb->stack_alloc_ptr, 0xaa, stack_size);
+ }
+#endif
+
/* The Z80 uses a push-down stack: the stack grows toward lower
* addresses in memory. The stack pointer register, points to the
* lowest, valid work address (the "top" of the stack). Items on
diff --git a/arch/z80/src/z180/z180_initialstate.c b/arch/z80/src/z180/z180_initialstate.c
index bafae8a..fb883fb 100644
--- a/arch/z80/src/z180/z180_initialstate.c
+++ b/arch/z80/src/z180/z180_initialstate.c
@@ -32,18 +32,6 @@
#include "z80_arch.h"
/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
* Public Functions
****************************************************************************/
@@ -65,6 +53,14 @@ void up_initial_state(struct tcb_s *tcb)
{
struct xcptcontext *xcp = &tcb->xcp;
+ /* Initialize the idle thread stack */
+
+ if (tcb->pid == 0)
+ {
+ up_use_stack(tcb,
+ (void *)CONFIG_STACK_BASE, CONFIG_IDLETHREAD_STACKSIZE);
+ }
+
/* Initialize the initial exception register context structure */
memset(xcp, 0, sizeof(struct xcptcontext));
diff --git a/arch/z80/src/z80/z80_initialstate.c b/arch/z80/src/z80/z80_initialstate.c
index 1507f6f..a068a39 100644
--- a/arch/z80/src/z80/z80_initialstate.c
+++ b/arch/z80/src/z80/z80_initialstate.c
@@ -32,18 +32,6 @@
#include "z80_arch.h"
/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
* Public Functions
****************************************************************************/
@@ -65,6 +53,14 @@ void up_initial_state(struct tcb_s *tcb)
{
struct xcptcontext *xcp = &tcb->xcp;
+ /* Initialize the idle thread stack */
+
+ if (tcb->pid == 0)
+ {
+ up_use_stack(tcb,
+ (void *)CONFIG_STACK_BASE, CONFIG_IDLETHREAD_STACKSIZE);
+ }
+
/* Initialize the initial exception register context structure */
memset(xcp, 0, sizeof(struct xcptcontext));
diff --git a/boards/arm/cxd56xx/common/src/cxd56_crashdump.c b/boards/arm/cxd56xx/common/src/cxd56_crashdump.c
index 3ff34e6..7139cc7 100644
--- a/boards/arm/cxd56xx/common/src/cxd56_crashdump.c
+++ b/boards/arm/cxd56xx/common/src/cxd56_crashdump.c
@@ -197,16 +197,8 @@ void board_crashdump(uintptr_t currentsp, FAR void *tcb,
pdump->info.stacks.user.sp = currentsp;
}
- if (pdump->info.pid == 0)
- {
- pdump->info.stacks.user.top = g_idle_topstack - 4;
- pdump->info.stacks.user.size = CONFIG_IDLETHREAD_STACKSIZE;
- }
- else
- {
- pdump->info.stacks.user.top = (uint32_t)rtcb->adj_stack_ptr;
- pdump->info.stacks.user.size = (uint32_t)rtcb->adj_stack_size;
- }
+ pdump->info.stacks.user.top = (uint32_t)rtcb->adj_stack_ptr;
+ pdump->info.stacks.user.size = (uint32_t)rtcb->adj_stack_size;
#if CONFIG_ARCH_INTERRUPTSTACK > 3
/* Get the limits on the interrupt stack memory */
diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_bbsram.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_bbsram.c
index 0b51b21..6c8c324 100644
--- a/boards/arm/stm32/nucleo-f429zi/src/stm32_bbsram.c
+++ b/boards/arm/stm32/nucleo-f429zi/src/stm32_bbsram.c
@@ -449,16 +449,8 @@ void board_crashdump(uintptr_t currentsp, FAR void *tcb,
pdump->info.stacks.user.sp = currentsp;
}
- if (pdump->info.pid == 0)
- {
- pdump->info.stacks.user.top = g_idle_topstack - 4;
- pdump->info.stacks.user.size = CONFIG_IDLETHREAD_STACKSIZE;
- }
- else
- {
- pdump->info.stacks.user.top = (uint32_t) rtcb->adj_stack_ptr;
- pdump->info.stacks.user.size = (uint32_t) rtcb->adj_stack_size;
- }
+ pdump->info.stacks.user.top = (uint32_t) rtcb->adj_stack_ptr;
+ pdump->info.stacks.user.size = (uint32_t) rtcb->adj_stack_size;
#if CONFIG_ARCH_INTERRUPTSTACK > 3
/* Get the limits on the interrupt stack memory */
diff --git a/boards/arm/stm32f7/nucleo-144/src/stm32_bbsram.c b/boards/arm/stm32f7/nucleo-144/src/stm32_bbsram.c
index 2c8dd0e..51589ad 100644
--- a/boards/arm/stm32f7/nucleo-144/src/stm32_bbsram.c
+++ b/boards/arm/stm32f7/nucleo-144/src/stm32_bbsram.c
@@ -464,16 +464,8 @@ void board_crashdump(uintptr_t currentsp, FAR void *tcb,
pdump->info.stacks.user.sp = currentsp;
}
- if (pdump->info.pid == 0)
- {
- pdump->info.stacks.user.top = g_idle_topstack - 4;
- pdump->info.stacks.user.size = CONFIG_IDLETHREAD_STACKSIZE;
- }
- else
- {
- pdump->info.stacks.user.top = (uint32_t) rtcb->adj_stack_ptr;
- pdump->info.stacks.user.size = (uint32_t) rtcb->adj_stack_size;
- }
+ pdump->info.stacks.user.top = (uint32_t) rtcb->adj_stack_ptr;
+ pdump->info.stacks.user.size = (uint32_t) rtcb->adj_stack_size;
#if CONFIG_ARCH_INTERRUPTSTACK > 3
/* Get the limits on the interrupt stack memory */
diff --git a/boards/renesas/rx65n/rx65n-grrose/src/rx65n_sbram.c b/boards/renesas/rx65n/rx65n-grrose/src/rx65n_sbram.c
index 90094c7..80d1d89 100644
--- a/boards/renesas/rx65n/rx65n-grrose/src/rx65n_sbram.c
+++ b/boards/renesas/rx65n/rx65n-grrose/src/rx65n_sbram.c
@@ -403,16 +403,8 @@ void board_crashdump(uintptr_t currentsp, FAR void *tcb,
pdump->info.stacks.user.sp = currentsp;
}
- if (pdump->info.pid == 0)
- {
- pdump->info.stacks.user.top = g_idle_topstack - 4;
- pdump->info.stacks.user.size = CONFIG_IDLETHREAD_STACKSIZE;
- }
- else
- {
- pdump->info.stacks.user.top = (uint32_t) rtcb->adj_stack_ptr;
- pdump->info.stacks.user.size = (uint32_t) rtcb->adj_stack_size;
- }
+ pdump->info.stacks.user.top = (uint32_t) rtcb->adj_stack_ptr;
+ pdump->info.stacks.user.size = (uint32_t) rtcb->adj_stack_size;
#if CONFIG_ARCH_INTERRUPTSTACK > 3
/* Get the limits on the interrupt stack memory */
diff --git a/boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_sbram.c b/boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_sbram.c
index 10a69bd..98f03d6 100644
--- a/boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_sbram.c
+++ b/boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_sbram.c
@@ -401,16 +401,8 @@ void board_crashdump(uintptr_t currentsp, FAR void *tcb,
pdump->info.stacks.user.sp = currentsp;
}
- if (pdump->info.pid == 0)
- {
- pdump->info.stacks.user.top = g_idle_topstack - 4;
- pdump->info.stacks.user.size = CONFIG_IDLETHREAD_STACKSIZE;
- }
- else
- {
- pdump->info.stacks.user.top = (uint32_t) rtcb->adj_stack_ptr;
- pdump->info.stacks.user.size = (uint32_t) rtcb->adj_stack_size;
- }
+ pdump->info.stacks.user.top = (uint32_t) rtcb->adj_stack_ptr;
+ pdump->info.stacks.user.size = (uint32_t) rtcb->adj_stack_size;
#if CONFIG_ARCH_INTERRUPTSTACK > 3
/* Get the limits on the interrupt stack memory */