[GitHub] [mynewt-core] utzig commented on a change in pull request #2271: hw/drivers/i2s: Add I2S driver for STM32F1 family

[GitBox <gi...@apache.org>]

utzig commented on a change in pull request #2271:
URL: https://github.com/apache/mynewt-core/pull/2271#discussion_r411731930



##########
File path: hw/drivers/i2s/i2s_stm32f1/src/i2s_stm32f1.c
##########
@@ -0,0 +1,475 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <os/mynewt.h>
+#include <mcu/mcu.h>
+#include <mcu/stm32_hal.h>
+#include <i2s/i2s.h>
+#include <i2s/i2s_driver.h>
+#include <i2s_stm32f1/stm32_pin_cfg.h>
+#include <i2s_stm32f1/i2s_stm32f1.h>
+
+static struct stm32_i2s stm32_i2s2;
+static struct stm32_i2s stm32_i2s3;
+
+void
+i2s2_irq_handler(void)
+{
+    HAL_I2S_IRQHandler(&stm32_i2s2.hi2s);
+}
+
+void
+i2s3_irq_handler(void)
+{
+    HAL_I2S_IRQHandler(&stm32_i2s3.hi2s);
+}
+
+static void
+i2s2_clock_enable(bool enable)
+{
+#ifdef SPI2
+    if (enable) {
+        __HAL_RCC_SPI2_CLK_ENABLE();
+    } else {
+        __HAL_RCC_SPI2_CLK_DISABLE();
+    }
+#endif
+}
+
+static void
+i2s3_clock_enable(bool enable)
+{
+#ifdef SPI3
+    if (enable) {
+        __HAL_RCC_SPI3_CLK_ENABLE();
+    } else {
+        __HAL_RCC_SPI3_CLK_DISABLE();
+    }
+#endif
+}
+
+void
+HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+    struct stm32_i2s *i2s_data = (struct stm32_i2s *)hi2s;
+    struct i2s *i2s = i2s_data->i2s;
+    struct i2s_sample_buffer *processed_buffer = i2s_data->active_buffer;
+
+    i2s_data->active_buffer = i2s_driver_buffer_get(i2s);
+    if (i2s_data->active_buffer) {
+        HAL_I2S_Transmit_DMA(&i2s_data->hi2s,
+                             i2s_data->active_buffer->sample_data,
+                             i2s_data->active_buffer->sample_count);
+    } else {
+        i2s_driver_state_changed(i2s, I2S_STATE_OUT_OF_BUFFERS);
+    }
+    i2s_driver_buffer_put(i2s, processed_buffer);
+}
+
+void
+HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+    struct stm32_i2s *i2s_data = (struct stm32_i2s *)hi2s;
+    struct i2s *i2s = i2s_data->i2s;
+    struct i2s_sample_buffer *processed_buffer = i2s_data->active_buffer;
+
+    i2s_data->active_buffer = i2s_driver_buffer_get(i2s);
+    if (i2s_data->active_buffer) {
+        HAL_I2S_Receive_DMA(&i2s_data->hi2s,
+                            i2s_data->active_buffer->sample_data,
+                            i2s_data->active_buffer->capacity);
+    } else {
+        i2s_driver_state_changed(i2s, I2S_STATE_OUT_OF_BUFFERS);
+    }
+    processed_buffer->sample_count = processed_buffer->capacity;
+    i2s_driver_buffer_put(i2s, processed_buffer);
+}
+
+static void
+i2s2_dma_stream_irq_handler(void)
+{
+    HAL_DMA_IRQHandler(&stm32_i2s2.hdma_spi);
+}
+
+static void
+i2s3_dma_stream_irq_handler(void)
+{
+    HAL_DMA_IRQHandler(&stm32_i2s3.hdma_spi);
+}
+
+static void
+dma1_enable_clock(bool enable)
+{
+    if (enable) {
+        __HAL_RCC_DMA1_CLK_ENABLE();
+    } else {
+        __HAL_RCC_DMA1_CLK_DISABLE();
+    }
+}
+
+static void
+dma2_enable_clock(bool enable)
+{
+#ifdef __HAL_RCC_DMA2_CLK_DISABLE
+    if (enable) {
+        __HAL_RCC_DMA2_CLK_ENABLE();
+    } else {
+        __HAL_RCC_DMA2_CLK_DISABLE();
+    }
+#endif
+}
+
+static void
+i2s_init_interrupts(const struct i2s_cfg *cfg)
+{
+    NVIC_SetVector(cfg->hw_cfg->dma_channel_irq, (uint32_t)cfg->hw_cfg->dma_irq_handler);
+    HAL_NVIC_SetPriority(cfg->hw_cfg->dma_channel_irq, 5, 0);
+    HAL_NVIC_EnableIRQ(cfg->hw_cfg->dma_channel_irq);
+
+    /* I2S interrupt Init */
+    NVIC_SetVector(cfg->hw_cfg->i2s_irq, (uint32_t)cfg->hw_cfg->i2s_irq_handler);
+    HAL_NVIC_SetPriority(cfg->hw_cfg->i2s_irq, 5, 0);
+    HAL_NVIC_EnableIRQ(cfg->hw_cfg->i2s_irq);
+}
+
+static void
+i2s_init_pins(const struct stm32_i2s_pins *pins)
+{
+    GPIO_InitTypeDef gpio_init;
+
+    gpio_init = pins->ck_pin->hal_init;
+    hal_gpio_init_stm(pins->ck_pin->pin, &gpio_init);
+    gpio_init = pins->ws_pin->hal_init;
+    hal_gpio_init_stm(pins->ws_pin->pin, &gpio_init);
+    gpio_init = pins->sd_pin->hal_init;
+    hal_gpio_init_stm(pins->sd_pin->pin, &gpio_init);
+}
+
+static int
+stm32_i2s_init(struct i2s *i2s, const struct i2s_cfg *cfg)
+{
+    int rc = 0;
+    struct stm32_i2s *stm32_i2s;
+
+    i2s->direction = ((cfg->mode == I2S_MODE_MASTER_TX) ||
+                      (cfg->mode == I2S_MODE_SLAVE_TX)) ? I2S_OUT : I2S_IN;
+
+    if (cfg->data_format == I2S_DATAFORMAT_16B_EXTENDED ||
+        cfg->data_format == I2S_DATAFORMAT_16B) {
+        i2s->sample_size_in_bytes = 2;
+    } else {
+        i2s->sample_size_in_bytes = 4;
+    }
+
+    rc = i2s_init(i2s, cfg->pool);
+
+    if (rc != OS_OK) {
+        goto end;
+    }
+
+    stm32_i2s = cfg->hw_cfg->driver_data;
+    stm32_i2s->i2s = i2s;
+
+    i2s->sample_rate = cfg->sample_rate;
+    i2s->driver_data = stm32_i2s;
+
+    i2s_init_pins((struct stm32_i2s_pins *)&cfg->hw_cfg->pins);
+
+    cfg->hw_cfg->i2s_enable_clock(true);
+
+    stm32_i2s->hi2s.Instance = cfg->hw_cfg->i2s_base;
+    stm32_i2s->hi2s.Init.Mode = cfg->mode;
+    stm32_i2s->hi2s.Init.Standard = cfg->standard;
+    stm32_i2s->hi2s.Init.DataFormat = cfg->data_format;
+    stm32_i2s->hi2s.Init.MCLKOutput = I2S_MCLKOUTPUT_DISABLE;
+    stm32_i2s->hi2s.Init.AudioFreq = cfg->sample_rate;
+    stm32_i2s->hi2s.Init.CPOL = I2S_CPOL_LOW;
+
+    if (HAL_I2S_Init(&stm32_i2s->hi2s) != HAL_OK) {
+        rc = SYS_EUNKNOWN;
+        goto end;
+    }
+
+    cfg->hw_cfg->dma_enable_clock(true);
+
+    stm32_i2s->hdma_spi.Instance = cfg->hw_cfg->dma_channel_base;
+    if (cfg->mode == I2S_MODE_MASTER_TX || cfg->mode == I2S_MODE_SLAVE_TX) {
+        stm32_i2s->hdma_spi.Init.Direction = DMA_MEMORY_TO_PERIPH;
+    } else {
+        stm32_i2s->hdma_spi.Init.Direction = DMA_PERIPH_TO_MEMORY;
+    }
+    stm32_i2s->hdma_spi.Init.PeriphInc = DMA_PINC_DISABLE;
+    stm32_i2s->hdma_spi.Init.MemInc = DMA_MINC_ENABLE;
+    stm32_i2s->hdma_spi.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
+    stm32_i2s->hdma_spi.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
+    stm32_i2s->hdma_spi.Init.Mode = DMA_NORMAL;
+    stm32_i2s->hdma_spi.Init.Priority = DMA_PRIORITY_LOW;
+    if (HAL_DMA_Init(&stm32_i2s->hdma_spi) != HAL_OK) {
+        rc = SYS_EUNKNOWN;
+        goto end;
+    }
+
+    if (cfg->mode == I2S_MODE_MASTER_TX || cfg->mode == I2S_MODE_SLAVE_TX) {
+        __HAL_LINKDMA(&stm32_i2s->hi2s, hdmatx, stm32_i2s->hdma_spi);
+    } else {
+        __HAL_LINKDMA(&stm32_i2s->hi2s, hdmarx, stm32_i2s->hdma_spi);
+    }
+
+    i2s_init_interrupts(cfg);
+end:
+    return rc;

Review comment:
       With a `return` as the only thing here, you could also just `return` in the failure tests; it is no clear if it was done on purpose.




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