Re: [PR] arch/risc-v: implement SBI ipi extension [nuttx]

["xiaoxiang781216 (via GitHub)" <gi...@apache.org>]

xiaoxiang781216 commented on code in PR #12250:
URL: https://github.com/apache/nuttx/pull/12250#discussion_r1584010055


##########
arch/risc-v/src/common/supervisor/riscv_sbi.c:
##########
@@ -125,7 +106,8 @@ void riscv_sbi_set_timer(uint64_t stime_value)
 uint64_t riscv_sbi_get_time(void)
 {
 #ifdef CONFIG_NUTTSBI
-  return sbi_mcall_get_time();
+  return sbi_ecall(SBI_EXT_FIRMWARE, SBI_EXT_FIRMWARE_GET_MTIME, 0, 0,
+                   0, 0, 0, 0);
 #else
 #ifdef CONFIG_ARCH_RV64

Review Comment:
   let's merge `#else\n#ifdef` to `#elif defined`



##########
arch/risc-v/src/common/riscv_ipi.h:
##########
@@ -34,10 +34,12 @@
 
 static inline void riscv_ipi_send(int cpu)
 {
-#if defined(RISCV_IPI)
+#if defined(CONFIG_ARCH_USE_S_MODE)
+  riscv_sbi_send_ipi(0x1, cpu);
+#elif defined(RISCV_IPI)
   putreg32(1, (uintptr_t)RISCV_IPI + (4 * cpu));
 #else
-  PANIC();
+# error "No IPI support for this SoC"

Review Comment:
   two soaces after `#`



##########
arch/risc-v/src/nuttsbi/Kconfig:
##########
@@ -15,6 +15,12 @@ config NUTTSBI_HART_CNT
 	int "Amount of harts in SoC"
 	default 1
 
+config NUTTSBI_IPI_BASE
+	hex "MTIMECMP base address"

Review Comment:
   correct the  comment



##########
arch/risc-v/src/common/supervisor/riscv_sbi.c:
##########
@@ -127,6 +127,12 @@ uint64_t riscv_sbi_get_time(void)
 #endif
 }
 
+uintptr_t riscv_sbi_send_ipi(uint32_t hmask, uintptr_t hbase)
+{
+  return sbi_ecall(SBI_EXT_IPI, SBI_EXT_IPI_SEND_IPI,

Review Comment:
   does it wrok for OpenSBI



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