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Posted to commits@nuttx.apache.org by xi...@apache.org on 2021/09/22 01:25:22 UTC
[incubator-nuttx] branch master updated (0504e1d -> a9ff808)
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git.
from 0504e1d esp32-devkitc/wifinsh: Adds missing dependency on defconfig
new d5e306e stm32:Etablish device before enabling outputs
new 5e19ebb stm32F7:Etablish device before enabling outputs
new a8d5f21 stm32H7:Etablish device before enabling outputs
new a9ff808 stm32xx:sdmmc/sdio remove redundant GPIO config
The 4 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
arch/arm/src/stm32/stm32_gpio.c | 83 ++++++++++++++++++++++----------
arch/arm/src/stm32/stm32_sdio.c | 5 +-
arch/arm/src/stm32f7/stm32_gpio.c | 83 ++++++++++++++++++++++----------
arch/arm/src/stm32f7/stm32_sdmmc.c | 5 +-
arch/arm/src/stm32h7/stm32_gpio.c | 92 ++++++++++++++++++++++++++----------
arch/arm/src/stm32h7/stm32_sdmmc.c | 5 +-
arch/arm/src/stm32l4/stm32l4_sdmmc.c | 5 +-
7 files changed, 191 insertions(+), 87 deletions(-)
[incubator-nuttx] 01/04: stm32:Etablish device before enabling
outputs
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit d5e306e6f300cda9984bf03222a8ff36134b3213
Author: David Sidrane <Da...@NscDg.com>
AuthorDate: Thu Sep 16 10:43:59 2021 -0700
stm32:Etablish device before enabling outputs
This prevents gliches on changing to an output mode.
If not the ALT mux can be selecting a IP block that
is drving the line to say 0. Then the output is connected
to that source, then swithced to the correct source. This
produced a 430 nS glich on a F4 @168 Mhz. It was a enough
to corrupt an I2C device with a bus monitor.
---
arch/arm/src/stm32/stm32_gpio.c | 83 ++++++++++++++++++++++++++++-------------
1 file changed, 58 insertions(+), 25 deletions(-)
diff --git a/arch/arm/src/stm32/stm32_gpio.c b/arch/arm/src/stm32/stm32_gpio.c
index 3e59649..c5bc424 100644
--- a/arch/arm/src/stm32/stm32_gpio.c
+++ b/arch/arm/src/stm32/stm32_gpio.c
@@ -406,6 +406,7 @@ int stm32_configgpio(uint32_t cfgset)
uintptr_t base;
uint32_t regval;
uint32_t setting;
+ uint32_t alt_setting;
unsigned int regoffset;
unsigned int port;
unsigned int pin;
@@ -463,6 +464,41 @@ int stm32_configgpio(uint32_t cfgset)
flags = enter_critical_section();
+ /* Determine the alternate function (Only alternate function pins) */
+
+ if (pinmode == GPIO_MODER_ALT)
+ {
+ alt_setting = (cfgset & GPIO_AF_MASK) >> GPIO_AF_SHIFT;
+ }
+ else
+ {
+ alt_setting = 0;
+ }
+
+ /* Set the alternate function (Only alternate function pins)
+ * This is done before configuring the Outputs on a change to
+ * an Alternate function.
+ */
+
+ if (alt_setting != 0)
+ {
+ if (pin < 8)
+ {
+ regoffset = STM32_GPIO_AFRL_OFFSET;
+ pos = pin;
+ }
+ else
+ {
+ regoffset = STM32_GPIO_AFRH_OFFSET;
+ pos = pin - 8;
+ }
+
+ regval = getreg32(base + regoffset);
+ regval &= ~GPIO_AFR_MASK(pos);
+ regval |= (alt_setting << GPIO_AFR_SHIFT(pos));
+ putreg32(regval, base + regoffset);
+ }
+
/* Now apply the configuration to the mode register */
regval = getreg32(base + STM32_GPIO_MODER_OFFSET);
@@ -496,32 +532,29 @@ int stm32_configgpio(uint32_t cfgset)
regval |= (setting << GPIO_PUPDR_SHIFT(pin));
putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET);
- /* Set the alternate function (Only alternate function pins) */
-
- if (pinmode == GPIO_MODER_ALT)
- {
- setting = (cfgset & GPIO_AF_MASK) >> GPIO_AF_SHIFT;
- }
- else
- {
- setting = 0;
- }
-
- if (pin < 8)
- {
- regoffset = STM32_GPIO_AFRL_OFFSET;
- pos = pin;
- }
- else
- {
- regoffset = STM32_GPIO_AFRH_OFFSET;
- pos = pin - 8;
- }
+ /* Set the alternate function (Only alternate function pins)
+ * This is done after configuring the the pin's connection
+ * on a change away from an Alternate function.
+ */
- regval = getreg32(base + regoffset);
- regval &= ~GPIO_AFR_MASK(pos);
- regval |= (setting << GPIO_AFR_SHIFT(pos));
- putreg32(regval, base + regoffset);
+ if (alt_setting == 0)
+ {
+ if (pin < 8)
+ {
+ regoffset = STM32_GPIO_AFRL_OFFSET;
+ pos = pin;
+ }
+ else
+ {
+ regoffset = STM32_GPIO_AFRH_OFFSET;
+ pos = pin - 8;
+ }
+
+ regval = getreg32(base + regoffset);
+ regval &= ~GPIO_AFR_MASK(pos);
+ regval |= (alt_setting << GPIO_AFR_SHIFT(pos));
+ putreg32(regval, base + regoffset);
+ }
/* Set speed (Only outputs and alternate function pins) */
[incubator-nuttx] 03/04: stm32H7:Etablish device before enabling
outputs
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit a8d5f21f8196c56c661adcbb7767cfa2a892fa5f
Author: David Sidrane <Da...@NscDg.com>
AuthorDate: Fri Sep 17 06:35:49 2021 -0700
stm32H7:Etablish device before enabling outputs
This prevents gliches on changing to an output mode.
If not the ALT mux can be selecting a IP block that
is drving the line to say 0. Then the output is connected
to that source, then swithced to the correct source.
---
arch/arm/src/stm32h7/stm32_gpio.c | 92 ++++++++++++++++++++++++++++-----------
1 file changed, 67 insertions(+), 25 deletions(-)
diff --git a/arch/arm/src/stm32h7/stm32_gpio.c b/arch/arm/src/stm32h7/stm32_gpio.c
index f2da8fd..cf5180a 100644
--- a/arch/arm/src/stm32h7/stm32_gpio.c
+++ b/arch/arm/src/stm32h7/stm32_gpio.c
@@ -140,6 +140,7 @@ int stm32_configgpio(uint32_t cfgset)
uintptr_t base;
uint32_t regval;
uint32_t setting;
+ uint32_t alt_setting;
unsigned int regoffset;
unsigned int port;
unsigned int pin;
@@ -201,6 +202,50 @@ int stm32_configgpio(uint32_t cfgset)
flags = enter_critical_section();
+ /* Determine the alternate function (Only alternate function pins) */
+
+ if (pinmode == GPIO_MODER_ALT)
+ {
+ setting = (cfgset & GPIO_AF_MASK) >> GPIO_AF_SHIFT;
+ }
+ else
+ {
+ setting = 0;
+ }
+
+ if (pinmode == GPIO_MODER_ALT)
+ {
+ alt_setting = (cfgset & GPIO_AF_MASK) >> GPIO_AF_SHIFT;
+ }
+ else
+ {
+ alt_setting = 0;
+ }
+
+ /* Set the alternate function (Only alternate function pins)
+ * This is done before configuring the Outputs on a change to
+ * an Alternate function.
+ */
+
+ if (alt_setting != 0)
+ {
+ if (pin < 8)
+ {
+ regoffset = STM32_GPIO_AFRL_OFFSET;
+ pos = pin;
+ }
+ else
+ {
+ regoffset = STM32_GPIO_AFRH_OFFSET;
+ pos = pin - 8;
+ }
+
+ regval = getreg32(base + regoffset);
+ regval &= ~GPIO_AFR_MASK(pos);
+ regval |= (alt_setting << GPIO_AFR_SHIFT(pos));
+ putreg32(regval, base + regoffset);
+ }
+
/* Now apply the configuration to the mode register */
regval = getreg32(base + STM32_GPIO_MODER_OFFSET);
@@ -234,32 +279,29 @@ int stm32_configgpio(uint32_t cfgset)
regval |= (setting << GPIO_PUPDR_SHIFT(pin));
putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET);
- /* Set the alternate function (Only alternate function pins) */
-
- if (pinmode == GPIO_MODER_ALT)
- {
- setting = (cfgset & GPIO_AF_MASK) >> GPIO_AF_SHIFT;
- }
- else
- {
- setting = 0;
- }
-
- if (pin < 8)
- {
- regoffset = STM32_GPIO_AFRL_OFFSET;
- pos = pin;
- }
- else
- {
- regoffset = STM32_GPIO_AFRH_OFFSET;
- pos = pin - 8;
- }
+ /* Set the alternate function (Only alternate function pins)
+ * This is done after configuring the the pin's connection
+ * on a change away from an Alternate function.
+ */
- regval = getreg32(base + regoffset);
- regval &= ~GPIO_AFR_MASK(pos);
- regval |= (setting << GPIO_AFR_SHIFT(pos));
- putreg32(regval, base + regoffset);
+ if (alt_setting == 0)
+ {
+ if (pin < 8)
+ {
+ regoffset = STM32_GPIO_AFRL_OFFSET;
+ pos = pin;
+ }
+ else
+ {
+ regoffset = STM32_GPIO_AFRH_OFFSET;
+ pos = pin - 8;
+ }
+
+ regval = getreg32(base + regoffset);
+ regval &= ~GPIO_AFR_MASK(pos);
+ regval |= (alt_setting << GPIO_AFR_SHIFT(pos));
+ putreg32(regval, base + regoffset);
+ }
/* Set speed (Only outputs and alternate function pins) */
[incubator-nuttx] 04/04: stm32xx:sdmmc/sdio remove redundant GPIO
config
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit a9ff808dd1acd55f7c76644d391d3da21973badd
Author: David Sidrane <Da...@NscDg.com>
AuthorDate: Tue Sep 21 11:11:23 2021 -0700
stm32xx:sdmmc/sdio remove redundant GPIO config
The stm32_gpiosetevent calls stm32_configgpio. So
the pin is infact restored to the SDMMC/SDIO D0.
The seconday init, dropped interrupts in a debug
build with HW stack checking on after the GPIO glich
fixes and that was how it was detected.
---
arch/arm/src/stm32/stm32_sdio.c | 5 ++---
arch/arm/src/stm32f7/stm32_sdmmc.c | 5 ++---
arch/arm/src/stm32h7/stm32_sdmmc.c | 5 ++---
arch/arm/src/stm32l4/stm32l4_sdmmc.c | 5 ++---
4 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/arch/arm/src/stm32/stm32_sdio.c b/arch/arm/src/stm32/stm32_sdio.c
index 3b38f7d..cce6936 100644
--- a/arch/arm/src/stm32/stm32_sdio.c
+++ b/arch/arm/src/stm32/stm32_sdio.c
@@ -667,19 +667,18 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask,
pinset = GPIO_SDIO_D0 & (GPIO_PORT_MASK | GPIO_PIN_MASK);
pinset |= (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI);
- /* Arm the SDIO_D Ready and install Isr */
+ /* Arm the SDIO_D0 Ready and install Isr */
stm32_gpiosetevent(pinset, true, false, false,
stm32_rdyinterrupt, priv);
}
- /* Disarm SDIO_D ready */
+ /* Disarm SDIO_D0 ready and return it to SDIO D0 */
if ((wkupevent & SDIOWAIT_WRCOMPLETE) != 0)
{
stm32_gpiosetevent(GPIO_SDIO_D0, false, false, false,
NULL, NULL);
- stm32_configgpio(GPIO_SDIO_D0);
}
#endif
diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.c b/arch/arm/src/stm32f7/stm32_sdmmc.c
index 920a02a..0126f87 100644
--- a/arch/arm/src/stm32f7/stm32_sdmmc.c
+++ b/arch/arm/src/stm32f7/stm32_sdmmc.c
@@ -862,19 +862,18 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask,
GPIO_PUPD_MASK);
pinset |= (GPIO_INPUT | GPIO_EXTI);
- /* Arm the SDMMC_D Ready and install Isr */
+ /* Arm the SDMMC_D0 Ready and install Isr */
stm32_gpiosetevent(pinset, true, false, false,
stm32_sdmmc_rdyinterrupt, priv);
}
- /* Disarm SDMMC_D ready */
+ /* Disarm SDMMC_D0 ready and return it to SDMMC D0 */
if ((wkupevent & SDIOWAIT_WRCOMPLETE) != 0)
{
stm32_gpiosetevent(priv->d0_gpio, false, false, false,
NULL, NULL);
- stm32_configgpio(priv->d0_gpio);
}
#endif
diff --git a/arch/arm/src/stm32h7/stm32_sdmmc.c b/arch/arm/src/stm32h7/stm32_sdmmc.c
index 795c4d7..09c65cf 100644
--- a/arch/arm/src/stm32h7/stm32_sdmmc.c
+++ b/arch/arm/src/stm32h7/stm32_sdmmc.c
@@ -801,19 +801,18 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask,
GPIO_PUPD_MASK);
pinset |= (GPIO_INPUT | GPIO_EXTI);
- /* Arm the SDMMC_D Ready and install Isr */
+ /* Arm the SDMMC_D0 Ready and install Isr */
stm32_gpiosetevent(pinset, true, false, false,
stm32_sdmmc_rdyinterrupt, priv);
}
- /* Disarm SDMMC_D ready */
+ /* Disarm SDMMC_D0 ready and return it to SDMMC D0 */
if ((wkupevent & SDIOWAIT_WRCOMPLETE) != 0)
{
stm32_gpiosetevent(priv->d0_gpio, false, false, false,
NULL, NULL);
- stm32_configgpio(priv->d0_gpio);
}
#endif
diff --git a/arch/arm/src/stm32l4/stm32l4_sdmmc.c b/arch/arm/src/stm32l4/stm32l4_sdmmc.c
index 77f6d70..be92f71 100644
--- a/arch/arm/src/stm32l4/stm32l4_sdmmc.c
+++ b/arch/arm/src/stm32l4/stm32l4_sdmmc.c
@@ -782,19 +782,18 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask,
pinset = priv->d0_gpio & (GPIO_PORT_MASK | GPIO_PIN_MASK);
pinset |= (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI);
- /* Arm the SDMMC_D Ready and install ISR */
+ /* Arm the SDMMC_D0 Ready and install ISR */
stm32_gpiosetevent(pinset, true, false, false,
stm32_sdmmc_rdyinterrupt, priv);
}
- /* Disarm SDMMC_D ready */
+ /* Disarm SDMMC_D0 ready and return it to SDMMC D0 */
if ((wkupevent & SDIOWAIT_WRCOMPLETE) != 0)
{
stm32_gpiosetevent(priv->d0_gpio, false, false, false,
NULL, NULL);
- stm32_configgpio(priv->d0_gpio);
}
#endif
[incubator-nuttx] 02/04: stm32F7:Etablish device before enabling
outputs
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 5e19ebb818056f3433f7501a819673b85c9c6ea8
Author: David Sidrane <Da...@NscDg.com>
AuthorDate: Fri Sep 17 06:35:00 2021 -0700
stm32F7:Etablish device before enabling outputs
This prevents gliches on changing to an output mode.
If not the ALT mux can be selecting a IP block that
is drving the line to say 0. Then the output is connected
to that source, then swithced to the correct source.
---
arch/arm/src/stm32f7/stm32_gpio.c | 83 +++++++++++++++++++++++++++------------
1 file changed, 58 insertions(+), 25 deletions(-)
diff --git a/arch/arm/src/stm32f7/stm32_gpio.c b/arch/arm/src/stm32f7/stm32_gpio.c
index a3b1a01..162776b 100644
--- a/arch/arm/src/stm32f7/stm32_gpio.c
+++ b/arch/arm/src/stm32f7/stm32_gpio.c
@@ -114,6 +114,7 @@ int stm32_configgpio(uint32_t cfgset)
uintptr_t base;
uint32_t regval;
uint32_t setting;
+ uint32_t alt_setting;
unsigned int regoffset;
unsigned int port;
unsigned int pin;
@@ -171,6 +172,41 @@ int stm32_configgpio(uint32_t cfgset)
flags = enter_critical_section();
+ /* Determine the alternate function (Only alternate function pins) */
+
+ if (pinmode == GPIO_MODER_ALT)
+ {
+ alt_setting = (cfgset & GPIO_AF_MASK) >> GPIO_AF_SHIFT;
+ }
+ else
+ {
+ alt_setting = 0;
+ }
+
+ /* Set the alternate function (Only alternate function pins)
+ * This is done before configuring the Outputs on a change to
+ * an Alternate function.
+ */
+
+ if (alt_setting != 0)
+ {
+ if (pin < 8)
+ {
+ regoffset = STM32_GPIO_AFRL_OFFSET;
+ pos = pin;
+ }
+ else
+ {
+ regoffset = STM32_GPIO_AFRH_OFFSET;
+ pos = pin - 8;
+ }
+
+ regval = getreg32(base + regoffset);
+ regval &= ~GPIO_AFR_MASK(pos);
+ regval |= (alt_setting << GPIO_AFR_SHIFT(pos));
+ putreg32(regval, base + regoffset);
+ }
+
/* Now apply the configuration to the mode register */
regval = getreg32(base + STM32_GPIO_MODER_OFFSET);
@@ -204,32 +240,29 @@ int stm32_configgpio(uint32_t cfgset)
regval |= (setting << GPIO_PUPDR_SHIFT(pin));
putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET);
- /* Set the alternate function (Only alternate function pins) */
-
- if (pinmode == GPIO_MODER_ALT)
- {
- setting = (cfgset & GPIO_AF_MASK) >> GPIO_AF_SHIFT;
- }
- else
- {
- setting = 0;
- }
-
- if (pin < 8)
- {
- regoffset = STM32_GPIO_AFRL_OFFSET;
- pos = pin;
- }
- else
- {
- regoffset = STM32_GPIO_AFRH_OFFSET;
- pos = pin - 8;
- }
+ /* Set the alternate function (Only alternate function pins)
+ * This is done after configuring the the pin's connection
+ * on a change away from an Alternate function.
+ */
- regval = getreg32(base + regoffset);
- regval &= ~GPIO_AFR_MASK(pos);
- regval |= (setting << GPIO_AFR_SHIFT(pos));
- putreg32(regval, base + regoffset);
+ if (alt_setting == 0)
+ {
+ if (pin < 8)
+ {
+ regoffset = STM32_GPIO_AFRL_OFFSET;
+ pos = pin;
+ }
+ else
+ {
+ regoffset = STM32_GPIO_AFRH_OFFSET;
+ pos = pin - 8;
+ }
+
+ regval = getreg32(base + regoffset);
+ regval &= ~GPIO_AFR_MASK(pos);
+ regval |= (alt_setting << GPIO_AFR_SHIFT(pos));
+ putreg32(regval, base + regoffset);
+ }
/* Set speed (Only outputs and alternate function pins) */