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Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2022/07/23 10:25:32 UTC
[GitHub] [incubator-nuttx] raiden00pl opened a new pull request, #6692: stm32f0l0g0: fixes for SPI half suplex
raiden00pl opened a new pull request, #6692:
URL: https://github.com/apache/incubator-nuttx/pull/6692
## Summary
- stm32f0l0g0/hardware/stm32_spi.h: remove unused definitions
- stm32f0l0g0/stm32_spi.c: add missing SPI mode config and fix ifdef
- stm32f0l0g0/stm32_spi.c: remove unused spi_readbyte function
- stm32f0l0g0/stm32_spi.c: fix receiving data for half duplex mode
## Impact
rx for SPI half duplex works correctly now
## Testing
read data from MEMS sensor in SPI 3-wire mode
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[GitHub] [incubator-nuttx] raiden00pl commented on a diff in pull request #6692: stm32f0l0g0: fixes for SPI half duplex
Posted by GitBox <gi...@apache.org>.
raiden00pl commented on code in PR #6692:
URL: https://github.com/apache/incubator-nuttx/pull/6692#discussion_r928214036
##########
arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h:
##########
@@ -96,42 +96,6 @@
# define STM32_SPI3_I2SPR (STM32_SPI3_BASE + STM32_SPI_I2SPR_OFFSET)
#endif
-#if STM32_NSPI > 3
-# define STM32_SPI4_CR1 (STM32_SPI4_BASE + STM32_SPI_CR1_OFFSET)
-# define STM32_SPI4_CR2 (STM32_SPI4_BASE + STM32_SPI_CR2_OFFSET)
-# define STM32_SPI4_SR (STM32_SPI4_BASE + STM32_SPI_SR_OFFSET)
-# define STM32_SPI4_DR (STM32_SPI4_BASE + STM32_SPI_DR_OFFSET)
-# define STM32_SPI4_CRCPR (STM32_SPI4_BASE + STM32_SPI_CRCPR_OFFSET)
-# define STM32_SPI4_RXCRCR (STM32_SPI4_BASE + STM32_SPI_RXCRCR_OFFSET)
-# define STM32_SPI4_TXCRCR (STM32_SPI4_BASE + STM32_SPI_TXCRCR_OFFSET)
-# define STM32_SPI4_I2SCFGR (STM32_SPI4_BASE + STM32_SPI_I2SCFGR_OFFSET)
-# define STM32_SPI4_I2SPR (STM32_SPI4_BASE + STM32_SPI_I2SPR_OFFSET)
-#endif
-
-#if STM32_NSPI > 4
-# define STM32_SPI5_CR1 (STM32_SPI5_BASE + STM32_SPI_CR1_OFFSET)
-# define STM32_SPI5_CR2 (STM32_SPI5_BASE + STM32_SPI_CR2_OFFSET)
-# define STM32_SPI5_SR (STM32_SPI5_BASE + STM32_SPI_SR_OFFSET)
-# define STM32_SPI5_DR (STM32_SPI5_BASE + STM32_SPI_DR_OFFSET)
-# define STM32_SPI5_CRCPR (STM32_SPI5_BASE + STM32_SPI_CRCPR_OFFSET)
-# define STM32_SPI5_RXCRCR (STM32_SPI5_BASE + STM32_SPI_RXCRCR_OFFSET)
-# define STM32_SPI5_TXCRCR (STM32_SPI5_BASE + STM32_SPI_TXCRCR_OFFSET)
-# define STM32_SPI5_I2SCFGR (STM32_SPI5_BASE + STM32_SPI_I2SCFGR_OFFSET)
-# define STM32_SPI5_I2SPR (STM32_SPI5_BASE + STM32_SPI_I2SPR_OFFSET)
-#endif
-
-#if STM32_NSPI > 5
-# define STM32_SPI6_CR1 (STM32_SPI6_BASE + STM32_SPI_CR1_OFFSET)
-# define STM32_SPI6_CR2 (STM32_SPI6_BASE + STM32_SPI_CR2_OFFSET)
-# define STM32_SPI6_SR (STM32_SPI6_BASE + STM32_SPI_SR_OFFSET)
-# define STM32_SPI6_DR (STM32_SPI6_BASE + STM32_SPI_DR_OFFSET)
-# define STM32_SPI6_CRCPR (STM32_SPI6_BASE + STM32_SPI_CRCPR_OFFSET)
-# define STM32_SPI6_RXCRCR (STM32_SPI6_BASE + STM32_SPI_RXCRCR_OFFSET)
-# define STM32_SPI6_TXCRCR (STM32_SPI6_BASE + STM32_SPI_TXCRCR_OFFSET)
-# define STM32_SPI6_I2SCFGR (STM32_SPI6_BASE + STM32_SPI_I2SCFGR_OFFSET)
-# define STM32_SPI6_I2SPR (STM32_SPI6_BASE + STM32_SPI_I2SPR_OFFSET)
-#endif
-
Review Comment:
I see now that ST has introduced STM32G0Bx and STM32G0Cx chips that have SPI3. I'll restore SPI3 definitions and add support for it in the next PR (removed in https://github.com/apache/incubator-nuttx/pull/6622/commits/98d62e3e12fef192b3b67fb21547a063500ec975). For sure there is no SPI4/5/6.
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[GitHub] [incubator-nuttx] raiden00pl commented on a diff in pull request #6692: stm32f0l0g0: fixes for SPI half duplex
Posted by GitBox <gi...@apache.org>.
raiden00pl commented on code in PR #6692:
URL: https://github.com/apache/incubator-nuttx/pull/6692#discussion_r928214036
##########
arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h:
##########
@@ -96,42 +96,6 @@
# define STM32_SPI3_I2SPR (STM32_SPI3_BASE + STM32_SPI_I2SPR_OFFSET)
#endif
-#if STM32_NSPI > 3
-# define STM32_SPI4_CR1 (STM32_SPI4_BASE + STM32_SPI_CR1_OFFSET)
-# define STM32_SPI4_CR2 (STM32_SPI4_BASE + STM32_SPI_CR2_OFFSET)
-# define STM32_SPI4_SR (STM32_SPI4_BASE + STM32_SPI_SR_OFFSET)
-# define STM32_SPI4_DR (STM32_SPI4_BASE + STM32_SPI_DR_OFFSET)
-# define STM32_SPI4_CRCPR (STM32_SPI4_BASE + STM32_SPI_CRCPR_OFFSET)
-# define STM32_SPI4_RXCRCR (STM32_SPI4_BASE + STM32_SPI_RXCRCR_OFFSET)
-# define STM32_SPI4_TXCRCR (STM32_SPI4_BASE + STM32_SPI_TXCRCR_OFFSET)
-# define STM32_SPI4_I2SCFGR (STM32_SPI4_BASE + STM32_SPI_I2SCFGR_OFFSET)
-# define STM32_SPI4_I2SPR (STM32_SPI4_BASE + STM32_SPI_I2SPR_OFFSET)
-#endif
-
-#if STM32_NSPI > 4
-# define STM32_SPI5_CR1 (STM32_SPI5_BASE + STM32_SPI_CR1_OFFSET)
-# define STM32_SPI5_CR2 (STM32_SPI5_BASE + STM32_SPI_CR2_OFFSET)
-# define STM32_SPI5_SR (STM32_SPI5_BASE + STM32_SPI_SR_OFFSET)
-# define STM32_SPI5_DR (STM32_SPI5_BASE + STM32_SPI_DR_OFFSET)
-# define STM32_SPI5_CRCPR (STM32_SPI5_BASE + STM32_SPI_CRCPR_OFFSET)
-# define STM32_SPI5_RXCRCR (STM32_SPI5_BASE + STM32_SPI_RXCRCR_OFFSET)
-# define STM32_SPI5_TXCRCR (STM32_SPI5_BASE + STM32_SPI_TXCRCR_OFFSET)
-# define STM32_SPI5_I2SCFGR (STM32_SPI5_BASE + STM32_SPI_I2SCFGR_OFFSET)
-# define STM32_SPI5_I2SPR (STM32_SPI5_BASE + STM32_SPI_I2SPR_OFFSET)
-#endif
-
-#if STM32_NSPI > 5
-# define STM32_SPI6_CR1 (STM32_SPI6_BASE + STM32_SPI_CR1_OFFSET)
-# define STM32_SPI6_CR2 (STM32_SPI6_BASE + STM32_SPI_CR2_OFFSET)
-# define STM32_SPI6_SR (STM32_SPI6_BASE + STM32_SPI_SR_OFFSET)
-# define STM32_SPI6_DR (STM32_SPI6_BASE + STM32_SPI_DR_OFFSET)
-# define STM32_SPI6_CRCPR (STM32_SPI6_BASE + STM32_SPI_CRCPR_OFFSET)
-# define STM32_SPI6_RXCRCR (STM32_SPI6_BASE + STM32_SPI_RXCRCR_OFFSET)
-# define STM32_SPI6_TXCRCR (STM32_SPI6_BASE + STM32_SPI_TXCRCR_OFFSET)
-# define STM32_SPI6_I2SCFGR (STM32_SPI6_BASE + STM32_SPI_I2SCFGR_OFFSET)
-# define STM32_SPI6_I2SPR (STM32_SPI6_BASE + STM32_SPI_I2SPR_OFFSET)
-#endif
-
Review Comment:
I see now that ST has introduced STM32G0Bx and STM32G0Cx chips that have SPI3. I'll restore SPI3 definitions and add support for it in the next PR.
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[GitHub] [incubator-nuttx] pkarashchenko commented on a diff in pull request #6692: stm32f0l0g0: fixes for SPI half duplex
Posted by GitBox <gi...@apache.org>.
pkarashchenko commented on code in PR #6692:
URL: https://github.com/apache/incubator-nuttx/pull/6692#discussion_r928292251
##########
arch/arm/src/stm32f0l0g0/stm32_spi.c:
##########
@@ -428,6 +433,62 @@ static inline void spi_putreg(struct stm32_spidev_s *priv,
putreg16(value, priv->spibase + offset);
}
+/****************************************************************************
+ * Name: spi_rx_mode
+ *
+ * Description:
+ * Activate SPI RX or SPI TX for the half-duplex mode
+ *
+ ****************************************************************************/
+
+static inline void spi_rx_mode(struct stm32_spidev_s *priv, bool enable)
+{
+ if (enable == true)
+ {
+ /* Enable RX */
+
+ if (priv->rx_mode == false)
+ {
+ /* Disable SPI */
+
+ spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE);
+
+ /* Disable output for half-duplex mode - SPI starts to
+ * automatically output clocks.
+ */
+
+ spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_BIDIOE);
+
+ /* Enable SPI */
+
+ spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0);
+
+ priv->rx_mode = true;
+ }
+ }
+ else
+ {
+ /* Enable TX */
+
+ if (priv->rx_mode == true)
Review Comment:
```suggestion
if (priv->rx_mode)
```
##########
arch/arm/src/stm32f0l0g0/stm32_spi.c:
##########
@@ -428,6 +433,62 @@ static inline void spi_putreg(struct stm32_spidev_s *priv,
putreg16(value, priv->spibase + offset);
}
+/****************************************************************************
+ * Name: spi_rx_mode
+ *
+ * Description:
+ * Activate SPI RX or SPI TX for the half-duplex mode
+ *
+ ****************************************************************************/
+
+static inline void spi_rx_mode(struct stm32_spidev_s *priv, bool enable)
+{
+ if (enable == true)
+ {
+ /* Enable RX */
+
+ if (priv->rx_mode == false)
Review Comment:
```suggestion
if (!priv->rx_mode)
```
##########
arch/arm/src/stm32f0l0g0/stm32_spi.c:
##########
@@ -428,6 +433,62 @@ static inline void spi_putreg(struct stm32_spidev_s *priv,
putreg16(value, priv->spibase + offset);
}
+/****************************************************************************
+ * Name: spi_rx_mode
+ *
+ * Description:
+ * Activate SPI RX or SPI TX for the half-duplex mode
+ *
+ ****************************************************************************/
+
+static inline void spi_rx_mode(struct stm32_spidev_s *priv, bool enable)
+{
+ if (enable == true)
Review Comment:
```suggestion
if (enable)
```
##########
arch/arm/src/stm32f0l0g0/stm32_spi.c:
##########
@@ -1326,12 +1356,32 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd)
{
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev;
uint32_t regval;
- uint32_t ret;
+ uint32_t ret = 0;
DEBUGASSERT(priv && priv->spibase);
- spi_writeword(priv, (uint16_t)(wd & 0xffff));
- ret = (uint32_t)spi_readword(priv);
+ if (priv->config != HALF_DUPLEX)
+ {
+ spi_writeword(priv, (uint16_t)(wd & 0xffff));
+ ret = (uint32_t)spi_readword(priv);
+ }
+ else
+ {
+ /* In half duplex we must send data and receive data in separate
+ * spi_send() calls.
+ */
+
+ if (priv->rx_now == false)
Review Comment:
```suggestion
if (!priv->rx_now)
```
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[GitHub] [incubator-nuttx] acassis commented on a diff in pull request #6692: stm32f0l0g0: fixes for SPI half duplex
Posted by GitBox <gi...@apache.org>.
acassis commented on code in PR #6692:
URL: https://github.com/apache/incubator-nuttx/pull/6692#discussion_r928158975
##########
arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h:
##########
@@ -96,42 +96,6 @@
# define STM32_SPI3_I2SPR (STM32_SPI3_BASE + STM32_SPI_I2SPR_OFFSET)
#endif
-#if STM32_NSPI > 3
-# define STM32_SPI4_CR1 (STM32_SPI4_BASE + STM32_SPI_CR1_OFFSET)
-# define STM32_SPI4_CR2 (STM32_SPI4_BASE + STM32_SPI_CR2_OFFSET)
-# define STM32_SPI4_SR (STM32_SPI4_BASE + STM32_SPI_SR_OFFSET)
-# define STM32_SPI4_DR (STM32_SPI4_BASE + STM32_SPI_DR_OFFSET)
-# define STM32_SPI4_CRCPR (STM32_SPI4_BASE + STM32_SPI_CRCPR_OFFSET)
-# define STM32_SPI4_RXCRCR (STM32_SPI4_BASE + STM32_SPI_RXCRCR_OFFSET)
-# define STM32_SPI4_TXCRCR (STM32_SPI4_BASE + STM32_SPI_TXCRCR_OFFSET)
-# define STM32_SPI4_I2SCFGR (STM32_SPI4_BASE + STM32_SPI_I2SCFGR_OFFSET)
-# define STM32_SPI4_I2SPR (STM32_SPI4_BASE + STM32_SPI_I2SPR_OFFSET)
-#endif
-
-#if STM32_NSPI > 4
-# define STM32_SPI5_CR1 (STM32_SPI5_BASE + STM32_SPI_CR1_OFFSET)
-# define STM32_SPI5_CR2 (STM32_SPI5_BASE + STM32_SPI_CR2_OFFSET)
-# define STM32_SPI5_SR (STM32_SPI5_BASE + STM32_SPI_SR_OFFSET)
-# define STM32_SPI5_DR (STM32_SPI5_BASE + STM32_SPI_DR_OFFSET)
-# define STM32_SPI5_CRCPR (STM32_SPI5_BASE + STM32_SPI_CRCPR_OFFSET)
-# define STM32_SPI5_RXCRCR (STM32_SPI5_BASE + STM32_SPI_RXCRCR_OFFSET)
-# define STM32_SPI5_TXCRCR (STM32_SPI5_BASE + STM32_SPI_TXCRCR_OFFSET)
-# define STM32_SPI5_I2SCFGR (STM32_SPI5_BASE + STM32_SPI_I2SCFGR_OFFSET)
-# define STM32_SPI5_I2SPR (STM32_SPI5_BASE + STM32_SPI_I2SPR_OFFSET)
-#endif
-
-#if STM32_NSPI > 5
-# define STM32_SPI6_CR1 (STM32_SPI6_BASE + STM32_SPI_CR1_OFFSET)
-# define STM32_SPI6_CR2 (STM32_SPI6_BASE + STM32_SPI_CR2_OFFSET)
-# define STM32_SPI6_SR (STM32_SPI6_BASE + STM32_SPI_SR_OFFSET)
-# define STM32_SPI6_DR (STM32_SPI6_BASE + STM32_SPI_DR_OFFSET)
-# define STM32_SPI6_CRCPR (STM32_SPI6_BASE + STM32_SPI_CRCPR_OFFSET)
-# define STM32_SPI6_RXCRCR (STM32_SPI6_BASE + STM32_SPI_RXCRCR_OFFSET)
-# define STM32_SPI6_TXCRCR (STM32_SPI6_BASE + STM32_SPI_TXCRCR_OFFSET)
-# define STM32_SPI6_I2SCFGR (STM32_SPI6_BASE + STM32_SPI_I2SCFGR_OFFSET)
-# define STM32_SPI6_I2SPR (STM32_SPI6_BASE + STM32_SPI_I2SPR_OFFSET)
-#endif
-
Review Comment:
@raiden00pl are you sure none STM32L0xx, STM32F0xx, STM32L0xx, STM32G0xx have SPI4/5/6 ?
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[GitHub] [incubator-nuttx] xiaoxiang781216 merged pull request #6692: stm32f0l0g0: fixes for SPI half duplex
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 merged PR #6692:
URL: https://github.com/apache/incubator-nuttx/pull/6692
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[GitHub] [incubator-nuttx] raiden00pl commented on a diff in pull request #6692: stm32f0l0g0: fixes for SPI half duplex
Posted by GitBox <gi...@apache.org>.
raiden00pl commented on code in PR #6692:
URL: https://github.com/apache/incubator-nuttx/pull/6692#discussion_r928798428
##########
arch/arm/src/stm32f0l0g0/stm32_spi.c:
##########
@@ -1326,12 +1356,32 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd)
{
struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev;
uint32_t regval;
- uint32_t ret;
+ uint32_t ret = 0;
DEBUGASSERT(priv && priv->spibase);
- spi_writeword(priv, (uint16_t)(wd & 0xffff));
- ret = (uint32_t)spi_readword(priv);
+ if (priv->config != HALF_DUPLEX)
+ {
+ spi_writeword(priv, (uint16_t)(wd & 0xffff));
+ ret = (uint32_t)spi_readword(priv);
+ }
+ else
+ {
+ /* In half duplex we must send data and receive data in separate
+ * spi_send() calls.
+ */
+
+ if (priv->rx_now == false)
Review Comment:
done
--
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