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Posted to commits@tvm.apache.org by GitBox <gi...@apache.org> on 2022/02/02 01:53:20 UTC
[GitHub] [tvm] areusch opened a new issue #10141: [Tracking Issue] Write schedules for RISC-V targets
areusch opened a new issue #10141:
URL: https://github.com/apache/tvm/issues/10141
We added initial support for RISC-V in microTVM by proving that we can run regression tests against the Zephyr RISC-V target (backed by QEMU). However, we have not yet added support for any V- or P- extension SIMD instructions to provide more interesting performance numbers out of the box. This issue tracks adding those schedules, which involves:
- [ ] selecting a simulator which can correctly execute those instructions
- [ ] adding the schedules
- [ ] adding tests to verify functional correctness
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[GitHub] [tvm] PhilippvK commented on issue #10141: [Tracking Issue] Write schedules for RISC-V targets
Posted by GitBox <gi...@apache.org>.
PhilippvK commented on issue #10141:
URL: https://github.com/apache/tvm/issues/10141#issuecomment-1038014042
I've recently worked with RISC-V vector instructions using these simulators:
- **Spike (`riscv-isa-sim`)** - https://github.com/riscv-software-src/riscv-isa-sim
- Supports V-Ext. (v2.0) and P-Ext. (v0.9.2)
- No pre-build binaries available - Need to compile simulator (`spike`) and proxy kernel (`pk`) from source
- Debugging support with GDB very limited
- **riscvOVPSimPlus** - https://www.ovpworld.org/library/wikka.php?wakka=riscvOVPsimPlus
- Version with V-Ext. support: Sign-up required for download, internet connection for usage
- However, perfomance and usability is great (Much faster than Spike)
Both of them are only ISS, e.g. not cycle accurate, but that should not be an issue.
---
Another thing I would like to point out is that the vectorization support in the RISC-V GCC toolchain seems to be (References: [1](https://github.com/riscv-collab/riscv-gnu-toolchain/issues/975) [2](https://github.com/riscv-collab/riscv-gnu-toolchain/issues/990) [3](https://github.com/riscv-collab/riscv-gnu-toolchain/issues/968)). Thus, one should switch to using LLVM/Clang instead (LLVM also supports all RVV intrinsics).
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[GitHub] [tvm] PhilippvK commented on issue #10141: [Tracking Issue] Write schedules for RISC-V targets
Posted by GitBox <gi...@apache.org>.
PhilippvK commented on issue #10141:
URL: https://github.com/apache/tvm/issues/10141#issuecomment-1038014042
I've recently worked with RISC-V vector instructions using these simulators:
- **Spike (`riscv-isa-sim`)** - https://github.com/riscv-software-src/riscv-isa-sim
- Supports V-Ext. (v2.0) and P-Ext. (v0.9.2)
- No pre-build binaries available - Need to compile simulator (`spike`) and proxy kernel (`pk`) from source
- Debugging support with GDB very limited
- **riscvOVPSimPlus** - https://www.ovpworld.org/library/wikka.php?wakka=riscvOVPsimPlus
- Version with V-Ext. support: Sign-up required for download, internet connection for usage
- However, perfomance and usability is great (Much faster than Spike)
Both of them are only ISS, e.g. not cycle accurate, but that should not be an issue.
---
Another thing I would like to point out is that the vectorization support in the RISC-V GCC toolchain seems to be (References: [1](https://github.com/riscv-collab/riscv-gnu-toolchain/issues/975) [2](https://github.com/riscv-collab/riscv-gnu-toolchain/issues/990) [3](https://github.com/riscv-collab/riscv-gnu-toolchain/issues/968)). Thus, one should switch to using LLVM/Clang instead (LLVM also supports all RVV intrinsics).
--
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