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Posted to commits@mynewt.apache.org by ma...@apache.org on 2017/03/10 18:37:03 UTC
[1/9] incubator-mynewt-core git commit: bsp for ublox NINA-B112
nRF52832 based module
Repository: incubator-mynewt-core
Updated Branches:
refs/heads/develop 021f57931 -> 0759b1237
bsp for ublox NINA-B112 nRF52832 based module
Project: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/repo
Commit: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/commit/74c0d139
Tree: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/tree/74c0d139
Diff: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/diff/74c0d139
Branch: refs/heads/develop
Commit: 74c0d139b1a8aee2bb8c31b7aca95527d9e30433
Parents: 0f34d53
Author: Alan <ag...@gemcore.com>
Authored: Fri Mar 3 11:52:34 2017 -0800
Committer: Alan <ag...@gemcore.com>
Committed: Thu Mar 9 12:07:38 2017 -0800
----------------------------------------------------------------------
hw/bsp/nina-b1/boot-nrf52xxaa.ld | 25 ++
hw/bsp/nina-b1/bsp.yml | 62 ++++
hw/bsp/nina-b1/include/bsp/boards.h | 19 ++
hw/bsp/nina-b1/include/bsp/bsp.h | 65 ++++
hw/bsp/nina-b1/include/bsp/cmsis_nvic.h | 29 ++
hw/bsp/nina-b1/nrf52dk_debug.sh | 46 +++
hw/bsp/nina-b1/nrf52dk_download.sh | 40 +++
hw/bsp/nina-b1/nrf52dk_no_boot.ld | 191 ++++++++++++
hw/bsp/nina-b1/nrf52xxaa.ld | 25 ++
hw/bsp/nina-b1/pkg.yml | 92 ++++++
hw/bsp/nina-b1/split-nrf52dk.ld | 208 +++++++++++++
.../src/arch/cortex_m4/gcc_startup_nrf52.s | 299 +++++++++++++++++++
.../arch/cortex_m4/gcc_startup_nrf52_split.s | 163 ++++++++++
hw/bsp/nina-b1/src/hal_bsp.c | 217 ++++++++++++++
hw/bsp/nina-b1/src/sbrk.c | 59 ++++
hw/bsp/nina-b1/syscfg.yml | 111 +++++++
16 files changed, 1651 insertions(+)
----------------------------------------------------------------------
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/74c0d139/hw/bsp/nina-b1/boot-nrf52xxaa.ld
----------------------------------------------------------------------
diff --git a/hw/bsp/nina-b1/boot-nrf52xxaa.ld b/hw/bsp/nina-b1/boot-nrf52xxaa.ld
new file mode 100644
index 0000000..d1f1b99
--- /dev/null
+++ b/hw/bsp/nina-b1/boot-nrf52xxaa.ld
@@ -0,0 +1,25 @@
+/* Linker script for Nordic Semiconductor nRF5 devices
+ *
+ * Version: Sourcery G++ 4.5-1
+ * Support: https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x4000
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x10000
+}
+
+/* The bootloader does not contain an image header */
+_imghdr_size = 0x0;
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/74c0d139/hw/bsp/nina-b1/bsp.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/nina-b1/bsp.yml b/hw/bsp/nina-b1/bsp.yml
new file mode 100644
index 0000000..9525330
--- /dev/null
+++ b/hw/bsp/nina-b1/bsp.yml
@@ -0,0 +1,62 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+bsp.arch: cortex_m4
+bsp.compiler: compiler/arm-none-eabi-m4
+bsp.linkerscript:
+ - "hw/bsp/nina-b1/nrf52xxaa.ld"
+ - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+bsp.linkerscript.BOOT_LOADER.OVERWRITE:
+ - "hw/bsp/nina-b1/boot-nrf52xxaa.ld"
+ - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+bsp.part2linkerscript: "hw/bsp/nina-b1/split-nrf52dk.ld"
+bsp.downloadscript: "hw/bsp/nina-b1/nrf52dk_download.sh"
+bsp.debugscript: "hw/bsp/nina-b1/nrf52dk_debug.sh"
+
+bsp.flash_map:
+ areas:
+ # System areas.
+ FLASH_AREA_BOOTLOADER:
+ device: 0
+ offset: 0x00000000
+ size: 16kB
+ FLASH_AREA_IMAGE_0:
+ device: 0
+ offset: 0x00008000
+ size: 232kB
+ FLASH_AREA_IMAGE_1:
+ device: 0
+ offset: 0x00042000
+ size: 232kB
+ FLASH_AREA_IMAGE_SCRATCH:
+ device: 0
+ offset: 0x0007c000
+ size: 4kB
+
+ # User areas.
+ FLASH_AREA_REBOOT_LOG:
+ user_id: 0
+ device: 0
+ offset: 0x00004000
+ size: 16kB
+ FLASH_AREA_NFFS:
+ user_id: 1
+ device: 0
+ offset: 0x0007d000
+ size: 12kB
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/74c0d139/hw/bsp/nina-b1/include/bsp/boards.h
----------------------------------------------------------------------
diff --git a/hw/bsp/nina-b1/include/bsp/boards.h b/hw/bsp/nina-b1/include/bsp/boards.h
new file mode 100644
index 0000000..560c31f
--- /dev/null
+++ b/hw/bsp/nina-b1/include/bsp/boards.h
@@ -0,0 +1,19 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/74c0d139/hw/bsp/nina-b1/include/bsp/bsp.h
----------------------------------------------------------------------
diff --git a/hw/bsp/nina-b1/include/bsp/bsp.h b/hw/bsp/nina-b1/include/bsp/bsp.h
new file mode 100644
index 0000000..53e4f18
--- /dev/null
+++ b/hw/bsp/nina-b1/include/bsp/bsp.h
@@ -0,0 +1,65 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef H_BSP_H
+#define H_BSP_H
+
+#include <inttypes.h>
+
+#include <syscfg/syscfg.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Define special stackos sections */
+#define sec_data_core __attribute__((section(".data.core")))
+#define sec_bss_core __attribute__((section(".bss.core")))
+#define sec_bss_nz_core __attribute__((section(".bss.core.nz")))
+
+/* More convenient section placement macros. */
+#define bssnz_t sec_bss_nz_core
+
+extern uint8_t _ram_start;
+#define RAM_SIZE 0x10000
+
+/* LED pins */
+#define LED_BLINK_PIN (8)
+#define LED_2 (11)
+
+/* UART info */
+#define CONSOLE_UART "uart0"
+
+#if MYNEWT_VAL(BOOT_SERIAL)
+#define BOOT_SERIAL_DETECT_PIN 16 /* on IRC-BTLE board P0.16=SWITCH_1 */
+//#define BOOT_SERIAL_DETECT_PIN 30 /* on IRC-BTLE board P0.30=SWITCH_2 */
+#define BOOT_SERIAL_DETECT_PIN_CFG HAL_GPIO_PULL_UP
+#define BOOT_SERIAL_DETECT_PIN_VAL 0
+
+#define BOOT_SERIAL_REPORT_PIN LED_BLINK_PIN
+#define BOOT_SERIAL_REPORT_FREQ (MYNEWT_VAL(OS_CPUTIME_FREQ) / 4)
+#endif
+
+#define NFFS_AREA_MAX (8)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* H_BSP_H */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/74c0d139/hw/bsp/nina-b1/include/bsp/cmsis_nvic.h
----------------------------------------------------------------------
diff --git a/hw/bsp/nina-b1/include/bsp/cmsis_nvic.h b/hw/bsp/nina-b1/include/bsp/cmsis_nvic.h
new file mode 100644
index 0000000..856f7d0
--- /dev/null
+++ b/hw/bsp/nina-b1/include/bsp/cmsis_nvic.h
@@ -0,0 +1,29 @@
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include <stdint.h>
+
+#define NVIC_NUM_VECTORS (16 + 38) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "nrf52.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_Relocate(void);
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/74c0d139/hw/bsp/nina-b1/nrf52dk_debug.sh
----------------------------------------------------------------------
diff --git a/hw/bsp/nina-b1/nrf52dk_debug.sh b/hw/bsp/nina-b1/nrf52dk_debug.sh
new file mode 100755
index 0000000..17b980d
--- /dev/null
+++ b/hw/bsp/nina-b1/nrf52dk_debug.sh
@@ -0,0 +1,46 @@
+#!/bin/sh
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Called with following variables set:
+# - CORE_PATH is absolute path to @apache-mynewt-core
+# - BSP_PATH is absolute path to hw/bsp/bsp_name
+# - BIN_BASENAME is the path to prefix to target binary,
+# .elf appended to name is the ELF file
+# - FEATURES holds the target features string
+# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+# - RESET set if target should be reset when attaching
+# - NO_GDB set if we should not start gdb to debug
+#
+
+. $CORE_PATH/hw/scripts/jlink.sh
+
+FILE_NAME=$BIN_BASENAME.elf
+
+if [ $# -gt 2 ]; then
+ SPLIT_ELF_NAME=$3.elf
+ # TODO -- this magic number 0x42000 is the location of the second image
+ # slot. we should either get this from a flash map file or somehow learn
+ # this from the image itself
+ EXTRA_GDB_CMDS="add-symbol-file $SPLIT_ELF_NAME 0x8000 -readnow"
+fi
+
+JLINK_DEV="nRF52"
+
+jlink_debug
+
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/74c0d139/hw/bsp/nina-b1/nrf52dk_download.sh
----------------------------------------------------------------------
diff --git a/hw/bsp/nina-b1/nrf52dk_download.sh b/hw/bsp/nina-b1/nrf52dk_download.sh
new file mode 100755
index 0000000..08d45b4
--- /dev/null
+++ b/hw/bsp/nina-b1/nrf52dk_download.sh
@@ -0,0 +1,40 @@
+#!/bin/sh
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+
+# Called with following variables set:
+# - CORE_PATH is absolute path to @apache-mynewt-core
+# - BSP_PATH is absolute path to hw/bsp/bsp_name
+# - BIN_BASENAME is the path to prefix to target binary,
+# .elf appended to name is the ELF file
+# - IMAGE_SLOT is the image slot to download to (for non-mfg-image, non-boot)
+# - FEATURES holds the target features string
+# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+# - MFG_IMAGE is "1" if this is a manufacturing image
+# - FLASH_OFFSET contains the flash offset to download to
+# - BOOT_LOADER is set if downloading a bootloader
+
+. $CORE_PATH/hw/scripts/jlink.sh
+
+if [ "$MFG_IMAGE" ]; then
+ FLASH_OFFSET=0x0
+fi
+
+JLINK_DEV="nRF52"
+
+common_file_to_load
+jlink_load
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/74c0d139/hw/bsp/nina-b1/nrf52dk_no_boot.ld
----------------------------------------------------------------------
diff --git a/hw/bsp/nina-b1/nrf52dk_no_boot.ld b/hw/bsp/nina-b1/nrf52dk_no_boot.ld
new file mode 100644
index 0000000..e2fb5a8
--- /dev/null
+++ b/hw/bsp/nina-b1/nrf52dk_no_boot.ld
@@ -0,0 +1,191 @@
+/* Linker script for Nordic Semiconductor nRF5 devices
+ *
+ * Version: Sourcery G++ 4.5-1
+ * Support: https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x10000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __HeapBase
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __bssnz_start__
+ * __bssnz_end__
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ __isr_vector_start = .;
+ KEEP(*(.isr_vector))
+ __isr_vector_end = .;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ *(.eh_frame*)
+ . = ALIGN(4);
+ } > FLASH
+
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ . = ALIGN(4);
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .vector_relocation :
+ {
+ . = ALIGN(4);
+ __vector_tbl_reloc__ = .;
+ . = . + (__isr_vector_end - __isr_vector_start);
+ . = ALIGN(4);
+ } > RAM
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ *(.preinit_array)
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ *(SORT(.init_array.*))
+ *(.init_array)
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ *(SORT(.fini_array.*))
+ *(.fini_array)
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ *(.jcr)
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ } > RAM
+
+ /* Non-zeroed BSS. This section is similar to BSS, with the following
+ * caveat:
+ * 1. It does not get zeroed at init-time.
+ */
+ .bssnz :
+ {
+ . = ALIGN(4);
+ __bssnz_start__ = .;
+ *(.bss.core.nz*)
+ . = ALIGN(4);
+ __bssnz_end__ = .;
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ /* Heap starts after BSS */
+ __HeapBase = .;
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Top of head is the bottom of the stack */
+ __HeapLimit = __StackLimit;
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__HeapBase <= __HeapLimit, "region RAM overflowed with stack")
+}
+
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/74c0d139/hw/bsp/nina-b1/nrf52xxaa.ld
----------------------------------------------------------------------
diff --git a/hw/bsp/nina-b1/nrf52xxaa.ld b/hw/bsp/nina-b1/nrf52xxaa.ld
new file mode 100644
index 0000000..9433e37
--- /dev/null
+++ b/hw/bsp/nina-b1/nrf52xxaa.ld
@@ -0,0 +1,25 @@
+/* Linker script for Nordic Semiconductor nRF5 devices
+ *
+ * Version: Sourcery G++ 4.5-1
+ * Support: https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00008000, LENGTH = 0x3a000
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x10000
+}
+
+/* This linker script is used for images and thus contains an image header */
+_imghdr_size = 0x20;
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/74c0d139/hw/bsp/nina-b1/pkg.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/nina-b1/pkg.yml b/hw/bsp/nina-b1/pkg.yml
new file mode 100644
index 0000000..1ad4de8
--- /dev/null
+++ b/hw/bsp/nina-b1/pkg.yml
@@ -0,0 +1,92 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: hw/bsp/nina-b1
+pkg.type: bsp
+pkg.description: BSP definition for the Nordic nRF52 based ublox NINA-B1xx series modules
+pkg.author: "Apache Mynewt <de...@mynewt.incubator.apache.org>"
+pkg.homepage: "http://mynewt.apache.org/"
+pkg.keywords:
+ - nrf52
+ - nrf52dk
+
+pkg.cflags:
+ # Nordic SDK files require these defines.
+ - '-DADC_ENABLED=0'
+ - '-DCLOCK_ENABLED=1'
+ - '-DCOMP_ENABLED=1'
+ - '-DEGU_ENABLED=0'
+ - '-DGPIOTE_ENABLED=1'
+ - '-DI2S_ENABLED=1'
+ - '-DLPCOMP_ENABLED=1'
+ - '-DNRF52'
+ - '-DPDM_ENABLED=0'
+ - '-DPERIPHERAL_RESOURCE_SHARING_ENABLED=1'
+ - '-DPWM0_ENABLED=1'
+ - '-DPWM1_ENABLED=0'
+ - '-DPWM2_ENABLED=0'
+ - '-DQDEC_ENABLED=1'
+ - '-DRNG_ENABLED=1'
+ - '-DRTC0_ENABLED=0'
+ - '-DRTC1_ENABLED=0'
+ - '-DRTC2_ENABLED=0'
+ - '-DSAADC_ENABLED=1'
+ - '-DSPI_MASTER_0_ENABLE=1'
+ - '-DSPI0_CONFIG_MISO_PIN=25'
+ - '-DSPI0_CONFIG_MOSI_PIN=24'
+ - '-DSPI0_CONFIG_SCK_PIN=23'
+ - '-DSPI0_ENABLED=1'
+ - '-DSPI0_USE_EASY_DMA=1'
+ - '-DSPI1_ENABLED=0'
+ - '-DSPI2_ENABLED=0'
+ - '-DSPIS0_CONFIG_MISO_PIN=25'
+ - '-DSPIS0_CONFIG_MOSI_PIN=24'
+ - '-DSPIS0_CONFIG_SCK_PIN=23'
+ - '-DSPIS0_ENABLED=1'
+ - '-DSPIS1_CONFIG_MISO_PIN=4'
+ - '-DSPIS1_CONFIG_MOSI_PIN=3'
+ - '-DSPIS1_CONFIG_SCK_PIN=2'
+ - '-DSPIS1_ENABLED=0'
+ - '-DSPIS2_ENABLED=0'
+ - '-DTIMER0_ENABLED=1'
+ - '-DTIMER1_ENABLED=0'
+ - '-DTIMER2_ENABLED=0'
+ - '-DTIMER3_ENABLED=0'
+ - '-DTIMER4_ENABLED=0'
+ - '-DTWI0_CONFIG_SCL=27'
+ - '-DTWI0_CONFIG_SDA=26'
+ - '-DTWI0_ENABLED=1'
+ - '-DTWI1_ENABLED=1'
+ - '-DTWIS0_ENABLED=1'
+ - '-DTWIS1_ENABLED=0'
+ - '-DUART0_ENABLED=1'
+ - '-DWDT_ENABLED=1'
+
+pkg.deps:
+ - hw/mcu/nordic/nrf52xxx
+ - libc/baselibc
+
+pkg.deps.BLE_DEVICE:
+ - hw/drivers/nimble/nrf52
+
+pkg.deps.UART_0:
+ - hw/drivers/uart/uart_hal
+
+pkg.deps.UART_1:
+ - hw/drivers/uart/uart_bitbang
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/74c0d139/hw/bsp/nina-b1/split-nrf52dk.ld
----------------------------------------------------------------------
diff --git a/hw/bsp/nina-b1/split-nrf52dk.ld b/hw/bsp/nina-b1/split-nrf52dk.ld
new file mode 100644
index 0000000..ebfac21
--- /dev/null
+++ b/hw/bsp/nina-b1/split-nrf52dk.ld
@@ -0,0 +1,208 @@
+/* Linker script for Nordic Semiconductor nRF5 devices
+ *
+ * Version: Sourcery G++ 4.5-1
+ * Support: https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00042000, LENGTH = 0x3a000
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x10000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __HeapBase
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __bssnz_start__
+ * __bssnz_end__
+ */
+ENTRY(Reset_Handler_split)
+
+SECTIONS
+{
+ .imghdr (NOLOAD):
+ {
+ . = . + 0x20;
+ } > FLASH
+
+ .text :
+ {
+ __split_isr_vector_start = .;
+ KEEP(*(.isr_vector_split))
+ __split_isr_vector_end = .;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ *(.eh_frame*)
+ . = ALIGN(4);
+ } > FLASH
+
+
+ .ARM.extab : ALIGN(4)
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ . = ALIGN(4);
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ /* save RAM used by the split image. This assumes that
+ * the loader uses all the RAM up to its HeapBase */
+ .loader_ram_contents :
+ {
+ _loader_ram_start = .;
+
+ /* this symbol comes from the loader linker */
+ . = . + (ABSOLUTE(__HeapBase_loader) - _loader_ram_start);
+ _loader_ram_end = .;
+ } > RAM
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ *(.preinit_array)
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ *(SORT(.init_array.*))
+ *(.init_array)
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ *(SORT(.fini_array.*))
+ *(.fini_array)
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ *(.jcr)
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ } > RAM
+
+ /* Non-zeroed BSS. This section is similar to BSS, with the following two
+ * caveats:
+ * 1. It does not get zeroed at init-time.
+ * 2. You cannot use it as source memory for EasyDMA.
+ *
+ * This section exists because of a hardware defect; see errata 33 and 34
+ * in nrf52 errata sheet.
+ */
+ .bssnz :
+ {
+ . = ALIGN(4);
+ __bssnz_start__ = .;
+ *(.bss.core.nz*)
+ . = ALIGN(4);
+ __bssnz_end__ = .;
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ /* Heap starts after BSS */
+ __HeapBase = .;
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ _ram_start = ORIGIN(RAM);
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Top of head is the bottom of the stack */
+ __HeapLimit = __StackLimit;
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__HeapBase <= __HeapLimit, "region RAM overflowed with stack")
+}
+
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/74c0d139/hw/bsp/nina-b1/src/arch/cortex_m4/gcc_startup_nrf52.s
----------------------------------------------------------------------
diff --git a/hw/bsp/nina-b1/src/arch/cortex_m4/gcc_startup_nrf52.s b/hw/bsp/nina-b1/src/arch/cortex_m4/gcc_startup_nrf52.s
new file mode 100644
index 0000000..b45a73c
--- /dev/null
+++ b/hw/bsp/nina-b1/src/arch/cortex_m4/gcc_startup_nrf52.s
@@ -0,0 +1,299 @@
+/*
+Copyright (c) 2015, Nordic Semiconductor ASA
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+* Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+NOTE: Template files (including this one) are application specific and therefore
+expected to be copied into the application project folder prior to its use!
+*/
+
+ .syntax unified
+ .arch armv7-m
+
+ .section .stack
+ .align 3
+ .equ Stack_Size, 432
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External Interrupts */
+ .long POWER_CLOCK_IRQHandler
+ .long RADIO_IRQHandler
+ .long UARTE0_UART0_IRQHandler
+ .long SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+ .long SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+ .long NFCT_IRQHandler
+ .long GPIOTE_IRQHandler
+ .long SAADC_IRQHandler
+ .long TIMER0_IRQHandler
+ .long TIMER1_IRQHandler
+ .long TIMER2_IRQHandler
+ .long RTC0_IRQHandler
+ .long TEMP_IRQHandler
+ .long RNG_IRQHandler
+ .long ECB_IRQHandler
+ .long CCM_AAR_IRQHandler
+ .long WDT_IRQHandler
+ .long RTC1_IRQHandler
+ .long QDEC_IRQHandler
+ .long COMP_LPCOMP_IRQHandler
+ .long SWI0_EGU0_IRQHandler
+ .long SWI1_EGU1_IRQHandler
+ .long SWI2_EGU2_IRQHandler
+ .long SWI3_EGU3_IRQHandler
+ .long SWI4_EGU4_IRQHandler
+ .long SWI5_EGU5_IRQHandler
+ .long TIMER3_IRQHandler
+ .long TIMER4_IRQHandler
+ .long PWM0_IRQHandler
+ .long PDM_IRQHandler
+ .long 0 /*Reserved */
+ .long 0 /*Reserved */
+ .long MWU_IRQHandler
+ .long PWM1_IRQHandler
+ .long PWM2_IRQHandler
+ .long SPIM2_SPIS2_SPI2_IRQHandler
+ .long RTC2_IRQHandler
+ .long I2S_IRQHandler
+
+ .size __isr_vector, . - __isr_vector
+
+/* Reset Handler */
+
+ .text
+ .thumb
+ .thumb_func
+ .align 1
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ .fnstart
+
+ /* Clear BSS */
+ mov r0, #0
+ ldr r2, =__bss_start__
+ ldr r3, =__bss_end__
+.bss_zero_loop:
+ cmp r2, r3
+ itt lt
+ strlt r0, [r2], #4
+ blt .bss_zero_loop
+
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .LC0
+
+.LC1:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC1
+
+.LC0:
+
+ LDR R0, =__HeapBase
+ LDR R1, =__HeapLimit
+ BL _sbrkInit
+
+ LDR R0, =SystemInit
+ BLX R0
+
+ LDR R0, =_start
+ BX R0
+
+ .pool
+ .cantunwind
+ .fnend
+ .size Reset_Handler,.-Reset_Handler
+
+ .section ".text"
+
+
+/* Dummy Exception Handlers (infinite loops which can be modified) */
+
+ .weak NMI_Handler
+ .type NMI_Handler, %function
+NMI_Handler:
+ B .
+ .size NMI_Handler, . - NMI_Handler
+
+
+ .weak HardFault_Handler
+ .type HardFault_Handler, %function
+HardFault_Handler:
+ B .
+ .size HardFault_Handler, . - HardFault_Handler
+
+
+ .weak MemoryManagement_Handler
+ .type MemoryManagement_Handler, %function
+MemoryManagement_Handler:
+ B .
+ .size MemoryManagement_Handler, . - MemoryManagement_Handler
+
+
+ .weak BusFault_Handler
+ .type BusFault_Handler, %function
+BusFault_Handler:
+ B .
+ .size BusFault_Handler, . - BusFault_Handler
+
+
+ .weak UsageFault_Handler
+ .type UsageFault_Handler, %function
+UsageFault_Handler:
+ B .
+ .size UsageFault_Handler, . - UsageFault_Handler
+
+
+ .weak SVC_Handler
+ .type SVC_Handler, %function
+SVC_Handler:
+ B .
+ .size SVC_Handler, . - SVC_Handler
+
+
+ .weak PendSV_Handler
+ .type PendSV_Handler, %function
+PendSV_Handler:
+ B .
+ .size PendSV_Handler, . - PendSV_Handler
+
+
+ .weak SysTick_Handler
+ .type SysTick_Handler, %function
+SysTick_Handler:
+ B .
+ .size SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+ .globl Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ B .
+ .size Default_Handler, . - Default_Handler
+
+ .macro IRQ handler
+ .weak \handler
+ .set \handler, Default_Handler
+ .endm
+
+ IRQ POWER_CLOCK_IRQHandler
+ IRQ RADIO_IRQHandler
+ IRQ UARTE0_UART0_IRQHandler
+ IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+ IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+ IRQ NFCT_IRQHandler
+ IRQ GPIOTE_IRQHandler
+ IRQ SAADC_IRQHandler
+ IRQ TIMER0_IRQHandler
+ IRQ TIMER1_IRQHandler
+ IRQ TIMER2_IRQHandler
+ IRQ RTC0_IRQHandler
+ IRQ TEMP_IRQHandler
+ IRQ RNG_IRQHandler
+ IRQ ECB_IRQHandler
+ IRQ CCM_AAR_IRQHandler
+ IRQ WDT_IRQHandler
+ IRQ RTC1_IRQHandler
+ IRQ QDEC_IRQHandler
+ IRQ COMP_LPCOMP_IRQHandler
+ IRQ SWI0_EGU0_IRQHandler
+ IRQ SWI1_EGU1_IRQHandler
+ IRQ SWI2_EGU2_IRQHandler
+ IRQ SWI3_EGU3_IRQHandler
+ IRQ SWI4_EGU4_IRQHandler
+ IRQ SWI5_EGU5_IRQHandler
+ IRQ TIMER3_IRQHandler
+ IRQ TIMER4_IRQHandler
+ IRQ PWM0_IRQHandler
+ IRQ PDM_IRQHandler
+ IRQ MWU_IRQHandler
+ IRQ PWM1_IRQHandler
+ IRQ PWM2_IRQHandler
+ IRQ SPIM2_SPIS2_SPI2_IRQHandler
+ IRQ RTC2_IRQHandler
+ IRQ I2S_IRQHandler
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/74c0d139/hw/bsp/nina-b1/src/arch/cortex_m4/gcc_startup_nrf52_split.s
----------------------------------------------------------------------
diff --git a/hw/bsp/nina-b1/src/arch/cortex_m4/gcc_startup_nrf52_split.s b/hw/bsp/nina-b1/src/arch/cortex_m4/gcc_startup_nrf52_split.s
new file mode 100644
index 0000000..de1ce6e
--- /dev/null
+++ b/hw/bsp/nina-b1/src/arch/cortex_m4/gcc_startup_nrf52_split.s
@@ -0,0 +1,163 @@
+/*
+Copyright (c) 2015, Nordic Semiconductor ASA
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+* Neither the name of Nordic Semiconductor ASA nor the names of its
+ contributors may be used to endorse or promote products derived from
+ this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+NOTE: Template files (including this one) are application specific and therefore
+expected to be copied into the application project folder prior to its use!
+*/
+
+ .syntax unified
+ .arch armv7-m
+ .section .stack
+ .align 3
+ .equ Stack_Size, 432
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector_split
+ .align 2
+ .globl __isr_vector_split
+__isr_vector_split:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler_split /* Reset Handler */
+
+ .size __isr_vector_split, . - __isr_vector_split
+
+/* Reset Handler */
+
+ .text
+ .thumb
+ .thumb_func
+ .align 1
+ .globl Reset_Handler_split
+ .type Reset_Handler_split, %function
+Reset_Handler_split:
+ .fnstart
+
+ /* Clear CPU state before proceeding */
+ mov r0, #0
+ msr control, r0
+ msr primask, r0
+ /* Clear BSS */
+ ldr r2, =__bss_start__
+ ldr r3, =__bss_end__
+.bss_zero_loop:
+ cmp r2, r3
+ itt lt
+ strlt r0, [r2], #4
+ blt .bss_zero_loop
+
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .LC0
+
+.LC1:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC1
+
+.LC0:
+ ldr r1, =__etext_loader
+ ldr r2, =__data_start___loader
+ ldr r3, =__data_end___loader
+
+ subs r3, r2
+ ble .LC2
+
+.LC3:
+ subs r3, 4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .LC3
+.LC2:
+
+ subs r0, r0
+ ldr r2, =__bss_start___loader
+ ldr r3, =__bss_end___loader
+
+ subs r3, r2
+ ble .LC4
+
+.LC5:
+ subs r3, 4
+ str r0, [r2,r3]
+ bgt .LC5
+.LC4:
+
+ LDR R0, =__HeapBase
+ LDR R1, =__HeapLimit
+ BL _sbrkInit
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =_start_split
+ BX R0
+
+ .pool
+ .cantunwind
+ .fnend
+ .size Reset_Handler_split,.-Reset_Handler_split
+
+ .section ".text"
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/74c0d139/hw/bsp/nina-b1/src/hal_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/nina-b1/src/hal_bsp.c b/hw/bsp/nina-b1/src/hal_bsp.c
new file mode 100644
index 0000000..40ce57b
--- /dev/null
+++ b/hw/bsp/nina-b1/src/hal_bsp.c
@@ -0,0 +1,217 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <stdint.h>
+#include <stddef.h>
+#include <assert.h>
+#include <nrf52.h>
+#include "os/os_cputime.h"
+#include "syscfg/syscfg.h"
+#include "sysflash/sysflash.h"
+#include "flash_map/flash_map.h"
+#include "hal/hal_bsp.h"
+#include "hal/hal_flash.h"
+#include "hal/hal_spi.h"
+#include "hal/hal_watchdog.h"
+#include "hal/hal_i2c.h"
+#include "mcu/nrf52_hal.h"
+#if MYNEWT_VAL(UART_0) || MYNEWT_VAL(UART_1)
+#include "uart/uart.h"
+#endif
+#if MYNEWT_VAL(UART_0)
+#include "uart_hal/uart_hal.h"
+#endif
+#if MYNEWT_VAL(UART_1)
+#include "uart_bitbang/uart_bitbang.h"
+#endif
+#include "os/os_dev.h"
+#include "bsp.h"
+
+#if MYNEWT_VAL(UART_0)
+static struct uart_dev os_bsp_uart0;
+static const struct nrf52_uart_cfg os_bsp_uart0_cfg = {
+ .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS),
+};
+#endif
+
+#if MYNEWT_VAL(UART_1)
+static struct uart_dev os_bsp_bitbang_uart1;
+static const struct uart_bitbang_conf os_bsp_uart1_cfg = {
+ .ubc_rxpin = MYNEWT_VAL(UART_1_PIN_TX),
+ .ubc_txpin = MYNEWT_VAL(UART_1_PIN_RX),
+ .ubc_cputimer_freq = MYNEWT_VAL(OS_CPUTIME_FREQ),
+};
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+/*
+ * NOTE: Our HAL expects that the SS pin, if used, is treated as a gpio line
+ * and is handled outside the SPI routines.
+ */
+static const struct nrf52_hal_spi_cfg os_bsp_spi0m_cfg = {
+ .sck_pin = 23,
+ .mosi_pin = 24,
+ .miso_pin = 25,
+};
+#endif
+
+#if MYNEWT_VAL(SPI_0_SLAVE)
+static const struct nrf52_hal_spi_cfg os_bsp_spi0s_cfg = {
+ .sck_pin = 23,
+ .mosi_pin = 24,
+ .miso_pin = 25,
+ .ss_pin = 22,
+};
+#endif
+
+#if MYNEWT_VAL(I2C_0)
+static const struct nrf52_hal_i2c_cfg hal_i2c_cfg = {
+ .scl_pin = 27,
+ .sda_pin = 26,
+ .i2c_frequency = 100 /* 100 kHz */
+};
+#endif
+
+/*
+ * What memory to include in coredump.
+ */
+static const struct hal_bsp_mem_dump dump_cfg[] = {
+ [0] = {
+ .hbmd_start = &_ram_start,
+ .hbmd_size = RAM_SIZE
+ }
+};
+
+const struct hal_flash *
+hal_bsp_flash_dev(uint8_t id)
+{
+ /*
+ * Internal flash mapped to id 0.
+ */
+ if (id != 0) {
+ return NULL;
+ }
+ return &nrf52k_flash_dev;
+}
+
+const struct hal_bsp_mem_dump *
+hal_bsp_core_dump(int *area_cnt)
+{
+ *area_cnt = sizeof(dump_cfg) / sizeof(dump_cfg[0]);
+ return dump_cfg;
+}
+
+int
+hal_bsp_power_state(int state)
+{
+ return (0);
+}
+
+/**
+ * Returns the configured priority for the given interrupt. If no priority
+ * configured, return the priority passed in
+ *
+ * @param irq_num
+ * @param pri
+ *
+ * @return uint32_t
+ */
+uint32_t
+hal_bsp_get_nvic_priority(int irq_num, uint32_t pri)
+{
+ uint32_t cfg_pri;
+
+ switch (irq_num) {
+ /* Radio gets highest priority */
+ case RADIO_IRQn:
+ cfg_pri = 0;
+ break;
+ default:
+ cfg_pri = pri;
+ }
+ return cfg_pri;
+}
+
+void
+hal_bsp_init(void)
+{
+ int rc;
+
+ (void)rc;
+#if MYNEWT_VAL(TIMER_0)
+ rc = hal_timer_init(0, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_1)
+ rc = hal_timer_init(1, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_2)
+ rc = hal_timer_init(2, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_3)
+ rc = hal_timer_init(3, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_4)
+ rc = hal_timer_init(4, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_5)
+ rc = hal_timer_init(5, NULL);
+ assert(rc == 0);
+#endif
+
+#if (MYNEWT_VAL(OS_CPUTIME_TIMER_NUM) >= 0)
+ rc = os_cputime_init(MYNEWT_VAL(OS_CPUTIME_FREQ));
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(I2C_0)
+ rc = hal_i2c_init(0, (void *)&hal_i2c_cfg);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+ rc = hal_spi_init(0, (void *)&os_bsp_spi0m_cfg, HAL_SPI_TYPE_MASTER);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(SPI_0_SLAVE)
+ rc = hal_spi_init(0, (void *)&os_bsp_spi0s_cfg, HAL_SPI_TYPE_SLAVE);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(UART_0)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart0, "uart0",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&os_bsp_uart0_cfg);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(UART_1)
+ rc = os_dev_create((struct os_dev *) &os_bsp_bitbang_uart1, "uart1",
+ OS_DEV_INIT_PRIMARY, 0, uart_bitbang_init, (void *)&os_bsp_uart1_cfg);
+ assert(rc == 0);
+#endif
+
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/74c0d139/hw/bsp/nina-b1/src/sbrk.c
----------------------------------------------------------------------
diff --git a/hw/bsp/nina-b1/src/sbrk.c b/hw/bsp/nina-b1/src/sbrk.c
new file mode 100644
index 0000000..5df43c9
--- /dev/null
+++ b/hw/bsp/nina-b1/src/sbrk.c
@@ -0,0 +1,59 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <hal/hal_bsp.h>
+
+/* put these in the data section so they are not cleared by _start */
+static char *sbrkBase __attribute__ ((section (".data")));
+static char *sbrkLimit __attribute__ ((section (".data")));
+static char *brk __attribute__ ((section (".data")));
+
+void
+_sbrkInit(char *base, char *limit) {
+ sbrkBase = base;
+ sbrkLimit = limit;
+ brk = base;
+}
+
+void *
+_sbrk(int incr)
+{
+ void *prev_brk;
+
+ if (incr < 0) {
+ /* Returning memory to the heap. */
+ incr = -incr;
+ if (brk - incr < sbrkBase) {
+ prev_brk = (void *)-1;
+ } else {
+ prev_brk = brk;
+ brk -= incr;
+ }
+ } else {
+ /* Allocating memory from the heap. */
+ if (sbrkLimit - brk >= incr) {
+ prev_brk = brk;
+ brk += incr;
+ } else {
+ prev_brk = (void *)-1;
+ }
+ }
+
+ return prev_brk;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/74c0d139/hw/bsp/nina-b1/syscfg.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/nina-b1/syscfg.yml b/hw/bsp/nina-b1/syscfg.yml
new file mode 100644
index 0000000..9558fea
--- /dev/null
+++ b/hw/bsp/nina-b1/syscfg.yml
@@ -0,0 +1,111 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Package: hw/bsp/nina-b1
+
+syscfg.defs:
+ BSP_NRF52:
+ description: 'Set to indicate that BSP has NRF52'
+ value: 1
+
+ XTAL_32768:
+ description: 'External 32k oscillator available.'
+ value: 1
+
+ UART_0:
+ description: 'Whether to enable UART0'
+ value: 1
+ UART_0_PIN_TX:
+ description: 'TX pin for UART0'
+ value: 6
+ UART_0_PIN_RX:
+ description: 'RX pin for UART0'
+ value: 5
+ UART_0_PIN_RTS:
+ description: 'RTS pin for UART0'
+ value: 31
+ UART_0_PIN_CTS:
+ description: 'CTS pin for UART0'
+ value: 7
+
+ UART_1:
+ description: 'whether to enable Bitbanger UART1'
+ value: 0
+ UART_1_PIN_TX:
+ description: 'TX pin for UART1'
+ value: -1
+ UART_1_PIN_RX:
+ description: 'RX pin for UART1'
+ value: -1
+
+ SPI_0_MASTER:
+ description: 'SPI 0 master'
+ value: 0
+ restrictions:
+ - "!SPI_0_SLAVE"
+ SPI_0_MASTER_SS_PIN:
+ description: 'SPI 0 (master) SS pin number.'
+ value: 22
+ SPI_0_SLAVE:
+ description: 'SPI 0 slave'
+ value: 0
+ restrictions:
+ - "!SPI_0_MASTER"
+
+ SPI_1_MASTER:
+ description: 'SPI 1 master'
+ value: 0
+ restrictions:
+ - "!SPI_1_SLAVE"
+ SPI_1_MASTER_SS_PIN:
+ description: 'SPI 1 (master) SS pin number.'
+ value: -1
+ SPI_1_SLAVE:
+ description: 'SPI 1 slave'
+ value: 0
+ restrictions:
+ - "!SPI_1_MASTER"
+
+ TIMER_0:
+ description: 'NRF52 Timer 0'
+ value: 1
+ TIMER_1:
+ description: 'NRF52 Timer 1'
+ value: 0
+ TIMER_2:
+ description: 'NRF52 Timer 2'
+ value: 0
+ TIMER_3:
+ description: 'NRF52 Timer 3'
+ value: 0
+ TIMER_4:
+ description: 'NRF52 Timer 4'
+ value: 0
+ TIMER_5:
+ description: 'NRF52 RTC 0'
+ value: 0
+
+ I2C_0:
+ description: 'NRF52 I2C (TWI) interface 0'
+ value: '0'
+
+syscfg.vals:
+ CONFIG_FCB_FLASH_AREA: FLASH_AREA_NFFS
+ REBOOT_LOG_FLASH_AREA: FLASH_AREA_REBOOT_LOG
+ NFFS_FLASH_AREA: FLASH_AREA_NFFS
+ COREDUMP_FLASH_AREA: FLASH_AREA_IMAGE_1
[5/9] incubator-mynewt-core git commit: Update repository.yml to
point to 1.0.0-b1 tag.
Posted by ma...@apache.org.
Update repository.yml to point to 1.0.0-b1 tag.
Project: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/repo
Commit: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/commit/581926e6
Tree: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/tree/581926e6
Diff: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/diff/581926e6
Branch: refs/heads/develop
Commit: 581926e6fe3d6730960367fb23984fe9a411ef3d
Parents: b3f9b96
Author: Christopher Collins <cc...@apache.org>
Authored: Tue Nov 22 14:55:05 2016 -0800
Committer: Alan <ag...@gemcore.com>
Committed: Thu Mar 9 12:07:38 2017 -0800
----------------------------------------------------------------------
repository.yml | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
----------------------------------------------------------------------
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/581926e6/repository.yml
----------------------------------------------------------------------
diff --git a/repository.yml b/repository.yml
index 615004f..79990b3 100644
--- a/repository.yml
+++ b/repository.yml
@@ -20,11 +20,15 @@
repo.name: apache-mynewt-core
repo.versions:
"0.0.0": "develop"
+ "0.0.1": "master"
"0.7.9": "mynewt_0_8_0_b2_tag"
"0.8.0": "mynewt_0_8_0_tag"
"0.9.0": "mynewt_0_9_0_tag"
- "0.9.1": "master"
- "0-latest": "0.9.0"
- "0-dev": "0.9.1"
+ "0.9.9": "mynewt_1_0_0_b1_tag"
+
+ "0-latest": "0.9.9" # 1.0.0-b1
+ "0-dev": "0.0.0" # develop
+
"0.8-latest": "0.8.0"
"0.9-latest": "0.9.0"
+ "1.0-latest": "0.9.9" # 1.0.0-b1
[6/9] incubator-mynewt-core git commit: removed unused file
Posted by ma...@apache.org.
removed unused file
Project: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/repo
Commit: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/commit/873f6bbd
Tree: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/tree/873f6bbd
Diff: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/diff/873f6bbd
Branch: refs/heads/develop
Commit: 873f6bbde4007a121e24c97a1e0977d19d4f08be
Parents: 469eabd
Author: Alan <ag...@gemcore.com>
Authored: Thu Mar 9 11:19:03 2017 -0800
Committer: Alan <ag...@gemcore.com>
Committed: Thu Mar 9 12:07:39 2017 -0800
----------------------------------------------------------------------
hw/bsp/sensorhub/src/hal_bsp_sav.c | 123 --------------------------------
1 file changed, 123 deletions(-)
----------------------------------------------------------------------
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/873f6bbd/hw/bsp/sensorhub/src/hal_bsp_sav.c
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/src/hal_bsp_sav.c b/hw/bsp/sensorhub/src/hal_bsp_sav.c
deleted file mode 100644
index 2d18815..0000000
--- a/hw/bsp/sensorhub/src/hal_bsp_sav.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-//#include <stdint.h>
-//#include <stddef.h>
-#include <assert.h>
-#include "syscfg/syscfg.h"
-//#include "bsp/bsp.h"
-
-#if MYNEWT_VAL(UART_0)
-//#include <uart/uart.h>
-//#include <uart_hal/uart_hal.h>
-#endif
-#include "os/os_dev.h"
-
-#include <hal/hal_bsp.h>
-#include <hal/hal_gpio.h>
-#include <hal/hal_flash_int.h>
-#include <hal/hal_timer.h>
-
-#include <stm32f427xx.h>
-#include <stm32f4xx_hal_gpio_ex.h>
-#include <mcu/stm32f4_bsp.h>
-
-#if MYNEWT_VAL(UART_0)
-#include "bsp/bsp.h"
-#include <uart/uart.h>
-#include <uart_hal/uart_hal.h>
-
-static struct uart_dev hal_uart0;
-
-static const struct stm32f4_uart_cfg uart_cfg[UART_CNT] = {
- [0] = {
- .suc_uart = UART4,
- .suc_rcc_reg = &RCC->APB1ENR,
- .suc_rcc_dev = RCC_APB1ENR_UART4EN,
- .suc_pin_tx = MCU_GPIO_PORTC(10), /* PC10 */
- .suc_pin_rx = MCU_GPIO_PORTC(11), /* PC11 */
- .suc_pin_rts = -1,
- .suc_pin_cts = -1,
- .suc_pin_af = GPIO_AF8_UART4,
- .suc_irqn = UART4_IRQn
- }
-};
-#endif
-
-static const struct hal_bsp_mem_dump dump_cfg[] = {
- [0] = {
- .hbmd_start = &_ram_start,
- .hbmd_size = RAM_SIZE
- },
- [1] = {
- .hbmd_start = &_ccram_start,
- .hbmd_size = CCRAM_SIZE
- }
-};
-
-const struct hal_flash *
-hal_bsp_flash_dev(uint8_t id)
-{
- /*
- * Internal flash mapped to id 0.
- */
- if (id != 0) {
- return NULL;
- }
- return &stm32f4_flash_dev;
-}
-
-const struct hal_bsp_mem_dump *
-hal_bsp_core_dump(int *area_cnt)
-{
- *area_cnt = sizeof(dump_cfg) / sizeof(dump_cfg[0]);
- return dump_cfg;
-}
-
-void
-hal_bsp_init(void)
-{
- int rc;
-
- (void)rc;
-
-#if MYNEWT_VAL(UART_0)
- rc = os_dev_create((struct os_dev *) &hal_uart0, CONSOLE_UART,
- OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&uart_cfg[0]);
- assert(rc == 0);
-#endif
-#if MYNEWT_VAL(TIMER_0)
- hal_timer_init(0, TIM9);
-#endif
-}
-
-/**
- * Returns the configured priority for the given interrupt. If no priority
- * configured, return the priority passed in
- *
- * @param irq_num
- * @param pri
- *
- * @return uint32_t
- */
-uint32_t
-hal_bsp_get_nvic_priority(int irq_num, uint32_t pri)
-{
- /* Add any interrupt priorities configured by the bsp here */
- return pri;
-}
[4/9] incubator-mynewt-core git commit: Update repository yaml file
for 1.0.0.b2 release
Posted by ma...@apache.org.
Update repository yaml file for 1.0.0.b2 release
Project: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/repo
Commit: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/commit/c49b270c
Tree: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/tree/c49b270c
Diff: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/diff/c49b270c
Branch: refs/heads/develop
Commit: c49b270ce8e598bd9147ae553f4bb1785e88fd72
Parents: 581926e
Author: William San Filippo <wi...@runtime.io>
Authored: Fri Feb 3 17:09:54 2017 -0800
Committer: Alan <ag...@gemcore.com>
Committed: Thu Mar 9 12:07:38 2017 -0800
----------------------------------------------------------------------
repository.yml | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
----------------------------------------------------------------------
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/c49b270c/repository.yml
----------------------------------------------------------------------
diff --git a/repository.yml b/repository.yml
index 79990b3..3f4fe1b 100644
--- a/repository.yml
+++ b/repository.yml
@@ -25,10 +25,11 @@ repo.versions:
"0.8.0": "mynewt_0_8_0_tag"
"0.9.0": "mynewt_0_9_0_tag"
"0.9.9": "mynewt_1_0_0_b1_tag"
+ "0.9.99": "mynewt_1_0_0_b2_rc1_tag"
- "0-latest": "0.9.9" # 1.0.0-b1
+ "0-latest": "0.9.99" # 1.0.0-b2
"0-dev": "0.0.0" # develop
"0.8-latest": "0.8.0"
"0.9-latest": "0.9.0"
- "1.0-latest": "0.9.9" # 1.0.0-b1
+ "1.0-latest": "0.9.99" # 1.0.0-b2
[3/9] incubator-mynewt-core git commit: Updating version with release
1.0.0-b2 tag.
Posted by ma...@apache.org.
Updating version with release 1.0.0-b2 tag.
Project: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/repo
Commit: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/commit/2057a2df
Tree: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/tree/2057a2df
Diff: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/diff/2057a2df
Branch: refs/heads/develop
Commit: 2057a2dfbdec52216a283af8b88b36b6525e429d
Parents: c49b270
Author: William San Filippo <wi...@runtime.io>
Authored: Fri Feb 17 15:43:52 2017 -0800
Committer: Alan <ag...@gemcore.com>
Committed: Thu Mar 9 12:07:38 2017 -0800
----------------------------------------------------------------------
repository.yml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
----------------------------------------------------------------------
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/2057a2df/repository.yml
----------------------------------------------------------------------
diff --git a/repository.yml b/repository.yml
index 3f4fe1b..7aae50d 100644
--- a/repository.yml
+++ b/repository.yml
@@ -25,7 +25,7 @@ repo.versions:
"0.8.0": "mynewt_0_8_0_tag"
"0.9.0": "mynewt_0_9_0_tag"
"0.9.9": "mynewt_1_0_0_b1_tag"
- "0.9.99": "mynewt_1_0_0_b2_rc1_tag"
+ "0.9.99": "mynewt_1_0_0_b2_tag"
"0-latest": "0.9.99" # 1.0.0-b2
"0-dev": "0.0.0" # develop
[2/9] incubator-mynewt-core git commit: repository.yml;
add info about 1.0.0-rc1.
Posted by ma...@apache.org.
repository.yml; add info about 1.0.0-rc1.
Project: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/repo
Commit: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/commit/0f34d532
Tree: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/tree/0f34d532
Diff: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/diff/0f34d532
Branch: refs/heads/develop
Commit: 0f34d532014ca433b70bd21f8ff5d8136fdf6c91
Parents: 2057a2d
Author: Marko Kiiskila <ma...@runtime.io>
Authored: Tue Mar 7 17:08:33 2017 -0800
Committer: Alan <ag...@gemcore.com>
Committed: Thu Mar 9 12:07:38 2017 -0800
----------------------------------------------------------------------
repository.yml | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
----------------------------------------------------------------------
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/0f34d532/repository.yml
----------------------------------------------------------------------
diff --git a/repository.yml b/repository.yml
index 7aae50d..e0509cc 100644
--- a/repository.yml
+++ b/repository.yml
@@ -26,10 +26,11 @@ repo.versions:
"0.9.0": "mynewt_0_9_0_tag"
"0.9.9": "mynewt_1_0_0_b1_tag"
"0.9.99": "mynewt_1_0_0_b2_tag"
+ "0.9.999": "mynewt_1_0_0_rc1_tag"
- "0-latest": "0.9.99" # 1.0.0-b2
+ "0-latest": "0.9.999" # 1.0.0-rc1
"0-dev": "0.0.0" # develop
"0.8-latest": "0.8.0"
"0.9-latest": "0.9.0"
- "1.0-latest": "0.9.99" # 1.0.0-b2
+ "1.0-latest": "0.9.999" # 1.0.0-rc1
[7/9] incubator-mynewt-core git commit: BSP for 'sensorhub' board
fixed openocd issues, seems to be ok
Posted by ma...@apache.org.
BSP for 'sensorhub' board fixed openocd issues, seems to be ok
Project: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/repo
Commit: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/commit/469eabd1
Tree: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/tree/469eabd1
Diff: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/diff/469eabd1
Branch: refs/heads/develop
Commit: 469eabd1ec9bb985dd6ccbd3399df6dd8cc7fd3e
Parents: b85fcd3
Author: Alan <ag...@gemcore.com>
Authored: Wed Mar 8 16:59:21 2017 -0800
Committer: Alan <ag...@gemcore.com>
Committed: Thu Mar 9 12:07:39 2017 -0800
----------------------------------------------------------------------
apps/boot/src/boot.c | 2 +-
diff.txt | 330 +++++++++++++++++
hw/bsp/sensorhub/boot-sensorhub.ld | 31 ++
hw/bsp/sensorhub/boot-stm32f4discovery.ld | 29 --
hw/bsp/sensorhub/bsp.yml | 16 +-
hw/bsp/sensorhub/f4discovery.cfg | 22 --
hw/bsp/sensorhub/include/bsp/bsp.h | 8 +-
hw/bsp/sensorhub/include/bsp/cmsis_nvic.h | 2 +-
hw/bsp/sensorhub/pkg.yml | 4 +-
hw/bsp/sensorhub/sensorhub.cfg | 22 ++
hw/bsp/sensorhub/sensorhub.ld | 31 ++
hw/bsp/sensorhub/sensorhub_debug.cmd | 3 +
hw/bsp/sensorhub/sensorhub_debug.sh | 39 ++
hw/bsp/sensorhub/sensorhub_download.cmd | 3 +
hw/bsp/sensorhub/sensorhub_download.sh | 42 +++
.../src/arch/cortex_m4/startup_STM32F40x.s | 353 ------------------
.../src/arch/cortex_m4/startup_STM32F427xx.s | 369 +++++++++++++++++++
hw/bsp/sensorhub/src/hal_bsp.c | 13 +-
hw/bsp/sensorhub/src/hal_bsp_sav.c | 123 +++++++
hw/bsp/sensorhub/stm32f4discovery.ld | 31 --
hw/bsp/sensorhub/stm32f4discovery_debug.cmd | 3 -
hw/bsp/sensorhub/stm32f4discovery_debug.sh | 39 --
hw/bsp/sensorhub/stm32f4discovery_download.cmd | 3 -
hw/bsp/sensorhub/stm32f4discovery_download.sh | 42 ---
hw/mcu/stm/stm32f4xx/src/hal_gpio.c | 8 +-
hw/mcu/stm/stm32f4xx/stm32f427.ld | 203 ++++++++++
26 files changed, 1220 insertions(+), 551 deletions(-)
----------------------------------------------------------------------
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/469eabd1/apps/boot/src/boot.c
----------------------------------------------------------------------
diff --git a/apps/boot/src/boot.c b/apps/boot/src/boot.c
index 9cd59e7..d6f0325 100755
--- a/apps/boot/src/boot.c
+++ b/apps/boot/src/boot.c
@@ -23,7 +23,7 @@
#include "syscfg/syscfg.h"
#include <flash_map/flash_map.h>
#include <os/os.h>
-#include <bsp/bsp.h>
+
#include <hal/hal_bsp.h>
#include <hal/hal_system.h>
#include <hal/hal_flash.h>
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/469eabd1/diff.txt
----------------------------------------------------------------------
diff --git a/diff.txt b/diff.txt
new file mode 100644
index 0000000..1496b88
--- /dev/null
+++ b/diff.txt
@@ -0,0 +1,330 @@
+diff --git a/apps/boot/src/boot.c b/apps/boot/src/boot.c
+index 9cd59e7..4f4f827 100755
+--- a/apps/boot/src/boot.c
++++ b/apps/boot/src/boot.c
+@@ -23,7 +23,7 @@
+ #include "syscfg/syscfg.h"
+ #include <flash_map/flash_map.h>
+ #include <os/os.h>
+-#include <bsp/bsp.h>
++//#include <bsp/bsp.h>
+ #include <hal/hal_bsp.h>
+ #include <hal/hal_system.h>
+ #include <hal/hal_flash.h>
+diff --git a/hw/bsp/sensorhub/boot-stm32f4discovery.ld b/hw/bsp/sensorhub/boot-stm32f4discovery.ld
+deleted file mode 100644
+index ae34f19..0000000
+--- a/hw/bsp/sensorhub/boot-stm32f4discovery.ld
++++ /dev/null
+@@ -1,31 +0,0 @@
+-/*
+- * Licensed to the Apache Software Foundation (ASF) under one
+- * or more contributor license agreements. See the NOTICE file
+- * distributed with this work for additional information
+- * regarding copyright ownership. The ASF licenses this file
+- * to you under the Apache License, Version 2.0 (the
+- * "License"); you may not use this file except in compliance
+- * with the License. You may obtain a copy of the License at
+- *
+- * http://www.apache.org/licenses/LICENSE-2.0
+- *
+- * Unless required by applicable law or agreed to in writing,
+- * software distributed under the License is distributed on an
+- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+- * KIND, either express or implied. See the License for the
+- * specific language governing permissions and limitations
+- * under the License.
+- */
+-
+-/* Linker script for STM32F427 when running from flash and using the bootloader */
+-
+-/* Linker script to configure memory regions. */
+-MEMORY
+-{
+- FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 32K
+- CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
+- RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 192K
+-}
+-
+-/* The bootloader does not contain an image header */
+-_imghdr_size = 0x0;
+diff --git a/hw/bsp/sensorhub/bsp.yml b/hw/bsp/sensorhub/bsp.yml
+index c87e36a..f19e0e8 100644
+--- a/hw/bsp/sensorhub/bsp.yml
++++ b/hw/bsp/sensorhub/bsp.yml
+@@ -20,15 +20,15 @@
+ bsp.arch: cortex_m4
+ bsp.compiler: compiler/arm-none-eabi-m4
+ bsp.linkerscript:
+- - "hw/bsp/stm32f4discovery/stm32f4discovery.ld"
++ - "hw/bsp/sensorhub/sensorhub.ld"
+ - "hw/mcu/stm/stm32f4xx/stm32f427.ld"
+ bsp.linkerscript.BOOT_LOADER.OVERWRITE:
+- - "hw/bsp/stm32f4discovery/boot-stm32f4discovery.ld"
++ - "hw/bsp/sensorhub/boot-sensorhub.ld"
+ - "hw/mcu/stm/stm32f4xx/stm32f427.ld"
+-bsp.downloadscript: "hw/bsp/stm32f4discovery/stm32f4discovery_download.sh"
+-bsp.debugscript: "hw/bsp/stm32f4discovery/stm32f4discovery_debug.sh"
+-bsp.downloadscript.WINDOWS.OVERRIDE: "hw/bsp/stm32f4discovery/stm32f4discovery_download.cmd"
+-bsp.debugscript.WINDOWS.OVERRIDE: "hw/bsp/stm32f4discovery/stm32f4discovery_debug.cmd"
++bsp.downloadscript: "hw/bsp/sensorhub/sensorhub_download.sh"
++bsp.debugscript: "hw/bsp/sensorhub/sensorhub_debug.sh"
++bsp.downloadscript.WINDOWS.OVERRIDE: "hw/bsp/sensorhub/sensorhub_download.cmd"
++bsp.debugscript.WINDOWS.OVERRIDE: "hw/bsp/sensorhub/sensorhub_debug.cmd"
+
+ bsp.flash_map:
+ areas:
+diff --git a/hw/bsp/sensorhub/f4discovery.cfg b/hw/bsp/sensorhub/f4discovery.cfg
+deleted file mode 100644
+index 3fa5699..0000000
+--- a/hw/bsp/sensorhub/f4discovery.cfg
++++ /dev/null
+@@ -1,22 +0,0 @@
+-#!/bin/sh
+-# Licensed to the Apache Software Foundation (ASF) under one
+-# or more contributor license agreements. See the NOTICE file
+-# distributed with this work for additional information
+-# regarding copyright ownership. The ASF licenses this file
+-# to you under the Apache License, Version 2.0 (the
+-# "License"); you may not use this file except in compliance
+-# with the License. You may obtain a copy of the License at
+-#
+-# http://www.apache.org/licenses/LICENSE-2.0
+-#
+-# Unless required by applicable law or agreed to in writing,
+-# software distributed under the License is distributed on an
+-# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+-# KIND, either express or implied. See the License for the
+-# specific language governing permissions and limitations
+-# under the License.
+-
+-# JLink debugger
+-source [find interface/jlink.cfg]
+-transport select hla_swd
+-source [find target/stm32f4x.cfg]
+diff --git a/hw/bsp/sensorhub/include/bsp/bsp.h b/hw/bsp/sensorhub/include/bsp/bsp.h
+index f7866a2..ef7f6b4 100644
+--- a/hw/bsp/sensorhub/include/bsp/bsp.h
++++ b/hw/bsp/sensorhub/include/bsp/bsp.h
+@@ -1,4 +1,4 @@
+-/*
++quit/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+@@ -35,11 +35,10 @@ extern "C" {
+ /* More convenient section placement macros. */
+ #define bssnz_t sec_bss_nz_core
+
+-extern uint8_t _ram_start;
+-extern uint8_t _ccram_start;
+-
+ /* System SRAM including CCM (core coupled memory) data RAM. */
++extern uint8_t _ram_start;
+ #define RAM_SIZE (192 * 1024)
++extern uint8_t _ccram_start;
+ #define CCRAM_SIZE (64 * 1024)
+
+ /* 4KB of backup SRAM, accessible only from the CPU.
+@@ -54,14 +53,14 @@ extern uint8_t _ccram_start;
+ #define UART_CNT 1
+ #define CONSOLE_UART "uart0"
+
+-#if MYNEWT_VAL(BOOT_SERIAL)
++//#if MYNEWT_VAL(BOOT_SERIAL)
+ #define BOOT_SERIAL_DETECT_PIN 16 /* on Sensor Hub board BOOT0 is dedicated! */
+ #define BOOT_SERIAL_DETECT_PIN_CFG HAL_GPIO_PULL_UP
+ #define BOOT_SERIAL_DETECT_PIN_VAL 0
+
+ #define BOOT_SERIAL_REPORT_PIN LED_BLINK_PIN
+ #define BOOT_SERIAL_REPORT_FREQ (MYNEWT_VAL(OS_CPUTIME_FREQ) / 4)
+-#endif
++//#endif
+
+ #define NFFS_AREA_MAX (8)
+
+diff --git a/hw/bsp/sensorhub/src/hal_bsp.c b/hw/bsp/sensorhub/src/hal_bsp.c
+index 18a0f6c..1cea958 100644
+--- a/hw/bsp/sensorhub/src/hal_bsp.c
++++ b/hw/bsp/sensorhub/src/hal_bsp.c
+@@ -16,15 +16,10 @@
+ * specific language governing permissions and limitations
+ * under the License.
+ */
++#include <stdint.h>
++#include <stddef.h>
+ #include <assert.h>
+-
+-#include <syscfg/syscfg.h>
+-
+-#include <os/os_dev.h>
+-#if MYNEWT_VAL(UART_0)
+-#include <uart/uart.h>
+-#include <uart_hal/uart_hal.h>
+-#endif
++#include "syscfg/syscfg.h"
+
+ #include <hal/hal_bsp.h>
+ #include <hal/hal_gpio.h>
+@@ -35,7 +30,12 @@
+ #include <stm32f4xx_hal_gpio_ex.h>
+ #include <mcu/stm32f4_bsp.h>
+
+-#include "bsp/bsp.h"
++#if MYNEWT_VAL(UART_0)
++#include <uart/uart.h>
++#include <uart_hal/uart_hal.h>
++#endif
++#include "os/os_dev.h"
++#include "bsp.h"
+
+ #if MYNEWT_VAL(UART_0)
+ static struct uart_dev hal_uart0;
+diff --git a/hw/bsp/sensorhub/stm32f4discovery.ld b/hw/bsp/sensorhub/stm32f4discovery.ld
+deleted file mode 100644
+index 923a133..0000000
+--- a/hw/bsp/sensorhub/stm32f4discovery.ld
++++ /dev/null
+@@ -1,31 +0,0 @@
+-/*
+- * Licensed to the Apache Software Foundation (ASF) under one
+- * or more contributor license agreements. See the NOTICE file
+- * distributed with this work for additional information
+- * regarding copyright ownership. The ASF licenses this file
+- * to you under the Apache License, Version 2.0 (the
+- * "License"); you may not use this file except in compliance
+- * with the License. You may obtain a copy of the License at
+- *
+- * http://www.apache.org/licenses/LICENSE-2.0
+- *
+- * Unless required by applicable law or agreed to in writing,
+- * software distributed under the License is distributed on an
+- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+- * KIND, either express or implied. See the License for the
+- * specific language governing permissions and limitations
+- * under the License.
+- */
+-
+-/* Linker script for STM32F427 when running from flash and using the bootloader */
+-
+-/* Linker script to configure memory regions. */
+-MEMORY
+-{
+- FLASH (rx) : ORIGIN = 0x08020000, LENGTH = 384K /* First image slot. */
+- CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
+- RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 192K
+-}
+-
+-/* This linker script is used for images and thus contains an image header */
+-_imghdr_size = 0x20;
+diff --git a/hw/bsp/sensorhub/stm32f4discovery_debug.cmd b/hw/bsp/sensorhub/stm32f4discovery_debug.cmd
+deleted file mode 100755
+index d6cfc11..0000000
+--- a/hw/bsp/sensorhub/stm32f4discovery_debug.cmd
++++ /dev/null
+@@ -1,3 +0,0 @@
+-@rem Execute a shell with a script of the same name and .sh extension
+-
+-@bash "%~dp0%~n0.sh"
+diff --git a/hw/bsp/sensorhub/stm32f4discovery_debug.sh b/hw/bsp/sensorhub/stm32f4discovery_debug.sh
+deleted file mode 100755
+index 14b2a64..0000000
+--- a/hw/bsp/sensorhub/stm32f4discovery_debug.sh
++++ /dev/null
+@@ -1,39 +0,0 @@
+-#!/bin/sh
+-# Licensed to the Apache Software Foundation (ASF) under one
+-# or more contributor license agreements. See the NOTICE file
+-# distributed with this work for additional information
+-# regarding copyright ownership. The ASF licenses this file
+-# to you under the Apache License, Version 2.0 (the
+-# "License"); you may not use this file except in compliance
+-# with the License. You may obtain a copy of the License at
+-#
+-# http://www.apache.org/licenses/LICENSE-2.0
+-#
+-# Unless required by applicable law or agreed to in writing,
+-# software distributed under the License is distributed on an
+-# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+-# KIND, either express or implied. See the License for the
+-# specific language governing permissions and limitations
+-# under the License.
+-#
+-
+-# Called with following variables set:
+-# - CORE_PATH is absolute path to @apache-mynewt-core
+-# - BSP_PATH is absolute path to hw/bsp/bsp_name
+-# - BIN_BASENAME is the path to prefix to target binary,
+-# .elf appended to name is the ELF file
+-# - FEATURES holds the target features string
+-# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+-# - RESET set if target should be reset when attaching
+-# - NO_GDB set if we should not start gdb to debug
+-#
+-. $CORE_PATH/hw/scripts/openocd.sh
+-
+-FILE_NAME=$BIN_BASENAME.elf
+-CFG="-s $BSP_PATH -f $BSP_PATH/f4discovery.cfg"
+-#ADG! CFG="-s $BSP_PATH -f /usr/share/openocd/scripts/interface/jlink.cfg -f /home/alan/dev/myproj-2/targets/stm_blinky/openocd.cfg"
+-
+-# Exit openocd when gdb detaches.
+-EXTRA_JTAG_CMD="$EXTRA_JTAG_CMD; stm32f4x.cpu configure -event gdb-detach {if {[stm32f4x.cpu curstate] eq \"halted\"} resume;shutdown}"
+-
+-openocd_debug
+diff --git a/hw/bsp/sensorhub/stm32f4discovery_download.cmd b/hw/bsp/sensorhub/stm32f4discovery_download.cmd
+deleted file mode 100755
+index d6cfc11..0000000
+--- a/hw/bsp/sensorhub/stm32f4discovery_download.cmd
++++ /dev/null
+@@ -1,3 +0,0 @@
+-@rem Execute a shell with a script of the same name and .sh extension
+-
+-@bash "%~dp0%~n0.sh"
+diff --git a/hw/bsp/sensorhub/stm32f4discovery_download.sh b/hw/bsp/sensorhub/stm32f4discovery_download.sh
+deleted file mode 100755
+index 5a3a17d..0000000
+--- a/hw/bsp/sensorhub/stm32f4discovery_download.sh
++++ /dev/null
+@@ -1,42 +0,0 @@
+-#!/bin/sh
+-# Licensed to the Apache Software Foundation (ASF) under one
+-# or more contributor license agreements. See the NOTICE file
+-# distributed with this work for additional information
+-# regarding copyright ownership. The ASF licenses this file
+-# to you under the Apache License, Version 2.0 (the
+-# "License"); you may not use this file except in compliance
+-# with the License. You may obtain a copy of the License at
+-#
+-# http://www.apache.org/licenses/LICENSE-2.0
+-#
+-# Unless required by applicable law or agreed to in writing,
+-# software distributed under the License is distributed on an
+-# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+-# KIND, either express or implied. See the License for the
+-# specific language governing permissions and limitations
+-# under the License.
+-#
+-
+-# Called with following variables set:
+-# - CORE_PATH is absolute path to @apache-mynewt-core
+-# - BSP_PATH is absolute path to hw/bsp/bsp_name
+-# - BIN_BASENAME is the path to prefix to target binary,
+-# .elf appended to name is the ELF file
+-# - IMAGE_SLOT is the image slot to download to (for non-mfg-image, non-boot)
+-# - FEATURES holds the target features string
+-# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+-# - MFG_IMAGE is "1" if this is a manufacturing image
+-# - FLASH_OFFSET contains the flash offset to download to
+-# - BOOT_LOADER is set if downloading a bootloader
+-. $CORE_PATH/hw/scripts/openocd.sh
+-
+-CFG="-s $BSP_PATH -f f4discovery.cfg"
+-#ADG! CFG="-s $BSP_PATH -f /usr/share/openocd/scripts/interface/jlink.cfg -f /home/alan/dev/myproj-2/targets/stm_blinky/openocd.cfg"
+-
+-if [ "$MFG_IMAGE" ]; then
+- FLASH_OFFSET=0x08000000
+-fi
+-
+-common_file_to_load
+-openocd_load
+-openocd_reset_run
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/469eabd1/hw/bsp/sensorhub/boot-sensorhub.ld
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/boot-sensorhub.ld b/hw/bsp/sensorhub/boot-sensorhub.ld
new file mode 100644
index 0000000..ae34f19
--- /dev/null
+++ b/hw/bsp/sensorhub/boot-sensorhub.ld
@@ -0,0 +1,31 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/* Linker script for STM32F427 when running from flash and using the bootloader */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 32K
+ CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 192K
+}
+
+/* The bootloader does not contain an image header */
+_imghdr_size = 0x0;
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/469eabd1/hw/bsp/sensorhub/boot-stm32f4discovery.ld
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/boot-stm32f4discovery.ld b/hw/bsp/sensorhub/boot-stm32f4discovery.ld
deleted file mode 100644
index 342de6a..0000000
--- a/hw/bsp/sensorhub/boot-stm32f4discovery.ld
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-/* Linker script to configure memory regions. */
-MEMORY
-{
- FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 32K
- CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
- RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
-}
-
-/* The bootloader does not contain an image header */
-_imghdr_size = 0x0;
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/469eabd1/hw/bsp/sensorhub/bsp.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/bsp.yml b/hw/bsp/sensorhub/bsp.yml
index 658cb21..f19e0e8 100644
--- a/hw/bsp/sensorhub/bsp.yml
+++ b/hw/bsp/sensorhub/bsp.yml
@@ -20,15 +20,15 @@
bsp.arch: cortex_m4
bsp.compiler: compiler/arm-none-eabi-m4
bsp.linkerscript:
- - "hw/bsp/stm32f4discovery/stm32f4discovery.ld"
- - "hw/mcu/stm/stm32f4xx/stm32f407.ld"
+ - "hw/bsp/sensorhub/sensorhub.ld"
+ - "hw/mcu/stm/stm32f4xx/stm32f427.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- - "hw/bsp/stm32f4discovery/boot-stm32f4discovery.ld"
- - "hw/mcu/stm/stm32f4xx/stm32f407.ld"
-bsp.downloadscript: "hw/bsp/stm32f4discovery/stm32f4discovery_download.sh"
-bsp.debugscript: "hw/bsp/stm32f4discovery/stm32f4discovery_debug.sh"
-bsp.downloadscript.WINDOWS.OVERRIDE: "hw/bsp/stm32f4discovery/stm32f4discovery_download.cmd"
-bsp.debugscript.WINDOWS.OVERRIDE: "hw/bsp/stm32f4discovery/stm32f4discovery_debug.cmd"
+ - "hw/bsp/sensorhub/boot-sensorhub.ld"
+ - "hw/mcu/stm/stm32f4xx/stm32f427.ld"
+bsp.downloadscript: "hw/bsp/sensorhub/sensorhub_download.sh"
+bsp.debugscript: "hw/bsp/sensorhub/sensorhub_debug.sh"
+bsp.downloadscript.WINDOWS.OVERRIDE: "hw/bsp/sensorhub/sensorhub_download.cmd"
+bsp.debugscript.WINDOWS.OVERRIDE: "hw/bsp/sensorhub/sensorhub_debug.cmd"
bsp.flash_map:
areas:
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/469eabd1/hw/bsp/sensorhub/f4discovery.cfg
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/f4discovery.cfg b/hw/bsp/sensorhub/f4discovery.cfg
deleted file mode 100644
index 694ab8d..0000000
--- a/hw/bsp/sensorhub/f4discovery.cfg
+++ /dev/null
@@ -1,22 +0,0 @@
-#!/bin/sh
-# Licensed to the Apache Software Foundation (ASF) under one
-# or more contributor license agreements. See the NOTICE file
-# distributed with this work for additional information
-# regarding copyright ownership. The ASF licenses this file
-# to you under the Apache License, Version 2.0 (the
-# "License"); you may not use this file except in compliance
-# with the License. You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing,
-# software distributed under the License is distributed on an
-# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
-# KIND, either express or implied. See the License for the
-# specific language governing permissions and limitations
-# under the License.
-
-# New version of St-link
-source [find interface/stlink-v2-1.cfg]
-transport select hla_swd
-source [find target/stm32f4x.cfg]
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/469eabd1/hw/bsp/sensorhub/include/bsp/bsp.h
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/include/bsp/bsp.h b/hw/bsp/sensorhub/include/bsp/bsp.h
index da9ffc4..822a2ca 100644
--- a/hw/bsp/sensorhub/include/bsp/bsp.h
+++ b/hw/bsp/sensorhub/include/bsp/bsp.h
@@ -35,11 +35,11 @@ extern "C" {
/* More convenient section placement macros. */
#define bssnz_t sec_bss_nz_core
+/* System SRAM */
extern uint8_t _ram_start;
+#define RAM_SIZE (192 * 1024)
+/* System CCM (core coupled memory) data RAM. */
extern uint8_t _ccram_start;
-
-/* System SRAM including CCM (core coupled memory) data RAM. */
-#define RAM_SIZE (256 * 1024)
#define CCRAM_SIZE (64 * 1024)
/* 4KB of backup SRAM, accessible only from the CPU.
@@ -50,7 +50,7 @@ extern uint8_t _ccram_start;
/* LED pins */
#define LED_BLINK_PIN MCU_GPIO_PORTD(12)
-/* UART */
+/* UART pins */
#define UART_CNT 1
#define CONSOLE_UART "uart0"
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/469eabd1/hw/bsp/sensorhub/include/bsp/cmsis_nvic.h
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/include/bsp/cmsis_nvic.h b/hw/bsp/sensorhub/include/bsp/cmsis_nvic.h
index d0c8b44..f61c10b 100644
--- a/hw/bsp/sensorhub/include/bsp/cmsis_nvic.h
+++ b/hw/bsp/sensorhub/include/bsp/cmsis_nvic.h
@@ -9,7 +9,7 @@
#include <stdint.h>
-#define NVIC_NUM_VECTORS (16 + 81) // CORE + MCU Peripherals
+#define NVIC_NUM_VECTORS (16 + 90) // CORE + MCU Peripherals
#define NVIC_USER_IRQ_OFFSET 16
#include "stm32f4xx.h"
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/469eabd1/hw/bsp/sensorhub/pkg.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/pkg.yml b/hw/bsp/sensorhub/pkg.yml
index d329ea4..d4063c9 100644
--- a/hw/bsp/sensorhub/pkg.yml
+++ b/hw/bsp/sensorhub/pkg.yml
@@ -25,9 +25,9 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
- stm32
- stm32f4
- - discovery
+ - sensorhub
-pkg.cflags: -DSTM32F407xx
+pkg.cflags: -DSTM32F427xx
pkg.cflags.HARDFLOAT:
- -mfloat-abi=hard -mfpu=fpv4-sp-d16
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/469eabd1/hw/bsp/sensorhub/sensorhub.cfg
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/sensorhub.cfg b/hw/bsp/sensorhub/sensorhub.cfg
new file mode 100644
index 0000000..0758e0a
--- /dev/null
+++ b/hw/bsp/sensorhub/sensorhub.cfg
@@ -0,0 +1,22 @@
+#!/bin/sh
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+
+# JLink debugger
+source [find interface/jlink.cfg]
+transport select jtag
+source [find target/stm32f4x.cfg]
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/469eabd1/hw/bsp/sensorhub/sensorhub.ld
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/sensorhub.ld b/hw/bsp/sensorhub/sensorhub.ld
new file mode 100644
index 0000000..923a133
--- /dev/null
+++ b/hw/bsp/sensorhub/sensorhub.ld
@@ -0,0 +1,31 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/* Linker script for STM32F427 when running from flash and using the bootloader */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08020000, LENGTH = 384K /* First image slot. */
+ CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 192K
+}
+
+/* This linker script is used for images and thus contains an image header */
+_imghdr_size = 0x20;
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/469eabd1/hw/bsp/sensorhub/sensorhub_debug.cmd
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/sensorhub_debug.cmd b/hw/bsp/sensorhub/sensorhub_debug.cmd
new file mode 100755
index 0000000..d6cfc11
--- /dev/null
+++ b/hw/bsp/sensorhub/sensorhub_debug.cmd
@@ -0,0 +1,3 @@
+@rem Execute a shell with a script of the same name and .sh extension
+
+@bash "%~dp0%~n0.sh"
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/469eabd1/hw/bsp/sensorhub/sensorhub_debug.sh
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/sensorhub_debug.sh b/hw/bsp/sensorhub/sensorhub_debug.sh
new file mode 100755
index 0000000..109aa55
--- /dev/null
+++ b/hw/bsp/sensorhub/sensorhub_debug.sh
@@ -0,0 +1,39 @@
+#!/bin/sh
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Called with following variables set:
+# - CORE_PATH is absolute path to @apache-mynewt-core
+# - BSP_PATH is absolute path to hw/bsp/bsp_name
+# - BIN_BASENAME is the path to prefix to target binary,
+# .elf appended to name is the ELF file
+# - FEATURES holds the target features string
+# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+# - RESET set if target should be reset when attaching
+# - NO_GDB set if we should not start gdb to debug
+#
+. $CORE_PATH/hw/scripts/openocd.sh
+
+FILE_NAME=$BIN_BASENAME.elf
+CFG="-s $BSP_PATH -f $BSP_PATH/sensorhub.cfg"
+#ADG! CFG="-s $BSP_PATH -f /usr/share/openocd/scripts/interface/jlink.cfg -f /home/alan/dev/myproj-2/targets/stm_blinky/openocd.cfg"
+
+# Exit openocd when gdb detaches.
+EXTRA_JTAG_CMD="$EXTRA_JTAG_CMD; stm32f4x.cpu configure -event gdb-detach {if {[stm32f4x.cpu curstate] eq \"halted\"} resume;shutdown}"
+
+openocd_debug
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/469eabd1/hw/bsp/sensorhub/sensorhub_download.cmd
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/sensorhub_download.cmd b/hw/bsp/sensorhub/sensorhub_download.cmd
new file mode 100755
index 0000000..d6cfc11
--- /dev/null
+++ b/hw/bsp/sensorhub/sensorhub_download.cmd
@@ -0,0 +1,3 @@
+@rem Execute a shell with a script of the same name and .sh extension
+
+@bash "%~dp0%~n0.sh"
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/469eabd1/hw/bsp/sensorhub/sensorhub_download.sh
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/sensorhub_download.sh b/hw/bsp/sensorhub/sensorhub_download.sh
new file mode 100755
index 0000000..14fe38a
--- /dev/null
+++ b/hw/bsp/sensorhub/sensorhub_download.sh
@@ -0,0 +1,42 @@
+#!/bin/sh
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Called with following variables set:
+# - CORE_PATH is absolute path to @apache-mynewt-core
+# - BSP_PATH is absolute path to hw/bsp/bsp_name
+# - BIN_BASENAME is the path to prefix to target binary,
+# .elf appended to name is the ELF file
+# - IMAGE_SLOT is the image slot to download to (for non-mfg-image, non-boot)
+# - FEATURES holds the target features string
+# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+# - MFG_IMAGE is "1" if this is a manufacturing image
+# - FLASH_OFFSET contains the flash offset to download to
+# - BOOT_LOADER is set if downloading a bootloader
+. $CORE_PATH/hw/scripts/openocd.sh
+
+CFG="-s $BSP_PATH -f sensorhub.cfg"
+#ADG! CFG="-s $BSP_PATH -f /usr/share/openocd/scripts/interface/jlink.cfg -f /home/alan/dev/myproj-2/targets/stm_blinky/openocd.cfg"
+
+if [ "$MFG_IMAGE" ]; then
+ FLASH_OFFSET=0x08000000
+fi
+
+common_file_to_load
+openocd_load
+openocd_reset_run
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/469eabd1/hw/bsp/sensorhub/src/arch/cortex_m4/startup_STM32F40x.s
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/src/arch/cortex_m4/startup_STM32F40x.s b/hw/bsp/sensorhub/src/arch/cortex_m4/startup_STM32F40x.s
deleted file mode 100644
index e84feac..0000000
--- a/hw/bsp/sensorhub/src/arch/cortex_m4/startup_STM32F40x.s
+++ /dev/null
@@ -1,353 +0,0 @@
-/* File: startup_STM32F40x.S
- * Purpose: startup file for Cortex-M4 devices. Should use with
- * GCC for ARM Embedded Processors
- * Version: V1.4
- * Date: 09 July 2012
- *
- * Copyright (c) 2011, 2012, ARM Limited
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- * Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- * Neither the name of the ARM Limited nor the
- names of its contributors may be used to endorse or promote products
- derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
- .syntax unified
- .arch armv7-m
-
- .section .stack
- .align 3
-#ifdef __STACK_SIZE
- .equ Stack_Size, __STACK_SIZE
-#else
- .equ Stack_Size, 0xc00
-#endif
- .globl __StackTop
- .globl __StackLimit
-__StackLimit:
- .space Stack_Size
- .size __StackLimit, . - __StackLimit
-__StackTop:
- .size __StackTop, . - __StackTop
-
- .section .heap
- .align 3
-#ifdef __HEAP_SIZE
- .equ Heap_Size, __HEAP_SIZE
-#else
- .equ Heap_Size, 0
-#endif
- .globl __HeapBase
- .globl __HeapLimit
-__HeapBase:
- .if Heap_Size
- .space Heap_Size
- .endif
- .size __HeapBase, . - __HeapBase
-__HeapLimit:
- .size __HeapLimit, . - __HeapLimit
-
- .section .isr_vector
- .align 2
- .globl __isr_vector
-__isr_vector:
- .long __StackTop /* Top of Stack */
- .long Reset_Handler /* Reset Handler */
- .long NMI_Handler /* NMI Handler */
- .long HardFault_Handler /* Hard Fault Handler */
- .long MemManage_Handler /* MPU Fault Handler */
- .long BusFault_Handler /* Bus Fault Handler */
- .long UsageFault_Handler /* Usage Fault Handler */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long 0 /* Reserved */
- .long SVC_Handler /* SVCall Handler */
- .long DebugMon_Handler /* Debug Monitor Handler */
- .long 0 /* Reserved */
- .long PendSV_Handler /* PendSV Handler */
- .long SysTick_Handler /* SysTick Handler */
-
- /* External interrupts */
- .long WWDG_IRQHandler /* Window WatchDog */
- .long PVD_IRQHandler /* PVD through EXTI Line detection */
- .long TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
- .long RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
- .long FLASH_IRQHandler /* FLASH */
- .long RCC_IRQHandler /* RCC */
- .long EXTI0_IRQHandler /* EXTI Line0 */
- .long EXTI1_IRQHandler /* EXTI Line1 */
- .long EXTI2_IRQHandler /* EXTI Line2 */
- .long EXTI3_IRQHandler /* EXTI Line3 */
- .long EXTI4_IRQHandler /* EXTI Line4 */
- .long DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
- .long DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
- .long DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
- .long DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
- .long DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
- .long DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
- .long DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
- .long ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
- .long CAN1_TX_IRQHandler /* CAN1 TX */
- .long CAN1_RX0_IRQHandler /* CAN1 RX0 */
- .long CAN1_RX1_IRQHandler /* CAN1 RX1 */
- .long CAN1_SCE_IRQHandler /* CAN1 SCE */
- .long EXTI9_5_IRQHandler /* External Line[9:5]s */
- .long TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
- .long TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
- .long TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
- .long TIM1_CC_IRQHandler /* TIM1 Capture Compare */
- .long TIM2_IRQHandler /* TIM2 */
- .long TIM3_IRQHandler /* TIM3 */
- .long TIM4_IRQHandler /* TIM4 */
- .long I2C1_EV_IRQHandler /* I2C1 Event */
- .long I2C1_ER_IRQHandler /* I2C1 Error */
- .long I2C2_EV_IRQHandler /* I2C2 Event */
- .long I2C2_ER_IRQHandler /* I2C2 Error */
- .long SPI1_IRQHandler /* SPI1 */
- .long SPI2_IRQHandler /* SPI2 */
- .long USART1_IRQHandler /* USART1 */
- .long USART2_IRQHandler /* USART2 */
- .long USART3_IRQHandler /* USART3 */
- .long EXTI15_10_IRQHandler /* External Line[15:10]s */
- .long RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
- .long OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
- .long TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
- .long TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
- .long TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
- .long TIM8_CC_IRQHandler /* TIM8 Capture Compare */
- .long DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
- .long FSMC_IRQHandler /* FSMC */
- .long SDIO_IRQHandler /* SDIO */
- .long TIM5_IRQHandler /* TIM5 */
- .long SPI3_IRQHandler /* SPI3 */
- .long UART4_IRQHandler /* UART4 */
- .long UART5_IRQHandler /* UART5 */
- .long TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
- .long TIM7_IRQHandler /* TIM7 */
- .long DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
- .long DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
- .long DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
- .long DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
- .long DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
- .long ETH_IRQHandler /* Ethernet */
- .long ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
- .long CAN2_TX_IRQHandler /* CAN2 TX */
- .long CAN2_RX0_IRQHandler /* CAN2 RX0 */
- .long CAN2_RX1_IRQHandler /* CAN2 RX1 */
- .long CAN2_SCE_IRQHandler /* CAN2 SCE */
- .long OTG_FS_IRQHandler /* USB OTG FS */
- .long DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
- .long DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
- .long DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
- .long USART6_IRQHandler /* USART6 */
- .long I2C3_EV_IRQHandler /* I2C3 event */
- .long I2C3_ER_IRQHandler /* I2C3 error */
- .long OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
- .long OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
- .long OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
- .long OTG_HS_IRQHandler /* USB OTG HS */
- .long DCMI_IRQHandler /* DCMI */
- .long CRYP_IRQHandler /* CRYP crypto */
- .long HASH_RNG_IRQHandler /* Hash and Rng */
- .long FPU_IRQHandler /* FPU */
-
- .size __isr_vector, . - __isr_vector
-
- .text
- .thumb
- .thumb_func
- .align 2
- .globl Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
-/* Copy data core section from flash to RAM */
- ldr r1, =__etext
- ldr r2, =__coredata_start__
- ldr r3, =__coredata_end__
-
-.LC0:
- cmp r2, r3
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r2], #4
- blt .LC0
-
-/* Loop to copy data from read only memory to RAM. The ranges
- * of copy from/to are specified by following symbols evaluated in
- * linker script.
- * __etext: End of code section, i.e., begin of data sections to copy from.
- * __data_start__/__data_end__: RAM address range that data should be
- * copied to. Both must be aligned to 4 bytes boundary. */
- ldr r1, =__ecoredata
- ldr r2, =__data_start__
- ldr r3, =__data_end__
-
-.LC1:
- cmp r2, r3
- ittt lt
- ldrlt r0, [r1], #4
- strlt r0, [r2], #4
- blt .LC1
-
-/* Set the bss core section to zero */
- mov r0, #0
- ldr r1, =__corebss_start__
- ldr r2, =__corebss_end__
-
-.LC2:
- cmp r1, r2
- itt lt
- strlt r0, [r1], #4
- blt .LC2
-
- /* Set the other bss section to zero as well*/
- ldr r1, =__bss_start__
- ldr r2, =__bss_end__
-
-.LC3:
- cmp r1, r2
- itt lt
- strlt r0, [r1], #4
- blt .LC3
-
-/* Call system initialization and startup routines */
- ldr r0, =SystemInit
- blx r0
- ldr r0, =_start
- bx r0
- .pool
- .size Reset_Handler, . - Reset_Handler
-
- .text
-/* Macro to define default handlers. Default handler
- * will be weak symbol and just dead loops. They can be
- * overwritten by other handlers */
- .macro def_default_handler handler_name
- .align 1
- .thumb_func
- .weak \handler_name
- .type \handler_name, %function
-\handler_name :
- b .
- .size \handler_name, . - \handler_name
- .endm
-
- def_default_handler NMI_Handler
- def_default_handler HardFault_Handler
- def_default_handler MemManage_Handler
- def_default_handler BusFault_Handler
- def_default_handler UsageFault_Handler
- def_default_handler SVC_Handler
- def_default_handler DebugMon_Handler
- def_default_handler PendSV_Handler
- def_default_handler SysTick_Handler
- def_default_handler Default_Handler
-
- .macro def_irq_default_handler handler_name
- .weak \handler_name
- .set \handler_name, Default_Handler
- .endm
-
- def_irq_default_handler WWDG_IRQHandler
- def_irq_default_handler PVD_IRQHandler
- def_irq_default_handler TAMP_STAMP_IRQHandler
- def_irq_default_handler RTC_WKUP_IRQHandler
- def_irq_default_handler FLASH_IRQHandler
- def_irq_default_handler RCC_IRQHandler
- def_irq_default_handler EXTI0_IRQHandler
- def_irq_default_handler EXTI1_IRQHandler
- def_irq_default_handler EXTI2_IRQHandler
- def_irq_default_handler EXTI3_IRQHandler
- def_irq_default_handler EXTI4_IRQHandler
- def_irq_default_handler DMA1_Stream0_IRQHandler
- def_irq_default_handler DMA1_Stream1_IRQHandler
- def_irq_default_handler DMA1_Stream2_IRQHandler
- def_irq_default_handler DMA1_Stream3_IRQHandler
- def_irq_default_handler DMA1_Stream4_IRQHandler
- def_irq_default_handler DMA1_Stream5_IRQHandler
- def_irq_default_handler DMA1_Stream6_IRQHandler
- def_irq_default_handler ADC_IRQHandler
- def_irq_default_handler CAN1_TX_IRQHandler
- def_irq_default_handler CAN1_RX0_IRQHandler
- def_irq_default_handler CAN1_RX1_IRQHandler
- def_irq_default_handler CAN1_SCE_IRQHandler
- def_irq_default_handler EXTI9_5_IRQHandler
- def_irq_default_handler TIM1_BRK_TIM9_IRQHandler
- def_irq_default_handler TIM1_UP_TIM10_IRQHandler
- def_irq_default_handler TIM1_TRG_COM_TIM11_IRQHandler
- def_irq_default_handler TIM1_CC_IRQHandler
- def_irq_default_handler TIM2_IRQHandler
- def_irq_default_handler TIM3_IRQHandler
- def_irq_default_handler TIM4_IRQHandler
- def_irq_default_handler I2C1_EV_IRQHandler
- def_irq_default_handler I2C1_ER_IRQHandler
- def_irq_default_handler I2C2_EV_IRQHandler
- def_irq_default_handler I2C2_ER_IRQHandler
- def_irq_default_handler SPI1_IRQHandler
- def_irq_default_handler SPI2_IRQHandler
- def_irq_default_handler USART1_IRQHandler
- def_irq_default_handler USART2_IRQHandler
- def_irq_default_handler USART3_IRQHandler
- def_irq_default_handler EXTI15_10_IRQHandler
- def_irq_default_handler RTC_Alarm_IRQHandler
- def_irq_default_handler OTG_FS_WKUP_IRQHandler
- def_irq_default_handler TIM8_BRK_TIM12_IRQHandler
- def_irq_default_handler TIM8_UP_TIM13_IRQHandler
- def_irq_default_handler TIM8_TRG_COM_TIM14_IRQHandler
- def_irq_default_handler TIM8_CC_IRQHandler
- def_irq_default_handler DMA1_Stream7_IRQHandler
- def_irq_default_handler FSMC_IRQHandler
- def_irq_default_handler SDIO_IRQHandler
- def_irq_default_handler TIM5_IRQHandler
- def_irq_default_handler SPI3_IRQHandler
- def_irq_default_handler UART4_IRQHandler
- def_irq_default_handler UART5_IRQHandler
- def_irq_default_handler TIM6_DAC_IRQHandler
- def_irq_default_handler TIM7_IRQHandler
- def_irq_default_handler DMA2_Stream0_IRQHandler
- def_irq_default_handler DMA2_Stream1_IRQHandler
- def_irq_default_handler DMA2_Stream2_IRQHandler
- def_irq_default_handler DMA2_Stream3_IRQHandler
- def_irq_default_handler DMA2_Stream4_IRQHandler
- def_irq_default_handler ETH_IRQHandler
- def_irq_default_handler ETH_WKUP_IRQHandler
- def_irq_default_handler CAN2_TX_IRQHandler
- def_irq_default_handler CAN2_RX0_IRQHandler
- def_irq_default_handler CAN2_RX1_IRQHandler
- def_irq_default_handler CAN2_SCE_IRQHandler
- def_irq_default_handler OTG_FS_IRQHandler
- def_irq_default_handler DMA2_Stream5_IRQHandler
- def_irq_default_handler DMA2_Stream6_IRQHandler
- def_irq_default_handler DMA2_Stream7_IRQHandler
- def_irq_default_handler USART6_IRQHandler
- def_irq_default_handler I2C3_EV_IRQHandler
- def_irq_default_handler I2C3_ER_IRQHandler
- def_irq_default_handler OTG_HS_EP1_OUT_IRQHandler
- def_irq_default_handler OTG_HS_EP1_IN_IRQHandler
- def_irq_default_handler OTG_HS_WKUP_IRQHandler
- def_irq_default_handler OTG_HS_IRQHandler
- def_irq_default_handler DCMI_IRQHandler
- def_irq_default_handler CRYP_IRQHandler
- def_irq_default_handler HASH_RNG_IRQHandler
- def_irq_default_handler FPU_IRQHandler
- def_irq_default_handler DEF_IRQHandler
-
- .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/469eabd1/hw/bsp/sensorhub/src/arch/cortex_m4/startup_STM32F427xx.s
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/src/arch/cortex_m4/startup_STM32F427xx.s b/hw/bsp/sensorhub/src/arch/cortex_m4/startup_STM32F427xx.s
new file mode 100644
index 0000000..996ad81
--- /dev/null
+++ b/hw/bsp/sensorhub/src/arch/cortex_m4/startup_STM32F427xx.s
@@ -0,0 +1,369 @@
+/* File: startup_STM32F42x.S
+ * Purpose: startup file for Cortex-M4 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V1.4
+ * Date: 09 July 2012
+ *
+ * Copyright (c) 2011, 2012, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of the ARM Limited nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ .syntax unified
+ .arch armv7-m
+
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0xc00
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long WWDG_IRQHandler /* Window WatchDog */
+ .long PVD_IRQHandler /* PVD through EXTI Line detection */
+ .long TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .long RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .long FLASH_IRQHandler /* FLASH */
+ .long RCC_IRQHandler /* RCC */
+ .long EXTI0_IRQHandler /* EXTI Line0 */
+ .long EXTI1_IRQHandler /* EXTI Line1 */
+ .long EXTI2_IRQHandler /* EXTI Line2 */
+ .long EXTI3_IRQHandler /* EXTI Line3 */
+ .long EXTI4_IRQHandler /* EXTI Line4 */
+ .long DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .long DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .long DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .long DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .long DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .long DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .long DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .long ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .long CAN1_TX_IRQHandler /* CAN1 TX */
+ .long CAN1_RX0_IRQHandler /* CAN1 RX0 */
+ .long CAN1_RX1_IRQHandler /* CAN1 RX1 */
+ .long CAN1_SCE_IRQHandler /* CAN1 SCE */
+ .long EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .long TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
+ .long TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
+ .long TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
+ .long TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .long TIM2_IRQHandler /* TIM2 */
+ .long TIM3_IRQHandler /* TIM3 */
+ .long TIM4_IRQHandler /* TIM4 */
+ .long I2C1_EV_IRQHandler /* I2C1 Event */
+ .long I2C1_ER_IRQHandler /* I2C1 Error */
+ .long I2C2_EV_IRQHandler /* I2C2 Event */
+ .long I2C2_ER_IRQHandler /* I2C2 Error */
+ .long SPI1_IRQHandler /* SPI1 */
+ .long SPI2_IRQHandler /* SPI2 */
+ .long USART1_IRQHandler /* USART1 */
+ .long USART2_IRQHandler /* USART2 */
+ .long USART3_IRQHandler /* USART3 */
+ .long EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .long RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .long OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
+ .long TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .long TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .long TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .long TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .long DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .long FSMC_IRQHandler /* FSMC */
+ .long SDIO_IRQHandler /* SDIO */
+ .long TIM5_IRQHandler /* TIM5 */
+ .long SPI3_IRQHandler /* SPI3 */
+ .long UART4_IRQHandler /* UART4 */
+ .long UART5_IRQHandler /* UART5 */
+ .long TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .long TIM7_IRQHandler /* TIM7 */
+ .long DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .long DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .long DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .long DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .long DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .long ETH_IRQHandler /* Ethernet */
+ .long ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
+ .long CAN2_TX_IRQHandler /* CAN2 TX */
+ .long CAN2_RX0_IRQHandler /* CAN2 RX0 */
+ .long CAN2_RX1_IRQHandler /* CAN2 RX1 */
+ .long CAN2_SCE_IRQHandler /* CAN2 SCE */
+ .long OTG_FS_IRQHandler /* USB OTG FS */
+ .long DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .long DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .long DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .long USART6_IRQHandler /* USART6 */
+ .long I2C3_EV_IRQHandler /* I2C3 event */
+ .long I2C3_ER_IRQHandler /* I2C3 error */
+ .long OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .long OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .long OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .long OTG_HS_IRQHandler /* USB OTG HS */
+ .long DCMI_IRQHandler /* DCMI */
+ .long CRYP_IRQHandler /* CRYP crypto */
+ .long HASH_RNG_IRQHandler /* Hash and Rng */
+ .long FPU_IRQHandler /* FPU */
+ .long UART7_IRQHandler /* UART7 */
+ .long UART8_IRQHandler /* UART8 */
+ .long SPI4_IRQHandler /* SPI4 */
+ .long SPI5_IRQHandler /* SPI5 */
+ .long SPI6_IRQHandler /* SPI6 */
+ .long SAI1_IRQHandler /* SAI1 */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long DMA2D_IRQHandler /* DMA2D */
+
+ .size __isr_vector, . - __isr_vector
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Copy data core section from flash to RAM */
+ ldr r1, =__etext
+ ldr r2, =__coredata_start__
+ ldr r3, =__coredata_end__
+
+.LC0:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .LC0
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+ ldr r1, =__ecoredata
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.LC1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .LC1
+
+/* Set the bss core section to zero */
+ mov r0, #0
+ ldr r1, =__corebss_start__
+ ldr r2, =__corebss_end__
+
+.LC2:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .LC2
+
+ /* Set the other bss section to zero as well*/
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+.LC3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .LC3
+
+/* Call system initialization and startup routines */
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler MemManage_Handler
+ def_default_handler BusFault_Handler
+ def_default_handler UsageFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler DebugMon_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_default_handler WWDG_IRQHandler
+ def_irq_default_handler PVD_IRQHandler
+ def_irq_default_handler TAMP_STAMP_IRQHandler
+ def_irq_default_handler RTC_WKUP_IRQHandler
+ def_irq_default_handler FLASH_IRQHandler
+ def_irq_default_handler RCC_IRQHandler
+ def_irq_default_handler EXTI0_IRQHandler
+ def_irq_default_handler EXTI1_IRQHandler
+ def_irq_default_handler EXTI2_IRQHandler
+ def_irq_default_handler EXTI3_IRQHandler
+ def_irq_default_handler EXTI4_IRQHandler
+ def_irq_default_handler DMA1_Stream0_IRQHandler
+ def_irq_default_handler DMA1_Stream1_IRQHandler
+ def_irq_default_handler DMA1_Stream2_IRQHandler
+ def_irq_default_handler DMA1_Stream3_IRQHandler
+ def_irq_default_handler DMA1_Stream4_IRQHandler
+ def_irq_default_handler DMA1_Stream5_IRQHandler
+ def_irq_default_handler DMA1_Stream6_IRQHandler
+ def_irq_default_handler ADC_IRQHandler
+ def_irq_default_handler CAN1_TX_IRQHandler
+ def_irq_default_handler CAN1_RX0_IRQHandler
+ def_irq_default_handler CAN1_RX1_IRQHandler
+ def_irq_default_handler CAN1_SCE_IRQHandler
+ def_irq_default_handler EXTI9_5_IRQHandler
+ def_irq_default_handler TIM1_BRK_TIM9_IRQHandler
+ def_irq_default_handler TIM1_UP_TIM10_IRQHandler
+ def_irq_default_handler TIM1_TRG_COM_TIM11_IRQHandler
+ def_irq_default_handler TIM1_CC_IRQHandler
+ def_irq_default_handler TIM2_IRQHandler
+ def_irq_default_handler TIM3_IRQHandler
+ def_irq_default_handler TIM4_IRQHandler
+ def_irq_default_handler I2C1_EV_IRQHandler
+ def_irq_default_handler I2C1_ER_IRQHandler
+ def_irq_default_handler I2C2_EV_IRQHandler
+ def_irq_default_handler I2C2_ER_IRQHandler
+ def_irq_default_handler SPI1_IRQHandler
+ def_irq_default_handler SPI2_IRQHandler
+ def_irq_default_handler USART1_IRQHandler
+ def_irq_default_handler USART2_IRQHandler
+ def_irq_default_handler USART3_IRQHandler
+ def_irq_default_handler EXTI15_10_IRQHandler
+ def_irq_default_handler RTC_Alarm_IRQHandler
+ def_irq_default_handler OTG_FS_WKUP_IRQHandler
+ def_irq_default_handler TIM8_BRK_TIM12_IRQHandler
+ def_irq_default_handler TIM8_UP_TIM13_IRQHandler
+ def_irq_default_handler TIM8_TRG_COM_TIM14_IRQHandler
+ def_irq_default_handler TIM8_CC_IRQHandler
+ def_irq_default_handler DMA1_Stream7_IRQHandler
+ def_irq_default_handler FSMC_IRQHandler
+ def_irq_default_handler SDIO_IRQHandler
+ def_irq_default_handler TIM5_IRQHandler
+ def_irq_default_handler SPI3_IRQHandler
+ def_irq_default_handler UART4_IRQHandler
+ def_irq_default_handler UART5_IRQHandler
+ def_irq_default_handler TIM6_DAC_IRQHandler
+ def_irq_default_handler TIM7_IRQHandler
+ def_irq_default_handler DMA2_Stream0_IRQHandler
+ def_irq_default_handler DMA2_Stream1_IRQHandler
+ def_irq_default_handler DMA2_Stream2_IRQHandler
+ def_irq_default_handler DMA2_Stream3_IRQHandler
+ def_irq_default_handler DMA2_Stream4_IRQHandler
+ def_irq_default_handler ETH_IRQHandler
+ def_irq_default_handler ETH_WKUP_IRQHandler
+ def_irq_default_handler CAN2_TX_IRQHandler
+ def_irq_default_handler CAN2_RX0_IRQHandler
+ def_irq_default_handler CAN2_RX1_IRQHandler
+ def_irq_default_handler CAN2_SCE_IRQHandler
+ def_irq_default_handler OTG_FS_IRQHandler
+ def_irq_default_handler DMA2_Stream5_IRQHandler
+ def_irq_default_handler DMA2_Stream6_IRQHandler
+ def_irq_default_handler DMA2_Stream7_IRQHandler
+ def_irq_default_handler USART6_IRQHandler
+ def_irq_default_handler I2C3_EV_IRQHandler
+ def_irq_default_handler I2C3_ER_IRQHandler
+ def_irq_default_handler OTG_HS_EP1_OUT_IRQHandler
+ def_irq_default_handler OTG_HS_EP1_IN_IRQHandler
+ def_irq_default_handler OTG_HS_WKUP_IRQHandler
+ def_irq_default_handler OTG_HS_IRQHandler
+ def_irq_default_handler DCMI_IRQHandler
+ def_irq_default_handler CRYP_IRQHandler
+ def_irq_default_handler HASH_RNG_IRQHandler
+ def_irq_default_handler FPU_IRQHandler
+ def_irq_default_handler UART7_IRQHandler
+ def_irq_default_handler UART8_IRQHandler
+ def_irq_default_handler SPI4_IRQHandler
+ def_irq_default_handler SPI5_IRQHandler
+ def_irq_default_handler SPI6_IRQHandler
+ def_irq_default_handler SAI1_IRQHandler
+ def_irq_default_handler DMA2D_IRQHandler
+ def_irq_default_handler DEF_IRQHandler
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/469eabd1/hw/bsp/sensorhub/src/hal_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/src/hal_bsp.c b/hw/bsp/sensorhub/src/hal_bsp.c
index 0f2cbfe..722a13b 100644
--- a/hw/bsp/sensorhub/src/hal_bsp.c
+++ b/hw/bsp/sensorhub/src/hal_bsp.c
@@ -17,24 +17,19 @@
* under the License.
*/
#include <assert.h>
-
-#include <syscfg/syscfg.h>
-
-#include <os/os_dev.h>
+#include "syscfg/syscfg.h"
+#include "os/os_dev.h"
#if MYNEWT_VAL(UART_0)
#include <uart/uart.h>
#include <uart_hal/uart_hal.h>
#endif
-
#include <hal/hal_bsp.h>
#include <hal/hal_gpio.h>
#include <hal/hal_flash_int.h>
#include <hal/hal_timer.h>
-
-#include <stm32f407xx.h> //ADG! Should be using stm32f427xx.h
+#include <stm32f427xx.h>
#include <stm32f4xx_hal_gpio_ex.h>
#include <mcu/stm32f4_bsp.h>
-
#include "bsp/bsp.h"
#if MYNEWT_VAL(UART_0)
@@ -43,7 +38,7 @@ static struct uart_dev hal_uart0;
static const struct stm32f4_uart_cfg uart_cfg[UART_CNT] = {
[0] = {
.suc_uart = UART4,
- .suc_rcc_reg = &RCC->APB2ENR,
+ .suc_rcc_reg = &RCC->APB1ENR,
.suc_rcc_dev = RCC_APB1ENR_UART4EN,
.suc_pin_tx = MCU_GPIO_PORTC(10), /* PC10 */
.suc_pin_rx = MCU_GPIO_PORTC(11), /* PC11 */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/469eabd1/hw/bsp/sensorhub/src/hal_bsp_sav.c
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/src/hal_bsp_sav.c b/hw/bsp/sensorhub/src/hal_bsp_sav.c
new file mode 100644
index 0000000..2d18815
--- /dev/null
+++ b/hw/bsp/sensorhub/src/hal_bsp_sav.c
@@ -0,0 +1,123 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+//#include <stdint.h>
+//#include <stddef.h>
+#include <assert.h>
+#include "syscfg/syscfg.h"
+//#include "bsp/bsp.h"
+
+#if MYNEWT_VAL(UART_0)
+//#include <uart/uart.h>
+//#include <uart_hal/uart_hal.h>
+#endif
+#include "os/os_dev.h"
+
+#include <hal/hal_bsp.h>
+#include <hal/hal_gpio.h>
+#include <hal/hal_flash_int.h>
+#include <hal/hal_timer.h>
+
+#include <stm32f427xx.h>
+#include <stm32f4xx_hal_gpio_ex.h>
+#include <mcu/stm32f4_bsp.h>
+
+#if MYNEWT_VAL(UART_0)
+#include "bsp/bsp.h"
+#include <uart/uart.h>
+#include <uart_hal/uart_hal.h>
+
+static struct uart_dev hal_uart0;
+
+static const struct stm32f4_uart_cfg uart_cfg[UART_CNT] = {
+ [0] = {
+ .suc_uart = UART4,
+ .suc_rcc_reg = &RCC->APB1ENR,
+ .suc_rcc_dev = RCC_APB1ENR_UART4EN,
+ .suc_pin_tx = MCU_GPIO_PORTC(10), /* PC10 */
+ .suc_pin_rx = MCU_GPIO_PORTC(11), /* PC11 */
+ .suc_pin_rts = -1,
+ .suc_pin_cts = -1,
+ .suc_pin_af = GPIO_AF8_UART4,
+ .suc_irqn = UART4_IRQn
+ }
+};
+#endif
+
+static const struct hal_bsp_mem_dump dump_cfg[] = {
+ [0] = {
+ .hbmd_start = &_ram_start,
+ .hbmd_size = RAM_SIZE
+ },
+ [1] = {
+ .hbmd_start = &_ccram_start,
+ .hbmd_size = CCRAM_SIZE
+ }
+};
+
+const struct hal_flash *
+hal_bsp_flash_dev(uint8_t id)
+{
+ /*
+ * Internal flash mapped to id 0.
+ */
+ if (id != 0) {
+ return NULL;
+ }
+ return &stm32f4_flash_dev;
+}
+
+const struct hal_bsp_mem_dump *
+hal_bsp_core_dump(int *area_cnt)
+{
+ *area_cnt = sizeof(dump_cfg) / sizeof(dump_cfg[0]);
+ return dump_cfg;
+}
+
+void
+hal_bsp_init(void)
+{
+ int rc;
+
+ (void)rc;
+
+#if MYNEWT_VAL(UART_0)
+ rc = os_dev_create((struct os_dev *) &hal_uart0, CONSOLE_UART,
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&uart_cfg[0]);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_0)
+ hal_timer_init(0, TIM9);
+#endif
+}
+
+/**
+ * Returns the configured priority for the given interrupt. If no priority
+ * configured, return the priority passed in
+ *
+ * @param irq_num
+ * @param pri
+ *
+ * @return uint32_t
+ */
+uint32_t
+hal_bsp_get_nvic_priority(int irq_num, uint32_t pri)
+{
+ /* Add any interrupt priorities configured by the bsp here */
+ return pri;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/469eabd1/hw/bsp/sensorhub/stm32f4discovery.ld
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/stm32f4discovery.ld b/hw/bsp/sensorhub/stm32f4discovery.ld
deleted file mode 100644
index 3382dcc..0000000
--- a/hw/bsp/sensorhub/stm32f4discovery.ld
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-/* Linker script for STM32F407 when running from flash and using the bootloader */
-
-/* Linker script to configure memory regions. */
-MEMORY
-{
- FLASH (rx) : ORIGIN = 0x08020000, LENGTH = 384K /* First image slot. */
- CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
- RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
-}
-
-/* This linker script is used for images and thus contains an image header */
-_imghdr_size = 0x20;
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/469eabd1/hw/bsp/sensorhub/stm32f4discovery_debug.cmd
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/stm32f4discovery_debug.cmd b/hw/bsp/sensorhub/stm32f4discovery_debug.cmd
deleted file mode 100755
index d6cfc11..0000000
--- a/hw/bsp/sensorhub/stm32f4discovery_debug.cmd
+++ /dev/null
@@ -1,3 +0,0 @@
-@rem Execute a shell with a script of the same name and .sh extension
-
-@bash "%~dp0%~n0.sh"
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/469eabd1/hw/bsp/sensorhub/stm32f4discovery_debug.sh
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/stm32f4discovery_debug.sh b/hw/bsp/sensorhub/stm32f4discovery_debug.sh
deleted file mode 100755
index 14b2a64..0000000
--- a/hw/bsp/sensorhub/stm32f4discovery_debug.sh
+++ /dev/null
@@ -1,39 +0,0 @@
-#!/bin/sh
-# Licensed to the Apache Software Foundation (ASF) under one
-# or more contributor license agreements. See the NOTICE file
-# distributed with this work for additional information
-# regarding copyright ownership. The ASF licenses this file
-# to you under the Apache License, Version 2.0 (the
-# "License"); you may not use this file except in compliance
-# with the License. You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing,
-# software distributed under the License is distributed on an
-# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
-# KIND, either express or implied. See the License for the
-# specific language governing permissions and limitations
-# under the License.
-#
-
-# Called with following variables set:
-# - CORE_PATH is absolute path to @apache-mynewt-core
-# - BSP_PATH is absolute path to hw/bsp/bsp_name
-# - BIN_BASENAME is the path to prefix to target binary,
-# .elf appended to name is the ELF file
-# - FEATURES holds the target features string
-# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
-# - RESET set if target should be reset when attaching
-# - NO_GDB set if we should not start gdb to debug
-#
-. $CORE_PATH/hw/scripts/openocd.sh
-
-FILE_NAME=$BIN_BASENAME.elf
-CFG="-s $BSP_PATH -f $BSP_PATH/f4discovery.cfg"
-#ADG! CFG="-s $BSP_PATH -f /usr/share/openocd/scripts/interface/jlink.cfg -f /home/alan/dev/myproj-2/targets/stm_blinky/openocd.cfg"
-
-# Exit openocd when gdb detaches.
-EXTRA_JTAG_CMD="$EXTRA_JTAG_CMD; stm32f4x.cpu configure -event gdb-detach {if {[stm32f4x.cpu curstate] eq \"halted\"} resume;shutdown}"
-
-openocd_debug
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/469eabd1/hw/bsp/sensorhub/stm32f4discovery_download.cmd
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/stm32f4discovery_download.cmd b/hw/bsp/sensorhub/stm32f4discovery_download.cmd
deleted file mode 100755
index d6cfc11..0000000
--- a/hw/bsp/sensorhub/stm32f4discovery_download.cmd
+++ /dev/null
@@ -1,3 +0,0 @@
-@rem Execute a shell with a script of the same name and .sh extension
-
-@bash "%~dp0%~n0.sh"
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/469eabd1/hw/bsp/sensorhub/stm32f4discovery_download.sh
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/stm32f4discovery_download.sh b/hw/bsp/sensorhub/stm32f4discovery_download.sh
deleted file mode 100755
index 5a3a17d..0000000
--- a/hw/bsp/sensorhub/stm32f4discovery_download.sh
+++ /dev/null
@@ -1,42 +0,0 @@
-#!/bin/sh
-# Licensed to the Apache Software Foundation (ASF) under one
-# or more contributor license agreements. See the NOTICE file
-# distributed with this work for additional information
-# regarding copyright ownership. The ASF licenses this file
-# to you under the Apache License, Version 2.0 (the
-# "License"); you may not use this file except in compliance
-# with the License. You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing,
-# software distributed under the License is distributed on an
-# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
-# KIND, either express or implied. See the License for the
-# specific language governing permissions and limitations
-# under the License.
-#
-
-# Called with following variables set:
-# - CORE_PATH is absolute path to @apache-mynewt-core
-# - BSP_PATH is absolute path to hw/bsp/bsp_name
-# - BIN_BASENAME is the path to prefix to target binary,
-# .elf appended to name is the ELF file
-# - IMAGE_SLOT is the image slot to download to (for non-mfg-image, non-boot)
-# - FEATURES holds the target features string
-# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
-# - MFG_IMAGE is "1" if this is a manufacturing image
-# - FLASH_OFFSET contains the flash offset to download to
-# - BOOT_LOADER is set if downloading a bootloader
-. $CORE_PATH/hw/scripts/openocd.sh
-
-CFG="-s $BSP_PATH -f f4discovery.cfg"
-#ADG! CFG="-s $BSP_PATH -f /usr/share/openocd/scripts/interface/jlink.cfg -f /home/alan/dev/myproj-2/targets/stm_blinky/openocd.cfg"
-
-if [ "$MFG_IMAGE" ]; then
- FLASH_OFFSET=0x08000000
-fi
-
-common_file_to_load
-openocd_load
-openocd_reset_run
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/469eabd1/hw/mcu/stm/stm32f4xx/src/hal_gpio.c
----------------------------------------------------------------------
diff --git a/hw/mcu/stm/stm32f4xx/src/hal_gpio.c b/hw/mcu/stm/stm32f4xx/src/hal_gpio.c
index 44c2eb8..5aac030 100644
--- a/hw/mcu/stm/stm32f4xx/src/hal_gpio.c
+++ b/hw/mcu/stm/stm32f4xx/src/hal_gpio.c
@@ -17,8 +17,8 @@
* under the License.
*/
-#include "hal/hal_gpio.h"
#include "bsp/cmsis_nvic.h"
+#include "hal/hal_gpio.h"
#include "stm32f4xx.h"
#include "stm32f4xx_hal_gpio.h"
#include "stm32f4xx_hal_rcc.h"
@@ -102,13 +102,13 @@ static GPIO_TypeDef * const portmap[HAL_GPIO_NUM_PORTS] =
GPIOH,
#endif
#if defined GPIOI_BASE
- GPIOI
+ GPIOI,
#endif
#if defined GPIOJ_BASE
- GPIOJ
+ GPIOJ,
#endif
#if defined GPIOK_BASE
- GPIOK
+ GPIOK,
#endif
};
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/469eabd1/hw/mcu/stm/stm32f4xx/stm32f427.ld
----------------------------------------------------------------------
diff --git a/hw/mcu/stm/stm32f4xx/stm32f427.ld b/hw/mcu/stm/stm32f4xx/stm32f427.ld
new file mode 100644
index 0000000..7d2887a
--- /dev/null
+++ b/hw/mcu/stm/stm32f4xx/stm32f427.ld
@@ -0,0 +1,203 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapBase
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __coredata_start__
+ * __coredata_end__
+ * __corebss_start__
+ * __corebss_end__
+ * __ecoredata
+ * __ecorebss
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ /* Reserve space at the start of the image for the header. */
+ .imghdr (NOLOAD):
+ {
+ . = . + _imghdr_size;
+ } > FLASH
+
+ .text :
+ {
+ __isr_vector_start = .;
+ KEEP(*(.isr_vector))
+ __isr_vector_end = .;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+
+ __exidx_end = .;
+
+ __etext = .;
+
+ .vector_relocation :
+ {
+ . = ALIGN(4);
+ __vector_tbl_reloc__ = .;
+ . = . + (__isr_vector_end - __isr_vector_start);
+ . = ALIGN(4);
+ } > RAM
+
+ .coredata :
+ {
+ __coredata_start__ = .;
+ *(.data.core)
+ . = ALIGN(4);
+ __coredata_end__ = .;
+ } > CCM AT > FLASH
+
+ __ecoredata = __etext + SIZEOF(.coredata);
+
+ .data :
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM AT > FLASH
+
+ .corebss (NOLOAD):
+ {
+ . = ALIGN(4);
+ __corebss_start__ = .;
+ *(.bss.core)
+ . = ALIGN(4);
+ __corebss_end__ = .;
+ *(.corebss*)
+ *(.bss.core.nz)
+ . = ALIGN(4);
+ __ecorebss = .;
+ } > CCM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ __HeapBase = .;
+ __HeapLimit = ORIGIN(RAM) + LENGTH(RAM);
+
+ _ram_start = ORIGIN(RAM);
+ _ccram_start = ORIGIN(CCM);
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > CCM
+
+ /* Set stack top to end of CCM; stack limit is bottom of stack */
+ __StackTop = ORIGIN(CCM) + LENGTH(CCM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check for CCM overflow */
+ ASSERT(__StackLimit >= __ecorebss, "CCM overflow!")
+}
+
[8/9] incubator-mynewt-core git commit: BSP for 'sensorhub' board,
which is based on the STM32F427IG MCU
Posted by ma...@apache.org.
BSP for 'sensorhub' board, which is based on the STM32F427IG MCU
Project: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/repo
Commit: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/commit/b85fcd3d
Tree: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/tree/b85fcd3d
Diff: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/diff/b85fcd3d
Branch: refs/heads/develop
Commit: b85fcd3d6ee0fd2b2f3290d7750449a9f5192a2e
Parents: 74c0d13
Author: Alan <ag...@gemcore.com>
Authored: Fri Mar 3 17:24:40 2017 -0800
Committer: Alan <ag...@gemcore.com>
Committed: Thu Mar 9 12:07:39 2017 -0800
----------------------------------------------------------------------
hw/bsp/sensorhub/boot-stm32f4discovery.ld | 29 ++
hw/bsp/sensorhub/bsp.yml | 63 +++
hw/bsp/sensorhub/f407.cfg | 82 ++++
hw/bsp/sensorhub/f4discovery.cfg | 22 +
hw/bsp/sensorhub/include/bsp/bsp.h | 72 ++++
hw/bsp/sensorhub/include/bsp/cmsis_nvic.h | 29 ++
.../sensorhub/include/bsp/stm32f4xx_hal_conf.h | 431 +++++++++++++++++++
hw/bsp/sensorhub/pkg.yml | 40 ++
.../src/arch/cortex_m4/startup_STM32F40x.s | 353 +++++++++++++++
hw/bsp/sensorhub/src/hal_bsp.c | 119 +++++
hw/bsp/sensorhub/src/sbrk.c | 50 +++
hw/bsp/sensorhub/src/system_stm32f4xx.c | 275 ++++++++++++
hw/bsp/sensorhub/stm32f4discovery.ld | 31 ++
hw/bsp/sensorhub/stm32f4discovery_debug.cmd | 3 +
hw/bsp/sensorhub/stm32f4discovery_debug.sh | 39 ++
hw/bsp/sensorhub/stm32f4discovery_download.cmd | 3 +
hw/bsp/sensorhub/stm32f4discovery_download.sh | 42 ++
hw/bsp/sensorhub/syscfg.yml | 32 ++
18 files changed, 1715 insertions(+)
----------------------------------------------------------------------
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/b85fcd3d/hw/bsp/sensorhub/boot-stm32f4discovery.ld
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/boot-stm32f4discovery.ld b/hw/bsp/sensorhub/boot-stm32f4discovery.ld
new file mode 100644
index 0000000..342de6a
--- /dev/null
+++ b/hw/bsp/sensorhub/boot-stm32f4discovery.ld
@@ -0,0 +1,29 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 32K
+ CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
+}
+
+/* The bootloader does not contain an image header */
+_imghdr_size = 0x0;
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/b85fcd3d/hw/bsp/sensorhub/bsp.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/bsp.yml b/hw/bsp/sensorhub/bsp.yml
new file mode 100644
index 0000000..658cb21
--- /dev/null
+++ b/hw/bsp/sensorhub/bsp.yml
@@ -0,0 +1,63 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+bsp.arch: cortex_m4
+bsp.compiler: compiler/arm-none-eabi-m4
+bsp.linkerscript:
+ - "hw/bsp/stm32f4discovery/stm32f4discovery.ld"
+ - "hw/mcu/stm/stm32f4xx/stm32f407.ld"
+bsp.linkerscript.BOOT_LOADER.OVERWRITE:
+ - "hw/bsp/stm32f4discovery/boot-stm32f4discovery.ld"
+ - "hw/mcu/stm/stm32f4xx/stm32f407.ld"
+bsp.downloadscript: "hw/bsp/stm32f4discovery/stm32f4discovery_download.sh"
+bsp.debugscript: "hw/bsp/stm32f4discovery/stm32f4discovery_debug.sh"
+bsp.downloadscript.WINDOWS.OVERRIDE: "hw/bsp/stm32f4discovery/stm32f4discovery_download.cmd"
+bsp.debugscript.WINDOWS.OVERRIDE: "hw/bsp/stm32f4discovery/stm32f4discovery_debug.cmd"
+
+bsp.flash_map:
+ areas:
+ # System areas.
+ FLASH_AREA_BOOTLOADER:
+ device: 0
+ offset: 0x08000000
+ size: 16kB
+ FLASH_AREA_IMAGE_0:
+ device: 0
+ offset: 0x08020000
+ size: 384kB
+ FLASH_AREA_IMAGE_1:
+ device: 0
+ offset: 0x08080000
+ size: 384kB
+ FLASH_AREA_IMAGE_SCRATCH:
+ device: 0
+ offset: 0x080e0000
+ size: 128kB
+
+ # User areas.
+ FLASH_AREA_REBOOT_LOG:
+ user_id: 0
+ device: 0
+ offset: 0x08004000
+ size: 16kB
+ FLASH_AREA_NFFS:
+ user_id: 1
+ device: 0
+ offset: 0x08008000
+ size: 32kB
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/b85fcd3d/hw/bsp/sensorhub/f407.cfg
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/f407.cfg b/hw/bsp/sensorhub/f407.cfg
new file mode 100644
index 0000000..7c46d8b
--- /dev/null
+++ b/hw/bsp/sensorhub/f407.cfg
@@ -0,0 +1,82 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# script for stm32f4x family
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME stm32f4x
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 64kB
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ set _WORKAREASIZE 0x10000
+}
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+#
+# Since we may be running of an RC oscilator, we crank down the speed a
+# bit more to be on the safe side. Perhaps superstition, but if are
+# running off a crystal, we can run closer to the limit. Note
+# that there can be a pretty wide band where things are more or less stable.
+adapter_khz 1000
+
+adapter_nsrst_delay 100
+jtag_ntrst_delay 100
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # See STM Document RM0090
+ # Section 32.6.2 - corresponds to Cortex-M4 r0p1
+ set _CPUTAPID 0x4ba00477
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID] } {
+ set _BSTAPID $BSTAPID
+} else {
+ # See STM Document RM0090
+ # Section 32.6.3
+ set _BSTAPID 0x06413041
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
+
+# if srst is not fitted use SYSRESETREQ to
+# perform a soft reset
+cortex_m3 reset_config sysresetreq
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/b85fcd3d/hw/bsp/sensorhub/f4discovery.cfg
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/f4discovery.cfg b/hw/bsp/sensorhub/f4discovery.cfg
new file mode 100644
index 0000000..694ab8d
--- /dev/null
+++ b/hw/bsp/sensorhub/f4discovery.cfg
@@ -0,0 +1,22 @@
+#!/bin/sh
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+
+# New version of St-link
+source [find interface/stlink-v2-1.cfg]
+transport select hla_swd
+source [find target/stm32f4x.cfg]
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/b85fcd3d/hw/bsp/sensorhub/include/bsp/bsp.h
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/include/bsp/bsp.h b/hw/bsp/sensorhub/include/bsp/bsp.h
new file mode 100644
index 0000000..da9ffc4
--- /dev/null
+++ b/hw/bsp/sensorhub/include/bsp/bsp.h
@@ -0,0 +1,72 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#ifndef H_BSP_H
+#define H_BSP_H
+
+#include <inttypes.h>
+#include <mcu/mcu.h>
+#include <syscfg/syscfg.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Define special stackos sections */
+#define sec_data_core __attribute__((section(".data.core")))
+#define sec_bss_core __attribute__((section(".bss.core")))
+#define sec_bss_nz_core __attribute__((section(".bss.core.nz")))
+
+/* More convenient section placement macros. */
+#define bssnz_t sec_bss_nz_core
+
+extern uint8_t _ram_start;
+extern uint8_t _ccram_start;
+
+/* System SRAM including CCM (core coupled memory) data RAM. */
+#define RAM_SIZE (256 * 1024)
+#define CCRAM_SIZE (64 * 1024)
+
+/* 4KB of backup SRAM, accessible only from the CPU.
+ * Protected and retained in Standby or VBAT mode.
+ */
+#define BACKUPRAM_SIZE (4 * 1024)
+
+/* LED pins */
+#define LED_BLINK_PIN MCU_GPIO_PORTD(12)
+
+/* UART */
+#define UART_CNT 1
+#define CONSOLE_UART "uart0"
+
+#if MYNEWT_VAL(BOOT_SERIAL)
+#define BOOT_SERIAL_DETECT_PIN 16 /* on Sensor Hub board BOOT0 is dedicated! */
+#define BOOT_SERIAL_DETECT_PIN_CFG HAL_GPIO_PULL_UP
+#define BOOT_SERIAL_DETECT_PIN_VAL 0
+
+#define BOOT_SERIAL_REPORT_PIN LED_BLINK_PIN
+#define BOOT_SERIAL_REPORT_FREQ (MYNEWT_VAL(OS_CPUTIME_FREQ) / 4)
+#endif
+
+#define NFFS_AREA_MAX (8)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* H_BSP_H */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/b85fcd3d/hw/bsp/sensorhub/include/bsp/cmsis_nvic.h
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/include/bsp/cmsis_nvic.h b/hw/bsp/sensorhub/include/bsp/cmsis_nvic.h
new file mode 100644
index 0000000..d0c8b44
--- /dev/null
+++ b/hw/bsp/sensorhub/include/bsp/cmsis_nvic.h
@@ -0,0 +1,29 @@
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include <stdint.h>
+
+#define NVIC_NUM_VECTORS (16 + 81) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "stm32f4xx.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_Relocate(void);
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/b85fcd3d/hw/bsp/sensorhub/include/bsp/stm32f4xx_hal_conf.h
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/include/bsp/stm32f4xx_hal_conf.h b/hw/bsp/sensorhub/include/bsp/stm32f4xx_hal_conf.h
new file mode 100644
index 0000000..d459b12
--- /dev/null
+++ b/hw/bsp/sensorhub/include/bsp/stm32f4xx_hal_conf.h
@@ -0,0 +1,431 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_conf.h
+ * @author MCD Application Team
+ * @version V1.2.4
+ * @date 06-May-2016
+ * @brief HAL configuration file
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+#if 0
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DCMI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+/* #define HAL_DMA2D_MODULE_ENABLED */
+#define HAL_ETH_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_PCCARD_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+/* #define HAL_SDRAM_MODULE_ENABLED */
+#define HAL_HASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_LTDC_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+/* #define HAL_SAI_MODULE_ENABLED */
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
+#else
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#endif
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE ((uint32_t)32000)
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined (LSE_STARTUP_TIMEOUT)
+ #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief External clock source for I2S peripheral
+ * This value is used by the I2S HAL module to compute the I2S clock source
+ * frequency, this source is inserted directly through I2S_CKIN pad.
+ */
+#if !defined (EXTERNAL_CLOCK_VALUE)
+ #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
+#define USE_RTOS 0
+#define PREFETCH_ENABLE 0 /* The prefetch will be enabled in SystemClock_Config(), depending on the used
+ STM32F405/415/07/417 device: RevA (prefetch must be off) or RevZ (prefetch can be on/off) */
+#define INSTRUCTION_CACHE_ENABLE 1
+#define DATA_CACHE_ENABLE 1
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1 */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0 2
+#define MAC_ADDR1 0
+#define MAC_ADDR2 0
+#define MAC_ADDR3 0
+#define MAC_ADDR4 0
+#define MAC_ADDR5 0
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
+#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
+#define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
+#define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848 PHY Address*/
+#define DP83848_PHY_ADDRESS 0x01
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY ((uint32_t)0x000000FF)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF)
+
+#define PHY_READ_TO ((uint32_t)0x0000FFFF)
+#define PHY_WRITE_TO ((uint32_t)0x0000FFFF)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */
+#define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */
+
+#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
+#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
+#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
+#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
+#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
+#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
+#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
+
+#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
+#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
+#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
+
+/* Section 4: Extended PHY Registers */
+
+#define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */
+#define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */
+#define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */
+
+#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
+#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
+#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
+
+#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
+#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
+
+#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020U) /*!< Enable Interrupt on change of link status */
+#define PHY_LINK_INTERRUPT ((uint16_t)0x2000U) /*!< PHY link status interrupt mask */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+* Activated: CRC code is present inside driver
+* Deactivated: CRC code cleaned from driver
+*/
+
+#define USE_SPI_CRC 1U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+ #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+ #include "stm32f4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+ #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+ #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+ #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+ #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/b85fcd3d/hw/bsp/sensorhub/pkg.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/pkg.yml b/hw/bsp/sensorhub/pkg.yml
new file mode 100644
index 0000000..d329ea4
--- /dev/null
+++ b/hw/bsp/sensorhub/pkg.yml
@@ -0,0 +1,40 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: hw/bsp/sensorhub
+pkg.type: bsp
+pkg.description: BSP definition for the stm32f427 based sensor hub board.
+pkg.author: "Apache Mynewt <de...@mynewt.incubator.apache.org>"
+pkg.homepage: "http://mynewt.apache.org/"
+pkg.keywords:
+ - stm32
+ - stm32f4
+ - discovery
+
+pkg.cflags: -DSTM32F407xx
+
+pkg.cflags.HARDFLOAT:
+ - -mfloat-abi=hard -mfpu=fpv4-sp-d16
+
+pkg.deps:
+ - hw/mcu/stm/stm32f4xx
+ - libc/baselibc
+
+pkg.deps.UART_0:
+ - hw/drivers/uart/uart_hal
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/b85fcd3d/hw/bsp/sensorhub/src/arch/cortex_m4/startup_STM32F40x.s
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/src/arch/cortex_m4/startup_STM32F40x.s b/hw/bsp/sensorhub/src/arch/cortex_m4/startup_STM32F40x.s
new file mode 100644
index 0000000..e84feac
--- /dev/null
+++ b/hw/bsp/sensorhub/src/arch/cortex_m4/startup_STM32F40x.s
@@ -0,0 +1,353 @@
+/* File: startup_STM32F40x.S
+ * Purpose: startup file for Cortex-M4 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V1.4
+ * Date: 09 July 2012
+ *
+ * Copyright (c) 2011, 2012, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of the ARM Limited nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ .syntax unified
+ .arch armv7-m
+
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0xc00
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long WWDG_IRQHandler /* Window WatchDog */
+ .long PVD_IRQHandler /* PVD through EXTI Line detection */
+ .long TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .long RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .long FLASH_IRQHandler /* FLASH */
+ .long RCC_IRQHandler /* RCC */
+ .long EXTI0_IRQHandler /* EXTI Line0 */
+ .long EXTI1_IRQHandler /* EXTI Line1 */
+ .long EXTI2_IRQHandler /* EXTI Line2 */
+ .long EXTI3_IRQHandler /* EXTI Line3 */
+ .long EXTI4_IRQHandler /* EXTI Line4 */
+ .long DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .long DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .long DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .long DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .long DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .long DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .long DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .long ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .long CAN1_TX_IRQHandler /* CAN1 TX */
+ .long CAN1_RX0_IRQHandler /* CAN1 RX0 */
+ .long CAN1_RX1_IRQHandler /* CAN1 RX1 */
+ .long CAN1_SCE_IRQHandler /* CAN1 SCE */
+ .long EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .long TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
+ .long TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
+ .long TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
+ .long TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .long TIM2_IRQHandler /* TIM2 */
+ .long TIM3_IRQHandler /* TIM3 */
+ .long TIM4_IRQHandler /* TIM4 */
+ .long I2C1_EV_IRQHandler /* I2C1 Event */
+ .long I2C1_ER_IRQHandler /* I2C1 Error */
+ .long I2C2_EV_IRQHandler /* I2C2 Event */
+ .long I2C2_ER_IRQHandler /* I2C2 Error */
+ .long SPI1_IRQHandler /* SPI1 */
+ .long SPI2_IRQHandler /* SPI2 */
+ .long USART1_IRQHandler /* USART1 */
+ .long USART2_IRQHandler /* USART2 */
+ .long USART3_IRQHandler /* USART3 */
+ .long EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .long RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .long OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
+ .long TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .long TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .long TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .long TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .long DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .long FSMC_IRQHandler /* FSMC */
+ .long SDIO_IRQHandler /* SDIO */
+ .long TIM5_IRQHandler /* TIM5 */
+ .long SPI3_IRQHandler /* SPI3 */
+ .long UART4_IRQHandler /* UART4 */
+ .long UART5_IRQHandler /* UART5 */
+ .long TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .long TIM7_IRQHandler /* TIM7 */
+ .long DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .long DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .long DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .long DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .long DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .long ETH_IRQHandler /* Ethernet */
+ .long ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
+ .long CAN2_TX_IRQHandler /* CAN2 TX */
+ .long CAN2_RX0_IRQHandler /* CAN2 RX0 */
+ .long CAN2_RX1_IRQHandler /* CAN2 RX1 */
+ .long CAN2_SCE_IRQHandler /* CAN2 SCE */
+ .long OTG_FS_IRQHandler /* USB OTG FS */
+ .long DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .long DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .long DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .long USART6_IRQHandler /* USART6 */
+ .long I2C3_EV_IRQHandler /* I2C3 event */
+ .long I2C3_ER_IRQHandler /* I2C3 error */
+ .long OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .long OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .long OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .long OTG_HS_IRQHandler /* USB OTG HS */
+ .long DCMI_IRQHandler /* DCMI */
+ .long CRYP_IRQHandler /* CRYP crypto */
+ .long HASH_RNG_IRQHandler /* Hash and Rng */
+ .long FPU_IRQHandler /* FPU */
+
+ .size __isr_vector, . - __isr_vector
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Copy data core section from flash to RAM */
+ ldr r1, =__etext
+ ldr r2, =__coredata_start__
+ ldr r3, =__coredata_end__
+
+.LC0:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .LC0
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+ ldr r1, =__ecoredata
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.LC1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .LC1
+
+/* Set the bss core section to zero */
+ mov r0, #0
+ ldr r1, =__corebss_start__
+ ldr r2, =__corebss_end__
+
+.LC2:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .LC2
+
+ /* Set the other bss section to zero as well*/
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+.LC3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .LC3
+
+/* Call system initialization and startup routines */
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler MemManage_Handler
+ def_default_handler BusFault_Handler
+ def_default_handler UsageFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler DebugMon_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_default_handler WWDG_IRQHandler
+ def_irq_default_handler PVD_IRQHandler
+ def_irq_default_handler TAMP_STAMP_IRQHandler
+ def_irq_default_handler RTC_WKUP_IRQHandler
+ def_irq_default_handler FLASH_IRQHandler
+ def_irq_default_handler RCC_IRQHandler
+ def_irq_default_handler EXTI0_IRQHandler
+ def_irq_default_handler EXTI1_IRQHandler
+ def_irq_default_handler EXTI2_IRQHandler
+ def_irq_default_handler EXTI3_IRQHandler
+ def_irq_default_handler EXTI4_IRQHandler
+ def_irq_default_handler DMA1_Stream0_IRQHandler
+ def_irq_default_handler DMA1_Stream1_IRQHandler
+ def_irq_default_handler DMA1_Stream2_IRQHandler
+ def_irq_default_handler DMA1_Stream3_IRQHandler
+ def_irq_default_handler DMA1_Stream4_IRQHandler
+ def_irq_default_handler DMA1_Stream5_IRQHandler
+ def_irq_default_handler DMA1_Stream6_IRQHandler
+ def_irq_default_handler ADC_IRQHandler
+ def_irq_default_handler CAN1_TX_IRQHandler
+ def_irq_default_handler CAN1_RX0_IRQHandler
+ def_irq_default_handler CAN1_RX1_IRQHandler
+ def_irq_default_handler CAN1_SCE_IRQHandler
+ def_irq_default_handler EXTI9_5_IRQHandler
+ def_irq_default_handler TIM1_BRK_TIM9_IRQHandler
+ def_irq_default_handler TIM1_UP_TIM10_IRQHandler
+ def_irq_default_handler TIM1_TRG_COM_TIM11_IRQHandler
+ def_irq_default_handler TIM1_CC_IRQHandler
+ def_irq_default_handler TIM2_IRQHandler
+ def_irq_default_handler TIM3_IRQHandler
+ def_irq_default_handler TIM4_IRQHandler
+ def_irq_default_handler I2C1_EV_IRQHandler
+ def_irq_default_handler I2C1_ER_IRQHandler
+ def_irq_default_handler I2C2_EV_IRQHandler
+ def_irq_default_handler I2C2_ER_IRQHandler
+ def_irq_default_handler SPI1_IRQHandler
+ def_irq_default_handler SPI2_IRQHandler
+ def_irq_default_handler USART1_IRQHandler
+ def_irq_default_handler USART2_IRQHandler
+ def_irq_default_handler USART3_IRQHandler
+ def_irq_default_handler EXTI15_10_IRQHandler
+ def_irq_default_handler RTC_Alarm_IRQHandler
+ def_irq_default_handler OTG_FS_WKUP_IRQHandler
+ def_irq_default_handler TIM8_BRK_TIM12_IRQHandler
+ def_irq_default_handler TIM8_UP_TIM13_IRQHandler
+ def_irq_default_handler TIM8_TRG_COM_TIM14_IRQHandler
+ def_irq_default_handler TIM8_CC_IRQHandler
+ def_irq_default_handler DMA1_Stream7_IRQHandler
+ def_irq_default_handler FSMC_IRQHandler
+ def_irq_default_handler SDIO_IRQHandler
+ def_irq_default_handler TIM5_IRQHandler
+ def_irq_default_handler SPI3_IRQHandler
+ def_irq_default_handler UART4_IRQHandler
+ def_irq_default_handler UART5_IRQHandler
+ def_irq_default_handler TIM6_DAC_IRQHandler
+ def_irq_default_handler TIM7_IRQHandler
+ def_irq_default_handler DMA2_Stream0_IRQHandler
+ def_irq_default_handler DMA2_Stream1_IRQHandler
+ def_irq_default_handler DMA2_Stream2_IRQHandler
+ def_irq_default_handler DMA2_Stream3_IRQHandler
+ def_irq_default_handler DMA2_Stream4_IRQHandler
+ def_irq_default_handler ETH_IRQHandler
+ def_irq_default_handler ETH_WKUP_IRQHandler
+ def_irq_default_handler CAN2_TX_IRQHandler
+ def_irq_default_handler CAN2_RX0_IRQHandler
+ def_irq_default_handler CAN2_RX1_IRQHandler
+ def_irq_default_handler CAN2_SCE_IRQHandler
+ def_irq_default_handler OTG_FS_IRQHandler
+ def_irq_default_handler DMA2_Stream5_IRQHandler
+ def_irq_default_handler DMA2_Stream6_IRQHandler
+ def_irq_default_handler DMA2_Stream7_IRQHandler
+ def_irq_default_handler USART6_IRQHandler
+ def_irq_default_handler I2C3_EV_IRQHandler
+ def_irq_default_handler I2C3_ER_IRQHandler
+ def_irq_default_handler OTG_HS_EP1_OUT_IRQHandler
+ def_irq_default_handler OTG_HS_EP1_IN_IRQHandler
+ def_irq_default_handler OTG_HS_WKUP_IRQHandler
+ def_irq_default_handler OTG_HS_IRQHandler
+ def_irq_default_handler DCMI_IRQHandler
+ def_irq_default_handler CRYP_IRQHandler
+ def_irq_default_handler HASH_RNG_IRQHandler
+ def_irq_default_handler FPU_IRQHandler
+ def_irq_default_handler DEF_IRQHandler
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/b85fcd3d/hw/bsp/sensorhub/src/hal_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/src/hal_bsp.c b/hw/bsp/sensorhub/src/hal_bsp.c
new file mode 100644
index 0000000..0f2cbfe
--- /dev/null
+++ b/hw/bsp/sensorhub/src/hal_bsp.c
@@ -0,0 +1,119 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include <assert.h>
+
+#include <syscfg/syscfg.h>
+
+#include <os/os_dev.h>
+#if MYNEWT_VAL(UART_0)
+#include <uart/uart.h>
+#include <uart_hal/uart_hal.h>
+#endif
+
+#include <hal/hal_bsp.h>
+#include <hal/hal_gpio.h>
+#include <hal/hal_flash_int.h>
+#include <hal/hal_timer.h>
+
+#include <stm32f407xx.h> //ADG! Should be using stm32f427xx.h
+#include <stm32f4xx_hal_gpio_ex.h>
+#include <mcu/stm32f4_bsp.h>
+
+#include "bsp/bsp.h"
+
+#if MYNEWT_VAL(UART_0)
+static struct uart_dev hal_uart0;
+
+static const struct stm32f4_uart_cfg uart_cfg[UART_CNT] = {
+ [0] = {
+ .suc_uart = UART4,
+ .suc_rcc_reg = &RCC->APB2ENR,
+ .suc_rcc_dev = RCC_APB1ENR_UART4EN,
+ .suc_pin_tx = MCU_GPIO_PORTC(10), /* PC10 */
+ .suc_pin_rx = MCU_GPIO_PORTC(11), /* PC11 */
+ .suc_pin_rts = -1,
+ .suc_pin_cts = -1,
+ .suc_pin_af = GPIO_AF8_UART4,
+ .suc_irqn = UART4_IRQn
+ }
+};
+#endif
+
+static const struct hal_bsp_mem_dump dump_cfg[] = {
+ [0] = {
+ .hbmd_start = &_ram_start,
+ .hbmd_size = RAM_SIZE
+ },
+ [1] = {
+ .hbmd_start = &_ccram_start,
+ .hbmd_size = CCRAM_SIZE
+ }
+};
+
+const struct hal_flash *
+hal_bsp_flash_dev(uint8_t id)
+{
+ /*
+ * Internal flash mapped to id 0.
+ */
+ if (id != 0) {
+ return NULL;
+ }
+ return &stm32f4_flash_dev;
+}
+
+const struct hal_bsp_mem_dump *
+hal_bsp_core_dump(int *area_cnt)
+{
+ *area_cnt = sizeof(dump_cfg) / sizeof(dump_cfg[0]);
+ return dump_cfg;
+}
+
+void
+hal_bsp_init(void)
+{
+ int rc;
+
+ (void)rc;
+
+#if MYNEWT_VAL(UART_0)
+ rc = os_dev_create((struct os_dev *) &hal_uart0, CONSOLE_UART,
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&uart_cfg[0]);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_0)
+ hal_timer_init(0, TIM9);
+#endif
+}
+
+/**
+ * Returns the configured priority for the given interrupt. If no priority
+ * configured, return the priority passed in
+ *
+ * @param irq_num
+ * @param pri
+ *
+ * @return uint32_t
+ */
+uint32_t
+hal_bsp_get_nvic_priority(int irq_num, uint32_t pri)
+{
+ /* Add any interrupt priorities configured by the bsp here */
+ return pri;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/b85fcd3d/hw/bsp/sensorhub/src/sbrk.c
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/src/sbrk.c b/hw/bsp/sensorhub/src/sbrk.c
new file mode 100644
index 0000000..34edf72
--- /dev/null
+++ b/hw/bsp/sensorhub/src/sbrk.c
@@ -0,0 +1,50 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+extern char __HeapBase;
+extern char __HeapLimit;
+
+void *
+_sbrk(int incr)
+{
+ static char *brk = &__HeapBase;
+
+ void *prev_brk;
+
+ if (incr < 0) {
+ /* Returning memory to the heap. */
+ incr = -incr;
+ if (brk - incr < &__HeapBase) {
+ prev_brk = (void *)-1;
+ } else {
+ prev_brk = brk;
+ brk -= incr;
+ }
+ } else {
+ /* Allocating memory from the heap. */
+ if (&__HeapLimit - brk >= incr) {
+ prev_brk = brk;
+ brk += incr;
+ } else {
+ prev_brk = (void *)-1;
+ }
+ }
+
+ return prev_brk;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/b85fcd3d/hw/bsp/sensorhub/src/system_stm32f4xx.c
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/src/system_stm32f4xx.c b/hw/bsp/sensorhub/src/system_stm32f4xx.c
new file mode 100644
index 0000000..8d39d6e
--- /dev/null
+++ b/hw/bsp/sensorhub/src/system_stm32f4xx.c
@@ -0,0 +1,275 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.c
+ * @author MCD Application Team
+ * @version V1.2.4
+ * @date 06-May-2016
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+ *
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f4xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32f4xx.h"
+#include "bsp/cmsis_nvic.h"
+
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Defines
+ * @{
+ */
+
+/************************* Miscellaneous Configuration ************************/
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+/******************************************************************************/
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Variables
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+ uint32_t SystemCoreClock = 16000000;
+ __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+ #endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+ /* Relocate the vector table */
+ NVIC_Relocate();
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+ * 16 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
+ * depends on the application requirements), user has to ensure that HSE_VALUE
+ * is same as the real frequency of the crystal used. Otherwise, this function
+ * may have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate(void)
+{
+ uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock source */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock source */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x08: /* PLL used as system clock source */
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+ SYSCLK = PLL_VCO / PLL_P
+ */
+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+
+ if (pllsource != 0)
+ {
+ /* HSE used as PLL clock source */
+ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ }
+ else
+ {
+ /* HSI used as PLL clock source */
+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ }
+
+ pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+ SystemCoreClock = pllvco/pllp;
+ break;
+ default:
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+ /* Compute HCLK frequency --------------------------------------------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/b85fcd3d/hw/bsp/sensorhub/stm32f4discovery.ld
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/stm32f4discovery.ld b/hw/bsp/sensorhub/stm32f4discovery.ld
new file mode 100644
index 0000000..3382dcc
--- /dev/null
+++ b/hw/bsp/sensorhub/stm32f4discovery.ld
@@ -0,0 +1,31 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/* Linker script for STM32F407 when running from flash and using the bootloader */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08020000, LENGTH = 384K /* First image slot. */
+ CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
+}
+
+/* This linker script is used for images and thus contains an image header */
+_imghdr_size = 0x20;
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/b85fcd3d/hw/bsp/sensorhub/stm32f4discovery_debug.cmd
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/stm32f4discovery_debug.cmd b/hw/bsp/sensorhub/stm32f4discovery_debug.cmd
new file mode 100755
index 0000000..d6cfc11
--- /dev/null
+++ b/hw/bsp/sensorhub/stm32f4discovery_debug.cmd
@@ -0,0 +1,3 @@
+@rem Execute a shell with a script of the same name and .sh extension
+
+@bash "%~dp0%~n0.sh"
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/b85fcd3d/hw/bsp/sensorhub/stm32f4discovery_debug.sh
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/stm32f4discovery_debug.sh b/hw/bsp/sensorhub/stm32f4discovery_debug.sh
new file mode 100755
index 0000000..14b2a64
--- /dev/null
+++ b/hw/bsp/sensorhub/stm32f4discovery_debug.sh
@@ -0,0 +1,39 @@
+#!/bin/sh
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Called with following variables set:
+# - CORE_PATH is absolute path to @apache-mynewt-core
+# - BSP_PATH is absolute path to hw/bsp/bsp_name
+# - BIN_BASENAME is the path to prefix to target binary,
+# .elf appended to name is the ELF file
+# - FEATURES holds the target features string
+# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+# - RESET set if target should be reset when attaching
+# - NO_GDB set if we should not start gdb to debug
+#
+. $CORE_PATH/hw/scripts/openocd.sh
+
+FILE_NAME=$BIN_BASENAME.elf
+CFG="-s $BSP_PATH -f $BSP_PATH/f4discovery.cfg"
+#ADG! CFG="-s $BSP_PATH -f /usr/share/openocd/scripts/interface/jlink.cfg -f /home/alan/dev/myproj-2/targets/stm_blinky/openocd.cfg"
+
+# Exit openocd when gdb detaches.
+EXTRA_JTAG_CMD="$EXTRA_JTAG_CMD; stm32f4x.cpu configure -event gdb-detach {if {[stm32f4x.cpu curstate] eq \"halted\"} resume;shutdown}"
+
+openocd_debug
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/b85fcd3d/hw/bsp/sensorhub/stm32f4discovery_download.cmd
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/stm32f4discovery_download.cmd b/hw/bsp/sensorhub/stm32f4discovery_download.cmd
new file mode 100755
index 0000000..d6cfc11
--- /dev/null
+++ b/hw/bsp/sensorhub/stm32f4discovery_download.cmd
@@ -0,0 +1,3 @@
+@rem Execute a shell with a script of the same name and .sh extension
+
+@bash "%~dp0%~n0.sh"
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/b85fcd3d/hw/bsp/sensorhub/stm32f4discovery_download.sh
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/stm32f4discovery_download.sh b/hw/bsp/sensorhub/stm32f4discovery_download.sh
new file mode 100755
index 0000000..5a3a17d
--- /dev/null
+++ b/hw/bsp/sensorhub/stm32f4discovery_download.sh
@@ -0,0 +1,42 @@
+#!/bin/sh
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Called with following variables set:
+# - CORE_PATH is absolute path to @apache-mynewt-core
+# - BSP_PATH is absolute path to hw/bsp/bsp_name
+# - BIN_BASENAME is the path to prefix to target binary,
+# .elf appended to name is the ELF file
+# - IMAGE_SLOT is the image slot to download to (for non-mfg-image, non-boot)
+# - FEATURES holds the target features string
+# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+# - MFG_IMAGE is "1" if this is a manufacturing image
+# - FLASH_OFFSET contains the flash offset to download to
+# - BOOT_LOADER is set if downloading a bootloader
+. $CORE_PATH/hw/scripts/openocd.sh
+
+CFG="-s $BSP_PATH -f f4discovery.cfg"
+#ADG! CFG="-s $BSP_PATH -f /usr/share/openocd/scripts/interface/jlink.cfg -f /home/alan/dev/myproj-2/targets/stm_blinky/openocd.cfg"
+
+if [ "$MFG_IMAGE" ]; then
+ FLASH_OFFSET=0x08000000
+fi
+
+common_file_to_load
+openocd_load
+openocd_reset_run
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/b85fcd3d/hw/bsp/sensorhub/syscfg.yml
----------------------------------------------------------------------
diff --git a/hw/bsp/sensorhub/syscfg.yml b/hw/bsp/sensorhub/syscfg.yml
new file mode 100644
index 0000000..5df91a7
--- /dev/null
+++ b/hw/bsp/sensorhub/syscfg.yml
@@ -0,0 +1,32 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+syscfg.defs:
+ UART_0:
+ description: 'UART 0'
+ value: 1
+ TIMER_0:
+ description: 'Timer 0'
+ value: 0
+
+syscfg.vals:
+ REBOOT_LOG_FLASH_AREA: FLASH_AREA_REBOOT_LOG
+ CONFIG_FCB_FLASH_AREA: FLASH_AREA_NFFS
+ NFFS_FLASH_AREA: FLASH_AREA_NFFS
+ COREDUMP_FLASH_AREA: FLASH_AREA_IMAGE_1
[9/9] incubator-mynewt-core git commit: This closes #201.
Posted by ma...@apache.org.
This closes #201.
Merge branch 'adgbranch' of https://github.com/gemcore/incubator-mynewt-core into develop
Project: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/repo
Commit: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/commit/0759b123
Tree: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/tree/0759b123
Diff: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/diff/0759b123
Branch: refs/heads/develop
Commit: 0759b1237b47d010453cf1b3cf796d5ae1ae4f29
Parents: 021f579 873f6bb
Author: Marko Kiiskila <ma...@runtime.io>
Authored: Fri Mar 10 10:30:14 2017 -0800
Committer: Marko Kiiskila <ma...@runtime.io>
Committed: Fri Mar 10 10:30:14 2017 -0800
----------------------------------------------------------------------
apps/boot/src/boot.c | 2 +-
diff.txt | 330 ++++++++++++++
hw/bsp/nina-b1/boot-nrf52xxaa.ld | 25 ++
hw/bsp/nina-b1/bsp.yml | 62 +++
hw/bsp/nina-b1/include/bsp/boards.h | 19 +
hw/bsp/nina-b1/include/bsp/bsp.h | 65 +++
hw/bsp/nina-b1/include/bsp/cmsis_nvic.h | 29 ++
hw/bsp/nina-b1/nrf52dk_debug.sh | 46 ++
hw/bsp/nina-b1/nrf52dk_download.sh | 40 ++
hw/bsp/nina-b1/nrf52dk_no_boot.ld | 191 ++++++++
hw/bsp/nina-b1/nrf52xxaa.ld | 25 ++
hw/bsp/nina-b1/pkg.yml | 92 ++++
hw/bsp/nina-b1/split-nrf52dk.ld | 208 +++++++++
.../src/arch/cortex_m4/gcc_startup_nrf52.s | 299 +++++++++++++
.../arch/cortex_m4/gcc_startup_nrf52_split.s | 163 +++++++
hw/bsp/nina-b1/src/hal_bsp.c | 217 ++++++++++
hw/bsp/nina-b1/src/sbrk.c | 59 +++
hw/bsp/nina-b1/syscfg.yml | 111 +++++
hw/bsp/sensorhub/boot-sensorhub.ld | 31 ++
hw/bsp/sensorhub/bsp.yml | 63 +++
hw/bsp/sensorhub/f407.cfg | 82 ++++
hw/bsp/sensorhub/include/bsp/bsp.h | 72 ++++
hw/bsp/sensorhub/include/bsp/cmsis_nvic.h | 29 ++
.../sensorhub/include/bsp/stm32f4xx_hal_conf.h | 431 +++++++++++++++++++
hw/bsp/sensorhub/pkg.yml | 40 ++
hw/bsp/sensorhub/sensorhub.cfg | 22 +
hw/bsp/sensorhub/sensorhub.ld | 31 ++
hw/bsp/sensorhub/sensorhub_debug.cmd | 3 +
hw/bsp/sensorhub/sensorhub_debug.sh | 39 ++
hw/bsp/sensorhub/sensorhub_download.cmd | 3 +
hw/bsp/sensorhub/sensorhub_download.sh | 42 ++
.../src/arch/cortex_m4/startup_STM32F427xx.s | 369 ++++++++++++++++
hw/bsp/sensorhub/src/hal_bsp.c | 114 +++++
hw/bsp/sensorhub/src/sbrk.c | 50 +++
hw/bsp/sensorhub/src/system_stm32f4xx.c | 275 ++++++++++++
hw/bsp/sensorhub/syscfg.yml | 32 ++
hw/mcu/stm/stm32f4xx/src/hal_gpio.c | 2 +-
hw/mcu/stm/stm32f4xx/stm32f427.ld | 203 +++++++++
repository.yml | 12 +-
39 files changed, 3923 insertions(+), 5 deletions(-)
----------------------------------------------------------------------