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Posted to commits@nuttx.apache.org by xi...@apache.org on 2022/04/25 07:44:12 UTC
[incubator-nuttx] branch master updated: RISC-V: Fix system crash when FPU is in use
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new 2580520828 RISC-V: Fix system crash when FPU is in use
2580520828 is described below
commit 25805208283a485da2e113cb0b83c365b6770694
Author: Ville Juven <vi...@unikie.com>
AuthorDate: Fri Apr 22 14:19:10 2022 +0300
RISC-V: Fix system crash when FPU is in use
FPU registers need to be written prior to updating CSR_STATUS
---
arch/risc-v/src/common/riscv_exception_common.S | 3 ++-
arch/risc-v/src/common/supervisor/riscv_dispatch_syscall.S | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/risc-v/src/common/riscv_exception_common.S b/arch/risc-v/src/common/riscv_exception_common.S
index ecf2a1b684..0bf0f74f09 100644
--- a/arch/risc-v/src/common/riscv_exception_common.S
+++ b/arch/risc-v/src/common/riscv_exception_common.S
@@ -127,6 +127,8 @@ exception_common:
mv sp, a0
+ riscv_loadfpu sp
+
REGLOAD s0, REG_EPC(sp) /* restore sepc */
csrw CSR_EPC, s0
@@ -134,7 +136,6 @@ exception_common:
csrw CSR_STATUS, s0
load_ctx sp
- riscv_loadfpu sp
REGLOAD sp, REG_SP(sp) /* restore original sp */
diff --git a/arch/risc-v/src/common/supervisor/riscv_dispatch_syscall.S b/arch/risc-v/src/common/supervisor/riscv_dispatch_syscall.S
index 4629d16dfb..1bf11633c0 100644
--- a/arch/risc-v/src/common/supervisor/riscv_dispatch_syscall.S
+++ b/arch/risc-v/src/common/supervisor/riscv_dispatch_syscall.S
@@ -109,6 +109,8 @@ riscv_dispatch_syscall:
mv sp, a0 /* use sp, as a0 gets wiped */
+ riscv_loadfpu sp
+
REGLOAD s0, REG_EPC(sp) /* restore epc */
csrw CSR_EPC, s0
@@ -127,7 +129,6 @@ riscv_dispatch_syscall:
csrw CSR_STATUS, s0
load_ctx sp
- riscv_loadfpu sp
REGLOAD sp, REG_SP(sp) /* restore original sp */