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Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2022/01/12 14:45:01 UTC
[GitHub] [incubator-nuttx] no1wudi opened a new pull request #5210: arch/risc-v: Refine exception_common
no1wudi opened a new pull request #5210:
URL: https://github.com/apache/incubator-nuttx/pull/5210
## Summary
Remove duplicated exception_common from chip specific codes, but keep custom implements for rv32m1/mpfs/esp32c3
## Impact
Refactor only.
## Testing
CI and fe310/rv32-virt on qemu.
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[GitHub] [incubator-nuttx] no1wudi edited a comment on pull request #5210: arch/risc-v: Refine exception_common
Posted by GitBox <gi...@apache.org>.
no1wudi edited a comment on pull request #5210:
URL: https://github.com/apache/incubator-nuttx/pull/5210#issuecomment-1014069195
@normanr Could you please have a try to add this line to riscv_exception_common.S line 46 ?
```
.align 8
```
This is only difference with bl602's implementation and riscv_exception_common.S
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[GitHub] [incubator-nuttx] normanr edited a comment on pull request #5210: arch/risc-v: Refine exception_common
Posted by GitBox <gi...@apache.org>.
normanr edited a comment on pull request #5210:
URL: https://github.com/apache/incubator-nuttx/pull/5210#issuecomment-1014056001
commit c6749fd6fd3e15bd65ab25a7de05a6a0abdb6bd5 causes my bl602 board to fail to start with `irq_unexpected_isr: ERROR irq: 2`. The backtrace isn't really helpful because it's so early in startup so there's only the idle and irq threads.
```
[ 0.000000] [ 0] [<0x2302092a>] sched_dumpstack+0x34/0x8a
[ 0.000000] [ 0] [<0x2301cafa>] nxsched_foreach+0x5a/0x5e
[ 0.000000] [ 0] [<0x23007c4c>] up_assert+0x352/0x402
[ 0.000000] [ 0] [<0x23004f32>] _assert+0x10/0x1a
[ 0.000000] [ 0] [<0x23001f38>] sched_lock+0/0x34
[ 0.000000] [ 0] [<0x23001ed6>] irq_dispatch+0x26/0x4a
[ 0.000000] [ 0] [<0x23000d8e>] riscv_dispatch_irq+0x38/0x6c
[ 0.000000] [ 0] [<0x23000d06>] exception_common+0x78/0xc8
[ 0.000000] [ 0] [<0x413bed1e>] __init_array_end+0x1e3347e2/0
```
(my guess is that the bl602 doesn't have a Hardware thread ID register (mhartid), so when the common code tries to access it, it raise an illegal instruction exception).
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[GitHub] [incubator-nuttx] no1wudi commented on pull request #5210: arch/risc-v: Refine exception_common
Posted by GitBox <gi...@apache.org>.
no1wudi commented on pull request #5210:
URL: https://github.com/apache/incubator-nuttx/pull/5210#issuecomment-1014069195
@normanr Could you please have a try to add this line to riscv_exception_common.S line 46 ?
```
.align 8
```
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[GitHub] [incubator-nuttx] normanr commented on pull request #5210: arch/risc-v: Refine exception_common
Posted by GitBox <gi...@apache.org>.
normanr commented on pull request #5210:
URL: https://github.com/apache/incubator-nuttx/pull/5210#issuecomment-1014067025
EPC isn't compiled code, but other registers are close:
```
[ 0.000000] riscv_registerdump: EPC: 415bed1e
[ 0.000000] riscv_registerdump: A0: 00000000 A1: 00000000 A2: 00000000 A3: 4203b4c0
[ 0.000000] riscv_registerdump: A4: 00000000 A5: 00000001 A6: 00000000 A7: 00000003
[ 0.000000] riscv_registerdump: T0: 4202109c T1: 42011c88 T2: 00000000 T3: 4203b50c
[ 0.000000] riscv_registerdump: T4: 415e3738 T5: 0000002a T6: 0000002e
[ 0.000000] riscv_registerdump: S0: 00000000 S1: 00000001 S2: 42010fc0 S3: 0008ad60
[ 0.000000] riscv_registerdump: S4: 23000000 S5: 4202109c S6: 42020000 S7: 0009bd60
[ 0.000000] riscv_registerdump: S8: 4202137c S9: 2300266a S10: 00000d60 S11: 42010cb0
[ 0.000000] riscv_registerdump: SP: 420110c0 FP: 00000000 TP: 230000f6 RA: 23000106
[ 0.000000] riscv_dumpstate: sp: 42011970
[ 0.000000] riscv_dumpstate: IRQ stack:
[ 0.000000] riscv_dumpstate: base: 42011200
[ 0.000000] riscv_dumpstate: size: 00000800
[ 0.000000] riscv_stackdump: 08x: 42011960 42011970 2307b000 420119b0 23007b36 deadbeef deadbeef 2307adac
[ 0.000000] riscv_stackdump: 08x: 42011980 00000d60 2300266a 4202137c 0009bd60 42020000 4202109c 23000000
[ 0.000000] riscv_stackdump: 08x: 420119a0 42010fb8 42016000 420119c0 23004f32 42016220 80007880 420119d0
[ 0.000000] riscv_stackdump: 08x: 420119c0 deadbeef deadbeef 420119e0 23001ed6 deadbeef deadbeef 42011a00
[ 0.000000] riscv_stackdump: 08x: 420119e0 deadbeef deadbeef deadbeef 0008ad60 42010fc0 23000c6c 00000000
```
addr2line for other registers and stack values:
```
23000000 __start arch/risc-v/src/chip/bl602_entry.S:42
230000f6 bl602_entry_enable_fpu_end arch/risc-v/src/chip/bl602_entry.S:143
23000106 bl602_entry_deadloop arch/risc-v/src/chip/bl602_entry.S:154
2300266a work_thread sched/wqueue/kwork_thread.c:122
23000c6c modifyreg32 arch/risc-v/src/common/riscv_modifyreg32.c:47
```
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[GitHub] [incubator-nuttx] no1wudi edited a comment on pull request #5210: arch/risc-v: Refine exception_common
Posted by GitBox <gi...@apache.org>.
no1wudi edited a comment on pull request #5210:
URL: https://github.com/apache/incubator-nuttx/pull/5210#issuecomment-1014063517
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[GitHub] [incubator-nuttx] normanr commented on pull request #5210: arch/risc-v: Refine exception_common
Posted by GitBox <gi...@apache.org>.
normanr commented on pull request #5210:
URL: https://github.com/apache/incubator-nuttx/pull/5210#issuecomment-1014056001
commit c6749fd6fd3e15bd65ab25a7de05a6a0abdb6bd5 causes my bl602 board to fail to start with `irq_unexpected_isr: ERROR irq: 2`. The backtrace isn't really helpful because it's so early in startup so there's only the idle and irq threads.
```
[ 0.000000] [ 0] [<0x2302092a>] sched_dumpstack+0x34/0x8a
[ 0.000000] [ 0] [<0x2301cafa>] nxsched_foreach+0x5a/0x5e
[ 0.000000] [ 0] [<0x23007c4c>] up_assert+0x352/0x402
[ 0.000000] [ 0] [<0x23004f32>] _assert+0x10/0x1a
[ 0.000000] [ 0] [<0x23001f38>] sched_lock+0/0x34
[ 0.000000] [ 0] [<0x23001ed6>] irq_dispatch+0x26/0x4a
[ 0.000000] [ 0] [<0x23000d8e>] riscv_dispatch_irq+0x38/0x6c
[ 0.000000] [ 0] [<0x23000d06>] exception_common+0x78/0xc8
[ 0.000000] [ 0] [<0x413bed1e>] __init_array_end+0x1e3347e2/0
```
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[GitHub] [incubator-nuttx] no1wudi commented on pull request #5210: arch/risc-v: Refine exception_common
Posted by GitBox <gi...@apache.org>.
no1wudi commented on pull request #5210:
URL: https://github.com/apache/incubator-nuttx/pull/5210#issuecomment-1014080847
See #5243
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[GitHub] [incubator-nuttx] xiaoxiang781216 commented on a change in pull request #5210: arch/risc-v: Refine exception_common
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on a change in pull request #5210:
URL: https://github.com/apache/incubator-nuttx/pull/5210#discussion_r783773000
##########
File path: arch/risc-v/src/c906/c906_head.S
##########
@@ -108,145 +108,3 @@ _fini:
/* These don't have to do anything since we use init_array/fini_array. */
ret
-
Review comment:
remove "global exception_common" at line 37
##########
File path: arch/risc-v/src/litex/litex_head.S
##########
@@ -72,132 +72,3 @@ _fini:
/* These don't have to do anything since we use init_array/fini_array. */
ret
-
-/****************************************************************************
Review comment:
remove ".global exception_common” at line 34
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[GitHub] [incubator-nuttx] normanr edited a comment on pull request #5210: arch/risc-v: Refine exception_common
Posted by GitBox <gi...@apache.org>.
normanr edited a comment on pull request #5210:
URL: https://github.com/apache/incubator-nuttx/pull/5210#issuecomment-1014067025
EPC isn't compiled code, but other registers are close:
```
[ 0.000000] riscv_registerdump: EPC: 415bed1e
[ 0.000000] riscv_registerdump: A0: 00000000 A1: 00000000 A2: 00000000 A3: 4203b4c0
[ 0.000000] riscv_registerdump: A4: 00000000 A5: 00000001 A6: 00000000 A7: 00000003
[ 0.000000] riscv_registerdump: T0: 4202109c T1: 42011c88 T2: 00000000 T3: 4203b50c
[ 0.000000] riscv_registerdump: T4: 415e3738 T5: 0000002a T6: 0000002e
[ 0.000000] riscv_registerdump: S0: 00000000 S1: 00000001 S2: 42010fc0 S3: 0008ad60
[ 0.000000] riscv_registerdump: S4: 23000000 S5: 4202109c S6: 42020000 S7: 0009bd60
[ 0.000000] riscv_registerdump: S8: 4202137c S9: 2300266a S10: 00000d60 S11: 42010cb0
[ 0.000000] riscv_registerdump: SP: 420110c0 FP: 00000000 TP: 230000f6 RA: 23000106
[ 0.000000] riscv_dumpstate: sp: 42011970
[ 0.000000] riscv_dumpstate: IRQ stack:
[ 0.000000] riscv_dumpstate: base: 42011200
[ 0.000000] riscv_dumpstate: size: 00000800
[ 0.000000] riscv_stackdump: 08x: 42011960 42011970 2307b000 420119b0 23007b36 deadbeef deadbeef 2307adac
[ 0.000000] riscv_stackdump: 08x: 42011980 00000d60 2300266a 4202137c 0009bd60 42020000 4202109c 23000000
[ 0.000000] riscv_stackdump: 08x: 420119a0 42010fb8 42016000 420119c0 23004f32 42016220 80007880 420119d0
[ 0.000000] riscv_stackdump: 08x: 420119c0 deadbeef deadbeef 420119e0 23001ed6 deadbeef deadbeef 42011a00
[ 0.000000] riscv_stackdump: 08x: 420119e0 deadbeef deadbeef deadbeef 0008ad60 42010fc0 23000c6c 00000000
```
addr2line for other registers and stack values:
```
23000000 __start arch/risc-v/src/chip/bl602_entry.S:42
230000f6 bl602_entry_enable_fpu_end arch/risc-v/src/chip/bl602_entry.S:143
23000106 bl602_entry_deadloop arch/risc-v/src/chip/bl602_entry.S:154
23000c6c modifyreg32 arch/risc-v/src/common/riscv_modifyreg32.c:47
23001ed6 irq_dispatch sched/irq/irq_dispatch.c:200
2300266a work_thread sched/wqueue/kwork_thread.c:122
```
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[GitHub] [incubator-nuttx] xiaoxiang781216 commented on a change in pull request #5210: arch/risc-v: Refine exception_common
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on a change in pull request #5210:
URL: https://github.com/apache/incubator-nuttx/pull/5210#discussion_r783290961
##########
File path: arch/risc-v/src/bl602/Make.defs
##########
@@ -20,7 +20,7 @@
# Specify our HEAD assembly file. This will be linked as
# the first object file, so it will appear at address 0
-HEAD_ASRC = bl602_entry.S
+HEAD_ASRC = bl602_entry.S riscv_exception_common.S
# Specify our general Assembly files
CHIP_ASRCS = bl602_head.S
Review comment:
change bl602_head.S to riscv_exception_common.S
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[GitHub] [incubator-nuttx] no1wudi commented on a change in pull request #5210: arch/risc-v: Refine exception_common
Posted by GitBox <gi...@apache.org>.
no1wudi commented on a change in pull request #5210:
URL: https://github.com/apache/incubator-nuttx/pull/5210#discussion_r783569129
##########
File path: arch/risc-v/src/qemu-rv32/Make.defs
##########
@@ -20,7 +20,7 @@
# Specify our HEAD assembly file. This will be linked as
# the first object file, so it will appear at address 0
-HEAD_ASRC = qemu_rv32_head.S
+HEAD_ASRC = qemu_rv32_head.S riscv_exception_common.S
Review comment:
Yes, we should do this, but some potential problem here, for FE310 on QEMU, it only works with `exception_common` implemented in fe310_head.S or disable the "C" extension.
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[GitHub] [incubator-nuttx] no1wudi commented on pull request #5210: arch/risc-v: Refine exception_common
Posted by GitBox <gi...@apache.org>.
no1wudi commented on pull request #5210:
URL: https://github.com/apache/incubator-nuttx/pull/5210#issuecomment-1014063517
@normanr Hi, exception 2 means illegal instruction, could you check the exception address by this:
```
riscv64-unknown-elf-addr2line -f -e nuttx value_of_epc
```
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[GitHub] [incubator-nuttx] no1wudi commented on pull request #5210: arch/risc-v: Refine exception_common
Posted by GitBox <gi...@apache.org>.
no1wudi commented on pull request #5210:
URL: https://github.com/apache/incubator-nuttx/pull/5210#issuecomment-1014089035
> It's not the only difference, the CONFIG_ARCH_INTERRUPTSTACK block has different code:
Yes, this section is different on text, but on bl602 the mhartid is always 0, so the different logic will not execute.
>
> ```
> 1:
> la sp, g_intstacktop
> li t0, -(CONFIG_ARCH_INTERRUPTSTACK & ~15)
> add sp, sp, t0
> 2:
>
> #endif
> ```
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[GitHub] [incubator-nuttx] xiaoxiang781216 commented on a change in pull request #5210: arch/risc-v: Refine exception_common
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on a change in pull request #5210:
URL: https://github.com/apache/incubator-nuttx/pull/5210#discussion_r783288310
##########
File path: arch/risc-v/src/litex/Make.defs
##########
@@ -20,7 +20,7 @@
# Specify our HEAD assembly file. This will be linked as
# the first object file, so it will appear at address 0
-HEAD_ASRC = litex_head.S
+HEAD_ASRC = litex_head.S riscv_exception_common.S
Review comment:
ditto
##########
File path: arch/risc-v/src/k210/Make.defs
##########
@@ -20,7 +20,7 @@
# Specify our HEAD assembly file. This will be linked as
# the first object file, so it will appear at address 0
-HEAD_ASRC = k210_head.S
+HEAD_ASRC = k210_head.S riscv_exception_common.S
Review comment:
ditto
##########
File path: arch/risc-v/src/bl602/Make.defs
##########
@@ -20,7 +20,7 @@
# Specify our HEAD assembly file. This will be linked as
# the first object file, so it will appear at address 0
-HEAD_ASRC = bl602_entry.S
+HEAD_ASRC = bl602_entry.S riscv_exception_common.S
Review comment:
ditto
##########
File path: arch/risc-v/src/fe310/Make.defs
##########
@@ -20,10 +20,10 @@
# Specify our HEAD assembly file. This will be linked as
# the first object file, so it will appear at address 0
-HEAD_ASRC = fe310_head.S
+HEAD_ASRC = fe310_head.S riscv_exception_common.S
Review comment:
ditto
##########
File path: arch/risc-v/src/qemu-rv32/Make.defs
##########
@@ -20,7 +20,7 @@
# Specify our HEAD assembly file. This will be linked as
# the first object file, so it will appear at address 0
-HEAD_ASRC = qemu_rv32_head.S
+HEAD_ASRC = qemu_rv32_head.S riscv_exception_common.S
Review comment:
should we move to CMN_ASRCS? HEAD_ASRC can only contain one source file.
##########
File path: arch/risc-v/src/c906/Make.defs
##########
@@ -20,7 +20,7 @@
# Specify our HEAD assembly file. This will be linked as
# the first object file, so it will appear at address 0
-HEAD_ASRC = c906_head.S
+HEAD_ASRC = c906_head.S riscv_exception_common.S
Review comment:
ditto
##########
File path: arch/risc-v/src/fe310/Make.defs
##########
@@ -20,10 +20,10 @@
# Specify our HEAD assembly file. This will be linked as
# the first object file, so it will appear at address 0
-HEAD_ASRC = fe310_head.S
+HEAD_ASRC = fe310_head.S riscv_exception_common.S
# Specify our general Assembly files
-CMN_ASRCS += riscv_vectors.S riscv_testset.S
+CMN_ASRCS += riscv_vectors.S riscv_testset.S
Review comment:
revert the change
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[GitHub] [incubator-nuttx] normanr commented on pull request #5210: arch/risc-v: Refine exception_common
Posted by GitBox <gi...@apache.org>.
normanr commented on pull request #5210:
URL: https://github.com/apache/incubator-nuttx/pull/5210#issuecomment-1014072189
It's not the only difference, the CONFIG_ARCH_INTERRUPTSTACK block has different code:
```
#if CONFIG_ARCH_INTERRUPTSTACK > 15
/* Switch to interrupt stack */
lui sp, %hi(g_intstacktop)
addi sp, sp, %lo(g_intstacktop)
#ifdef CONFIG_STACK_OVERFLOW_CHECK
la s11, g_intstackalloc
#endif
#endif
```
vs
```
#if CONFIG_ARCH_INTERRUPTSTACK > 15
/* Load mhartid (cpuid) */
csrr s0, mhartid
/* Switch to interrupt stack */
bnez s0, 1f
la sp, g_intstacktop
j 2f
1:
la sp, g_intstacktop
li t0, -(CONFIG_ARCH_INTERRUPTSTACK & ~15)
add sp, sp, t0
2:
#endif
```
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[GitHub] [incubator-nuttx] no1wudi commented on pull request #5210: arch/risc-v: Refine exception_common
Posted by GitBox <gi...@apache.org>.
no1wudi commented on pull request #5210:
URL: https://github.com/apache/incubator-nuttx/pull/5210#issuecomment-1014076580
> Adding the `.align 8` seems to make things happy!
Thank you ! I'll submit the fix soon.
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[GitHub] [incubator-nuttx] normanr commented on pull request #5210: arch/risc-v: Refine exception_common
Posted by GitBox <gi...@apache.org>.
normanr commented on pull request #5210:
URL: https://github.com/apache/incubator-nuttx/pull/5210#issuecomment-1014073225
Adding the `.align 8` seems to make things happy!
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[GitHub] [incubator-nuttx] no1wudi commented on a change in pull request #5210: arch/risc-v: Refine exception_common
Posted by GitBox <gi...@apache.org>.
no1wudi commented on a change in pull request #5210:
URL: https://github.com/apache/incubator-nuttx/pull/5210#discussion_r783590478
##########
File path: arch/risc-v/src/qemu-rv32/Make.defs
##########
@@ -20,7 +20,7 @@
# Specify our HEAD assembly file. This will be linked as
# the first object file, so it will appear at address 0
-HEAD_ASRC = qemu_rv32_head.S
+HEAD_ASRC = qemu_rv32_head.S riscv_exception_common.S
Review comment:
It seems that __trap_vec is not on 4 byte boundary in some situation.
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[GitHub] [incubator-nuttx] pkarashchenko merged pull request #5210: arch/risc-v: Refine exception_common
Posted by GitBox <gi...@apache.org>.
pkarashchenko merged pull request #5210:
URL: https://github.com/apache/incubator-nuttx/pull/5210
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