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Posted to commits@mynewt.apache.org by je...@apache.org on 2023/04/13 19:34:03 UTC
[mynewt-core] 03/05: hw/bsp: Add nucleo-u575zi-q bsp
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit 05a88c92c7d39589261d3d31eb564e13922c16ad
Author: Jerzy Kasenberg <je...@codecoup.pl>
AuthorDate: Tue Mar 28 21:36:20 2023 +0200
hw/bsp: Add nucleo-u575zi-q bsp
---
hw/bsp/nucleo-u575zi-q/boot-nucleo-u575zi-q.ld | 28 +
hw/bsp/nucleo-u575zi-q/bsp.yml | 70 +++
hw/bsp/nucleo-u575zi-q/debug.sh | 34 +
hw/bsp/nucleo-u575zi-q/download.sh | 39 ++
hw/bsp/nucleo-u575zi-q/include/bsp/bsp.h | 93 +++
.../include/bsp/stm32u5xx_hal_conf.h | 505 +++++++++++++++
hw/bsp/nucleo-u575zi-q/nucleo-u575zi-q.ld | 30 +
hw/bsp/nucleo-u575zi-q/pkg.yml | 39 ++
.../src/arch/cortex_m33/startup_stm32u575xx.s | 691 +++++++++++++++++++++
hw/bsp/nucleo-u575zi-q/src/hal_bsp.c | 251 ++++++++
hw/bsp/nucleo-u575zi-q/syscfg.yml | 75 +++
11 files changed, 1855 insertions(+)
diff --git a/hw/bsp/nucleo-u575zi-q/boot-nucleo-u575zi-q.ld b/hw/bsp/nucleo-u575zi-q/boot-nucleo-u575zi-q.ld
new file mode 100644
index 000000000..8a6dd565c
--- /dev/null
+++ b/hw/bsp/nucleo-u575zi-q/boot-nucleo-u575zi-q.ld
@@ -0,0 +1,28 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 32K
+}
+
+/* The bootloader does not contain an image header */
+_imghdr_size = 0x0;
diff --git a/hw/bsp/nucleo-u575zi-q/bsp.yml b/hw/bsp/nucleo-u575zi-q/bsp.yml
new file mode 100644
index 000000000..8663f43b2
--- /dev/null
+++ b/hw/bsp/nucleo-u575zi-q/bsp.yml
@@ -0,0 +1,70 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+bsp.name: "NUCLEO-U575ZI-Q"
+bsp.url: https://www.st.com/en/evaluation-tools/nucleo-u575zi-q.html
+bsp.maker: "STMicroelectronics"
+bsp.arch: cortex_m33
+bsp.compiler: compiler/arm-none-eabi-m33
+bsp.linkerscript:
+ - "hw/bsp/nucleo-u575zi-q/nucleo-u575zi-q.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32u5xx/stm32u5xx.ld"
+bsp.linkerscript.BOOT_LOADER.OVERWRITE:
+ - "hw/bsp/nucleo-u575zi-q/boot-nucleo-u575zi-q.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32u5xx/stm32u5xx.ld"
+bsp.downloadscript: "hw/bsp/nucleo-u575zi-q/download.sh"
+bsp.debugscript: "hw/bsp/nucleo-u575zi-q/debug.sh"
+
+bsp.flash_map:
+ areas:
+ # System areas.
+ FLASH_AREA_BOOTLOADER:
+ device: 0
+ offset: 0x08000000
+ size: 128kB
+ FLASH_AREA_IMAGE_0:
+ device: 0
+ offset: 0x08020000
+ size: 256kB
+ FLASH_AREA_IMAGE_1:
+ device: 0
+ offset: 0x08060000
+ size: 256kB
+ FLASH_AREA_IMAGE_SCRATCH:
+ device: 0
+ offset: 0x080A0000
+ size: 128kB
+
+ # User areas.
+ FLASH_AREA_REBOOT_LOG:
+ user_id: 0
+ device: 0
+ offset: 0x080C0000
+ size: 128kB
+ FLASH_AREA_NFFS:
+ user_id: 1
+ device: 0
+ offset: 0x080E0000
+ size: 128kB
+
+ FLASH_AREA_SPI:
+ user_id: 2
+ device: 1
+ offset: 0x0
+ size: 128kB
diff --git a/hw/bsp/nucleo-u575zi-q/debug.sh b/hw/bsp/nucleo-u575zi-q/debug.sh
new file mode 100644
index 000000000..8445f238e
--- /dev/null
+++ b/hw/bsp/nucleo-u575zi-q/debug.sh
@@ -0,0 +1,34 @@
+#!/bin/sh
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Called with following variables set:
+# - CORE_PATH is absolute path to @apache-mynewt-core
+# - BSP_PATH is absolute path to hw/bsp/bsp_name
+# - BIN_BASENAME is the path to prefix to target binary,
+# .elf appended to name is the ELF file
+# - FEATURES holds the target features string
+# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+# - RESET set if target should be reset when attaching
+# - NO_GDB set if we should not start gdb to debug
+#
+. $CORE_PATH/hw/scripts/stlink.sh
+
+FILE_NAME=$BIN_BASENAME.elf
+
+stlink_debug
diff --git a/hw/bsp/nucleo-u575zi-q/download.sh b/hw/bsp/nucleo-u575zi-q/download.sh
new file mode 100644
index 000000000..ad96a8d44
--- /dev/null
+++ b/hw/bsp/nucleo-u575zi-q/download.sh
@@ -0,0 +1,39 @@
+#!/bin/sh
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Called with following variables set:
+# - CORE_PATH is absolute path to @apache-mynewt-core
+# - BSP_PATH is absolute path to hw/bsp/bsp_name
+# - BIN_BASENAME is the path to prefix to target binary,
+# .elf appended to name is the ELF file
+# - IMAGE_SLOT is the image slot to download to (for non-mfg-image, non-boot)
+# - FEATURES holds the target features string
+# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+# - MFG_IMAGE is "1" if this is a manufacturing image
+# - FLASH_OFFSET contains the flash offset to download to
+# - BOOT_LOADER is set if downloading a bootloader
+
+. $CORE_PATH/hw/scripts/stlink.sh
+
+if [ "$MFG_IMAGE" ]; then
+ FLASH_OFFSET=0x0C000000
+fi
+
+common_file_to_load
+stlink_load
diff --git a/hw/bsp/nucleo-u575zi-q/include/bsp/bsp.h b/hw/bsp/nucleo-u575zi-q/include/bsp/bsp.h
new file mode 100644
index 000000000..a9e6f7104
--- /dev/null
+++ b/hw/bsp/nucleo-u575zi-q/include/bsp/bsp.h
@@ -0,0 +1,93 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#ifndef H_BSP_H
+#define H_BSP_H
+
+#include <inttypes.h>
+#include <mcu/mcu.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Define special stackos sections */
+#define sec_data_core __attribute__((section(".data.core")))
+#define sec_bss_core __attribute__((section(".bss.core")))
+#define sec_bss_nz_core __attribute__((section(".bss.core.nz")))
+
+/* More convenient section placement macros. */
+#define bssnz_t sec_bss_nz_core
+
+extern uint8_t _ram_start[];
+
+#define RAM_SIZE (SRAM1_SIZE + SRAM2_SIZE + SRAM3_SIZE)
+
+/* LED pins */
+#define LED_1 MCU_GPIO_PORTC(7)
+#define LED_2 MCU_GPIO_PORTB(7)
+#define LED_3 MCU_GPIO_PORTG(2)
+
+#define LED_GREEN LED_1
+#define LED_BLUE LED_2
+#define LED_RED LED_3
+
+#define LED_BLINK_PIN LED_1
+
+/* Button pin */
+#define BUTTON_1 MCU_GPIO_PORTC(13)
+
+/* Arduino pins */
+#define ARDUINO_PIN_D0 MCU_GPIO_PORTG(8)
+#define ARDUINO_PIN_D1 MCU_GPIO_PORTG(7)
+#define ARDUINO_PIN_D2 MCU_GPIO_PORTF(15)
+#define ARDUINO_PIN_D3 MCU_GPIO_PORTE(13)
+#define ARDUINO_PIN_D4 MCU_GPIO_PORTF(14)
+#define ARDUINO_PIN_D5 MCU_GPIO_PORTE(11)
+#define ARDUINO_PIN_D6 MCU_GPIO_PORTE(9)
+#define ARDUINO_PIN_D7 MCU_GPIO_PORTF(13)
+#define ARDUINO_PIN_D8 MCU_GPIO_PORTF(12)
+#define ARDUINO_PIN_D9 MCU_GPIO_PORTD(15)
+#define ARDUINO_PIN_D10 MCU_GPIO_PORTD(14)
+#define ARDUINO_PIN_D11 MCU_GPIO_PORTA(7)
+#define ARDUINO_PIN_D12 MCU_GPIO_PORTA(6)
+#define ARDUINO_PIN_D13 MCU_GPIO_PORTA(5)
+#define ARDUINO_PIN_D14 MCU_GPIO_PORTB(9)
+#define ARDUINO_PIN_D15 MCU_GPIO_PORTB(8)
+#define ARDUINO_PIN_A0 MCU_GPIO_PORTA(3)
+#define ARDUINO_PIN_A1 MCU_GPIO_PORTA(2)
+#define ARDUINO_PIN_A2 MCU_GPIO_PORTC(3)
+#define ARDUINO_PIN_A3 MCU_GPIO_PORTB(0)
+#define ARDUINO_PIN_A4 MCU_GPIO_PORTC(1)
+#define ARDUINO_PIN_A5 MCU_GPIO_PORTC(0)
+
+#define ARDUINO_PIN_RX ARDUINO_PIN_D0
+#define ARDUINO_PIN_TX ARDUINO_PIN_D1
+
+#define ARDUINO_PIN_SCL MCU_GPIO_PORTB(8)
+#define ARDUINO_PIN_SDA MCU_GPIO_PORTB(9)
+
+#define ARDUINO_PIN_SCK ARDUINO_PIN_D13
+#define ARDUINO_PIN_MOSI ARDUINO_PIN_D11
+#define ARDUINO_PIN_MISO ARDUINO_PIN_D12
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* H_BSP_H */
diff --git a/hw/bsp/nucleo-u575zi-q/include/bsp/stm32u5xx_hal_conf.h b/hw/bsp/nucleo-u575zi-q/include/bsp/stm32u5xx_hal_conf.h
new file mode 100644
index 000000000..b210b73ca
--- /dev/null
+++ b/hw/bsp/nucleo-u575zi-q/include/bsp/stm32u5xx_hal_conf.h
@@ -0,0 +1,505 @@
+/**
+ ******************************************************************************
+ * @file stm32u5xx_hal_conf_template.h
+ * @author MCD Application Team
+ * @brief HAL configuration template file.
+ * This file should be copied to the application folder and renamed
+ * to stm32u5xx_hal_conf.h.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32U5xx_HAL_CONF_H
+#define STM32U5xx_HAL_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <syscfg/syscfg.h>
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_COMP_MODULE_ENABLED
+#define HAL_CORDIC_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DCACHE_MODULE_ENABLED
+#define HAL_DCMI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_DMA2D_MODULE_ENABLED
+#define HAL_DSI_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+//#define HAL_FDCAN_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_FMAC_MODULE_ENABLED
+#define HAL_GFXMMU_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_GPU2D_MODULE_ENABLED
+#define HAL_GTZC_MODULE_ENABLED
+#define HAL_HASH_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_ICACHE_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_LPTIM_MODULE_ENABLED
+#define HAL_LTDC_MODULE_ENABLED
+#define HAL_MDF_MODULE_ENABLED
+#define HAL_MMC_MODULE_ENABLED
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_OPAMP_MODULE_ENABLED
+#define HAL_OSPI_MODULE_ENABLED
+#define HAL_OTFDEC_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_PKA_MODULE_ENABLED
+#define HAL_PSSI_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RAMCFG_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SAI_MODULE_ENABLED
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_SMBUS_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_TSC_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+//#define HAL_XSPI_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+#define HSE_VALUE 16000000UL /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal Multiple Speed oscillator (MSI) default value.
+ * This value is the default MSI range value after Reset.
+ */
+#if !defined (MSI_VALUE)
+#define MSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+#define HSI_VALUE 16000000UL /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
+ * This internal oscillator is mainly dedicated to provide a high precision clock to
+ * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
+ * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
+ * which is subject to manufacturing process variations.
+ */
+#if !defined (HSI48_VALUE)
+#define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
+ The real value my vary depending on manufacturing process variations.*/
+#endif /* HSI48_VALUE */
+
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz. The real value may
+vary depending on the variations in voltage and temperature.*/
+
+#if !defined (LSI_STARTUP_TIMEOUT)
+#define LSI_STARTUP_TIMEOUT 130UL /*!< Time out for LSI start up, in ms */
+#endif /* LSI_STARTUP_TIMEOUT */
+
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ * This value is used by the UART, RTC HAL module to compute the system frequency
+ */
+#if !defined (LSE_VALUE)
+#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief External clock source for SAI1 peripheral
+ * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
+ * frequency.
+ */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+#define EXTERNAL_SAI1_CLOCK_VALUE 48000UL /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE 3300UL /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY ((1UL<<__NVIC_PRIO_BITS) - 1UL) /*!< tick interrupt priority (lowest by default) */
+#define USE_RTOS 0U
+#define PREFETCH_ENABLE MYNEWT_VAL(STM32_FLASH_PREFETCH_ENABLE)
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1U */
+
+/* ################## Register callback feature configuration ############### */
+/**
+ * @brief Set below the peripheral configuration to "1U" to add the support
+ * of HAL callback registration/unregistration feature for the HAL
+ * driver(s). This allows user application to provide specific callback
+ * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting
+ * the default weak callback functions (see each stm32u5xx_hal_ppp.h file
+ * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef
+ * for each PPP peripheral).
+ */
+#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
+#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */
+#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */
+#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
+#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
+#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
+#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */
+#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */
+#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
+#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */
+#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */
+#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U /* GFXMMU register callback disabled */
+#define USE_HAL_GPU2D_REGISTER_CALLBACKS 0U /* GPU2D register callback disabled */
+#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
+#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
+#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
+#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */
+#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
+#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */
+#define USE_HAL_MDF_REGISTER_CALLBACKS 0U /* MDF register callback disabled */
+#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
+#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
+#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
+#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */
+#define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0U /* OTFDEC register callback disabled */
+#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
+#define USE_HAL_PKA_REGISTER_CALLBACKS 0U /* PKA register callback disabled */
+#define USE_HAL_RAMCFG_REGISTER_CALLBACKS 0U /* RAMCFG register callback disabled */
+#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
+#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
+#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */
+#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
+#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
+#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
+#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
+#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
+#define USE_HAL_TSC_REGISTER_CALLBACKS 0U /* TSC register callback disabled */
+#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
+#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
+#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
+#define USE_HAL_XSPI_REGISTER_CALLBACKS 0U /* XSPI register callback disabled */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+#define USE_SPI_CRC 1U
+
+/* ################## SDMMC peripheral configuration ######################### */
+
+#define USE_SD_TRANSCEIVER 0U
+
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+#include "stm32u5xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+#include "stm32u5xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_ICACHE_MODULE_ENABLED
+#include "stm32u5xx_hal_icache.h"
+#endif /* HAL_ICACHE_MODULE_ENABLED */
+
+#ifdef HAL_DCACHE_MODULE_ENABLED
+#include "stm32u5xx_hal_dcache.h"
+#endif /* HAL_DCACHE_MODULE_ENABLED */
+
+#ifdef HAL_GTZC_MODULE_ENABLED
+#include "stm32u5xx_hal_gtzc.h"
+#endif /* HAL_GTZC_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+#include "stm32u5xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+#include "stm32u5xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+#include "stm32u5xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+#include "stm32u5xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_PKA_MODULE_ENABLED
+#include "stm32u5xx_hal_pka.h"
+#endif /* HAL_PKA_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+#include "stm32u5xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+#include "stm32u5xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+#include "stm32u5xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+#include "stm32u5xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+#include "stm32u5xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+#include "stm32u5xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GFXMMU_MODULE_ENABLED
+#include "stm32u5xx_hal_gfxmmu.h"
+#endif /* HAL_GFXMMU_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+#include "stm32u5xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+#include "stm32u5xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+#include "stm32u5xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+#include "stm32u5xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+#include "stm32u5xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+#include "stm32u5xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+#include "stm32u5xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32u5xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+#include "stm32u5xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+#include "stm32u5xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+#include "stm32u5xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+#include "stm32u5xx_hal_ospi.h"
+#endif /* HAL_OSPI_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+#include "stm32u5xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+#include "stm32u5xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+#include "stm32u5xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+#include "stm32u5xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+#include "stm32u5xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+#include "stm32u5xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+#include "stm32u5xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+#include "stm32u5xx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+#include "stm32u5xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+#include "stm32u5xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+#include "stm32u5xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+#include "stm32u5xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+#include "stm32u5xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+#include "stm32u5xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+#include "stm32u5xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_CORDIC_MODULE_ENABLED
+#include "stm32u5xx_hal_cordic.h"
+#endif /* HAL_CORDIC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+#include "stm32u5xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+#include "stm32u5xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+#include "stm32u5xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_FMAC_MODULE_ENABLED
+#include "stm32u5xx_hal_fmac.h"
+#endif /* HAL_FMAC_MODULE_ENABLED */
+
+#ifdef HAL_OTFDEC_MODULE_ENABLED
+#include "stm32u5xx_hal_otfdec.h"
+#endif /* HAL_OTFDEC_MODULE_ENABLED */
+
+#ifdef HAL_PSSI_MODULE_ENABLED
+#include "stm32u5xx_hal_pssi.h"
+#endif /* HAL_PSSI_MODULE_ENABLED */
+
+#ifdef HAL_RAMCFG_MODULE_ENABLED
+#include "stm32u5xx_hal_ramcfg.h"
+#endif /* HAL_RAMCFG_MODULE_ENABLED */
+
+#ifdef HAL_MDF_MODULE_ENABLED
+#include "stm32u5xx_hal_mdf.h"
+#endif /* HAL_MDF_MODULE_ENABLED */
+
+#ifdef HAL_GPU2D_MODULE_ENABLED
+#include "stm32u5xx_hal_gpu2d.h"
+#endif /* HAL_GPU2D_MODULE_ENABLED */
+
+#ifdef HAL_XSPI_MODULE_ENABLED
+#include "stm32u5xx_hal_xspi.h"
+#endif /* HAL_XSPI_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t *file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32U5xx_HAL_CONF_H */
+
diff --git a/hw/bsp/nucleo-u575zi-q/nucleo-u575zi-q.ld b/hw/bsp/nucleo-u575zi-q/nucleo-u575zi-q.ld
new file mode 100644
index 000000000..92131c646
--- /dev/null
+++ b/hw/bsp/nucleo-u575zi-q/nucleo-u575zi-q.ld
@@ -0,0 +1,30 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/* Linker script for STM32U575 when running from flash and using the bootloader */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08020000, LENGTH = 384K /* Image slot 1 */
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 704K /* SRAM1 + SRAM2 + SRAM3 */
+}
+
+/* This linker script is used for images and thus contains an image header */
+_imghdr_size = 0x20;
diff --git a/hw/bsp/nucleo-u575zi-q/pkg.yml b/hw/bsp/nucleo-u575zi-q/pkg.yml
new file mode 100644
index 000000000..d6083fd2c
--- /dev/null
+++ b/hw/bsp/nucleo-u575zi-q/pkg.yml
@@ -0,0 +1,39 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: hw/bsp/nucleo-u575zi-q
+pkg.type: bsp
+pkg.description: BSP definition for the nucleo u575zi-q board.
+pkg.author: "Apache Mynewt <de...@mynewt.apache.org>"
+pkg.homepage: "http://mynewt.apache.org/"
+pkg.keywords:
+ - stm32
+ - stm32u5
+ - nucleo
+
+pkg.cflags: -DSTM32U575xx -DUSE_FULL_LL_DRIVER
+
+pkg.cflags.HARDFLOAT:
+ - -mfloat-abi=hard -mfpu=fpv4-sp-d16
+
+pkg.deps:
+ - "@apache-mynewt-core/hw/mcu/stm/stm32u5xx"
+ - "@apache-mynewt-core/libc/baselibc"
+ - "@apache-mynewt-core/hw/drivers/flash/spiflash"
+ - "@apache-mynewt-core/hw/bus/drivers/spi_hal"
diff --git a/hw/bsp/nucleo-u575zi-q/src/arch/cortex_m33/startup_stm32u575xx.s b/hw/bsp/nucleo-u575zi-q/src/arch/cortex_m33/startup_stm32u575xx.s
new file mode 100644
index 000000000..2d12e5506
--- /dev/null
+++ b/hw/bsp/nucleo-u575zi-q/src/arch/cortex_m33/startup_stm32u575xx.s
@@ -0,0 +1,691 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32u575xx.s
+ * @author MCD Application Team
+ * @brief STM32U575xx devices vector table GCC toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M33 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ *******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ *******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m33
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF1E0F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/*
+ * mynewt specific corebss clearing.
+ */
+ ldr r2, =__corebss_start__
+ b LoopFillZeroCoreBss
+
+/* Zero fill the bss segment. */
+FillZeroCoreBss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZeroCoreBss:
+ ldr r3, =__corebss_end__
+ cmp r2, r3
+ bcc FillZeroCoreBss
+
+ ldr r0, =__HeapBase
+ ldr r1, =__HeapLimit
+ bl _sbrkInit
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+/* Call the libc entry point.*/
+ bl _start
+
+LoopForever:
+ b LoopForever
+
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M33. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .globl __isr_vector
+__isr_vector:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word SecureFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_PVM_IRQHandler
+ .word RTC_IRQHandler
+ .word RTC_S_IRQHandler
+ .word TAMP_IRQHandler
+ .word RAMCFG_IRQHandler
+ .word FLASH_IRQHandler
+ .word FLASH_S_IRQHandler
+ .word GTZC_IRQHandler
+ .word RCC_IRQHandler
+ .word RCC_S_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word EXTI5_IRQHandler
+ .word EXTI6_IRQHandler
+ .word EXTI7_IRQHandler
+ .word EXTI8_IRQHandler
+ .word EXTI9_IRQHandler
+ .word EXTI10_IRQHandler
+ .word EXTI11_IRQHandler
+ .word EXTI12_IRQHandler
+ .word EXTI13_IRQHandler
+ .word EXTI14_IRQHandler
+ .word EXTI15_IRQHandler
+ .word IWDG_IRQHandler
+ .word 0
+ .word GPDMA1_Channel0_IRQHandler
+ .word GPDMA1_Channel1_IRQHandler
+ .word GPDMA1_Channel2_IRQHandler
+ .word GPDMA1_Channel3_IRQHandler
+ .word GPDMA1_Channel4_IRQHandler
+ .word GPDMA1_Channel5_IRQHandler
+ .word GPDMA1_Channel6_IRQHandler
+ .word GPDMA1_Channel7_IRQHandler
+ .word ADC1_IRQHandler
+ .word DAC1_IRQHandler
+ .word FDCAN1_IT0_IRQHandler
+ .word FDCAN1_IT1_IRQHandler
+ .word TIM1_BRK_IRQHandler
+ .word TIM1_UP_IRQHandler
+ .word TIM1_TRG_COM_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word TIM5_IRQHandler
+ .word TIM6_IRQHandler
+ .word TIM7_IRQHandler
+ .word TIM8_BRK_IRQHandler
+ .word TIM8_UP_IRQHandler
+ .word TIM8_TRG_COM_IRQHandler
+ .word TIM8_CC_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word UART4_IRQHandler
+ .word UART5_IRQHandler
+ .word LPUART1_IRQHandler
+ .word LPTIM1_IRQHandler
+ .word LPTIM2_IRQHandler
+ .word TIM15_IRQHandler
+ .word TIM16_IRQHandler
+ .word TIM17_IRQHandler
+ .word COMP_IRQHandler
+ .word OTG_FS_IRQHandler
+ .word CRS_IRQHandler
+ .word FMC_IRQHandler
+ .word OCTOSPI1_IRQHandler
+ .word PWR_S3WU_IRQHandler
+ .word SDMMC1_IRQHandler
+ .word SDMMC2_IRQHandler
+ .word GPDMA1_Channel8_IRQHandler
+ .word GPDMA1_Channel9_IRQHandler
+ .word GPDMA1_Channel10_IRQHandler
+ .word GPDMA1_Channel11_IRQHandler
+ .word GPDMA1_Channel12_IRQHandler
+ .word GPDMA1_Channel13_IRQHandler
+ .word GPDMA1_Channel14_IRQHandler
+ .word GPDMA1_Channel15_IRQHandler
+ .word I2C3_EV_IRQHandler
+ .word I2C3_ER_IRQHandler
+ .word SAI1_IRQHandler
+ .word SAI2_IRQHandler
+ .word TSC_IRQHandler
+ .word 0
+ .word RNG_IRQHandler
+ .word FPU_IRQHandler
+ .word HASH_IRQHandler
+ .word 0
+ .word LPTIM3_IRQHandler
+ .word SPI3_IRQHandler
+ .word I2C4_ER_IRQHandler
+ .word I2C4_EV_IRQHandler
+ .word MDF1_FLT0_IRQHandler
+ .word MDF1_FLT1_IRQHandler
+ .word MDF1_FLT2_IRQHandler
+ .word MDF1_FLT3_IRQHandler
+ .word UCPD1_IRQHandler
+ .word ICACHE_IRQHandler
+ .word 0
+ .word 0
+ .word LPTIM4_IRQHandler
+ .word DCACHE1_IRQHandler
+ .word ADF1_IRQHandler
+ .word ADC4_IRQHandler
+ .word LPDMA1_Channel0_IRQHandler
+ .word LPDMA1_Channel1_IRQHandler
+ .word LPDMA1_Channel2_IRQHandler
+ .word LPDMA1_Channel3_IRQHandler
+ .word DMA2D_IRQHandler
+ .word DCMI_PSSI_IRQHandler
+ .word OCTOSPI2_IRQHandler
+ .word MDF1_FLT4_IRQHandler
+ .word MDF1_FLT5_IRQHandler
+ .word CORDIC_IRQHandler
+ .word FMAC_IRQHandler
+
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SecureFault_Handler
+ .thumb_set SecureFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_PVM_IRQHandler
+ .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+ .weak RTC_IRQHandler
+ .thumb_set RTC_IRQHandler,Default_Handler
+
+ .weak RTC_S_IRQHandler
+ .thumb_set RTC_S_IRQHandler,Default_Handler
+
+ .weak TAMP_IRQHandler
+ .thumb_set TAMP_IRQHandler,Default_Handler
+
+ .weak RAMCFG_IRQHandler
+ .thumb_set RAMCFG_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak FLASH_S_IRQHandler
+ .thumb_set FLASH_S_IRQHandler,Default_Handler
+
+ .weak GTZC_IRQHandler
+ .thumb_set GTZC_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak RCC_S_IRQHandler
+ .thumb_set RCC_S_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak EXTI5_IRQHandler
+ .thumb_set EXTI5_IRQHandler,Default_Handler
+
+ .weak EXTI6_IRQHandler
+ .thumb_set EXTI6_IRQHandler,Default_Handler
+
+ .weak EXTI7_IRQHandler
+ .thumb_set EXTI7_IRQHandler,Default_Handler
+
+ .weak EXTI8_IRQHandler
+ .thumb_set EXTI8_IRQHandler,Default_Handler
+
+ .weak EXTI9_IRQHandler
+ .thumb_set EXTI9_IRQHandler,Default_Handler
+
+ .weak EXTI10_IRQHandler
+ .thumb_set EXTI10_IRQHandler,Default_Handler
+
+ .weak EXTI11_IRQHandler
+ .thumb_set EXTI11_IRQHandler,Default_Handler
+
+ .weak EXTI12_IRQHandler
+ .thumb_set EXTI12_IRQHandler,Default_Handler
+
+ .weak EXTI13_IRQHandler
+ .thumb_set EXTI13_IRQHandler,Default_Handler
+
+ .weak EXTI14_IRQHandler
+ .thumb_set EXTI14_IRQHandler,Default_Handler
+
+ .weak EXTI15_IRQHandler
+ .thumb_set EXTI15_IRQHandler,Default_Handler
+
+ .weak IWDG_IRQHandler
+ .thumb_set IWDG_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel0_IRQHandler
+ .thumb_set GPDMA1_Channel0_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel1_IRQHandler
+ .thumb_set GPDMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel2_IRQHandler
+ .thumb_set GPDMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel3_IRQHandler
+ .thumb_set GPDMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel4_IRQHandler
+ .thumb_set GPDMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel5_IRQHandler
+ .thumb_set GPDMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel6_IRQHandler
+ .thumb_set GPDMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel7_IRQHandler
+ .thumb_set GPDMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_IRQHandler
+ .thumb_set ADC1_IRQHandler,Default_Handler
+
+ .weak DAC1_IRQHandler
+ .thumb_set DAC1_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT0_IRQHandler
+ .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT1_IRQHandler
+ .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak TIM6_IRQHandler
+ .thumb_set TIM6_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_IRQHandler
+ .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_IRQHandler
+ .thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_IRQHandler
+ .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak COMP_IRQHandler
+ .thumb_set COMP_IRQHandler,Default_Handler
+
+ .weak OTG_FS_IRQHandler
+ .thumb_set OTG_FS_IRQHandler,Default_Handler
+
+ .weak CRS_IRQHandler
+ .thumb_set CRS_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak OCTOSPI1_IRQHandler
+ .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+ .weak PWR_S3WU_IRQHandler
+ .thumb_set PWR_S3WU_IRQHandler,Default_Handler
+
+ .weak SDMMC1_IRQHandler
+ .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+ .weak SDMMC2_IRQHandler
+ .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel8_IRQHandler
+ .thumb_set GPDMA1_Channel8_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel9_IRQHandler
+ .thumb_set GPDMA1_Channel9_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel10_IRQHandler
+ .thumb_set GPDMA1_Channel10_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel11_IRQHandler
+ .thumb_set GPDMA1_Channel11_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel12_IRQHandler
+ .thumb_set GPDMA1_Channel12_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel13_IRQHandler
+ .thumb_set GPDMA1_Channel13_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel14_IRQHandler
+ .thumb_set GPDMA1_Channel14_IRQHandler,Default_Handler
+
+ .weak GPDMA1_Channel15_IRQHandler
+ .thumb_set GPDMA1_Channel15_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak SAI2_IRQHandler
+ .thumb_set SAI2_IRQHandler,Default_Handler
+
+ .weak TSC_IRQHandler
+ .thumb_set TSC_IRQHandler,Default_Handler
+
+ .weak RNG_IRQHandler
+ .thumb_set RNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak HASH_IRQHandler
+ .thumb_set HASH_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak I2C4_ER_IRQHandler
+ .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+ .weak I2C4_EV_IRQHandler
+ .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+ .weak MDF1_FLT0_IRQHandler
+ .thumb_set MDF1_FLT0_IRQHandler,Default_Handler
+
+ .weak MDF1_FLT1_IRQHandler
+ .thumb_set MDF1_FLT1_IRQHandler,Default_Handler
+
+ .weak MDF1_FLT2_IRQHandler
+ .thumb_set MDF1_FLT2_IRQHandler,Default_Handler
+
+ .weak MDF1_FLT3_IRQHandler
+ .thumb_set MDF1_FLT3_IRQHandler,Default_Handler
+
+ .weak UCPD1_IRQHandler
+ .thumb_set UCPD1_IRQHandler,Default_Handler
+
+ .weak ICACHE_IRQHandler
+ .thumb_set ICACHE_IRQHandler,Default_Handler
+
+ .weak LPTIM4_IRQHandler
+ .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+ .weak DCACHE1_IRQHandler
+ .thumb_set DCACHE1_IRQHandler,Default_Handler
+
+ .weak ADF1_IRQHandler
+ .thumb_set ADF1_IRQHandler,Default_Handler
+
+ .weak ADC4_IRQHandler
+ .thumb_set ADC4_IRQHandler,Default_Handler
+
+ .weak LPDMA1_Channel0_IRQHandler
+ .thumb_set LPDMA1_Channel0_IRQHandler,Default_Handler
+
+ .weak LPDMA1_Channel1_IRQHandler
+ .thumb_set LPDMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak LPDMA1_Channel2_IRQHandler
+ .thumb_set LPDMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak LPDMA1_Channel3_IRQHandler
+ .thumb_set LPDMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2D_IRQHandler
+ .thumb_set DMA2D_IRQHandler,Default_Handler
+
+ .weak DCMI_PSSI_IRQHandler
+ .thumb_set DCMI_PSSI_IRQHandler,Default_Handler
+
+ .weak OCTOSPI2_IRQHandler
+ .thumb_set OCTOSPI2_IRQHandler,Default_Handler
+
+ .weak MDF1_FLT4_IRQHandler
+ .thumb_set MDF1_FLT4_IRQHandler,Default_Handler
+
+ .weak MDF1_FLT5_IRQHandler
+ .thumb_set MDF1_FLT5_IRQHandler,Default_Handler
+
+ .weak CORDIC_IRQHandler
+ .thumb_set CORDIC_IRQHandler,Default_Handler
+
+ .weak FMAC_IRQHandler
+ .thumb_set FMAC_IRQHandler,Default_Handler
+
+
diff --git a/hw/bsp/nucleo-u575zi-q/src/hal_bsp.c b/hw/bsp/nucleo-u575zi-q/src/hal_bsp.c
new file mode 100644
index 000000000..f8517bd56
--- /dev/null
+++ b/hw/bsp/nucleo-u575zi-q/src/hal_bsp.c
@@ -0,0 +1,251 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include <assert.h>
+
+#include "bsp/bsp.h"
+#include "os/mynewt.h"
+#include "spiflash/spiflash.h"
+
+#include <hal/hal_bsp.h>
+#include <hal/hal_flash_int.h>
+#include <hal/hal_system.h>
+
+#include <stm32u5xx.h>
+#include <stm32_common/stm32_hal.h>
+#include <bus/drivers/spi_common.h>
+
+#if MYNEWT_VAL(ETH_0)
+#include <stm32_eth/stm32_eth.h>
+#include <stm32_eth/stm32_eth_cfg.h>
+#endif
+
+#if MYNEWT_VAL(PWM_0) || MYNEWT_VAL(PWM_1) || MYNEWT_VAL(PWM_2)
+#include <pwm_stm32/pwm_stm32.h>
+#endif
+
+#if MYNEWT_VAL(PWM_0)
+struct stm32_pwm_conf os_bsp_pwm0_cfg = {
+ .tim = TIM3,
+ .irq = TIM3_IRQn,
+};
+#endif
+#if MYNEWT_VAL(PWM_1)
+struct stm32_pwm_conf os_bsp_pwm1_cfg = {
+ .tim = TIM4,
+ .irq = TIM4_IRQn,
+};
+#endif
+#if MYNEWT_VAL(PWM_2)
+struct stm32_pwm_conf os_bsp_pwm2_cfg = {
+ .tim = TIM11,
+ .irq = TIM1_TRG_COM_TIM11_IRQn,
+};
+#endif
+
+#if MYNEWT_VAL(UART_0)
+const struct stm32_uart_cfg os_bsp_uart0_cfg = {
+ .suc_uart = USART1,
+ .suc_rcc_reg = &RCC->APB2ENR,
+ .suc_rcc_dev = RCC_APB2ENR_USART1EN,
+ .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS),
+ .suc_pin_af = GPIO_AF7_USART1,
+ .suc_irqn = USART1_IRQn,
+};
+#endif
+
+#if MYNEWT_VAL(UART_1)
+const struct stm32_uart_cfg os_bsp_uart1_cfg = {
+ .suc_uart = USART2,
+ .suc_rcc_reg = &RCC->APB1ENR1,
+ .suc_rcc_dev = RCC_APB1ENR1_USART2EN,
+ .suc_pin_tx = MYNEWT_VAL(UART_1_PIN_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_1_PIN_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_1_PIN_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_1_PIN_CTS),
+ .suc_pin_af = GPIO_AF7_USART2,
+ .suc_irqn = USART2_IRQn,
+};
+#endif
+
+#if MYNEWT_VAL(I2C_0)
+/*
+ * The PB8 and PB9 pins are connected through jumpers in the board to
+ * both ADC_IN and I2C pins. To enable I2C functionality SB147/SB157 need
+ * to be removed (they are the default connections) and SB138/SB143 need
+ * to be shorted.
+ */
+const struct stm32_hal_i2c_cfg os_bsp_i2c0_cfg = {
+ .hic_i2c = I2C1,
+ .hic_rcc_reg = &RCC->APB1ENR,
+ .hic_rcc_dev = RCC_APB1ENR_I2C1EN,
+ .hic_pin_sda = MYNEWT_VAL(I2C_0_PIN_SDA),
+ .hic_pin_scl = MYNEWT_VAL(I2C_0_PIN_SCL),
+ .hic_pin_af = GPIO_AF4_I2C1,
+ .hic_10bit = 0,
+ .hic_timingr = 0x20404768, /* 100kHz at 216 MHz system clock */
+};
+#endif
+
+#if MYNEWT_VAL(I2C_1)
+const struct stm32_hal_i2c_cfg os_bsp_i2c1_cfg = {
+ .hic_i2c = I2C2,
+ .hic_rcc_reg = &RCC->APB1ENR,
+ .hic_rcc_dev = RCC_APB1ENR_I2C2EN,
+ .hic_pin_sda = MYNEWT_VAL(I2C_1_PIN_SDA),
+ .hic_pin_scl = MYNEWT_VAL(I2C_1_PIN_SCL),
+ .hic_pin_af = GPIO_AF4_I2C2,
+ .hic_10bit = 0,
+ .hic_timingr = 0x20404768, /* 100kHz at 216 MHz system clock */
+};
+#endif
+
+#if MYNEWT_VAL(I2C_2)
+const struct stm32_hal_i2c_cfg os_bsp_i2c2_cfg = {
+ .hic_i2c = I2C3,
+ .hic_rcc_reg = &RCC->APB1ENR,
+ .hic_rcc_dev = RCC_APB1ENR_I2C3EN,
+ .hic_pin_sda = MYNEWT_VAL(I2C_2_PIN_SDA),
+ .hic_pin_scl = MYNEWT_VAL(I2C_2_PIN_SCL),
+ .hic_pin_af = GPIO_AF4_I2C3,
+ .hic_10bit = 0,
+ .hic_timingr = 0x20404768, /* 100kHz at 216 MHz system clock */
+};
+#endif
+
+#if MYNEWT_VAL(I2C_3)
+const struct stm32_hal_i2c_cfg os_bsp_i2c3_cfg = {
+ .hic_i2c = I2C4,
+ .hic_rcc_reg = &RCC->APB1ENR,
+ .hic_rcc_dev = RCC_APB1ENR_I2C4EN,
+ .hic_pin_sda = MYNEWT_VAL(I2C_3_PIN_SDA),
+ .hic_pin_scl = MYNEWT_VAL(I2C_3_PIN_SCL),
+ .hic_pin_af = GPIO_AF4_I2C4,
+ .hic_10bit = 0,
+ .hic_timingr = 0x20404768, /* 100kHz at 216 MHz system clock */
+};
+#endif
+
+/* FIXME */
+static const struct hal_bsp_mem_dump dump_cfg[] = {
+ [0] = {
+ .hbmd_start = &_ram_start,
+ .hbmd_size = RAM_SIZE,
+ },
+};
+
+extern const struct hal_flash stm32_flash_dev;
+
+#if MYNEWT_VAL(SPIFLASH)
+#if MYNEWT_VAL(BUS_DRIVER_PRESENT)
+struct bus_spi_node_cfg flash_spi_cfg = {
+ .node_cfg.bus_name = MYNEWT_VAL(BSP_FLASH_SPI_BUS),
+ .pin_cs = MYNEWT_VAL(SPIFLASH_SPI_CS_PIN),
+ .mode = BUS_SPI_MODE_0,
+ .data_order = HAL_SPI_MSB_FIRST,
+ .freq = MYNEWT_VAL(SPIFLASH_BAUDRATE),
+};
+#endif
+#endif
+
+static const struct hal_flash *flash_devs[] = {
+ [0] = &stm32_flash_dev,
+#if MYNEWT_VAL(SPIFLASH)
+ [1] = &spiflash_dev.hal,
+#endif
+};
+
+const struct hal_flash *
+hal_bsp_flash_dev(uint8_t id)
+{
+ if (id >= ARRAY_SIZE(flash_devs)) {
+ return NULL;
+ }
+
+ return flash_devs[id];
+}
+
+const struct hal_bsp_mem_dump *
+hal_bsp_core_dump(int *area_cnt)
+{
+ *area_cnt = sizeof(dump_cfg) / sizeof(dump_cfg[0]);
+ return dump_cfg;
+}
+
+void
+hal_bsp_init(void)
+{
+ int rc;
+ (void)rc;
+
+ stm32_periph_create();
+
+#if MYNEWT_VAL(SPIFLASH) && MYNEWT_VAL(BUS_DRIVER_PRESENT)
+ rc = spiflash_create_spi_dev(&spiflash_dev.dev,
+ MYNEWT_VAL(BSP_FLASH_SPI_NAME), &flash_spi_cfg);
+ assert(rc == 0);
+#endif
+}
+
+void
+hal_bsp_deinit(void)
+{
+ RCC->AHB1ENR = 0xD0000100;
+ RCC->AHB2ENR1 = 0xC0000000;
+ RCC->AHB2ENR2 = 0;
+ RCC->AHB3ENR = 0x80000000;
+ RCC->APB1ENR1 = 0;
+ RCC->APB1ENR2 = 0;
+ RCC->APB3ENR = 0;
+
+ RCC->AHB1RSTR = 0x0007100F;
+ RCC->AHB2RSTR1 = 0x19BF55FF;
+ RCC->AHB2RSTR2 = 0x00000111;
+ RCC->AHB3RSTR = 0x00000661;
+ RCC->APB1RSTR1 = 0x017E403F;
+ RCC->APB1RSTR2 = 0x00800222;
+ RCC->APB2RSTR = 0x00677800;
+ RCC->APB3RSTR = 0x0010F8E2;
+ RCC->AHB1RSTR = 0;
+ RCC->AHB2RSTR1 = 0;
+ RCC->AHB2RSTR2 = 0;
+ RCC->AHB3RSTR = 0;
+ RCC->APB1RSTR1 = 0;
+ RCC->APB1RSTR2 = 0;
+ RCC->APB2RSTR = 0;
+ RCC->APB3RSTR = 0;
+}
+
+/**
+ * Returns the configured priority for the given interrupt. If no priority
+ * configured, return the priority passed in
+ *
+ * @param irq_num
+ * @param pri
+ *
+ * @return uint32_t
+ */
+uint32_t
+hal_bsp_get_nvic_priority(int irq_num, uint32_t pri)
+{
+ /* Add any interrupt priorities configured by the bsp here */
+ return pri;
+}
diff --git a/hw/bsp/nucleo-u575zi-q/syscfg.yml b/hw/bsp/nucleo-u575zi-q/syscfg.yml
new file mode 100644
index 000000000..d94d73568
--- /dev/null
+++ b/hw/bsp/nucleo-u575zi-q/syscfg.yml
@@ -0,0 +1,75 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+syscfg.defs:
+ STM32_FLASH_SIZE_KB:
+ description: 'Total flash size in KB.'
+ value: 2048
+
+ BSP_FLASH_SPI_BUS:
+ description: 'bus name SPIFLASH is connected to'
+ value: '"spi0"'
+
+ BSP_FLASH_SPI_NAME:
+ description: 'SPIFLASH device name'
+ value: '"spiflash0"'
+
+syscfg.vals:
+ REBOOT_LOG_FLASH_AREA: FLASH_AREA_REBOOT_LOG
+ CONFIG_FCB_FLASH_AREA: FLASH_AREA_NFFS
+ NFFS_FLASH_AREA: FLASH_AREA_NFFS
+ COREDUMP_FLASH_AREA: FLASH_AREA_IMAGE_1
+ STM32_CLOCK_VOLTAGESCALING_CONFIG: 'PWR_REGULATOR_VOLTAGE_SCALE1'
+ STM32_CLOCK_HSI: 1
+ STM32_CLOCK_HSE: 0
+ STM32_CLOCK_HSE_BYPASS: 0
+ STM32_CLOCK_PLL_PLLM: 1
+ STM32_CLOCK_PLL_PLLN: 80
+ STM32_CLOCK_PLL_PLLP: 2
+ STM32_CLOCK_PLL_PLLQ: 2
+ STM32_CLOCK_PLL_PLLR: 2
+ STM32_CLOCK_ENABLE_OVERDRIVE: 0
+ STM32_CLOCK_AHB_DIVIDER: 'RCC_SYSCLK_DIV1'
+ STM32_CLOCK_APB1_DIVIDER: 'RCC_HCLK_DIV1'
+ STM32_CLOCK_APB2_DIVIDER: 'RCC_HCLK_DIV1'
+ STM32_CLOCK_APB3_DIVIDER: 'RCC_HCLK_DIV1'
+ STM32_CLOCK_APB4_DIVIDER: 'RCC_HCLK_DIV1'
+ STM32_CLOCK_PLLRGE: 'RCC_PLLVCIRANGE_0'
+ STM32_FLASH_LATENCY: 'FLASH_LATENCY_4'
+ UART_0_PIN_TX: 'MCU_GPIO_PORTA(9)'
+ UART_0_PIN_RX: 'MCU_GPIO_PORTA(10)'
+ UART_1_PIN_TX: 'MCU_GPIO_PORTD(5)'
+ UART_1_PIN_RX: 'MCU_GPIO_PORTD(6)'
+ UART_1_PIN_RTS: 'MCU_GPIO_PORTD(4)'
+ UART_1_PIN_CTS: 'MCU_GPIO_PORTD(3)'
+ SPI_0_PIN_SS: 'MCU_GPIO_PORTD(14)'
+ SPI_0_PIN_SCK: ARDUINO_PIN_SCK
+ SPI_0_PIN_MISO: ARDUINO_PIN_MISO
+ SPI_0_PIN_MOSI: ARDUINO_PIN_MOSI
+ I2C_0_PIN_SCL: 'MCU_GPIO_PORTB(8)'
+ I2C_0_PIN_SDA: 'MCU_GPIO_PORTB(9)'
+ I2C_1_PIN_SCL: 'MCU_GPIO_PORTF(1)'
+ I2C_1_PIN_SDA: 'MCU_GPIO_PORTF(0)'
+ I2C_2_PIN_SCL: 'MCU_GPIO_PORTA(8)'
+ I2C_2_PIN_SDA: 'MCU_GPIO_PORTC(9)'
+ I2C_3_PIN_SCL: 'MCU_GPIO_PORTD(12)'
+ I2C_3_PIN_SDA: 'MCU_GPIO_PORTD(13)'
+ TIMER_0_TIM: 'TIM15'
+ TIMER_1_TIM: 'TIM16'
+ TIMER_2_TIM: 'TIM17'