[GitHub] [tvm] giuseros commented on pull request #6971: [Hardware][Verilator] Integrating and simulating hardware accelerators in TVM

[GitBox <gi...@apache.org>]

giuseros commented on pull request #6971:
URL: https://github.com/apache/tvm/pull/6971#issuecomment-733654476


   Hi @vegaluisjose , 
   
   This looks very interesting! I would suggest to move the RFC discussion in https://discuss.tvm.apache.org/. Meanwhile, let me double check I understood the design. So, the idea is: 
   a) Write Verilog
   b) Compile (e.g., with Verilator) in a C++ Cycle Accurate Model
   c) Link that model into TVM
   You are using BYOC so that you can split your graph on the operations you want, and offload the one you decided to support (potentially, the entire graph) to the C++ model. Is my understanding correct?
   
   Two questions:
   a) How hard is to open a route in TIR for this (to test smaller hw parts)? In theory `call_extern` should be sufficient? 
   b) Why adding `hw-widgets` as a dependency? IIUC this is just an example, right?
   
   
   


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