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Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2022/01/11 18:33:34 UTC
[GitHub] [incubator-nuttx] acassis commented on a change in pull request #5206: stm32: add FDCAN support
acassis commented on a change in pull request #5206:
URL: https://github.com/apache/incubator-nuttx/pull/5206#discussion_r782419571
##########
File path: arch/arm/src/stm32/hardware/stm32_fdcan.h
##########
@@ -0,0 +1,586 @@
+/****************************************************************************
+ * arch/arm/src/stm32/hardware/stm32_fdcan.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FDCAN_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FDCAN_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Only for STM32G4 */
+
+#ifndef CONFIG_STM32_STM32G4XXX
+# error Not tested
Review comment:
Please make the error message more clear, i.e.: "Currently STM32 FDCAN driver only was tested for STM32G4 family".
##########
File path: arch/arm/src/stm32/hardware/stm32_fdcan.h
##########
@@ -0,0 +1,586 @@
+/****************************************************************************
+ * arch/arm/src/stm32/hardware/stm32_fdcan.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FDCAN_H
+#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FDCAN_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Only for STM32G4 */
+
+#ifndef CONFIG_STM32_STM32G4XXX
+# error Not tested
+#endif
+
+/* Register Offsets *********************************************************/
+
+#define STM32_FDCAN_CREL_OFFSET 0x0000 /* FDCAN core release register */
+#define STM32_FDCAN_ENDN_OFFSET 0x0004 /* FDCAN endian register */
+ /* 0x0008 Reserved */
+#define STM32_FDCAN_DBTP_OFFSET 0x000c /* FDCAN data bit timing and prescaler register */
+#define STM32_FDCAN_TEST_OFFSET 0x0010 /* FDCAN test register */
+#define STM32_FDCAN_RWD_OFFSET 0x0014 /* FDCAN RAM watchdog register */
+#define STM32_FDCAN_CCCR_OFFSET 0x0018 /* FDCAN CC control register */
+#define STM32_FDCAN_NBTP_OFFSET 0x001c /* FDCAN nominal bit timing and prescaler register */
+#define STM32_FDCAN_TSCC_OFFSET 0x0020 /* FDCAN timestamp counter configuration register */
+#define STM32_FDCAN_TSCV_OFFSET 0x0024 /* FDCAN timestamp counter value register */
+#define STM32_FDCAN_TOCC_OFFSET 0x0028 /* FDCAN timeout counter configuration register */
+#define STM32_FDCAN_TOCV_OFFSET 0x002c /* FDCAN timeout counter value register */
+ /* 0x0030 to 0x003c Reserved */
+#define STM32_FDCAN_ECR_OFFSET 0x0040 /* FDCAN error counter register */
+#define STM32_FDCAN_PSR_OFFSET 0x0044 /* FDCAN protocol status register */
+#define STM32_FDCAN_TDCR_OFFSET 0x0048 /* FDCAN transmitter delay compensation register */
+ /* 0x004c Reserved */
+#define STM32_FDCAN_IR_OFFSET 0x0050 /* FDCAN interrupt register */
+#define STM32_FDCAN_IE_OFFSET 0x0054 /* FDCAN interrupt enable register */
+#define STM32_FDCAN_ILS_OFFSET 0x0058 /* FDCAN interrupt line select register */
+#define STM32_FDCAN_ILE_OFFSET 0x005c /* FDCAN interrupt line enable register */
+ /* 0x0060 to 0x007c Reserved */
+#define STM32_FDCAN_RXGFC_OFFSET 0x0080 /* FDCAN global filter configuration register */
+#define STM32_FDCAN_XIDAM_OFFSET 0x0084 /* FDCAN extended ID and mask register */
+#define STM32_FDCAN_HPMS_OFFSET 0x0088 /* FDCAN high-priority message status register */
+#define STM32_FDCAN_RXFS_OFFSET(f) (0x0090 + ((f) << 3)
+#define STM32_FDCAN_RXFA_OFFSET(f) (0x0094 + ((f) << 3)
+#define STM32_FDCAN_RXF0S_OFFSET 0x0090 /* FDCAN Rx FIFO 0 status register */
+#define STM32_FDCAN_RXF0A_OFFSET 0x0094 /* CAN Rx FIFO 0 acknowledge register */
+#define STM32_FDCAN_RXF1S_OFFSET 0x0098 /* FDCAN Rx FIFO 1 status register */
+#define STM32_FDCAN_RXF1A_OFFSET 0x009c /* FDCAN Rx FIFO 1 acknowledge register */
+ /* 0x00a0 to 0x00bc Reserved */
+#define STM32_FDCAN_TXBC_OFFSET 0x00c0 /* FDCAN Tx buffer configuration register */
+#define STM32_FDCAN_TXFQS_OFFSET 0x00c4 /* FDCAN Tx FIFO/queue status register */
+#define STM32_FDCAN_TXBRP_OFFSET 0x00c8 /* FDCAN Tx buffer request pending register */
+#define STM32_FDCAN_TXBAR_OFFSET 0x00cc /* FDCAN Tx buffer add request register */
+#define STM32_FDCAN_TXBCR_OFFSET 0x00d0 /* FDCAN Tx buffer cancellation request register */
+#define STM32_FDCAN_TXBTO_OFFSET 0x00d4 /* FDCAN Tx buffer transmission occurred register */
+#define STM32_FDCAN_TXBCNF_OFFSET 0x00d8 /* FDCAN Tx buffer cancellation finished register */
+#define STM32_FDCAN_TXBTIE_OFFSET 0x00dc /* FDCAN Tx buffer transmission interrupt enable register */
+#define STM32_FDCAN_TXBCIE_OFFSET 0x00e0 /* FDCAN Tx buffer cancellation finished interrupt enable register */
+#define STM32_FDCAN_TXEFS_OFFSET 0x00e4 /* FDCAN Tx event FIFO status register */
+#define STM32_FDCAN_TXEFA_OFFSET 0x00e8 /* FDCAN Tx event FIFO acknowledge register */
+#define STM32_FDCAN_CKDIV_OFFSET 0x0100 /* FDCAN CFG clock divider register */
+
+/* Register Bitfield Definitions ********************************************/
+
+/* FDCAN core release register */
+
+#define FDCAN_CREL_DAY_SHIFT (0) /* Bits 0-7: DAY */
+#define FDCAN_CREL_DAY_MASK (0xff << FDCAN_CREL_DAY_SHIFT)
+#define FDCAN_CREL_MON_SHIFT (8) /* Bits 8-15: MON */
+#define FDCAN_CREL_MON_MASK (0xff << FDCAN_CREL_MON_SHIFT)
+#define FDCAN_CREL_YEAR_SHIFT (16) /* Bits 8-15: YEAR */
+#define FDCAN_CREL_YEAR_MASK (0x0f << FDCAN_CREL_YEAR_SHIFT)
+#define FDCAN_CREL_SUBSTEP_SHIFT (20) /* Bits 20-23: SUBSTEP */
+#define FDCAN_CREL_SUBSTEP_MASK (0x0f << FDCAN_CREL_SUBSTEP_SHIFT)
+#define FDCAN_CREL_STEP_SHIFT (24) /* Bits 24-27: STEP */
+#define FDCAN_CREL_STEP_MASK (0x0f << FDCAN_CREL_STEP_SHIFT)
+#define FDCAN_CREL_REL_SHIFT (28) /* Bits 28-31: REL */
+#define FDCAN_CREL_REL_MASK (0x0f << FDCAN_CREL_REL_SHIFT)
+
+/* FDCAN data bit timing and prescaler register */
+
+#define FDCAN_DBTP_DSJW_SHIFT (0) /* Bits 0-3: Synchronization jump width */
+#define FDCAN_DBTP_DSJW_MASK (0x0f << FDCAN_DBTP_DSJW_SHIFT)
+# define FDCAN_DBTP_DSJW(value) ((value) << FDCAN_DBTP_DSJW_SHIFT)
+# define FDCAN_DBTP_DSJW_MAX (15)
+#define FDCAN_DBTP_DTSEG2_SHIFT (4) /* Bits 4-7: Data time segment after sample point*/
+#define FDCAN_DBTP_DTSEG2_MASK (0x0f << FDCAN_DBTP_DTSEG2_SHIFT)
+# define FDCAN_DBTP_DTSEG2(value) ((value) << FDCAN_DBTP_DTSEG2_SHIFT)
+# define FDCAN_DBTP_DTSEG2_MAX (15)
+#define FDCAN_DBTP_DTSEG1_SHIFT (8) /* Bits 8-12: Data time segment before sample point*/
+#define FDCAN_DBTP_DTSEG1_MASK (0x1f << FDCAN_DBTP_DTSEG1_SHIFT)
+# define FDCAN_DBTP_DTSEG1(value) ((value) << FDCAN_DBTP_DTSEG1_SHIFT)
+# define FDCAN_DBTP_DTSEG1_MAX (31)
+#define FDCAN_DBTP_DBRP_SHIFT (16) /* Bits 16-20: Data bitrate prescaler */
+#define FDCAN_DBTP_DBRP_MASK (0x1f << FDCAN_DBTP_DBRP_SHIFT)
+# define FDCAN_DBTP_DBRP(value) ((value) << FDCAN_DBTP_DBRP_SHIFT)
+# define FDCAN_DBTP_DBRP_MAX (31)
+#define FDCAN_DBTP_TDC_EN (1 << 23) /* Bit 23: Transceiver delay compensation enable */
+
+/* FDCAN test register */
+
+#define FDCAN_TEST_LBCK (1 << 4) /* Bit 4: Loop back mode */
+#define FDCAN_TEST_TX_SHIFT (5) /* Bits 5-6: Control of transmit pin */
+#define FDCAN_TEST_TX_MASK (0x3 << FDCAN_TEST_TX_SHIFT)
+# define FDCAN_TEST_TX_RESET (0 << FDCAN_TEST_TX_SHIFT) /* 00: TX is controlled by CAN core */
+# define FDCAN_TEST_TX_SP (1 << FDCAN_TEST_TX_SHIFT) /* 01: Sample point can be monitored at TX pin */
+# define FDCAN_TEST_TX_DLVL (2 << FDCAN_TEST_TX_SHIFT) /* 10: Dominant (0) level at TX pin */
+# define FDCAN_TEST_TX_RLVL (3 << FDCAN_TEST_TX_SHIFT) /* 11: Recesive (1) level at TX pin */
+#define FDCAN_TEST_RX (1 << 7) /* Bit 7: Receive pin */
+
+/* FDCAN RAM watchdog register */
+
+#define FDCAN_RWD_WDC_SHIFT (0) /* Bits 0-7: RAM watchdog counter start value */
+#define FDCAN_RWD_WDC_MASK (0xff << FDCAN_RWD_WDC_SHIFT)
+# define FDCAN_RWD_WDC_DIS (0 << FDCAN_RWD_WDC_SHIFT) /* Counter disabled */
+# define FDCAN_RWD_WDC(value) ((value) << FDCAN_RWD_WDC_SHIFT)
+#define FDCAN_RWD_WDV_SHIFT (8) /* Bits 8-15: RAM watchdog counter value */
+#define FDCAN_RWD_WDV_MASK (0xff << FDCAN_RWD_WDV_SHIFT)
+
+/* FDCAN CC control register */
+
+#define FDCAN_CCCR_INIT (1 << 0) /* Bit 0: Initialization */
+#define FDCAN_CCCR_CCE (1 << 1) /* Bit 1: Configuration change enable */
+#define FDCAN_CCCR_ASM (1 << 2) /* Bit 2: ASM restricted operation mode */
+#define FDCAN_CCCR_CSA (1 << 3) /* Bit 3: Clock stop acknowledge */
+#define FDCAN_CCCR_CSR (1 << 4) /* Bit 4: Clock stop request */
+#define FDCAN_CCCR_MON (1 << 5) /* Bit 5: Bus monitoring mode */
+#define FDCAN_CCCR_DAR (1 << 6) /* Bit 6: Disable automatic retransmission */
+#define FDCAN_CCCR_TEST (1 << 7) /* Bit 7: Test mode enable */
+#define FDCAN_CCCR_FDOE (1 << 8) /* Bit 8: FD operation enable */
+#define FDCAN_CCCR_BRSE (1 << 9) /* Bit 9: FDCAN Bitrate switching */
+ /* Bits 10-11: Reserved */
+#define FDCAN_CCCR_PXHD (1 << 12) /* Bit 12: Protocol exception handling disable */
+#define FDCAN_CCCR_EFBI (1 << 13) /* Bit 13: Edge filtering during bus integration */
+#define FDCAN_CCCR_TXP (1 << 14) /* Bit 14: Tx pause */
+#define FDCAN_CCCR_NISO (1 << 15) /* Bit 15: Non ISO operation */
+
+/* FDCAN nominal bit timing and prescaler register */
+
+#define FDCAN_NBTP_NTSEG2_SHIFT (0) /* Bits 0-6: Nominal time segment after sample point */
+#define FDCAN_NBTP_NTSEG2_MASK (0x7f << FDCAN_NBTP_NTSEG2_SHIFT)
+# define FDCAN_NBTP_NTSEG2(value) ((value) << FDCAN_NBTP_NTSEG2_SHIFT)
+# define FDCAN_NBTP_NTSEG2_MAX (127)
+#define FDCAN_NBTP_NTSEG1_SHIFT (8) /* Bits 8-15: Nominal time segment before sample point */
+#define FDCAN_NBTP_NTSEG1_MASK (0xff << FDCAN_NBTP_NTSEG1_SHIFT)
+# define FDCAN_NBTP_NTSEG1(value) ((value) << FDCAN_NBTP_NTSEG1_SHIFT)
+# define FDCAN_NBTP_NTSEG1_MAX (255)
+#define FDCAN_NBTP_NBRP_SHIFT (16) /* Bits 16-24: Bitrate prescaler */
+#define FDCAN_NBTP_NBRP_MASK (0x1ff << FDCAN_NBTP_NBRP_SHIFT)
+# define FDCAN_NBTP_NBRP(value) ((value) << FDCAN_NBTP_NBRP_SHIFT)
+# define FDCAN_NBTP_NBRP_MAX (511)
+#define FDCAN_NBTP_NSJW_SHIFT (25) /* Bits 25-31: Nominal (re)synchronization jump width */
+#define FDCAN_NBTP_NSJW_MASK (0x7f << FDCAN_NBTP_NSJW_SHIFT)
+# define FDCAN_NBTP_NSJW(value) ((value) << FDCAN_NBTP_NSJW_SHIFT)
+# define FDCAN_NBTP_NSJW_MAX (127)
+
+/* FDCAN timestamp counter configuration register */
+
+#define FDCAN_TSCC_TSS_SHIFT (0) /* Bits 0-1: Timestamp counter select */
+#define FDCAN_TSCC_TSS_MASK (0x3 << FDCAN_TSCC_TSS_SHIFT)
+# define FDCAN_TSCC_TSS_ZERO (0 << FDCAN_TSCC_TSS_SHIFT) /* 00: Always 0 */
+# define FDCAN_TSCC_TSS_TCP (1 << FDCAN_TSCC_TSS_SHIFT) /* 01: Incremented based on TCP */
+# define FDCAN_TSCC_TSS_TIM3 (2 << FDCAN_TSCC_TSS_SHIFT) /* 10: Value from TIM3 used */
+#define FDCAN_TSCC_TCP_SHIFT (16) /* Bits 16-19: Timestamp counter prescaler */
+#define FDCAN_TSCC_TCP_MASK (0x0f << FDCAN_TSCC_TCP_SHIFT)
+# define FDCAN_TSCC_TCP(value) ((value) << FDCAN_TSCC_TCP_SHIFT)
+
+/* FDCAN timestamp counter value register */
+
+#define FDCAN_TSCV_TSC_SHIFT (0) /* Bits 0-15: Timestamp counter */
+#define FDCAN_TSCV_TSC_MASK (0xffff << FDCAN_TSCV_TSC_SHIFT)
+
+/* FDCAN timeout counter configuration register */
+
+#define FDCAN_TOCC_ETOC (1 << 0) /* Bit 0: Enable timeout counter */
+#define FDCAN_TOCC_TOS_SHIFT (1) /* Bits 1-2: Timeout select */
+#define FDCAN_TOCC_TOS_MASK (0x03 << FDCAN_TOCC_TOS_SHIFT)
+# define FDCAN_TOCC_TOS_CONT (0 << FDCAN_TOCC_TOS_SHIFT) /* 00: Continuous operation */
+# define FDCAN_TOCC_TOS_TXFIFO (1 << FDCAN_TOCC_TOS_SHIFT) /* 01: Tx event FIFO */
+# define FDCAN_TOCC_TOS_RX_FIFO0 (2 << FDCAN_TOCC_TOS_SHIFT) /* 10: Rx FIFO 0 */
+# define FDCAN_TOCC_TOS_RX_FIFO1 (3 << FDCAN_TOCC_TOS_SHIFT) /* 11: Rx FIFO 1 */
+#define FDCAN_TOCC_TOP_SHIFT (16) /* Bits 16-31: Timeout period counter start value */
+#define FDCAN_TOCC_TOP_MASK (0xffff << FDCAN_TOCC_TOP_SHIFT)
+# define FDCAN_TOCC_TOP(value) ((value) << FDCAN_TOCC_TOP_SHIFT)
+
+/* FDCAN timeout counter value register */
+
+#define FDCAN_TOCV_TOC_SHIFT (0) /* Bits 0-15: Timestamp counter */
+#define FDCAN_TOCV_TOC_MASK (0xffff << FDCAN_TOCV_TOC_SHIFT)
+
+/* FDCAN error counter register */
+
+#define FDCAN_ECR_TEC_SHIFT (0) /* Bits 0-7: Transmit error counter */
+#define FDCAN_CR_TEC_MASK (0xff << FDCAN_ECR_TEC_SHIFT)
+#define FDCAN_ECR_REC_SHIFT (8) /* Bits 8-14: Receive error counter */
+#define FDCAN_ECR_REC_MASK (0x7f << FDCAN_ECR_REC_SHIFT)
+#define FDCAN_ECR_RP (1 << 15) /* Bit 15: Receive error passive */
+#define FDCAN_ECR_CEL_SHIFT (16) /* Bits 16-23: CAN error logging */
+#define FDCAN_ECR_CEL_MASK (0xff << FDCAN_ECR_CEL_SHIFT)
+
+/* FDCAN protocol status register */
+
+/* Error codes */
+
+#define FDCAN_PSR_EC_NO_ERROR (0) /* No error occurred since LEC has been reset */
+#define FDCAN_PSR_EC_STUFF_ERROR (1) /* More than 5 equal bits in a sequence */
+#define FDCAN_PSR_EC_FORM_ERROR (2) /* Part of a received frame has wrong format */
+#define FDCAN_PSR_EC_ACK_ERROR (3) /* Message not acknowledged by another node */
+#define FDCAN_PSR_EC_BIT1_ERROR (4) /* Send with recessive level, but bus value was dominant */
+#define FDCAN_PSR_EC_BIT0_ERROR (5) /* Send with dominant level, but bus value was recessive */
+#define FDCAN_PSR_EC_CRC_ERROR (6) /* CRC received message incorrect */
+#define FDCAN_PSR_EC_NO_CHANGE (7) /* No CAN bus event was detected since last read */
+
+#define FDCAN_PSR_LEC_SHIFT (0) /* Bits 0-2: Last error code */
+#define FDCAN_PSR_LEC_MASK (0x7 << FDCAN_PSR_LEC_SHIFT)
+# define FDCAN_PSR_LEC(n) ((uint32_t)(n) << FDCAN_PSR_LEC_SHIFT) /* See error codes above */
+#define FDCAN_PSR_ACT_SHIFT (3) /* Bits 3-4: Activity */
+#define FDCAN_PSR_ACT_MASK (3 << FDCAN_PSR_ACT_SHIFT)
+# define FDCAN_PSR_ACT_SYNC (0 << FDCAN_PSR_ACT_SHIFT) /* 00: Synchronizing */
+# define FDCAN_PSR_ACT_IDLE (1 << FDCAN_PSR_ACT_SHIFT) /* 01: Idle */
+# define FDCAN_PSR_ACT_RECV (2 << FDCAN_PSR_ACT_SHIFT) /* 10: Receiver */
+# define FDCAN_PSR_ACT_TRANS (3 << FDCAN_PSR_ACT_SHIFT) /* 11: Transmitter */
+#define FDCAN_PSR_EP (1 << 5) /* Bit 5: Error passive */
+#define FDCAN_PSR_EW (1 << 6) /* Bit 6: Warning status */
+#define FDCAN_PSR_BO (1 << 7) /* Bit 7: Bus_off status */
+#define FDCAN_PSR_DLEC_SHIFT (8) /* Bits 8-10: Data last error code */
+#define FDCAN_PSR_DLEC_MASK (0x7 << FDCAN_PSR_DLEC_SHIFT)
+# define FDCAN_PSR_DLEC(n) ((uint32_t)(n) << FDCAN_PSR_DLEC_SHIFT) /* See error codes above */
+#define FDCAN_PSR_RESI (1 << 11) /* Bit 11: ESI flag of last message */
+#define FDCAN_PSR_RBRS (1 << 12) /* Bit 12: BRS flag of last message */
+#define FDCAN_PSR_REDL (1 << 13) /* Bit 13: Recieved message */
Review comment:
```suggestion
#define FDCAN_PSR_REDL (1 << 13) /* Bit 13: Received message */
```
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