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Posted to commits@nuttx.apache.org by xi...@apache.org on 2022/08/06 17:57:08 UTC
[incubator-nuttx] branch master updated: remove unused lib,fix according review comments
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new 702e2f3680 remove unused lib,fix according review comments
702e2f3680 is described below
commit 702e2f368019053723be42ba8ce72128491ca621
Author: p-eaglelaw <p-...@xiaomi.com>
AuthorDate: Sat Aug 6 11:03:43 2022 +0800
remove unused lib,fix according review comments
---
arch/arm/src/phy62xx/Make.defs | 55 ++---
arch/arm/src/phy62xx/bus_dev.h | 77 +++---
arch/arm/src/phy62xx/clock.c | 21 ++
arch/arm/src/phy62xx/irq.c | 91 +++----
arch/arm/src/phy62xx/phy6222_irq.h | 371 ++++++++++++++++++++++++++++
arch/arm/src/phy62xx/phy6222_patch.c | 19 ++
arch/arm/src/phy62xx/phy62xx_exception.S | 26 +-
arch/arm/src/phy62xx/rom_sym_def.h | 1 +
arch/arm/src/phy62xx/timer.c | 4 +-
arch/arm/src/phy62xx/uart.c | 6 +-
boards/arm/phy62xx/phy6222/scripts/flash.ld | 1 +
11 files changed, 538 insertions(+), 134 deletions(-)
diff --git a/arch/arm/src/phy62xx/Make.defs b/arch/arm/src/phy62xx/Make.defs
index 846f005da9..ac7023e67e 100644
--- a/arch/arm/src/phy62xx/Make.defs
+++ b/arch/arm/src/phy62xx/Make.defs
@@ -20,18 +20,12 @@
include armv6-m/Make.defs
-CMN_ASRCS := $(filter-out arm_exception.S,$(CMN_ASRCS))
-
CMN_ASRCS += phy62xx_exception.S phy62xx_start.S
-CHIP_CSRCS = start.c gpio.c irq.c timer.c uart.c pwrmgr.c idle.c my_printf.c
-#CHIP_CSRCS = start.c gpio.c irq.c timer.c clock.c uart.c pwrmgr.c idle.c my_printf.c flash.c
+CHIP_CSRCS = start.c irq.c timer.c idle.c
CHIP_CSRCS += jump_table.c
CHIP_CSRCS += pplus_mtd_flash.c
ifeq ($(CONFIG_PHY6222_BLE),y)
-#CHIP_CSRCS += phy62xx_ble.c phy62xx_ble_hcitl.c
-#CHIP_CSRCS += phy62xx_ble_patch.c phy62xx_ble_hci_event_patch.c rf_phy_driver.c
-#CHIP_CSRCS += phy62xx_ble.c phy62xx_ble_patch.c rf_phy_driver.c
CHIP_CSRCS += phy62xx_ble.c
endif
@@ -55,11 +49,8 @@ endif
INCLUDES += $(shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)include)
INCLUDES += $(shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)ble)
-#INCLUDES += $(shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)ble$(DELIM)controller)
-#INCLUDES += $(shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)ble$(DELIM)hci)
-#INCLUDES += $(shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)ble$(DELIM)include)
-#INCLUDES += $(shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)osal$(DELIM)include)
+CFLAGS += -ffunction-sections
CFLAGS += -DCFG_CP
CFLAGS += -DPHY_MCU_TYPE=MCU_BUMBEE_M0
CFLAGS += -DHOST_CONFIG=4
@@ -73,53 +64,39 @@ CFLAGS += -DUSE_SYS_TICK
CFLAGS += -DHUGE_MODE=0
CFLAGS += -DMAX_NUM_LL_CONN=1
CFLAGS += -DUSE_ROMSYM_ALIAS
-#CFLAGS += -Wimplicit-function-declaration
CFLAGS += -Wno-unused-but-set-variable
CFLAGS += -DEXTERN_BLE_FUNC=0
LDFLAGS += "$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)bb_rom_sym_m0.gdbsym"
-.buildlib:
- $(Q) if [ -d ../../../../phy62xxble ]; then \
- echo "##############build lib internally##############"; \
- make -C ../../../../phy62xxble; \
- else \
- if [ ! -f libphy62xxble.a ]; then \
- echo "############download lib form server############"; \
- curl -L -o libphy62xxble.a http://www.phyplusinc.com/phyplus/libphy62xxble.a; \
- mkdir -p ../../../staging; \
- cp -a libphy62xxble.a ../../../staging; \
- else \
- echo "############file exist############"; \
- fi \
- fi
-
-context:: .buildlib
-
ifndef CONFIG_PHY6222_SDK
EXTRA_LIBPATHS += -L$(TOPDIR)/arch/arm/src/chip
-EXTRA_LIBS += -lphy62xxble
CHIP_CSRCS += flash.c
-CHIP_CSRCS += clock.c
+CHIP_CSRCS += clock.c
+CHIP_CSRCS += gpio.c
+CHIP_CSRCS += pwrmgr.c
+CHIP_CSRCS += uart.c
+CHIP_CSRCS += my_printf.c
+CHIP_CSRCS += phy6222_patch.c
+else
+EXTRA_LIBPATHS += -L$(TOPDIR)/../apps/vendor/phyplus/phy6222_sdk/lib
+ifdef CONFIG_PHYAPP_SBPADVSCAN
+EXTRA_LIBS += -lphy6222_rf_advscan
else
-EXTRA_LIBPATHS += -L$(TOPDIR)/../apps/phy6222/bbb_sdk/lib
EXTRA_LIBS += -lphy6222_rf
+endif
EXTRA_LIBS += -lphy6222_sec_boot
EXTRA_LIBS += -lphy6222_host
endif
ifdef CONFIG_PHY6222_PHY_MESH
-EXTRA_LIBPATHS += -L$(TOPDIR)/../apps/phy6222/bbb_sdk/components/ethermind/lib/meshlibs/phyos/armgcc/
+EXTRA_LIBPATHS += -L$(TOPDIR)/../apps/vendor/phyplus/phy6222_sdk/components/ethermind/lib/meshlibs/phyos/armgcc/
EXTRA_LIBS += -lethermind_mesh_core
EXTRA_LIBS += -lethermind_mesh_models
EXTRA_LIBS += -lethermind_utils
-#LDLIBPATH += $(APPDIR)/phy6222/bbb_sdk/components/ethermind/lib/meshlibs/phyos/armgcc/
-#LDLIBS += -lethermind_mesh_core
-#LDLIBS += -lethermind_mesh_models
-#LDLIBS += -lethermind_utils
endif
ifdef CONFIG_MIJIA_APIS
-EXTRA_LIBPATHS += -L$(TOPDIR)/../apps/phy6222/bbb_sdk/components/xiaomi/libs/mesh_auth/debug/
-EXTRA_LIBS += -lmesh-auth-cortex-m0plus-debug
+EXTRA_LIBPATHS += -L$(TOPDIR)/../apps/vendor/phyplus/phy6222_sdk/components/xiaomi/libs/mesh_auth/debug/
+EXTRA_LIBS += $(TOPDIR)/../apps/vendor/phyplus/phy6222_sdk/components/xiaomi/libs/mesh_auth/debug/mesh-auth-cortex-m0plus-debug.a
endif
diff --git a/arch/arm/src/phy62xx/bus_dev.h b/arch/arm/src/phy62xx/bus_dev.h
index 99d62dff93..c948bb6700 100644
--- a/arch/arm/src/phy62xx/bus_dev.h
+++ b/arch/arm/src/phy62xx/bus_dev.h
@@ -57,43 +57,50 @@ enum
/* ---- Interrupt Number Definition ---- */
+#if defined ( __CC_ARM )
+#define M0_IRQ_BASE 0
+#elif defined ( __GNUC__ )
+#define M0_IRQ_BASE 16
+#endif
typedef enum IRQn
{
- /* ---- Cortex-M0 Processor Exceptions Numbers ---- */
-
- NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /* 3 HardFault Interrupt */
- SVCall_IRQn = -5, /* 11 SV Call Interrupt */
- PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
- SysTick_IRQn = -1, /* 15 System Tick Interrupt */
-
- /* ---- PHY BUMBEE M0 Interrupt Numbers ---- */
-
- BB_IRQn = 4, /* Base band Interrupt */
- KSCAN_IRQn = 5, /* Key scan Interrupt */
- RTC_IRQn = 6, /* RTC Timer Interrupt */
-
- WDT_IRQn = 10, /* Watchdog Timer Interrupt */
- UART0_IRQn = 11, /* UART0 Interrupt */
- I2C0_IRQn = 12, /* I2C0 Interrupt */
- I2C1_IRQn = 13, /* I2C1 Interrupt */
- SPI0_IRQn = 14, /* SPI0 Interrupt */
- SPI1_IRQn = 15, /* SPI1 Interrupt */
- GPIO_IRQn = 16, /* GPIO Interrupt */
- UART1_IRQn = 17, /* UART1 Interrupt */
- SPIF_IRQn = 18, /* SPIF Interrupt */
- DMAC_IRQn = 19, /* DMAC Interrupt */
- TIM1_IRQn = 20, /* Timer1 Interrupt */
- TIM2_IRQn = 21, /* Timer2 Interrupt */
- TIM3_IRQn = 22, /* Timer3 Interrupt */
- TIM4_IRQn = 23, /* Timer4 Interrupt */
- TIM5_IRQn = 24, /* Timer5 Interrupt */
- TIM6_IRQn = 25, /* Timer6 Interrupt */
-
- AES_IRQn = 28, /* AES Interrupt */
- ADCC_IRQn = 29, /* ADC Interrupt */
- QDEC_IRQn = 30, /* QDEC Interrupt */
- RNG_IRQn = 31, /* RNG Interrupt */
+ /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
+ NonMaskableInt_IRQn = -14+M0_IRQ_BASE, /* 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13+M0_IRQ_BASE, /* 3 HardFault Interrupt */
+
+
+
+ SVCall_IRQn = -5+M0_IRQ_BASE, /* 11 SV Call Interrupt */
+
+ PendSV_IRQn = -2+M0_IRQ_BASE, /* 14 Pend SV Interrupt */
+ SysTick_IRQn = -1+M0_IRQ_BASE, /* 15 System Tick Interrupt */
+
+ /* ---------------------- PHY BUMBEE M0 Interrupt Numbers --------------------- */
+ BB_IRQn = 4+M0_IRQ_BASE, /* Base band Interrupt */
+ KSCAN_IRQn = 5+M0_IRQ_BASE, /* Key scan Interrupt */
+ RTC_IRQn = 6+M0_IRQ_BASE, /* RTC Timer Interrupt */
+
+ WDT_IRQn = 10+M0_IRQ_BASE, /* Watchdog Timer Interrupt */
+ UART0_IRQn = 11+M0_IRQ_BASE, /* UART0 Interrupt */
+ I2C0_IRQn = 12+M0_IRQ_BASE, /* I2C0 Interrupt */
+ I2C1_IRQn = 13+M0_IRQ_BASE, /* I2C1 Interrupt */
+ SPI0_IRQn = 14+M0_IRQ_BASE, /* SPI0 Interrupt */
+ SPI1_IRQn = 15+M0_IRQ_BASE, /* SPI1 Interrupt */
+ GPIO_IRQn = 16+M0_IRQ_BASE, /* GPIO Interrupt */
+ UART1_IRQn = 17+M0_IRQ_BASE, /* UART1 Interrupt */
+ SPIF_IRQn = 18+M0_IRQ_BASE, /* SPIF Interrupt */
+ DMAC_IRQn = 19+M0_IRQ_BASE, /* DMAC Interrupt */
+ TIM1_IRQn = 20+M0_IRQ_BASE, /* Timer1 Interrupt */
+ TIM2_IRQn = 21+M0_IRQ_BASE, /* Timer2 Interrupt */
+ TIM3_IRQn = 22+M0_IRQ_BASE, /* Timer3 Interrupt */
+ TIM4_IRQn = 23+M0_IRQ_BASE, /* Timer4 Interrupt */
+ TIM5_IRQn = 24+M0_IRQ_BASE, /* Timer5 Interrupt */
+ TIM6_IRQn = 25+M0_IRQ_BASE, /* Timer6 Interrupt */
+
+ AES_IRQn = 28+M0_IRQ_BASE, /* AES Interrupt */
+ ADCC_IRQn = 29+M0_IRQ_BASE, /* ADC Interrupt */
+ QDEC_IRQn = 30+M0_IRQ_BASE, /* QDEC Interrupt */
+ RNG_IRQn = 31+M0_IRQ_BASE /* RNG Interrupt */
} IRQn_Type;
#ifdef __cplusplus
diff --git a/arch/arm/src/phy62xx/clock.c b/arch/arm/src/phy62xx/clock.c
index 8da285d78f..9dd0a08e59 100644
--- a/arch/arm/src/phy62xx/clock.c
+++ b/arch/arm/src/phy62xx/clock.c
@@ -35,6 +35,27 @@ extern uint32_t osal_sys_tick;
* Public Functions
****************************************************************************/
+extern volatile sysclk_t g_system_clk;
+uint32_t timer_sysclk_get_clk(void)
+{
+ switch (g_system_clk)
+ {
+ case SYS_CLK_RC_32M:
+ case SYS_CLK_DBL_32M:
+ return 32000000;
+ case SYS_CLK_XTAL_16M:
+ return 16000000;
+ case SYS_CLK_DLL_48M:
+ return 48000000;
+ case SYS_CLK_DLL_64M:
+ return 64000000;
+ default:
+ break;
+ }
+
+ return 16000000;
+}
+
void hal_clk_gate_enable(MODULE_e module)
{
if (module < MOD_CP_CPU)
diff --git a/arch/arm/src/phy62xx/irq.c b/arch/arm/src/phy62xx/irq.c
index 6a127ba82e..827d54baad 100644
--- a/arch/arm/src/phy62xx/irq.c
+++ b/arch/arm/src/phy62xx/irq.c
@@ -36,6 +36,7 @@
#include "arm_internal.h"
#include "jump_function.h"
#include "bus_dev.h"
+
/* #include "phy62xx_irq.h" */
/****************************************************************************
@@ -181,8 +182,8 @@ static inline void phy62xx_clrpend(int irq)
* Name: up_irqinitialize
****************************************************************************/
+extern void exception_phy(void);
extern void exception_common(void);
-extern void exception_origin(void);
#define svc(code) asm volatile("svc %[immediate]"::[immediate]"I"(code))
#define SVC_CALL_WR 0
@@ -204,15 +205,17 @@ int irq_priority(int irqid, uint8_t priority)
return 0;
}
+#ifdef CONFIG_PHY6222_SDK
void LL_IRQHandler1(void);
+#endif
void TIM1_IRQHandler1(void);
#ifdef CONFIG_PHY6222_SDK
void TIM2_IRQHandler1(void);
#endif
-
+#ifdef CONFIG_PHY6222_SDK
void TIM3_IRQHandler1(void);
-
+#endif
#ifdef CONFIG_PHY6222_SDK
void TIM5_IRQHandler1(void);
#endif
@@ -241,46 +244,46 @@ void up_irqinitialize(void)
/* register jump table irq handler */
- JUMP_FUNCTION(NMI_HANDLER) = (uint32_t)&exception_origin;
- JUMP_FUNCTION(HARDFAULT_HANDLER) = (uint32_t)&exception_common;
- JUMP_FUNCTION(SVC_HANDLER) = (uint32_t)&exception_origin;
- JUMP_FUNCTION(PENDSV_HANDLER) = (uint32_t)&exception_origin;
- JUMP_FUNCTION(SYSTICK_HANDLER) = (uint32_t)&exception_origin;
+ JUMP_FUNCTION(NMI_HANDLER) = (uint32_t)&exception_common;
+ JUMP_FUNCTION(HARDFAULT_HANDLER) = (uint32_t)&exception_phy;
+ JUMP_FUNCTION(SVC_HANDLER) = (uint32_t)&exception_common;
+ JUMP_FUNCTION(PENDSV_HANDLER) = (uint32_t)&exception_common;
+ JUMP_FUNCTION(SYSTICK_HANDLER) = (uint32_t)&exception_common;
/* Vectors 16 - 47 external irq handler */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 0) = (unsigned)&exception_origin, /* 16+0 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 1) = (unsigned)&exception_origin, /* 16+1 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 2) = (unsigned)&exception_origin, /* 16+2 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 3) = (unsigned)&exception_origin, /* 16+3 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 4) = (unsigned)&exception_common, /* 16+4 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 5) = (unsigned)&exception_origin, /* 16+5 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 6) = (unsigned)&exception_origin, /* 16+6 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 7) = (unsigned)&exception_origin, /* 16+7 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 8) = (unsigned)&exception_origin, /* 16+8 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 9) = (unsigned)&exception_origin, /* 16+9 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 10) = (unsigned)&exception_origin, /* 16+10 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 11) = (unsigned)&exception_common, /* 16+11 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 12) = (unsigned)&exception_origin, /* 16+12 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 13) = (unsigned)&exception_origin, /* 16+13 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 14) = (unsigned)&exception_origin, /* 16+14 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 15) = (unsigned)&exception_origin, /* 16+15 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 16) = (unsigned)&exception_common, /* 16+16 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 17) = (unsigned)&exception_origin, /* 16+17 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 18) = (unsigned)&exception_common, /* 16+18 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 19) = (unsigned)&exception_origin, /* 16+19 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 20) = (unsigned)&exception_common, /* 16+20 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 21) = (unsigned)&exception_common, /* 16+21 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 22) = (unsigned)&exception_common, /* 16+22 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 23) = (unsigned)&exception_common, /* 16+23 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 24) = (unsigned)&exception_origin, /* 16+24 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 25) = (unsigned)&exception_origin, /* 16+25 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 26) = (unsigned)&exception_origin, /* 16+26 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 27) = (unsigned)&exception_origin, /* 16+27 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 28) = (unsigned)&exception_origin, /* 16+28 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 29) = (unsigned)&exception_origin, /* 16+29 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 30) = (unsigned)&exception_origin, /* 16+30 */
- JUMP_FUNCTION(V0_IRQ_HANDLER + 31) = (unsigned)&exception_origin, /* 16+31 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 0) = (unsigned)&exception_common, /* 16+0 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 1) = (unsigned)&exception_common, /* 16+1 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 2) = (unsigned)&exception_common, /* 16+2 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 3) = (unsigned)&exception_common, /* 16+3 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 4) = (unsigned)&exception_phy, /* 16+4 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 5) = (unsigned)&exception_common, /* 16+5 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 6) = (unsigned)&exception_common, /* 16+6 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 7) = (unsigned)&exception_common, /* 16+7 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 8) = (unsigned)&exception_common, /* 16+8 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 9) = (unsigned)&exception_common, /* 16+9 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 10) = (unsigned)&exception_common, /* 16+10 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 11) = (unsigned)&exception_phy, /* 16+11 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 12) = (unsigned)&exception_common, /* 16+12 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 13) = (unsigned)&exception_common, /* 16+13 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 14) = (unsigned)&exception_common, /* 16+14 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 15) = (unsigned)&exception_common, /* 16+15 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 16) = (unsigned)&exception_phy, /* 16+16 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 17) = (unsigned)&exception_common, /* 16+17 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 18) = (unsigned)&exception_phy, /* 16+18 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 19) = (unsigned)&exception_common, /* 16+19 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 20) = (unsigned)&exception_phy, /* 16+20 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 21) = (unsigned)&exception_phy, /* 16+21 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 22) = (unsigned)&exception_phy, /* 16+22 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 23) = (unsigned)&exception_phy, /* 16+23 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 24) = (unsigned)&exception_common, /* 16+24 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 25) = (unsigned)&exception_common, /* 16+25 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 26) = (unsigned)&exception_common, /* 16+26 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 27) = (unsigned)&exception_common, /* 16+27 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 28) = (unsigned)&exception_common, /* 16+28 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 29) = (unsigned)&exception_common, /* 16+29 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 30) = (unsigned)&exception_common, /* 16+30 */
+ JUMP_FUNCTION(V0_IRQ_HANDLER + 31) = (unsigned)&exception_common, /* 16+31 */
/* currents_regs is non-NULL only while processing an interrupt */
@@ -316,16 +319,16 @@ void up_irqinitialize(void)
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* And finally, enable interrupts */
-
+#ifdef CONFIG_PHY6222_SDK
irq_attach(PHY62XX_IRQ_BB_IRQn, (xcpt_t)LL_IRQHandler1, NULL);
+#endif
irq_attach(PHY62XX_IRQ_TIM1_IRQn, (xcpt_t)TIM1_IRQHandler1, NULL);
-
#ifdef CONFIG_PHY6222_SDK
irq_attach(PHY62XX_IRQ_TIM2_IRQn, (xcpt_t)TIM2_IRQHandler1, NULL);
#endif
-
+#ifdef CONFIG_PHY6222_SDK
irq_attach(PHY62XX_IRQ_TIM3_IRQn, (xcpt_t)TIM3_IRQHandler1, NULL);
-
+#endif
#ifdef CONFIG_PHY6222_SDK
irq_attach(PHY62XX_IRQ_TIM5_IRQn, (xcpt_t)TIM5_IRQHandler1, NULL);
#endif
diff --git a/arch/arm/src/phy62xx/phy6222_irq.h b/arch/arm/src/phy62xx/phy6222_irq.h
new file mode 100644
index 0000000000..92d215aec3
--- /dev/null
+++ b/arch/arm/src/phy62xx/phy6222_irq.h
@@ -0,0 +1,371 @@
+/****************************************************************************
+ * arch/arm/src/phy62xx/phy6222_irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_SRC_PHY62XX_PHY6222_IRQ_H
+#define __ARCH_ARM_SRC_PHY62XX_PHY6222_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/irq.h>
+#ifndef __ASSEMBLY__
+# include <nuttx/compiler.h>
+# include <stdint.h>
+#endif
+
+#include <arch/chip/chip.h>
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+/* If this is a kernel build,
+ * how many nested system calls should we support?
+ */
+
+#ifndef CONFIG_SYS_NNEST
+# define CONFIG_SYS_NNEST 2
+#endif
+
+/* IRQ Stack Frame Format ***************************************************
+ *
+ * The following additional registers are stored by the interrupt handling
+ * logic.
+ */
+
+#define REG_R13 (0) /* R13 = SP at time of interrupt */
+#define REG_PRIMASK (1) /* PRIMASK */
+#define REG_R4 (2) /* R4 */
+#define REG_R5 (3) /* R5 */
+#define REG_R6 (4) /* R6 */
+#define REG_R7 (5) /* R7 */
+#define REG_R8 (6) /* R8 */
+#define REG_R9 (7) /* R9 */
+#define REG_R10 (8) /* R10 */
+#define REG_R11 (9) /* R11 */
+
+/* In the kernel build, we may return to either privileged or unprivileged
+ * modes.
+ */
+
+#ifdef CONFIG_BUILD_PROTECTED
+# define REG_EXC_RETURN (10) /* EXC_RETURN */
+# define SW_XCPT_REGS (11)
+#else
+# define SW_XCPT_REGS (10)
+#endif
+
+/* The total number of registers saved by software */
+
+#define SW_XCPT_SIZE (4 * SW_XCPT_REGS)
+
+/* On entry into an IRQ, the hardware automatically saves the following
+ * registers on the stack in this (address) order:
+ */
+
+#define REG_DUMMY0 (SW_XCPT_REGS + 0) /* DUMMY */
+#define REG_DUMMY1 (SW_XCPT_REGS + 1) /* DUMMY */
+#define REG_R0 (SW_XCPT_REGS + 0 + 2) /* R0 */
+#define REG_R1 (SW_XCPT_REGS + 1 + 2) /* R1 */
+#define REG_R2 (SW_XCPT_REGS + 2 + 2) /* R2 */
+#define REG_R3 (SW_XCPT_REGS + 3 + 2) /* R3 */
+#define REG_R12 (SW_XCPT_REGS + 4 + 2) /* R12 */
+#define REG_R14 (SW_XCPT_REGS + 5 + 2) /* R14 = LR */
+#define REG_R15 (SW_XCPT_REGS + 6 + 2) /* R15 = PC */
+#define REG_XPSR (SW_XCPT_REGS + 7 + 2) /* xPSR */
+
+#define HW_XCPT_REGS (10)
+#define HW_XCPT_SIZE (4 * HW_XCPT_REGS)
+
+#define XCPTCONTEXT_REGS (HW_XCPT_REGS + SW_XCPT_REGS)
+#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS)
+
+/* Alternate register names */
+
+#define REG_A1 REG_R0
+#define REG_A2 REG_R1
+#define REG_A3 REG_R2
+#define REG_A4 REG_R3
+#define REG_V1 REG_R4
+#define REG_V2 REG_R5
+#define REG_V3 REG_R6
+#define REG_V4 REG_R7
+#define REG_V5 REG_R8
+#define REG_V6 REG_R9
+#define REG_V7 REG_R10
+#define REG_SB REG_R9
+#define REG_SL REG_R10
+#define REG_FP REG_R11
+#define REG_IP REG_R12
+#define REG_SP REG_R13
+#define REG_LR REG_R14
+#define REG_PC REG_R15
+
+/* The PIC register is usually R10. It can be R9 is stack checking is enabled
+ * or if the user changes it with -mpic-register on the GCC command line.
+ */
+
+#define REG_PIC REG_R10
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* This structure represents the return state from a system call */
+
+#ifdef CONFIG_LIB_SYSCALL
+struct xcpt_syscall_s
+{
+ uint32_t excreturn; /* The EXC_RETURN value */
+ uint32_t sysreturn; /* The return PC */
+};
+#endif
+
+/* The following structure is included in the TCB and defines the complete
+ * state of the thread.
+ */
+
+struct xcptcontext
+{
+ /* The following function pointer is non-zero if there
+ * are pending signals to be processed.
+ */
+
+ void *sigdeliver; /* Actual type is sig_deliver_t */
+
+ /* These are saved copies of LR, PRIMASK, and xPSR used during
+ * signal processing.
+ *
+ * REVISIT: Because there is only one copy of these save areas,
+ * only a single signal handler can be active. This precludes
+ * queuing of signal actions. As a result, signals received while
+ * another signal handler is executing will be ignored!
+ */
+
+ uint32_t saved_pc;
+ uint32_t saved_primask;
+ uint32_t saved_xpsr;
+#ifdef CONFIG_BUILD_PROTECTED
+ uint32_t saved_lr;
+
+ /* This is the saved address to use when returning from a user-space
+ * signal handler.
+ */
+
+ uint32_t sigreturn;
+#endif
+
+#ifdef CONFIG_LIB_SYSCALL
+ /* The following array holds the return address and the exc_return value
+ * needed to return from each nested system call.
+ */
+
+ uint8_t nsyscalls;
+ struct xcpt_syscall_s syscall[CONFIG_SYS_NNEST];
+#endif
+
+ /* Register save area */
+
+ uint32_t regs[XCPTCONTEXT_REGS];
+};
+#endif
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* Name: up_irq_save, up_irq_restore, and friends.
+ *
+ * NOTE: This function should never be called from application code and,
+ * as a general rule unless you really know what you are doing, this
+ * function should not be called directly from operation system code either:
+ * Typically, the wrapper functions, enter_critical_section() and
+ * leave_critical section(), are probably what you really want.
+ */
+
+/* Get/set the PRIMASK register */
+
+static inline uint8_t getprimask(void) inline_function;
+static inline uint8_t getprimask(void)
+{
+ uint32_t primask;
+ __asm__ __volatile__
+ (
+ "\tmrs %0, primask\n"
+ : "=r" (primask)
+ :
+ : "memory");
+
+ return (uint8_t)primask;
+}
+
+static inline void setprimask(uint32_t primask) inline_function;
+static inline void setprimask(uint32_t primask)
+{
+ __asm__ __volatile__
+ (
+ "\tmsr primask, %0\n"
+ :
+ : "r" (primask)
+ : "memory");
+}
+
+/* Disable IRQs */
+
+static inline void up_irq_disable(void) inline_function;
+static inline void up_irq_disable(void)
+{
+ __asm__ __volatile__ ("\tcpsid i\n");
+}
+
+/* Save the current primask state & disable IRQs */
+
+typedef void (*gpiowr_t)(int id, unsigned int en);
+#if 0
+static inline irqstate_t up_irq_save(void) inline_function;
+static inline irqstate_t up_irq_save(void)
+{
+ unsigned short primask;
+
+ /* Return the current value of primask register and set
+ * bit 0 of the primask register to disable interrupts
+ */
+
+ ((gpiowr_t)0x0000b319)(12, 1);
+
+ __asm__ __volatile__
+ (
+ "\tmrs %0, primask\n"
+ "\tcpsid i\n"
+ : "=r" (primask)
+ :
+ : "memory");
+
+ return primask;
+}
+#endif
+/* Enable IRQs */
+
+static inline void up_irq_enable(void) inline_function;
+static inline void up_irq_enable(void)
+{
+ __asm__ __volatile__ ("\tcpsie i\n");
+}
+
+/* Restore saved primask state */
+#if 0
+static inline void up_irq_restore(irqstate_t flags) inline_function;
+static inline void up_irq_restore(irqstate_t flags)
+{
+ /* If bit 0 of the primask is 0, then we need to restore
+ * interrupts.
+ */
+
+ __asm__ __volatile__
+ (
+ "\tmsr primask, %0\n"
+ :
+ : "r" (flags)
+ : "memory");
+ ((gpiowr_t)0x0000b319)(12, 0);
+}
+#endif
+/* Get/set IPSR */
+
+static inline uint32_t getipsr(void) inline_function;
+static inline uint32_t getipsr(void)
+{
+ uint32_t ipsr;
+ __asm__ __volatile__
+ (
+ "\tmrs %0, ipsr\n"
+ : "=r" (ipsr)
+ :
+ : "memory");
+
+ return ipsr;
+}
+
+/* Get/set CONTROL */
+
+static inline uint32_t getcontrol(void) inline_function;
+static inline uint32_t getcontrol(void)
+{
+ uint32_t control;
+ __asm__ __volatile__
+ (
+ "\tmrs %0, control\n"
+ : "=r" (control)
+ :
+ : "memory");
+
+ return control;
+}
+
+static inline void setcontrol(uint32_t control) inline_function;
+static inline void setcontrol(uint32_t control)
+{
+ __asm__ __volatile__
+ (
+ "\tmsr control, %0\n"
+ :
+ : "r" (control)
+ : "memory");
+}
+
+#endif /* __ASSEMBLY__ */
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_SRC_PHY62XX_PHY6222_IRQ_H */
diff --git a/arch/arm/src/phy62xx/phy6222_patch.c b/arch/arm/src/phy62xx/phy6222_patch.c
new file mode 100644
index 0000000000..bafa96fe84
--- /dev/null
+++ b/arch/arm/src/phy62xx/phy6222_patch.c
@@ -0,0 +1,19 @@
+#include "types.h"
+#include <arch/irq.h>
+#include "mcu_phy_bumbee.h"
+
+#ifndef CONFIG_PHY6222_SDK
+void TIM1_IRQHandler1(void)
+{
+ /* HAL_ENTER_CRITICAL_SECTION() */
+
+ if (AP_TIM1->status & 0x1)
+ {
+ clear_timer_int(AP_TIM1);
+ clear_timer(AP_TIM1);
+ LL_evt_schedule();
+ }
+
+ /* HAL_EXIT_CRITICAL_SECTION(); */
+}
+#endif
diff --git a/arch/arm/src/phy62xx/phy62xx_exception.S b/arch/arm/src/phy62xx/phy62xx_exception.S
index 12b5f98924..c36008a6d5 100644
--- a/arch/arm/src/phy62xx/phy62xx_exception.S
+++ b/arch/arm/src/phy62xx/phy62xx_exception.S
@@ -1,4 +1,4 @@
-/***************************************************************************
+/****************************************************************************
* arch/arm/src/phy62xx/phy62xx_exception.S
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,7 +16,11 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ***************************************************************************/
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
/****************************************************************************
* Included Files
@@ -31,8 +35,8 @@
* Public Symbols
****************************************************************************/
- .globl exception_common
- .file "arm_exception.S"
+ .globl exception_phy
+ .file "phy62xx_exception.S"
/****************************************************************************
* .text
@@ -60,21 +64,21 @@
.align 2
.code 16
.thumb_func
- .type exception_common, function
-exception_common:
+ .type exception_phy, function
+exception_phy:
/* Complete the context save */
+ .extern exception_common
pop {r4}
pop {r1}
- /* Jump to exception_origin in arm_exception.S */
+ /* Jump to exception_common in arm_exception.S */
- b exception_origin
+ b exception_common
- .size exception_common, .-exception_common
+ .size exception_phy, .-exception_phy
+ .end
-#define exception_common exception_origin
-#include "arm_exception.S"
diff --git a/arch/arm/src/phy62xx/rom_sym_def.h b/arch/arm/src/phy62xx/rom_sym_def.h
index 10f0eb05b8..2dc844b302 100644
--- a/arch/arm/src/phy62xx/rom_sym_def.h
+++ b/arch/arm/src/phy62xx/rom_sym_def.h
@@ -68,6 +68,7 @@
#define g_currentLocalRpa _symrom_g_currentLocalRpa
#define g_currentPeerRpa _symrom_g_currentPeerRpa
#define llProcessSlaveControlProcedures0 _symrom_llProcessSlaveControlProcedures0
+ #define llProcessSlaveControlPacket0 _symrom_llProcessSlaveControlPacket0
#define g_rfTxPathCompensation _symrom_g_rfTxPathCompensation
#define ll_isLegacyAdv _symrom_ll_isLegacyAdv
#define g_llScanMode _symrom_g_llScanMode
diff --git a/arch/arm/src/phy62xx/timer.c b/arch/arm/src/phy62xx/timer.c
index 0ab38feca0..21702fe781 100644
--- a/arch/arm/src/phy62xx/timer.c
+++ b/arch/arm/src/phy62xx/timer.c
@@ -194,13 +194,13 @@ static int systic_timerisr(int irq, uint32_t *regs, void *arg)
return 0;
}
-extern uint32_t sysclk_get_clk(void);
+extern uint32_t timer_sysclk_get_clk(void);
void up_timer_initialize(void)
{
irq_attach(PHY62XX_IRQ_SYSTICK, (xcpt_t)systic_timerisr, NULL);
- putreg32((sysclk_get_clk() / 100 - 1), ARMV6M_SYSTICK_RVR); /* 10ms tick */
+ putreg32((timer_sysclk_get_clk() / 100 - 1), ARMV6M_SYSTICK_RVR); /* 10ms tick */
putreg32((SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE |
SYSTICK_CSR_CLKSOURCE), ARMV6M_SYSTICK_CSR);
diff --git a/arch/arm/src/phy62xx/uart.c b/arch/arm/src/phy62xx/uart.c
index c92c4caa1d..5884989c21 100644
--- a/arch/arm/src/phy62xx/uart.c
+++ b/arch/arm/src/phy62xx/uart.c
@@ -346,12 +346,12 @@ int hal_uart_txint_en(UART_INDEX_e uart_index, bool en)
return 0;
}
-extern uint32_t sysclk_get_clk(void);
+extern uint32_t timer_sysclk_get_clk(void);
int uart_hw_init(UART_INDEX_e uart_index)
{
uart_Cfg_t *pcfg;
- int pclk = sysclk_get_clk();
+ int pclk = timer_sysclk_get_clk();
uint32_t dll;
AP_UART_TypeDef *cur_uart = AP_UART0;
MODULE_e mod = MOD_UART0;
@@ -756,7 +756,7 @@ static int pplus_uart_interrupt(int irq, void *context, void *arg)
break;
case BUSY_IRQ:
- priv->reg->USR;
+ (void)priv->reg->USR;
break;
default:
diff --git a/boards/arm/phy62xx/phy6222/scripts/flash.ld b/boards/arm/phy62xx/phy6222/scripts/flash.ld
old mode 100644
new mode 100755
index 9b651ed40b..d48f31847c
--- a/boards/arm/phy62xx/phy6222/scripts/flash.ld
+++ b/boards/arm/phy62xx/phy6222/scripts/flash.ld
@@ -62,6 +62,7 @@ SECTIONS
_sdata = ABSOLUTE(.);
_stextram = ABSOLUTE(.);
*libarch.a:*flash.o(.text .text.*)
+ *libarch.a:arm_exception.o(.text .text.*)
*libarch.a:phy62xx_exception.o(.text .text.*)
*libarch.a:irq.o(.text.arm_ack_irq)
*phy62xx_ble_patch.o(.text .text.*)