[GitHub] [tvm-vta] vegaluisjose commented on a change in pull request #27: Chisel Pipelined ALU

[GitBox <gi...@apache.org>]

vegaluisjose commented on a change in pull request #27:
URL: https://github.com/apache/tvm-vta/pull/27#discussion_r646699023



##########
File path: hardware/chisel/src/main/scala/core/TensorAlu.scala
##########
@@ -97,38 +97,330 @@ class AluVector(implicit p: Parameters) extends Module {
   io.out.data.valid := valid.asUInt.andR
 }
 
-/** TensorAlu.
- *
- * This unit instantiate the ALU vector unit (AluVector) and go over the
- * micro-ops (uops) which are used to read the source operands (vectors)
- * from the acc-scratchpad and then they are written back the same
- * acc-scratchpad.
- */
-class TensorAlu(debug: Boolean = false)(implicit p: Parameters) extends Module {
+class TensorAluIndexGenerator(debug: Boolean = false)(implicit p: Parameters) extends Module {
+  val cnt_o_width = (new AluDecode).lp_0.getWidth
+  val cnt_i_width = (new AluDecode).lp_1.getWidth
+
+  val io = IO(new Bundle {
+    val start = Input(Bool())
+    val last = Output(Bool())
+    val dec = Input(new AluDecode)
+    val valid = Output(Bool())
+    val src_valid = Output(Bool())
+    val dst_idx = Output(UInt(new TensorParams(tensorType="acc").memAddrBits.W))
+    val src_idx = Output(UInt(new TensorParams(tensorType="acc").memAddrBits.W))
+    val uop_idx = Output(UInt(log2Ceil(p(CoreKey).uopMemDepth).W))
+    val cnt_o = Output(UInt(cnt_o_width.W))
+    val cnt_i = Output(UInt(cnt_i_width.W))
+  })
+
+  io.last := false.B
+
+  val running = RegInit( false.B)
+  val stutter = RegInit( false.B)

Review comment:
       Hey @adavare, pretty nice PR. Btw, is it possible to remove this space in `Reg` declarations in this file i.e., `Reg(false.B)` instead of `Reg( false.B)`




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