[mynewt-core] 01/02: nRF5340/nrf52xxx: Add instr/data cache support

[vi...@apache.org]

This is an automated email from the ASF dual-hosted git repository.

vipulrahane pushed a commit to branch nrf5340_misc_fixes
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git

commit b2a24be516fc37b3772ed9244d477e715e180ffa
Author: Vipul Rahane <vi...@proxy.com>
AuthorDate: Mon Apr 12 15:53:44 2021 -0700

    nRF5340/nrf52xxx: Add instr/data cache support
    
    - Add syscfg for controlling instruction/data cache
    - Add syscfgs for enabling ICACHE and add corresponding code in hal_system_init()
---
 hw/mcu/nordic/nrf52xxx/src/hal_system.c |  5 +++++
 hw/mcu/nordic/nrf52xxx/syscfg.yml       |  4 ++++
 hw/mcu/nordic/nrf5340/src/hal_system.c  | 10 ++++++++++
 hw/mcu/nordic/nrf5340/syscfg.yml        | 13 +++++++++++++
 4 files changed, 32 insertions(+)

diff --git a/hw/mcu/nordic/nrf52xxx/src/hal_system.c b/hw/mcu/nordic/nrf52xxx/src/hal_system.c
index ba98306..497c7b6 100644
--- a/hw/mcu/nordic/nrf52xxx/src/hal_system.c
+++ b/hw/mcu/nordic/nrf52xxx/src/hal_system.c
@@ -37,6 +37,11 @@
 void
 hal_system_init(void)
 {
+
+#if MYNEWT_VAL(MCU_ICACHE_ENABLED)
+    NRF_NVMC->ICACHECNF = 1;
+#endif
+
 #if MYNEWT_VAL(MCU_DCDC_ENABLED)
     NRF_POWER->DCDCEN = 1;
 #endif
diff --git a/hw/mcu/nordic/nrf52xxx/syscfg.yml b/hw/mcu/nordic/nrf52xxx/syscfg.yml
index bb038ab..8452301 100644
--- a/hw/mcu/nordic/nrf52xxx/syscfg.yml
+++ b/hw/mcu/nordic/nrf52xxx/syscfg.yml
@@ -92,6 +92,10 @@ syscfg.defs:
             the breakpoint wherever it gets called, For example, reset and crash
        value: 0
 
+    MCU_ICACHE_ENABLED:
+       description: >
+            Enabled Instruction code cache
+       value: 0
 
 # MCU peripherals definitions
     I2C_0:
diff --git a/hw/mcu/nordic/nrf5340/src/hal_system.c b/hw/mcu/nordic/nrf5340/src/hal_system.c
index 59ca458..512cd38 100644
--- a/hw/mcu/nordic/nrf5340/src/hal_system.c
+++ b/hw/mcu/nordic/nrf5340/src/hal_system.c
@@ -36,6 +36,15 @@
 void
 hal_system_init(void)
 {
+
+#if MYNEWT_VAL(MCU_ICACHE_ENABLED)
+    NRF_NVMC_S->ICACHECNF = 1;
+#endif
+
+#if MYNEWT_VAL(MCU_CACHE_ENABLED)
+    NRF_CACHE_S->ENABLE = 1;
+#endif
+
 #if MYNEWT_VAL(MCU_DCDC_ENABLED)
     NRF_REGULATORS_S->VREGMAIN.DCDCEN = 1;
 
@@ -72,6 +81,7 @@ hal_debugger_connected(void)
 void
 hal_system_clock_start(void)
 {
+
 #if MYNEWT_VAL(MCU_LFCLK_SOURCE)
     uint32_t regmsk;
     uint32_t regval;
diff --git a/hw/mcu/nordic/nrf5340/syscfg.yml b/hw/mcu/nordic/nrf5340/syscfg.yml
index d3a1e2e..8aaeca9 100644
--- a/hw/mcu/nordic/nrf5340/syscfg.yml
+++ b/hw/mcu/nordic/nrf5340/syscfg.yml
@@ -53,12 +53,25 @@ syscfg.defs:
             When enabled, asm(bkpt) will be ignored. If not set, it will hit
             the breakpoint wherever it gets called, For example, reset and crash
        value: 0
+
     MCU_HFCLCK192_DIV:
         description: >
             Divider of 192MHz clock that is used for QSPI.
             Default value 4, clock runs at 48MHz.
         range: 1,2,4
         value: 4
+ 
+    MCU_CACHE_ENABLED:
+        description: >
+            Enable instruction and data cache
+            Default value is 0, so disabled.
+        value: 0
+
+    MCU_ICACHE_ENABLED:
+        description: >
+            Enable instruction code cache
+            Default value is 0, so disabled.
+        value: 0
 
 # MCU peripherals definitions
     ADC_0: