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Posted to commits@mynewt.apache.org by je...@apache.org on 2024/03/05 08:38:49 UTC
(mynewt-core) 04/07: hw/bsp: Add nucleo-g0b1re
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit 79836aecdfdf22b59e311d5a40d22f73e2b3b5d3
Author: Jerzy Kasenberg <je...@codecoup.pl>
AuthorDate: Thu Feb 1 09:04:08 2024 +0100
hw/bsp: Add nucleo-g0b1re
This adds BSP for STM32G0 based nucleo-g0b1re board.
Signed-off-by: Jerzy Kasenberg <je...@codecoup.pl>
---
hw/bsp/nucleo-g0b1re/bsp.yml | 65 ++++
hw/bsp/nucleo-g0b1re/debug.sh | 34 ++
hw/bsp/nucleo-g0b1re/include/bsp/bsp.h | 89 ++++++
.../nucleo-g0b1re/include/bsp/stm32g0xx_hal_conf.h | 356 +++++++++++++++++++++
hw/bsp/nucleo-g0b1re/pkg.yml | 40 +++
hw/bsp/nucleo-g0b1re/src/hal_bsp.c | 284 ++++++++++++++++
hw/bsp/nucleo-g0b1re/syscfg.yml | 78 +++++
7 files changed, 946 insertions(+)
diff --git a/hw/bsp/nucleo-g0b1re/bsp.yml b/hw/bsp/nucleo-g0b1re/bsp.yml
new file mode 100644
index 000000000..1cf9878b1
--- /dev/null
+++ b/hw/bsp/nucleo-g0b1re/bsp.yml
@@ -0,0 +1,65 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+bsp.name: "NUCLEO-G0B1RE"
+bsp.url: https://www.st.com/en/evaluation-tools/nucleo-g0b1re.html
+bsp.maker: "STMicroelectronics"
+bsp.arch: cortex_m0
+bsp.compiler: compiler/arm-none-eabi-m0
+bsp.linkerscript: autogenerated
+bsp.downloadscript: "hw/scripts/download.sh"
+bsp.debugscript: "hw/bsp/nucleo-g0b1re/debug.sh"
+
+bsp.flash_map:
+ areas:
+ # System areas.
+ FLASH_AREA_BOOTLOADER:
+ device: 0
+ offset: 0x08000000
+ size: 32kB
+ FLASH_AREA_IMAGE_0:
+ device: 0
+ offset: 0x08010000
+ size: 192kB
+ FLASH_AREA_IMAGE_1:
+ device: 0
+ offset: 0x08040000
+ size: 192kB
+ FLASH_AREA_IMAGE_SCRATCH:
+ device: 0
+ offset: 0x08070000
+ size: 4kB
+
+ # User areas.
+ FLASH_AREA_REBOOT_LOG:
+ user_id: 0
+ device: 0
+ offset: 0x08071000
+ size: 16kB
+ FLASH_AREA_NFFS:
+ user_id: 1
+ device: 0
+ offset: 0x08078000
+ size: 32kB
+
+ FLASH_AREA_SPI:
+ user_id: 2
+ device: 1
+ offset: 0x0
+ size: 192kB
diff --git a/hw/bsp/nucleo-g0b1re/debug.sh b/hw/bsp/nucleo-g0b1re/debug.sh
new file mode 100644
index 000000000..8445f238e
--- /dev/null
+++ b/hw/bsp/nucleo-g0b1re/debug.sh
@@ -0,0 +1,34 @@
+#!/bin/sh
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Called with following variables set:
+# - CORE_PATH is absolute path to @apache-mynewt-core
+# - BSP_PATH is absolute path to hw/bsp/bsp_name
+# - BIN_BASENAME is the path to prefix to target binary,
+# .elf appended to name is the ELF file
+# - FEATURES holds the target features string
+# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+# - RESET set if target should be reset when attaching
+# - NO_GDB set if we should not start gdb to debug
+#
+. $CORE_PATH/hw/scripts/stlink.sh
+
+FILE_NAME=$BIN_BASENAME.elf
+
+stlink_debug
diff --git a/hw/bsp/nucleo-g0b1re/include/bsp/bsp.h b/hw/bsp/nucleo-g0b1re/include/bsp/bsp.h
new file mode 100644
index 000000000..5a3328cdc
--- /dev/null
+++ b/hw/bsp/nucleo-g0b1re/include/bsp/bsp.h
@@ -0,0 +1,89 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#ifndef H_BSP_H
+#define H_BSP_H
+
+#include <inttypes.h>
+#include <mcu/mcu.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Define special stackos sections */
+#define sec_data_core __attribute__((section(".data.core")))
+#define sec_bss_core __attribute__((section(".bss.core")))
+#define sec_bss_nz_core __attribute__((section(".bss.core.nz")))
+
+/* More convenient section placement macros. */
+#define bssnz_t sec_bss_nz_core
+
+extern uint8_t _ram_start[];
+
+#define RAM_SIZE (144 * 1024)
+
+/* LED pins */
+#define LED_1 MCU_GPIO_PORTA(5)
+
+#define LED_GREEN LED_1
+
+#define LED_BLINK_PIN LED_1
+
+/* Button pin */
+#define BUTTON_1 MCU_GPIO_PORTC(13)
+
+/* Arduino pins */
+#define ARDUINO_PIN_D0 MCU_GPIO_PORTC(5)
+#define ARDUINO_PIN_D1 MCU_GPIO_PORTC(4)
+#define ARDUINO_PIN_D2 MCU_GPIO_PORTA(10)
+#define ARDUINO_PIN_D3 MCU_GPIO_PORTB(3)
+#define ARDUINO_PIN_D4 MCU_GPIO_PORTB(5)
+#define ARDUINO_PIN_D5 MCU_GPIO_PORTB(4)
+#define ARDUINO_PIN_D6 MCU_GPIO_PORTB(14)
+#define ARDUINO_PIN_D7 MCU_GPIO_PORTA(8)
+#define ARDUINO_PIN_D8 MCU_GPIO_PORTA(9)
+#define ARDUINO_PIN_D9 MCU_GPIO_PORTC(7)
+#define ARDUINO_PIN_D10 MCU_GPIO_PORTB(0)
+#define ARDUINO_PIN_D11 MCU_GPIO_PORTA(7)
+#define ARDUINO_PIN_D12 MCU_GPIO_PORTA(6)
+#define ARDUINO_PIN_D13 MCU_GPIO_PORTA(5)
+#define ARDUINO_PIN_D14 MCU_GPIO_PORTB(9)
+#define ARDUINO_PIN_D15 MCU_GPIO_PORTB(8)
+#define ARDUINO_PIN_A0 MCU_GPIO_PORTA(0)
+#define ARDUINO_PIN_A1 MCU_GPIO_PORTA(1)
+#define ARDUINO_PIN_A2 MCU_GPIO_PORTA(4)
+#define ARDUINO_PIN_A3 MCU_GPIO_PORTB(1)
+#define ARDUINO_PIN_A4 MCU_GPIO_PORTB(11)
+#define ARDUINO_PIN_A5 MCU_GPIO_PORTB(12)
+
+#define ARDUINO_PIN_RX ARDUINO_PIN_D0
+#define ARDUINO_PIN_TX ARDUINO_PIN_D1
+
+#define ARDUINO_PIN_SCL MCU_GPIO_PORTB(8)
+#define ARDUINO_PIN_SDA MCU_GPIO_PORTB(9)
+
+#define ARDUINO_PIN_SCK ARDUINO_PIN_D13
+#define ARDUINO_PIN_MOSI ARDUINO_PIN_D11
+#define ARDUINO_PIN_MISO ARDUINO_PIN_D12
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* H_BSP_H */
diff --git a/hw/bsp/nucleo-g0b1re/include/bsp/stm32g0xx_hal_conf.h b/hw/bsp/nucleo-g0b1re/include/bsp/stm32g0xx_hal_conf.h
new file mode 100644
index 000000000..3f363abff
--- /dev/null
+++ b/hw/bsp/nucleo-g0b1re/include/bsp/stm32g0xx_hal_conf.h
@@ -0,0 +1,356 @@
+/**
+ ******************************************************************************
+ * @file stm32g0xx_hal_conf.h
+ * @author MCD Application Team
+ * @brief HAL configuration template file.
+ * This file should be copied to the application folder and renamed
+ * to stm32g0xx_hal_conf.h.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2018 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G0xx_HAL_CONF_H
+#define STM32G0xx_HAL_CONF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <syscfg/syscfg.h>
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CEC_MODULE_ENABLED
+#define HAL_COMP_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_FDCAN_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_LPTIM_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_SMBUS_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+
+/* ########################## Register Callbacks selection ############################## */
+/**
+ * @brief This is the list of modules where register callback can be used
+ */
+#define USE_HAL_ADC_REGISTER_CALLBACKS 0u
+#define USE_HAL_CEC_REGISTER_CALLBACKS 0u
+#define USE_HAL_COMP_REGISTER_CALLBACKS 0u
+#define USE_HAL_CRYP_REGISTER_CALLBACKS 0u
+#define USE_HAL_DAC_REGISTER_CALLBACKS 0u
+#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0u
+#define USE_HAL_I2C_REGISTER_CALLBACKS 0u
+#define USE_HAL_I2S_REGISTER_CALLBACKS 0u
+#define USE_HAL_IRDA_REGISTER_CALLBACKS 0u
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0u
+#define USE_HAL_HCD_REGISTER_CALLBACKS 0u
+#define USE_HAL_PCD_REGISTER_CALLBACKS 0u
+#define USE_HAL_RNG_REGISTER_CALLBACKS 0u
+#define USE_HAL_RTC_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0u
+#define USE_HAL_SPI_REGISTER_CALLBACKS 0u
+#define USE_HAL_TIM_REGISTER_CALLBACKS 0u
+#define USE_HAL_UART_REGISTER_CALLBACKS 0u
+#define USE_HAL_USART_REGISTER_CALLBACKS 0u
+#define USE_HAL_WWDG_REGISTER_CALLBACKS 0u
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+#define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
+/**
+ * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG.
+ * This internal oscillator is mainly dedicated to provide a high precision clock to
+ * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
+ * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
+ * which is subject to manufacturing process variations.
+ */
+#if !defined (HSI48_VALUE)
+ #define HSI48_VALUE 48000000U /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz.
+ The real value my vary depending on manufacturing process variations.*/
+#endif /* HSI48_VALUE */
+#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
+
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+The real value may vary depending on the variations
+in voltage and temperature.*/
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ * This value is used by the UART, RTC HAL module to compute the system frequency
+ */
+#if !defined (LSE_VALUE)
+#define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined (LSE_STARTUP_TIMEOUT)
+#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief External clock source for I2S1 peripheral
+ * This value is used by the RCC HAL module to compute the I2S1 clock source
+ * frequency.
+ */
+#if !defined (EXTERNAL_I2S1_CLOCK_VALUE)
+#define EXTERNAL_I2S1_CLOCK_VALUE (48000UL) /*!< Value of the I2S1 External clock source in Hz*/
+#endif /* EXTERNAL_I2S1_CLOCK_VALUE */
+
+#if defined(STM32G0C1xx) || defined(STM32G0B1xx) || defined(STM32G0B0xx)
+/**
+ * @brief External clock source for I2S2 peripheral
+ * This value is used by the RCC HAL module to compute the I2S2 clock source
+ * frequency.
+ */
+#if !defined (EXTERNAL_I2S2_CLOCK_VALUE)
+ #define EXTERNAL_I2S2_CLOCK_VALUE 48000U /*!< Value of the I2S2 External clock source in Hz*/
+#endif /* EXTERNAL_I2S2_CLOCK_VALUE */
+#endif /* STM32G0C1xx || STM32G0B1xx || STM32G0B0xx */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY ((1UL<<__NVIC_PRIO_BITS) - 1UL) /*!< tick interrupt priority */
+#define USE_RTOS 0U
+#define PREFETCH_ENABLE MYNEWT_VAL(STM32_FLASH_PREFETCH_ENABLE)
+#define INSTRUCTION_CACHE_ENABLE 1U
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+#define USE_SPI_CRC 1U
+
+/* ################## CRYP peripheral configuration ########################## */
+
+#define USE_HAL_CRYP_SUSPEND_RESUME 1U
+
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1U */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include modules header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+#include "stm32g0xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+#include "stm32g0xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+#include "stm32g0xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+#include "stm32g0xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+#include "stm32g0xx_hal_adc.h"
+#include "stm32g0xx_hal_adc_ex.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+#include "stm32g0xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+#include "stm32g0xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+#include "stm32g0xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+#include "stm32g0xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+#include "stm32g0xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+#include "stm32g0xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+#include "stm32g0xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+#include "stm32g0xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+#include "stm32g0xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+#include "stm32g0xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+#include "stm32g0xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+#include "stm32g0xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32g0xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+#include "stm32g0xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+#include "stm32g0xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+#include "stm32g0xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+#include "stm32g0xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+#include "stm32g0xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+#include "stm32g0xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+#include "stm32g0xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+#include "stm32g0xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+#include "stm32g0xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+#include "stm32g0xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+#include "stm32g0xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+#include "stm32g0xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for functions parameters check.
+ * @param expr If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t *file, uint32_t line);
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G0xx_HAL_CONF_H */
+
+
+
diff --git a/hw/bsp/nucleo-g0b1re/pkg.yml b/hw/bsp/nucleo-g0b1re/pkg.yml
new file mode 100644
index 000000000..397c64a16
--- /dev/null
+++ b/hw/bsp/nucleo-g0b1re/pkg.yml
@@ -0,0 +1,40 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: hw/bsp/nucleo-g0b1re
+pkg.type: bsp
+pkg.description: BSP definition for the nucleo-g0b1re board.
+pkg.author: "Apache Mynewt <de...@mynewt.apache.org>"
+pkg.homepage: "http://mynewt.apache.org/"
+pkg.keywords:
+ - stm32
+ - stm32g0
+ - nucleo
+
+pkg.cflags: -DSTM32G0B1xx -DUSE_FULL_LL_DRIVER
+
+pkg.cflags.HARDFLOAT:
+ - -mfloat-abi=hard -mfpu=fpv4-sp-d16
+
+pkg.deps:
+ - "@apache-mynewt-core/hw/mcu/stm/stm32g0xx"
+ - "@apache-mynewt-core/libc"
+ - "@apache-mynewt-core/hw/drivers/flash/spiflash"
+ - "@apache-mynewt-core/hw/bus/drivers/spi_hal"
+ - "@apache-mynewt-core/hw/scripts"
diff --git a/hw/bsp/nucleo-g0b1re/src/hal_bsp.c b/hw/bsp/nucleo-g0b1re/src/hal_bsp.c
new file mode 100644
index 000000000..3d2062730
--- /dev/null
+++ b/hw/bsp/nucleo-g0b1re/src/hal_bsp.c
@@ -0,0 +1,284 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include <assert.h>
+
+#include "bsp/bsp.h"
+#include "os/mynewt.h"
+#include "spiflash/spiflash.h"
+
+#include <hal/hal_bsp.h>
+#include <hal/hal_flash_int.h>
+#include <hal/hal_system.h>
+
+#include <stm32g0xx.h>
+#include <stm32_common/stm32_hal.h>
+#if MYNEWT_PKG_apache_mynewt_core__bus_drivers
+#include <bus/drivers/spi_common.h>
+#endif
+
+#if MYNEWT_PKG_apache_mynewt_core__hw_drivers_flash_fs_flash
+#include <fs_flash/fs_flash.h>
+#endif
+
+#if MYNEWT_VAL(PWM_0) || MYNEWT_VAL(PWM_1) || MYNEWT_VAL(PWM_2)
+#include <pwm_stm32/pwm_stm32.h>
+#endif
+
+#if MYNEWT_VAL(PWM_0)
+struct stm32_pwm_conf os_bsp_pwm0_cfg = {
+ .tim = TIM3,
+ .irq = TIM3_IRQn,
+};
+#endif
+#if MYNEWT_VAL(PWM_1)
+struct stm32_pwm_conf os_bsp_pwm1_cfg = {
+ .tim = TIM4,
+ .irq = TIM4_IRQn,
+};
+#endif
+#if MYNEWT_VAL(PWM_2)
+struct stm32_pwm_conf os_bsp_pwm2_cfg = {
+ .tim = TIM1,
+ .irq = TIM1_CC_IRQn,
+};
+#endif
+
+#if MYNEWT_VAL(UART_0)
+const struct stm32_uart_cfg os_bsp_uart0_cfg = {
+ .suc_uart = USART1,
+ .suc_rcc_reg = &RCC->APBENR2,
+ .suc_rcc_dev = RCC_APBENR2_USART1EN,
+ .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS),
+ .suc_pin_af = GPIO_AF0_USART1,
+ .suc_irqn = USART1_IRQn,
+};
+#endif
+
+#if MYNEWT_VAL(UART_1)
+const struct stm32_uart_cfg os_bsp_uart1_cfg = {
+ .suc_uart = USART2,
+ .suc_rcc_reg = &RCC->APBENR1,
+ .suc_rcc_dev = RCC_APBENR1_USART2EN,
+ .suc_pin_tx = MYNEWT_VAL(UART_1_PIN_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_1_PIN_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_1_PIN_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_1_PIN_CTS),
+ .suc_pin_af = GPIO_AF1_USART2,
+ .suc_irqn = USART2_LPUART2_IRQn,
+};
+#endif
+
+#if MYNEWT_VAL(UART_2)
+const struct stm32_uart_cfg os_bsp_uart1_cfg = {
+ .suc_uart = USART3,
+ .suc_rcc_reg = &RCC->APBENR1,
+ .suc_rcc_dev = RCC_APBENR1_USART3EN,
+ .suc_pin_tx = MYNEWT_VAL(UART_2_PIN_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_2_PIN_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_2_PIN_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_2_PIN_CTS),
+ .suc_pin_af = GPIO_AF0_USART3,
+ .suc_irqn = USART3_4_5_6_LPUART1_IRQn,
+};
+#endif
+
+#if MYNEWT_VAL(UART_3)
+const struct stm32_uart_cfg os_bsp_uart1_cfg = {
+ .suc_uart = USART4,
+ .suc_rcc_reg = &RCC->APBENR1,
+ .suc_rcc_dev = RCC_APBENR1_USART4EN,
+ .suc_pin_tx = MYNEWT_VAL(UART_4_PIN_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_4_PIN_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_4_PIN_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_4_PIN_CTS),
+ .suc_pin_af = GPIO_AF0_USART4,
+ .suc_irqn = USART3_4_5_6_LPUART1_IRQn,
+};
+#endif
+
+#if MYNEWT_VAL(UART_4)
+const struct stm32_uart_cfg os_bsp_uart1_cfg = {
+ .suc_uart = USART5,
+ .suc_rcc_reg = &RCC->APBENR1,
+ .suc_rcc_dev = RCC_APBENR1_USART5EN,
+ .suc_pin_tx = MYNEWT_VAL(UART_4_PIN_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_4_PIN_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_4_PIN_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_4_PIN_CTS),
+ .suc_pin_af = GPIO_AF3_USART5,
+ .suc_irqn = USART3_4_5_6_LPUART1_IRQn,
+};
+#endif
+
+#if MYNEWT_VAL(UART_5)
+const struct stm32_uart_cfg os_bsp_uart1_cfg = {
+ .suc_uart = USART6,
+ .suc_rcc_reg = &RCC->APBENR1,
+ .suc_rcc_dev = RCC_APBENR1_USART6EN,
+ .suc_pin_tx = MYNEWT_VAL(UART_5_PIN_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_5_PIN_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_5_PIN_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_5_PIN_CTS),
+ .suc_pin_af = GPIO_AF3_USART6,
+ .suc_irqn = USART3_4_5_6_LPUART1_IRQn,
+};
+#endif
+
+#if MYNEWT_VAL(I2C_0)
+/*
+ * The PB8 and PB9 pins are connected through jumpers in the board to
+ * both ADC_IN and I2C pins. To enable I2C functionality SB147/SB157 need
+ * to be removed (they are the default connections) and SB138/SB143 need
+ * to be shorted.
+ */
+const struct stm32_hal_i2c_cfg os_bsp_i2c0_cfg = {
+ .hic_i2c = I2C1,
+ .hic_rcc_reg = &RCC->APBENR1,
+ .hic_rcc_dev = RCC_APBENR1_I2C1EN,
+ .hic_pin_sda = MYNEWT_VAL(I2C_0_PIN_SDA),
+ .hic_pin_scl = MYNEWT_VAL(I2C_0_PIN_SCL),
+ .hic_pin_af = GPIO_AF6_I2C1,
+ .hic_10bit = 0,
+ .hic_timingr = 0x20404768, /* 100kHz at 216 MHz system clock */
+};
+#endif
+
+#if MYNEWT_VAL(I2C_1)
+const struct stm32_hal_i2c_cfg os_bsp_i2c1_cfg = {
+ .hic_i2c = I2C2,
+ .hic_rcc_reg = &RCC->APBENR1,
+ .hic_rcc_dev = RCC_APBENR1_I2C2EN,
+ .hic_pin_sda = MYNEWT_VAL(I2C_1_PIN_SDA),
+ .hic_pin_scl = MYNEWT_VAL(I2C_1_PIN_SCL),
+ .hic_pin_af = GPIO_AF6_I2C2,
+ .hic_10bit = 0,
+ .hic_timingr = 0x20404768, /* 100kHz at 216 MHz system clock */
+};
+#endif
+
+#if MYNEWT_VAL(I2C_2)
+const struct stm32_hal_i2c_cfg os_bsp_i2c2_cfg = {
+ .hic_i2c = I2C3,
+ .hic_rcc_reg = &RCC->APBENR1,
+ .hic_rcc_dev = RCC_APBENR1_I2C3EN,
+ .hic_pin_sda = MYNEWT_VAL(I2C_2_PIN_SDA),
+ .hic_pin_scl = MYNEWT_VAL(I2C_2_PIN_SCL),
+ .hic_pin_af = GPIO_AF6_I2C3,
+ .hic_10bit = 0,
+ .hic_timingr = 0x20404768, /* 100kHz at 216 MHz system clock */
+};
+#endif
+
+static const struct hal_bsp_mem_dump dump_cfg[] = {
+ [0] = {
+ .hbmd_start = &_ram_start,
+ .hbmd_size = RAM_SIZE,
+ },
+};
+
+extern const struct hal_flash stm32_flash_dev;
+
+#if MYNEWT_VAL(SPIFLASH)
+#if MYNEWT_VAL(BUS_DRIVER_PRESENT)
+struct bus_spi_node_cfg flash_spi_cfg = {
+ .node_cfg.bus_name = MYNEWT_VAL(BSP_FLASH_SPI_BUS),
+ .pin_cs = MYNEWT_VAL(SPIFLASH_SPI_CS_PIN),
+ .mode = MYNEWT_VAL(SPIFLASH_SPI_MODE),
+ .data_order = HAL_SPI_MSB_FIRST,
+ .freq = MYNEWT_VAL(SPIFLASH_BAUDRATE),
+};
+#endif
+#endif
+
+static const struct hal_flash *flash_devs[] = {
+ [0] = &stm32_flash_dev,
+#if MYNEWT_VAL(SPIFLASH)
+ [1] = &spiflash_dev.hal,
+#endif
+#if MYNEWT_PKG_apache_mynewt_core__hw_drivers_flash_fs_flash
+ [2] = &fs_flash_dev.hal,
+#endif
+};
+
+const struct hal_flash *
+hal_bsp_flash_dev(uint8_t id)
+{
+ if (id >= ARRAY_SIZE(flash_devs)) {
+ return NULL;
+ }
+
+ return flash_devs[id];
+}
+
+const struct hal_bsp_mem_dump *
+hal_bsp_core_dump(int *area_cnt)
+{
+ *area_cnt = sizeof(dump_cfg) / sizeof(dump_cfg[0]);
+ return dump_cfg;
+}
+
+void
+hal_bsp_init(void)
+{
+ int rc;
+ (void)rc;
+
+ stm32_periph_create();
+
+#if MYNEWT_VAL(SPIFLASH) && MYNEWT_VAL(BUS_DRIVER_PRESENT)
+ rc = spiflash_create_spi_dev(&spiflash_dev.dev,
+ MYNEWT_VAL(BSP_FLASH_SPI_NAME), &flash_spi_cfg);
+ assert(rc == 0);
+#endif
+}
+
+void
+hal_bsp_deinit(void)
+{
+ RCC->AHBENR = 0x00000100;
+ RCC->APBENR1 = 0x00000000;
+ RCC->APBENR2 = 0x00000000;
+
+ RCC->AHBRSTR = 0x00051103;
+ RCC->APBRSTR1 = 0xFFFFFFB7;
+ RCC->APBRSTR2 = 0x0017D801;
+
+ RCC->AHBRSTR = 0;
+ RCC->APBRSTR1 = 0;
+ RCC->APBRSTR2 = 0;
+}
+
+/**
+ * Returns the configured priority for the given interrupt. If no priority
+ * configured, return the priority passed in
+ *
+ * @param irq_num
+ * @param pri
+ *
+ * @return uint32_t
+ */
+uint32_t
+hal_bsp_get_nvic_priority(int irq_num, uint32_t pri)
+{
+ /* Add any interrupt priorities configured by the bsp here */
+ return pri;
+}
diff --git a/hw/bsp/nucleo-g0b1re/syscfg.yml b/hw/bsp/nucleo-g0b1re/syscfg.yml
new file mode 100644
index 000000000..ecf9d146c
--- /dev/null
+++ b/hw/bsp/nucleo-g0b1re/syscfg.yml
@@ -0,0 +1,78 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+syscfg.defs:
+ STM32_FLASH_SIZE_KB:
+ description: 'Total flash size in KB.'
+ value: 512
+
+ BSP_FLASH_SPI_BUS:
+ description: 'bus name SPIFLASH is connected to'
+ value: '"spi0"'
+
+ BSP_FLASH_SPI_NAME:
+ description: 'SPIFLASH device name'
+ value: '"spiflash0"'
+
+syscfg.vals:
+ REBOOT_LOG_FLASH_AREA: FLASH_AREA_REBOOT_LOG
+ CONFIG_FCB_FLASH_AREA: FLASH_AREA_NFFS
+ NFFS_FLASH_AREA: FLASH_AREA_NFFS
+ COREDUMP_FLASH_AREA: FLASH_AREA_IMAGE_1
+ STM32_CLOCK_VOLTAGESCALING_CONFIG: 'PWR_REGULATOR_VOLTAGE_SCALE1'
+ STM32_CLOCK_HSI: 1
+ STM32_CLOCK_HSE: 0
+ STM32_CLOCK_HSE_BYPASS: 0
+ STM32_CLOCK_PLL_PLLM: RCC_PLLM_DIV1
+ STM32_CLOCK_PLL_PLLN: 8
+ STM32_CLOCK_PLL_PLLP: RCC_PLLP_DIV2
+ STM32_CLOCK_PLL_PLLQ: RCC_PLLQ_DIV2
+ STM32_CLOCK_PLL_PLLR: RCC_PLLR_DIV2
+ STM32_CLOCK_AHB_DIVIDER: 'RCC_SYSCLK_DIV1'
+ STM32_CLOCK_APB1_DIVIDER: 'RCC_HCLK_DIV1'
+ STM32_CLOCK_APB2_DIVIDER: 'RCC_HCLK_DIV1'
+ STM32_CLOCK_APB3_DIVIDER: 'RCC_HCLK_DIV1'
+ STM32_CLOCK_APB4_DIVIDER: 'RCC_HCLK_DIV1'
+ STM32_CLOCK_PLLRGE: 'RCC_PLLVCIRANGE_0'
+ STM32_FLASH_LATENCY: 'FLASH_LATENCY_2'
+ UART_0: 0
+ UART_1: 1
+ UART_0_PIN_TX: 'MCU_GPIO_PORTC(4)'
+ UART_0_PIN_RX: 'MCU_GPIO_PORTC(5)'
+ UART_1_PIN_TX: 'MCU_GPIO_PORTA(2)'
+ UART_1_PIN_RX: 'MCU_GPIO_PORTA(3)'
+ CONSOLE_UART_DEV: '"uart1"'
+ SPI_0_PIN_SS: 'MCU_GPIO_PORTD(14)'
+ SPI_0_PIN_SCK: ARDUINO_PIN_SCK
+ SPI_0_PIN_MISO: ARDUINO_PIN_MISO
+ SPI_0_PIN_MOSI: ARDUINO_PIN_MOSI
+ I2C_0_PIN_SCL: 'MCU_GPIO_PORTB(8)'
+ I2C_0_PIN_SDA: 'MCU_GPIO_PORTB(9)'
+ I2C_1_PIN_SCL: 'MCU_GPIO_PORTF(1)'
+ I2C_1_PIN_SDA: 'MCU_GPIO_PORTF(0)'
+ I2C_2_PIN_SCL: 'MCU_GPIO_PORTA(8)'
+ I2C_2_PIN_SDA: 'MCU_GPIO_PORTC(9)'
+ I2C_3_PIN_SCL: 'MCU_GPIO_PORTD(12)'
+ I2C_3_PIN_SDA: 'MCU_GPIO_PORTD(13)'
+ TIMER_0_TIM: 'TIM15'
+ TIMER_1_TIM: 'TIM16'
+ TIMER_2_TIM: 'TIM17'
+ MYNEWT_DOWNLOADER: stm32_programmer_cli
+ MYNEWT_DOWNLOADER_MFG_IMAGE_FLASH_OFFSET: 0x0C000000
+ JLINK_TARGET: STM32G0B1RE