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Posted to commits@nuttx.apache.org by xi...@apache.org on 2022/07/01 04:14:05 UTC
[incubator-nuttx] branch master updated: New stm32wb chip family
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new 4285274c31 New stm32wb chip family
4285274c31 is described below
commit 4285274c3127c7a9ee52ae769ff1f98434bd591a
Author: Sergey Nikitenko <s....@me.com>
AuthorDate: Thu Jun 30 11:57:20 2022 +0300
New stm32wb chip family
---
arch/arm/Kconfig | 20 +
arch/arm/include/stm32wb/chip.h | 170 ++
arch/arm/include/stm32wb/irq.h | 99 +
arch/arm/include/stm32wb/stm32wb_irq.h | 220 ++
arch/arm/src/stm32wb/Kconfig | 944 +++++++
arch/arm/src/stm32wb/Make.defs | 102 +
arch/arm/src/stm32wb/chip.h | 57 +
arch/arm/src/stm32wb/hardware/stm32wb_crs.h | 103 +
arch/arm/src/stm32wb/hardware/stm32wb_dma.h | 274 ++
arch/arm/src/stm32wb/hardware/stm32wb_dmamux.h | 284 ++
arch/arm/src/stm32wb/hardware/stm32wb_exti.h | 168 ++
arch/arm/src/stm32wb/hardware/stm32wb_flash.h | 359 +++
arch/arm/src/stm32wb/hardware/stm32wb_gpio.h | 319 +++
arch/arm/src/stm32wb/hardware/stm32wb_ipcc.h | 114 +
arch/arm/src/stm32wb/hardware/stm32wb_memorymap.h | 165 ++
arch/arm/src/stm32wb/hardware/stm32wb_pinmap.h | 606 ++++
arch/arm/src/stm32wb/hardware/stm32wb_pwr.h | 324 +++
arch/arm/src/stm32wb/hardware/stm32wb_rcc.h | 877 ++++++
arch/arm/src/stm32wb/hardware/stm32wb_rtc.h | 388 +++
arch/arm/src/stm32wb/hardware/stm32wb_spi.h | 151 +
arch/arm/src/stm32wb/hardware/stm32wb_syscfg.h | 227 ++
arch/arm/src/stm32wb/hardware/stm32wb_tim.h | 1385 ++++++++++
arch/arm/src/stm32wb/hardware/stm32wb_uart.h | 339 +++
arch/arm/src/stm32wb/stm32wb.h | 43 +
arch/arm/src/stm32wb/stm32wb_allocateheap.c | 324 +++
arch/arm/src/stm32wb/stm32wb_dma.c | 1404 ++++++++++
arch/arm/src/stm32wb/stm32wb_dma.h | 281 ++
arch/arm/src/stm32wb/stm32wb_dumpgpio.c | 120 +
arch/arm/src/stm32wb/stm32wb_exti.h | 129 +
arch/arm/src/stm32wb/stm32wb_exti_alarm.c | 135 +
arch/arm/src/stm32wb/stm32wb_exti_gpio.c | 371 +++
arch/arm/src/stm32wb/stm32wb_exti_pwr.c | 142 +
arch/arm/src/stm32wb/stm32wb_exti_wakeup.c | 135 +
arch/arm/src/stm32wb/stm32wb_flash.c | 521 ++++
arch/arm/src/stm32wb/stm32wb_flash.h | 58 +
arch/arm/src/stm32wb/stm32wb_freerun.c | 298 ++
arch/arm/src/stm32wb/stm32wb_freerun.h | 160 ++
arch/arm/src/stm32wb/stm32wb_gpio.c | 399 +++
arch/arm/src/stm32wb/stm32wb_gpio.h | 372 +++
arch/arm/src/stm32wb/stm32wb_idle.c | 192 ++
arch/arm/src/stm32wb/stm32wb_ipcc.c | 120 +
arch/arm/src/stm32wb/stm32wb_ipcc.h | 80 +
arch/arm/src/stm32wb/stm32wb_irq.c | 534 ++++
arch/arm/src/stm32wb/stm32wb_lowputc.c | 319 +++
arch/arm/src/stm32wb/stm32wb_lowputc.h | 64 +
arch/arm/src/stm32wb/stm32wb_mpuinit.c | 100 +
arch/arm/src/stm32wb/stm32wb_mpuinit.h | 63 +
arch/arm/src/stm32wb/stm32wb_oneshot.c | 460 ++++
arch/arm/src/stm32wb/stm32wb_oneshot.h | 196 ++
arch/arm/src/stm32wb/stm32wb_oneshot_lowerhalf.c | 331 +++
arch/arm/src/stm32wb/stm32wb_pm.h | 149 +
arch/arm/src/stm32wb/stm32wb_pminitialize.c | 63 +
arch/arm/src/stm32wb/stm32wb_pmlpr.c | 91 +
arch/arm/src/stm32wb/stm32wb_pmsleep.c | 84 +
arch/arm/src/stm32wb/stm32wb_pmstandby.c | 85 +
arch/arm/src/stm32wb/stm32wb_pmstop.c | 142 +
arch/arm/src/stm32wb/stm32wb_pwr.c | 197 ++
arch/arm/src/stm32wb/stm32wb_pwr.h | 116 +
arch/arm/src/stm32wb/stm32wb_rcc.c | 1005 +++++++
arch/arm/src/stm32wb/stm32wb_rcc.h | 279 ++
arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c | 164 ++
arch/arm/src/stm32wb/stm32wb_rcc_lse.c | 124 +
arch/arm/src/stm32wb/stm32wb_rcc_lsi.c | 72 +
arch/arm/src/stm32wb/stm32wb_rtc.c | 1831 +++++++++++++
arch/arm/src/stm32wb/stm32wb_rtc.h | 315 +++
arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c | 719 +++++
arch/arm/src/stm32wb/stm32wb_serial.c | 2879 ++++++++++++++++++++
arch/arm/src/stm32wb/stm32wb_spi.c | 1818 ++++++++++++
arch/arm/src/stm32wb/stm32wb_spi.h | 157 ++
arch/arm/src/stm32wb/stm32wb_start.c | 233 ++
arch/arm/src/stm32wb/stm32wb_start.h | 45 +
arch/arm/src/stm32wb/stm32wb_tickless.c | 837 ++++++
arch/arm/src/stm32wb/stm32wb_tim.c | 1287 +++++++++
arch/arm/src/stm32wb/stm32wb_tim.h | 252 ++
arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c | 486 ++++
arch/arm/src/stm32wb/stm32wb_timerisr.c | 146 +
arch/arm/src/stm32wb/stm32wb_uart.h | 174 ++
arch/arm/src/stm32wb/stm32wb_uid.c | 46 +
arch/arm/src/stm32wb/stm32wb_uid.h | 36 +
arch/arm/src/stm32wb/stm32wb_userspace.c | 91 +
arch/arm/src/stm32wb/stm32wb_userspace.h | 49 +
arch/arm/src/stm32wb/stm32wb_waste.c | 44 +
arch/arm/src/stm32wb/stm32wb_waste.h | 64 +
boards/Kconfig | 13 +
boards/arm/stm32wb/nucleo-wb55rg/Kconfig | 8 +
boards/arm/stm32wb/nucleo-wb55rg/README.txt | 62 +
.../stm32wb/nucleo-wb55rg/configs/nsh/defconfig | 41 +
boards/arm/stm32wb/nucleo-wb55rg/include/board.h | 202 ++
.../stm32wb/nucleo-wb55rg/include/nucleo-wb55rg.h | 256 ++
boards/arm/stm32wb/nucleo-wb55rg/scripts/Make.defs | 39 +
boards/arm/stm32wb/nucleo-wb55rg/scripts/wb55rg.ld | 114 +
boards/arm/stm32wb/nucleo-wb55rg/src/Makefile | 35 +
.../arm/stm32wb/nucleo-wb55rg/src/nucleo-wb55rg.h | 98 +
.../arm/stm32wb/nucleo-wb55rg/src/stm32_appinit.c | 160 ++
.../arm/stm32wb/nucleo-wb55rg/src/stm32_autoleds.c | 107 +
boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c | 86 +
.../arm/stm32wb/nucleo-wb55rg/src/stm32_userleds.c | 216 ++
97 files changed, 30563 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index da54cacfa5..7d398b39c5 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -431,6 +431,22 @@ config ARCH_CHIP_STM32U5
---help---
STMicro STM32 U5 architectures (ARM Cortex-M33).
+config ARCH_CHIP_STM32WB
+ bool "STMicro STM32 WB"
+ select ARCH_CORTEXM4
+ select ARCH_HAVE_FPU
+ select ARCH_HAVE_MPU
+ select ARCH_HAVE_FETCHADD
+ select ARCH_HAVE_I2CRESET
+ select ARCH_HAVE_HEAPCHECK
+ select ARCH_HAVE_PROGMEM
+ select ARCH_HAVE_SPI_BITORDER
+ select ARCH_HAVE_TICKLESS
+ select ARM_HAVE_MPU_UNIFIED
+ select ARMV7M_HAVE_STACKCHECK
+ ---help---
+ STMicro STM32WB architectures (ARM Cortex-M4).
+
config ARCH_CHIP_STM32WL5
bool "STMicro STM32 WL5"
select ARCH_CORTEXM4
@@ -868,6 +884,7 @@ config ARCH_CHIP
default "stm32l4" if ARCH_CHIP_STM32L4
default "stm32l5" if ARCH_CHIP_STM32L5
default "stm32u5" if ARCH_CHIP_STM32U5
+ default "stm32wb" if ARCH_CHIP_STM32WB
default "stm32wl5" if ARCH_CHIP_STM32WL5
default "str71x" if ARCH_CHIP_STR71X
default "tms570" if ARCH_CHIP_TMS570
@@ -1253,6 +1270,9 @@ endif
if ARCH_CHIP_STM32U5
source "arch/arm/src/stm32u5/Kconfig"
endif
+if ARCH_CHIP_STM32WB
+source arch/arm/src/stm32wb/Kconfig
+endif
if ARCH_CHIP_STM32WL5
source "arch/arm/src/stm32wl5/Kconfig"
endif
diff --git a/arch/arm/include/stm32wb/chip.h b/arch/arm/include/stm32wb/chip.h
new file mode 100644
index 0000000000..4d11c568c0
--- /dev/null
+++ b/arch/arm/include/stm32wb/chip.h
@@ -0,0 +1,170 @@
+/****************************************************************************
+ * arch/arm/include/stm32wb/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_INCLUDE_STM32WB_CHIP_H
+#define __ARCH_ARM_INCLUDE_STM32WB_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+#define STM32WB_NFSMC 0 /* No FSMC */
+#define STM32WB_NBTIM 0 /* No basic timers */
+#define STM32WB_NATIM 1 /* One advanced timers TIM1 */
+#define STM32WB_NGTIM32 1 /* 32-bit general timers TIM2 with DMA */
+#define STM32WB_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
+#define STM32WB_NGTIMNDMA 0 /* No general timers without DMA */
+
+#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \
+ || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55)
+# define STM32WB_NGTIM16 2 /* 16-bit general timers TIM16-17 with DMA */
+#else
+# define STM32WB_NGTIM16 0 /* No 16-bit general timers */
+#endif
+
+#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55)
+# define STM32WB_NDMA 2 /* DMA1-2 with 7 channels each */
+# define STM32WB_NI2S 1 /* SAI1 (dual channel high quality audio) */
+# define STM32WB_NI2C 2 /* I2C1, I2C3 */
+# define STM32WB_NUSBOTG 1 /* USB 2.0 FS */
+# define STM32WB_NCMP 2 /* Two Comparators */
+# if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define STM32WB_NSPI 3 /* SPI1-2, QSPI */
+# else
+# define STM32WB_NSPI 2 /* SPI1, QSPI */
+# endif
+#else
+# define STM32WB_NDMA 1 /* DMA1 with 7 channels */
+# define STM32WB_NI2S 0 /* No SAI */
+# define STM32WB_NI2C 1 /* I2C1 */
+# define STM32WB_NUSBOTG 0 /* No USB */
+# define STM32WB_NCMP 0 /* No Comparators */
+# define STM32WB_NSPI 1 /* SPI1 */
+#endif
+
+#if defined(CONFIG_STM32WB_STM32WB15) || defined(CONFIG_STM32WB_STM32WB35) \
+ || defined(CONFIG_STM32WB_STM32WB55)
+# define STM32WB_NLPUART 1 /* LPUART1 */
+#else
+# define STM32WB_NLPUART 0 /* No LPUART */
+#endif
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define STM32WB_NCAPSENSE 18 /* Capacitive sensing channels */
+#else
+# define STM32WB_NCAPSENSE 0 /* No Capacitive sensing */
+#endif
+
+#if defined(CONFIG_STM32WB_STM32WB55)
+# define STM32WB_NLCD 1 /* One LCD controller with up to 8x40
+ * terminals, depending on subfamily.
+ * 55Cx: 4x13
+ * 55Rx: 4x28
+ * 55Vx: 4x44, 8x40 */
+#else
+# define STM32WB_NLCD 0 /* No LCD */
+#endif
+
+#define STM32WB_NUSART 1 /* USART1 */
+#define STM32WB_NCAN 0 /* No CAN */
+#define STM32WB_NSDIO 0 /* No SDIO interface */
+#define STM32WB_NADC 1 /* ADC1, up to 19-channels */
+#define STM32WB_NDAC 0 /* No DAC */
+#define STM32WB_NCRC 1 /* CRC */
+#define STM32WB_NETHERNET 0 /* No ethernet */
+#define STM32WB_NRNG 1 /* Random number generator (RNG) */
+#define STM32WB_NDCMI 0 /* No digital camera interface (DCMI) */
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_C)
+# define STM32WB_NGPIO 30 /* GPIO[A,B,C,E,H] */
+#elif defined(CONFIG_STM32WB_IO_CONFIG_C_48E)
+# define STM32WB_NGPIO 37 /* GPIO[A,B,C,E,H] */
+#elif defined(CONFIG_STM32WB_IO_CONFIG_C_49)
+# define STM32WB_NGPIO 25 /* GPIO[A,B,C,H] */
+#elif defined(CONFIG_STM32WB_IO_CONFIG_R)
+# define STM32WB_NGPIO 49 /* GPIO[A,B,C,D,E,H] */
+#elif defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define STM32WB_NGPIO 72 /* GPIO[A,B,C,D,E,H] */
+#else
+# error "Unsupported STM32WB chip"
+#endif
+
+/* STM32WB1xCC have 48 Kib:
+ * 1) 12 KiB of SRAM1 beginning at address 0x2000:0000 - 0x2000:3000
+ * 2) 32 KiB of SRAM2a beginning at address 0x2003:0000 - 0x2003:8000
+ * 3) 4 KiB of SRAM2b beginning at address 0x2003:8000 - 0x2003:9000
+ *
+ * STM32WB3xxx have 96 Kib:
+ *
+ * 1) 32 KiB of SRAM1 beginning at address 0x2000:0000 - 0x2000:8000
+ * 2) 32 KiB of SRAM2a beginning at address 0x2003:0000 - 0x2003:8000
+ * 3) 32 KiB of SRAM2b beginning at address 0x2003:8000 - 0x2004:0000
+ *
+ * STM32WB50CG and STM32WB55xC have 128 Kib:
+ *
+ * 1) 64 KiB of SRAM1 beginning at address 0x2000:0000 - 0x2001:0000
+ * 2) 32 KiB of SRAM2a beginning at address 0x2003:0000 - 0x2003:8000
+ * 3) 32 KiB of SRAM2b beginning at address 0x2003:8000 - 0x2004:0000
+ *
+ * STM32WB55x[E,Y,G] have 256 Kib:
+ *
+ * 1) 192 KiB of SRAM1 beginning at address 0x2000:0000 - 0x2001:8000
+ * 2) 32 KiB of SRAM2a beginning at address 0x2003:0000 - 0x2003:8000
+ * 3) 32 KiB of SRAM2b beginning at address 0x2003:8000 - 0x2004:0000
+ */
+
+#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15)
+# define STM32WB_SRAM1_SIZE (12*1024)
+# define STM32WB_SRAM2A_SIZE (32*1024)
+# define STM32WB_SRAM2B_SIZE (4*1024)
+#elif defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB35)
+# define STM32WB_SRAM1_SIZE (32*1024)
+# define STM32WB_SRAM2A_SIZE (32*1024)
+# define STM32WB_SRAM2B_SIZE (32*1024)
+#elif (defined(CONFIG_STM32WB_STM32WB50) || defined(CONFIG_STM32WB_STM32WB55)) \
+ && defined(CONFIG_STM32WB_IO_CONFIG_C)
+# define STM32WB_SRAM1_SIZE (64*1024)
+# define STM32WB_SRAM2A_SIZE (32*1024)
+# define STM32WB_SRAM2B_SIZE (32*1024)
+#elif defined(CONFIG_STM32WB_STM32WB55) && \
+ (defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V))
+# define STM32WB_SRAM1_SIZE (192*1024)
+# define STM32WB_SRAM2A_SIZE (32*1024)
+# define STM32WB_SRAM2B_SIZE (32*1024)
+#else
+# error "Unsupported STM32WB chip"
+#endif
+
+/* NVIC priority levels *****************************************************/
+
+/* 16 Programmable interrupt levels */
+
+#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */
+#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
+#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
+#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
+
+#endif /* __ARCH_ARM_INCLUDE_STM32WB_CHIP_H */
diff --git a/arch/arm/include/stm32wb/irq.h b/arch/arm/include/stm32wb/irq.h
new file mode 100644
index 0000000000..bf75492029
--- /dev/null
+++ b/arch/arm/include/stm32wb/irq.h
@@ -0,0 +1,99 @@
+/****************************************************************************
+ * arch/arm/include/stm32wb/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather,
+ * only indirectly through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_STM32WB_IRQ_H
+#define __ARCH_ARM_INCLUDE_STM32WB_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+/* IRQ numbers. The IRQ number corresponds vector number and hence map
+ * directly to bits in the NVIC. This does, however, waste several words of
+ * memory in the IRQ to handle mapping tables.
+ */
+
+/* Processor Exceptions (vectors 0-15) */
+
+#define STM32WB_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
+ /* Vector 0: Reset stack pointer value */
+ /* Vector 1: Reset (not handler as an IRQ) */
+#define STM32WB_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
+#define STM32WB_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
+#define STM32WB_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
+#define STM32WB_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
+#define STM32WB_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
+ /* Vectors 7-10: Reserved */
+#define STM32WB_IRQ_SVCALL (11) /* Vector 11: SVC call */
+#define STM32WB_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
+ /* Vector 13: Reserved */
+#define STM32WB_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
+#define STM32WB_IRQ_SYSTICK (15) /* Vector 15: System tick */
+
+/* External interrupts (vectors >= 16). These definitions are
+ * chip-specific
+ */
+
+#define STM32WB_IRQ_FIRST (16) /* Vector number of the first external interrupt */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <arch/stm32wb/stm32wb_irq.h>
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_STM32WB_IRQ_H */
diff --git a/arch/arm/include/stm32wb/stm32wb_irq.h b/arch/arm/include/stm32wb/stm32wb_irq.h
new file mode 100644
index 0000000000..13518adb90
--- /dev/null
+++ b/arch/arm/include/stm32wb/stm32wb_irq.h
@@ -0,0 +1,220 @@
+/****************************************************************************
+ * arch/arm/include/stm32wb/stm32wb_irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through arch/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_STM32WB_STM32WB_IRQ_H
+#define __ARCH_ARM_INCLUDE_STM32WB_STM32WB_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+/* IRQ numbers. The IRQ number corresponds vector number and hence map
+ * directly to bits in the NVIC. This does, however, waste several words of
+ * memory in the IRQ to handle mapping tables.
+ *
+ * Processor Exceptions (vectors 0-15). These common definitions can be
+ * found in the file nuttx/arch/arm/include/stm32wb/irq.h which includes
+ * this file
+ *
+ * External interrupts (vectors >= 16)
+ *
+ * These interrupts vectors was implemented based on RM0434 Table 61.
+ *
+ */
+
+#define STM32WB_IRQ_WWDG (STM32WB_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
+#define STM32WB_IRQ_PVD (STM32WB_IRQ_FIRST + 1) /* 1: PVD through EXTI[16] Line detection interrupt */
+
+#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55)
+# define STM32WB_IRQ_PVM1 (STM32WB_IRQ_FIRST + 1) /* 1: PVM1 through EXTI[31] Line detection interrupt */
+#endif
+
+#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) \
+ || defined(CONFIG_STM32WB_STM32WB15)
+# define STM32WB_IRQ_PVM3 (STM32WB_IRQ_FIRST + 1) /* 1: PVM3 through EXTI[33] Line detection interrupt */
+#endif
+
+#define STM32WB_IRQ_TAMPER (STM32WB_IRQ_FIRST + 2) /* 2: Tamper through EXTI[18] interrupts */
+#define STM32WB_IRQ_TIMESTAMP (STM32WB_IRQ_FIRST + 2) /* 2: Time stamp through EXTI[18] interrupts */
+#define STM32WB_IRQ_LSECSS (STM32WB_IRQ_FIRST + 2) /* 2: LSECSS through EXTI[18] interrupts */
+#define STM32WB_IRQ_RTC_WKUP (STM32WB_IRQ_FIRST + 3) /* 3: RTC global interrupt */
+#define STM32WB_IRQ_FLASH (STM32WB_IRQ_FIRST + 4) /* 4: Flash global interrupt */
+#define STM32WB_IRQ_RCC (STM32WB_IRQ_FIRST + 5) /* 5: RCC global interrupt */
+#define STM32WB_IRQ_EXTI0 (STM32WB_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */
+#define STM32WB_IRQ_EXTI1 (STM32WB_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */
+#define STM32WB_IRQ_EXTI2 (STM32WB_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */
+#define STM32WB_IRQ_EXTI3 (STM32WB_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */
+#define STM32WB_IRQ_EXTI4 (STM32WB_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */
+#define STM32WB_IRQ_DMA1CH1 (STM32WB_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */
+#define STM32WB_IRQ_DMA1CH2 (STM32WB_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */
+#define STM32WB_IRQ_DMA1CH3 (STM32WB_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */
+#define STM32WB_IRQ_DMA1CH4 (STM32WB_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */
+#define STM32WB_IRQ_DMA1CH5 (STM32WB_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */
+#define STM32WB_IRQ_DMA1CH6 (STM32WB_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */
+#define STM32WB_IRQ_DMA1CH7 (STM32WB_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */
+#define STM32WB_IRQ_ADC1 (STM32WB_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */
+
+#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55)
+ #define STM32WB_IRQ_USB_HP (STM32WB_IRQ_FIRST + 19) /* 19: USB High Priority Interrupt */
+ #define STM32WB_IRQ_USB_LP (STM32WB_IRQ_FIRST + 20) /* 20: USB Low Priority Interrupt */
+#endif
+
+#define STM32WB_IRQ_C2SEV (STM32WB_IRQ_FIRST + 21) /* 21: CPU2 SEV Interrupt */
+
+#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) \
+ || defined(CONFIG_STM32WB_STM32WB15)
+# define STM32WB_IRQ_COMP (STM32WB_IRQ_FIRST + 22) /* 22: COMP1/COMP2 Interrupts */
+#endif
+
+#define STM32WB_IRQ_EXTI95 (STM32WB_IRQ_FIRST + 23) /* 23: EXTI Lines [9:5] Interrupt */
+#define STM32WB_IRQ_TIM1BRK (STM32WB_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */
+#define STM32WB_IRQ_TIM1UP (STM32WB_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */
+#define STM32WB_IRQ_TIM1TRGCOM (STM32WB_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Communication Interrupts */
+
+#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \
+ || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55)
+# define STM32WB_IRQ_TIM16 (STM32WB_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */
+# define STM32WB_IRQ_TIM17 (STM32WB_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */
+#endif
+
+#define STM32WB_IRQ_TIM1CC (STM32WB_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */
+#define STM32WB_IRQ_TIM2 (STM32WB_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */
+#define STM32WB_IRQ_PKA (STM32WB_IRQ_FIRST + 29) /* 29: PKA Interrupt */
+#define STM32WB_IRQ_I2C1EV (STM32WB_IRQ_FIRST + 30) /* 30: I2C1 event interrupt */
+#define STM32WB_IRQ_I2C1ER (STM32WB_IRQ_FIRST + 31) /* 31: I2C1 error interrupt */
+
+#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55)
+# define STM32WB_IRQ_I2C3EV (STM32WB_IRQ_FIRST + 32) /* 32: I2C3 event interrupt */
+# define STM32WB_IRQ_I2C3ER (STM32WB_IRQ_FIRST + 33) /* 33: I2C3 error interrupt */
+#endif
+
+#define STM32WB_IRQ_SPI1 (STM32WB_IRQ_FIRST + 34) /* 34: SPI1 global interrupt */
+
+#if defined(CONFIG_STM32WB_STM32WB55)
+# define STM32WB_IRQ_SPI2 (STM32WB_IRQ_FIRST + 35) /* 35: SPI2 global interrupt */
+#endif
+
+#define STM32WB_IRQ_USART1 (STM32WB_IRQ_FIRST + 36) /* 36: USART1 global interrupt */
+
+#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) \
+ || defined(CONFIG_STM32WB_STM32WB15)
+# define STM32WB_IRQ_LPUART1 (STM32WB_IRQ_FIRST + 37) /* 37: LPUART1 global interrupt */
+#endif
+
+#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55)
+# define STM32WB_IRQ_SAI1 (STM32WB_IRQ_FIRST + 38) /* 38: SAI1 A/B global interrupt */
+#endif
+
+#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) \
+ || defined(CONFIG_STM32WB_STM32WB55)
+# define STM32WB_IRQ_TSC (STM32WB_IRQ_FIRST + 39) /* 39: TSC global interrupt */
+#endif
+
+#define STM32WB_IRQ_EXTI1510 (STM32WB_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */
+#define STM32WB_IRQ_RTCALRM (STM32WB_IRQ_FIRST + 41) /* 41: RTC alarm A/B interrupt */
+
+#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55)
+# define STM32WB_IRQ_CRS (STM32WB_IRQ_FIRST + 42) /* 42: CRS interrupt */
+#endif
+
+#define STM32WB_IRQ_PWRSOTF (STM32WB_IRQ_FIRST + 43) /* 43: PWR switching on the fly interrupt */
+#define STM32WB_IRQ_PWRBLEACT (STM32WB_IRQ_FIRST + 43) /* 43: PWR end of BLE activity interrupt */
+#define STM32WB_IRQ_PWRRFPHASE (STM32WB_IRQ_FIRST + 43) /* 43: PWR end of critical radio phase interrupt */
+
+#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \
+ || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55)
+# define STM32WB_IRQ_PWR802ACT (STM32WB_IRQ_FIRST + 43) /* 43: PWR end of 802.15.4 activity interrupt */
+#endif
+
+#define STM32WB_IRQ_IPCCRX (STM32WB_IRQ_FIRST + 44) /* 44: IPCC RX occupied interrupt */
+#define STM32WB_IRQ_IPCCTX (STM32WB_IRQ_FIRST + 45) /* 45: IPCC TX free interrupt */
+#define STM32WB_IRQ_HSEM (STM32WB_IRQ_FIRST + 46) /* 46: Semaphore interrupt 0 to CPU1 */
+#define STM32WB_IRQ_LPTIM1 (STM32WB_IRQ_FIRST + 47) /* 47: LPTIM1 global interrupt */
+#define STM32WB_IRQ_LPTIM2 (STM32WB_IRQ_FIRST + 48) /* 48: LPTIM2 global interrupt */
+
+#if defined(CONFIG_STM32WB_STM32WB55)
+# define STM32WB_IRQ_LCD (STM32WB_IRQ_FIRST + 49) /* 49: LCD global interrupt */
+#endif
+
+#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55)
+# define STM32WB_IRQ_QUADSPI (STM32WB_IRQ_FIRST + 50) /* 50: QUADSPI global interrupt */
+# define STM32WB_IRQ_AES1 (STM32WB_IRQ_FIRST + 51) /* 51: AES1 crypto global interrupt */
+#endif
+
+#define STM32WB_IRQ_AES2 (STM32WB_IRQ_FIRST + 52) /* 52: AES2 crypto global interrupt */
+#define STM32WB_IRQ_RNG (STM32WB_IRQ_FIRST + 53) /* 53: RNG global interrupt */
+#define STM32WB_IRQ_FPU (STM32WB_IRQ_FIRST + 54) /* 54: FPU global interrupt */
+
+#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55)
+# define STM32WB_IRQ_DMA2CH1 (STM32WB_IRQ_FIRST + 55) /* 55: DMA2 Channel 1 global interrupt */
+# define STM32WB_IRQ_DMA2CH2 (STM32WB_IRQ_FIRST + 56) /* 56: DMA2 Channel 2 global interrupt */
+# define STM32WB_IRQ_DMA2CH3 (STM32WB_IRQ_FIRST + 57) /* 57: DMA2 Channel 3 global interrupt */
+# define STM32WB_IRQ_DMA2CH4 (STM32WB_IRQ_FIRST + 58) /* 58: DMA2 Channel 4 global interrupt */
+# define STM32WB_IRQ_DMA2CH5 (STM32WB_IRQ_FIRST + 59) /* 59: DMA2 Channel 5 global interrupt */
+# define STM32WB_IRQ_DMA2CH6 (STM32WB_IRQ_FIRST + 60) /* 60: DMA2 Channel 6 global interrupt */
+# define STM32WB_IRQ_DMA2CH7 (STM32WB_IRQ_FIRST + 61) /* 61: DMA2 Channel 7 global interrupt */
+#endif
+
+#define STM32WB_IRQ_DMAMUX1 (STM32WB_IRQ_FIRST + 62) /* 62: DMAMUX1 overrun interrupt */
+
+#define STM32WB_IRQ_NEXTINTS 63
+
+/* (EXTI interrupts do not use IRQ numbers) */
+
+#define NR_IRQS (STM32WB_IRQ_FIRST + STM32WB_IRQ_NEXTINTS)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_STM32WB_STM32WB_IRQ_H */
diff --git a/arch/arm/src/stm32wb/Kconfig b/arch/arm/src/stm32wb/Kconfig
new file mode 100644
index 0000000000..9396f76881
--- /dev/null
+++ b/arch/arm/src/stm32wb/Kconfig
@@ -0,0 +1,944 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_CHIP_STM32WB
+
+comment "STM32WB Configuration Options"
+
+choice
+ prompt "STM32 WB Chip Selection"
+ default ARCH_CHIP_STM32WB55RG
+ depends on ARCH_CHIP_STM32WB
+
+config ARCH_CHIP_STM32WB10CC
+ bool "STM32WB10CC"
+ select STM32WB_STM32WB10
+ select STM32WB_IO_CONFIG_C
+ select STM32WB_FLASH_CONFIG_C_320
+ ---help---
+ STM32 WB Cortex M4, 320 Kb FLASH, 12+32+4 Kb SRAM
+
+config ARCH_CHIP_STM32WB15CC
+ bool "STM32WB15CC"
+ select STM32WB_STM32WB15
+ select STM32WB_IO_CONFIG_C
+ select STM32WB_FLASH_CONFIG_C_320
+ ---help---
+ STM32 WB Cortex M4, 320 Kb FLASH, 12+32+4 Kb SRAM
+
+config ARCH_CHIP_STM32WB30CE
+ bool "STM32WB30CE"
+ select STM32WB_STM32WB30
+ select STM32WB_IO_CONFIG_C
+ select STM32WB_FLASH_CONFIG_E_512
+ ---help---
+ STM32 WB Cortex M4, 512 Kb FLASH, 32+32+32 Kb SRAM
+
+config ARCH_CHIP_STM32WB50CG
+ bool "STM32WB50CG"
+ select STM32WB_STM32WB50
+ select STM32WB_IO_CONFIG_C
+ select STM32WB_FLASH_CONFIG_G_1024
+ ---help---
+ STM32 WB Cortex M4, 1024 Kb FLASH, 64+32+32 Kb SRAM
+
+config ARCH_CHIP_STM32WB35CC
+ bool "STM32WB35CC"
+ select STM32WB_STM32WB35
+ select STM32WB_IO_CONFIG_C
+ select STM32WB_FLASH_CONFIG_C_256
+ ---help---
+ STM32 WB Cortex M4, 256 Kb FLASH, 32+32+32 Kb SRAM
+
+config ARCH_CHIP_STM32WB35CE
+ bool "STM32WB35CE"
+ select STM32WB_STM32WB35
+ select STM32WB_IO_CONFIG_C
+ select STM32WB_FLASH_CONFIG_E_512
+ ---help---
+ STM32 WB Cortex M4, 512 Kb FLASH, 32+32+32 Kb SRAM
+
+config ARCH_CHIP_STM32WB55CC
+ bool "STM32WB55CC"
+ select STM32WB_STM32WB55
+ select STM32WB_IO_CONFIG_C
+ select STM32WB_FLASH_CONFIG_C_256
+ ---help---
+ STM32 WB Cortex M4, 256 Kb FLASH, 64+32+32 Kb SRAM
+
+config ARCH_CHIP_STM32WB55RC
+ bool "STM32WB55RC"
+ select STM32WB_STM32WB55
+ select STM32WB_IO_CONFIG_R
+ select STM32WB_FLASH_CONFIG_C_256
+ ---help---
+ STM32 WB Cortex M4, 256 Kb FLASH, 64+32+32 Kb SRAM
+
+config ARCH_CHIP_STM32WB55VC
+ bool "STM32WB55VC"
+ select STM32WB_STM32WB55
+ select STM32WB_IO_CONFIG_V
+ select STM32WB_FLASH_CONFIG_C_256
+ ---help---
+ STM32 WB Cortex M4, 256 Kb FLASH, 64+32+32 Kb SRAM
+
+config ARCH_CHIP_STM32WB55CE
+ bool "STM32WB55CE"
+ select STM32WB_STM32WB55
+ select STM32WB_IO_CONFIG_C
+ select STM32WB_FLASH_CONFIG_E_512
+ ---help---
+ STM32 WB Cortex M4, 512 Kb FLASH, 192+32+32 Kb SRAM
+
+config ARCH_CHIP_STM32WB55RE
+ bool "STM32WB55RE"
+ select STM32WB_STM32WB55
+ select STM32WB_IO_CONFIG_R
+ select STM32WB_FLASH_CONFIG_E_512
+ ---help---
+ STM32 WB Cortex M4, 512 Kb FLASH, 192+32+32 Kb SRAM
+
+config ARCH_CHIP_STM32WB55VE
+ bool "STM32WB55VE"
+ select STM32WB_STM32WB55
+ select STM32WB_IO_CONFIG_V
+ select STM32WB_FLASH_CONFIG_E_512
+ ---help---
+ STM32 WB Cortex M4, 512 Kb FLASH, 192+32+32 Kb SRAM
+
+config ARCH_CHIP_STM32WB55VY
+ bool "STM32WB55VY"
+ select STM32WB_STM32WB55
+ select STM32WB_IO_CONFIG_V
+ select STM32WB_FLASH_CONFIG_Y_640
+ ---help---
+ STM32 WB Cortex M4, 640 Kb FLASH, 192+32+32 Kb SRAM
+
+config ARCH_CHIP_STM32WB55CG
+ bool "STM32WB55CG"
+ select STM32WB_STM32WB55
+ select STM32WB_IO_CONFIG_C
+ select STM32WB_FLASH_CONFIG_G_1024
+ ---help---
+ STM32 WB Cortex M4, 1024 Kb FLASH, 192+32+32 Kb SRAM
+
+config ARCH_CHIP_STM32WB55RG
+ bool "STM32WB55RG"
+ select STM32WB_STM32WB55
+ select STM32WB_IO_CONFIG_R
+ select STM32WB_FLASH_CONFIG_G_1024
+ ---help---
+ STM32 WB Cortex M4, 1024 Kb FLASH, 192+32+32 Kb SRAM
+
+config ARCH_CHIP_STM32WB55VG
+ bool "STM32WB55VG"
+ select STM32WB_STM32WB55
+ select STM32WB_IO_CONFIG_V
+ select STM32WB_FLASH_CONFIG_G_1024
+ ---help---
+ STM32 WB Cortex M4, 1024 Kb FLASH, 192+32+32 Kb SRAM
+
+endchoice # STM32 WB Chip Selection
+
+# Chip product lines
+
+config STM32WB_STM32WB10
+ # STM32WB10 Value Line
+ bool
+ default n
+ select STM32WB_HAVE_TSC
+
+config STM32WB_STM32WB15
+ # STM32WB15 Standard Line
+ bool
+ default n
+ select STM32WB_HAVE_TSC
+ select STM32WB_HAVE_LPUART
+ select STM32WB_HAVE_SMPS if !ARCH_CHIP_STM32WB15CCUXE
+
+config STM32WB_STM32WB30
+ # STM32WB30 Value Line
+ bool
+ default n
+ select STM32WB_HAVE_HSI48
+ select STM32WB_HAVE_TIM16
+ select STM32WB_HAVE_TIM17
+
+config STM32WB_STM32WB50
+ # STM32WB50 Value Line
+ bool
+ default n
+ select STM32WB_HAVE_HSI48
+ select STM32WB_HAVE_TIM16
+ select STM32WB_HAVE_TIM17
+
+config STM32WB_STM32WB35
+ # STM32WB35 Standard Line
+ bool
+ default n
+ select STM32WB_HAVE_HSI48
+ select STM32WB_HAVE_DMA2
+ select STM32WB_HAVE_TIM16
+ select STM32WB_HAVE_TIM17
+ select STM32WB_HAVE_I2C3
+ select STM32WB_HAVE_QSPI
+ select STM32WB_HAVE_USB
+ select STM32WB_HAVE_SAI
+ select STM32WB_HAVE_COMP
+ select STM32WB_HAVE_SMPS
+
+config STM32WB_STM32WB55
+ # STM32WB55 Standard Line
+ bool
+ default n
+ select STM32WB_HAVE_HSI48
+ select STM32WB_HAVE_DMA2
+ select STM32WB_HAVE_TIM16
+ select STM32WB_HAVE_TIM17
+ select STM32WB_HAVE_I2C3
+ select STM32WB_HAVE_SPI2 if STM32WB_IO_CONFIG_R || STM32WB_IO_CONFIG_V
+ select STM32WB_HAVE_QSPI
+ select STM32WB_HAVE_USB
+ select STM32WB_HAVE_SAI
+ select STM32WB_HAVE_COMP
+ select STM32WB_HAVE_LPUART
+ select STM32WB_HAVE_TSC if STM32WB_IO_CONFIG_R || STM32WB_IO_CONFIG_V
+ select STM32WB_HAVE_LCD
+ select STM32WB_HAVE_SMPS
+
+choice
+ prompt "Override Flash Size Designator"
+ depends on ARCH_CHIP_STM32WB
+ default STM32WB_FLASH_OVERRIDE_DEFAULT
+ ---help---
+ STM32WB series parts numbering (sans the package type) ends with a letter
+ that designates the FLASH size.
+
+ Designator Size in KiB
+ C 256 or 320
+ E 512
+ Y 640
+ G 1024
+
+ This configuration option defaults to using the configuration based on that designator
+ or the default smaller size if there is no last character designator is present in the
+ STM32WB Chip Selection.
+
+ Examples:
+ If the STM32WB55RG is chosen, the Flash configuration would be 'G', if a variant of
+ the part with a 2048 KiB Flash is released in the future one could simply select
+ the 'I' designator here.
+
+ If an STM32WB Series parts is chosen the default Flash configuration will be set
+ herein and can be changed.
+
+config STM32WB_FLASH_OVERRIDE_DEFAULT
+ bool "Default"
+
+config STM32WB_FLASH_OVERRIDE_C_256
+ bool "C 256 KB"
+
+config STM32WB_FLASH_OVERRIDE_C_320
+ bool "C 320 KB"
+
+config STM32WB_FLASH_OVERRIDE_E_512
+ bool "E 512 KB"
+
+config STM32WB_FLASH_OVERRIDE_Y_640
+ bool "Y 640 KB"
+
+config STM32WB_FLASH_OVERRIDE_G_1024
+ bool "G 1024 KB"
+
+endchoice # "Override Flash Size Designator"
+
+# Flash configurations
+
+config STM32WB_FLASH_CONFIG_C_256
+ bool
+ default n
+
+config STM32WB_FLASH_CONFIG_C_320
+ bool
+ default n
+
+config STM32WB_FLASH_CONFIG_E_512
+ bool
+ default n
+
+config STM32WB_FLASH_CONFIG_Y_640
+ bool
+ default n
+
+config STM32WB_FLASH_CONFIG_G_1024
+ bool
+ default n
+
+# Pin/package configurations
+
+config STM32WB_IO_CONFIG_C
+ # UFQFPN48 package
+ bool
+ default n
+ select STM32WB_GPIO_HAVE_PORTE
+
+config STM32WB_IO_CONFIG_C_48E
+ # UFQFPN48E package
+ bool
+ default n
+ select STM32WB_GPIO_HAVE_PORTE
+
+config STM32WB_IO_CONFIG_C_49
+ # WLCSP49 package
+ bool
+ default n
+
+config STM32WB_IO_CONFIG_R
+ # VFQFPN68 package
+ bool
+ default n
+ select STM32WB_GPIO_HAVE_PORTD
+ select STM32WB_GPIO_HAVE_PORTE
+
+config STM32WB_IO_CONFIG_V
+ # WLCSP100 and UFBGA129 packages
+ bool
+ default n
+ select STM32WB_GPIO_HAVE_PORTD
+ select STM32WB_GPIO_HAVE_PORTE
+
+comment "STM32WB SRAM2a and SRAM2b Options"
+
+config STM32WB_SRAM2A_HEAP
+ bool "SRAM2a is used for heap"
+ default n
+
+config STM32WB_SRAM2A_USER_BASE_OFFSET
+ int "SRAM2a user application base offset"
+ default 2048
+ range 0 32768
+ depends on STM32WB_SRAM2A_HEAP
+ ---help---
+ The beginning part of the SRAM2a memory can be used by RF stack. The
+ available space for the user application can be obtained from the
+ release notes for STM32WB coprocessor wireless binaries.
+
+config STM32WB_SRAM2A_USER_SIZE
+ int "SRAM2a user application size"
+ default 8192
+ range 0 32768
+ depends on STM32WB_SRAM2A_HEAP
+ ---help---
+ The ending part of the SRAM2a memory contains a secure section, which
+ cannot be read nor written by CPU1. The secure start address for the
+ SRAM2a memory can be read from the SBRSA option byte. When CPU2 update
+ support required, there must be some free sectors just below the secure
+ memory to support CPU2 firmware updates requiring more sectors to be
+ secure.
+
+config STM32WB_SRAM2A_INIT
+ bool "SRAM2a is initialized to zero"
+ default y
+ depends on STM32WB_SRAM2A_HEAP
+ ---help---
+ The STM32WB SRAM2a region has parity checking. However, when the system
+ powers on, the memory is in an unknown state, and reads from uninitialized
+ memory can trigger parity faults from the random data. This can be
+ avoided by first writing to all locations to force the parity into a valid
+ state.
+ However, if the SRAM2a is being retained in Standby mode, this may be
+ undesirable (because it will destroy the contents). In that case, the board
+ should handle the initialization itself at the appropriate time.
+
+config STM32WB_SRAM2B_HEAP
+ bool "SRAM2b is used for heap"
+ default n
+
+config STM32WB_SRAM2B_USER_SIZE
+ int "SRAM2b user application size"
+ default 32768
+ range 0 32768
+ depends on STM32WB_SRAM2B_HEAP
+ ---help---
+ For any CPU2 firmware supporting the BLE protocol the ending part of
+ the SRAM2b memory contains a secure section, which cannot be read nor
+ written by CPU1. The secure start address for the SRAM2b memory can be
+ read from the SNBRSA option byte. When CPU2 update support required,
+ there must be some free sectors just below the secure memory to support
+ CPU2 firmware updates requiring more sectors to be secure. The SRAM2b
+ memory is all secure for any CPU2 firmware supporting the Thread protocol.
+
+config STM32WB_SRAM2B_INIT
+ bool "SRAM2b is initialized to zero"
+ default y
+ depends on STM32WB_SRAM2B_HEAP
+ ---help---
+ The STM32WB SRAM2b region has parity checking. However, when the system
+ powers on, the memory is in an unknown state, and reads from uninitialized
+ memory can trigger parity faults from the random data. This can be
+ avoided by first writing to all locations to force the parity into a valid
+ state.
+
+comment "STM32WB Peripherals"
+
+menu "STM32WB Peripheral Support"
+
+# These "hidden" settings determine whether a peripheral option is available
+# for the selected MCU
+
+config STM32WB_GPIO_HAVE_PORTD
+ bool
+ default n
+
+config STM32WB_GPIO_HAVE_PORTE
+ bool
+ default n
+
+config STM32WB_HAVE_COMP
+ bool
+ default n
+
+config STM32WB_HAVE_LPUART
+ bool
+ default n
+
+config STM32WB_HAVE_DMA2
+ bool
+ default n
+
+config STM32WB_HAVE_TIM16
+ bool
+ default n
+
+config STM32WB_HAVE_TIM17
+ bool
+ default n
+
+config STM32WB_HAVE_SPI2
+ bool
+ default n
+
+config STM32WB_HAVE_I2C3
+ bool
+ default n
+
+config STM32WB_HAVE_SAI
+ bool
+ default n
+
+config STM32WB_HAVE_LCD
+ bool
+ default n
+
+config STM32WB_HAVE_TSC
+ bool
+ default n
+
+config STM32WB_HAVE_USB
+ bool
+ default n
+
+config STM32WB_HAVE_QSPI
+ bool
+ default n
+
+config STM32WB_HAVE_SMPS
+ bool
+ default n
+
+# These are the peripheral selections proper
+
+config STM32WB_RTC
+ bool "RTC"
+ default n
+ select RTC
+
+# These "hidden" settings are the OR of individual peripheral selections
+# indicating that the general capability is required.
+
+config STM32WB_ADC
+ bool
+ default n
+
+config STM32WB_DMAMUX
+ bool
+ default n
+
+config STM32WB_DMA
+ bool
+ default n
+ select STM32WB_DMAMUX
+
+config STM32WB_IPCC
+ bool
+ default n
+
+config STM32WB_I2C
+ bool
+ default n
+
+config STM32WB_SAI
+ bool
+ default n
+
+config STM32WB_SPI
+ bool
+ default n
+
+config STM32WB_USART
+ bool
+ default n
+
+config STM32WB_LPTIM
+ bool
+ default n
+
+# These are the peripheral selections proper
+
+comment "AHB1 Peripherals"
+
+config STM32WB_DMA1
+ bool "DMA1"
+ default n
+ select ARCH_DMA
+ select STM32WB_DMA
+
+config STM32WB_DMA2
+ bool "DMA2"
+ default n
+ depends on STM32WB_HAVE_DMA2
+ select ARCH_DMA
+ select STM32WB_DMA
+
+config STM32WB_CRC
+ bool "CRC"
+ default n
+
+comment "APB1 Peripherals"
+
+config STM32WB_PWR
+ bool "PWR"
+ default n
+
+config STM32WB_TIM2
+ bool "TIM2"
+ default n
+
+config STM32WB_SPI2
+ bool "SPI2"
+ default n
+ depends on STM32WB_HAVE_SPI2
+ select SPI
+ select STM32WB_SPI
+
+config STM32WB_LPTIM1
+ bool "LPTIM1"
+ default n
+ select STM32WB_LPTIM
+
+config STM32WB_LPTIM2
+ bool "LPTIM2"
+ default n
+ select STM32WB_LPTIM
+
+config STM32WB_LPUART1
+ bool "LPUART1"
+ default n
+ depends on STM32WB_HAVE_LPUART
+ select ARCH_HAVE_SERIAL_TERMIOS
+ select ARCH_HAVE_LPUART1
+ select STM32WB_USART
+
+comment "APB2 Peripherals"
+
+config STM32WB_SYSCFG
+ bool "SYSCFG"
+ default y
+
+config STM32WB_TIM1
+ bool "TIM1"
+ default n
+
+config STM32WB_SPI1
+ bool "SPI1"
+ default n
+ select SPI
+ select STM32WB_SPI
+
+config STM32WB_USART1
+ bool "USART1"
+ default n
+ select ARCH_HAVE_SERIAL_TERMIOS
+ select STM32WB_USART
+
+config STM32WB_TIM16
+ bool "TIM16"
+ default n
+ depends on STM32WB_HAVE_TIM16
+
+config STM32WB_TIM17
+ bool "TIM17"
+ default n
+ depends on STM32WB_HAVE_TIM17
+
+endmenu
+
+config STM32WB_FLASH_PREFETCH
+ bool "Enable FLASH Pre-fetch"
+ default y
+ ---help---
+ Enable FLASH prefetch
+
+config STM32WB_DISABLE_IDLE_SLEEP_DURING_DEBUG
+ bool "Disable IDLE Sleep (WFI) in debug mode"
+ default n
+ ---help---
+ In debug configuration, disables the WFI instruction in the IDLE loop
+ to prevent the JTAG from disconnecting. With some JTAG debuggers, such
+ as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI
+ instruction, the debugger will disconnect, terminating the debug session.
+
+config ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG
+ bool "Custom clock configuration"
+ default n
+ ---help---
+ Enables special, board-specific STM32WB clock configuration.
+
+config STM32WB_HAVE_RTC_SUBSECONDS
+ bool
+ select ARCH_HAVE_RTC_SUBSECONDS
+ default y
+
+menu "RTC Configuration"
+ depends on STM32WB_RTC
+
+config STM32WB_RTC_MAGIC_REG
+ int "BKP register"
+ default 0
+ range 0 31
+ ---help---
+ The BKP register used to store/check the Magic value to determine if
+ RTC is already setup
+
+config STM32WB_RTC_MAGIC
+ hex "RTC Magic 1"
+ default 0xfacefeed
+ ---help---
+ Value used as Magic to determine if the RTC is already setup
+
+config STM32WB_RTC_MAGIC_TIME_SET
+ hex "RTC Magic 2"
+ default 0xf00dface
+ ---help---
+ Value used as Magic to determine if the RTC has been setup and has
+ time set
+
+choice
+ prompt "RTC clock source"
+ default STM32WB_RTC_LSECLOCK
+ depends on STM32WB_RTC
+
+config STM32WB_RTC_LSECLOCK
+ bool "LSE clock"
+ ---help---
+ Drive the RTC with the LSE clock
+
+config STM32WB_RTC_LSICLOCK
+ bool "LSI clock"
+ ---help---
+ Drive the RTC with the LSI clock
+
+config STM32WB_RTC_HSECLOCK
+ bool "HSE clock"
+ ---help---
+ Drive the RTC with the HSE clock, divided down to 1MHz.
+
+endchoice
+
+if STM32WB_RTC_LSECLOCK
+
+config STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY
+ int "LSE oscillator drive capability level at LSE start-up"
+ default 0
+ range 0 3
+ ---help---
+ 0 = Low drive capability (default)
+ 1 = Medium low drive capability
+ 2 = Medium high drive capability
+ 3 = High drive capability
+
+config STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY
+ int "LSE oscillator drive capability level after LSE start-up"
+ default 0
+ range 0 3
+ ---help---
+ 0 = Low drive capability (default)
+ 1 = Medium low drive capability
+ 2 = Medium high drive capability
+ 3 = High drive capability
+
+endif # STM32WB_RTC_LSECLOCK
+
+endmenu # RTC Configuration
+
+menu "Timer Configuration"
+
+if SCHED_TICKLESS
+
+config STM32WB_TICKLESS_TIMER
+ int "Tickless hardware timer"
+ default 2
+ range 1 17
+ depends on !STM32WB_TICKLESS_SYSTICK
+ ---help---
+ If the Tickless OS feature is enabled, then one clock must be
+ assigned to provided the timer needed by the OS.
+
+config STM32WB_TICKLESS_CHANNEL
+ int "Tickless timer channel"
+ default 1
+ range 1 4
+ ---help---
+ If the Tickless OS feature is enabled, the one clock must be
+ assigned to provided the free-running timer needed by the OS
+ and one channel on that clock is needed to handle intervals.
+
+endif # SCHED_TICKLESS
+
+config STM32WB_ONESHOT
+ bool "TIM one-shot wrapper"
+ default n
+ ---help---
+ Enable a wrapper around the low level timer/counter functions to
+ support one-shot timer.
+
+config STM32WB_FREERUN
+ bool "TIM free-running wrapper"
+ default n
+ ---help---
+ Enable a wrapper around the low level timer/counter functions to
+ support a free-running timer.
+
+config STM32WB_ONESHOT_MAXTIMERS
+ int "Maximum number of oneshot timers"
+ default 1
+ range 1 8
+ depends on STM32WB_ONESHOT
+ ---help---
+ Determines the maximum number of oneshot timers that can be
+ supported. This setting pre-allocates some minimal support for each
+ of the timers and places an upper limit on the number of oneshot
+ timers that you can use.
+
+endmenu # Timer Configuration
+
+config STM32WB_SERIALDRIVER
+ bool
+
+menu "[LP]U[S]ART Configuration"
+ depends on STM32WB_LPUART1 || STM32WB_USART1
+
+choice
+ prompt "LPUART1 Driver Configuration"
+ default STM32WB_LPUART1_SERIALDRIVER
+ depends on STM32WB_LPUART1
+
+config STM32WB_LPUART1_SERIALDRIVER
+ bool "Standard serial driver"
+ select LPUART1_SERIALDRIVER
+ select STM32WB_SERIALDRIVER
+
+endchoice # LPUART1 Driver Configuration
+
+if LPUART1_SERIALDRIVER
+
+config LPUART1_RS485
+ bool "RS-485 on LPUART1"
+ default n
+ depends on STM32WB_LPUART1
+ ---help---
+ Enable RS-485 interface on LPUART1. Your board config will have to
+ provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be
+ used with LPUART1_RXDMA.
+
+config LPUART1_RS485_DIR_POLARITY
+ int "LPUART1 RS-485 DIR pin polarity"
+ default 1
+ range 0 1
+ depends on LPUART1_RS485
+ ---help---
+ Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which
+ enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+config LPUART1_RXDMA
+ bool "LPUART1 Rx DMA"
+ default n
+ depends on STM32WB_LPUART1 && STM32WB_DMA
+ ---help---
+ In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+endif # LPUART1_SERIALDRIVER
+
+choice
+ prompt "USART1 Driver Configuration"
+ default STM32WB_USART1_SERIALDRIVER
+ depends on STM32WB_USART1
+
+config STM32WB_USART1_SERIALDRIVER
+ bool "Standard serial driver"
+ select USART1_SERIALDRIVER
+ select STM32WB_SERIALDRIVER
+
+endchoice # USART1 Driver Configuration
+
+if USART1_SERIALDRIVER
+
+config USART1_RS485
+ bool "RS-485 on USART1"
+ default n
+ depends on STM32WB_USART1
+ ---help---
+ Enable RS-485 interface on USART1. Your board config will have to
+ provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be
+ used with USART1_RXDMA.
+
+config USART1_RS485_DIR_POLARITY
+ int "USART1 RS-485 DIR pin polarity"
+ default 1
+ range 0 1
+ depends on USART1_RS485
+ ---help---
+ Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which
+ enables TX (0 - low / nTXEN, 1 - high / TXEN).
+
+config USART1_RXDMA
+ bool "USART1 Rx DMA"
+ default n
+ depends on STM32WB_USART1 && STM32WB_DMA
+ ---help---
+ In high data rate usage, Rx DMA may eliminate Rx overrun errors
+
+endif # USART1_SERIALDRIVER
+
+if STM32WB_SERIALDRIVER
+
+comment "Serial Driver Configuration"
+
+config STM32WB_SERIAL_RXDMA_BUFFER_SIZE
+ int "Rx DMA buffer size"
+ default 32
+ depends on USART1_RXDMA
+ ---help---
+ The DMA buffer size when using RX DMA to emulate a FIFO.
+
+ When streaming data, the generic serial layer will be called
+ every time the FIFO receives half this number of bytes.
+
+ Value given here will be rounded up to next multiple of 32 bytes.
+
+config STM32WB_SERIAL_DISABLE_REORDERING
+ bool "Disable reordering of ttySx devices."
+ depends on STM32WB_USART1
+ default n
+ ---help---
+ NuttX per default reorders the serial ports (/dev/ttySx) so that the
+ console is always on /dev/ttyS0. If more than one UART is in use this
+ can, however, have the side-effect that all port mappings
+ (hardware USART1 -> /dev/ttyS0) change if the console is moved to another
+ UART. This is in particular relevant if a project uses the USB console
+ in some boards and a serial console in other boards, but does not
+ want the side effect of having all serial port names change when just
+ the console is moved from serial to USB.
+
+config STM32WB_FLOWCONTROL_BROKEN
+ bool "Use Software UART RTS flow control"
+ depends on STM32WB_USART1
+ default n
+ ---help---
+ Enable UART RTS flow control using Software. Because STM
+ Current STM32WB have broken HW based RTS behavior (they assert
+ nRTS after every byte received) Enable this setting workaround
+ this issue by using software based management of RTS
+
+config STM32WB_USART_BREAKS
+ bool "Add TIOxSBRK to support sending Breaks"
+ depends on STM32WB_USART1
+ default n
+ ---help---
+ Add TIOCxBRK routines to send a line break per the STM32WB manual, the
+ break will be a pulse based on the value M. This is not a BSD compatible
+ break.
+
+config STM32WB_SERIALBRK_BSDCOMPAT
+ bool "Use GPIO To send Break"
+ depends on STM32WB_USART1 && STM32WB_USART_BREAKS
+ default n
+ ---help---
+ Enable using GPIO on the TX pin to send a BSD compatible break:
+ TIOCSBRK will start the break and TIOCCBRK will end the break.
+ The current STM32WB U[S]ARTS have no way to leave the break (TX=LOW)
+ on because the SW starts the break and then the HW automatically clears
+ the break. This makes it is difficult to sent a long break.
+
+config STM32WB_USART_SINGLEWIRE
+ bool "Single Wire Support"
+ default n
+ depends on STM32WB_USART1
+ ---help---
+ Enable single wire UART support. The option enables support for the
+ TIOCSSINGLEWIRE ioctl in the STM32WB serial driver.
+
+config STM32WB_USART_INVERT
+ bool "Signal Invert Support"
+ default n
+ depends on STM32WB_USART1
+ ---help---
+ Enable signal inversion UART support. The option enables support for the
+ TIOCSINVERT ioctl in the STM32WB serial driver.
+
+config STM32WB_USART_SWAP
+ bool "Swap RX/TX pins support"
+ default n
+ depends on STM32WB_USART1
+ ---help---
+ Enable RX/TX pin swapping support. The option enables support for the
+ TIOCSSWAP ioctl in the STM32WB serial driver.
+
+if PM
+
+config STM32WB_PM_SERIAL_ACTIVITY
+ int "PM serial activity"
+ default 10
+ ---help---
+ PM activity reported to power management logic on every serial
+ interrupt.
+
+endif
+
+endif # STM32WB_SERIALDRIVER
+
+endmenu # [LP]U[S]ART Configuration
+
+menu "SPI Configuration"
+ depends on STM32WB_SPI1 || STM32WB_SPI2
+
+config STM32WB_SPI_INTERRUPTS
+ bool "Interrupt driver SPI"
+ default n
+ ---help---
+ Select to enable interrupt driven SPI support. Non-interrupt-driven,
+ poll-waiting is recommended if the interrupt rate would be to high in
+ the interrupt driven case.
+
+config STM32WB_SPI_DMA
+ bool "SPI DMA"
+ depends on STM32WB_DMA
+ default n
+ ---help---
+ Use DMA to improve SPI transfer performance. Cannot be used with STM32WB_SPI_INTERRUPT.
+
+endmenu
+
+endif # ARCH_CHIP_STM32WB
diff --git a/arch/arm/src/stm32wb/Make.defs b/arch/arm/src/stm32wb/Make.defs
new file mode 100644
index 0000000000..a0c9611422
--- /dev/null
+++ b/arch/arm/src/stm32wb/Make.defs
@@ -0,0 +1,102 @@
+############################################################################
+# arch/arm/src/stm32wb/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+# The start-up, "head", file. Only common vectors are support so there
+# isn't one.
+
+# Common ARM and Cortex-M4 files (copied from stm32/Make.defs)
+
+include armv7-m/Make.defs
+
+# Required STM32WB files
+
+CHIP_CSRCS = stm32wb_allocateheap.c stm32wb_exti_gpio.c stm32wb_gpio.c
+CHIP_CSRCS += stm32wb_irq.c stm32wb_lowputc.c stm32wb_rcc.c stm32wb_spi.c
+CHIP_CSRCS += stm32wb_serial.c stm32wb_start.c stm32wb_waste.c stm32wb_uid.c
+CHIP_CSRCS += stm32wb_rcc_lse.c stm32wb_rcc_lsi.c
+CHIP_CSRCS += stm32wb_pwr.c stm32wb_tim.c
+CHIP_CSRCS += stm32wb_flash.c
+
+ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
+CHIP_CSRCS += stm32wb_idle.c
+endif
+
+ifeq ($(CONFIG_TIMER),y)
+CHIP_CSRCS += stm32wb_tim_lowerhalf.c
+endif
+
+ifneq ($(CONFIG_SCHED_TICKLESS),y)
+CHIP_CSRCS += stm32wb_timerisr.c
+else
+CHIP_CSRCS += stm32wb_tickless.c
+endif
+
+ifeq ($(CONFIG_STM32WB_ONESHOT),y)
+CHIP_CSRCS += stm32wb_oneshot.c stm32wb_oneshot_lowerhalf.c
+endif
+
+ifeq ($(CONFIG_STM32WB_FREERUN),y)
+CHIP_CSRCS += stm32wb_freerun.c
+endif
+
+ifeq ($(CONFIG_BUILD_PROTECTED),y)
+CHIP_CSRCS += stm32wb_userspace.c stm32wb_mpuinit.c
+endif
+
+ifeq ($(CONFIG_STM32WB_HAVE_HSI48),y)
+CHIP_CSRCS += stm32wb_rcc_hsi48.c
+endif
+
+ifeq ($(CONFIG_STM32WB_DMA),y)
+CHIP_CSRCS += stm32wb_dma.c
+endif
+
+ifeq ($(CONFIG_PM),y)
+CHIP_CSRCS += stm32wb_pmlpr.c stm32wb_pmsleep.c stm32wb_pmstandby.c
+CHIP_CSRCS += stm32wb_pmstop.c
+
+ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y)
+CHIP_CSRCS += stm32wb_pminitialize.c
+endif
+endif
+
+ifeq ($(CONFIG_STM32WB_PWR),y)
+CHIP_CSRCS += stm32wb_exti_pwr.c
+endif
+
+ifeq ($(CONFIG_STM32WB_IPCC),y)
+CHIP_CSRCS += stm32wb_ipcc.c
+endif
+
+ifeq ($(CONFIG_STM32WB_RTC),y)
+ifeq ($(CONFIG_RTC_ALARM),y)
+CHIP_CSRCS += stm32wb_exti_alarm.c
+endif
+ifeq ($(CONFIG_RTC_PERIODIC),y)
+CHIP_CSRCS += stm32wb_exti_wakeup.c
+endif
+ifeq ($(CONFIG_RTC_DRIVER),y)
+CHIP_CSRCS += stm32wb_rtc.c stm32wb_rtc_lowerhalf.c
+endif
+endif
+
+ifeq ($(CONFIG_DEBUG_FEATURES),y)
+CHIP_CSRCS += stm32wb_dumpgpio.c
+endif
diff --git a/arch/arm/src/stm32wb/chip.h b/arch/arm/src/stm32wb/chip.h
new file mode 100644
index 0000000000..cc5fdc7633
--- /dev/null
+++ b/arch/arm/src/stm32wb/chip.h
@@ -0,0 +1,57 @@
+/****************************************************************************
+ * arch/arm/src/stm32wb/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32WB_CHIP_H
+#define __ARCH_ARM_SRC_STM32WB_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/* Include the memory map and the chip definitions file.
+ * Other chip hardware files should then include this file for the proper
+ * setup.
+ */
+
+#include <arch/irq.h>
+#include <arch/stm32wb/chip.h>
+#include "hardware/stm32wb_pinmap.h"
+#include "hardware/stm32wb_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* If the common ARMv7-M vector handling logic is used, then it expects the
+ * following definition in this file that provides the number of supported
+ * external interrupts which, for this architecture, is provided in the
+ * arch/stm32wb/chip.h header file.
+ */
+
+#define ARMV7M_PERIPHERAL_INTERRUPTS STM32WB_IRQ_NEXTINTS
+
+/* Cache line sizes (in bytes) for the STM32WB */
+
+#define ARMV7M_DCACHE_LINESIZE 32 /* 32 bytes (4 x 64 bits) */
+#define ARMV7M_ICACHE_LINESIZE 32 /* 32 bytes (4 x 64 bits) */
+
+#endif /* __ARCH_ARM_SRC_STM32WB_CHIP_H */
diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_crs.h b/arch/arm/src/stm32wb/hardware/stm32wb_crs.h
new file mode 100644
index 0000000000..240a51e864
--- /dev/null
+++ b/arch/arm/src/stm32wb/hardware/stm32wb_crs.h
@@ -0,0 +1,103 @@
+/****************************************************************************
+ * arch/arm/src/stm32wb/hardware/stm32wb_crs.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_CRS_H
+#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_CRS_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define STM32WB_CRS_CR_OFFSET 0x0000 /* CRS control register */
+#define STM32WB_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */
+#define STM32WB_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */
+#define STM32WB_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */
+
+/* Register Addresses *******************************************************/
+
+#define STM32WB_CRS_CR (STM32WB_CRS_BASE + STM32WB_CRS_CR_OFFSET)
+#define STM32WB_CRS_CFGR (STM32WB_CRS_BASE + STM32WB_CRS_CFGR_OFFSET)
+#define STM32WB_CRS_ISR (STM32WB_CRS_BASE + STM32WB_CRS_ISR_OFFSET)
+#define STM32WB_CRS_ICR (STM32WB_CRS_BASE + STM32WB_CRS_ICR_OFFSET)
+
+/* Register Bitfield Definitions ********************************************/
+
+/* CRS control register (CR) */
+
+#define CRS_CR_SYNCOKIE (1 << 0) /* Bit 0: SYNC event OK interrupt enable */
+#define CRS_CR_SYNCWARNIE (1 << 1) /* Bit 1: SYNC warning interrupt enable */
+#define CRS_CR_ERRIE (1 << 2) /* Bit 2: Synchronization or Trimming error interrupt enabled */
+#define CRS_CR_ESYNCIE (1 << 3) /* Bit 3: Expected SYNC interrupt enable */
+#define CRS_CR_CEN (1 << 5) /* Bit 5: Frequency error counter enable */
+#define CRS_CR_AUTOTRIMEN (1 << 6) /* Bit 6: Automatic trimming enabled */
+#define CRS_CR_SWSYNC (1 << 7) /* Bit 7: Generate software SYNC event */
+#define CRS_CR_TRIM_SHIFT (8) /* Bits 8-13: HSI48 oscillator smooth trimming */
+#define CRS_CR_TRIM_MASK (0x3f << CRS_CR_TRIM_SHIFT)
+
+/* CRS configuration register (CFGR) */
+
+#define CRS_CFGR_RELOAD_SHIFT (0) /* Bits 0-15: Counter reload value */
+#define CRS_CFGR_RELOAD_MASK (0xffff << CRS_CFGR_RELOAD_SHIFT)
+#define CRS_CFGR_FELIM_SHIFT (16) /* Bits 16-23: Frequency error limit */
+#define CRS_CFGR_FELIM_MASK (0xff << CRS_CFGR_FELIM_SHIFT)
+#define CRS_CFGR_SYNCDIV_SHIFT (24) /* Bits 24-26: SYNC divider */
+#define CRS_CFGR_SYNCDIV_MASK (0x7 << CRS_CFGR_SYNCDIV_SHIFT)
+# define CRS_CFGR_SYNCDIV_d1 (0x0 << CRS_CFGR_SYNCDIV_SHIFT) /* 000: SYNC not divided */
+# define CRS_CFGR_SYNCDIV_d2 (0x1 << CRS_CFGR_SYNCDIV_SHIFT) /* 001: SYNC divided by 2 */
+# define CRS_CFGR_SYNCDIV_d4 (0x2 << CRS_CFGR_SYNCDIV_SHIFT) /* 010: SYNC divided by 4 */
+# define CRS_CFGR_SYNCDIV_d8 (0x3 << CRS_CFGR_SYNCDIV_SHIFT) /* 011: SYNC divided by 8 */
+# define CRS_CFGR_SYNCDIV_d16 (0x4 << CRS_CFGR_SYNCDIV_SHIFT) /* 100: SYNC divided by 16 */
+# define CRS_CFGR_SYNCDIV_d32 (0x5 << CRS_CFGR_SYNCDIV_SHIFT) /* 101: SYNC divided by 32 */
+# define CRS_CFGR_SYNCDIV_d64 (0x6 << CRS_CFGR_SYNCDIV_SHIFT) /* 110: SYNC divided by 64 */
+# define CRS_CFGR_SYNCDIV_d128 (0x7 << CRS_CFGR_SYNCDIV_SHIFT) /* 111: SYNC divided by 128 */
+
+#define CRS_CFGR_SYNCSRC_SHIFT (28) /* Bits 28-29: SYNC signal source selection */
+#define CRS_CFGR_SYNCSRC_MASK (0x3 << CRS_CFGR_SYNCSRC_SHIFT)
+# define CRS_CFGR_SYNCSRC_GPIO (0x0 << CRS_CFGR_SYNCSRC_SHIFT) /* 00: GPIO as SYNC signal source */
+# define CRS_CFGR_SYNCSRC_LSE (0x1 << CRS_CFGR_SYNCSRC_SHIFT) /* 01: LSE as SYNC signal source */
+# define CRS_CFGR_SYNCSRC_USBSOF (0x2 << CRS_CFGR_SYNCSRC_SHIFT) /* 10: USB SOF as SYNC signal source */
+
+#define CRS_CFGR_SYNCPOL (1 << 31) /* SYNC polarity selection */
+# define CRS_CFGR_SYNCPOL_RISING (0 << 31) /* 0: SYNC active on rising edge */
+# define CRS_CFGR_SYNCPOL_FALLING (1 << 31) /* 1: SYNC active on falling edge */
+
+/* CRS interrupt and status register (ISR) */
+
+#define CRS_ISR_SYNCOKF (1 << 0) /* Bit 0: SYNC event OK flag */
+#define CRS_ISR_SYNCWARNF (1 << 1) /* Bit 1: SYNC warning flag */
+#define CRS_ISR_ERRF (1 << 2) /* Bit 2: Error flag */
+#define CRS_ISR_ESYNCF (1 << 3) /* Bit 3: Expected SYNC flag */
+#define CRS_ISR_SYNCERR (1 << 8) /* Bit 8: SYNC error */
+#define CRS_ISR_SYNCMISS (1 << 9) /* Bit 9: SYNC missed */
+#define CRS_ISR_TRIMOVF (1 << 10) /* Bit 10: Trimming overflow or underflow */
+#define CRS_ISR_FEDIR (1 << 15) /* Bit 15: Frequency error direction */
+#define CRS_ISR_FECAP_SHIFT (16) /* Bits 16-31: Frequency error capture */
+#define CRS_ISR_FECAP_MASK (0xffff << CRS_ISR_FECAP_SHIFT)
+
+/* CRS interrupt flag clear register (ICR) */
+
+#define CRS_ICR_SYNCOKC (1 << 0) /* Bit 0: SYNC event OK clear flag */
+#define CRS_ICR_SYNCWARNC (1 << 1) /* Bit 1: SYNC warning clear flag */
+#define CRS_ICR_ERRC (1 << 2) /* Bit 2: Error clear flag */
+#define CRS_ICR_ESYNCC (1 << 3) /* Bit 3: Expected SYNC clear flag */
+
+#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_CRS_H */
diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_dma.h b/arch/arm/src/stm32wb/hardware/stm32wb_dma.h
new file mode 100644
index 0000000000..1d6f075bea
--- /dev/null
+++ b/arch/arm/src/stm32wb/hardware/stm32wb_dma.h
@@ -0,0 +1,274 @@
+/****************************************************************************
+ * arch/arm/src/stm32wb/hardware/stm32wb_dma.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_DMA_H
+#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_DMA_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* 14 Channels Total: 7 DMA1 Channels(1-7) and 7 DMA2 channels (1-7) */
+
+#define DMA1 0
+#define DMA2 1
+
+/* Register Offsets *********************************************************/
+
+#define STM32WB_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */
+#define STM32WB_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */
+
+#define STM32WB_DMACHAN_OFFSET(n) (0x0014 * (n))
+#define STM32WB_DMACHAN1_OFFSET 0x0000
+#define STM32WB_DMACHAN2_OFFSET 0x0014
+#define STM32WB_DMACHAN3_OFFSET 0x0028
+#define STM32WB_DMACHAN4_OFFSET 0x003c
+#define STM32WB_DMACHAN5_OFFSET 0x0050
+#define STM32WB_DMACHAN6_OFFSET 0x0064
+#define STM32WB_DMACHAN7_OFFSET 0x0078
+
+#define STM32WB_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */
+#define STM32WB_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */
+#define STM32WB_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */
+#define STM32WB_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */
+
+#define STM32WB_DMA_CCR_OFFSET(n) (STM32WB_DMACHAN_CCR_OFFSET + STM32WB_DMACHAN_OFFSET(n))
+#define STM32WB_DMA_CNDTR_OFFSET(n) (STM32WB_DMACHAN_CNDTR_OFFSET + STM32WB_DMACHAN_OFFSET(n))
+#define STM32WB_DMA_CPAR_OFFSET(n) (STM32WB_DMACHAN_CPAR_OFFSET + STM32WB_DMACHAN_OFFSET(n))
+#define STM32WB_DMA_CMAR_OFFSET(n) (STM32WB_DMACHAN_CMAR_OFFSET + STM32WB_DMACHAN_OFFSET(n))
+
+#define STM32WB_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */
+#define STM32WB_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */
+#define STM32WB_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */
+#define STM32WB_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */
+#define STM32WB_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */
+#define STM32WB_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */
+#define STM32WB_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */
+
+#define STM32WB_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */
+#define STM32WB_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */
+#define STM32WB_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */
+#define STM32WB_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */
+#define STM32WB_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */
+#define STM32WB_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */
+#define STM32WB_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */
+
+#define STM32WB_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */
+#define STM32WB_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */
+#define STM32WB_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */
+#define STM32WB_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */
+#define STM32WB_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */
+#define STM32WB_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */
+#define STM32WB_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */
+
+#define STM32WB_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */
+#define STM32WB_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */
+#define STM32WB_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */
+#define STM32WB_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */
+#define STM32WB_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */
+#define STM32WB_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */
+#define STM32WB_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */
+
+/* Register Addresses *******************************************************/
+
+#define STM32WB_DMA1_ISRC (STM32WB_DMA1_BASE + STM32WB_DMA_ISR_OFFSET)
+#define STM32WB_DMA1_IFCR (STM32WB_DMA1_BASE + STM32WB_DMA_IFCR_OFFSET)
+
+#define STM32WB_DMA1_CCR(n) (STM32WB_DMA1_BASE + STM32WB_DMA_CCR_OFFSET(n))
+#define STM32WB_DMA1_CCR1 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR1_OFFSET)
+#define STM32WB_DMA1_CCR2 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR2_OFFSET)
+#define STM32WB_DMA1_CCR3 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR3_OFFSET)
+#define STM32WB_DMA1_CCR4 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR4_OFFSET)
+#define STM32WB_DMA1_CCR5 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR5_OFFSET)
+#define STM32WB_DMA1_CCR6 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR6_OFFSET)
+#define STM32WB_DMA1_CCR7 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR7_OFFSET)
+
+#define STM32WB_DMA1_CNDTR(n) (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR_OFFSET(n))
+#define STM32WB_DMA1_CNDTR1 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR1_OFFSET)
+#define STM32WB_DMA1_CNDTR2 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR2_OFFSET)
+#define STM32WB_DMA1_CNDTR3 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR3_OFFSET)
+#define STM32WB_DMA1_CNDTR4 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR4_OFFSET)
+#define STM32WB_DMA1_CNDTR5 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR5_OFFSET)
+#define STM32WB_DMA1_CNDTR6 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR6_OFFSET)
+#define STM32WB_DMA1_CNDTR7 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR7_OFFSET)
+
+#define STM32WB_DMA1_CPAR(n) (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR_OFFSET(n))
+#define STM32WB_DMA1_CPAR1 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR1_OFFSET)
+#define STM32WB_DMA1_CPAR2 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR2_OFFSET)
+#define STM32WB_DMA1_CPAR3 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR3_OFFSET)
+#define STM32WB_DMA1_CPAR4 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR4_OFFSET)
+#define STM32WB_DMA1_CPAR5 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR5_OFFSET)
+#define STM32WB_DMA1_CPAR6 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR6_OFFSET)
+#define STM32WB_DMA1_CPAR7 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR7_OFFSET)
+
+#define STM32WB_DMA1_CMAR(n) (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR_OFFSET(n))
+#define STM32WB_DMA1_CMAR1 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR1_OFFSET)
+#define STM32WB_DMA1_CMAR2 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR2_OFFSET)
+#define STM32WB_DMA1_CMAR3 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR3_OFFSET)
+#define STM32WB_DMA1_CMAR4 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR4_OFFSET)
+#define STM32WB_DMA1_CMAR5 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR5_OFFSET)
+#define STM32WB_DMA1_CMAR6 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR6_OFFSET)
+#define STM32WB_DMA1_CMAR7 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR7_OFFSET)
+
+#define STM32WB_DMA2_ISRC (STM32WB_DMA2_BASE + STM32WB_DMA_ISR_OFFSET)
+#define STM32WB_DMA2_IFCR (STM32WB_DMA2_BASE + STM32WB_DMA_IFCR_OFFSET)
+
+#define STM32WB_DMA2_CCR(n) (STM32WB_DMA2_BASE + STM32WB_DMA_CCR_OFFSET(n))
+#define STM32WB_DMA2_CCR1 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR1_OFFSET)
+#define STM32WB_DMA2_CCR2 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR2_OFFSET)
+#define STM32WB_DMA2_CCR3 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR3_OFFSET)
+#define STM32WB_DMA2_CCR4 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR4_OFFSET)
+#define STM32WB_DMA2_CCR5 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR5_OFFSET)
+#define STM32WB_DMA2_CCR6 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR6_OFFSET)
+#define STM32WB_DMA2_CCR7 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR7_OFFSET)
+
+#define STM32WB_DMA2_CNDTR(n) (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR_OFFSET(n))
+#define STM32WB_DMA2_CNDTR1 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR1_OFFSET)
+#define STM32WB_DMA2_CNDTR2 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR2_OFFSET)
+#define STM32WB_DMA2_CNDTR3 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR3_OFFSET)
+#define STM32WB_DMA2_CNDTR4 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR4_OFFSET)
+#define STM32WB_DMA2_CNDTR5 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR5_OFFSET)
+#define STM32WB_DMA2_CNDTR6 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR6_OFFSET)
+#define STM32WB_DMA2_CNDTR7 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR7_OFFSET)
+
+#define STM32WB_DMA2_CPAR(n) (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR_OFFSET(n))
+#define STM32WB_DMA2_CPAR1 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR1_OFFSET)
+#define STM32WB_DMA2_CPAR2 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR2_OFFSET)
+#define STM32WB_DMA2_CPAR3 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR3_OFFSET)
+#define STM32WB_DMA2_CPAR4 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR4_OFFSET)
+#define STM32WB_DMA2_CPAR5 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR5_OFFSET)
+#define STM32WB_DMA2_CPAR6 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR6_OFFSET)
+#define STM32WB_DMA2_CPAR7 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR7_OFFSET)
+
+#define STM32WB_DMA2_CMAR(n) (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR_OFFSET(n))
+#define STM32WB_DMA2_CMAR1 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR1_OFFSET)
+#define STM32WB_DMA2_CMAR2 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR2_OFFSET)
+#define STM32WB_DMA2_CMAR3 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR3_OFFSET)
+#define STM32WB_DMA2_CMAR4 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR4_OFFSET)
+#define STM32WB_DMA2_CMAR5 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR5_OFFSET)
+#define STM32WB_DMA2_CMAR6 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR6_OFFSET)
+#define STM32WB_DMA2_CMAR7 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR7_OFFSET)
+
+/* Register Bitfield Definitions ********************************************/
+
+#define DMA_CHAN_SHIFT(n) ((n) << 2)
+#define DMA_CHAN_MASK 0x0f
+#define DMA_CHAN_GIF_BIT (1 << 0) /* Bit 0: Channel Global interrupt flag */
+#define DMA_CHAN_TCIF_BIT (1 << 1) /* Bit 1: Channel Transfer Complete flag */
+#define DMA_CHAN_HTIF_BIT (1 << 2) /* Bit 2: Channel Half Transfer flag */
+#define DMA_CHAN_TEIF_BIT (1 << 3) /* Bit 3: Channel Transfer Error flag */
+
+/* DMA interrupt status register */
+
+#define DMA_ISR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n)
+#define DMA_ISR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_ISR_CHAN_SHIFT(n))
+#define DMA_ISR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt status */
+#define DMA_ISR_CHAN1_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN1_SHIFT)
+#define DMA_ISR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt status */
+#define DMA_ISR_CHAN2_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN2_SHIFT)
+#define DMA_ISR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt status */
+#define DMA_ISR_CHAN3_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN3_SHIFT)
+#define DMA_ISR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt status */
+#define DMA_ISR_CHAN4_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN4_SHIFT)
+#define DMA_ISR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt status */
+#define DMA_ISR_CHAN5_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN5_SHIFT)
+#define DMA_ISR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt status */
+#define DMA_ISR_CHAN6_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN6_SHIFT)
+#define DMA_ISR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt status */
+#define DMA_ISR_CHAN7_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN7_SHIFT)
+
+#define DMA_ISR_GIF(n) (DMA_CHAN_GIF_BIT << DMA_ISR_CHAN_SHIFT(n))
+#define DMA_ISR_TCIF(n) (DMA_CHAN_TCIF_BIT << DMA_ISR_CHAN_SHIFT(n))
+#define DMA_ISR_HTIF(n) (DMA_CHAN_HTIF_BIT << DMA_ISR_CHAN_SHIFT(n))
+#define DMA_ISR_TEIF(n) (DMA_CHAN_TEIF_BIT << DMA_ISR_CHAN_SHIFT(n))
+
+/* DMA interrupt flag clear register */
+
+#define DMA_IFCR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n)
+#define DMA_IFCR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_IFCR_CHAN_SHIFT(n))
+#define DMA_IFCR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt flag clear */
+#define DMA_IFCR_CHAN1_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN1_SHIFT)
+#define DMA_IFCR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt flag clear */
+#define DMA_IFCR_CHAN2_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN2_SHIFT)
+#define DMA_IFCR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt flag clear */
+#define DMA_IFCR_CHAN3_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN3_SHIFT)
+#define DMA_IFCR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt flag clear */
+#define DMA_IFCR_CHAN4_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN4_SHIFT)
+#define DMA_IFCR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt flag clear */
+#define DMA_IFCR_CHAN5_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN5_SHIFT)
+#define DMA_IFCR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt flag clear */
+#define DMA_IFCR_CHAN6_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN6_SHIFT)
+#define DMA_IFCR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt flag clear */
+#define DMA_IFCR_CHAN7_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN7_SHIFT)
+#define DMA_IFCR_ALLCHANNELS (0x0fffffff)
+
+#define DMA_IFCR_CGIF(n) (DMA_CHAN_GIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
+#define DMA_IFCR_CTCIF(n) (DMA_CHAN_TCIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
+#define DMA_IFCR_CHTIF(n) (DMA_CHAN_HTIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
+#define DMA_IFCR_CTEIF(n) (DMA_CHAN_TEIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
+
+/* DMA channel configuration register */
+
+#define DMA_CCR_EN (1 << 0) /* Bit 0: Channel enable */
+#define DMA_CCR_TCIE (1 << 1) /* Bit 1: Transfer complete interrupt enable */
+#define DMA_CCR_HTIE (1 << 2) /* Bit 2: Half Transfer interrupt enable */
+#define DMA_CCR_TEIE (1 << 3) /* Bit 3: Transfer error interrupt enable */
+#define DMA_CCR_DIR (1 << 4) /* Bit 4: Data transfer direction */
+#define DMA_CCR_CIRC (1 << 5) /* Bit 5: Circular mode */
+#define DMA_CCR_PINC (1 << 6) /* Bit 6: Peripheral increment mode */
+#define DMA_CCR_MINC (1 << 7) /* Bit 7: Memory increment mode */
+#define DMA_CCR_PSIZE_SHIFT (8) /* Bits 8-9: Peripheral size */
+#define DMA_CCR_PSIZE_MASK (3 << DMA_CCR_PSIZE_SHIFT)
+# define DMA_CCR_PSIZE_8BITS (0 << DMA_CCR_PSIZE_SHIFT) /* 00: 8-bits */
+# define DMA_CCR_PSIZE_16BITS (1 << DMA_CCR_PSIZE_SHIFT) /* 01: 16-bits */
+# define DMA_CCR_PSIZE_32BITS (2 << DMA_CCR_PSIZE_SHIFT) /* 10: 32-bits */
+
+#define DMA_CCR_MSIZE_SHIFT (10) /* Bits 10-11: Memory size */
+#define DMA_CCR_MSIZE_MASK (3 << DMA_CCR_MSIZE_SHIFT)
+# define DMA_CCR_MSIZE_8BITS (0 << DMA_CCR_MSIZE_SHIFT) /* 00: 8-bits */
+# define DMA_CCR_MSIZE_16BITS (1 << DMA_CCR_MSIZE_SHIFT) /* 01: 16-bits */
+# define DMA_CCR_MSIZE_32BITS (2 << DMA_CCR_MSIZE_SHIFT) /* 10: 32-bits */
+
+#define DMA_CCR_PL_SHIFT (12) /* Bits 12-13: Channel Priority level */
+#define DMA_CCR_PL_MASK (3 << DMA_CCR_PL_SHIFT)
+# define DMA_CCR_PRILO (0 << DMA_CCR_PL_SHIFT) /* 00: Low */
+# define DMA_CCR_PRIMED (1 << DMA_CCR_PL_SHIFT) /* 01: Medium */
+# define DMA_CCR_PRIHI (2 << DMA_CCR_PL_SHIFT) /* 10: High */
+# define DMA_CCR_PRIVERYHI (3 << DMA_CCR_PL_SHIFT) /* 11: Very high */
+
+#define DMA_CCR_MEM2MEM (1 << 14) /* Bit 14: Memory to memory mode */
+
+#define DMA_CCR_ALLINTS (DMA_CCR_TEIE | DMA_CCR_HTIE | DMA_CCR_TCIE)
+
+/* DMA channel number of data register */
+
+#define DMA_CNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */
+#define DMA_CNDTR_NDT_MASK (0xffff << DMA_CNDTR_NDT_SHIFT)
+
+/* NOTE: DMA channel mapping is done through DMAMUX1. */
+
+#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_DMA_H */
diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_dmamux.h b/arch/arm/src/stm32wb/hardware/stm32wb_dmamux.h
new file mode 100644
index 0000000000..bbc39cbf1f
--- /dev/null
+++ b/arch/arm/src/stm32wb/hardware/stm32wb_dmamux.h
@@ -0,0 +1,284 @@
+/****************************************************************************
+ * arch/arm/src/stm32wb/hardware/stm32wb_dmamux.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_DMAMUX_H
+#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_DMAMUX_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip.h"
+#include "stm32wb_dma.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define DMAMUX1 0
+
+/* Register Offsets *********************************************************/
+
+#define STM32WB_DMAMUX_CXCR_OFFSET(x) (0x0000 + 0x0004 * (x)) /* DMAMUX1 request line multiplexer channel x configuration register */
+#define STM32WB_DMAMUX_C0CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(0)
+#define STM32WB_DMAMUX_C1CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(1)
+#define STM32WB_DMAMUX_C2CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(2)
+#define STM32WB_DMAMUX_C3CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(3)
+#define STM32WB_DMAMUX_C4CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(4)
+#define STM32WB_DMAMUX_C5CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(5)
+#define STM32WB_DMAMUX_C6CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(6)
+#define STM32WB_DMAMUX_C7CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(7)
+#define STM32WB_DMAMUX_C8CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(8)
+#define STM32WB_DMAMUX_C9CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(9)
+#define STM32WB_DMAMUX_C10CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(10)
+#define STM32WB_DMAMUX_C11CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(11)
+#define STM32WB_DMAMUX_C12CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(12)
+#define STM32WB_DMAMUX_C13CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(13)
+ /* 0x034-0x07C: Reserved */
+#define STM32WB_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX1 request line multiplexer interrupt channel status register */
+#define STM32WB_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX1 request line multiplexer interrupt clear flag register */
+ /* 0x088-0x0FC: Reserved */
+
+#define STM32WB_DMAMUX_RGXCR_OFFSET(x) (0x0100 + 0x004 * (x)) /* DMAMUX1 request generator channel x configuration register */
+#define STM32WB_DMAMUX_RG0CR_OFFSET STM32WB_DMAMUX_RGXCR_OFFSET(0)
+#define STM32WB_DMAMUX_RG1CR_OFFSET STM32WB_DMAMUX_RGXCR_OFFSET(1)
+#define STM32WB_DMAMUX_RG2CR_OFFSET STM32WB_DMAMUX_RGXCR_OFFSET(2)
+#define STM32WB_DMAMUX_RG3CR_OFFSET STM32WB_DMAMUX_RGXCR_OFFSET(3)
+#define STM32WB_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX1 request generator interrupt status register */
+#define STM32WB_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX1 request generator interrupt clear flag register */
+ /* 0x148-0x3fc: Reserved */
+
+/* Register Addresses *******************************************************/
+
+#define STM32WB_DMAMUX1_CXCR(x) (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_CXCR_OFFSET(x))
+#define STM32WB_DMAMUX1_C0CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C0CR_OFFSET)
+#define STM32WB_DMAMUX1_C1CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C1CR_OFFSET)
+#define STM32WB_DMAMUX1_C2CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C2CR_OFFSET)
+#define STM32WB_DMAMUX1_C3CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C3CR_OFFSET)
+#define STM32WB_DMAMUX1_C4CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C4CR_OFFSET)
+#define STM32WB_DMAMUX1_C5CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C5CR_OFFSET)
+#define STM32WB_DMAMUX1_C6CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C6CR_OFFSET)
+#define STM32WB_DMAMUX1_C7CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C7CR_OFFSET)
+#define STM32WB_DMAMUX1_C8CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C8CR_OFFSET)
+#define STM32WB_DMAMUX1_C9CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C9CR_OFFSET)
+#define STM32WB_DMAMUX1_C10CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C10CR_OFFSET)
+#define STM32WB_DMAMUX1_C11CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C11CR_OFFSET)
+#define STM32WB_DMAMUX1_C12CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C12CR_OFFSET)
+#define STM32WB_DMAMUX1_C13CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C13CR_OFFSET)
+
+#define STM32WB_DMAMUX1_CSR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_CSR_OFFSET)
+#define STM32WB_DMAMUX1_CFR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_CFR_OFFSET)
+
+#define STM32WB_DMAMUX1_RGXCR(x) (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RGXCR_OFFSET(x))
+#define STM32WB_DMAMUX1_RG0CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RG0CR_OFFSET)
+#define STM32WB_DMAMUX1_RG1CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RG1CR_OFFSET)
+#define STM32WB_DMAMUX1_RG2CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RG2CR_OFFSET)
+#define STM32WB_DMAMUX1_RG3CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RG3CR_OFFSET)
+
+#define STM32WB_DMAMUX1_RGSR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RGSR_OFFSET)
+#define STM32WB_DMAMUX1_RGCFR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RGCFR_OFFSET)
+
+/* Register Bitfield Definitions ********************************************/
+
+/* DMAMUX1 request line multiplexer channel x configuration register */
+
+#define DMAMUX_CCR_DMAREQID_SHIFT (0) /* Bits 0-5: DMA request identification */
+#define DMAMUX_CCR_DMAREQID_MASK (0x3f << DMAMUX_CCR_DMAREQID_SHIFT)
+#define DMAMUX_CCR_SOIE (8) /* Bit 8: Synchronization overrun interrupt enable */
+#define DMAMUX_CCR_EGE (9) /* Bit 9: Event generation enable */
+#define DMAMUX_CCR_SE (16) /* Bit 16: Synchronization enable */
+#define DMAMUX_CCR_SPOL_SHIFT (17) /* Bits 17-18: Synchronization polarity */
+#define DMAMUX_CCR_SPOL_MASK (0x3 << DMAMUX_CCR_SPOL_SHIFT)
+#define DMAMUX_CCR_NBREQ_SHIFT (19) /* Bits 19-23: Number of DMA request minus 1 to forward */
+#define DMAMUX_CCR_NBREQ_MASK (0x1f << DMAMUX_CCR_NBREQ_SHIFT)
+#define DMAMUX_CCR_SYNCID_SHIFT (24) /* Bits 24-28: Synchronization identification */
+#define DMAMUX_CCR_SYNCID_MASK (0x1f << DMAMUX_CCR_SYNCID_SHIFT)
+
+/* DMAMUX1 request line multiplexer interrupt channel status register */
+
+#define DMAMUX_CSR_SOF(x) (1 << (x)) /* Synchronization overrun event flag */
+
+/* DMAMUX1 request line multiplexer interrupt clear flag register */
+
+#define DMAMUX_CFR_CSOF(x) (1 << (x)) /* Clear synchronization overrun event flag */
+
+/* DMAMUX1 request generator channel x configuration register */
+
+#define DMAMUX_RGCR_SIGID_SHIFT (0) /* Bits 0-4: Signal identifiaction */
+#define DMAMUX_RGCR_SIGID_MASK (0x1f << DMAMUX_RGCR_SIGID_SHIFT)
+#define DMAMUX_RGCR_OIE (8) /* Bit 8: Trigger overrun interrupt enable */
+#define DMAMUX_RGCR_GE (16) /* Bit 16: DMA request generator channel X enable*/
+#define DMAMUX_RGCR_GPOL_SHIFT (17) /* Bits 17-18: DMA request generator trigger polarity */
+#define DMAMUX_RGCR_GPOL_MASK (0x3 << DMAMUX_RGCR_GPOL_SHIFT)
+#define DMAMUX_RGCR_GNBREQ_SHIFT (19) /* Bits 19-23: Number of DMA requests to be generated minus 1 */
+#define DMAMUX_RGCR_GNBREQ_MASK (0x1f << DMAMUX_RGCR_GNBREQ_SHIFT)
+
+/* DMAMUX1 request generator interrupt status register */
+
+#define DMAMUX_RGSR_OF(x) (1 << (x)) /* Trigger overrun event flag */
+
+/* DMAMUX1 request generator interrupt clear flag register */
+
+#define DMAMUX_RGCFR_COF(x) (1 << (x)) /* Clear trigger overrun event flag */
+
+/* DMA channel mapping
+ *
+ * D.CCCCCCC
+ * C - DMAMUX1 request
+ * D - DMA controller (DMA1, DMA2)
+ */
+
+#define DMAMAP_MAP(d,c) ((((d) & 0x01) << 7) | ((c) & 0x7f))
+#define DMAMAP_CONTROLLER(m) (((m) >> 7) & 0x01)
+#define DMAMAP_REQUEST(m) (((m) >> 0) & 0x7f)
+
+/* DMAMUX1 mapping **********************************************************/
+
+/* NOTE: DMAMUX1 channels 0 to 6 are connected to DMA1 channels 1 to 7.
+ * DMAMUX1 channels 7 to 13 are connected to DMA2 channels 1 to 7.
+ */
+
+#define DMAMUX1_REQ_GEN0 (1)
+#define DMAMUX1_REQ_GEN1 (2)
+#define DMAMUX1_REQ_GEN2 (3)
+#define DMAMUX1_REQ_GEN3 (4)
+#define DMAMUX1_ADC1 (5)
+#define DMAMUX1_SPI1_RX (6)
+#define DMAMUX1_SPI1_TX (7)
+#define DMAMUX1_SPI2_RX (8)
+#define DMAMUX1_SPI2_TX (9)
+#define DMAMUX1_I2C1_RX (10)
+#define DMAMUX1_I2C1_TX (11)
+#define DMAMUX1_I2C3_RX (12)
+#define DMAMUX1_I2C3_TX (13)
+#define DMAMUX1_USART1_RX (14)
+#define DMAMUX1_USART1_TX (15)
+#define DMAMUX1_LPUART1_RX (16)
+#define DMAMUX1_LPUART1_TX (17)
+#define DMAMUX1_SAI1_A (18)
+#define DMAMUX1_SAI1_B (19)
+#define DMAMUX1_QSPI (20)
+#define DMAMUX1_TIM1_CH1 (21)
+#define DMAMUX1_TIM1_CH2 (22)
+#define DMAMUX1_TIM1_CH3 (23)
+#define DMAMUX1_TIM1_CH4 (24)
+#define DMAMUX1_TIM1_UP (25)
+#define DMAMUX1_TIM1_TRIG (26)
+#define DMAMUX1_TIM1_COM (27)
+#define DMAMUX1_TIM2_CH1 (28)
+#define DMAMUX1_TIM2_CH2 (29)
+#define DMAMUX1_TIM2_CH3 (30)
+#define DMAMUX1_TIM2_CH4 (31)
+#define DMAMUX1_TIM2_UP (32)
+#define DMAMUX1_TIM16_CH1 (33)
+#define DMAMUX1_TIM16_UP (34)
+#define DMAMUX1_TIM17_CH1 (35)
+#define DMAMUX1_TIM17_UP (36)
+#define DMAMUX1_AES1_IN (37)
+#define DMAMUX1_AES1_OUT (38)
+#define DMAMUX1_AES2_IN (39)
+#define DMAMUX1_AES2_OUT (40)
+/* DMAMUX1 41-63: Reserved */
+
+/* DMAMAP for DMA1 and DMA2 (DMAMUX1) ***************************************/
+
+#define DMAMAP_REQ_GEN0_0 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN0)
+#define DMAMAP_REQ_GEN0_1 DMAMAP_MAP(DMA2, DMAMUX1_REQ_GEN0)
+#define DMAMAP_REQ_GEN1_0 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN1)
+#define DMAMAP_REQ_GEN1_1 DMAMAP_MAP(DMA2, DMAMUX1_REQ_GEN1)
+#define DMAMAP_REQ_GEN2_0 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN2)
+#define DMAMAP_REQ_GEN2_1 DMAMAP_MAP(DMA2, DMAMUX1_REQ_GEN2)
+#define DMAMAP_REQ_GEN3_0 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN3)
+#define DMAMAP_REQ_GEN3_1 DMAMAP_MAP(DMA2, DMAMUX1_REQ_GEN3)
+#define DMAMAP_ADC1_0 DMAMAP_MAP(DMA1, DMAMUX1_ADC1)
+#define DMAMAP_ADC1_1 DMAMAP_MAP(DMA2, DMAMUX1_ADC1)
+#define DMAMAP_SPI1_RX_0 DMAMAP_MAP(DMA1, DMAMUX1_SPI1_RX)
+#define DMAMAP_SPI1_RX_1 DMAMAP_MAP(DMA2, DMAMUX1_SPI1_RX)
+#define DMAMAP_SPI1_TX_0 DMAMAP_MAP(DMA1, DMAMUX1_SPI1_TX)
+#define DMAMAP_SPI1_TX_1 DMAMAP_MAP(DMA2, DMAMUX1_SPI1_TX)
+#define DMAMAP_SPI2_RX_0 DMAMAP_MAP(DMA1, DMAMUX1_SPI2_RX)
+#define DMAMAP_SPI2_RX_1 DMAMAP_MAP(DMA2, DMAMUX1_SPI2_RX)
+#define DMAMAP_SPI2_TX_0 DMAMAP_MAP(DMA1, DMAMUX1_SPI2_TX)
+#define DMAMAP_SPI2_TX_1 DMAMAP_MAP(DMA2, DMAMUX1_SPI2_TX)
+#define DMAMAP_I2C1_RX_0 DMAMAP_MAP(DMA1, DMAMUX1_I2C1_RX)
+#define DMAMAP_I2C1_RX_1 DMAMAP_MAP(DMA2, DMAMUX1_I2C1_RX)
+#define DMAMAP_I2C1_TX_0 DMAMAP_MAP(DMA1, DMAMUX1_I2C1_TX)
+#define DMAMAP_I2C1_TX_1 DMAMAP_MAP(DMA2, DMAMUX1_I2C1_TX)
+#define DMAMAP_I2C3_RX_0 DMAMAP_MAP(DMA1, DMAMUX1_I2C3_RX)
+#define DMAMAP_I2C3_RX_1 DMAMAP_MAP(DMA2, DMAMUX1_I2C3_RX)
+#define DMAMAP_I2C3_TX_0 DMAMAP_MAP(DMA1, DMAMUX1_I2C3_TX)
+#define DMAMAP_I2C3_TX_1 DMAMAP_MAP(DMA2, DMAMUX1_I2C3_TX)
+#define DMAMAP_USART1_RX_0 DMAMAP_MAP(DMA1, DMAMUX1_USART1_RX)
+#define DMAMAP_USART1_RX_1 DMAMAP_MAP(DMA2, DMAMUX1_USART1_RX)
+#define DMAMAP_USART1_TX_0 DMAMAP_MAP(DMA1, DMAMUX1_USART1_TX)
+#define DMAMAP_USART1_TX_1 DMAMAP_MAP(DMA2, DMAMUX1_USART1_TX)
+#define DMAMAP_LPUART1_RX_0 DMAMAP_MAP(DMA1, DMAMUX1_LPUART1_RX)
+#define DMAMAP_LPUART1_RX_1 DMAMAP_MAP(DMA2, DMAMUX1_LPUART1_RX)
+#define DMAMAP_LPUART1_TX_0 DMAMAP_MAP(DMA1, DMAMUX1_LPUART1_TX)
+#define DMAMAP_LPUART1_TX_1 DMAMAP_MAP(DMA2, DMAMUX1_LPUART1_TX)
+#define DMAMAP_SAI1_A_0 DMAMAP_MAP(DMA1, DMAMUX1_SAI1_A)
+#define DMAMAP_SAI1_A_1 DMAMAP_MAP(DMA2, DMAMUX1_SAI1_A)
+#define DMAMAP_SAI1_B_0 DMAMAP_MAP(DMA1, DMAMUX1_SAI1_B)
+#define DMAMAP_SAI1_B_1 DMAMAP_MAP(DMA2, DMAMUX1_SAI1_B)
+#define DMAMAP_QSPI_0 DMAMAP_MAP(DMA1, DMAMUX1_QSPI)
+#define DMAMAP_QSPI_1 DMAMAP_MAP(DMA2, DMAMUX1_QSPI)
+#define DMAMAP_TIM1_CH1_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM1_CH1)
+#define DMAMAP_TIM1_CH1_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM1_CH1)
+#define DMAMAP_TIM1_CH2_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM1_CH2)
+#define DMAMAP_TIM1_CH2_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM1_CH2)
+#define DMAMAP_TIM1_CH3_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM1_CH3)
+#define DMAMAP_TIM1_CH3_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM1_CH3)
+#define DMAMAP_TIM1_CH4_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM1_CH4)
+#define DMAMAP_TIM1_CH4_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM1_CH4)
+#define DMAMAP_TIM1_UP_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM1_UP)
+#define DMAMAP_TIM1_UP_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM1_UP)
+#define DMAMAP_TIM1_TRIG_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM1_TRIG)
+#define DMAMAP_TIM1_TRIG_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM1_TRIG)
+#define DMAMAP_TIM1_COM_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM1_COM)
+#define DMAMAP_TIM1_COM_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM1_COM)
+#define DMAMAP_TIM2_CH1_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM2_CH1)
+#define DMAMAP_TIM2_CH1_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM2_CH1)
+#define DMAMAP_TIM2_CH2_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM2_CH2)
+#define DMAMAP_TIM2_CH2_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM2_CH2)
+#define DMAMAP_TIM2_CH3_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM2_CH3)
+#define DMAMAP_TIM2_CH3_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM2_CH3)
+#define DMAMAP_TIM2_CH4_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM2_CH4)
+#define DMAMAP_TIM2_CH4_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM2_CH4)
+#define DMAMAP_TIM2_UP_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM2_UP)
+#define DMAMAP_TIM2_UP_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM2_UP)
+#define DMAMAP_TIM16_CH1_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM16_CH1)
+#define DMAMAP_TIM16_CH1_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM16_CH1)
+#define DMAMAP_TIM16_UP_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM16_UP)
+#define DMAMAP_TIM16_UP_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM16_UP)
+#define DMAMAP_TIM17_CH1_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM17_CH1)
+#define DMAMAP_TIM17_CH1_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM17_CH1)
+#define DMAMAP_TIM17_UP_0 DMAMAP_MAP(DMA1, DMAMUX1_TIM17_UP)
+#define DMAMAP_TIM17_UP_1 DMAMAP_MAP(DMA2, DMAMUX1_TIM17_UP)
+#define DMAMAP_AES1_IN_0 DMAMAP_MAP(DMA1, DMAMUX1_AES1_IN)
+#define DMAMAP_AES1_IN_1 DMAMAP_MAP(DMA2, DMAMUX1_AES1_IN)
+#define DMAMAP_AES1_OUT_0 DMAMAP_MAP(DMA1, DMAMUX1_AES1_OUT)
+#define DMAMAP_AES1_OUT_1 DMAMAP_MAP(DMA2, DMAMUX1_AES1_OUT)
+#define DMAMAP_AES2_IN_0 DMAMAP_MAP(DMA1, DMAMUX1_AES2_IN)
+#define DMAMAP_AES2_IN_1 DMAMAP_MAP(DMA2, DMAMUX1_AES2_IN)
+#define DMAMAP_AES2_OUT_0 DMAMAP_MAP(DMA1, DMAMUX1_AES2_OUT)
+#define DMAMAP_AES2_OUT_1 DMAMAP_MAP(DMA2, DMAMUX1_AES2_OUT)
+
+#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_DMAMUX_H */
diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_exti.h b/arch/arm/src/stm32wb/hardware/stm32wb_exti.h
new file mode 100644
index 0000000000..c4053c0736
--- /dev/null
+++ b/arch/arm/src/stm32wb/hardware/stm32wb_exti.h
@@ -0,0 +1,168 @@
+/****************************************************************************
+ * arch/arm/src/stm32wb/hardware/stm32wb_exti.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_EXTI_H
+#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_EXTI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define STM32WB_EXTI_RTSR1_OFFSET 0x0000 /* Rising trigger selection register 1 */
+#define STM32WB_EXTI_FTSR1_OFFSET 0x0004 /* Falling trigger selection register 1 */
+#define STM32WB_EXTI_SWIER1_OFFSET 0x0008 /* Software interrupt event register 1 */
+#define STM32WB_EXTI_PR1_OFFSET 0x000c /* Pending register 1 */
+#define STM32WB_EXTI_RTSR2_OFFSET 0x0020 /* Rising trigger selection register 2 */
+#define STM32WB_EXTI_FTSR2_OFFSET 0x0024 /* Falling trigger selection register 2 */
+#define STM32WB_EXTI_SWIER2_OFFSET 0x0028 /* Software interrupt event register 2 */
+#define STM32WB_EXTI_PR2_OFFSET 0x002c /* Pending register 2 */
+#define STM32WB_EXTI_C1IMR1_OFFSET 0x0080 /* CPU1 wakeup with interrupt mask register 1 */
+#define STM32WB_EXTI_C1EMR1_OFFSET 0x0084 /* CPU1 wakeup with event mask register 1 */
+#define STM32WB_EXTI_C1IMR2_OFFSET 0x0090 /* CPU1 wakeup with interrupt mask register 2 */
+#define STM32WB_EXTI_C1EMR2_OFFSET 0x0094 /* CPU1 wakeup with event mask register 2 */
+#define STM32WB_EXTI_C2IMR1_OFFSET 0x00c0 /* CPU2 wakeup with interrupt mask register 1 */
+#define STM32WB_EXTI_C2EMR1_OFFSET 0x00c4 /* CPU2 wakeup with event mask register 1 */
+#define STM32WB_EXTI_C2IMR2_OFFSET 0x00d0 /* CPU2 wakeup with interrupt mask register 2 */
+#define STM32WB_EXTI_C2EMR2_OFFSET 0x00d4 /* CPU2 wakeup with event mask register 2 */
+
+/* Register Addresses *******************************************************/
+
+#define STM32WB_EXTI_RTSR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_RTSR1_OFFSET)
+#define STM32WB_EXTI_FTSR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_FTSR1_OFFSET)
+#define STM32WB_EXTI_SWIER1 (STM32WB_EXTI_BASE + STM32WB_EXTI_SWIER1_OFFSET)
+#define STM32WB_EXTI_PR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_PR1_OFFSET)
+#define STM32WB_EXTI_RTSR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_RTSR2_OFFSET)
+#define STM32WB_EXTI_FTSR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_FTSR2_OFFSET)
+#define STM32WB_EXTI_SWIER2 (STM32WB_EXTI_BASE + STM32WB_EXTI_SWIER2_OFFSET)
+#define STM32WB_EXTI_PR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_PR2_OFFSET)
+#define STM32WB_EXTI_C1IMR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_C1IMR1_OFFSET)
+#define STM32WB_EXTI_C1EMR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_C1EMR1_OFFSET)
+#define STM32WB_EXTI_C1IMR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_C1IMR2_OFFSET)
+#define STM32WB_EXTI_C1EMR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_C1EMR2_OFFSET)
+#define STM32WB_EXTI_C2IMR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_C2IMR1_OFFSET)
+#define STM32WB_EXTI_C2EMR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_C2EMR1_OFFSET)
+#define STM32WB_EXTI_C2IMR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_C2IMR2_OFFSET)
+#define STM32WB_EXTI_C2EMR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_C2EMR2_OFFSET)
+
+/* Register Bitfield Definitions ********************************************/
+
+/* EXTI lines > 15 peripheral event sources */
+
+#define EXTI_EVT_PVD (16) /* EXTI line 16: PVD output */
+#define EXTI_EVT_RTCALARM (17) /* EXTI line 17: RTC Alarm event */
+#define EXTI_EVT_RTCTAMPER (18) /* EXTI line 18: RTC Tamper, TimeStamp, LSE CSS interrupt */
+#define EXTI_EVT_RTCWAKEUP (19) /* EXTI line 19: RTC Wakeup event */
+#define EXTI_EVT_COMP1 (20) /* EXTI line 20: COMP1 (comparator) output */
+#define EXTI_EVT_COMP2 (21) /* EXTI line 21: COMP2 (comparator) output */
+#define EXTI_EVT_I2C1 (22) /* EXTI line 22: I2C1 wakeup */
+#define EXTI_EVT_I2C3 (23) /* EXTI line 23: I2C3 wakeup */
+#define EXTI_EVT_USART1 (24) /* EXTI line 24: USART1 wakeup */
+#define EXTI_EVT_LPUART1 (25) /* EXTI line 25: LPUART1 wakeup */
+#define EXTI_EVT_LPTIM1 (29) /* EXTI line 29: LPTIM1 */
+#define EXTI_EVT_LPTIM2 (30) /* EXTI line 30: LPTIM2 */
+#define EXTI_EVT_PVM1 (31) /* EXTI line 31: PVM1 wakeup */
+#define EXTI_EVT_PVM3 (33) /* EXTI line 33: PVM2 wakeup */
+#define EXTI_EVT_C1IPCC (36) /* EXTI line 36: CPU1 IPCC wakeup */
+#define EXTI_EVT_C2IPCC (37) /* EXTI line 37: CPU2 IPCC wakeup */
+#define EXTI_EVT_C1HSEM (38) /* EXTI line 38: CPU1 HSEM interrupt 0 */
+#define EXTI_EVT_C2HSEM (39) /* EXTI line 39: CPU2 HSEM interrupt 1 */
+#define EXTI_EVT_C2SEV (40) /* EXTI line 40: CPU2 SEV line */
+#define EXTI_EVT_C1SEV (41) /* EXTI line 41: CPU1 SEV line */
+#define EXTI_EVT_FLASH (42) /* EXTI line 42: Flash ECC and global interrupts */
+#define EXTI_EVT_LCD (43) /* EXTI line 43: LCD wakeup */
+#define EXTI_EVT_HSECSS (44) /* EXTI line 44: RCC HSE CSS interrupts */
+#define EXTI_EVT_BLE (45) /* EXTI line 45: BLE and RADIO interrupts */
+#define EXTI_EVT_802 (46) /* EXTI line 46: 802.15.14 Int0 and Int1 interrupts */
+#define EXTI_EVT_DBG (48) /* EXTI line 48: Debug power up request wakeup */
+
+/* Rising trigger selection registers */
+
+#define EXTI_RTSR1_RT(n) (1 << (n)) /* Rising trigger event enable for line n = 0..21, 31 */
+#define EXTI_RTSR1_MASK 0x803fffff
+
+#define EXTI_RTSR2_RT(n) (1 << ((n) & 31)) /* Rising trigger event enable for line n = 33, 40, 41 */
+#define EXTI_RTSR2_MASK 0x00000302
+
+/* Falling trigger selection registers */
+
+#define EXTI_FTSR1_FT(n) (1 << (n)) /* Falling trigger event enable for line n = 0..21, 31 */
+#define EXTI_FTSR1_MASK 0x803fffff
+
+#define EXTI_FTSR2_FT(n) (1 << ((n) & 31)) /* Falling trigger event enable for line n = 33, 40, 41 */
+#define EXTI_FTSR2_MASK 0x00000302
+
+/* Software interrupt event registers */
+
+#define EXTI_SWIER1_SWI(n) (1 << (n)) /* Software interrupt on line n = 0..21, 31 */
+#define EXTI_SWIER1_MASK 0x803fffff
+
+#define EXTI_SWIER2_SWI(n) (1 << ((n) & 31)) /* Software interrupt on line n = 33, 40, 41 */
+#define EXTI_SWIER2_MASK 0x00000302
+
+/* Pending registers */
+
+#define EXTI_PR1_PIF(n) (1 << (n)) /* Pending interrupt flag on line n = 0..21, 31 */
+#define EXTI_PR1_MASK 0x803fffff
+
+#define EXTI_PR2_PIF(n) (1 << ((n) & 31)) /* Pending interrupt flag on line n = 33, 40, 41 */
+#define EXTI_PR2_MASK 0x00000302
+
+/* Interrupt mask registers */
+
+#define EXTI_C1IMR1_IM(n) (1 << (n)) /* Interrupt mask on line n = 0..31 */
+#define EXTI_C1IMR1_MASK 0xffffffff
+
+#define EXTI_C1IMR2_IM(n) (1 << ((n) & 31)) /* Interrupt mask on line n = 32..48 */
+#define EXTI_C1IMR2_MASK 0x0001ffff
+
+/* Event mask registers */
+
+#define EXTI_C1EMR1_EM(n) (1 << (n)) /* Event mask on line n = 0..15, 17..21 */
+#define EXTI_C1EMR1_MASK 0x003effff
+
+#define EXTI_C1EMR2_EM(n) (1 << ((n) & 31)) /* Event mask on line n = 40, 41 */
+#define EXTI_C1EMR2_MASK 0x00000300
+
+/* CPU2 Interrupt mask registers */
+
+#define EXTI_C2IMR1_IM(n) (1 << (n)) /* CPU2 Interrupt mask on line n = 0..31 */
+#define EXTI_C2IMR1_MASK 0xffffffff
+
+#define EXTI_C2IMR2_IM(n) (1 << ((n) & 31)) /* CPU2 Interrupt mask on line n = 32..48 */
+#define EXTI_C2IMR2_MASK 0x0001ffff
+
+/* CPU2 Event mask registers */
+
+#define EXTI_C2EMR1_EM(n) (1 << (n)) /* CPU2 Event mask on line n = 0..15, 17..21 */
+#define EXTI_C2EMR1_MASK 0x003effff
+
+#define EXTI_C2EMR2_EM(n) (1 << ((n) & 31)) /* CPU2 Event mask on line n = 40, 41 */
+#define EXTI_C2EMR2_MASK 0x00000300
+
+#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_EXTI_H */
diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_flash.h b/arch/arm/src/stm32wb/hardware/stm32wb_flash.h
new file mode 100644
index 0000000000..8f794207d5
--- /dev/null
+++ b/arch/arm/src/stm32wb/hardware/stm32wb_flash.h
@@ -0,0 +1,359 @@
+/****************************************************************************
+ * arch/arm/src/stm32wb/hardware/stm32wb_flash.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_FLASH_H
+#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_FLASH_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Flash size is known from the chip selection:
+ *
+ * When CONFIG_STM32WB_FLASH_OVERRIDE_DEFAULT is set the
+ * CONFIG_STM32WB_FLASH_CONFIG_x selects the default FLASH size based on
+ * the chip part number. This value can be overridden with
+ * CONFIG_STM32WB_FLASH_OVERRIDE_x
+ *
+ * Parts STM32WB3xxC have 256Kb of FLASH
+ * Parts STM32WB5xxC have 256Kb of FLASH
+ * Parts STM32WB1xxC have 320Kb of FLASH
+ * Parts STM32WBxxxE have 512Kb of FLASH
+ * Parts STM32WBxxxY have 640Kb of FLASH
+ * Parts STM32WBxxxG have 1024Kb of FLASH
+ *
+ * N.B. Only Single bank mode is supported
+ */
+
+#if !defined(CONFIG_STM32WB_FLASH_OVERRIDE_DEFAULT) && \
+ !defined(CONFIG_STM32WB_FLASH_OVERRIDE_C_256) && \
+ !defined(CONFIG_STM32WB_FLASH_OVERRIDE_C_320) && \
+ !defined(CONFIG_STM32WB_FLASH_OVERRIDE_E_512) && \
+ !defined(CONFIG_STM32WB_FLASH_OVERRIDE_Y_640) && \
+ !defined(CONFIG_STM32WB_FLASH_OVERRIDE_G_1024) && \
+ !defined(CONFIG_STM32WB_FLASH_CONFIG_C_256) && \
+ !defined(CONFIG_STM32WB_FLASH_CONFIG_C_320) && \
+ !defined(CONFIG_STM32WB_FLASH_CONFIG_E_512) && \
+ !defined(CONFIG_STM32WB_FLASH_CONFIG_Y_640) && \
+ !defined(CONFIG_STM32WB_FLASH_CONFIG_G_1024)
+# error "Flash size not defined"
+#endif
+
+/* Override of the Flash has been chosen */
+
+#if !defined(CONFIG_STM32WB_FLASH_OVERRIDE_DEFAULT)
+# undef CONFIG_STM32WB_FLASH_CONFIG_C_256
+# undef CONFIG_STM32WB_FLASH_CONFIG_C_320
+# undef CONFIG_STM32WB_FLASH_CONFIG_E_512
+# undef CONFIG_STM32WB_FLASH_CONFIG_Y_640
+# undef CONFIG_STM32WB_FLASH_CONFIG_G_1024
+# if defined(CONFIG_STM32WB_FLASH_OVERRIDE_C_256)
+# define CONFIG_STM32WB_FLASH_CONFIG_C_256
+# elif defined(CONFIG_STM32WB_FLASH_OVERRIDE_C_320)
+# define CONFIG_STM32WB_FLASH_CONFIG_C_320
+# elif defined(CONFIG_STM32WB_FLASH_OVERRIDE_E_512)
+# define CONFIG_STM32WB_FLASH_CONFIG_E_512
+# elif defined(CONFIG_STM32WB_FLASH_OVERRIDE_Y_640)
+# define CONFIG_STM32WB_FLASH_CONFIG_Y_640
+# elif defined(CONFIG_STM32WB_FLASH_OVERRIDE_G_1024)
+# define CONFIG_STM32WB_FLASH_CONFIG_G_1024
+# endif
+#endif
+
+/* Define the valid configuration */
+
+#define STM32WB_FLASH_PAGESIZE 4096
+
+#if defined(CONFIG_STM32WB_FLASH_CONFIG_C_256) /* 256 kB */
+# define STM32WB_FLASH_NPAGES 64
+#elif defined(CONFIG_STM32WB_FLASH_CONFIG_C_320) /* 320 kB */
+# define STM32WB_FLASH_NPAGES 80
+#elif defined(CONFIG_STM32WB_FLASH_CONFIG_E_512) /* 512 kB */
+# define STM32WB_FLASH_NPAGES 128
+#elif defined(CONFIG_STM32WB_FLASH_CONFIG_Y_640) /* 640 kB */
+# define STM32WB_FLASH_NPAGES 160
+#elif defined(CONFIG_STM32WB_FLASH_CONFIG_G_1024) /* 1 MB */
+# define STM32WB_FLASH_NPAGES 256
+#else
+# error "Unknown flash configuration!"
+#endif
+
+#define STM32WB_FLASH_SIZE (STM32WB_FLASH_NPAGES * STM32WB_FLASH_PAGESIZE)
+
+/* Register Offsets *********************************************************/
+
+#define STM32WB_FLASH_ACR_OFFSET 0x0000 /* Flash Access Control Register */
+#define STM32WB_FLASH_KEYR_OFFSET 0x0008 /* Flash Key Register */
+#define STM32WB_FLASH_OPTKEYR_OFFSET 0x000c /* Flash Option Key Register */
+#define STM32WB_FLASH_SR_OFFSET 0x0010 /* Flash Status Register */
+#define STM32WB_FLASH_CR_OFFSET 0x0014 /* Flash Control Register */
+#define STM32WB_FLASH_ECCR_OFFSET 0x0018 /* Flash ECC Register */
+#define STM32WB_FLASH_OPTR_OFFSET 0x0020 /* Flash Option Register */
+#define STM32WB_FLASH_PCROP1ASR_OFFSET 0x0024 /* Flash PCROP zone A Start address Register */
+#define STM32WB_FLASH_PCROP1AER_OFFSET 0x0028 /* Flash PCROP zone A End address Register */
+#define STM32WB_FLASH_WRP1AR_OFFSET 0x002c /* Flash WRP area A Address Register */
+#define STM32WB_FLASH_WRP1BR_OFFSET 0x0030 /* Flash WRP area B Address Register */
+#define STM32WB_FLASH_PCROP1BSR_OFFSET 0x0034 /* Flash PCROP zone B Start address Register */
+#define STM32WB_FLASH_PCROP1BER_OFFSET 0x0038 /* Flash PCROP zone B End address Register */
+#define STM32WB_FLASH_IPCCBR_OFFSET 0x003C /* Flash IPCC mailbox data buffer address Register */
+#define STM32WB_FLASH_C2ACR_OFFSET 0x005C /* CPU2 flash Access Control Register */
+#define STM32WB_FLASH_C2SR_OFFSET 0x0060 /* CPU2 flash Status Register */
+#define STM32WB_FLASH_C2CR_OFFSET 0x0064 /* CPU2 flash Control Register */
+#define STM32WB_FLASH_SFR_OFFSET 0x0080 /* Secure Flash start address Register */
+#define STM32WB_FLASH_SRRVR_OFFSET 0x0084 /* SRAM2 start address and CPU2 Reset Vector Register */
+
+/* Register Addresses *******************************************************/
+
+#define STM32WB_FLASH_ACR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_ACR_OFFSET)
+#define STM32WB_FLASH_KEYR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_KEYR_OFFSET)
+#define STM32WB_FLASH_OPTKEYR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_OPTKEYR_OFFSET)
+#define STM32WB_FLASH_SR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_SR_OFFSET)
+#define STM32WB_FLASH_CR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_CR_OFFSET)
+#define STM32WB_FLASH_ECCR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_ECCR_OFFSET)
+#define STM32WB_FLASH_OPTR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_OPTR_OFFSET)
+#define STM32WB_FLASH_PCROP1ASR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_PCROP1ASR_OFFSET)
+#define STM32WB_FLASH_PCROP1AER (STM32WB_FLASHREG_BASE + STM32WB_FLASH_PCROP1AER_OFFSET)
+#define STM32WB_FLASH_WRP1AR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_WRP1AR_OFFSET)
+#define STM32WB_FLASH_WRP1BR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_WRP1BR_OFFSET)
+#define STM32WB_FLASH_PCROP1BSR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_PCROP1BSR_OFFSET)
+#define STM32WB_FLASH_PCROP1BER (STM32WB_FLASHREG_BASE + STM32WB_FLASH_PCROP1BER_OFFSET)
+#define STM32WB_FLASH_IPCCBR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_IPCCBR_OFFSET)
+#define STM32WB_FLASH_C2ACR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_C2ACR_OFFSET)
+#define STM32WB_FLASH_C2SR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_C2SR_OFFSET)
+#define STM32WB_FLASH_C2CR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_C2CR_OFFSET)
+#define STM32WB_FLASH_SFR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_SFR_OFFSET)
+#define STM32WB_FLASH_SRRVR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_SRRVR_OFFSET)
+
+/* Register Bitfield Definitions ********************************************/
+
+/* Flash Access Control Register (ACR) */
+
+#define FLASH_ACR_LATENCY_SHIFT (0) /* Bits 0-2: Flash memory access latency */
+#define FLASH_ACR_LATENCY_MASK (0x7 << FLASH_ACR_LATENCY_SHIFT)
+# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states, n = 0..3 */
+# define FLASH_ACR_LATENCY_0 (0x0 << FLASH_ACR_LATENCY_SHIFT) /* 000: Zero wait states */
+# define FLASH_ACR_LATENCY_1 (0x1 << FLASH_ACR_LATENCY_SHIFT) /* 001: One wait state */
+# define FLASH_ACR_LATENCY_2 (0x2 << FLASH_ACR_LATENCY_SHIFT) /* 010: Two wait states */
+# define FLASH_ACR_LATENCY_3 (0x3 << FLASH_ACR_LATENCY_SHIFT) /* 011: Three wait states */
+
+#define FLASH_ACR_PRFTEN (1 << 8) /* Bit 8: Prefetch enable */
+#define FLASH_ACR_ICEN (1 << 9) /* Bit 9: Instruction cache enable */
+#define FLASH_ACR_DCEN (1 << 10) /* Bit 10: Data cache enable */
+#define FLASH_ACR_ICRST (1 << 11) /* Bit 11: Instruction cache reset */
+#define FLASH_ACR_DCRST (1 << 12) /* Bit 12: Data cache reset */
+#define FLASH_ACR_PES (1 << 15) /* Bit 15: Program/Erase suspend request */
+#define FLASH_ACR_EMPTY (1 << 16) /* Bit 16: Flash memory user area empty */
+
+/* Flash Key Register (KEYR) */
+
+#define FLASH_KEYR_KEY1 (0x45670123)
+#define FLASH_KEYR_KEY2 (0xcdef89ab)
+
+/* Flash Option Key Register (OPTKEYR) */
+
+#define FLASH_OPTKEYR_KEY1 (0x08192a3b)
+#define FLASH_OPTKEYR_KEY2 (0x4c5d6e7f)
+
+/* Flash Status Register (SR) */
+
+#define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */
+#define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */
+#define FLASH_SR_PROGERR (1 << 3) /* Bit 3: Programming error */
+#define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */
+#define FLASH_SR_PGAERR (1 << 5) /* Bit 5: Programming alignment error */
+#define FLASH_SR_SIZERR (1 << 6) /* Bit 6: Size error */
+#define FLASH_SR_PGSERR (1 << 7) /* Bit 7: Programming sequence error */
+#define FLASH_SR_MISERR (1 << 8) /* Bit 8: Fast programming data miss error */
+#define FLASH_SR_FASTERR (1 << 9) /* Bit 9: Fast programming error */
+#define FLASH_SR_OPTNV (1 << 13) /* Bit 13: User option OPTVAL indication */
+#define FLASH_SR_RDERR (1 << 14) /* Bit 14: PCROP read error */
+#define FLASH_SR_OPTVERR (1 << 15) /* Bit 15: Option and Engineering bit validity error */
+#define FLASH_SR_BSY (1 << 16) /* Bit 16: Busy */
+#define FLASH_SR_CFGBSY (1 << 18) /* Bit 18: Programming or erase configuration busy */
+#define FLASH_SR_PESD (1 << 19) /* Bit 19: Programming / erase configuration suspended */
+
+/* Flash Control Register (CR) */
+
+#define FLASH_CR_PG (1 << 0) /* Bit 0: Programming */
+#define FLASH_CR_PER (1 << 1) /* Bit 1: Page Erase */
+#define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase */
+#define FLASH_CR_PNB_SHIFT (3) /* Bits 3-10: Page number selection */
+#define FLASH_CR_PNB_MASK (0xff << FLASH_CR_PNB_SHIFT)
+# define FLASH_CR_PNB(n) ((n) << FLASH_CR_PNB_SHIFT) /* Page n, n = 0..255 */
+
+#define FLASH_CR_STRT (1 << 16) /* Bit 16: Start Erase */
+#define FLASH_CR_OPTSTRT (1 << 17) /* Bit 17: Options modification Start */
+#define FLASH_CR_FSTPG (1 << 18) /* Bit 18: Fast programming */
+#define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */
+#define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */
+#define FLASH_CR_RDERRIE (1 << 26) /* Bit 26: PCROP read error interrupt enable */
+#define FLASH_CR_OBL_LAUNCH (1 << 27) /* Bit 27: Force option byte loading */
+#define FLASH_CR_OPTLOCK (1 << 30) /* Bit 30: Options Lock */
+#define FLASH_CR_LOCK (1 << 31) /* Bit 31: FLASH_CR register Lock */
+
+/* Flash ECC Register (ECCR) */
+
+#define FLASH_ECCR_ADDR_ECC_SHIFT (0) /* Bits 0-16: ECC fail address */
+#define FLASH_ECCR_ADDR_ECC_MASK (0x1ffff << FLASH_ECCR_ADDR_ECC_SHIFT)
+#define FLASH_ECCR_SYSF_ECC (1 << 20) /* Bit 20: System Flash ECC fail */
+#define FLASH_ECCR_ECCCIE (1 << 24) /* Bit 24: ECC correction interrupt enable */
+#define FLASH_ECCR_CPUID_SHIFT (26) /* Bits 26-28: CPU identification */
+#define FLASH_ECCR_CPUID_MASK (0x7 << FLASH_ECCR_CPUID_SHIFT)
+#define FLASH_ECCR_ECCC (1 << 30) /* Bit 30: ECC correction */
+#define FLASH_ECCR_ECCD (1 << 31) /* Bit 31: ECC detection */
+
+/* Flash Option Register (OPTR) */
+
+#define FLASH_OPTR_RDP_SHIFT (0) /* Bits 0-7: Read protection level */
+#define FLASH_OPTR_RDP_MASK (0xff << FLASH_OPTR_RDP_SHIFT)
+# define FLASH_OPTR_RDPLEV0 (0xaa << FLASH_OPTR_RDP_SHIFT) /* 0xAA: Level 0, read protection not active */
+# define FLASH_OPTR_RDPLEV2 (0xcc << FLASH_OPTR_RDP_SHIFT) /* 0xCC: Level 2, chip read protection active */
+# define FLASH_OPTR_RDPLEV1 (0x01 << FLASH_OPTR_RDP_SHIFT) /* Others: Level 1, memories read protection active */
+
+#define FLASH_OPTR_ESE (1 << 8) /* Bit 8: System security enabled flag */
+#define FLASH_OPTR_BORLEV_SHIFT (9) /* Bits 9-11: BOR level reset */
+#define FLASH_OPTR_BORLEV_MASK (0x7 << FLASH_OPTR_BORLEV_SHIFT)
+# define FLASH_OPTR_BORLEV0 (0x0 << FLASH_OPTR_BORLEV_SHIFT) /* 000: BOR Level 0 (1.7 V) */
+# define FLASH_OPTR_BORLEV1 (0x1 << FLASH_OPTR_BORLEV_SHIFT) /* 001: BOR Level 1 (2.0 V) */
+# define FLASH_OPTR_BORLEV2 (0x2 << FLASH_OPTR_BORLEV_SHIFT) /* 010: BOR Level 2 (2.2 V) */
+# define FLASH_OPTR_BORLEV3 (0x3 << FLASH_OPTR_BORLEV_SHIFT) /* 011: BOR Level 3 (2.5 V) */
+# define FLASH_OPTR_BORLEV4 (0x4 << FLASH_OPTR_BORLEV_SHIFT) /* 100: BOR Level 4 (2.8 V) */
+
+#define FLASH_OPTR_NRST_STOP (1 << 12) /* Bit 12: Not generate reset when entering the Stop mode */
+#define FLASH_OPTR_NRST_STDBY (1 << 13) /* Bit 13: Not generate reset when entering the Standby mode */
+#define FLASH_OPTR_NRST_SHDW (1 << 14) /* Bit 14: Not generate reset when entering the Shutdown mode */
+#define FLASH_OPTR_IWDG_SW (1 << 16) /* Bit 16: Independent watchdog selection */
+#define FLASH_OPTR_IWDG_STOP (1 << 17) /* Bit 17: Independent watchdog counter freeze in Stop mode */
+#define FLASH_OPTR_IWDG_STDBY (1 << 18) /* Bit 18: Independent watchdog counter freeze in Standby mode*/
+#define FLASH_OPTR_WWDG_SW (1 << 19) /* Bit 19: Window watchdog selection */
+#define FLASH_OPTR_NBOOT1 (1 << 23) /* Bit 23: Boot configuration */
+#define FLASH_OPTR_SRAM2_PE (1 << 24) /* Bit 24: SRAM2 parity check enable */
+#define FLASH_OPTR_SRAM2_RST (1 << 25) /* Bit 25: SRAM2 Erase when system reset */
+#define FLASH_OPTR_NSWBOOT0 (1 << 26) /* Bit 26: Software BOOT0 selection */
+#define FLASH_OPTR_NBOOT0 (1 << 27) /* Bit 27: nBOOT0 option bit */
+#define FLASH_OPTR_AGC_TRIM_SHIFT (29) /* Bits 29-31: Radio automatic gain control trimming */
+#define FLASH_OPTR_AGC_TRIM_MASK (0x7 << FLASH_OPTR_AGC_TRIM_SHIFT)
+
+/* Flash memory PCROP zone A start address register (PCROP1ASR) */
+
+#define FLASH_PCROP1ASR_STRT_SHIFT (0) /* Bits 0-8: PCROP1A area start offset */
+#define FLASH_PCROP1ASR_STRT_MASK (0x1ff << FLASH_PCROP1ASR_STRT_SHIFT)
+
+/* Flash memory PCROP zone A end address register (PCROP1AER) */
+
+#define FLASH_PCROP1AER_END_SHIFT (0) /* Bits 0-8: PCROP1A area end offset */
+#define FLASH_PCROP1AER_END_MASK (0x1ff << FLASH_PCROP1AER_END_SHIFT)
+#define FLASH_PCROP1AER_PCROP_RDP (1 << 31) /* Bit 31: PCROP area not preserved on RDP erase */
+
+/* Flash memory WRP area A address register (WRP1AR) */
+
+#define FLASH_WRP1AR_STRT_SHIFT (0) /* Bits 0-7: WRP first area A start offset */
+#define FLASH_WRP1AR_STRT_MASK (0xff << FLASH_WRP1AR_STRT_SHIFT)
+#define FLASH_WRP1AR_END_SHIFT (16) /* Bits 16-23: WRP first area A end offset */
+#define FLASH_WRP1AR_END_MASK (0xff << FLASH_WRP1AR_END_SHIFT)
+
+/* Flash memory WRP area B address register (WRP1BR) */
+
+#define FLASH_WRP1BR_STRT_SHIFT (0) /* Bits 0-7: WRP second area B start offset */
+#define FLASH_WRP1BR_STRT_MASK (0xff << FLASH_WRP1BR_STRT_SHIFT)
+#define FLASH_WRP1BR_END_SHIFT (16) /* Bits 16-23: WRP second area B end offset */
+#define FLASH_WRP1BR_END_MASK (0xff << FLASH_WRP1BR_END_SHIFT)
+
+/* Flash memory PCROP zone B start address register (PCROP1BSR) */
+
+#define FLASH_PCROP1BSR_STRT_SHIFT (0) /* Bits 0-8: PCROP1B area start offset */
+#define FLASH_PCROP1BSR_STRT_MASK (0x1ff << FLASH_PCROP1BSR_STRT_SHIFT)
+
+/* Flash PCROP zone B End Register (PCROP1BER) */
+
+#define FLASH_PCROP1BER_END_SHIFT (0) /* Bits 0-8: PCROP1B area end offset */
+#define FLASH_PCROP1BER_END_MASK (0x1ff << FLASH_PCROP1BER_END_SHIFT)
+
+/* Flash IPCC mailbox data Buffer Register (IPCCBR) */
+
+#define FLASH_IPCCBR_IPCCBDA_SHIFT (0) /* Bits 0-13: IPCC mailbox data buffer base address offset */
+#define FLASH_IPCCBR_IPCCBDA_MASK (0x3fff << FLASH_IPCCBR_IPCCBDA_SHIFT)
+
+/* CPU2 Flash Access Control Register (C2ACR) */
+
+#define FLASH_C2ACR_PRFTEN (1 << 8) /* Bit 8: CPU2 Prefetch enable */
+#define FLASH_C2ACR_ICEN (1 << 9) /* Bit 9: CPU2 Instruction cache enable */
+#define FLASH_C2ACR_ICRST (1 << 11) /* Bit 11: CPU2 Instruction cache reset */
+#define FLASH_C2ACR_PES (1 << 15) /* Bit 15: CPU2 Program/Erase suspend request */
+
+/* CPU2 Flash Status Register (C2SR) */
+
+#define FLASH_C2SR_EOP (1 << 0) /* Bit 0: CPU2 End of operation */
+#define FLASH_C2SR_OPERR (1 << 1) /* Bit 1: CPU2 Operation error */
+#define FLASH_C2SR_PROGERR (1 << 3) /* Bit 3: CPU2 Programming error */
+#define FLASH_C2SR_WRPERR (1 << 4) /* Bit 4: CPU2 Write protection error */
+#define FLASH_C2SR_PGAERR (1 << 5) /* Bit 5: CPU2 Programming alignment error */
+#define FLASH_C2SR_SIZERR (1 << 6) /* Bit 6: CPU2 Size error */
+#define FLASH_C2SR_PGSERR (1 << 7) /* Bit 7: CPU2 Programming sequence error */
+#define FLASH_C2SR_MISERR (1 << 8) /* Bit 8: CPU2 Fast programming data miss error */
+#define FLASH_C2SR_FASTERR (1 << 9) /* Bit 9: CPU2 Fast programming error */
+#define FLASH_C2SR_RDERR (1 << 14) /* Bit 14: CPU2 PCROP read error */
+#define FLASH_C2SR_BSY (1 << 16) /* Bit 16: CPU2 Busy */
+#define FLASH_C2SR_CFGBSY (1 << 18) /* Bit 18: CPU2 Programming or erase configuration busy */
+#define FLASH_C2SR_PESD (1 << 19) /* Bit 19: CPU2 Programming / erase configuration suspended */
+
+/* CPU2 Flash Control Register (C2CR) */
+
+#define FLASH_C2CR_PG (1 << 0) /* Bit 0: CPU2 Programming */
+#define FLASH_C2CR_PER (1 << 1) /* Bit 1: CPU2 Page Erase */
+#define FLASH_C2CR_MER (1 << 2) /* Bit 2: CPU2 Mass Erase */
+#define FLASH_C2CR_PNB_SHIFT (3) /* Bits 3-10: Page number selection */
+#define FLASH_C2CR_PNB_MASK (0xff << FLASH_C2CR_PNB_SHIFT)
+# define FLASH_C2CR_PNB(n) ((n) << FLASH_C2CR_PNB_SHIFT) /* Page n, n = 0..255 */
+
+#define FLASH_C2CR_STRT (1 << 16) /* Bit 16: CPU2 Start Erase */
+#define FLASH_C2CR_FSTPG (1 << 18) /* Bit 18: CPU2 Fast programming */
+#define FLASH_C2CR_EOPIE (1 << 24) /* Bit 24: CPU2 End of operation interrupt enable */
+#define FLASH_C2CR_ERRIE (1 << 25) /* Bit 25: CPU2 Error interrupt enable */
+#define FLASH_C2CR_RDERRIE (1 << 26) /* Bit 26: CPU2 PCROP read error interrupt enable */
+
+/* Secure Flash start address Register (SFR) */
+
+#define FLASH_SFR_SFSA_SHIFT (0) /* Bits 0-7: Secure flash start address */
+#define FLASH_SFR_SFSA_MASK (0xff << FLASH_SFR_SFSA_SHIFT)
+#define FLASH_SFR_FSD (1 << 8) /* Bit 8: Flash security disabled */
+#define FLASH_SFR_DDS (1 << 12) /* Bit 12: Disable CPU2 debug access */
+
+/* SRAM2 start address and CPU2 Reset Vector Register (SRRVR) */
+
+#define FLASH_SRRVR_SBRV_SHIFT (0) /* Bits 0-17: CPU2 boot reset vector */
+#define FLASH_SRRVR_SBRV_MASK (0x3ffff << FLASH_SRRVR_SBRV_SHIFT)
+#define FLASH_SRRVR_SBRSA_SHIFT (18) /* Bits 18-22: Secure backup SRAM2a start address */
+#define FLASH_SRRVR_SBRSA_MASK (0x1f << FLASH_SRRVR_SBRSA_SHIFT)
+#define FLASH_SRRVR_BRSD (1 << 23) /* Bit 23: Backup SRAM2a security disable */
+#define FLASH_SRRVR_SNBRSA_SHIFT (25) /* Bits 25-29: Secure non-backup SRAM2b start address */
+#define FLASH_SRRVR_SNBRSA_MASK (0x1f << FLASH_SRRVR_SNBRSA_SHIFT)
+#define FLASH_SRRVR_NBRSD (1 << 30) /* Bit 30: Non-backup SRAM2a security disable */
+#define FLASH_SRRVR_C2OPT (1 << 31) /* Bit 31: CPU2 boot reset vector memory selection */
+# define FLASH_SRRVR_C2OPT_SRAM (0 << 31) /* 0: SBRV offset addresses SRAM1/2, starting from 0x20000000 */
+# define FLASH_SRRVR_C2OPT_FLASH (1 << 31) /* 1: SBRV offset addresses Flash, starting from 0x08000000 */
+
+#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_FLASH_H */
diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h b/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h
new file mode 100644
index 0000000000..dc6ff3cad5
--- /dev/null
+++ b/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h
@@ -0,0 +1,319 @@
+/****************************************************************************
+ * arch/arm/src/stm32wb/hardware/stm32wb_gpio.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_GPIO_H
+#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_GPIO_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define STM32WB_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */
+#define STM32WB_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */
+#define STM32WB_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */
+#define STM32WB_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */
+#define STM32WB_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */
+#define STM32WB_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */
+#define STM32WB_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */
+#define STM32WB_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */
+#define STM32WB_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */
+#define STM32WB_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */
+#define STM32WB_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */
+
+/* Register Addresses *******************************************************/
+
+#define STM32WB_GPIOA_MODER (STM32WB_GPIOA_BASE + STM32WB_GPIO_MODER_OFFSET)
+#define STM32WB_GPIOA_OTYPER (STM32WB_GPIOA_BASE + STM32WB_GPIO_OTYPER_OFFSET)
+#define STM32WB_GPIOA_OSPEED (STM32WB_GPIOA_BASE + STM32WB_GPIO_OSPEED_OFFSET)
+#define STM32WB_GPIOA_PUPDR (STM32WB_GPIOA_BASE + STM32WB_GPIO_PUPDR_OFFSET)
+#define STM32WB_GPIOA_IDR (STM32WB_GPIOA_BASE + STM32WB_GPIO_IDR_OFFSET)
+#define STM32WB_GPIOA_ODR (STM32WB_GPIOA_BASE + STM32WB_GPIO_ODR_OFFSET)
+#define STM32WB_GPIOA_BSRR (STM32WB_GPIOA_BASE + STM32WB_GPIO_BSRR_OFFSET)
+#define STM32WB_GPIOA_LCKR (STM32WB_GPIOA_BASE + STM32WB_GPIO_LCKR_OFFSET)
+#define STM32WB_GPIOA_AFRL (STM32WB_GPIOA_BASE + STM32WB_GPIO_AFRL_OFFSET)
+#define STM32WB_GPIOA_AFRH (STM32WB_GPIOA_BASE + STM32WB_GPIO_AFRH_OFFSET)
+#define STM32WB_GPIOA_BRR (STM32WB_GPIOA_BASE + STM32WB_GPIO_BRR_OFFSET)
+
+#define STM32WB_GPIOB_MODER (STM32WB_GPIOB_BASE + STM32WB_GPIO_MODER_OFFSET)
+#define STM32WB_GPIOB_OTYPER (STM32WB_GPIOB_BASE + STM32WB_GPIO_OTYPER_OFFSET)
+#define STM32WB_GPIOB_OSPEED (STM32WB_GPIOB_BASE + STM32WB_GPIO_OSPEED_OFFSET)
+#define STM32WB_GPIOB_PUPDR (STM32WB_GPIOB_BASE + STM32WB_GPIO_PUPDR_OFFSET)
+#define STM32WB_GPIOB_IDR (STM32WB_GPIOB_BASE + STM32WB_GPIO_IDR_OFFSET)
+#define STM32WB_GPIOB_ODR (STM32WB_GPIOB_BASE + STM32WB_GPIO_ODR_OFFSET)
+#define STM32WB_GPIOB_BSRR (STM32WB_GPIOB_BASE + STM32WB_GPIO_BSRR_OFFSET)
+#define STM32WB_GPIOB_LCKR (STM32WB_GPIOB_BASE + STM32WB_GPIO_LCKR_OFFSET)
+#define STM32WB_GPIOB_AFRL (STM32WB_GPIOB_BASE + STM32WB_GPIO_AFRL_OFFSET)
+#define STM32WB_GPIOB_AFRH (STM32WB_GPIOB_BASE + STM32WB_GPIO_AFRH_OFFSET)
+#define STM32WB_GPIOB_BRR (STM32WB_GPIOB_BASE + STM32WB_GPIO_BRR_OFFSET)
+
+#define STM32WB_GPIOC_MODER (STM32WB_GPIOC_BASE + STM32WB_GPIO_MODER_OFFSET)
+#define STM32WB_GPIOC_OTYPER (STM32WB_GPIOC_BASE + STM32WB_GPIO_OTYPER_OFFSET)
+#define STM32WB_GPIOC_OSPEED (STM32WB_GPIOC_BASE + STM32WB_GPIO_OSPEED_OFFSET)
+#define STM32WB_GPIOC_PUPDR (STM32WB_GPIOC_BASE + STM32WB_GPIO_PUPDR_OFFSET)
+#define STM32WB_GPIOC_IDR (STM32WB_GPIOC_BASE + STM32WB_GPIO_IDR_OFFSET)
+#define STM32WB_GPIOC_ODR (STM32WB_GPIOC_BASE + STM32WB_GPIO_ODR_OFFSET)
+#define STM32WB_GPIOC_BSRR (STM32WB_GPIOC_BASE + STM32WB_GPIO_BSRR_OFFSET)
+#define STM32WB_GPIOC_LCKR (STM32WB_GPIOC_BASE + STM32WB_GPIO_LCKR_OFFSET)
+#define STM32WB_GPIOC_AFRL (STM32WB_GPIOC_BASE + STM32WB_GPIO_AFRL_OFFSET)
+#define STM32WB_GPIOC_AFRH (STM32WB_GPIOC_BASE + STM32WB_GPIO_AFRH_OFFSET)
+#define STM32WB_GPIOC_BRR (STM32WB_GPIOC_BASE + STM32WB_GPIO_BRR_OFFSET)
+
+#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTD)
+# define STM32WB_GPIOD_MODER (STM32WB_GPIOD_BASE + STM32WB_GPIO_MODER_OFFSET)
+# define STM32WB_GPIOD_OTYPER (STM32WB_GPIOD_BASE + STM32WB_GPIO_OTYPER_OFFSET)
+# define STM32WB_GPIOD_OSPEED (STM32WB_GPIOD_BASE + STM32WB_GPIO_OSPEED_OFFSET)
+# define STM32WB_GPIOD_PUPDR (STM32WB_GPIOD_BASE + STM32WB_GPIO_PUPDR_OFFSET)
+# define STM32WB_GPIOD_IDR (STM32WB_GPIOD_BASE + STM32WB_GPIO_IDR_OFFSET)
+# define STM32WB_GPIOD_ODR (STM32WB_GPIOD_BASE + STM32WB_GPIO_ODR_OFFSET)
+# define STM32WB_GPIOD_BSRR (STM32WB_GPIOD_BASE + STM32WB_GPIO_BSRR_OFFSET)
+# define STM32WB_GPIOD_LCKR (STM32WB_GPIOD_BASE + STM32WB_GPIO_LCKR_OFFSET)
+# define STM32WB_GPIOD_AFRL (STM32WB_GPIOD_BASE + STM32WB_GPIO_AFRL_OFFSET)
+# define STM32WB_GPIOD_AFRH (STM32WB_GPIOD_BASE + STM32WB_GPIO_AFRH_OFFSET)
+# define STM32WB_GPIOD_BRR (STM32WB_GPIOD_BASE + STM32WB_GPIO_BRR_OFFSET)
+#endif
+
+#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTE)
+# define STM32WB_GPIOE_MODER (STM32WB_GPIOE_BASE + STM32WB_GPIO_MODER_OFFSET)
+# define STM32WB_GPIOE_OTYPER (STM32WB_GPIOE_BASE + STM32WB_GPIO_OTYPER_OFFSET)
+# define STM32WB_GPIOE_OSPEED (STM32WB_GPIOE_BASE + STM32WB_GPIO_OSPEED_OFFSET)
+# define STM32WB_GPIOE_PUPDR (STM32WB_GPIOE_BASE + STM32WB_GPIO_PUPDR_OFFSET)
+# define STM32WB_GPIOE_IDR (STM32WB_GPIOE_BASE + STM32WB_GPIO_IDR_OFFSET)
+# define STM32WB_GPIOE_ODR (STM32WB_GPIOE_BASE + STM32WB_GPIO_ODR_OFFSET)
+# define STM32WB_GPIOE_BSRR (STM32WB_GPIOE_BASE + STM32WB_GPIO_BSRR_OFFSET)
+# define STM32WB_GPIOE_LCKR (STM32WB_GPIOE_BASE + STM32WB_GPIO_LCKR_OFFSET)
+# define STM32WB_GPIOE_AFRL (STM32WB_GPIOE_BASE + STM32WB_GPIO_AFRL_OFFSET)
+# define STM32WB_GPIOE_BRR (STM32WB_GPIOE_BASE + STM32WB_GPIO_BRR_OFFSET)
+#endif
+
+#define STM32WB_GPIOH_MODER (STM32WB_GPIOH_BASE + STM32WB_GPIO_MODER_OFFSET)
+#define STM32WB_GPIOH_OTYPER (STM32WB_GPIOH_BASE + STM32WB_GPIO_OTYPER_OFFSET)
+#define STM32WB_GPIOH_OSPEED (STM32WB_GPIOH_BASE + STM32WB_GPIO_OSPEED_OFFSET)
+#define STM32WB_GPIOH_PUPDR (STM32WB_GPIOH_BASE + STM32WB_GPIO_PUPDR_OFFSET)
+#define STM32WB_GPIOH_IDR (STM32WB_GPIOH_BASE + STM32WB_GPIO_IDR_OFFSET)
+#define STM32WB_GPIOH_ODR (STM32WB_GPIOH_BASE + STM32WB_GPIO_ODR_OFFSET)
+#define STM32WB_GPIOH_BSRR (STM32WB_GPIOH_BASE + STM32WB_GPIO_BSRR_OFFSET)
+#define STM32WB_GPIOH_LCKR (STM32WB_GPIOH_BASE + STM32WB_GPIO_LCKR_OFFSET)
+#define STM32WB_GPIOH_AFRL (STM32WB_GPIOH_BASE + STM32WB_GPIO_AFRL_OFFSET)
+#define STM32WB_GPIOH_BRR (STM32WB_GPIOH_BASE + STM32WB_GPIO_BRR_OFFSET)
+
+/* Register Bitfield Definitions ********************************************/
+
+/* GPIO port mode register */
+
+#define GPIO_MODER_INPUT (0x0) /* Input mode */
+#define GPIO_MODER_OUTPUT (0x1) /* General purpose output mode */
+#define GPIO_MODER_ALT (0x2) /* Alternate mode */
+#define GPIO_MODER_ANALOG (0x3) /* Analog mode (reset state) */
+
+#define GPIO_MODER_SHIFT(n) ((n) << 1)
+#define GPIO_MODER_MASK(n) (0x3 << GPIO_MODER_SHIFT(n))
+
+#define GPIO_MODER0_SHIFT (0)
+#define GPIO_MODER0_MASK (0x3 << GPIO_MODER0_SHIFT)
+#define GPIO_MODER1_SHIFT (2)
+#define GPIO_MODER1_MASK (0x3 << GPIO_MODER1_SHIFT)
+#define GPIO_MODER2_SHIFT (4)
+#define GPIO_MODER2_MASK (0x3 << GPIO_MODER2_SHIFT)
+#define GPIO_MODER3_SHIFT (6)
+#define GPIO_MODER3_MASK (0x3 << GPIO_MODER3_SHIFT)
+#define GPIO_MODER4_SHIFT (8)
+#define GPIO_MODER4_MASK (0x3 << GPIO_MODER4_SHIFT)
+#define GPIO_MODER5_SHIFT (10)
+#define GPIO_MODER5_MASK (0x3 << GPIO_MODER5_SHIFT)
+#define GPIO_MODER6_SHIFT (12)
+#define GPIO_MODER6_MASK (0x3 << GPIO_MODER6_SHIFT)
+#define GPIO_MODER7_SHIFT (14)
+#define GPIO_MODER7_MASK (0x3 << GPIO_MODER7_SHIFT)
+#define GPIO_MODER8_SHIFT (16)
+#define GPIO_MODER8_MASK (0x3 << GPIO_MODER8_SHIFT)
+#define GPIO_MODER9_SHIFT (18)
+#define GPIO_MODER9_MASK (0x3 << GPIO_MODER9_SHIFT)
+#define GPIO_MODER10_SHIFT (20)
+#define GPIO_MODER10_MASK (0x3 << GPIO_MODER10_SHIFT)
+#define GPIO_MODER11_SHIFT (22)
+#define GPIO_MODER11_MASK (0x3 << GPIO_MODER11_SHIFT)
+#define GPIO_MODER12_SHIFT (24)
+#define GPIO_MODER12_MASK (0x3 << GPIO_MODER12_SHIFT)
+#define GPIO_MODER13_SHIFT (26)
+#define GPIO_MODER13_MASK (0x3 << GPIO_MODER13_SHIFT)
+#define GPIO_MODER14_SHIFT (28)
+#define GPIO_MODER14_MASK (0x3 << GPIO_MODER14_SHIFT)
+#define GPIO_MODER15_SHIFT (30)
+#define GPIO_MODER15_MASK (0x3 << GPIO_MODER15_SHIFT)
+
+/* GPIO port output type register */
+
+#define GPIO_OTYPER_PP(n) (0) /* 0=Output push-pull (reset state) */
+#define GPIO_OTYPER_OD(n) (1 << (n)) /* 1=Output open-drain */
+
+/* GPIO port output speed register */
+
+#define GPIO_OSPEED_5MHz (0x0) /* 5 MHz Low speed output */
+#define GPIO_OSPEED_25MHz (0x1) /* 25 MHz Medium speed output */
+#define GPIO_OSPEED_50MHz (0x2) /* 50 MHz Fast speed output */
+#define GPIO_OSPEED_120MHz (0x3) /* 120 MHz High speed output */
+
+#define GPIO_OSPEED_SHIFT(n) ((n) << 1)
+#define GPIO_OSPEED_MASK(n) (0x3 << GPIO_OSPEED_SHIFT(n))
+
+#define GPIO_OSPEED0_SHIFT (0)
+#define GPIO_OSPEED0_MASK (0x3 << GPIO_OSPEED0_SHIFT)
+#define GPIO_OSPEED1_SHIFT (2)
+#define GPIO_OSPEED1_MASK (0x3 << GPIO_OSPEED1_SHIFT)
+#define GPIO_OSPEED2_SHIFT (4)
+#define GPIO_OSPEED2_MASK (0x3 << GPIO_OSPEED2_SHIFT)
+#define GPIO_OSPEED3_SHIFT (6)
+#define GPIO_OSPEED3_MASK (0x3 << GPIO_OSPEED3_SHIFT)
+#define GPIO_OSPEED4_SHIFT (8)
+#define GPIO_OSPEED4_MASK (0x3 << GPIO_OSPEED4_SHIFT)
+#define GPIO_OSPEED5_SHIFT (10)
+#define GPIO_OSPEED5_MASK (0x3 << GPIO_OSPEED5_SHIFT)
+#define GPIO_OSPEED6_SHIFT (12)
+#define GPIO_OSPEED6_MASK (0x3 << GPIO_OSPEED6_SHIFT)
+#define GPIO_OSPEED7_SHIFT (14)
+#define GPIO_OSPEED7_MASK (0x3 << GPIO_OSPEED7_SHIFT)
+#define GPIO_OSPEED8_SHIFT (16)
+#define GPIO_OSPEED8_MASK (0x3 << GPIO_OSPEED8_SHIFT)
+#define GPIO_OSPEED9_SHIFT (18)
+#define GPIO_OSPEED9_MASK (0x3 << GPIO_OSPEED9_SHIFT)
+#define GPIO_OSPEED10_SHIFT (20)
+#define GPIO_OSPEED10_MASK (0x3 << GPIO_OSPEED10_SHIFT)
+#define GPIO_OSPEED11_SHIFT (22)
+#define GPIO_OSPEED11_MASK (0x3 << GPIO_OSPEED11_SHIFT)
+#define GPIO_OSPEED12_SHIFT (24)
+#define GPIO_OSPEED12_MASK (0x3 << GPIO_OSPEED12_SHIFT)
+#define GPIO_OSPEED13_SHIFT (26)
+#define GPIO_OSPEED13_MASK (0x3 << GPIO_OSPEED13_SHIFT)
+#define GPIO_OSPEED14_SHIFT (28)
+#define GPIO_OSPEED14_MASK (0x3 << GPIO_OSPEED14_SHIFT)
+#define GPIO_OSPEED15_SHIFT (30)
+#define GPIO_OSPEED15_MASK (0x3 << GPIO_OSPEED15_SHIFT)
+
+/* GPIO port pull-up/pull-down register */
+
+#define GPIO_PUPDR_NONE (0x0) /* No pull-up, pull-down */
+#define GPIO_PUPDR_PULLUP (0x1) /* Pull-up */
+#define GPIO_PUPDR_PULLDOWN (0x2) /* Pull-down */
+
+#define GPIO_PUPDR_SHIFT(n) ((n) << 1)
+#define GPIO_PUPDR_MASK(n) (0x3 << GPIO_PUPDR_SHIFT(n))
+
+#define GPIO_PUPDR0_SHIFT (0)
+#define GPIO_PUPDR0_MASK (0x3 << GPIO_PUPDR0_SHIFT)
+#define GPIO_PUPDR1_SHIFT (2)
+#define GPIO_PUPDR1_MASK (0x3 << GPIO_PUPDR1_SHIFT)
+#define GPIO_PUPDR2_SHIFT (4)
+#define GPIO_PUPDR2_MASK (0x3 << GPIO_PUPDR2_SHIFT)
+#define GPIO_PUPDR3_SHIFT (6)
+#define GPIO_PUPDR3_MASK (0x3 << GPIO_PUPDR3_SHIFT)
+#define GPIO_PUPDR4_SHIFT (8)
+#define GPIO_PUPDR4_MASK (0x3 << GPIO_PUPDR4_SHIFT)
+#define GPIO_PUPDR5_SHIFT (10)
+#define GPIO_PUPDR5_MASK (0x3 << GPIO_PUPDR5_SHIFT)
+#define GPIO_PUPDR6_SHIFT (12)
+#define GPIO_PUPDR6_MASK (0x3 << GPIO_PUPDR6_SHIFT)
+#define GPIO_PUPDR7_SHIFT (14)
+#define GPIO_PUPDR7_MASK (0x3 << GPIO_PUPDR7_SHIFT)
+#define GPIO_PUPDR8_SHIFT (16)
+#define GPIO_PUPDR8_MASK (0x3 << GPIO_PUPDR8_SHIFT)
+#define GPIO_PUPDR9_SHIFT (18)
+#define GPIO_PUPDR9_MASK (0x3 << GPIO_PUPDR9_SHIFT)
+#define GPIO_PUPDR10_SHIFT (20)
+#define GPIO_PUPDR10_MASK (0x3 << GPIO_PUPDR10_SHIFT)
+#define GPIO_PUPDR11_SHIFT (22)
+#define GPIO_PUPDR11_MASK (0x3 << GPIO_PUPDR11_SHIFT)
+#define GPIO_PUPDR12_SHIFT (24)
+#define GPIO_PUPDR12_MASK (0x3 << GPIO_PUPDR12_SHIFT)
+#define GPIO_PUPDR13_SHIFT (26)
+#define GPIO_PUPDR13_MASK (0x3 << GPIO_PUPDR13_SHIFT)
+#define GPIO_PUPDR14_SHIFT (28)
+#define GPIO_PUPDR14_MASK (0x3 << GPIO_PUPDR14_SHIFT)
+#define GPIO_PUPDR15_SHIFT (30)
+#define GPIO_PUPDR15_MASK (0x3 << GPIO_PUPDR15_SHIFT)
+
+/* GPIO port input data register */
+
+#define GPIO_IDR(n) (1 << (n))
+
+/* GPIO port output data register */
+
+#define GPIO_ODR(n) (1 << (n))
+
+/* GPIO port bit set/reset register */
+
+#define GPIO_BSRR_SET(n) (1 << (n))
+#define GPIO_BSRR_RESET(n) (1 << ((n) + 16))
+
+/* GPIO port configuration lock register */
+
+#define GPIO_LCKR(n) (1 << (n))
+#define GPIO_LCKK (1 << 16) /* Bit 16: Lock key */
+
+/* GPIO alternate function low register */
+
+#define GPIO_AFRL_AFSEL_SHIFT(n) ((n) << 2) /* Alt function selection for pins 0 to 7 */
+#define GPIO_AFRL_AFSEL_MASK(n) (0xf << GPIO_AFRL_AFSEL_SHIFT(n))
+
+#define GPIO_AFRL_AFSEL0_SHIFT (0)
+#define GPIO_AFRL_AFSEL0_MASK (0xf << GPIO_AFRL_AFSEL0_SHIFT)
+#define GPIO_AFRL_AFSEL1_SHIFT (4)
+#define GPIO_AFRL_AFSEL1_MASK (0xf << GPIO_AFRL_AFSEL1_SHIFT)
+#define GPIO_AFRL_AFSEL2_SHIFT (8)
+#define GPIO_AFRL_AFSEL2_MASK (0xf << GPIO_AFRL_AFSEL2_SHIFT)
+#define GPIO_AFRL_AFSEL3_SHIFT (12)
+#define GPIO_AFRL_AFSEL3_MASK (0xf << GPIO_AFRL_AFSEL3_SHIFT)
+#define GPIO_AFRL_AFSEL4_SHIFT (16)
+#define GPIO_AFRL_AFSEL4_MASK (0xf << GPIO_AFRL_AFSEL4_SHIFT)
+#define GPIO_AFRL_AFSEL5_SHIFT (20)
+#define GPIO_AFRL_AFSEL5_MASK (0xf << GPIO_AFRL_AFSEL5_SHIFT)
+#define GPIO_AFRL_AFSEL6_SHIFT (24)
+#define GPIO_AFRL_AFSEL6_MASK (0xf << GPIO_AFRL_AFSEL6_SHIFT)
+#define GPIO_AFRL_AFSEL7_SHIFT (28)
+#define GPIO_AFRL_AFSEL7_MASK (0xf << GPIO_AFRL_AFSEL7_SHIFT)
+
+/* GPIO alternate function high register */
+
+#define GPIO_AFRH_AFSEL_SHIFT(n) (((n) - 8) << 2) /* Alt function selection for pins 8 to 15 */
+#define GPIO_AFRH_AFSEL_MASK(n) (0xf << GPIO_AFRH_AFSEL_SHIFT(n))
+
+#define GPIO_AFRH_AFSEL8_SHIFT (0)
+#define GPIO_AFRH_AFSEL8_MASK (0xf << GPIO_AFRH_AFSEL8_SHIFT)
+#define GPIO_AFRH_AFSEL9_SHIFT (4)
+#define GPIO_AFRH_AFSEL9_MASK (0xf << GPIO_AFRH_AFSEL9_SHIFT)
+#define GPIO_AFRH_AFSEL10_SHIFT (8)
+#define GPIO_AFRH_AFSEL10_MASK (0xf << GPIO_AFRH_AFSEL10_SHIFT)
+#define GPIO_AFRH_AFSEL11_SHIFT (12)
+#define GPIO_AFRH_AFSEL11_MASK (0xf << GPIO_AFRH_AFSEL11_SHIFT)
+#define GPIO_AFRH_AFSEL12_SHIFT (16)
+#define GPIO_AFRH_AFSEL12_MASK (0xf << GPIO_AFRH_AFSEL12_SHIFT)
+#define GPIO_AFRH_AFSEL13_SHIFT (20)
+#define GPIO_AFRH_AFSEL13_MASK (0xf << GPIO_AFRH_AFSEL13_SHIFT)
+#define GPIO_AFRH_AFSEL14_SHIFT (24)
+#define GPIO_AFRH_AFSEL14_MASK (0xf << GPIO_AFRH_AFSEL14_SHIFT)
+#define GPIO_AFRH_AFSEL15_SHIFT (28)
+#define GPIO_AFRH_AFSEL15_MASK (0xf << GPIO_AFRH_AFSEL15_SHIFT)
+
+/* GPIO port bit reset register */
+
+#define GPIO_BRR_RESET(n) (1 << (n))
+
+#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_GPIO_H */
diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_ipcc.h b/arch/arm/src/stm32wb/hardware/stm32wb_ipcc.h
new file mode 100644
index 0000000000..740f408849
--- /dev/null
+++ b/arch/arm/src/stm32wb/hardware/stm32wb_ipcc.h
@@ -0,0 +1,114 @@
+/****************************************************************************
+ * arch/arm/src/stm32wb/hardware/stm32wb_ipcc.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_IPCC_H
+#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_IPCC_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define STM32WB_IPCC_C1CR_OFFSET 0x0000 /* CPU1 control register */
+#define STM32WB_IPCC_C1MR_OFFSET 0x0004 /* CPU1 mask register */
+#define STM32WB_IPCC_C1SCR_OFFSET 0x0008 /* CPU1 status set/clear register */
+#define STM32WB_IPCC_C1TOC2SR_OFFSET 0x000c /* CPU1 to CPU2 status register */
+#define STM32WB_IPCC_C2CR_OFFSET 0x0010 /* CPU2 control register */
+#define STM32WB_IPCC_C2MR_OFFSET 0x0014 /* CPU2 mask register */
+#define STM32WB_IPCC_C2SCR_OFFSET 0x0018 /* CPU2 status set/clear register */
+#define STM32WB_IPCC_C2TOC1SR_OFFSET 0x001c /* CPU2 to CPU2 status register */
+
+/* Register Addresses *******************************************************/
+
+#define STM32WB_IPCC_C1CR (STM32WB_IPCC_BASE + STM32WB_IPCC_C1CR_OFFSET)
+#define STM32WB_IPCC_C1MR (STM32WB_IPCC_BASE + STM32WB_IPCC_C1MR_OFFSET)
+#define STM32WB_IPCC_C1SCR (STM32WB_IPCC_BASE + STM32WB_IPCC_C1SCR_OFFSET)
+#define STM32WB_IPCC_C1TOC2SR (STM32WB_IPCC_BASE + STM32WB_IPCC_C1TOC2SR_OFFSET)
+#define STM32WB_IPCC_C2CR (STM32WB_IPCC_BASE + STM32WB_IPCC_C2CR_OFFSET)
+#define STM32WB_IPCC_C2MR (STM32WB_IPCC_BASE + STM32WB_IPCC_C2MR_OFFSET)
+#define STM32WB_IPCC_C2SCR (STM32WB_IPCC_BASE + STM32WB_IPCC_C2SCR_OFFSET)
+#define STM32WB_IPCC_C2TOC1SR (STM32WB_IPCC_BASE + STM32WB_IPCC_C2TOC1SR_OFFSET)
+
+/* Register Bitfield Definitions ********************************************/
+
+/* CPU1 control register (C1CR) */
+
+#define IPCC_C1CR_RXOIE (1 << 0) /* Bit 0: Receive channel occupied interrupt enable */
+#define IPCC_C1CR_TXFIE (1 << 16) /* Bit 16: Transmit channel free interrupt enable */
+
+/* CPU1 mask register (C1MR) */
+
+#define IPCC_C1MR_OM_SHIFT (0) /* Bits 0-5: Receive channels occupied interrupt mask */
+#define IPCC_C1MR_OM_MASK (0x3f << IPCC_C1MR_OM_SHIFT)
+#define IPCC_C1MR_OM_BIT(n) (1 << (IPCC_C1MR_OM_SHIFT + (n) - 1)) /* Receive channel n = 1..6 */
+
+#define IPCC_C1MR_FM_SHIFT (16) /* Bits 16-21: Transmit channels free interrupt mask */
+#define IPCC_C1MR_FM_MASK (0x3f << IPCC_C1MR_FM_SHIFT)
+#define IPCC_C1MR_FM_BIT(n) (1 << (IPCC_C1MR_FM_SHIFT + (n) - 1)) /* Transmit channel n = 1..6 */
+
+/* CPU1 status set/clear register (C1SCR) */
+
+#define IPCC_C1SCR_CLR_SHIFT (0) /* Bits 0-5: Receive channels status clear mask */
+#define IPCC_C1SCR_CLR_MASK (0x3f << IPCC_C1SCR_CLR_SHIFT)
+#define IPCC_C1SCR_CLR_BIT(n) (1 << (IPCC_C1SCR_CLR_SHIFT + (n) - 1)) /* Receive channel n = 1..6 */
+
+#define IPCC_C1SCR_SET_SHIFT (16) /* Bits 16-21: Transmit channels status set mask */
+#define IPCC_C1SCR_SET_MASK (0x3f << IPCC_C1SCR_SET_SHIFT)
+#define IPCC_C1SCR_SET_BIT(n) (1 << (IPCC_C1SCR_SET_SHIFT + (n) - 1)) /* Transmit channel n = 1..6 */
+
+/* CPU1 to CPU2 status register (C1TOC2SR) */
+
+#define IPCC_C1TOC2SR_SHIFT (0) /* Bits 0-5: CPU1 to CPU2 channels status flag */
+#define IPCC_C1TOC2SR_MASK (0x3f << IPCC_C1TOC2SR_SHIFT)
+#define IPCC_C1TOC2SR_BIT(n) (1 << (IPCC_C1TOC2SR_SHIFT + (n) - 1)) /* Channel n = 1..6 */
+
+/* CPU2 control register (C2CR) */
+
+#define IPCC_C2CR_RXOIE (1 << 0) /* Bit 0: Receive channel occupied interrupt enable */
+#define IPCC_C2CR_TXFIE (1 << 16) /* Bit 16: Transmit channel free interrupt enable */
+
+/* CPU2 mask register (C2MR) */
+
+#define IPCC_C2MR_OM_SHIFT (0) /* Bits 0-5: Receive channels occupied interrupt mask */
+#define IPCC_C2MR_OM_MASK (0x3f << IPCC_C2MR_OM_SHIFT)
+#define IPCC_C2MR_OM_BIT(n) (1 << (IPCC_C2MR_OM_SHIFT + (n) - 1)) /* Receive channel n = 1..6 */
+
+#define IPCC_C2MR_FM_SHIFT (16) /* Bits 16-21: Transmit channels free interrupt mask */
+#define IPCC_C2MR_FM_MASK (0x3f << IPCC_C2MR_FM_SHIFT)
+#define IPCC_C2MR_FM_BIT(n) (1 << (IPCC_C2MR_FM_SHIFT + (n) - 1)) /* Transmit channel n = 1..6 */
+
+/* CPU2 status set/clear register (C2SCR) */
+
+#define IPCC_C2SCR_CLR_SHIFT (0) /* Bits 0-5: Receive channels status clear mask */
+#define IPCC_C2SCR_CLR_MASK (0x3f << IPCC_C2SCR_CLR_SHIFT)
+#define IPCC_C2SCR_CLR_BIT(n) (1 << (IPCC_C2SCR_CLR_SHIFT + (n) - 1)) /* Receive channel n = 1..6 */
+
+#define IPCC_C2SCR_SET_SHIFT (16) /* Bits 16-21: Transmit channels status set mask */
+#define IPCC_C2SCR_SET_MASK (0x3f << IPCC_C2SCR_SET_SHIFT)
+#define IPCC_C2SCR_SET_BIT(n) (1 << (IPCC_C2SCR_SET_SHIFT + (n) - 1)) /* Transmit channel n = 1..6 */
+
+/* CPU2 to CPU1 status register (C2TOC1SR) */
+
+#define IPCC_C2TOC1SR_SHIFT (0) /* Bits 0-5: CPU2 to CPU1 channels status flag */
+#define IPCC_C2TOC1SR_MASK (0x3f << IPCC_C2TOC1SR_SHIFT)
+#define IPCC_C2TOC1SR_BIT(n) (1 << (IPCC_C2TOC1SR_SHIFT + (n) - 1)) /* Channel n = 1..6 */
+
+#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_IPCC_H */
diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_memorymap.h b/arch/arm/src/stm32wb/hardware/stm32wb_memorymap.h
new file mode 100644
index 0000000000..2d85c6580c
--- /dev/null
+++ b/arch/arm/src/stm32wb/hardware/stm32wb_memorymap.h
@@ -0,0 +1,165 @@
+/****************************************************************************
+ * arch/arm/src/stm32wb/hardware/stm32wb_memorymap.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_MEMORYMAP_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* STM32WBXXX Address Blocks ************************************************/
+
+#define STM32WB_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
+#define STM32WB_SRAM_BASE 0x20000000 /* 0x20000000-0x2003ffff: 256k RAM block */
+#define STM32WB_PERIPH_BASE 0x40000000 /* Peripheral base address */
+#define STM32WB_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */
+
+/* Code Base Addresses ******************************************************/
+
+#define STM32WB_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */
+#define STM32WB_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */
+#define STM32WB_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */
+#define STM32WB_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192к RAM1 block */
+#define STM32WB_SRAM2A_BASE 0x20030000 /* 0x20030000-0x20037fff: 32k RAM2a block */
+#define STM32WB_SRAM2B_BASE 0x20038000 /* 0x20038000-0x2003ffff: 32k RAM2b block */
+
+#define STM32WB_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x20006fff: System memory */
+#define STM32WB_OTP_BASE 0x1fff7000 /* 0x1fff7000-0x1fff73ff: OTP memory */
+#define STM32WB_OPTION_BASE 0x1fff8000 /* 0x1fff8000-0x1fff8fff: Option bytes */
+
+/* System Memory Addresses **************************************************/
+
+#define STM32WB_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */
+#define STM32WB_SYSMEM_FSIZE 0x1fff75e0 /* This bitfield indicates the size of
+ * the device Flash memory expressed in
+ * Kbytes. Example: 0x0400 corresponds
+ * to 1024 Kbytes.
+ */
+#define STM32WB_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package
+ * type. 5 LSB corresponds to:
+ * 0x11: WLCSP100 / UFBGA129
+ * 0x13: VFQFPN68
+ * 0x0A: UFQPFN48
+ */
+
+/* SRAM Base Addresses ******************************************************/
+
+#define STM32WB_SRAMBB_BASE 0x22000000 /* 0x22000000-0x227fffff: SRAM bit-band region */
+
+/* Peripheral Base Addresses ************************************************/
+
+#define STM32WB_APB1_BASE 0x40000000 /* 0x40000000-0x400097ff: APB1 */
+ /* 0x40009800-0x4000ffff: Reserved */
+#define STM32WB_APB2_BASE 0x40010000 /* 0x40010000-0x400157ff: APB2 */
+ /* 0x40015800-0x4001ffff: Reserved */
+#define STM32WB_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: AHB1 */
+ /* 0x40024400-0x47ffffff: Reserved */
+#define STM32WB_AHB2_BASE 0x48000000 /* 0x48000000-0x500603ff: AHB2 */
+ /* 0x50060400-0x57ffffff: Reserved */
+#define STM32WB_AHB4_BASE 0x58000000 /* 0x58000000-0x580043ff: AHB4 */
+ /* 0x58004400-0x5fffffff: Reserved */
+#define STM32WB_APB3_BASE 0x60000000 /* 0x60000000-0x60001fff: APB3 */
+ /* 0x60002000-0x8fffffff: Reserved */
+#define STM32WB_AHB3_BASE 0x90000000 /* 0x90000000-0xA00013ff: AHB3 */
+
+/* APB1 Base Addresses ******************************************************/
+
+#define STM32WB_TIM2_BASE 0x40000000
+#define STM32WB_LCD_BASE 0x40002400
+#define STM32WB_RTC_BASE 0x40002800
+#define STM32WB_WWDG_BASE 0x40002c00
+#define STM32WB_IWDG_BASE 0x40003000
+#define STM32WB_SPI2_BASE 0x40003800
+#define STM32WB_I2C1_BASE 0x40005400
+#define STM32WB_I2C3_BASE 0x40005c00
+#define STM32WB_CRS_BASE 0x40006000
+#define STM32WB_USB1_BASE 0x40006800
+#define STM32WB_USB1_PMAADDR 0x40006c00
+#define STM32WB_LPTIM1_BASE 0x40007c00
+#define STM32WB_LPUART1_BASE 0x40008000
+#define STM32WB_LPTIM2_BASE 0x40009400
+
+/* APB2 Base Addresses ******************************************************/
+
+#define STM32WB_SYSCFG_BASE 0x40010000
+#define STM32WB_VREFBUF_BASE 0x40010030
+#define STM32WB_COMP1_BASE 0x40010200
+#define STM32WB_COMP2_BASE 0x40010204
+#define STM32WB_TIM1_BASE 0x40012c00
+#define STM32WB_SPI1_BASE 0x40013000
+#define STM32WB_USART1_BASE 0x40013800
+#define STM32WB_TIM16_BASE 0x40014400
+#define STM32WB_TIM17_BASE 0x40014800
+#define STM32WB_SAI1_BASE 0x40015400
+
+/* AHB1 Base Addresses ******************************************************/
+
+#define STM32WB_DMA1_BASE 0x40020000
+#define STM32WB_DMA2_BASE 0x40020400
+#define STM32WB_DMAMUX1_BASE 0x40020800
+#define STM32WB_CRC_BASE 0x40023000
+#define STM32WB_TSC_BASE 0x40024000
+
+/* AHB2 Base Addresses ******************************************************/
+
+#define STM32WB_GPIOA_BASE 0x48000000
+#define STM32WB_GPIOB_BASE 0x48000400
+#define STM32WB_GPIOC_BASE 0x48000800
+#define STM32WB_GPIOD_BASE 0x48000c00
+#define STM32WB_GPIOE_BASE 0x48001000
+#define STM32WB_GPIOH_BASE 0x48001c00
+#define STM32WB_ADC1_BASE 0x50040000
+#define STM32WB_AES1_BASE 0x50060000
+
+/* AHB4 Base Addresses ******************************************************/
+
+#define STM32WB_RCC_BASE 0x58000000
+#define STM32WB_PWR_BASE 0x58000400
+#define STM32WB_EXTI_BASE 0x58000800
+#define STM32WB_IPCC_BASE 0x58000c00
+#define STM32WB_RNG_BASE 0x58001000
+#define STM32WB_HSEM_BASE 0x58001400
+#define STM32WB_AES2_BASE 0x58001800
+#define STM32WB_PKA_BASE 0x58002000
+#define STM32WB_FLASHREG_BASE 0x58004000
+
+/* APB3 Base Addresses ******************************************************/
+
+#define STM32WB_BLE_BASE 0x60000000
+#define STM32WB_RADIO_BASE 0x60000400
+#define STM32WB_802154_BASE 0x60001000
+
+/* AHB3 Base Addresses ******************************************************/
+
+#define STM32WB_QSPI_BASE 0x90000000
+#define STM32WB_QSPI_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QSPI memory mapping */
+#define STM32WB_QSPIREF_BASE 0xa0001000
+
+/* Cortex-M4 Base Addresses *************************************************/
+
+/* Other registers -- see armv7-m/nvic.h for standard Cortex-M4 registers in
+ * this address range
+ */
+
+#define STM32WB_SCS_BASE 0xe000e000
+#define STM32WB_DEBUGMCU_BASE 0xe0042000
+
+#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_MEMORYMAP_H */
diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_pinmap.h b/arch/arm/src/stm32wb/hardware/stm32wb_pinmap.h
new file mode 100644
index 0000000000..e8162b71f7
--- /dev/null
+++ b/arch/arm/src/stm32wb/hardware/stm32wb_pinmap.h
@@ -0,0 +1,606 @@
+/****************************************************************************
+ * arch/arm/src/stm32wb/hardware/stm32wb_pinmap.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_PINMAP_H
+#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_PINMAP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Alternate Pin Functions. All members of the STM32WB3x and STM32WB5x
+ * family share the same pin multiplexing (although they may differ in the
+ * pins physically available), while the STM32WB1x family have some
+ * differences.
+ *
+ * Alternative pin selections are provided with a numeric suffix like _1, _2,
+ * etc. Drivers, however, will use the pin selection without the numeric
+ * suffix. Additional definitions are required in the board.h file. For
+ * example, if CAN1_RX connects vis PA11 on some board, then the following
+ * definitions should appear in the board.h header file for that board:
+ *
+ * #define GPIO_CAN1_RX GPIO_CAN1_RX_1
+ *
+ * The driver will then automatically configure PA11 as the CAN1 RX pin.
+ */
+
+/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
+ * Additional effort is required to select specific GPIO options such as
+ * frequency, open-drain/push-pull, and pull-up/down! Just the basics are
+ * defined for most pins in this file.
+ */
+
+/* ADC */
+
+#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15)
+# define GPIO_ADC1_IN2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7)
+# define GPIO_ADC1_IN3 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN8)
+# define GPIO_ADC1_IN4 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN9)
+#elif defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_ADC1_IN1 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN0)
+# define GPIO_ADC1_IN2 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN1)
+# define GPIO_ADC1_IN3 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN2)
+# define GPIO_ADC1_IN4 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN3)
+#endif
+
+#define GPIO_ADC1_IN5 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN0)
+#define GPIO_ADC1_IN6 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1)
+#define GPIO_ADC1_IN7 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN2)
+#define GPIO_ADC1_IN8 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3)
+#define GPIO_ADC1_IN9 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4)
+#define GPIO_ADC1_IN10 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5)
+#define GPIO_ADC1_IN11 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN6)
+
+#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \
+ || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55)
+# define GPIO_ADC1_IN12 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7)
+# define GPIO_ADC1_IN15 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN8)
+# define GPIO_ADC1_IN16 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN9)
+#endif
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_ADC1_IN13 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN4)
+# define GPIO_ADC1_IN14 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5)
+#endif
+
+/* Clocks outputs */
+
+#define GPIO_MCO (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN8)
+
+/* Comparators */
+
+#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55)
+
+#define GPIO_COMP1_INP_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1)
+#define GPIO_COMP1_INP_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN2)
+#define GPIO_COMP1_INM_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN0)
+#define GPIO_COMP1_INM_2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4)
+#define GPIO_COMP1_INM_3 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5)
+#define GPIO_COMP1_INM_4 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN9)
+#define GPIO_COMP1_OUT_1 (GPIO_ALT | GPIO_AF12 | GPIO_PORTA | GPIO_PIN0)
+#define GPIO_COMP1_OUT_2 (GPIO_ALT | GPIO_AF12 | GPIO_PORTB | GPIO_PIN0)
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_COMP1_INP_3 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5)
+# define GPIO_COMP1_INM_5 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN4)
+# define GPIO_COMP1_OUT_3 (GPIO_ALT | GPIO_AF12 | GPIO_PORTB | GPIO_PIN10)
+#endif
+
+#define GPIO_COMP2_INP_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN4)
+#define GPIO_COMP2_INP_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN6)
+#define GPIO_COMP2_INP_3 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3)
+#define GPIO_COMP2_INM_1 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN3)
+#define GPIO_COMP2_INM_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN7)
+#define GPIO_COMP2_INM_3 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN2)
+#define GPIO_COMP2_INM_4 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4)
+#define GPIO_COMP2_INM_5 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5)
+#define GPIO_COMP2_OUT_1 (GPIO_ALT | GPIO_AF12 | GPIO_PORTA | GPIO_PIN2)
+#define GPIO_COMP2_OUT_2 (GPIO_ALT | GPIO_AF12 | GPIO_PORTA | GPIO_PIN7)
+#define GPIO_COMP2_OUT_3 (GPIO_ALT | GPIO_AF12 | GPIO_PORTB | GPIO_PIN5)
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_COMP2_OUT_4 (GPIO_ALT | GPIO_AF12 | GPIO_PORTB | GPIO_PIN11)
+#endif
+
+#endif /* defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */
+
+/* I2C */
+
+#define GPIO_I2C1_SDA_1 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN7)
+#define GPIO_I2C1_SDA_3 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTA | GPIO_PIN10)
+#define GPIO_I2C1_SCL_1 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN6)
+#define GPIO_I2C1_SCL_2 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN8)
+#define GPIO_I2C1_SCL_3 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTA | GPIO_PIN9)
+#define GPIO_I2C1_SMBA_1 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN1)
+#define GPIO_I2C1_SMBA_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN14)
+#define GPIO_I2C1_SMBA_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN5)
+
+#if !defined(CONFIG_STM32WB_IO_CONFIG_C_49)
+# define GPIO_I2C1_SDA_2 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN9)
+#endif
+
+#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55)
+
+#define GPIO_I2C3_SDA_1 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN4)
+#define GPIO_I2C3_SCL_1 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTA | GPIO_PIN7)
+#define GPIO_I2C3_SMBA_1 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN2)
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_I2C3_SMBA_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN12)
+# define GPIO_I2C3_SDA_2 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN11)
+# define GPIO_I2C3_SDA_3 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN14)
+# define GPIO_I2C3_SCL_2 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN10)
+# define GPIO_I2C3_SCL_3 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN13)
+# define GPIO_I2C3_SCL_4 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTC | GPIO_PIN0)
+# define GPIO_I2C3_SDA_4 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTC | GPIO_PIN1)
+#endif
+
+#endif /* defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */
+
+/* JTAG/SWD */
+
+#define GPIO_JTMS_SWDIO (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN13)
+#define GPIO_JTCK_SWCLK (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN14)
+#define GPIO_NJTRST (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN4)
+
+#if !defined(CONFIG_STM32WB_IO_CONFIG_C_49)
+# define GPIO_JTDO_SWO (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN3)
+# define GPIO_JTDI (GPIO_ALT | GPIO_AF0 | GPIO_PORTA | GPIO_PIN15)
+#endif
+
+/* QUADSPI */
+
+#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55)
+
+#define GPIO_QSPI_NCS_1 (GPIO_ALT | GPIO_AF10 | GPIO_PORTA | GPIO_PIN2)
+#define GPIO_QSPI_CLK_1 (GPIO_ALT | GPIO_AF10 | GPIO_PORTA | GPIO_PIN3)
+#define GPIO_QSPI_BK1_IO0_1 (GPIO_ALT | GPIO_AF10 | GPIO_PORTB | GPIO_PIN9)
+#define GPIO_QSPI_BK1_IO1_1 (GPIO_ALT | GPIO_AF10 | GPIO_PORTB | GPIO_PIN8)
+#define GPIO_QSPI_BK1_IO2_1 (GPIO_ALT | GPIO_AF10 | GPIO_PORTA | GPIO_PIN7)
+#define GPIO_QSPI_BK1_IO3_1 (GPIO_ALT | GPIO_AF10 | GPIO_PORTA | GPIO_PIN6)
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_QSPI_NCS_2 (GPIO_ALT | GPIO_AF10 | GPIO_PORTB | GPIO_PIN11)
+# define GPIO_QSPI_CLK_2 (GPIO_ALT | GPIO_AF10 | GPIO_PORTB | GPIO_PIN10)
+#endif
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_QSPI_NCS_3 (GPIO_ALT | GPIO_AF10 | GPIO_PORTD | GPIO_PIN3)
+# define GPIO_QSPI_BK1_IO0_2 (GPIO_ALT | GPIO_AF10 | GPIO_PORTD | GPIO_PIN4)
+# define GPIO_QSPI_BK1_IO1_2 (GPIO_ALT | GPIO_AF10 | GPIO_PORTD | GPIO_PIN5)
+# define GPIO_QSPI_BK1_IO2_2 (GPIO_ALT | GPIO_AF10 | GPIO_PORTD | GPIO_PIN6)
+# define GPIO_QSPI_BK1_IO3_2 (GPIO_ALT | GPIO_AF10 | GPIO_PORTD | GPIO_PIN7)
+#endif
+
+#endif /* defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */
+
+/* RTC */
+
+#define GPIO_RTC_OUT_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN2)
+#define GPIO_RTC_TAMP2 (GPIO_PORTA | GPIO_PIN0)
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_RTC_OUT_2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN13)
+# define GPIO_RTC_REFIN (GPIO_ALT | GPIO_AF0 | GPIO_PORTB | GPIO_PIN15)
+# define GPIO_RTC_TS (GPIO_PORTC | GPIO_PIN13)
+# define GPIO_RTC_TAMP1 (GPIO_PORTC | GPIO_PIN13)
+# define GPIO_RTC_TAMP3 (GPIO_PORTC | GPIO_PIN12)
+#endif
+
+/* SAI */
+
+#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55)
+
+#define GPIO_SAI1_EXTCLK_1 (GPIO_ALT | GPIO_AF13 | GPIO_PORTA | GPIO_PIN0)
+#define GPIO_SAI1_EXTCLK_2 (GPIO_ALT | GPIO_AF13 | GPIO_PORTB | GPIO_PIN2)
+#define GPIO_SAI1_FS_A_1 (GPIO_ALT | GPIO_AF13 | GPIO_PORTA | GPIO_PIN9)
+#define GPIO_SAI1_FS_A_2 (GPIO_ALT | GPIO_AF13 | GPIO_PORTB | GPIO_PIN9)
+#define GPIO_SAI1_SCK_A_1 (GPIO_ALT | GPIO_AF13 | GPIO_PORTA | GPIO_PIN8)
+#define GPIO_SAI1_SD_A_1 (GPIO_ALT | GPIO_AF13 | GPIO_PORTA | GPIO_PIN10)
+#define GPIO_SAI1_MCLK_A_1 (GPIO_ALT | GPIO_AF13 | GPIO_PORTA | GPIO_PIN3)
+#define GPIO_SAI1_MCLK_A_2 (GPIO_ALT | GPIO_AF13 | GPIO_PORTB | GPIO_PIN8)
+#define GPIO_SAI1_FS_B_1 (GPIO_ALT | GPIO_AF13 | GPIO_PORTA | GPIO_PIN4)
+#define GPIO_SAI1_FS_B_2 (GPIO_ALT | GPIO_AF13 | GPIO_PORTA | GPIO_PIN14)
+#define GPIO_SAI1_FS_B_3 (GPIO_ALT | GPIO_AF13 | GPIO_PORTB | GPIO_PIN6)
+#define GPIO_SAI1_SCK_B_1 (GPIO_ALT | GPIO_AF13 | GPIO_PORTB | GPIO_PIN3)
+#define GPIO_SAI1_SD_B_1 (GPIO_ALT | GPIO_AF13 | GPIO_PORTA | GPIO_PIN5)
+#define GPIO_SAI1_SD_B_2 (GPIO_ALT | GPIO_AF13 | GPIO_PORTA | GPIO_PIN13)
+#define GPIO_SAI1_SD_B_3 (GPIO_ALT | GPIO_AF13 | GPIO_PORTB | GPIO_PIN5)
+#define GPIO_SAI1_PDMCK1_1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN3)
+#define GPIO_SAI1_PDMCK1_2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN8)
+#define GPIO_SAI1_PDMCK2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN8)
+#define GPIO_SAI1_PDMDI1_1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN10)
+#define GPIO_SAI1_PDMDI2_1 (GPIO_ALT | GPIO_AF3 | GPIO_PORTA | GPIO_PIN9)
+#define GPIO_SAI1_PDMDI2_2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN9)
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_SAI1_FS_A_3 (GPIO_ALT | GPIO_AF13 | GPIO_PORTB | GPIO_PIN12)
+# define GPIO_SAI1_SCK_A_2 (GPIO_ALT | GPIO_AF13 | GPIO_PORTB | GPIO_PIN10)
+# define GPIO_SAI1_SCK_A_3 (GPIO_ALT | GPIO_AF13 | GPIO_PORTB | GPIO_PIN13)
+# define GPIO_SAI1_SD_A_2 (GPIO_ALT | GPIO_AF13 | GPIO_PORTB | GPIO_PIN15)
+# define GPIO_SAI1_SD_A_3 (GPIO_ALT | GPIO_AF13 | GPIO_PORTC | GPIO_PIN3)
+# define GPIO_SAI1_MCLK_A_3 (GPIO_ALT | GPIO_AF13 | GPIO_PORTB | GPIO_PIN14)
+# define GPIO_SAI1_PDMDI1_2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTC | GPIO_PIN3)
+#endif
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_SAI1_SD_A_4 (GPIO_ALT | GPIO_AF13 | GPIO_PORTD | GPIO_PIN6)
+# define GPIO_SAI1_MCLK_A_4 (GPIO_ALT | GPIO_AF13 | GPIO_PORTE | GPIO_PIN2)
+# define GPIO_SAI1_SCK_B_2 (GPIO_ALT | GPIO_AF13 | GPIO_PORTC | GPIO_PIN9)
+# define GPIO_SAI1_PDMCK1_3 (GPIO_ALT | GPIO_AF3 | GPIO_PORTE | GPIO_PIN2)
+# define GPIO_SAI1_PDMDI1_3 (GPIO_ALT | GPIO_AF3 | GPIO_PORTD | GPIO_PIN6)
+#endif
+
+#endif /* defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */
+
+/* SPI */
+
+#define GPIO_SPI1_NSS_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN4)
+#define GPIO_SPI1_NSS_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN2)
+#define GPIO_SPI1_SCK_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN1)
+#define GPIO_SPI1_SCK_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN5)
+#define GPIO_SPI1_MOSI_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN7)
+#define GPIO_SPI1_MOSI_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN12)
+#define GPIO_SPI1_MOSI_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN5)
+#define GPIO_SPI1_MISO_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN6)
+#define GPIO_SPI1_MISO_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN11)
+#define GPIO_SPI1_MISO_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN4)
+
+#if !defined(CONFIG_STM32WB_IO_CONFIG_C_49)
+# define GPIO_SPI1_NSS_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN15)
+# define GPIO_SPI1_SCK_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN3)
+#endif
+
+#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15)
+# define GPIO_SPI1_MOSI_4 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN5)
+# define GPIO_SPI1_MOSI_5 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN13)
+# define GPIO_SPI1_NSS_4 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN14)
+# define GPIO_SPI1_NSS_5 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN6)
+#endif
+
+#if defined(CONFIG_STM32WB_STM32WB55)
+
+#define GPIO_SPI2_NSS_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN9)
+#define GPIO_SPI2_NSS_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN12)
+#define GPIO_SPI2_NSS_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTD | GPIO_PIN0)
+#define GPIO_SPI2_SCK_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN9)
+#define GPIO_SPI2_SCK_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN13)
+#define GPIO_SPI2_SCK_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTD | GPIO_PIN1)
+#define GPIO_SPI2_SCK_5 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN10)
+#define GPIO_SPI2_MOSI_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN15)
+#define GPIO_SPI2_MOSI_2 (GPIO_ALT | GPIO_AF3 | GPIO_PORTC | GPIO_PIN1)
+#define GPIO_SPI2_MOSI_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTC | GPIO_PIN3)
+#define GPIO_SPI2_MISO_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN14)
+#define GPIO_SPI2_MISO_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTC | GPIO_PIN2)
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_SPI2_SCK_4 (GPIO_ALT | GPIO_AF3 | GPIO_PORTD | GPIO_PIN3)
+# define GPIO_SPI2_MOSI_4 (GPIO_ALT | GPIO_AF5 | GPIO_PORTD | GPIO_PIN4)
+# define GPIO_SPI2_MISO_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTD | GPIO_PIN3)
+#endif
+
+#endif /* defined(CONFIG_STM32WB_STM32WB55) */
+
+/* Timers */
+
+#define GPIO_TIM1_ETR_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN12)
+#define GPIO_TIM1_BKIN1_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN6)
+#define GPIO_TIM1_BKIN1_2 (GPIO_ALT | GPIO_AF12 | GPIO_PORTA | GPIO_PIN6)
+#define GPIO_TIM1_BKIN1_3 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN7)
+#define GPIO_TIM1_BKIN2_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN11)
+#define GPIO_TIM1_BKIN2_2 (GPIO_ALT | GPIO_AF12 | GPIO_PORTA | GPIO_PIN11)
+#define GPIO_TIM1_CH1IN_1 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN8)
+#define GPIO_TIM1_CH1OUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN8)
+#define GPIO_TIM1_CH1N_1 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN7)
+#define GPIO_TIM1_CH2IN_1 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN9)
+#define GPIO_TIM1_CH2OUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN9)
+#define GPIO_TIM1_CH2N_1 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN8)
+#define GPIO_TIM1_CH3IN_1 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN10)
+#define GPIO_TIM1_CH3OUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN10)
+#define GPIO_TIM1_CH4IN (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN11)
+#define GPIO_TIM1_CH4OUT (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN11)
+
+#if !defined(CONFIG_STM32WB_IO_CONFIG_C_49)
+# define GPIO_TIM1_CH3N_1 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN9)
+#endif
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_TIM1_BKIN1_4 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN12)
+# define GPIO_TIM1_BKIN1_5 (GPIO_ALT | GPIO_AF3 | GPIO_PORTB | GPIO_PIN12)
+# define GPIO_TIM1_CH1N_2 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN13)
+# define GPIO_TIM1_CH2N_2 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN14)
+# define GPIO_TIM1_CH3N_2 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN15)
+#endif
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_TIM1_ETR_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTE | GPIO_PIN0)
+# define GPIO_TIM1_CH1IN_2 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTD | GPIO_PIN14)
+# define GPIO_TIM1_CH1OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN14)
+# define GPIO_TIM1_CH2IN_2 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTD | GPIO_PIN15)
+# define GPIO_TIM1_CH2OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN15)
+#endif
+
+#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15)
+# define GPIO_TIM1_CH3IN_2 (GPIO_ALT | GPIO_AF12 | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN7)
+# define GPIO_TIM1_CH3OUT_2 (GPIO_ALT | GPIO_AF12 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN7)
+#endif
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_C_48E)
+# define GPIO_TIM1_CH1IN_3 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN14)
+# define GPIO_TIM1_CH1OUT_3 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN14)
+#endif
+
+#define GPIO_TIM2_ETR_1 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN0)
+#define GPIO_TIM2_ETR_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN5)
+#define GPIO_TIM2_CH1IN_1 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN0)
+#define GPIO_TIM2_CH1OUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN0)
+#define GPIO_TIM2_CH1IN_2 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN5)
+#define GPIO_TIM2_CH1OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN5)
+#define GPIO_TIM2_CH2IN_1 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN1)
+#define GPIO_TIM2_CH2OUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN1)
+#define GPIO_TIM2_CH3IN_1 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN2)
+#define GPIO_TIM2_CH3OUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN2)
+#define GPIO_TIM2_CH4IN_1 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN3)
+#define GPIO_TIM2_CH4OUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN3)
+
+#if !defined(CONFIG_STM32WB_IO_CONFIG_C_49)
+# define GPIO_TIM2_ETR_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN15)
+# define GPIO_TIM2_CH1IN_3 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN15)
+# define GPIO_TIM2_CH1OUT_3 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN15)
+# define GPIO_TIM2_CH2IN_2 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN3)
+# define GPIO_TIM2_CH2OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN3)
+#endif
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_TIM2_CH3IN_2 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN10)
+# define GPIO_TIM2_CH3OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN10)
+# define GPIO_TIM2_CH4IN_2 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN11)
+# define GPIO_TIM2_CH4OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN11)
+#endif
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_C_48E)
+# define GPIO_TIM2_CH1IN_4 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN15)
+# define GPIO_TIM2_CH1OUT_4 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN15)
+# define GPIO_TIM2_CH2IN_3 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN12)
+# define GPIO_TIM2_CH2OUT_3 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN12)
+# define GPIO_TIM2_CH3IN_3 (GPIO_ALT | GPIO_AF1 | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN13)
+# define GPIO_TIM2_CH3OUT_3 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN13)
+#endif
+
+#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \
+ || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55)
+
+#define GPIO_TIM16_BKIN (GPIO_ALT | GPIO_AF14 | GPIO_PORTB | GPIO_PIN5)
+#define GPIO_TIM16_CH1IN_1 (GPIO_ALT | GPIO_AF14 | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN8)
+#define GPIO_TIM16_CH1OUT_1 (GPIO_ALT | GPIO_AF14 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN8)
+#define GPIO_TIM16_CH1IN_2 (GPIO_ALT | GPIO_AF14 | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN6)
+#define GPIO_TIM16_CH1OUT_2 (GPIO_ALT | GPIO_AF14 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN6)
+#define GPIO_TIM16_CH1N (GPIO_ALT | GPIO_AF14 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN6)
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_TIM16_CH1IN_3 (GPIO_ALT | GPIO_AF14 | GPIO_FLOAT | GPIO_PORTE | GPIO_PIN0)
+# define GPIO_TIM16_CH1OUT_3 (GPIO_ALT | GPIO_AF14 | GPIO_PUSHPULL | GPIO_PORTE | GPIO_PIN0)
+#endif
+
+#define GPIO_TIM17_BKIN (GPIO_ALT | GPIO_AF14 | GPIO_PORTB | GPIO_PIN4)
+#define GPIO_TIM17_CH1IN_1 (GPIO_ALT | GPIO_AF14 | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN9)
+#define GPIO_TIM17_CH1OUT_1 (GPIO_ALT | GPIO_AF14 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN9)
+#define GPIO_TIM17_CH1IN_2 (GPIO_ALT | GPIO_AF14 | GPIO_FLOAT | GPIO_PORTA | GPIO_PIN7)
+#define GPIO_TIM17_CH1OUT_2 (GPIO_ALT | GPIO_AF14 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN7)
+#define GPIO_TIM17_CH1N (GPIO_ALT | GPIO_AF14 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN7)
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_TIM17_CH1IN_3 (GPIO_ALT | GPIO_AF14 | GPIO_FLOAT | GPIO_PORTE | GPIO_PIN1)
+# define GPIO_TIM17_CH1OUT_3 (GPIO_ALT | GPIO_AF14 | GPIO_PUSHPULL | GPIO_PORTE | GPIO_PIN1)
+#endif
+
+#endif /* defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */
+
+#define GPIO_LPTIM1_ETR_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN6)
+#define GPIO_LPTIM1_OUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN14)
+#define GPIO_LPTIM1_OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN2)
+#define GPIO_LPTIM1_IN1_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN5)
+#define GPIO_LPTIM1_IN2_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN7)
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_LPTIM1_ETR_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN3)
+# define GPIO_LPTIM1_IN1_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN0)
+# define GPIO_LPTIM1_OUT_3 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN1)
+# define GPIO_LPTIM1_IN2_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTC | GPIO_PIN2)
+#endif
+
+#define GPIO_LPTIM2_ETR_1 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN5)
+#define GPIO_LPTIM2_OUT_1 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN4)
+#define GPIO_LPTIM2_OUT_2 (GPIO_ALT | GPIO_AF14 | GPIO_PORTA | GPIO_PIN8)
+#define GPIO_LPTIM2_IN1_1 (GPIO_ALT | GPIO_AF14 | GPIO_PORTB | GPIO_PIN1)
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_LPTIM2_ETR_2 (GPIO_ALT | GPIO_AF14 | GPIO_PORTC | GPIO_PIN3)
+# define GPIO_LPTIM2_IN1_2 (GPIO_ALT | GPIO_AF14 | GPIO_PORTC | GPIO_PIN0)
+#endif
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_LPTIM2_ETR_3 (GPIO_ALT | GPIO_AF14 | GPIO_PORTD | GPIO_PIN11)
+# define GPIO_LPTIM2_OUT_3 (GPIO_ALT | GPIO_AF14 | GPIO_PORTD | GPIO_PIN13)
+# define GPIO_LPTIM2_IN1_3 (GPIO_ALT | GPIO_AF14 | GPIO_PORTD | GPIO_PIN12)
+#endif
+
+/* Touch Screen Controller */
+
+#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) || defined(CONFIG_STM32WB_STM32WB55)
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_TSC_SYNC_1 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN10)
+#endif
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_TSC_SYNC_2 (GPIO_ALT | GPIO_AF9 | GPIO_PORTD | GPIO_PIN2)
+#endif
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) || defined(CONFIG_STM32WB_IO_CONFIG_C_48E)
+# define GPIO_TSC_G1_IO1 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN12)
+# define GPIO_TSC_G1_IO2 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN13)
+#endif
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_TSC_G1_IO3 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN14)
+# define GPIO_TSC_G1_IO4 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN15)
+#endif
+
+#define GPIO_TSC_G2_IO1 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN4)
+#define GPIO_TSC_G2_IO2 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN5)
+#define GPIO_TSC_G2_IO3 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN6)
+#define GPIO_TSC_G2_IO4 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN7)
+
+#if !defined(CONFIG_STM32WB_IO_CONFIG_C_49)
+# define GPIO_TSC_G3_IO1 (GPIO_ALT | GPIO_AF9 | GPIO_PORTA | GPIO_PIN15)
+#endif
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_TSC_G3_IO2 (GPIO_ALT | GPIO_AF9 | GPIO_PORTC | GPIO_PIN10)
+# define GPIO_TSC_G3_IO3 (GPIO_ALT | GPIO_AF9 | GPIO_PORTC | GPIO_PIN11)
+# define GPIO_TSC_G3_IO4 (GPIO_ALT | GPIO_AF9 | GPIO_PORTC | GPIO_PIN12)
+#endif
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_C_48E)
+# define GPIO_TSC_G3_IO2 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN10)
+# define GPIO_TSC_G3_IO3 (GPIO_ALT | GPIO_AF9 | GPIO_PORTC | GPIO_PIN1)
+#endif
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_TSC_G4_IO1 (GPIO_ALT | GPIO_AF9 | GPIO_PORTC | GPIO_PIN6)
+#endif
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_TSC_G4_IO2 (GPIO_ALT | GPIO_AF9 | GPIO_PORTC | GPIO_PIN7)
+# define GPIO_TSC_G4_IO3 (GPIO_ALT | GPIO_AF9 | GPIO_PORTC | GPIO_PIN8)
+# define GPIO_TSC_G4_IO4 (GPIO_ALT | GPIO_AF9 | GPIO_PORTC | GPIO_PIN9)
+#endif
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_TSC_G5_IO1 (GPIO_ALT | GPIO_AF9 | GPIO_PORTD | GPIO_PIN4)
+# define GPIO_TSC_G5_IO2 (GPIO_ALT | GPIO_AF9 | GPIO_PORTD | GPIO_PIN5)
+# define GPIO_TSC_G5_IO3 (GPIO_ALT | GPIO_AF9 | GPIO_PORTD | GPIO_PIN6)
+# define GPIO_TSC_G5_IO4 (GPIO_ALT | GPIO_AF9 | GPIO_PORTD | GPIO_PIN7)
+#endif
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_TSC_G6_IO1 (GPIO_ALT | GPIO_AF9 | GPIO_PORTD | GPIO_PIN10)
+# define GPIO_TSC_G6_IO2 (GPIO_ALT | GPIO_AF9 | GPIO_PORTD | GPIO_PIN11)
+# define GPIO_TSC_G6_IO3 (GPIO_ALT | GPIO_AF9 | GPIO_PORTD | GPIO_PIN12)
+# define GPIO_TSC_G6_IO4 (GPIO_ALT | GPIO_AF9 | GPIO_PORTD | GPIO_PIN13)
+#endif
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_TSC_G7_IO1 (GPIO_ALT | GPIO_AF9 | GPIO_PORTE | GPIO_PIN0)
+# define GPIO_TSC_G7_IO2 (GPIO_ALT | GPIO_AF9 | GPIO_PORTE | GPIO_PIN1)
+# define GPIO_TSC_G7_IO3 (GPIO_ALT | GPIO_AF9 | GPIO_PORTE | GPIO_PIN2)
+#endif
+
+#if defined(CONFIG_STM32WB_STM32WB15)
+# define GPIO_TSC_G7_IO1 (GPIO_ALT | GPIO_AF9 | GPIO_PORTA | GPIO_PIN13)
+# define GPIO_TSC_G7_IO2 (GPIO_ALT | GPIO_AF9 | GPIO_PORTA | GPIO_PIN10)
+# define GPIO_TSC_G7_IO3 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN8)
+#endif
+
+#define GPIO_TSC_G7_IO4 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN9)
+
+#endif /* defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) || defined(CONFIG_STM32WB_STM32WB55) */
+
+/* IR interface (with timers 16 and 17) */
+
+#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \
+ || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55)
+# define GPIO_IR_OUT_1 (GPIO_ALT | GPIO_AF8 | GPIO_PORTA | GPIO_PIN13)
+# define GPIO_IR_OUT_2 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN9)
+#endif
+
+/* Trace port */
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_TRACED1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN10)
+# define GPIO_TRACED3 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN12)
+#endif
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_TRACECK (GPIO_ALT | GPIO_AF0 | GPIO_PORTE | GPIO_PIN2)
+# define GPIO_TRACED0 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN9)
+# define GPIO_TRACED2 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN2)
+#endif
+
+/* USART/LPUART */
+
+#define GPIO_USART1_TX_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN9)
+#define GPIO_USART1_TX_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTB | GPIO_PIN6)
+#define GPIO_USART1_RX_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN10)
+#define GPIO_USART1_RX_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTB | GPIO_PIN7)
+#define GPIO_USART1_CK_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN8)
+#define GPIO_USART1_CK_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTB | GPIO_PIN5)
+#define GPIO_USART1_CTS_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN11)
+#define GPIO_USART1_CTS_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTB | GPIO_PIN4)
+#define GPIO_USART1_RTS_DE_1 (GPIO_ALT | GPIO_AF7 | GPIO_PORTA | GPIO_PIN12)
+
+#if !defined(CONFIG_STM32WB_IO_CONFIG_C_49)
+# define GPIO_USART1_RTS_DE_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTB | GPIO_PIN3)
+#endif
+
+#if defined(CONFIG_STM32WB_STM32WB15) || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55)
+
+#define GPIO_LPUART1_TX_1 (GPIO_ALT | GPIO_AF8 | GPIO_PORTA | GPIO_PIN2)
+#define GPIO_LPUART1_TX_2 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN5)
+#define GPIO_LPUART1_RX_1 (GPIO_ALT | GPIO_AF8 | GPIO_PORTA | GPIO_PIN3)
+#define GPIO_LPUART1_RX_2 (GPIO_ALT | GPIO_AF8 | GPIO_PORTA | GPIO_PIN12)
+#define GPIO_LPUART1_CTS_1 (GPIO_ALT | GPIO_AF8 | GPIO_PORTA | GPIO_PIN6)
+#define GPIO_LPUART1_RTS_DE_1 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN1)
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_LPUART1_TX_3 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN11)
+# define GPIO_LPUART1_TX_4 (GPIO_ALT | GPIO_AF8 | GPIO_PORTC | GPIO_PIN1)
+# define GPIO_LPUART1_RX_3 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN10)
+# define GPIO_LPUART1_RX_4 (GPIO_ALT | GPIO_AF8 | GPIO_PORTC | GPIO_PIN0)
+# define GPIO_LPUART1_CTS_2 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN13)
+# define GPIO_LPUART1_RTS_DE_2 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN12)
+#endif
+
+#endif /* defined(CONFIG_STM32WB_STM32WB15) || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */
+
+/* USB */
+
+#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55)
+
+#define GPIO_USB_CRS_SYNC (GPIO_ALT | GPIO_AF10 | GPIO_PORTA | GPIO_PIN10)
+#define GPIO_USB_DM (GPIO_ALT | GPIO_AF10 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN11)
+#define GPIO_USB_DP (GPIO_ALT | GPIO_AF10 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN12)
+#define GPIO_USB_NOE_1 (GPIO_ALT | GPIO_AF10 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN13)
+
+#if defined(CONFIG_STM32WB_IO_CONFIG_V)
+# define GPIO_USB_NOE_2 (GPIO_ALT | GPIO_AF10 | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN9)
+#endif
+
+#endif /* defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */
+
+#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_PINMAP_H */
diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_pwr.h b/arch/arm/src/stm32wb/hardware/stm32wb_pwr.h
new file mode 100644
index 0000000000..fe9ef2117c
--- /dev/null
+++ b/arch/arm/src/stm32wb/hardware/stm32wb_pwr.h
@@ -0,0 +1,324 @@
+/****************************************************************************
+ * arch/arm/src/stm32wb/hardware/stm32wb_pwr.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_PWR_H
+#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_PWR_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define STM32WB_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */
+#define STM32WB_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */
+#define STM32WB_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */
+#define STM32WB_PWR_CR4_OFFSET 0x000C /* Power control register 4 */
+#define STM32WB_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */
+#define STM32WB_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */
+#define STM32WB_PWR_SCR_OFFSET 0x0018 /* Power status clear register */
+#define STM32WB_PWR_CR5_OFFSET 0x001C /* Power control register 5 */
+#define STM32WB_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */
+#define STM32WB_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */
+#define STM32WB_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */
+#define STM32WB_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */
+#define STM32WB_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */
+#define STM32WB_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */
+#define STM32WB_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */
+#define STM32WB_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */
+#define STM32WB_PWR_PUCRE_OFFSET 0x0040 /* Power Port E pull-up control register */
+#define STM32WB_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */
+#define STM32WB_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */
+#define STM32WB_PWR_C2CR1_OFFSET 0x0080 /* CPU2 control register 1 */
+#define STM32WB_PWR_C2CR3_OFFSET 0x0084 /* CPU2 control register 3 */
+#define STM32WB_PWR_EXTSCR_OFFSET 0x0088 /* Extended status and status clear register */
+
+/* Register Addresses *******************************************************/
+
+#define STM32WB_PWR_CR1 (STM32WB_PWR_BASE + STM32WB_PWR_CR1_OFFSET)
+#define STM32WB_PWR_CR2 (STM32WB_PWR_BASE + STM32WB_PWR_CR2_OFFSET)
+#define STM32WB_PWR_CR3 (STM32WB_PWR_BASE + STM32WB_PWR_CR3_OFFSET)
+#define STM32WB_PWR_CR4 (STM32WB_PWR_BASE + STM32WB_PWR_CR4_OFFSET)
+#define STM32WB_PWR_SR1 (STM32WB_PWR_BASE + STM32WB_PWR_SR1_OFFSET)
+#define STM32WB_PWR_SR2 (STM32WB_PWR_BASE + STM32WB_PWR_SR2_OFFSET)
+#define STM32WB_PWR_SCR (STM32WB_PWR_BASE + STM32WB_PWR_SCR_OFFSET)
+#define STM32WB_PWR_CR5 (STM32WB_PWR_BASE + STM32WB_PWR_CR5_OFFSET)
+#define STM32WB_PWR_PUCRA (STM32WB_PWR_BASE + STM32WB_PWR_PUCRA_OFFSET)
+#define STM32WB_PWR_PDCRA (STM32WB_PWR_BASE + STM32WB_PWR_PDCRA_OFFSET)
+#define STM32WB_PWR_PUCRB (STM32WB_PWR_BASE + STM32WB_PWR_PUCRB_OFFSET)
+#define STM32WB_PWR_PDCRB (STM32WB_PWR_BASE + STM32WB_PWR_PDCRB_OFFSET)
+#define STM32WB_PWR_PUCRC (STM32WB_PWR_BASE + STM32WB_PWR_PUCRC_OFFSET)
+#define STM32WB_PWR_PDCRC (STM32WB_PWR_BASE + STM32WB_PWR_PDCRC_OFFSET)
+#define STM32WB_PWR_PUCRD (STM32WB_PWR_BASE + STM32WB_PWR_PUCRD_OFFSET)
+#define STM32WB_PWR_PDCRD (STM32WB_PWR_BASE + STM32WB_PWR_PDCRD_OFFSET)
+#define STM32WB_PWR_PUCRE (STM32WB_PWR_BASE + STM32WB_PWR_PUCRE_OFFSET)
+#define STM32WB_PWR_PDCRE (STM32WB_PWR_BASE + STM32WB_PWR_PDCRE_OFFSET)
+#define STM32WB_PWR_PUCRH (STM32WB_PWR_BASE + STM32WB_PWR_PUCRH_OFFSET)
+#define STM32WB_PWR_PDCRH (STM32WB_PWR_BASE + STM32WB_PWR_PDCRH_OFFSET)
+#define STM32WB_PWR_C2CR1 (STM32WB_PWR_BASE + STM32WB_PWR_C2CR1_OFFSET)
+#define STM32WB_PWR_C2CR3 (STM32WB_PWR_BASE + STM32WB_PWR_C2CR3_OFFSET)
+#define STM32WB_PWR_EXTSCR (STM32WB_PWR_BASE + STM32WB_PWR_EXTSCR_OFFSET)
+
+/* Register Bitfield Definitions ********************************************/
+
+/* Power control register 1 */
+
+#define PWR_CR1_LPMS_SHIFT (0)
+#define PWR_CR1_LPMS_MASK (0x7 << PWR_CR1_LPMS_SHIFT) /* Bits 0-2: Low-power mode selection */
+# define PWR_CR1_LPMS_STOP0 (0x0 << PWR_CR1_LPMS_SHIFT) /* 000: Stop 0 mode */
+# define PWR_CR1_LPMS_STOP1 (0x1 << PWR_CR1_LPMS_SHIFT) /* 001: Stop 1 mode */
+# define PWR_CR1_LPMS_STOP2 (0x2 << PWR_CR1_LPMS_SHIFT) /* 010: Stop 2 mode */
+# define PWR_CR1_LPMS_STANDBY (0x3 << PWR_CR1_LPMS_SHIFT) /* 011: Standby mode */
+# define PWR_CR1_LPMS_SHUTDOWN (0x4 << PWR_CR1_LPMS_SHIFT) /* 1xx: Shutdown mode */
+
+#define PWR_CR1_FPDR (1 << 4) /* Bit 4: Flash memory power down during LPRun */
+#define PWR_CR1_FPDS (1 << 5) /* Bit 5: Flash memory power down during LPSleep */
+#define PWR_CR1_DBP (1 << 8) /* Bit 8: Disable Backup domain write protection */
+#define PWR_CR1_VOS_SHIFT (9)
+# define PWR_CR1_VOS_MASK (0x3 << PWR_CR1_VOS_SHIFT) /* Bits 9-10: Voltage scaling range selection */
+# define PWR_CR1_VOS_RANGE1 (0x1 << PWR_CR1_VOS_SHIFT) /* 01: Range 1 (1.2V, up to 64 MHz) */
+# define PWR_CR1_VOS_RANGE2 (0x2 << PWR_CR1_VOS_SHIFT) /* 10: Range 2 (1.0V, up to 16 MHz) */
+
+#define PWR_CR1_LPR (1 << 14) /* Bit 14: Low-power run */
+
+/* Power control register 2 */
+
+#define PWR_CR2_PVDE (1 << 0) /* Bit 0: Power voltage detector enable */
+#define PWR_CR2_PLS_SHIFT (1)
+#define PWR_CR2_PLS_MASK (0x7 << PWR_CR2_PLS_SHIFT) /* Bits 1-3: Power voltage detector level selection */
+# define PWR_CR2_PLS_2000mv (0x0 << PWR_CR2_PLS_SHIFT) /* 000: VPVD0 around 2.0V */
+# define PWR_CR2_PLS_2200mv (0x1 << PWR_CR2_PLS_SHIFT) /* 001: VPVD1 around 2.2V */
+# define PWR_CR2_PLS_2400mv (0x2 << PWR_CR2_PLS_SHIFT) /* 010: VPVD2 around 2.4V */
+# define PWR_CR2_PLS_2500mv (0x3 << PWR_CR2_PLS_SHIFT) /* 011: VPVD3 around 2.5V */
+# define PWR_CR2_PLS_2600mv (0x4 << PWR_CR2_PLS_SHIFT) /* 100: VPVD4 around 2.6V */
+# define PWR_CR2_PLS_2800mv (0x5 << PWR_CR2_PLS_SHIFT) /* 101: VPVD5 around 2.8V */
+# define PWR_CR2_PLS_2900mv (0x6 << PWR_CR2_PLS_SHIFT) /* 110: VPVD6 around 2.9V */
+# define PWR_CR2_PLS_EXT (0x7 << PWR_CR2_PLS_SHIFT) /* 111: External input analog voltage PVD_IN */
+
+#define PWR_CR2_PVME1 (1 << 4) /* Bit 4: Peripheral voltage monitoring 1 enable (VDDUSB vs 1.2V) */
+#define PWR_CR2_PVME3 (1 << 6) /* Bit 6: Peripheral voltage monitoring 3 enable (VDDA vs 1.62V) */
+#define PWR_CR2_PVME4 (1 << 7) /* Bit 7: Peripheral voltage monitoring 4 enable (VDDA vs 2.2V) */
+#define PWR_CR2_USV (1 << 10) /* Bit 10: VDDUSB supply validate */
+
+/* Power control register 3 */
+
+#define PWR_CR3_EWUP1 (1 << 0) /* Bit 0: Enable Wakeup pin WKUP1 */
+#define PWR_CR3_EWUP2 (1 << 1) /* Bit 1: Enable Wakeup pin WKUP2 */
+#define PWR_CR3_EWUP3 (1 << 2) /* Bit 2: Enable Wakeup pin WKUP3 */
+#define PWR_CR3_EWUP4 (1 << 3) /* Bit 3: Enable Wakeup pin WKUP4 */
+#define PWR_CR3_EWUP5 (1 << 4) /* Bit 4: Enable Wakeup pin WKUP5 */
+#define PWR_CR3_EBORHSMPSFB (1 << 8) /* Bit 8: Enable BORH and SMPS forced in Bypass interrupts */
+#define PWR_CR3_RRS (1 << 9) /* Bit 9: SRAM2a retention in Standby mode */
+#define PWR_CR3_APC (1 << 10) /* Bit 10: Apply pull-up and pull-down configuration */
+#define PWR_CR3_ECRPE (1 << 11) /* Bit 11: Enable critical radio phase end of activity interrupt */
+#define PWR_CR3_EBLEA (1 << 12) /* Bit 12: Enable BLE end of activity interrupt */
+#define PWR_CR3_E802A (1 << 13) /* Bit 13: Enable 802.15.4 end of activity interrupt */
+#define PWR_CR3_EC2H (1 << 14) /* Bit 14: Enable CPU2 Hold interrupt */
+#define PWR_CR3_EIWUL (1 << 15) /* Bit 15: Enable internal wakeup line */
+
+/* Power control register 4 */
+
+#define PWR_CR4_WP1 (1 << 0) /* Bit 0: Wakeup pin WKUP1 polarity */
+# define PWR_CR4_WP1_HI (0 << 0) /* 0: Detection on high level (rising edge) */
+# define PWR_CR4_WP1_LOW (1 << 0) /* 1: Detection on low level (failing edge) */
+
+#define PWR_CR4_WP2 (1 << 1) /* Bit 1: Wakeup pin WKUP2 polarity */
+# define PWR_CR4_WP2_HI (0 << 1) /* 0: Detection on high level (rising edge) */
+# define PWR_CR4_WP2_LOW (1 << 1) /* 1: Detection on low level (failing edge) */
+
+#define PWR_CR4_WP3 (1 << 2) /* Bit 2: Wakeup pin WKUP3 polarity */
+# define PWR_CR4_WP3_HI (0 << 2) /* 0: Detection on high level (rising edge) */
+# define PWR_CR4_WP3_LOW (1 << 2) /* 1: Detection on low level (failing edge) */
+
+#define PWR_CR4_WP4 (1 << 3) /* Bit 3: Wakeup pin WKUP4 polarity */
+# define PWR_CR4_WP4_HI (0 << 3) /* 0: Detection on high level (rising edge) */
+# define PWR_CR4_WP4_LOW (1 << 3) /* 1: Detection on low level (failing edge) */
+
+#define PWR_CR4_WP5 (1 << 4) /* Bit 4: Wakeup pin WKUP5 polarity */
+# define PWR_CR4_WP5_HI (0 << 4) /* 0: Detection on high level (rising edge) */
+# define PWR_CR4_WP5_LOW (1 << 4) /* 1: Detection on low level (failing edge) */
+
+#define PWR_CR4_VBE (1 << 8) /* Bit 8: Vbat battery charging enable */
+#define PWR_CR4_VBRS (1 << 9) /* Bit 9: Vbat battery charging resistor selection */
+# define PWR_CR4_VBRS_5k (0 << 9) /* 0: 5k resistor */
+# define PWR_CR4_VBRS_1k5 (1 << 9) /* 1: 1k5 resistor */
+
+#define PWR_CR4_C2BOOT (1 << 15) /* Bit 15: Boot CPU2 after reset or wakeup from Stop or Standby */
+
+/* Power status register 1 */
+
+#define PWR_SR1_WUF1 (1 << 0) /* Bit 0: Wakeup flag 1 */
+#define PWR_SR1_WUF2 (1 << 1) /* Bit 1: Wakeup flag 2 */
+#define PWR_SR1_WUF3 (1 << 2) /* Bit 2: Wakeup flag 3 */
+#define PWR_SR1_WUF4 (1 << 3) /* Bit 3: Wakeup flag 4 */
+#define PWR_SR1_WUF5 (1 << 4) /* Bit 4: Wakeup flag 5 */
+#define PWR_SR1_SBF (1 << 8) /* Bit 8: Standby flag */
+#define PWR_SR1_WUFI (1 << 15) /* Bit 15: Wakeup internal flag */
+
+/* Power status register 2 */
+
+#define PWR_SR2_SMPSBF (1 << 0) /* Bit 0: SMPS bypass mode flag */
+#define PWR_SR2_SMPSF (1 << 1) /* Bit 1: SMPS ready flag */
+#define PWR_SR2_REGLPS (1 << 8) /* Bit 8: Low power regulator started */
+#define PWR_SR2_REGLPF (1 << 9) /* Bit 9: Low power regulator flag */
+# define PWR_SR2_REGLPF_MR (0 << 9) /* 0: Regulator is ready in main mode */
+# define PWR_SR2_REGLPF_LPR (1 << 9) /* 1: Regulator is in low-power mode */
+
+#define PWR_SR2_VOSF (1 << 10) /* Bit 10: Voltage scaling flag */
+# define PWR_SR2_VOSF_RDY (0 << 10) /* 0: Regulator is ready in the selected voltage range */
+# define PWR_SR2_VOSF_NRDY (1 << 10) /* 1: Regulator voltage is changing */
+
+#define PWR_SR2_PVDO (1 << 11) /* Bit 11: Power voltage detector output */
+# define PWR_SR2_PVDO_ABV (0 << 11) /* 0: Voltage is above the selected PVD threshold */
+# define PWR_SR2_PVDO_BLW (1 << 11) /* 1: Voltage is below the selected PVD threshold */
+
+#define PWR_SR2_PVMO1 (1 << 12) /* Bit 12: VDDUSB voltage monitoring output (VDDUSB vs PVM1) */
+# define PWR_SR2_PVMO1_ABV (0 << 12) /* 0: VDDUSB voltage is above PVM1 threshold (~ 1.2V) */
+# define PWR_SR2_PVMO1_BLW (1 << 12) /* 1: VDDUSB voltage is below PVM1 threshold (~ 1.2V) */
+
+#define PWR_SR2_PVMO3 (1 << 14) /* Bit 14: VDDA voltage monitoring output (VDDA vs PVM3) */
+# define PWR_SR2_PVMO3_ABV (0 << 14) /* 0: VDDA voltage is above PVM3 threshold (~ 1.62V) */
+# define PWR_SR2_PVMO3_BLW (1 << 14) /* 1: VDDA voltage is below PVM3 threshold (~ 1.62V) */
+
+/* Power status clear register */
+
+#define PWR_SCR_CWUF1 (1 << 0) /* Bit 0: Clear wakeup flag 1 */
+#define PWR_SCR_CWUF2 (1 << 1) /* Bit 1: Clear wakeup flag 2 */
+#define PWR_SCR_CWUF3 (1 << 2) /* Bit 2: Clear wakeup flag 3 */
+#define PWR_SCR_CWUF4 (1 << 3) /* Bit 3: Clear wakeup flag 4 */
+#define PWR_SCR_CWUF5 (1 << 4) /* Bit 4: Clear wakeup flag 5 */
+#define PWR_SCR_CSMPSFBF (1 << 7) /* Bit 7: Clear SMPS forced in Bypass interrupt flag */
+#define PWR_SCR_CBORHF (1 << 8) /* Bit 8: Clear BORH interrupt flag */
+#define PWR_SCR_CBLEWUF (1 << 9) /* Bit 9: Clear BLE wakeup interrupt flag */
+#define PWR_SCR_C802WUF (1 << 10) /* Bit 10: Clear 802.15.4 wakeup interrupt flag */
+#define PWR_SCR_CCRPEF (1 << 11) /* Bit 11: Critical radio phase end of activity interrupt flag */
+#define PWR_SCR_CFBLEAF (1 << 12) /* Bit 12: Clear BLE end of activity interrupt flag */
+#define PWR_SCR_C802AF (1 << 13) /* Bit 13: Clear 802.15.4 end of activity interrupt flag */
+#define PWR_SCR_CC2HF (1 << 14) /* Bit 14: Clear CPU2 Hold interrupt flag */
+
+/* Power control register 5 */
+
+#define PWR_CR5_SMPSVOS_SHIFT (0)
+#define PWR_CR5_SMPSVOS_MASK (0xf << PWR_CR5_SMPSVOS_SHIFT) /* Bits 0-3: SMPS voltage output scaling */
+#define PWR_CR5_SMPSSC_SHIFT (4)
+#define PWR_CR5_SMPSSC_MASK (0x7 << PWR_CR5_SMPSSC_SHIFT) /* Bits 4-6: SMPS supply startup current */
+
+#define PWR_CR5_BORHC (1 << 8) /* Bit 8: BORH configuration selection */
+# define PWR_CR5_BORHC_SYSRST (0 << 8) /* 0: BORH generates a system reset */
+# define PWR_CR5_BORHC_SMPSFB (1 << 8) /* 1: BORH forces SMPS bypass mode */
+
+#define PWR_CR5_SMPSEN (1 << 15) /* Bit 15: SMPS enable */
+
+/* Power Port A Pull Up Control Register (PUCRA) */
+
+#define PWR_PUCRA_PU(y) (1 << (y)) /* Port A Pull Up control bit, y = 0..15 */
+
+/* Power Port A Pull Down Control Register (PDCRA) */
+
+#define PWR_PDCRA_PD(y) (1 << (y)) /* Port A Pull Down control bit, y = 0..15 */
+
+/* Power Port B Pull Up Control Register (PUCRB) */
+
+#define PWR_PUCRB_PU(y) (1 << (y)) /* Port B Pull Up control bit, y = 0..15 */
+
+/* Power Port B Pull Down Control Register (PDCRB) */
+
+#define PWR_PDCRB_PD(y) (1 << (y)) /* Port B Pull Down control bit, y = 0..15 */
+
+/* Power Port C Pull Up Control Register (PUCRC) */
+
+#define PWR_PUCRC_PU(y) (1 << (y)) /* Port C Pull Up control bit, y = 0..15 */
+
+/* Power Port C Pull Down Control Register (PDCRC) */
+
+#define PWR_PDCRC_PD(y) (1 << (y)) /* Port C Pull Down control bit, y = 0..15 */
+
+/* Power Port D Pull Up Control Register (PUCRD) */
+
+#define PWR_PUCRD_PU(y) (1 << (y)) /* Port D Pull Up control bit, y = 0..15 */
+
+/* Power Port D Pull Down Control Register (PDCRD) */
+
+#define PWR_PDCRD_PD(y) (1 << (y)) /* Port D Pull Down control bit, y = 0..15 */
+
+/* Power Port E Pull Up Control Register (PUCRE) */
+
+#define PWR_PUCRE_PU(y) (1 << (y)) /* Port E Pull Up control bit, y = 0..4 */
+
+/* Power Port E Pull Down Control Register (PDCRE) */
+
+#define PWR_PDCRE_PD(y) (1 << (y)) /* Port E Pull Down control bit, y = 0..4 */
+
+/* Power Port H Pull Up Control Register (PUCRH) */
+
+#define PWR_PUCRH_PU(y) (1 << (y)) /* Port H Pull Up control bit, y = 0..1 or 3 */
+
+/* Power Port H Pull Down Control Register (PDCRH) */
+
+#define PWR_PDCRH_PD(y) (1 << (y)) /* Port H Pull Down control bit, y = 0..1 or 3 */
+
+/* CPU2 control register 1 */
+
+#define PWR_C2CR1_LPMS_SHIFT (0)
+#define PWR_C2CR1_LPMS_MASK (0x7 << PWR_C2CR1_LPMS_SHIFT) /* Bits 0-2: CPU2 Low-power mode selection */
+# define PWR_C2CR1_LPMS_STOP0 (0x0 << PWR_C2CR1_LPMS_SHIFT) /* 000: Stop 0 mode */
+# define PWR_C2CR1_LPMS_STOP1 (0x1 << PWR_C2CR1_LPMS_SHIFT) /* 001: Stop 1 mode */
+# define PWR_C2CR1_LPMS_STOP2 (0x2 << PWR_C2CR1_LPMS_SHIFT) /* 010: Stop 2 mode */
+# define PWR_C2CR1_LPMS_STANDBY (0x3 << PWR_C2CR1_LPMS_SHIFT) /* 011: Standby mode */
+# define PWR_C2CR1_LPMS_SHUTDOWN (0x4 << PWR_C2CR1_LPMS_SHIFT) /* 1xx: Shutdown mode */
+
+#define PWR_C2CR1_FPDR (1 << 4) /* Bit 4: CPU2 Flash memory power down during LPRun */
+#define PWR_C2CR1_FPDS (1 << 5) /* Bit 5: CPU2 Flash memory power down during LPSleep */
+#define PWR_C2CR1_BLEEWKUP (1 << 14) /* Bit 14: BLE external wakeup */
+#define PWR_C2CR1_800EWKUP (1 << 15) /* Bit 15: 802.15.4 external wakeup */
+
+/* CPU2 control register 3 */
+
+#define PWR_C2CR3_EWUP1 (1 << 0) /* Bit 0: CPU2 Enable Wakeup pin WKUP1 */
+#define PWR_C2CR3_EWUP2 (1 << 1) /* Bit 1: CPU2 Enable Wakeup pin WKUP2 */
+#define PWR_C2CR3_EWUP3 (1 << 2) /* Bit 2: CPU2 Enable Wakeup pin WKUP3 */
+#define PWR_C2CR3_EWUP4 (1 << 3) /* Bit 3: CPU2 Enable Wakeup pin WKUP4 */
+#define PWR_C2CR3_EWUP5 (1 << 4) /* Bit 4: CPU2 Enable Wakeup pin WKUP5 */
+#define PWR_C2CR3_EBLEWUP (1 << 9) /* Bit 9: CPU2 Enable BLE host wakeup interrupt */
+#define PWR_C2CR3_E802WUP (1 << 10) /* Bit 10: CPU2 Enable 802.15.4 host wakeup interrupt */
+#define PWR_C2CR3_APC (1 << 12) /* Bit 12: CPU2 Apply pull-up and pull-down configuration */
+#define PWR_C2CR3_EIWUL (1 << 15) /* Bit 15: CPU2 Enable internal wakeup line */
+
+/* Extended status and status clear register */
+
+#define PWR_EXTSCR_C1CSSF (1 << 0) /* Bit 0: Clear CPU1 Stop Standby flags */
+#define PWR_EXTSCR_C2CSSF (1 << 1) /* Bit 1: Clear CPU2 Stop Standby flags */
+#define PWR_EXTSCR_CCRPF (1 << 2) /* Bit 2: Clear critical radio system phase */
+#define PWR_EXTSCR_C1SBF (1 << 8) /* Bit 8: System Standby flag for CPU1 */
+#define PWR_EXTSCR_C1STOPF (1 << 9) /* Bit 9: System Stop flag for CPU1 */
+#define PWR_EXTSCR_C2SBF (1 << 10) /* Bit 10: System Standby flag for CPU2 */
+#define PWR_EXTSCR_C2STOPF (1 << 11) /* Bit 11: System Stop flag for CPU2 */
+#define PWR_EXTSCR_CRPF (1 << 13) /* Bit 13: Critical radio system phase flag */
+#define PWR_EXTSCR_C1DS (1 << 14) /* Bit 14: CPU1 deepsleep mode */
+#define PWR_EXTSCR_C2DS (1 << 15) /* Bit 15: CPU2 deepsleep mode */
+
+#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_PWR_H */
diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_rcc.h b/arch/arm/src/stm32wb/hardware/stm32wb_rcc.h
new file mode 100644
index 0000000000..6a2e518ead
--- /dev/null
+++ b/arch/arm/src/stm32wb/hardware/stm32wb_rcc.h
@@ -0,0 +1,877 @@
+/****************************************************************************
+ * arch/arm/src/stm32wb/hardware/stm32wb_rcc.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_RCC_H
+#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_RCC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define STM32WB_RCC_CR_OFFSET 0x0000 /* Clock control register */
+#define STM32WB_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */
+#define STM32WB_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */
+#define STM32WB_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */
+#define STM32WB_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */
+#define STM32WB_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */
+#define STM32WB_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */
+#define STM32WB_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */
+#define STM32WB_RCC_SMPSCR_OFFSET 0x0024 /* Step-down converter control register */
+#define STM32WB_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */
+#define STM32WB_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */
+#define STM32WB_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */
+#define STM32WB_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */
+#define STM32WB_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */
+#define STM32WB_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */
+#define STM32WB_RCC_APB3RSTR_OFFSET 0x0044 /* APB3 Peripheral reset register */
+#define STM32WB_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */
+#define STM32WB_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */
+#define STM32WB_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */
+#define STM32WB_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */
+#define STM32WB_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */
+#define STM32WB_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */
+#define STM32WB_RCC_AHB1SMENR_OFFSET 0x0068 /* AHB1 clock enable in sleep and stop modes register */
+#define STM32WB_RCC_AHB2SMENR_OFFSET 0x006c /* AHB2 clock enable in sleep and stop modes register */
+#define STM32WB_RCC_AHB3SMENR_OFFSET 0x0070 /* AHB3 clock enable in sleep and stop modes register */
+#define STM32WB_RCC_APB1SMENR1_OFFSET 0x0078 /* APB1 clock enable in sleep and stop modes register 1 */
+#define STM32WB_RCC_APB1SMENR2_OFFSET 0x007c /* APB1 clock enable in sleep and stop modes register 2 */
+#define STM32WB_RCC_APB2SMENR_OFFSET 0x0080 /* APB2 clock enable in sleep and stop modes register */
+#define STM32WB_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register */
+#define STM32WB_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */
+#define STM32WB_RCC_CSR_OFFSET 0x0094 /* Control/status register */
+#define STM32WB_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */
+#define STM32WB_RCC_HSECR_OFFSET 0x009c /* Clock HSE register */
+#define STM32WB_RCC_EXTCFGR_OFFSET 0x0108 /* Extended clock recovery register */
+#define STM32WB_RCC_C2AHB1ENR_OFFSET 0x0148 /* CPU2 AHB1 Peripheral Clock enable register */
+#define STM32WB_RCC_C2AHB2ENR_OFFSET 0x014c /* CPU2 AHB2 Peripheral Clock enable register */
+#define STM32WB_RCC_C2AHB3ENR_OFFSET 0x0150 /* CPU2 AHB3 Peripheral Clock enable register */
+#define STM32WB_RCC_C2APB1ENR1_OFFSET 0x0158 /* CPU2 APB1 Peripheral Clock enable register 1 */
+#define STM32WB_RCC_C2APB1ENR2_OFFSET 0x015c /* CPU2 APB1 Peripheral Clock enable register 2 */
+#define STM32WB_RCC_C2APB2ENR_OFFSET 0x0160 /* CPU2 APB2 Peripheral Clock enable register */
+#define STM32WB_RCC_C2APB3ENR_OFFSET 0x0164 /* CPU2 APB3 Peripheral Clock enable register */
+#define STM32WB_RCC_C2AHB1SMENR_OFFSET 0x0168 /* CPU2 AHB1 clock enable in sleep and stop modes register */
+#define STM32WB_RCC_C2AHB2SMENR_OFFSET 0x016c /* CPU2 AHB2 clock enable in sleep and stop modes register */
+#define STM32WB_RCC_C2AHB3SMENR_OFFSET 0x0170 /* CPU2 AHB3 clock enable in sleep and stop modes register */
+#define STM32WB_RCC_C2APB1SMENR1_OFFSET 0x0178 /* CPU2 APB1 clock enable in sleep and stop modes register 1 */
+#define STM32WB_RCC_C2APB1SMENR2_OFFSET 0x017c /* CPU2 APB1 clock enable in sleep and stop modes register 2 */
+#define STM32WB_RCC_C2APB2SMENR_OFFSET 0x0180 /* CPU2 APB2 clock enable in sleep and stop modes register */
+#define STM32WB_RCC_C2APB3SMENR_OFFSET 0x0184 /* CPU2 APB3 clock enable in sleep and stop modes register */
+
+/* Register Addresses *******************************************************/
+
+#define STM32WB_RCC_CR (STM32WB_RCC_BASE + STM32WB_RCC_CR_OFFSET)
+#define STM32WB_RCC_ICSCR (STM32WB_RCC_BASE + STM32WB_RCC_ICSCR_OFFSET)
+#define STM32WB_RCC_CFGR (STM32WB_RCC_BASE + STM32WB_RCC_CFGR_OFFSET)
+#define STM32WB_RCC_PLLCFG (STM32WB_RCC_BASE + STM32WB_RCC_PLLCFG_OFFSET)
+#define STM32WB_RCC_PLLSAI1CFG (STM32WB_RCC_BASE + STM32WB_RCC_PLLSAI1CFG_OFFSET)
+#define STM32WB_RCC_CIER (STM32WB_RCC_BASE + STM32WB_RCC_CIER_OFFSET)
+#define STM32WB_RCC_CIFR (STM32WB_RCC_BASE + STM32WB_RCC_CIFR_OFFSET)
+#define STM32WB_RCC_CICR (STM32WB_RCC_BASE + STM32WB_RCC_CICR_OFFSET)
+#define STM32WB_RCC_SMPSCR (STM32WB_RCC_BASE + STM32WB_RCC_SMPSCR_OFFSET)
+#define STM32WB_RCC_AHB1RSTR (STM32WB_RCC_BASE + STM32WB_RCC_AHB1RSTR_OFFSET)
+#define STM32WB_RCC_AHB2RSTR (STM32WB_RCC_BASE + STM32WB_RCC_AHB2RSTR_OFFSET)
+#define STM32WB_RCC_AHB3RSTR (STM32WB_RCC_BASE + STM32WB_RCC_AHB3RSTR_OFFSET)
+#define STM32WB_RCC_APB1RSTR1 (STM32WB_RCC_BASE + STM32WB_RCC_APB1RSTR1_OFFSET)
+#define STM32WB_RCC_APB1RSTR2 (STM32WB_RCC_BASE + STM32WB_RCC_APB1RSTR2_OFFSET)
+#define STM32WB_RCC_APB2RSTR (STM32WB_RCC_BASE + STM32WB_RCC_APB2RSTR_OFFSET)
+#define STM32WB_RCC_APB3RSTR (STM32WB_RCC_BASE + STM32WB_RCC_APB3RSTR_OFFSET)
+#define STM32WB_RCC_AHB1ENR (STM32WB_RCC_BASE + STM32WB_RCC_AHB1ENR_OFFSET)
+#define STM32WB_RCC_AHB2ENR (STM32WB_RCC_BASE + STM32WB_RCC_AHB2ENR_OFFSET)
+#define STM32WB_RCC_AHB3ENR (STM32WB_RCC_BASE + STM32WB_RCC_AHB3ENR_OFFSET)
+#define STM32WB_RCC_APB1ENR1 (STM32WB_RCC_BASE + STM32WB_RCC_APB1ENR1_OFFSET)
+#define STM32WB_RCC_APB1ENR2 (STM32WB_RCC_BASE + STM32WB_RCC_APB1ENR2_OFFSET)
+#define STM32WB_RCC_APB2ENR (STM32WB_RCC_BASE + STM32WB_RCC_APB2ENR_OFFSET)
+#define STM32WB_RCC_AHB1SMENR (STM32WB_RCC_BASE + STM32WB_RCC_AHB1SMENR_OFFSET)
+#define STM32WB_RCC_AHB2SMENR (STM32WB_RCC_BASE + STM32WB_RCC_AHB2SMENR_OFFSET)
+#define STM32WB_RCC_AHB3SMENR (STM32WB_RCC_BASE + STM32WB_RCC_AHB3SMENR_OFFSET)
+#define STM32WB_RCC_APB1SMENR1 (STM32WB_RCC_BASE + STM32WB_RCC_APB1SMENR1_OFFSET)
+#define STM32WB_RCC_APB1SMENR2 (STM32WB_RCC_BASE + STM32WB_RCC_APB1SMENR2_OFFSET)
+#define STM32WB_RCC_APB2SMENR (STM32WB_RCC_BASE + STM32WB_RCC_APB2SMENR_OFFSET)
+#define STM32WB_RCC_CCIPR (STM32WB_RCC_BASE + STM32WB_RCC_CCIPR_OFFSET)
+#define STM32WB_RCC_BDCR (STM32WB_RCC_BASE + STM32WB_RCC_BDCR_OFFSET)
+#define STM32WB_RCC_CSR (STM32WB_RCC_BASE + STM32WB_RCC_CSR_OFFSET)
+#define STM32WB_RCC_CRRCR (STM32WB_RCC_BASE + STM32WB_RCC_CRRCR_OFFSET)
+#define STM32WB_RCC_HSECR (STM32WB_RCC_BASE + STM32WB_RCC_HSECR_OFFSET)
+#define STM32WB_RCC_EXTCFGR (STM32WB_RCC_BASE + STM32WB_RCC_EXTCFGR_OFFSET)
+#define STM32WB_RCC_C2AHB1ENR (STM32WB_RCC_BASE + STM32WB_RCC_C2AHB1ENR_OFFSET)
+#define STM32WB_RCC_C2AHB2ENR (STM32WB_RCC_BASE + STM32WB_RCC_C2AHB2ENR_OFFSET)
+#define STM32WB_RCC_C2AHB3ENR (STM32WB_RCC_BASE + STM32WB_RCC_C2AHB3ENR_OFFSET)
+#define STM32WB_RCC_C2APB1ENR1 (STM32WB_RCC_BASE + STM32WB_RCC_C2APB1ENR1_OFFSET)
+#define STM32WB_RCC_C2APB1ENR2 (STM32WB_RCC_BASE + STM32WB_RCC_C2APB1ENR2_OFFSET)
+#define STM32WB_RCC_C2APB2ENR (STM32WB_RCC_BASE + STM32WB_RCC_C2APB2ENR_OFFSET)
+#define STM32WB_RCC_C2APB3ENR (STM32WB_RCC_BASE + STM32WB_RCC_C2APB3ENR_OFFSET)
+#define STM32WB_RCC_C2AHB1SMENR (STM32WB_RCC_BASE + STM32WB_RCC_C2AHB1SMENR_OFFSET)
+#define STM32WB_RCC_C2AHB2SMENR (STM32WB_RCC_BASE + STM32WB_RCC_C2AHB2SMENR_OFFSET)
+#define STM32WB_RCC_C2AHB3SMENR (STM32WB_RCC_BASE + STM32WB_RCC_C2AHB3SMENR_OFFSET)
+#define STM32WB_RCC_C2APB1SMENR1 (STM32WB_RCC_BASE + STM32WB_RCC_C2APB1SMENR1_OFFSET)
+#define STM32WB_RCC_C2APB1SMENR2 (STM32WB_RCC_BASE + STM32WB_RCC_C2APB1SMENR2_OFFSET)
+#define STM32WB_RCC_C2APB2SMENR (STM32WB_RCC_BASE + STM32WB_RCC_C2APB2SMENR_OFFSET)
+#define STM32WB_RCC_C2APB3SMENR (STM32WB_RCC_BASE + STM32WB_RCC_C2APB3SMENR_OFFSET)
+
+/* Register Bitfield Definitions ********************************************/
+
+/* Clock control register */
+
+#define RCC_CR_MSION (1 << 0) /* Bit 0: Internal Multi Speed clock enable */
+#define RCC_CR_MSIRDY (1 << 1) /* Bit 1: Internal Multi Speed clock ready flag */
+#define RCC_CR_MSIPLLEN (1 << 2) /* Bit 2: MSI clock PLL enable */
+#define RCC_CR_MSIRANGE_SHIFT (4) /* Bits 7-4: MSI clock range */
+#define RCC_CR_MSIRANGE_MASK (0x0f << RCC_CR_MSIRANGE_SHIFT)
+# define RCC_CR_MSIRANGE_100K (0 << RCC_CR_MSIRANGE_SHIFT) /* 0000: around 100 kHz */
+# define RCC_CR_MSIRANGE_200K (1 << RCC_CR_MSIRANGE_SHIFT) /* 0001: around 200 kHz */
+# define RCC_CR_MSIRANGE_400K (2 << RCC_CR_MSIRANGE_SHIFT) /* 0010: around 400 kHz */
+# define RCC_CR_MSIRANGE_800K (3 << RCC_CR_MSIRANGE_SHIFT) /* 0011: around 800 kHz */
+# define RCC_CR_MSIRANGE_1M (4 << RCC_CR_MSIRANGE_SHIFT) /* 0100: around 1 MHz */
+# define RCC_CR_MSIRANGE_2M (5 << RCC_CR_MSIRANGE_SHIFT) /* 0101: around 2 MHz */
+# define RCC_CR_MSIRANGE_4M (6 << RCC_CR_MSIRANGE_SHIFT) /* 0110: around 4 MHz */
+# define RCC_CR_MSIRANGE_8M (7 << RCC_CR_MSIRANGE_SHIFT) /* 0111: around 8 MHz */
+# define RCC_CR_MSIRANGE_16M (8 << RCC_CR_MSIRANGE_SHIFT) /* 1000: around 16 MHz */
+# define RCC_CR_MSIRANGE_24M (9 << RCC_CR_MSIRANGE_SHIFT) /* 1001: around 24 MHz */
+# define RCC_CR_MSIRANGE_32M (10 << RCC_CR_MSIRANGE_SHIFT) /* 1010: around 32 MHz */
+# define RCC_CR_MSIRANGE_48M (11 << RCC_CR_MSIRANGE_SHIFT) /* 1011: around 48 MHz */
+
+#define RCC_CR_HSION (1 << 8) /* Bit 8: HSI16 clock enable */
+#define RCC_CR_HSIKERON (1 << 9) /* Bit 9: HSI16 always enable for peripheral kernels */
+#define RCC_CR_HSIRDY (1 << 10) /* Bit 10: HSI16 clock ready flag */
+#define RCC_CR_HSIASFS (1 << 11) /* Bit 11: HSI16 automatic start from stop */
+#define RCC_CR_HSEON (1 << 16) /* Bit 16: HSE clock enable */
+#define RCC_CR_HSERDY (1 << 17) /* Bit 17: HSE clock ready flag */
+#define RCC_CR_CSSON (1 << 19) /* Bit 19: Clock Security System enable */
+#define RCC_CR_HSEPRE (1 << 20) /* Bit 20: HSE sysclk and PLL M divider prescaler */
+#define RCC_CR_PLLON (1 << 24) /* Bit 24: PLL enable */
+#define RCC_CR_PLLRDY (1 << 25) /* Bit 25: PLL clock ready flag */
+#define RCC_CR_PLLSAI1ON (1 << 26) /* Bit 26: PLLSAI1 enable */
+#define RCC_CR_PLLSAI1RDY (1 << 27) /* Bit 27: PLLSAI1 clock ready flag */
+
+/* Internal Clock Sources Calibration */
+
+#define RCC_CR_HSITRIM_SHIFT (24) /* Bits 30-24: HSI16 clock trimming */
+#define RCC_CR_HSITRIM_MASK (0x7f << RCC_CR_HSITRIM_SHIFT)
+#define RCC_CR_HSICAL_SHIFT (16) /* Bits 23-16: HSI16 clock Calibration */
+#define RCC_CR_HSICAL_MASK (0xff << RCC_CR_HSICAL_SHIFT)
+#define RCC_CR_MSITRIM_SHIFT (8) /* Bits 15-8: Internal Multi Speed clock trimming */
+#define RCC_CR_MSITRIM_MASK (0xff << RCC_CR_MSITRIM_SHIFT)
+#define RCC_CR_MSICAL_SHIFT (0) /* Bits 7-0: Internal Multi Speed clock Calibration */
+#define RCC_CR_MSICAL_MASK (0xff << RCC_CR_MSICAL_SHIFT)
+
+/* Clock configuration register */
+
+#define RCC_CFGR_SW_SHIFT (0) /* Bits 0-1: System clock Switch */
+#define RCC_CFGR_SW_MASK (0x3 << RCC_CFGR_SW_SHIFT)
+# define RCC_CFGR_SW_MSI (0x0 << RCC_CFGR_SW_SHIFT) /* 00: MSI selected as system clock */
+# define RCC_CFGR_SW_HSI16 (0x1 << RCC_CFGR_SW_SHIFT) /* 00: HSI16 selected as system clock */
+# define RCC_CFGR_SW_HSE (0x2 << RCC_CFGR_SW_SHIFT) /* 01: HSE selected as system clock */
+# define RCC_CFGR_SW_PLL (0x3 << RCC_CFGR_SW_SHIFT) /* 10: PLL selected as system clock */
+
+#define RCC_CFGR_SWS_SHIFT (2) /* Bits 2-3: System Clock Switch Status */
+#define RCC_CFGR_SWS_MASK (0x3 << RCC_CFGR_SWS_SHIFT)
+# define RCC_CFGR_SWS_MSI (0x0 << RCC_CFGR_SWS_SHIFT) /* 00: MSI oscillator used as system clock */
+# define RCC_CFGR_SWS_HSI16 (0x1 << RCC_CFGR_SWS_SHIFT) /* 00: HSI16 oscillator used as system clock */
+# define RCC_CFGR_SWS_HSE (0x2 << RCC_CFGR_SWS_SHIFT) /* 01: HSE oscillator used as system clock */
+# define RCC_CFGR_SWS_PLL (0x3 << RCC_CFGR_SWS_SHIFT) /* 10: PLL used as system clock */
+
+#define RCC_CFGR_HPRE_SHIFT (4) /* Bits 4-7: HCLK1 prescaler (AHB1, AHB2, AHB3 and SRAM1) */
+#define RCC_CFGR_HPRE_MASK (0x0f << RCC_CFGR_HPRE_SHIFT)
+# define RCC_CFGR_HPRE_SYSCLK (0x00 << RCC_CFGR_HPRE_SHIFT) /* 0000: SYSCLK not divided */
+# define RCC_CFGR_HPRE_SYSCLKd3 (0x01 << RCC_CFGR_HPRE_SHIFT) /* 0001: SYSCLK divided by 3 */
+# define RCC_CFGR_HPRE_SYSCLKd5 (0x02 << RCC_CFGR_HPRE_SHIFT) /* 0010: SYSCLK divided by 5 */
+# define RCC_CFGR_HPRE_SYSCLKd6 (0x05 << RCC_CFGR_HPRE_SHIFT) /* 0101: SYSCLK divided by 6 */
+# define RCC_CFGR_HPRE_SYSCLKd10 (0x06 << RCC_CFGR_HPRE_SHIFT) /* 0110: SYSCLK divided by 10 */
+# define RCC_CFGR_HPRE_SYSCLKd32 (0x07 << RCC_CFGR_HPRE_SHIFT) /* 0111: SYSCLK divided by 32 */
+# define RCC_CFGR_HPRE_SYSCLKd2 (0x08 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */
+# define RCC_CFGR_HPRE_SYSCLKd4 (0x09 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */
+# define RCC_CFGR_HPRE_SYSCLKd8 (0x10 << RCC_CFGR_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */
+# define RCC_CFGR_HPRE_SYSCLKd16 (0x11 << RCC_CFGR_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */
+# define RCC_CFGR_HPRE_SYSCLKd64 (0x12 << RCC_CFGR_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */
+# define RCC_CFGR_HPRE_SYSCLKd128 (0x13 << RCC_CFGR_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */
+# define RCC_CFGR_HPRE_SYSCLKd256 (0x14 << RCC_CFGR_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */
+# define RCC_CFGR_HPRE_SYSCLKd512 (0x15 << RCC_CFGR_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */
+
+#define RCC_CFGR_PPRE1_SHIFT (8) /* Bits 8-10: PCLK1 Low speed prescaler (APB1) */
+#define RCC_CFGR_PPRE1_MASK (0x7 << RCC_CFGR_PPRE1_SHIFT)
+# define RCC_CFGR_PPRE1_HCLK1 (0x0 << RCC_CFGR_PPRE1_SHIFT) /* 0xx: HCLK1 not divided */
+# define RCC_CFGR_PPRE1_HCLK1d2 (0x4 << RCC_CFGR_PPRE1_SHIFT) /* 100: HCLK1 divided by 2 */
+# define RCC_CFGR_PPRE1_HCLK1d4 (0x5 << RCC_CFGR_PPRE1_SHIFT) /* 101: HCLK1 divided by 4 */
+# define RCC_CFGR_PPRE1_HCLK1d8 (0x6 << RCC_CFGR_PPRE1_SHIFT) /* 110: HCLK1 divided by 8 */
+# define RCC_CFGR_PPRE1_HCLK1d16 (0x7 << RCC_CFGR_PPRE1_SHIFT) /* 111: HCLK1 divided by 16 */
+
+#define RCC_CFGR_PPRE2_SHIFT (11) /* Bits 11-13: PCLK2 High speed prescaler (APB2) */
+#define RCC_CFGR_PPRE2_MASK (0x7 << RCC_CFGR_PPRE2_SHIFT)
+# define RCC_CFGR_PPRE2_HCLK1 (0x0 << RCC_CFGR_PPRE2_SHIFT) /* 0xx: HCLK1 not divided */
+# define RCC_CFGR_PPRE2_HCLK1d2 (0x4 << RCC_CFGR_PPRE2_SHIFT) /* 100: HCLK1 divided by 2 */
+# define RCC_CFGR_PPRE2_HCLK1d4 (0x5 << RCC_CFGR_PPRE2_SHIFT) /* 101: HCLK1 divided by 4 */
+# define RCC_CFGR_PPRE2_HCLK1d8 (0x6 << RCC_CFGR_PPRE2_SHIFT) /* 110: HCLK1 divided by 8 */
+# define RCC_CFGR_PPRE2_HCLK1d16 (0x7 << RCC_CFGR_PPRE2_SHIFT) /* 111: HCLK1 divided by 16 */
+
+#define RCC_CFGR_STOPWUCK (1 << 15) /* Bit 15: Wakeup from Stop and CSS backup clock selection */
+# define RCC_CFGR_STOPWUCK_MSI (0 << 15) /* 0: MSI */
+# define RCC_CFGR_STOPWUCK_HSI16 (1 << 15) /* 0: HSI16 */
+
+#define RCC_CFGR_HPREF (1 << 16) /* Bit 16: HCLK1 prescaler flag (AHB1, AHB2, AHB3, SRAM1) */
+#define RCC_CFGR_PPRE1F (1 << 17) /* Bit 17: PCLK1 prescaler flag (APB1) */
+#define RCC_CFGR_PPRE2F (1 << 18) /* Bit 18: PCLK2 prescaler flag (APB2) */
+
+#define RCC_CFGR_MCOSEL_SHIFT (24) /* Bits 24-27: Microcontroller Clock Output */
+#define RCC_CFGR_MCOSEL_MASK (0xf << RCC_CFGR_MCOSEL_SHIFT)
+# define RCC_CFGR_MCOSEL_DISABLED (0x0 << RCC_CFGR_MCOSEL_SHIFT) /* 0000: Output disabled, no clock on MCO */
+# define RCC_CFGR_MCOSEL_SYSCLK (0x1 << RCC_CFGR_MCOSEL_SHIFT) /* 0001: SYSCLK system clock selected */
+# define RCC_CFGR_MCOSEL_MSI (0x2 << RCC_CFGR_MCOSEL_SHIFT) /* 0010: MSI clock selected */
+# define RCC_CFGR_MCOSEL_HSI16 (0x3 << RCC_CFGR_MCOSEL_SHIFT) /* 0011: HSI16 clock selected */
+# define RCC_CFGR_MCOSEL_HSE_AFT (0x4 << RCC_CFGR_MCOSEL_SHIFT) /* 0100: HSE clock after stabilization */
+# define RCC_CFGR_MCOSEL_PLL (0x5 << RCC_CFGR_MCOSEL_SHIFT) /* 0101: Main PLLRCLK selected */
+# define RCC_CFGR_MCOSEL_LSI1 (0x6 << RCC_CFGR_MCOSEL_SHIFT) /* 0110: LSI1 clock selected */
+# define RCC_CFGR_MCOSEL_LSI2 (0x7 << RCC_CFGR_MCOSEL_SHIFT) /* 0111: LSI2 clock selected */
+# define RCC_CFGR_MCOSEL_LSE (0x8 << RCC_CFGR_MCOSEL_SHIFT) /* 1000: LSE clock selected */
+# define RCC_CFGR_MCOSEL_HSI48 (0x9 << RCC_CFGR_MCOSEL_SHIFT) /* 1001: HSI48 clock selected */
+# define RCC_CFGR_MCOSEL_HSE_BFR (0xc << RCC_CFGR_MCOSEL_SHIFT) /* 1100: HSE clock before stabilization */
+
+#define RCC_CFGR_MCOPRE_SHIFT (28) /* Bits 28-30: MCO prescaler */
+#define RCC_CFGR_MCOPRE_MASK (0x7 << RCC_CFGR_MCOPRE_SHIFT)
+# define RCC_CFGR_MCOPRE_DIV1 (0x0 << RCC_CFGR_MCOPRE_SHIFT) /* 000: no division */
+# define RCC_CFGR_MCOPRE_DIV2 (0x1 << RCC_CFGR_MCOPRE_SHIFT) /* 001: division by 2 */
+# define RCC_CFGR_MCOPRE_DIV4 (0x2 << RCC_CFGR_MCOPRE_SHIFT) /* 010: division by 4 */
+# define RCC_CFGR_MCOPRE_DIV8 (0x3 << RCC_CFGR_MCOPRE_SHIFT) /* 011: division by 8 */
+# define RCC_CFGR_MCOPRE_DIV16 (0x4 << RCC_CFGR_MCOPRE_SHIFT) /* 100: division by 16 */
+
+#define RCC_CFGR_RESET_MASK (0x00070000)
+
+/* PLL configuration register */
+
+#define RCC_PLLCFG_PLLSRC_SHIFT (0) /* Bits 0-1: Main PLL and audio PLLSAI1 entry clock source */
+#define RCC_PLLCFG_PLLSRC_MASK (0x3 << RCC_PLLCFG_PLLSRC_SHIFT)
+# define RCC_PLLCFG_PLLSRC_NONE (0x0 << RCC_PLLCFG_PLLSRC_SHIFT) /* 00: No clock sent to PLLs */
+# define RCC_PLLCFG_PLLSRC_MSI (0x1 << RCC_PLLCFG_PLLSRC_SHIFT) /* 01: MSI selected as PLLs source */
+# define RCC_PLLCFG_PLLSRC_HSI16 (0x2 << RCC_PLLCFG_PLLSRC_SHIFT) /* 10: HSI16 selected as PLLs source */
+# define RCC_PLLCFG_PLLSRC_HSE (0x3 << RCC_PLLCFG_PLLSRC_SHIFT) /* 11: HSE selected as PLLs source */
+
+#define RCC_PLLCFG_PLLM_SHIFT (4) /* Bits 4-6: Main PLL and audio PLLSAI1 divider */
+#define RCC_PLLCFG_PLLM_MASK (0x07 << RCC_PLLCFG_PLLM_SHIFT)
+# define RCC_PLLCFG_PLLM(n) (((n) - 1) << RCC_PLLCFG_PLLM_SHIFT) /* n = 1..8 */
+
+#define RCC_PLLCFG_PLLN_SHIFT (8) /* Bits 8-14: Main PLL (PLL) VCO multiplier */
+#define RCC_PLLCFG_PLLN_MASK (0x7f << RCC_PLLCFG_PLLN_SHIFT)
+# define RCC_PLLCFG_PLLN(n) ((n) << RCC_PLLCFG_PLLN_SHIFT) /* n = 6..127 */
+
+#define RCC_PLLCFG_PLLPEN (1 << 16) /* Bit 16: Main PLL PLLPCLK output enable */
+
+#define RCC_PLLCFG_PLLP_SHIFT (17) /* Bits 17-21: Main PLL div factor for PLLPCLK */
+#define RCC_PLLCFG_PLLP_MASK (0x1f << RCC_PLLCFG_PLLP_SHIFT)
+# define RCC_PLLCFG_PLLP(n) (((n) - 1) << RCC_PLLCFG_PLLP_SHIFT) /* n = 2..32 */
+
+#define RCC_PLLCFG_PLLQEN (1 << 24) /* Bit 24: Main PLL PLLQCLK output enable */
+
+#define RCC_PLLCFG_PLLQ_SHIFT (25) /* Bits 25-27: Main PLL division factor for PLLQCLK */
+#define RCC_PLLCFG_PLLQ_MASK (0x7 << RCC_PLLCFG_PLLQ_SHIFT)
+# define RCC_PLLCFG_PLLQ(n) (((n) - 1) << RCC_PLLCFG_PLLQ_SHIFT) /* n = 2..8 */
+
+#define RCC_PLLCFG_PLLREN (1 << 28) /* Bit 28: Main PLL PLLRCLK output enable */
+
+#define RCC_PLLCFG_PLLR_SHIFT (29) /* Bits 29-31: Main PLL division factor for PLLRCLK */
+#define RCC_PLLCFG_PLLR_MASK (0x7 << RCC_PLLCFG_PLLR_SHIFT)
+# define RCC_PLLCFG_PLLR(n) (((n) - 1) << RCC_PLLCFG_PLLR_SHIFT) /* n = 2..8 */
+
+#define RCC_PLLCFG_RESET (0x22040100) /* PLLCFG reset value */
+
+/* PLLSAI1 Configuration register */
+
+#define RCC_PLLSAI1CFG_PLLN_SHIFT (8) /* Bits 8-14: SAI1 PLL (PLLSAI1) VCO multiplier */
+#define RCC_PLLSAI1CFG_PLLN_MASK (0x7f << RCC_PLLSAI1CFG_PLLN_SHIFT)
+# define RCC_PLLSAI1CFG_PLLN(n) ((n) << RCC_PLLSAI1CFG_PLLN_SHIFT) /* n = 4..86 */
+
+#define RCC_PLLSAI1CFG_PLLPEN (1 << 16) /* Bit 16: SAI1 PLL PLLSAI1CLK output enable */
+
+#define RCC_PLLSAI1CFG_PLLP_SHIFT (17) /* Bit 17-21: Main PLL div factor for PLLSAI1CLK */
+#define RCC_PLLSAI1CFG_PLLP_MASK (0x1f << RCC_PLLSAI1CFG_PLLP_SHIFT)
+# define RCC_PLLSAI1CFG_PLLP(n) (((n) - 1) << RCC_PLLSAI1CFG_PLLP_SHIFT) /* n = 2..32 */
+
+#define RCC_PLLSAI1CFG_PLLQEN (1 << 24) /* Bit 24: PLLSAI1QCLK output enable */
+
+#define RCC_PLLSAI1CFG_PLLQ_SHIFT (25) /* Bits 25-27: PLLSAI1 division factor for PLLSAI1QCLK */
+#define RCC_PLLSAI1CFG_PLLQ_MASK (0x3 << RCC_PLLSAI1CFG_PLLQ_SHIFT)
+# define RCC_PLLSAI1CFG_PLLQ(n) (((n) - 1) << RCC_PLLSAI1CFG_PLLQ_SHIFT) /* n = 2..8 */
+
+#define RCC_PLLSAI1CFG_PLLREN (1 << 28) /* Bit 28: SAI1 PLL PLLSAI1RCLK output enable */
+
+#define RCC_PLLSAI1CFG_PLLR_SHIFT (29) /* Bits 29-31: PLLSAI1 division factor for PLLSAI1RCLK */
+#define RCC_PLLSAI1CFG_PLLR_MASK (0x3 << RCC_PLLSAI1CFG_PLLR_SHIFT)
+# define RCC_PLLSAI1CFG_PLLR(n) (((n) - 1) << RCC_PLLSAI1CFG_PLLR_SHIFT) /* n = 2..8 */
+
+#define RCC_PLLSAI1CFG_RESET (0x22040100) /* PLLSAI1CFG reset value */
+
+/* Clock interrupt enable register */
+
+#define RCC_CIER_LSI1RDYIE (1 << 0) /* Bit 0: LSI1 Ready Interrupt Enable */
+#define RCC_CIER_LSERDYIE (1 << 1) /* Bit 1: LSE Ready Interrupt Enable */
+#define RCC_CIER_MSIRDYIE (1 << 2) /* Bit 2: MSI Ready Interrupt Enable */
+#define RCC_CIER_HSI16RDYIE (1 << 3) /* Bit 3: HSI16 Ready Interrupt Enable */
+#define RCC_CIER_HSERDYIE (1 << 4) /* Bit 4: HSE Ready Interrupt Enable */
+#define RCC_CIER_PLLRDYIE (1 << 5) /* Bit 5: PLL Ready Interrupt Enable */
+#define RCC_CIER_PLLSAI1RDYIE (1 << 6) /* Bit 6: PLLSAI1 Ready Interrupt enable */
+#define RCC_CIER_LSECSSIE (1 << 9) /* Bit 9: LSE Clock Security System Interrupt Enable */
+#define RCC_CIER_HSI48RDYIE (1 << 10) /* Bit 10: HSI48 Ready Interrupt Enable */
+#define RCC_CIER_LSI2RDYIE (1 << 11) /* Bit 11: LSI2 Ready Interrupt Enable */
+
+/* Clock interrupt flag register */
+
+#define RCC_CIFR_LSI1RDYIF (1 << 0) /* Bit 0: LSI1 Ready Interrupt Flag */
+#define RCC_CIFR_LSERDYIF (1 << 1) /* Bit 1: LSE Ready Interrupt Flag */
+#define RCC_CIFR_MSIRDYIF (1 << 2) /* Bit 2: MSI Ready Interrupt Flag */
+#define RCC_CIFR_HSI16RDYIF (1 << 3) /* Bit 3: HSI16 Ready Interrupt Flag */
+#define RCC_CIFR_HSERDYIF (1 << 4) /* Bit 4: HSE Ready Interrupt Flag */
+#define RCC_CIFR_PLLRDYIF (1 << 5) /* Bit 5: PLL Ready Interrupt Flag */
+#define RCC_CIFR_PLLSAI1RDYIF (1 << 6) /* Bit 6: PLLSAI1 Ready Interrupt Flag */
+#define RCC_CIFR_CSSF (1 << 8) /* Bit 8: Clock Security System Interrupt Flag */
+#define RCC_CIFR_LSECSSIF (1 << 9) /* Bit 9: LSE Clock Security System Interrupt Flag */
+#define RCC_CIFR_HSI48RDYIF (1 << 10) /* Bit 10: HSI48 Ready Interrupt Flag */
+#define RCC_CIFR_LSI2RDYIF (1 << 11) /* Bit 11: LSI2 Ready Interrupt Flag */
+
+/* Clock interrupt clear register */
+
+#define RCC_CICR_LSI1RDYIC (1 << 0) /* Bit 0: LSI1 Ready Interrupt Clear */
+#define RCC_CICR_LSERDYIC (1 << 1) /* Bit 1: LSE Ready Interrupt Clear */
+#define RCC_CICR_MSIRDYIC (1 << 2) /* Bit 2: MSI Ready Interrupt Clear */
+#define RCC_CICR_HSI16RDYIC (1 << 3) /* Bit 3: HSI16 Ready Interrupt Clear */
+#define RCC_CICR_HSERDYIC (1 << 4) /* Bit 4: HSE Ready Interrupt Clear */
+#define RCC_CICR_PLLRDYIC (1 << 5) /* Bit 5: PLL Ready Interrupt Clear */
+#define RCC_CICR_PLLSAI1RDYIC (1 << 6) /* Bit 6: PLLSAI1 Ready Interrupt Clear */
+#define RCC_CICR_CSSC (1 << 8) /* Bit 8: Clock Security System Interrupt Clear */
+#define RCC_CICR_LSECSSIC (1 << 9) /* Bit 9: LSE Clock Security System Interrupt Clear */
+#define RCC_CICR_HSI48RDYIC (1 << 10) /* Bit 10: HSI48 Oscillator Ready Interrupt Clear */
+#define RCC_CICR_LSI2RDYIC (1 << 11) /* Bit 11: LSI2 Ready Interrupt Clear */
+
+/* SMPS step-down converter control register */
+
+#define RCC_SMPS_SMPSSEL_SHIFT (0) /* Bits 0-1: SMPS Clock Selection */
+#define RCC_SMPS_SMPSSEL_MASK (0x3 << RCC_SMPS_SMPSSEL_SHIFT)
+# define RCC_SMPS_SMPSSEL_HSI16 (0x0 << RCC_SMPS_SMPSSEL_SHIFT) /* 00: HSI16 selected as SMPS clock */
+# define RCC_SMPS_SMPSSEL_MSI (0x1 << RCC_SMPS_SMPSSEL_SHIFT) /* 01: MSI selected as SMPS clock */
+# define RCC_SMPS_SMPSSEL_HSE (0x2 << RCC_SMPS_SMPSSEL_SHIFT) /* 10: HSE selected as SMPS clock */
+# define RCC_SMPS_SMPSSEL_NONE (0x3 << RCC_SMPS_SMPSSEL_SHIFT) /* 11: no clock is used */
+
+#define RCC_SMPS_SMPSDIV_SHIFT (4) /* Bits 4-5: SMPS Clock Division factor */
+#define RCC_SMPS_SMPSDIV_MASK (0x3 << RCC_SMPS_SMPSDIV_SHIFT)
+# define RCC_SMPS_SMPSDIVd1 (0x0 << RCC_SMPS_SMPSDIV_SHIFT) /* 00: Selected clock not divided */
+# define RCC_SMPS_SMPSDIVd2 (0x1 << RCC_SMPS_SMPSDIV_SHIFT) /* 01: Selected clock divided by 2 */
+
+#define RCC_SMPS_SMPSSWS_SHIFT (8) /* Bits 8-9: SMPS Clock Switch Status */
+#define RCC_SMPS_SMPSSWS_MASK (0x3 << RCC_SMPS_SMPSSWS_SHIFT)
+# define RCC_SMPS_SMPSSWS_HSI16 (0x0 << RCC_SMPS_SMPSSWS_SHIFT) /* 00: HSI16 oscillator used as SMPS clock */
+# define RCC_SMPS_SMPSSWS_MSI (0x1 << RCC_SMPS_SMPSSWS_SHIFT) /* 01: MSI oscillator used as SMPS clock */
+# define RCC_SMPS_SMPSSWS_HSE (0x2 << RCC_SMPS_SMPSSWS_SHIFT) /* 10: HSE oscillator used as SMPS clock */
+# define RCC_SMPS_SMPSSWS_NONE (0x3 << RCC_SMPS_SMPSSWS_SHIFT) /* 11: no clock is used */
+
+/* AHB1 peripheral reset register */
+
+#define RCC_AHB1RSTR_DMA1RST (1 << 0) /* Bit 0: DMA1 reset */
+#define RCC_AHB1RSTR_DMA2RST (1 << 1) /* Bit 1: DMA2 reset */
+#define RCC_AHB1RSTR_DMAMUX1RST (1 << 2) /* Bit 2: DMAMUX1 reset */
+#define RCC_AHB1RSTR_FLASHRST (1 << 8) /* Bit 8: Flash memory interface reset */
+#define RCC_AHB1RSTR_CRCRST (1 << 12) /* Bit 12: CRC reset */
+#define RCC_AHB1RSTR_TSCRST (1 << 16) /* Bit 16: Touch Sensing Controller reset */
+
+/* AHB2 peripheral reset register */
+
+#define RCC_AHB2RSTR_GPIORST(n) (1 << (n))
+#define RCC_AHB2RSTR_GPIOARST (1 << 0) /* Bit 0: IO port A reset */
+#define RCC_AHB2RSTR_GPIOBRST (1 << 1) /* Bit 1: IO port B reset */
+#define RCC_AHB2RSTR_GPIOCRST (1 << 2) /* Bit 2: IO port C reset */
+#define RCC_AHB2RSTR_GPIODRST (1 << 3) /* Bit 3: IO port D reset */
+#define RCC_AHB2RSTR_GPIOERST (1 << 4) /* Bit 4: IO port E reset */
+#define RCC_AHB2RSTR_GPIOHRST (1 << 7) /* Bit 7: IO port H reset */
+#define RCC_AHB2RSTR_ADCRST (1 << 13) /* Bit 13: ADC reset */
+#define RCC_AHB2RSTR_AESRST (1 << 16) /* Bit 16: AES reset */
+
+/* AHB3 and AHB4 peripheral reset register */
+
+#define RCC_AHB3RSTR_QSPIRST (1 << 8) /* Bit 8: QSPI reset */
+#define RCC_AHB3RSTR_PKARST (1 << 16) /* Bit 16: PKA reset */
+#define RCC_AHB3RSTR_AES2IRST (1 << 17) /* Bit 17: AES2 reset */
+#define RCC_AHB3RSTR_RNGRST (1 << 18) /* Bit 18: RNG reset */
+#define RCC_AHB3RSTR_HSEMRST (1 << 19) /* Bit 19: HSEM reset */
+#define RCC_AHB3RSTR_IPCCRST (1 << 20) /* Bit 20: IPCC reset */
+#define RCC_AHB3RSTR_FLASHRST (1 << 25) /* Bit 25: FLASH reset */
+
+/* APB1 Peripheral reset register 1 */
+
+#define RCC_APB1RSTR1_TIM2RST (1 << 0) /* Bit 0: TIM2 reset */
+#define RCC_APB1RSTR1_LCDRST (1 << 9) /* Bit 9: LCD reset */
+#define RCC_APB1RSTR1_SPI2RST (1 << 14) /* Bit 14: SPI2 reset */
+#define RCC_APB1RSTR1_I2C1RST (1 << 21) /* Bit 21: I2C1 reset */
+#define RCC_APB1RSTR1_I2C3RST (1 << 23) /* Bit 23: I2C3 reset */
+#define RCC_APB1RSTR1_CRSRST (1 << 24) /* Bit 24: CRS reset */
+#define RCC_APB1RSTR1_USBRST (1 << 26) /* Bit 26: USB reset */
+#define RCC_APB1RSTR1_LPTIM1RST (1 << 31) /* Bit 31: LPTIM1 reset */
+
+/* APB1 Peripheral reset register 2 */
+
+#define RCC_APB1RSTR2_LPUART1RST (1 << 0) /* Bit 0: LPUART1 reset */
+#define RCC_APB1RSTR2_LPTIM2RST (1 << 5) /* Bit 5: LPTIM2 reset */
+
+/* APB2 Peripheral reset register */
+
+#define RCC_APB2RSTR_TIM1RST (1 << 11) /* Bit 11: TIM1 reset */
+#define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI1 reset */
+#define RCC_APB2RSTR_USART1RST (1 << 14) /* Bit 14: USART1 reset */
+#define RCC_APB2RSTR_TIM16RST (1 << 17) /* Bit 17: TIM16 reset */
+#define RCC_APB2RSTR_TIM17RST (1 << 18) /* Bit 18: TIM17 reset */
+#define RCC_APB2RSTR_SAI1RST (1 << 21) /* Bit 21: SAI1 reset */
+
+/* APB3 Peripheral reset register */
+
+#define RCC_APB3RSTR_RFRST (1 << 0) /* Bit 0: Radio system BLE and 802.15.4 reset */
+
+/* AHB1 Peripheral Clock enable register */
+
+#define RCC_AHB1ENR_DMA1EN (1 << 0) /* Bit 0: DMA1 Enable */
+#define RCC_AHB1ENR_DMA2EN (1 << 1) /* Bit 1: DMA2 Enable */
+#define RCC_AHB1ENR_DMAMUX1EN (1 << 2) /* Bit 2: DMAMUX1 Enable */
+#define RCC_AHB1ENR_CRCEN (1 << 12) /* Bit 12: CRC Enable */
+#define RCC_AHB1ENR_TSCEN (1 << 16) /* Bit 16: Touch Sensing Controller Enable */
+
+/* AHB2 Peripheral Clock enable register */
+
+#define RCC_AHB2ENR_GPIOEN(n) (1 << (n))
+#define RCC_AHB2ENR_GPIOAEN (1 << 0) /* Bit 0: IO port A Enable */
+#define RCC_AHB2ENR_GPIOBEN (1 << 1) /* Bit 1: IO port B Enable */
+#define RCC_AHB2ENR_GPIOCEN (1 << 2) /* Bit 2: IO port C Enable */
+#define RCC_AHB2ENR_GPIODEN (1 << 3) /* Bit 3: IO port D Enable */
+#define RCC_AHB2ENR_GPIOEEN (1 << 4) /* Bit 4: IO port E Enable */
+#define RCC_AHB2ENR_GPIOHEN (1 << 7) /* Bit 7: IO port H Enable */
+#define RCC_AHB2ENR_ADCEN (1 << 13) /* Bit 13: ADC interface Enable */
+#define RCC_AHB2ENR_AES1EN (1 << 16) /* Bit 16: AES1 Enable */
+
+/* AHB3 and AHB4 Peripheral Clock enable register */
+
+#define RCC_AHB3ENR_QSPIEN (1 << 8) /* Bit 8: QSPI Enable */
+#define RCC_AHB3ENR_PKAEN (1 << 16) /* Bit 16: PKA Enable */
+#define RCC_AHB3ENR_AES2EN (1 << 17) /* Bit 17: AES2 Enable */
+#define RCC_AHB3ENR_RNGEN (1 << 18) /* Bit 18: RNG Enable */
+#define RCC_AHB3ENR_HSEMEN (1 << 19) /* Bit 19: HSEM Enable */
+#define RCC_AHB3ENR_IPCCEN (1 << 20) /* Bit 20: IPCC Enable */
+#define RCC_AHB3ENR_FLASHEN (1 << 25) /* Bit 25: FLASH Enable */
+
+/* APB1 Peripheral Clock enable register 1 */
+
+#define RCC_APB1ENR1_TIM2EN (1 << 0) /* Bit 0: TIM2 enable */
+#define RCC_APB1ENR1_LCDEN (1 << 9) /* Bit 9: LCD enable */
+#define RCC_APB1ENR1_RTCAPBEN (1 << 10) /* Bit 10: RTC APB clock enable */
+#define RCC_APB1ENR1_WWDGEN (1 << 11) /* Bit 11: Windowed Watchdog enable */
+#define RCC_APB1ENR1_SPI2EN (1 << 14) /* Bit 14: SPI2 enable */
+#define RCC_APB1ENR1_I2C1EN (1 << 21) /* Bit 21: I2C1 enable */
+#define RCC_APB1ENR1_I2C3EN (1 << 23) /* Bit 23: I2C3 enable */
+#define RCC_APB1ENR1_CRSEN (1 << 24) /* Bit 24: CRSEN enable */
+#define RCC_APB1ENR1_USBEN (1 << 26) /* Bit 26: USB enable */
+#define RCC_APB1ENR1_LPTIM1EN (1 << 31) /* Bit 31: LPTIM1 enable */
+
+/* APB1 Peripheral Clock enable register 2 */
+
+#define RCC_APB1ENR2_LPUART1EN (1 << 0) /* Bit 0: LPUART1 enable */
+#define RCC_APB1ENR2_LPTIM2EN (1 << 5) /* Bit 5: LPTIM2 enable */
+
+/* APB2 Peripheral Clock enable register */
+
+#define RCC_APB2ENR_TIM1EN (1 << 11) /* Bit 11: TIM1 enable */
+#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: SPI1 enable */
+#define RCC_APB2ENR_USART1EN (1 << 14) /* Bit 14: USART1 enable */
+#define RCC_APB2ENR_TIM16EN (1 << 17) /* Bit 17: TIM16 enable */
+#define RCC_APB2ENR_TIM17EN (1 << 18) /* Bit 18: TIM17 enable */
+#define RCC_APB2ENR_SAI1EN (1 << 21) /* Bit 21: SAI1 enable */
+
+/* AHB1 peripheral clock enable in sleep and stop modes register */
+
+#define RCC_AHB1SMENR_DMA1LPSMEN (1 << 0) /* Bit 0: DMA1 enable in sleep and stop modes */
+#define RCC_AHB1SMENR_DMA2LPSMEN (1 << 1) /* Bit 1: DMA2 enable in sleep and stop modes */
+#define RCC_AHB1SMENR_DMAMUX1SMEN (1 << 2) /* Bit 2: DMAMUX1 clock enable in sleep and stop modes */
+#define RCC_AHB1SMENR_SRAM1SMEN (1 << 9) /* Bit 9: SRAM1 enable in sleep and stop modes */
+#define RCC_AHB1SMENR_CRCSMEN (1 << 12) /* Bit 12: CRC enable in sleep and stop modes */
+#define RCC_AHB1SMENR_TSCSMEN (1 << 16) /* Bit 16: TSC enable in sleep and stop modes */
+
+/* AHB2 peripheral clock enable in sleep and stop modes register */
+
+#define RCC_AHB2SMENR_GPIOASMEN (1 << 0) /* Bit 0: IO port A enable in sleep and stop modes */
+#define RCC_AHB2SMENR_GPIOBSMEN (1 << 1) /* Bit 1: IO port B enable in sleep and stop modes */
+#define RCC_AHB2SMENR_GPIOCSMEN (1 << 2) /* Bit 2: IO port C enable in sleep and stop modes */
+#define RCC_AHB2SMENR_GPIODSMEN (1 << 3) /* Bit 3: IO port D enable in sleep and stop modes */
+#define RCC_AHB2SMENR_GPIOESMEN (1 << 4) /* Bit 4: IO port E enable in sleep and stop modes */
+#define RCC_AHB2SMENR_GPIOHSMEN (1 << 7) /* Bit 7: IO port H enable in sleep and stop modes */
+#define RCC_AHB2SMENR_ADCSMEN (1 << 13) /* Bit 13: ADC enable in sleep and stop modes */
+#define RCC_AHB2SMENR_AES1SMEN (1 << 16) /* Bit 16: AES1 enable in sleep and stop modes */
+
+/* AHB3 and AHB4 peripheral clock enable in sleep and stop modes register */
+
+#define RCC_AHB3SMENR_QSPISMEN (1 << 8) /* Bit 8: QSPI enable in sleep and stop modes */
+#define RCC_AHB3SMENR_PKASMEN (1 << 16) /* Bit 16: PKA enable in sleep and stop modes */
+#define RCC_AHB3SMENR_AES2SMEN (1 << 17) /* Bit 17: AES2 enable in sleep and stop modes */
+#define RCC_AHB3SMENR_RNGSMEN (1 << 18) /* Bit 18: RNG enable in sleep and stop modes */
+#define RCC_AHB3SMENR_SRAM2SMEN (1 << 24) /* Bit 24: SRAM2x enable in sleep and stop modes */
+#define RCC_AHB3SMENR_FLASHSMEN (1 << 25) /* Bit 25: FLASH memory enable in sleep and stop modes */
+
+/* APB1 peripheral clock enable in sleep and stop modes register 1 */
+
+#define RCC_APB1SMENR1_TIM2SMEN (1 << 0) /* Bit 0: TIM2 enable in sleep and stop modes */
+#define RCC_APB1SMENR1_LCDSMEN (9 << 0) /* Bit 9: LCD enable in sleep and stop modes */
+#define RCC_APB1SMENR1_RTCAPBSMEN (1 << 10) /* Bit 10: RTC APB clock enable in sleep and stop modes */
+#define RCC_APB1SMENR1_WWDGSMEN (1 << 11) /* Bit 11: Windowed Watchdog enable in sleep and stop modes */
+#define RCC_APB1SMENR1_SPI2SMEN (1 << 14) /* Bit 14: SPI2 enable in sleep and stop modes */
+#define RCC_APB1SMENR1_I2C1SMEN (1 << 21) /* Bit 21: I2C1 enable in sleep and stop modes */
+#define RCC_APB1SMENR1_I2C3SMEN (1 << 23) /* Bit 23: I2C3 enable in sleep and stop modes */
+#define RCC_APB1SMENR1_CRSSMEN (1 << 24) /* Bit 24: CRS enable in sleep and stop modes */
+#define RCC_APB1SMENR1_USBSMEN (1 << 26) /* Bit 26: USB enable in sleep and stop modes */
+#define RCC_APB1SMENR1_LPTIM1SMEN (1 << 31) /* Bit 31: LPTIM1 enable in sleep and stop modes */
+
+/* APB1 peripheral clock enable in sleep and stop modes register 2 */
+
+#define RCC_APB1SMENR2_LPUART1SMEN (1 << 0) /* Bit 0: LPUART1 enable in sleep and stop modes */
+#define RCC_APB1SMENR2_LPTIM2SMEN (1 << 5) /* Bit 5: LPTIM2 enable in sleep and stop modes */
+
+/* APB2 peripheral clock enable in sleep and stop modes register */
+
+#define RCC_APB2SMENR_TIM1SMEN (1 << 11) /* Bit 11: TIM1 enable in sleep and stop modes */
+#define RCC_APB2SMENR_SPI1SMEN (1 << 12) /* Bit 12: SPI1 enable in sleep and stop modes */
+#define RCC_APB2SMENR_USART1SMEN (1 << 14) /* Bit 14: USART1 enable in sleep and stop modes */
+#define RCC_APB2SMENR_TIM16SMEN (1 << 17) /* Bit 17: TIM16 enable in sleep and stop modes */
+#define RCC_APB2SMENR_TIM17SMEN (1 << 18) /* Bit 18: TIM17 enable in sleep and stop modes */
+#define RCC_APB2SMENR_SAI1SMEN (1 << 21) /* Bit 21: SAI1 enable in sleep and stop modes */
+
+/* Peripheral Independent Clock Configuration register */
+
+#define RCC_CCIPR_USART1SEL_SHIFT (0) /* Bits 0-1: USART1 clock source selection */
+#define RCC_CCIPR_USART1SEL_MASK (0x3 << RCC_CCIPR_USART1SEL_SHIFT)
+# define RCC_CCIPR_USART1SEL_PCLK (0x0 << RCC_CCIPR_USART1SEL_SHIFT) /* 00: PCLK selected */
+# define RCC_CCIPR_USART1SEL_SYSCLK (0x1 << RCC_CCIPR_USART1SEL_SHIFT) /* 01: System clock selected */
+# define RCC_CCIPR_USART1SEL_HSI16 (0x2 << RCC_CCIPR_USART1SEL_SHIFT) /* 10: HSI16 clock selected */
+# define RCC_CCIPR_USART1SEL_LSE (0x3 << RCC_CCIPR_USART1SEL_SHIFT) /* 11: LSE clock selected */
+
+#define RCC_CCIPR_LPUART1SEL_SHIFT (10) /* Bits 10-11: LPUART1 clock source selection */
+#define RCC_CCIPR_LPUART1SEL_MASK (0x3 << RCC_CCIPR_LPUART1SEL_SHIFT)
+# define RCC_CCIPR_LPUART1SEL_PCLK (0x0 << RCC_CCIPR_LPUART1SEL_SHIFT) /* 00: PCLK selected */
+# define RCC_CCIPR_LPUART1SEL_SYSCLK (0x1 << RCC_CCIPR_LPUART1SEL_SHIFT) /* 01: System clock selected */
+# define RCC_CCIPR_LPUART1SEL_HSI16 (0x2 << RCC_CCIPR_LPUART1SEL_SHIFT) /* 10: HSI16 clock selected */
+# define RCC_CCIPR_LPUART1SEL_LSE (0x3 << RCC_CCIPR_LPUART1SEL_SHIFT) /* 11: LSE clock selected */
+
+#define RCC_CCIPR_I2C1SEL_SHIFT (12) /* Bits 12-13: I2C1 clock source selection */
+#define RCC_CCIPR_I2C1SEL_MASK (0x3 << RCC_CCIPR_I2C1SEL_SHIFT)
+# define RCC_CCIPR_I2C1SEL_PCLK (0x0 << RCC_CCIPR_I2C1SEL_SHIFT) /* 00: PCLK selected */
+# define RCC_CCIPR_I2C1SEL_SYSCLK (0x1 << RCC_CCIPR_I2C1SEL_SHIFT) /* 01: System clock selected */
+# define RCC_CCIPR_I2C1SEL_HSI16 (0x2 << RCC_CCIPR_I2C1SEL_SHIFT) /* 10: HSI16 clock selected */
+
+#define RCC_CCIPR_I2C3SEL_SHIFT (16) /* Bits 16-17: I2C3 clock source selection */
+#define RCC_CCIPR_I2C3SEL_MASK (0x3 << RCC_CCIPR_I2C3SEL_SHIFT)
+# define RCC_CCIPR_I2C3SEL_PCLK (0x0 << RCC_CCIPR_I2C3SEL_SHIFT) /* 00: PCLK selected */
+# define RCC_CCIPR_I2C3SEL_SYSCLK (0x1 << RCC_CCIPR_I2C3SEL_SHIFT) /* 01: System clock selected */
+# define RCC_CCIPR_I2C3SEL_HSI16 (0x2 << RCC_CCIPR_I2C3SEL_SHIFT) /* 10: HSI16 clock selected */
+
+#define RCC_CCIPR_LPTIM1SEL_SHIFT (18) /* Bits 18-19: LPTIM1 clock source selection */
+#define RCC_CCIPR_LPTIM1SEL_MASK (0x3 << RCC_CCIPR_LPTIM1SEL_SHIFT)
+# define RCC_CCIPR_LPTIM1SEL_PCLK (0x0 << RCC_CCIPR_LPTIM1SEL_SHIFT) /* 00: PCLK selected */
+# define RCC_CCIPR_LPTIM1SEL_LSI (0x1 << RCC_CCIPR_LPTIM1SEL_SHIFT) /* 01: LSI clock selected */
+# define RCC_CCIPR_LPTIM1SEL_HSI16 (0x2 << RCC_CCIPR_LPTIM1SEL_SHIFT) /* 10: HSI16 clock selected */
+# define RCC_CCIPR_LPTIM1SEL_LSE (0x3 << RCC_CCIPR_LPTIM1SEL_SHIFT) /* 11: LSE clock selected */
+
+#define RCC_CCIPR_LPTIM2SEL_SHIFT (20) /* Bits 20-21: LPTIM2 clock source selection */
+#define RCC_CCIPR_LPTIM2SEL_MASK (0x3 << RCC_CCIPR_LPTIM2SEL_SHIFT)
+# define RCC_CCIPR_LPTIM2SEL_PCLK (0x0 << RCC_CCIPR_LPTIM2SEL_SHIFT) /* 00: PCLK selected */
+# define RCC_CCIPR_LPTIM2SEL_LSI (0x1 << RCC_CCIPR_LPTIM2SEL_SHIFT) /* 01: LSI clock selected */
+# define RCC_CCIPR_LPTIM2SEL_HSI16 (0x2 << RCC_CCIPR_LPTIM2SEL_SHIFT) /* 10: HSI16 clock selected */
+# define RCC_CCIPR_LPTIM2SEL_LSE (0x3 << RCC_CCIPR_LPTIM2SEL_SHIFT) /* 11: LSE clock selected */
+
+#define RCC_CCIPR_SAI1SEL_SHIFT (22) /* Bits 22-23: SAI1 clock source selection */
+#define RCC_CCIPR_SAI1SEL_MASK (0x3 << RCC_CCIPR_SAI1SEL_SHIFT)
+# define RCC_CCIPR_SAI1SEL_PLLSAI1 (0x0 << RCC_CCIPR_SAI1SEL_SHIFT) /* 00: PLLSAI1 P clock selected */
+# define RCC_CCIPR_SAI1SEL_PLLP (0x1 << RCC_CCIPR_SAI1SEL_SHIFT) /* 01: PLL P clock selected */
+# define RCC_CCIPR_SAI1SEL_HSI16 (0x2 << RCC_CCIPR_SAI1SEL_SHIFT) /* 10: HSI16 clock selected */
+# define RCC_CCIPR_SAI1SEL_EXTCLK (0x3 << RCC_CCIPR_SAI1SEL_SHIFT) /* 11: External input SAI1_EXTCLK */
+
+#define RCC_CCIPR_CLK48SEL_SHIFT (26) /* Bits 26-27: 48 MHz clock source selection */
+#define RCC_CCIPR_CLK48SEL_MASK (0x3 << RCC_CCIPR_CLK48SEL_SHIFT)
+# define RCC_CCIPR_CLK48SEL_HSI48 (0x0 << RCC_CCIPR_CLK48SEL_SHIFT) /* 00: HSI48 clock selected */
+# define RCC_CCIPR_CLK48SEL_PLLSAI1 (0x1 << RCC_CCIPR_CLK48SEL_SHIFT) /* 01: PLLSAI1 Q clock selected */
+# define RCC_CCIPR_CLK48SEL_PLLMAIN (0x2 << RCC_CCIPR_CLK48SEL_SHIFT) /* 10: PLL Q clock selected */
+# define RCC_CCIPR_CLK48SEL_MSI (0x3 << RCC_CCIPR_CLK48SEL_SHIFT) /* 11: MSI clock selected */
+
+#define RCC_CCIPR_ADCSEL_SHIFT (28) /* Bits 28-29: ADC clock source selection */
+#define RCC_CCIPR_ADCSEL_MASK (0x3 << RCC_CCIPR_ADCSEL_SHIFT)
+# define RCC_CCIPR_ADCSEL_NONE (0x0 << RCC_CCIPR_ADCSEL_SHIFT) /* 00: No clock */
+# define RCC_CCIPR_ADCSEL_PLLSAI1 (0x1 << RCC_CCIPR_ADCSEL_SHIFT) /* 01: PLLSAI1 R clock selected */
+# define RCC_CCIPR_ADCSEL_PLLMAIN (0x2 << RCC_CCIPR_ADCSEL_SHIFT) /* 10: PLL P clock selected */
+# define RCC_CCIPR_ADCSEL_SYSCLK (0x3 << RCC_CCIPR_ADCSEL_SHIFT) /* 11: System clock selected */
+
+#define RCC_CCIPR_RNGSEL_SHIFT (30) /* Bits 30-31: RNG clock source selection */
+#define RCC_CCIPR_RNGSEL_MASK (0x3 << RCC_CCIPR_RNGSEL_SHIFT)
+# define RCC_CCIPR_RNGSEL_CLK48SEL (0x0 << RCC_CCIPR_RNGSEL_SHIFT) /* 00: Clock source selected by CLK48SEL */
+# define RCC_CCIPR_RNGSEL_LSI (0x1 << RCC_CCIPR_RNGSEL_SHIFT) /* 01: LSI clock selected */
+# define RCC_CCIPR_RNGSEL_LSE (0x2 << RCC_CCIPR_RNGSEL_SHIFT) /* 10: LSE clock selected */
+
+/* Backup domain control register */
+
+#define RCC_BDCR_LSEON (1 << 0) /* Bit 0: External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY (1 << 1) /* Bit 1: External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP (1 << 2) /* Bit 2: External Low Speed oscillator Bypass */
+
+#define RCC_BDCR_LSEDRV_SHIFT (3) /* Bits 3-4: LSE oscillator drive capability */
+#define RCC_BDCR_LSEDRV_MASK (0x3 << RCC_BDCR_LSEDRV_SHIFT)
+# define RCC_BDCR_LSEDRV_LOW (0x0 << RCC_BDCR_LSEDRV_SHIFT) /* 00: Lower driving capability */
+# define RCC_BDCR_LSEDRV_MEDLO (0x1 << RCC_BDCR_LSEDRV_SHIFT) /* 01: Medium Low driving capability */
+# define RCC_BDCR_LSEDRV_MEDHI (0x2 << RCC_BDCR_LSEDRV_SHIFT) /* 10: Medium High driving capability*/
+# define RCC_BDCR_LSEDRV_HIGH (0x3 << RCC_BDCR_LSEDRV_SHIFT) /* 11: Higher driving capability */
+
+#define RCC_BDCR_LSECSSON (1 << 5) /* Bit 5: CSS on LSE enable */
+#define RCC_BDCR_LSECSSD (1 << 6) /* Bit 6: CSS on LSE failure Detection */
+
+#define RCC_BDCR_RTCSEL_SHIFT (8) /* Bits 8-9: RTC clock source selection */
+#define RCC_BDCR_RTCSEL_MASK (0x3 << RCC_BDCR_RTCSEL_SHIFT)
+# define RCC_BDCR_RTCSEL_NOCLK (0x0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */
+# define RCC_BDCR_RTCSEL_LSE (0x1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */
+# define RCC_BDCR_RTCSEL_LSI (0x2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */
+# define RCC_BDCR_RTCSEL_HSE (0x3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 32 used as RTC clock */
+
+#define RCC_BDCR_RTCEN (1 << 15) /* Bit 15: RTC clock enable */
+#define RCC_BDCR_BDRST (1 << 16) /* Bit 16: Backup domain software reset */
+#define RCC_BDCR_LSCOEN (1 << 24) /* Bit 24: Low speed clock output enable */
+#define RCC_BDCR_LSCOSEL (1 << 25) /* Bit 25: Low speed clock output selection */
+# define RCC_BCDR_LSCOSEL_LSI (0 << 25) /* 0: LSI selected */
+# define RCC_BDCR_LSCOSEL_LSE (1 << 25) /* 1: LSE selected */
+
+/* Control/status register */
+
+#define RCC_CSR_LSI1ON (1 << 0) /* Bit 0: LSI1 Internal Low Speed oscillator enable */
+#define RCC_CSR_LSI1RDY (1 << 1) /* Bit 1: LSI1 Internal Low Speed oscillator Ready */
+#define RCC_CSR_LSI2ON (1 << 2) /* Bit 2: LSI2 Internal Low Speed oscillator enable */
+#define RCC_CSR_LSI2RDY (1 << 3) /* Bit 3: LSI2 Internal Low Speed oscillator Ready */
+
+#define RCC_CSR_LSI2TRIM_SHIFT (8) /* Bits: 8-11: LSI2 oscillator trim */
+#define RCC_CSR_LSI2TRIM_MASK (0x0f << RCC_CSR_LSI2TRIM_SHIFT)
+
+#define RCC_CSR_RFWKPSEL_SHIFT (14) /* Bits: 14-15: RF system wakeup clock source selection */
+#define RCC_CSR_RFWKPSEL_MASK (0x0f << RCC_CSR_RFWKPSEL_SHIFT)
+# define RCC_CSR_RFWKPSEL_NOCLK (0x0 << RCC_CSR_RFWKPSEL_SHIFT) /* 00: No clock */
+# define RCC_CSR_RFWKPSEL_LSE (0x1 << RCC_CSR_RFWKPSEL_SHIFT) /* 01: LSE used as RF wakeup clock */
+# define RCC_CSR_RFWKPSEL_HSE (0x3 << RCC_CSR_RFWKPSEL_SHIFT) /* 11: HSE divided by 1024 used as RF clock */
+
+#define RCC_CSR_RFRSTS (1 << 16) /* Bit 16: Radio system BLE and 802.15.4 reset status */
+#define RCC_CSR_RMVF (1 << 23) /* Bit 23: Remove reset flag */
+#define RCC_CSR_OBLRSTF (1 << 25) /* Bit 25: Option byte loader reset flag */
+#define RCC_CSR_PINRSTF (1 << 26) /* Bit 26: PIN reset flag */
+#define RCC_CSR_BORRSTF (1 << 27) /* Bit 27: BOR reset flag */
+#define RCC_CSR_SFTRSTF (1 << 28) /* Bit 28: Software Reset flag */
+#define RCC_CSR_IWWGRSTF (1 << 29) /* Bit 29: Independent window watchdog reset flag */
+#define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-power reset flag */
+
+/* Clock recovery RC register */
+
+#define RCC_CRRCR_HSI48ON (1 << 0) /* Bit 0: HSI48 clock enable */
+#define RCC_CRRCR_HSI48RDY (1 << 1) /* Bit 1: HSI48 clock ready flag */
+#define RCC_CRRCR_HSI48CAL_SHIFT (7) /* Bits 7-15: HSI48 clock calibration */
+#define RCC_CRRCR_HSI48CAL_MASK (0x01ff << RCC_CRRCR_HSI48CAL_SHIFT)
+
+/* Clock HSE register */
+
+#define RCC_HSECR_UNLOCKED (1 << 0) /* Bit 0: HSE clock control register unlocked */
+#define RCC_HSECR_HSES (1 << 3) /* Bit 3: HSE sense amplifier threshold */
+# define RCC_HSECR_HSES_1d2 (0 << 3) /* 0: HSE bias current factor 1/2 */
+# define RCC_HSECR_HSES_3d4 (1 << 3) /* 1: HSE bias current factor 3/4 */
+
+#define RCC_HSECR_HSEGMC_SHIFT (4) /* Bits 4-6: HSE current control */
+#define RCC_HSECR_HSEGMC_MASK (0x7 << RCC_HSECR_HSEGMC_SHIFT)
+# define RCC_HSECR_HSEGMC_018 (0x0 << RCC_HSECR_HSEGMC_SHIFT) /* 000: current max limit 0.18 mA/V */
+# define RCC_HSECR_HSEGMC_057 (0x1 << RCC_HSECR_HSEGMC_SHIFT) /* 001: current max limit 0.57 mA/V */
+# define RCC_HSECR_HSEGMC_078 (0x2 << RCC_HSECR_HSEGMC_SHIFT) /* 010: current max limit 0.78 mA/V */
+# define RCC_HSECR_HSEGMC_113 (0x3 << RCC_HSECR_HSEGMC_SHIFT) /* 011: current max limit 1.13 mA/V */
+# define RCC_HSECR_HSEGMC_061 (0x4 << RCC_HSECR_HSEGMC_SHIFT) /* 100: current max limit 0.61 mA/V */
+# define RCC_HSECR_HSEGMC_165 (0x5 << RCC_HSECR_HSEGMC_SHIFT) /* 101: current max limit 1.65 mA/V */
+# define RCC_HSECR_HSEGMC_212 (0x6 << RCC_HSECR_HSEGMC_SHIFT) /* 110: current max limit 2.12 mA/V */
+# define RCC_HSECR_HSEGMC_284 (0x7 << RCC_HSECR_HSEGMC_SHIFT) /* 111: current max limit 2.84 mA/V */
+
+#define RCC_HSECR_HSETUNE_SHIFT (8) /* Bits 8-13: HSE capacitor tuning */
+#define RCC_HSECR_HSETUNE_MASK (0x7 << RCC_HSECR_HSETUNE_SHIFT)
+
+#define RCC_HSECR_SHDHPREF (1 << 16) /* Bit 16: HCLK4 shared prescaler flag (AHB4, FLASH, SRAM2) */
+#define RCC_HSECR_C2HPREF (1 << 17) /* Bit 17: CPU2 HCLK2 prescaler flag */
+
+#define RCC_HSECR_RFCSS (1 << 20) /* Bit 20: Radio system HCLK5 and APB3 selected clock */
+# define RCC_HSECR_RFCSS_HSI16 (0 << 20) /* HSI16 used for Radio system HCLK5 and APB3 clock */
+# define RCC_HSECR_RFCSS_HSE2 (1 << 20) /* HSE divided by 2 used for Radio system HCLK5 and APB3 clock */
+
+/* Extended clock recovery register */
+
+#define RCC_EXTCFGR_SHDHPRE_SHIFT (0) /* Bits: 0-3: HCLK4 shared prescaler (AHB4, FLASH, SRAM2) */
+#define RCC_EXTCFGR_SHDHPRE_MASK (0xf)
+# define RCC_EXTCFGR_SHDHPRE_1 (0x0 << RCC_EXTCFGR_SHDHPRE_SHIFT) /* 0000: SYSCLK not divided */
+# define RCC_EXTCFGR_SHDHPRE_3 (0x1 << RCC_EXTCFGR_SHDHPRE_SHIFT) /* 0001: SYSCLK divided by 3 */
+# define RCC_EXTCFGR_SHDHPRE_5 (0x2 << RCC_EXTCFGR_SHDHPRE_SHIFT) /* 0010: SYSCLK divided by 5 */
+# define RCC_EXTCFGR_SHDHPRE_6 (0x5 << RCC_EXTCFGR_SHDHPRE_SHIFT) /* 0101: SYSCLK divided by 6 */
+# define RCC_EXTCFGR_SHDHPRE_10 (0x6 << RCC_EXTCFGR_SHDHPRE_SHIFT) /* 0110: SYSCLK divided by 10 */
+# define RCC_EXTCFGR_SHDHPRE_32 (0x7 << RCC_EXTCFGR_SHDHPRE_SHIFT) /* 0111: SYSCLK divided by 32 */
+# define RCC_EXTCFGR_SHDHPRE_2 (0x8 << RCC_EXTCFGR_SHDHPRE_SHIFT) /* 1000: SYSCLK divided by 2 */
+# define RCC_EXTCFGR_SHDHPRE_4 (0x9 << RCC_EXTCFGR_SHDHPRE_SHIFT) /* 1001: SYSCLK divided by 4 */
+# define RCC_EXTCFGR_SHDHPRE_8 (0xa << RCC_EXTCFGR_SHDHPRE_SHIFT) /* 1010: SYSCLK divided by 8 */
+# define RCC_EXTCFGR_SHDHPRE_16 (0xb << RCC_EXTCFGR_SHDHPRE_SHIFT) /* 1011: SYSCLK divided by 16 */
+# define RCC_EXTCFGR_SHDHPRE_64 (0xc << RCC_EXTCFGR_SHDHPRE_SHIFT) /* 1100: SYSCLK divided by 64 */
+# define RCC_EXTCFGR_SHDHPRE_128 (0xd << RCC_EXTCFGR_SHDHPRE_SHIFT) /* 1101: SYSCLK divided by 128 */
+# define RCC_EXTCFGR_SHDHPRE_256 (0xe << RCC_EXTCFGR_SHDHPRE_SHIFT) /* 1110: SYSCLK divided by 256 */
+# define RCC_EXTCFGR_SHDHPRE_512 (0xf << RCC_EXTCFGR_SHDHPRE_SHIFT) /* 1111: SYSCLK divided by 512 */
+
+#define RCC_EXTCFGR_C2HPRE_SHIFT (4) /* Bits: 4-7: CPU2 HCLK2 prescaler */
+#define RCC_EXTCFGR_C2HPRE_MASK (0xf)
+# define RCC_EXTCFGR_C2HPRE_1 (0x0 << RCC_EXTCFGR_C2HPRE_SHIFT) /* 0000: SYSCLK not divided */
+# define RCC_EXTCFGR_C2HPRE_3 (0x1 << RCC_EXTCFGR_C2HPRE_SHIFT) /* 0001: SYSCLK divided by 3 */
+# define RCC_EXTCFGR_C2HPRE_5 (0x2 << RCC_EXTCFGR_C2HPRE_SHIFT) /* 0010: SYSCLK divided by 5 */
+# define RCC_EXTCFGR_C2HPRE_6 (0x5 << RCC_EXTCFGR_C2HPRE_SHIFT) /* 0101: SYSCLK divided by 6 */
+# define RCC_EXTCFGR_C2HPRE_10 (0x6 << RCC_EXTCFGR_C2HPRE_SHIFT) /* 0110: SYSCLK divided by 10 */
+# define RCC_EXTCFGR_C2HPRE_32 (0x7 << RCC_EXTCFGR_C2HPRE_SHIFT) /* 0111: SYSCLK divided by 32 */
+# define RCC_EXTCFGR_C2HPRE_2 (0x8 << RCC_EXTCFGR_C2HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */
+# define RCC_EXTCFGR_C2HPRE_4 (0x9 << RCC_EXTCFGR_C2HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */
+# define RCC_EXTCFGR_C2HPRE_8 (0xa << RCC_EXTCFGR_C2HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */
+# define RCC_EXTCFGR_C2HPRE_16 (0xb << RCC_EXTCFGR_C2HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */
+# define RCC_EXTCFGR_C2HPRE_64 (0xc << RCC_EXTCFGR_C2HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */
+# define RCC_EXTCFGR_C2HPRE_128 (0xd << RCC_EXTCFGR_C2HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */
+# define RCC_EXTCFGR_C2HPRE_256 (0xe << RCC_EXTCFGR_C2HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */
+# define RCC_EXTCFGR_C2HPRE_512 (0xf << RCC_EXTCFGR_C2HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */
+
+/* CPU2 AHB1 Peripheral Clock enable register */
+
+#define RCC_C2AHB1ENR_DMA1EN (1 << 0) /* Bit 0: CPU2 DMA1 Enable */
+#define RCC_C2AHB1ENR_DMA2EN (1 << 1) /* Bit 1: CPU2 DMA2 Enable */
+#define RCC_C2AHB1ENR_DMAMUX1EN (1 << 2) /* Bit 2: CPU2 DMAMUX1 Enable */
+#define RCC_C2AHB1ENR_SRAM1EN (1 << 9) /* Bit 9: CPU2 SRAM1 Enable */
+#define RCC_C2AHB1ENR_CRCEN (1 << 12) /* Bit 12: CPU2 CRC Enable */
+#define RCC_C2AHB1ENR_TSCEN (1 << 16) /* Bit 16: CPU2 Touch Sensing Controller Enable */
+
+/* CPU2 AHB2 Peripheral Clock enable register */
+
+#define RCC_C2AHB2ENR_GPIOEN(n) (1 << (n))
+#define RCC_C2AHB2ENR_GPIOAEN (1 << 0) /* Bit 0: CPU2 IO port A Enable */
+#define RCC_C2AHB2ENR_GPIOBEN (1 << 1) /* Bit 1: CPU2 IO port B Enable */
+#define RCC_C2AHB2ENR_GPIOCEN (1 << 2) /* Bit 2: CPU2 IO port C Enable */
+#define RCC_C2AHB2ENR_GPIODEN (1 << 3) /* Bit 3: CPU2 IO port D Enable */
+#define RCC_C2AHB2ENR_GPIOEEN (1 << 4) /* Bit 4: CPU2 IO port E Enable */
+#define RCC_C2AHB2ENR_GPIOHEN (1 << 7) /* Bit 7: CPU2 IO port H Enable */
+#define RCC_C2AHB2ENR_ADCEN (1 << 13) /* Bit 13: CPU2 ADC interface Enable */
+#define RCC_C2AHB2ENR_AES1EN (1 << 16) /* Bit 16: CPU2 AES1 Enable */
+
+/* CPU2 AHB3 and AHB4 Peripheral Clock enable register */
+
+#define RCC_C2AHB3ENR_PKAEN (1 << 16) /* Bit 16: CPU2 PKA Enable */
+#define RCC_C2AHB3ENR_AES2EN (1 << 17) /* Bit 17: CPU2 AES2 Enable */
+#define RCC_C2AHB3ENR_RNGEN (1 << 18) /* Bit 18: CPU2 RNG Enable */
+#define RCC_C2AHB3ENR_HSEMEN (1 << 19) /* Bit 19: CPU2 HSEM Enable */
+#define RCC_C2AHB3ENR_IPCCEN (1 << 20) /* Bit 20: CPU2 IPCC Enable */
+#define RCC_C2AHB3ENR_FLASHEN (1 << 25) /* Bit 25: CPU2 FLASH Enable */
+
+/* CPU2 APB1 Peripheral Clock enable register 1 */
+
+#define RCC_C2APB1ENR1_TIM2EN (1 << 0) /* Bit 0: CPU2 TIM2 enable */
+#define RCC_C2APB1ENR1_LCDEN (1 << 9) /* Bit 9: CPU2 LCD enable */
+#define RCC_C2APB1ENR1_RTCAPBEN (1 << 10) /* Bit 10: CPU2 RTC APB clock enable */
+#define RCC_C2APB1ENR1_SPI2EN (1 << 14) /* Bit 14: CPU2 SPI2 enable */
+#define RCC_C2APB1ENR1_I2C1EN (1 << 21) /* Bit 21: CPU2 I2C1 enable */
+#define RCC_C2APB1ENR1_I2C3EN (1 << 23) /* Bit 23: CPU2 I2C3 enable */
+#define RCC_C2APB1ENR1_CRSEN (1 << 24) /* Bit 24: CPU2 CRSEN enable */
+#define RCC_C2APB1ENR1_USBEN (1 << 26) /* Bit 26: CPU2 USB enable */
+#define RCC_C2APB1ENR1_LPTIM1EN (1 << 31) /* Bit 31: CPU2 LPTIM1 enable */
+
+/* CPU2 APB1 Peripheral Clock enable register 2 */
+
+#define RCC_C2APB1ENR2_LPUART1EN (1 << 0) /* Bit 0: CPU2 LPUART1 enable */
+#define RCC_C2APB1ENR2_LPTIM2EN (1 << 5) /* Bit 5: CPU2 LPTIM2 enable */
+
+/* CPU2 APB2 Peripheral Clock enable register */
+
+#define RCC_C2APB2ENR_TIM1EN (1 << 11) /* Bit 11: CPU2 TIM1 enable */
+#define RCC_C2APB2ENR_SPI1EN (1 << 12) /* Bit 12: CPU2 SPI1 enable */
+#define RCC_C2APB2ENR_USART1EN (1 << 14) /* Bit 14: CPU2 USART1 enable */
+#define RCC_C2APB2ENR_TIM16EN (1 << 17) /* Bit 17: CPU2 TIM16 enable */
+#define RCC_C2APB2ENR_TIM17EN (1 << 18) /* Bit 18: CPU2 TIM17 enable */
+#define RCC_C2APB2ENR_SAI1EN (1 << 21) /* Bit 21: CPU2 SAI1 enable */
+
+/* CPU2 APB3 Peripheral Clock enable register */
+
+#define RCC_C2APB3ENR_BLEEN (1 << 0) /* Bit 0: CPU2 LPUART1 enable */
+#define RCC_C2APB3ENR_802EN (1 << 1) /* Bit 1: CPU2 LPTIM2 enable */
+
+/* CPU2 AHB1 peripheral clock enable in sleep and stop modes register */
+
+#define RCC_C2AHB1SMENR_DMA1LPSMEN (1 << 0) /* Bit 0: CPU2 DMA1 enable in sleep and stop modes */
+#define RCC_C2AHB1SMENR_DMA2LPSMEN (1 << 1) /* Bit 1: CPU2 DMA2 enable in sleep and stop modes */
+#define RCC_C2AHB1SMENR_DMAMUX1SMEN (1 << 2) /* Bit 2: CPU2 DMAMUX1 clock enable in sleep and stop modes */
+#define RCC_C2AHB1SMENR_SRAM1SMEN (1 << 9) /* Bit 9: CPU2 SRAM1 enable in sleep and stop modes */
+#define RCC_C2AHB1SMENR_CRCSMEN (1 << 12) /* Bit 12: CPU2 CRC enable in sleep and stop modes */
+#define RCC_C2AHB1SMENR_TSCSMEN (1 << 16) /* Bit 16: CPU2 TSC enable in sleep and stop modes */
+
+/* CPU2 AHB2 peripheral clock enable in sleep and stop modes register */
+
+#define RCC_C2AHB2SMENR_GPIOASMEN (1 << 0) /* Bit 0: CPU2 IO port A enable in sleep and stop modes */
+#define RCC_C2AHB2SMENR_GPIOBSMEN (1 << 1) /* Bit 1: CPU2 IO port B enable in sleep and stop modes */
+#define RCC_C2AHB2SMENR_GPIOCSMEN (1 << 2) /* Bit 2: CPU2 IO port C enable in sleep and stop modes */
+#define RCC_C2AHB2SMENR_GPIODSMEN (1 << 3) /* Bit 3: CPU2 IO port D enable in sleep and stop modes */
+#define RCC_C2AHB2SMENR_GPIOESMEN (1 << 4) /* Bit 4: CPU2 IO port E enable in sleep and stop modes */
+#define RCC_C2AHB2SMENR_GPIOHSMEN (1 << 7) /* Bit 7: CPU2 IO port H enable in sleep and stop modes */
+#define RCC_C2AHB2SMENR_ADCSMEN (1 << 13) /* Bit 13: CPU2 ADC enable in sleep and stop modes */
+#define RCC_C2AHB2SMENR_AES1SMEN (1 << 16) /* Bit 16: CPU2 AES1 enable in sleep and stop modes */
+
+/* CPU2 AHB3 and AHB4 peripheral clock enable in sleep and stop modes */
+
+#define RCC_C2AHB3SMENR_PKASMEN (1 << 16) /* Bit 16: CPU2 PKA enable in sleep and stop modes */
+#define RCC_C2AHB3SMENR_AES2SMEN (1 << 17) /* Bit 17: CPU2 AES2 enable in sleep and stop modes */
+#define RCC_C2AHB3SMENR_RNGSMEN (1 << 18) /* Bit 18: CPU2 RNG enable in sleep and stop modes */
+#define RCC_C2AHB3SMENR_SRAM2SMEN (1 << 24) /* Bit 24: CPU2 SRAM2x enable in sleep and stop modes */
+#define RCC_C2AHB3SMENR_FLASHSMEN (1 << 25) /* Bit 25: CPU2 FLASH memory enable in sleep and stop modes */
+
+/* CPU2 APB1 peripheral clock enable in sleep and stop modes register 1 */
+
+#define RCC_C2APB1SMENR1_TIM2SMEN (1 << 0) /* Bit 0: CPU2 TIM2 enable in sleep and stop modes */
+#define RCC_C2APB1SMENR1_LCDSMEN (9 << 0) /* Bit 9: CPU2 LCD enable in sleep and stop modes */
+#define RCC_C2APB1SMENR1_RTCAPBSMEN (1 << 10) /* Bit 10: CPU2 RTC APB clock enable in sleep and stop modes */
+#define RCC_C2APB1SMENR1_SPI2SMEN (1 << 14) /* Bit 14: CPU2 SPI2 enable in sleep and stop modes */
+#define RCC_C2APB1SMENR1_I2C1SMEN (1 << 21) /* Bit 21: CPU2 I2C1 enable in sleep and stop modes */
+#define RCC_C2APB1SMENR1_I2C3SMEN (1 << 23) /* Bit 23: CPU2 I2C3 enable in sleep and stop modes */
+#define RCC_C2APB1SMENR1_CRSSMEN (1 << 24) /* Bit 24: CPU2 CRS enable in sleep and stop modes */
+#define RCC_C2APB1SMENR1_USBSMEN (1 << 26) /* Bit 26: CPU2 USB enable in sleep and stop modes */
+#define RCC_C2APB1SMENR1_LPTIM1SMEN (1 << 31) /* Bit 31: CPU2 LPTIM1 enable in sleep and stop modes */
+
+/* CPU2 APB1 peripheral clock enable in sleep and stop modes register 2 */
+
+#define RCC_C2APB1SMENR2_LPUART1SMEN (1 << 0) /* Bit 0: CPU2 LPUART1 enable in sleep and stop modes */
+#define RCC_C2APB1SMENR2_LPTIM2SMEN (1 << 5) /* Bit 5: CPU2 LPTIM2 enable in sleep and stop modes */
+
+/* CPU2 APB2 peripheral clock enable in sleep and stop modes register */
+
+#define RCC_C2APB2SMENR_TIM1SMEN (1 << 11) /* Bit 11: CPU2 TIM1 enable in sleep and stop modes */
+#define RCC_C2APB2SMENR_SPI1SMEN (1 << 12) /* Bit 12: CPU2 SPI1 enable in sleep and stop modes */
+#define RCC_C2APB2SMENR_USART1SMEN (1 << 14) /* Bit 14: CPU2 USART1 enable in sleep and stop modes */
+#define RCC_C2APB2SMENR_TIM16SMEN (1 << 17) /* Bit 17: CPU2 TIM16 enable in sleep and stop modes */
+#define RCC_C2APB2SMENR_TIM17SMEN (1 << 18) /* Bit 18: CPU2 TIM17 enable in sleep and stop modes */
+#define RCC_C2APB2SMENR_SAI1SMEN (1 << 21) /* Bit 21: CPU2 SAI1 enable in sleep and stop modes */
+
+/* CPU2 APB3 Peripheral Clock enable in sleep and stop modes register */
+
+#define RCC_C2APB3ENR_BLEEN (1 << 0) /* Bit 0: CPU2 LPUART1 enable in sleep and stop modes */
+#define RCC_C2APB3ENR_802EN (1 << 1) /* Bit 1: CPU2 LPTIM2 enable in sleep and stop modes */
+
+#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_RCC_H */
diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_rtc.h b/arch/arm/src/stm32wb/hardware/stm32wb_rtc.h
new file mode 100644
index 0000000000..918d4a6ac9
--- /dev/null
+++ b/arch/arm/src/stm32wb/hardware/stm32wb_rtc.h
@@ -0,0 +1,388 @@
+/****************************************************************************
+ * arch/arm/src/stm32wb/hardware/stm32wb_rtc.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_RTCC_H
+#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_RTCC_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define STM32WB_RTC_TR_OFFSET 0x0000 /* RTC time register */
+#define STM32WB_RTC_DR_OFFSET 0x0004 /* RTC date register */
+#define STM32WB_RTC_CR_OFFSET 0x0008 /* RTC control register */
+#define STM32WB_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */
+#define STM32WB_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */
+#define STM32WB_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */
+#define STM32WB_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */
+#define STM32WB_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */
+#define STM32WB_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */
+#define STM32WB_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */
+#define STM32WB_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */
+#define STM32WB_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */
+#define STM32WB_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */
+#define STM32WB_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */
+#define STM32WB_RTC_CALR_OFFSET 0x003c /* RTC calibration register */
+#define STM32WB_RTC_TAMPCR_OFFSET 0x0040 /* RTC tamper configuration register */
+#define STM32WB_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */
+#define STM32WB_RTC_ALRMBSSR_OFFSET 0x0048 /* RTC alarm B sub second register */
+#define STM32WB_RTC_OR_OFFSET 0x004c /* RTC option register */
+
+#define STM32WB_RTC_BKPR_OFFSET(n) (0x0050 + ((n) << 2))
+#define STM32WB_RTC_BKP0R_OFFSET 0x0050 /* RTC backup register 0 */
+#define STM32WB_RTC_BKP1R_OFFSET 0x0054 /* RTC backup register 1 */
+#define STM32WB_RTC_BKP2R_OFFSET 0x0058 /* RTC backup register 2 */
+#define STM32WB_RTC_BKP3R_OFFSET 0x005c /* RTC backup register 3 */
+#define STM32WB_RTC_BKP4R_OFFSET 0x0060 /* RTC backup register 4 */
+#define STM32WB_RTC_BKP5R_OFFSET 0x0064 /* RTC backup register 5 */
+#define STM32WB_RTC_BKP6R_OFFSET 0x0068 /* RTC backup register 6 */
+#define STM32WB_RTC_BKP7R_OFFSET 0x006c /* RTC backup register 7 */
+#define STM32WB_RTC_BKP8R_OFFSET 0x0070 /* RTC backup register 8 */
+#define STM32WB_RTC_BKP9R_OFFSET 0x0074 /* RTC backup register 9 */
+#define STM32WB_RTC_BKP10R_OFFSET 0x0078 /* RTC backup register 10 */
+#define STM32WB_RTC_BKP11R_OFFSET 0x007c /* RTC backup register 11 */
+#define STM32WB_RTC_BKP12R_OFFSET 0x0080 /* RTC backup register 12 */
+#define STM32WB_RTC_BKP13R_OFFSET 0x0084 /* RTC backup register 13 */
+#define STM32WB_RTC_BKP14R_OFFSET 0x0088 /* RTC backup register 14 */
+#define STM32WB_RTC_BKP15R_OFFSET 0x008c /* RTC backup register 15 */
+#define STM32WB_RTC_BKP16R_OFFSET 0x0090 /* RTC backup register 16 */
+#define STM32WB_RTC_BKP17R_OFFSET 0x0094 /* RTC backup register 17 */
+#define STM32WB_RTC_BKP18R_OFFSET 0x0098 /* RTC backup register 18 */
+#define STM32WB_RTC_BKP19R_OFFSET 0x009c /* RTC backup register 19 */
+
+/* Register Addresses *******************************************************/
+
+#define STM32WB_RTC_TR (STM32WB_RTC_BASE + STM32WB_RTC_TR_OFFSET)
+#define STM32WB_RTC_DR (STM32WB_RTC_BASE + STM32WB_RTC_DR_OFFSET)
+#define STM32WB_RTC_CR (STM32WB_RTC_BASE + STM32WB_RTC_CR_OFFSET)
+#define STM32WB_RTC_ISR (STM32WB_RTC_BASE + STM32WB_RTC_ISR_OFFSET)
+#define STM32WB_RTC_PRER (STM32WB_RTC_BASE + STM32WB_RTC_PRER_OFFSET)
+#define STM32WB_RTC_WUTR (STM32WB_RTC_BASE + STM32WB_RTC_WUTR_OFFSET)
+#define STM32WB_RTC_ALRMAR (STM32WB_RTC_BASE + STM32WB_RTC_ALRMAR_OFFSET)
+#define STM32WB_RTC_ALRMBR (STM32WB_RTC_BASE + STM32WB_RTC_ALRMBR_OFFSET)
+#define STM32WB_RTC_WPR (STM32WB_RTC_BASE + STM32WB_RTC_WPR_OFFSET)
+#define STM32WB_RTC_SSR (STM32WB_RTC_BASE + STM32WB_RTC_SSR_OFFSET)
+#define STM32WB_RTC_SHIFTR (STM32WB_RTC_BASE + STM32WB_RTC_SHIFTR_OFFSET)
+#define STM32WB_RTC_TSTR (STM32WB_RTC_BASE + STM32WB_RTC_TSTR_OFFSET)
+#define STM32WB_RTC_TSDR (STM32WB_RTC_BASE + STM32WB_RTC_TSDR_OFFSET)
+#define STM32WB_RTC_TSSSR (STM32WB_RTC_BASE + STM32WB_RTC_TSSSR_OFFSET)
+#define STM32WB_RTC_CALR (STM32WB_RTC_BASE + STM32WB_RTC_CALR_OFFSET)
+#define STM32WB_RTC_TAMPCR (STM32WB_RTC_BASE + STM32WB_RTC_TAMPCR_OFFSET)
+#define STM32WB_RTC_ALRMASSR (STM32WB_RTC_BASE + STM32WB_RTC_ALRMASSR_OFFSET)
+#define STM32WB_RTC_ALRMBSSR (STM32WB_RTC_BASE + STM32WB_RTC_ALRMBSSR_OFFSET)
+#define STM32WB_RTC_OR (STM32WB_RTC_BASE + STM32WB_RTC_OR_OFFSET)
+
+#define STM32WB_RTC_BKPR(n) (STM32WB_RTC_BASE + STM32WB_RTC_BKPR_OFFSET(n))
+#define STM32WB_RTC_BKP0R (STM32WB_RTC_BASE + STM32WB_RTC_BKP0R_OFFSET)
+#define STM32WB_RTC_BKP1R (STM32WB_RTC_BASE + STM32WB_RTC_BKP1R_OFFSET)
+#define STM32WB_RTC_BKP2R (STM32WB_RTC_BASE + STM32WB_RTC_BKP2R_OFFSET)
+#define STM32WB_RTC_BKP3R (STM32WB_RTC_BASE + STM32WB_RTC_BKP3R_OFFSET)
+#define STM32WB_RTC_BKP4R (STM32WB_RTC_BASE + STM32WB_RTC_BKP4R_OFFSET)
+#define STM32WB_RTC_BKP5R (STM32WB_RTC_BASE + STM32WB_RTC_BKP5R_OFFSET)
+#define STM32WB_RTC_BKP6R (STM32WB_RTC_BASE + STM32WB_RTC_BKP6R_OFFSET)
+#define STM32WB_RTC_BKP7R (STM32WB_RTC_BASE + STM32WB_RTC_BKP7R_OFFSET)
+#define STM32WB_RTC_BKP8R (STM32WB_RTC_BASE + STM32WB_RTC_BKP8R_OFFSET)
+#define STM32WB_RTC_BKP9R (STM32WB_RTC_BASE + STM32WB_RTC_BKP9R_OFFSET)
+#define STM32WB_RTC_BKP10R (STM32WB_RTC_BASE + STM32WB_RTC_BKP10R_OFFSET)
+#define STM32WB_RTC_BKP11R (STM32WB_RTC_BASE + STM32WB_RTC_BKP11R_OFFSET)
+#define STM32WB_RTC_BKP12R (STM32WB_RTC_BASE + STM32WB_RTC_BKP12R_OFFSET)
+#define STM32WB_RTC_BKP13R (STM32WB_RTC_BASE + STM32WB_RTC_BKP13R_OFFSET)
+#define STM32WB_RTC_BKP14R (STM32WB_RTC_BASE + STM32WB_RTC_BKP14R_OFFSET)
+#define STM32WB_RTC_BKP15R (STM32WB_RTC_BASE + STM32WB_RTC_BKP15R_OFFSET)
+#define STM32WB_RTC_BKP16R (STM32WB_RTC_BASE + STM32WB_RTC_BKP16R_OFFSET)
+#define STM32WB_RTC_BKP17R (STM32WB_RTC_BASE + STM32WB_RTC_BKP17R_OFFSET)
+#define STM32WB_RTC_BKP18R (STM32WB_RTC_BASE + STM32WB_RTC_BKP18R_OFFSET)
+#define STM32WB_RTC_BKP19R (STM32WB_RTC_BASE + STM32WB_RTC_BKP19R_OFFSET)
+
+# define STM32WB_RTC_BKCOUNT 20
+
+/* Register Bitfield Definitions ********************************************/
+
+/* RTC time register */
+
+#define RTC_TR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format */
+#define RTC_TR_SU_MASK (0xf << RTC_TR_SU_SHIFT)
+#define RTC_TR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format */
+#define RTC_TR_ST_MASK (0x7 << RTC_TR_ST_SHIFT)
+#define RTC_TR_MNU_SHIFT (8) /* Bit 8-11: Minute units in BCD format */
+#define RTC_TR_MNU_MASK (0xf << RTC_TR_MNU_SHIFT)
+#define RTC_TR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format */
+#define RTC_TR_MNT_MASK (0x7 << RTC_TR_MNT_SHIFT)
+#define RTC_TR_HU_SHIFT (16) /* Bit 16-19: Hour units in BCD format */
+#define RTC_TR_HU_MASK (0xf << RTC_TR_HU_SHIFT)
+#define RTC_TR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format */
+#define RTC_TR_HT_MASK (0x3 << RTC_TR_HT_SHIFT)
+#define RTC_TR_PM (1 << 22) /* Bit 22: AM/PM notation */
+#define RTC_TR_RESERVED_BITS (0xff808080)
+
+/* RTC date register */
+
+#define RTC_DR_DU_SHIFT (0) /* Bits 0-3: Date units in BCD format */
+#define RTC_DR_DU_MASK (0xf << RTC_DR_DU_SHIFT)
+#define RTC_DR_DT_SHIFT (4) /* Bits 4-5: Date tens in BCD format */
+#define RTC_DR_DT_MASK (0x3 << RTC_DR_DT_SHIFT)
+#define RTC_DR_MU_SHIFT (8) /* Bits 8-11: Month units in BCD format */
+#define RTC_DR_MU_MASK (0xf << RTC_DR_MU_SHIFT)
+#define RTC_DR_MT (1 << 12) /* Bit 12: Month tens in BCD format */
+#define RTC_DR_WDU_SHIFT (13) /* Bits 13-15: Week day units */
+#define RTC_DR_WDU_MASK (0x7 << RTC_DR_WDU_SHIFT)
+# define RTC_DR_WDU_MONDAY (0x1 << RTC_DR_WDU_SHIFT)
+# define RTC_DR_WDU_TUESDAY (0x2 << RTC_DR_WDU_SHIFT)
+# define RTC_DR_WDU_WEDNESDAY (0x3 << RTC_DR_WDU_SHIFT)
+# define RTC_DR_WDU_THURSDAY (0x4 << RTC_DR_WDU_SHIFT)
+# define RTC_DR_WDU_FRIDAY (0x5 << RTC_DR_WDU_SHIFT)
+# define RTC_DR_WDU_SATURDAY (0x6 << RTC_DR_WDU_SHIFT)
+# define RTC_DR_WDU_SUNDAY (0x7 << RTC_DR_WDU_SHIFT)
+#define RTC_DR_YU_SHIFT (16) /* Bits 16-19: Year units in BCD format */
+#define RTC_DR_YU_MASK (0xf << RTC_DR_YU_SHIFT)
+#define RTC_DR_YT_SHIFT (20) /* Bits 20-23: Year tens in BCD format */
+#define RTC_DR_YT_MASK (0xf << RTC_DR_YT_SHIFT)
+#define RTC_DR_RESERVED_BITS (0xff0000c0)
+
+/* RTC control register */
+
+#define RTC_CR_WUCKSEL_SHIFT (0) /* Bits 0-2: Wakeup clock selection */
+#define RTC_CR_WUCKSEL_MASK (0x7 << RTC_CR_WUCKSEL_SHIFT)
+# define RTC_CR_WUCKSEL_RTCDIV16 (0x0 << RTC_CR_WUCKSEL_SHIFT) /* 000: RTC/16 clock is selected */
+# define RTC_CR_WUCKSEL_RTCDIV8 (0x1 << RTC_CR_WUCKSEL_SHIFT) /* 001: RTC/8 clock is selected */
+# define RTC_CR_WUCKSEL_RTCDIV4 (0x2 << RTC_CR_WUCKSEL_SHIFT) /* 010: RTC/4 clock is selected */
+# define RTC_CR_WUCKSEL_RTCDIV2 (0x3 << RTC_CR_WUCKSEL_SHIFT) /* 011: RTC/2 clock is selected */
+# define RTC_CR_WUCKSEL_CKSPRE (0x4 << RTC_CR_WUCKSEL_SHIFT) /* 10x: ck_spre clock is selected */
+# define RTC_CR_WUCKSEL_CKSPREADD (0x6 << RTC_CR_WUCKSEL_SHIFT) /* 11x: ck_spre and 2^16 added to WUT counter */
+
+#define RTC_CR_TSEDGE (1 << 3) /* Bit 3: Timestamp event active edge */
+# define RTC_CR_TSEDGE_RISING (0 << 3) /* 0: Rising edge generates event */
+# define RTC_CR_TSEDGE_FALLING (1 << 3) /* 1: Falling edge generates event */
+
+#define RTC_CR_REFCKON (1 << 4) /* Bit 4: Reference clock detection enable (50 or 60 Hz) */
+#define RTC_CR_BYPSHAD (1 << 5) /* Bit 5: Bypass the shadow registers */
+
+#define RTC_CR_FMT (1 << 6) /* Bit 6: Hour format */
+# define RTC_CR_FMT_24 (0 << 6) /* 0: 24 hour/day format */
+# define RTC_CR_FMT_AMPM (1 << 6) /* 1: AM/PM hour format */
+
+#define RTC_CR_ALRAE (1 << 8) /* Bit 8: Alarm A enable */
+#define RTC_CR_ALRBE (1 << 9) /* Bit 9: Alarm B enable */
+#define RTC_CR_WUTE (1 << 10) /* Bit 10: Wakeup timer enable */
+#define RTC_CR_TSE (1 << 11) /* Bit 11: Time stamp enable */
+#define RTC_CR_ALRAIE (1 << 12) /* Bit 12: Alarm A interrupt enable */
+#define RTC_CR_ALRBIE (1 << 13) /* Bit 13: Alarm B interrupt enable */
+#define RTC_CR_WUTIE (1 << 14) /* Bit 14: Wakeup timer interrupt enable */
+#define RTC_CR_TSIE (1 << 15) /* Bit 15: Timestamp interrupt enable */
+#define RTC_CR_ADD1H (1 << 16) /* Bit 16: Add 1 hour (summer time change) */
+#define RTC_CR_SUB1H (1 << 17) /* Bit 17: Subtract 1 hour (winter time change) */
+#define RTC_CR_BKP (1 << 18) /* Bit 18: Backup */
+#define RTC_CR_COSEL (1 << 19) /* Bit 19: Calibration output selection */
+# define RTC_CR_COSEL_512HZ (0 << 19) /* 0: Calibration output is 512 Hz */
+# define RTC_CR_COSEL_1HZ (1 << 19) /* 1: Calibration output is 1 Hz */
+
+#define RTC_CR_POL (1 << 20) /* Bit 20: Output polarity */
+# define RTC_CR_POL_HIGH (0 << 20) /* 0: Output pin is High on ALRAF/ALRBF/WUTF */
+# define RTC_CR_POL_LOW (1 << 20) /* 1: Output pin is Low on ALRAF/ALRBF/WUTF */
+
+#define RTC_CR_OSEL_SHIFT (21) /* Bits 21-22: Output selection */
+#define RTC_CR_OSEL_MASK (0x3 << RTC_CR_OSEL_SHIFT)
+# define RTC_CR_OSEL_DISABLED (0x0 << RTC_CR_OSEL_SHIFT) /* 00: Output disabled */
+# define RTC_CR_OSEL_ALRMA (0x1 << RTC_CR_OSEL_SHIFT) /* 01: Alarm A output enabled */
+# define RTC_CR_OSEL_ALRMB (0x2 << RTC_CR_OSEL_SHIFT) /* 10: Alarm B output enabled */
+# define RTC_CR_OSEL_WUT (0x3 << RTC_CR_OSEL_SHIFT) /* 11: Wakeup output enabled */
+
+#define RTC_CR_COE (1 << 23) /* Bit 23: Calibration output enable */
+#define RTC_CR_ITSE (1 << 24) /* Bit 24: Timestamp on internal event enable */
+
+/* RTC initialization and status register */
+
+#define RTC_ISR_ALRAWF (1 << 0) /* Bit 0: Alarm A write flag */
+#define RTC_ISR_ALRBWF (1 << 1) /* Bit 1: Alarm B write flag */
+#define RTC_ISR_WUTWF (1 << 2) /* Bit 2: Wakeup timer write flag */
+#define RTC_ISR_SHPF (1 << 3) /* Bit 3: Shift operation pending */
+#define RTC_ISR_INITS (1 << 4) /* Bit 4: Initialization status flag */
+#define RTC_ISR_RSF (1 << 5) /* Bit 5: Registers synchronization flag */
+#define RTC_ISR_INITF (1 << 6) /* Bit 6: Initialization flag */
+#define RTC_ISR_INIT (1 << 7) /* Bit 7: Initialization mode */
+#define RTC_ISR_ALRAF (1 << 8) /* Bit 8: Alarm A flag */
+#define RTC_ISR_ALRBF (1 << 9) /* Bit 9: Alarm B flag */
+#define RTC_ISR_WUTF (1 << 10) /* Bit 10: Wakeup timer flag */
+#define RTC_ISR_TSF (1 << 11) /* Bit 11: Time-stamp flag */
+#define RTC_ISR_TSOVF (1 << 12) /* Bit 12: Timestamp overflow flag */
+#define RTC_ISR_TAMP1F (1 << 13) /* Bit 13: Tamper 1 detection flag */
+#define RTC_ISR_TAMP2F (1 << 14) /* Bit 14: Tamper 2 detection flag */
+#define RTC_ISR_TAMP3F (1 << 15) /* Bit 15: Tamper 3 detection flag */
+#define RTC_ISR_RECALPF (1 << 16) /* Bit 16: Recalibration pending flag */
+#define RTC_ISR_ITSF (1 << 17) /* Bit 17: Internal time-stamp flag */
+#define RTC_ISR_ALLFLAGS (0x0003ffff)
+
+/* RTC prescaler register */
+
+#define RTC_PRER_PREDIV_S_SHIFT (0) /* Bits 0-14: Synchronous prescaler factor */
+#define RTC_PRER_PREDIV_S_MASK (0x7fff << RTC_PRER_PREDIV_S_SHIFT)
+#define RTC_PRER_PREDIV_A_SHIFT (16) /* Bits 16-22: Asynchronous prescaler factor */
+#define RTC_PRER_PREDIV_A_MASK (0x7f << RTC_PRER_PREDIV_A_SHIFT)
+
+/* RTC wakeup timer register */
+
+#define RTC_WUTR_SHIFT (0) /* Bits 15:0 Wakeup auto-reload value bits */
+#define RTC_WUTR_MASK (0xffff << RTC_WUTR_SHIFT)
+
+/* RTC alarm A/B registers */
+
+#define RTC_ALRMR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format. */
+#define RTC_ALRMR_SU_MASK (0xf << RTC_ALRMR_SU_SHIFT)
+#define RTC_ALRMR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format. */
+#define RTC_ALRMR_ST_MASK (0x7 << RTC_ALRMR_ST_SHIFT)
+#define RTC_ALRMR_MSK1 (1 << 7) /* Bit 7: Alarm A/B seconds mask */
+#define RTC_ALRMR_MNU_SHIFT (8) /* Bits 8-11: Minute units in BCD format. */
+#define RTC_ALRMR_MNU_MASK (0xf << RTC_ALRMR_MNU_SHIFT)
+#define RTC_ALRMR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format. */
+#define RTC_ALRMR_MNT_MASK (0x7 << RTC_ALRMR_MNT_SHIFT)
+#define RTC_ALRMR_MSK2 (1 << 15) /* Bit 15: Alarm A/B minutes mask */
+#define RTC_ALRMR_HU_SHIFT (16) /* Bits 16-19: Hour units in BCD format. */
+#define RTC_ALRMR_HU_MASK (15 << RTC_ALRMR_HU_SHIFT)
+#define RTC_ALRMR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format. */
+#define RTC_ALRMR_HT_MASK (0x3 << RTC_ALRMR_HT_SHIFT)
+#define RTC_ALRMR_PM (1 << 22) /* Bit 22: AM/PM notation */
+#define RTC_ALRMR_MSK3 (1 << 23) /* Bit 23: Alarm A/B hours mask */
+#define RTC_ALRMR_DU_SHIFT (24) /* Bits 24-27: Date units or day in BCD format. */
+#define RTC_ALRMR_DU_MASK (0xf << RTC_ALRMR_DU_SHIFT)
+#define RTC_ALRMR_DT_SHIFT (28) /* Bits 28-29: Date tens in BCD format. */
+#define RTC_ALRMR_DT_MASK (0x3 << RTC_ALRMR_DT_SHIFT)
+#define RTC_ALRMR_WDSEL (1 << 30) /* Bit 30: Week day selection */
+#define RTC_ALRMR_MSK4 (1 << 31) /* Bit 31: Alarm A/B date mask */
+
+/* RTC write protection register */
+
+#define RTC_WPR_KEY_SHIFT (0) /* Bits 0-7: Write protection key */
+#define RTC_WPR_KEY_MASK (0xff << RTC_WPR_KEY_SHIFT)
+# define RTC_WPR_KEY1 (0xca << RTC_WPR_KEY_SHIFT)
+# define RTC_WPR_KEY2 (0x53 << RTC_WPR_KEY_SHIFT)
+
+/* RTC sub second register */
+
+#define RTC_SSR_SHIFT (0) /* Bits 0-15: Sub second value */
+#define RTC_SSR_MASK (0xffff << RTC_SSR_SHIFT)
+
+/* RTC shift control register */
+
+#define RTC_SHIFTR_SUBFS_SHIFT (0) /* Bits 0-14: Subtract a fraction of a second */
+#define RTC_SHIFTR_SUBFS_MASK (0x7fff << RTC_SHIFTR_SUBFS_SHIFT)
+#define RTC_SHIFTR_ADD1S (1 << 31) /* Bit 31: Add one second */
+
+/* RTC time-stamp time register */
+
+#define RTC_TSTR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format. */
+#define RTC_TSTR_SU_MASK (0xf << RTC_TSTR_SU_SHIFT)
+#define RTC_TSTR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format. */
+#define RTC_TSTR_ST_MASK (0x7 << RTC_TSTR_ST_SHIFT)
+#define RTC_TSTR_MNU_SHIFT (8) /* Bits 8-11: Minute units in BCD format. */
+#define RTC_TSTR_MNU_MASK (0xf << RTC_TSTR_MNU_SHIFT)
+#define RTC_TSTR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format. */
+#define RTC_TSTR_MNT_MASK (0x7 << RTC_TSTR_MNT_SHIFT)
+#define RTC_TSTR_HU_SHIFT (16) /* Bits 16-19: Hour units in BCD format. */
+#define RTC_TSTR_HU_MASK (0xf << RTC_TSTR_HU_SHIFT)
+#define RTC_TSTR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format. */
+#define RTC_TSTR_HT_MASK (0x3 << RTC_TSTR_HT_SHIFT)
+#define RTC_TSTR_PM (1 << 22) /* Bit 22: AM/PM notation */
+
+/* RTC time-stamp date register */
+
+#define RTC_TSDR_DU_SHIFT (0) /* Bit 0-3: Date units in BCD format */
+#define RTC_TSDR_DU_MASK (0xf << RTC_TSDR_DU_SHIFT)
+#define RTC_TSDR_DT_SHIFT (4) /* Bits 4-5: Date tens in BCD format */
+#define RTC_TSDR_DT_MASK (0x3 << RTC_TSDR_DT_SHIFT)
+#define RTC_TSDR_MU_SHIFT (8) /* Bits 8-11: Month units in BCD format */
+#define RTC_TSDR_MU_MASK (0xf << RTC_TSDR_MU_SHIFT)
+#define RTC_TSDR_MT (1 << 12) /* Bit 12: Month tens in BCD format */
+#define RTC_TSDR_WDU_SHIFT (13) /* Bits 13-15: Week day units */
+#define RTC_TSDR_WDU_MASK (0x7 << RTC_TSDR_WDU_SHIFT)
+
+/* RTC time-stamp sub second register */
+
+#define RTC_TSSSR_SHIFT (0) /* Bits 0-15: Sub second value */
+#define RTC_TSSSR_MASK (0xffff << RTC_TSSSR_SHIFT)
+
+/* RTC calibration register */
+
+#define RTC_CALR_CALM_SHIFT (0) /* Bits 0-8: Calibration minus */
+#define RTC_CALR_CALM_MASK (0x1ff << RTC_CALR_CALM_SHIFT)
+#define RTC_CALR_CALW16 (1 << 13) /* Bit 13: Use a 16-second calibration cycle period */
+#define RTC_CALR_CALW8 (1 << 14) /* Bit 14: Use an 8-second calibration cycle period */
+#define RTC_CALR_CALP (1 << 15) /* Bit 15: Increase frequency of RTC by 488.5 ppm */
+
+/* RTC tamper configuration register */
+
+#define RTC_TAMPCR_TAMP1E (1 << 0) /* Bit 0: Tamper 1 input detection enable */
+#define RTC_TAMPCR_TAMP1TRG (1 << 1) /* Bit 1: Active level for Tamper 1 input */
+#define RTC_TAMPCR_TAMPIE (1 << 2) /* Bit 2: Tamper interrupt enable */
+#define RTC_TAMPCR_TAMP2E (1 << 3) /* Bit 3: Tamper 2 detection enable */
+#define RTC_TAMPCR_TAMP2TRG (1 << 4) /* Bit 4: Active level for Tamper 2 input */
+#define RTC_TAMPCR_TAMP3E (1 << 5) /* Bit 5: Tamper 3 detection enable */
+#define RTC_TAMPCR_TAMP3TRG (1 << 6) /* Bit 6: Active level for Tamper 3 input */
+#define RTC_TAMPCR_TAMPTS (1 << 7) /* Bit 7: Activate timestamp on tamper detection event */
+#define RTC_TAMPCR_TAMPFREQ_SHIFT (8) /* Bits 8-10: Tamper sampling frequency */
+#define RTC_TAMPCR_TAMPFREQ_MASK (0x7 << RTC_TAMPCR_TAMPFREQ_SHIFT)
+# define RTC_TAMPCR_TAMPFREQ_d32768 (0x0 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 32768 (1 Hz) */
+# define RTC_TAMPCR_TAMPFREQ_d16384 (0x1 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 16384 (2 Hz) */
+# define RTC_TAMPCR_TAMPFREQ_d8192 (0x2 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 8192 (4 Hz) */
+# define RTC_TAMPCR_TAMPFREQ_d4096 (0x3 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 4096 (8 Hz) */
+# define RTC_TAMPCR_TAMPFREQ_d2048 (0x4 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 2048 (16 Hz) */
+# define RTC_TAMPCR_TAMPFREQ_d1024 (0x5 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 1024 (32 Hz) */
+# define RTC_TAMPCR_TAMPFREQ_d512 (0x6 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 512 (64 Hz) */
+# define RTC_TAMPCR_TAMPFREQ_d256 (0x7 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 256 (128 Hz) */
+
+#define RTC_TAMPCR_TAMPFLT_SHIFT (11) /* Bits 11-12: RTC_TAMPx filter count */
+#define RTC_TAMPCR_TAMPFLT_MASK (0x3 << RTC_TAMPCR_TAMPFLT_SHIFT)
+
+#define RTC_TAMPCR_TAMPPRCH_SHIFT (13) /* Bits 13-14: RTC_TAMPx precharge duration */
+#define RTC_TAMPCR_TAMPPRCH_MASK (0x3 << RTC_TAMPCR_TAMPPRCH_SHIFT)
+# define RTC_TAMPCR_TAMPPRCH_1CYCLE (0x0 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 1 RTCCLK cycle */
+# define RTC_TAMPCR_TAMPPRCH_2CYCLES (0x1 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 2 RTCCLK cycles */
+# define RTC_TAMPCR_TAMPPRCH_4CYCLES (0x2 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 4 RTCCLK cycles */
+# define RTC_TAMPCR_TAMPPRCH_5CYCLES (0x3 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 8 RTCCLK cycles */
+
+#define RTC_TAMPCR_TAMPPUDIS (1 << 15) /* Bit 15: Tampers pull-up disable */
+#define RTC_TAMPCR_TAMP1IE (1 << 16) /* Bit 16: Tamper 1 interrupt enable */
+#define RTC_TAMPCR_TAMP1NOERASE (1 << 17) /* Bit 17: Tamper 1 no erase */
+#define RTC_TAMPCR_TAMP1MF (1 << 18) /* Bit 18: Tamper 1 mask flag */
+#define RTC_TAMPCR_TAMP2IE (1 << 19) /* Bit 19: Tamper 2 interrupt enable */
+#define RTC_TAMPCR_TAMP2NOERASE (1 << 20) /* Bit 20: Tamper 2 no erase */
+#define RTC_TAMPCR_TAMP2MF (1 << 21) /* Bit 21: Tamper 2 mask flag */
+#define RTC_TAMPCR_TAMP3IE (1 << 22) /* Bit 22: Tamper 3 interrupt enable */
+#define RTC_TAMPCR_TAMP3NOERASE (1 << 23) /* Bit 23: Tamper 3 no erase */
+#define RTC_TAMPCR_TAMP3MF (1 << 24) /* Bit 24: Tamper 3 mask flag */
+
+/* RTC alarm A/B sub second register */
+
+#define RTC_ALRMSSR_SS_SHIFT (0) /* Bits 0-14: Sub second value */
+#define RTC_ALRMSSR_SS_MASK (0x7fff << RTC_ALRMSSR_SS_SHIFT)
+#define RTC_ALRMSSR_MASKSS_SHIFT (24) /* Bits 24-27: Mask the most-significant bits starting at this bit */
+#define RTC_ALRMSSR_MASKSS_MASK (0xf << RTC_ALRMSSR_MASKSS_SHIFT)
+
+/* RTC option register */
+
+#define RTC_OR_ALARMTYPE (1 << 0) /* Bit 0: RTC alarm output type on PC13 (PP/OD) */
+# define RTC_OR_ALARMTYPE_OD (0 << 0) /* 0: Open-drain output when mapped to PC13 */
+# define RTC_OR_ALARMTYPE_PP (1 << 0) /* 1: Push-pull output when mapped to PC13 */
+#define RTC_OR_OUTRMP (1 << 1) /* Bit 1: Output remap */
+# define RTC_OR_OUTRMP_PC13 (0 << 1) /* 0: Alarm/calibration output on PC13 */
+# define RTC_OR_OUTRMP_PB2PC13 (1 << 1) /* 1: Alarm/calibration output on PB2 or PC13 */
+
+#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_RTCC_H */
diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_spi.h b/arch/arm/src/stm32wb/hardware/stm32wb_spi.h
new file mode 100644
index 0000000000..13469262c1
--- /dev/null
+++ b/arch/arm/src/stm32wb/hardware/stm32wb_spi.h
@@ -0,0 +1,151 @@
+/****************************************************************************
+ * arch/arm/src/stm32wb/hardware/stm32wb_spi.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_SPI_H
+#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_SPI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Maximum allowed speed as per specifications for all SPIs */
+
+#define STM32WB_SPI_CLK_MAX 32000000ul
+
+/* Register Offsets *********************************************************/
+
+#define STM32WB_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */
+#define STM32WB_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */
+#define STM32WB_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */
+#define STM32WB_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */
+#define STM32WB_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */
+#define STM32WB_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */
+#define STM32WB_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
+
+/* Register Addresses *******************************************************/
+
+#define STM32WB_SPI1_CR1 (STM32WB_SPI1_BASE + STM32WB_SPI_CR1_OFFSET)
+#define STM32WB_SPI1_CR2 (STM32WB_SPI1_BASE + STM32WB_SPI_CR2_OFFSET)
+#define STM32WB_SPI1_SR (STM32WB_SPI1_BASE + STM32WB_SPI_SR_OFFSET)
+#define STM32WB_SPI1_DR (STM32WB_SPI1_BASE + STM32WB_SPI_DR_OFFSET)
+#define STM32WB_SPI1_CRCPR (STM32WB_SPI1_BASE + STM32WB_SPI_CRCPR_OFFSET)
+#define STM32WB_SPI1_RXCRCR (STM32WB_SPI1_BASE + STM32WB_SPI_RXCRCR_OFFSET)
+#define STM32WB_SPI1_TXCRCR (STM32WB_SPI1_BASE + STM32WB_SPI_TXCRCR_OFFSET)
+
+#if CONFIG_STM32WB_HAVE_SPI2
+# define STM32WB_SPI2_CR1 (STM32WB_SPI2_BASE + STM32WB_SPI_CR1_OFFSET)
+# define STM32WB_SPI2_CR2 (STM32WB_SPI2_BASE + STM32WB_SPI_CR2_OFFSET)
+# define STM32WB_SPI2_SR (STM32WB_SPI2_BASE + STM32WB_SPI_SR_OFFSET)
+# define STM32WB_SPI2_DR (STM32WB_SPI2_BASE + STM32WB_SPI_DR_OFFSET)
+# define STM32WB_SPI2_CRCPR (STM32WB_SPI2_BASE + STM32WB_SPI_CRCPR_OFFSET)
+# define STM32WB_SPI2_RXCRCR (STM32WB_SPI2_BASE + STM32WB_SPI_RXCRCR_OFFSET)
+# define STM32WB_SPI2_TXCRCR (STM32WB_SPI2_BASE + STM32WB_SPI_TXCRCR_OFFSET)
+#endif
+
+/* Register Bitfield Definitions ********************************************/
+
+/* SPI Control Register 1 */
+
+#define SPI_CR1_CPHA (1 << 0) /* Bit 0: Clock Phase */
+#define SPI_CR1_CPOL (1 << 1) /* Bit 1: Clock Polarity */
+#define SPI_CR1_MSTR (1 << 2) /* Bit 2: Master Selection */
+#define SPI_CR1_BR_SHIFT (3) /* Bits 5:3 Baud Rate Control */
+#define SPI_CR1_BR_MASK (0x7 << SPI_CR1_BR_SHIFT)
+# define SPI_CR1_FPCLCKd2 (0x0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */
+# define SPI_CR1_FPCLCKd4 (0x1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */
+# define SPI_CR1_FPCLCKd8 (0x2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */
+# define SPI_CR1_FPCLCKd16 (0x3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */
+# define SPI_CR1_FPCLCKd32 (0x4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */
+# define SPI_CR1_FPCLCKd64 (0x5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */
+# define SPI_CR1_FPCLCKd128 (0x6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */
+# define SPI_CR1_FPCLCKd256 (0x7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */
+
+#define SPI_CR1_SPE (1 << 6) /* Bit 6: SPI Enable */
+#define SPI_CR1_LSBFIRST (1 << 7) /* Bit 7: Frame Format */
+#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */
+#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */
+#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */
+#define SPI_CR1_CRCL (1 << 11) /* Bit 11: CRC length */
+#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */
+#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE (1 << 15) /* Bit 15: Bidirectional data mode enable */
+
+/* SPI Control Register 2 */
+
+#define SPI_CR2_RXDMAEN (1 << 0) /* Bit 0: Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN (1 << 1) /* Bit 1: Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */
+#define SPI_CR2_NSSP (1 << 3) /* Bit 3: NSS pulse management */
+#define SPI_CR2_FRF (1 << 4) /* Bit 4: Frame format */
+#define SPI_CR2_ERRIE (1 << 5) /* Bit 5: Error interrupt enable */
+#define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */
+#define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */
+#define SPI_CR2_DS_SHIFT (8) /* Bits 8-11: Data size */
+#define SPI_CR2_DS_MASK (0xf << SPI_CR2_DS_SHIFT)
+# define SPI_CR2_DS_VAL(bits) (((bits) - 1) << SPI_CR2_DS_SHIFT)
+# define SPI_CR2_DS_4BIT SPI_CR2_DS_VAL(4)
+# define SPI_CR2_DS_5BIT SPI_CR2_DS_VAL(5)
+# define SPI_CR2_DS_6BIT SPI_CR2_DS_VAL(6)
+# define SPI_CR2_DS_7BIT SPI_CR2_DS_VAL(7)
+# define SPI_CR2_DS_8BIT SPI_CR2_DS_VAL(8)
+# define SPI_CR2_DS_9BIT SPI_CR2_DS_VAL(9)
+# define SPI_CR2_DS_10BIT SPI_CR2_DS_VAL(10)
+# define SPI_CR2_DS_11BIT SPI_CR2_DS_VAL(11)
+# define SPI_CR2_DS_12BIT SPI_CR2_DS_VAL(12)
+# define SPI_CR2_DS_13BIT SPI_CR2_DS_VAL(13)
+# define SPI_CR2_DS_14BIT SPI_CR2_DS_VAL(14)
+# define SPI_CR2_DS_15BIT SPI_CR2_DS_VAL(15)
+# define SPI_CR2_DS_16BIT SPI_CR2_DS_VAL(16)
+#define SPI_CR2_FRXTH (1 << 12) /* Bit 12: FIFO reception threshold */
+#define SPI_CR2_LDMARX (1 << 13) /* Bit 13: Last DMA transfer for receptione */
+#define SPI_CR2_LDMATX (1 << 14) /* Bit 14: Last DMA transfer for transmission */
+
+/* SPI status register */
+
+#define SPI_SR_RXNE (1 << 0) /* Bit 0: Receive buffer not empty */
+#define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */
+#define SPI_SR_CRCERR (1 << 4) /* Bit 4: CRC error flag */
+#define SPI_SR_MODF (1 << 5) /* Bit 5: Mode fault */
+#define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */
+#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */
+#define SPI_SR_FRE (1 << 8) /* Bit 8: Frame format error */
+#define SPI_SR_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */
+#define SPI_SR_FRLVL_MASK (0x3 << SPI_SR_FRLVL_SHIFT)
+# define SPI_SR_FRLVL_EMPTY (0x0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */
+# define SPI_SR_FRLVL_QUARTER (0x1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */
+# define SPI_SR_FRLVL_HALF (0x2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */
+# define SPI_SR_FRLVL_FULL (0x3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */
+
+#define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */
+#define SPI_SR_FTLVL_MASK (0x3 << SPI_SR_FTLVL_SHIFT)
+# define SPI_SR_FTLVL_EMPTY (0x0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */
+# define SPI_SR_FTLVL_QUARTER (0x1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */
+# define SPI_SR_FTLVL_HALF (0x2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */
+# define SPI_SR_FTLVL_FULL (0x3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */
+
+#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_SPI_H */
diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_syscfg.h b/arch/arm/src/stm32wb/hardware/stm32wb_syscfg.h
new file mode 100644
index 0000000000..64a5eb7b73
--- /dev/null
+++ b/arch/arm/src/stm32wb/hardware/stm32wb_syscfg.h
@@ -0,0 +1,227 @@
+/****************************************************************************
+ * arch/arm/src/stm32wb/hardware/stm32wb_syscfg.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_SYSCFG_H
+#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_SYSCFG_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define STM32WB_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
+#define STM32WB_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */
+
+#define STM32WB_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x0c)) /* Pin p = 0..15 */
+
+#define STM32WB_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
+#define STM32WB_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
+#define STM32WB_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */
+#define STM32WB_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */
+
+#define STM32WB_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */
+#define STM32WB_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */
+#define STM32WB_SYSCFG_SWPR1_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register 1 */
+#define STM32WB_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */
+#define STM32WB_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */
+
+#define STM32WB_SYSCFG_IMR1_OFFSET 0x0100 /* SYSCFG Interrupt mask register 1 */
+#define STM32WB_SYSCFG_IMR2_OFFSET 0x0104 /* SYSCFG Interrupt mask register 2 */
+#define STM32WB_SYSCFG_C2IMR1_OFFSET 0x0108 /* SYSCFG CPU2 Interrupt mask register 1 */
+#define STM32WB_SYSCFG_C2IMR2_OFFSET 0x010c /* SYSCFG CPU2 Interrupt mask register 2 */
+#define STM32WB_SYSCFG_SIPCR_OFFSET 0x0110 /* SYSCFG Secure IP control register */
+
+/* Register Addresses *******************************************************/
+
+#define STM32WB_SYSCFG_MEMRMP (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_MEMRMP_OFFSET)
+#define STM32WB_SYSCFG_CFGR1 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_CFGR1_OFFSET)
+#define STM32WB_SYSCFG_EXTICR(p) (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_EXTICR_OFFSET(p))
+#define STM32WB_SYSCFG_EXTICR1 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_EXTICR1_OFFSET)
+#define STM32WB_SYSCFG_EXTICR2 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_EXTICR2_OFFSET)
+#define STM32WB_SYSCFG_EXTICR3 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_EXTICR3_OFFSET)
+#define STM32WB_SYSCFG_EXTICR4 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_EXTICR4_OFFSET)
+#define STM32WB_SYSCFG_SCSR (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_SCSR_OFFSET)
+#define STM32WB_SYSCFG_CFGR2 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_CFGR2_OFFSET)
+#define STM32WB_SYSCFG_SWPR1 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_SWPR1_OFFSET)
+#define STM32WB_SYSCFG_SKR (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_SKR_OFFSET)
+#define STM32WB_SYSCFG_SWPR2 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_SWPR2_OFFSET)
+
+/* Register Bitfield Definitions ********************************************/
+
+/* SYSCFG memory remap register */
+
+#define SYSCFG_MEMRMP_SHIFT (0) /* Bits 2-0: Memory mapping selection */
+#define SYSCFG_MEMRMP_MASK (0x7 << SYSCFG_MEMRMP_SHIFT)
+# define SYSCFG_MEMRMP_FLASH (0x0 << SYSCFG_MEMRMP_SHIFT) /* 000: Main Flash memory mapped at 0x00000000 */
+# define SYSCFG_MEMRMP_SYSTEM (0x1 << SYSCFG_MEMRMP_SHIFT) /* 001: System Flash memory mapped at 0x00000000 */
+# define SYSCFG_MEMRMP_SRAM (0x3 << SYSCFG_MEMRMP_SHIFT) /* 011: SRAM1 mapped at 0x00000000 */
+# define SYSCFG_MEMRMP_QSPI (0x6 << SYSCFG_MEMRMP_SHIFT) /* 110: QSPI memory mapped at 0x00000000 */
+
+/* SYSCFG configuration register 1 */
+
+#define SYSCFG_CFGR1_BOOSTEN (1 << 8) /* Bit 8: I/O analog switch voltage booster enable */
+#define SYSCFG_CFGR1_I2C_PB6_FMP (1 << 16) /* Bit 16: Fast-mode Plus (Fm+) driving capability activation on PB6 */
+#define SYSCFG_CFGR1_I2C_PB7_FMP (1 << 17) /* Bit 17: Fast-mode Plus (Fm+) driving capability activation on PB7 */
+#define SYSCFG_CFGR1_I2C_PB8_FMP (1 << 18) /* Bit 18: Fast-mode Plus (Fm+) driving capability activation on PB8 */
+#define SYSCFG_CFGR1_I2C_PB9_FMP (1 << 19) /* Bit 19: Fast-mode Plus (Fm+) driving capability activation on PB9 */
+#define SYSCFG_CFGR1_I2C1_FMP (1 << 20) /* Bit 20: I2C1 Fast-mode Plus (Fm+) driving capability activation */
+#define SYSCFG_CFGR1_I2C3_FMP (1 << 22) /* Bit 22: I2C3 Fast-mode Plus (Fm+) driving capability activation */
+#define SYSCFG_CFGR1_FPU_IE0 (1 << 26) /* Bit 26: FPU Invalid operation interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE1 (1 << 27) /* Bit 27: FPU Divide-by-zero interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE2 (1 << 28) /* Bit 28: FPU Underflow interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE3 (1 << 29) /* Bit 29: FPU Overflow interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE4 (1 << 30) /* Bit 30: FPU Input denormal interrupt enable */
+#define SYSCFG_CFGR1_FPU_IE5 (1 << 31) /* Bit 31: FPU Inexact interrupt enable */
+
+/* SYSCFG external interrupt configuration register 1-4 */
+
+#define SYSCFG_EXTICR_PORTA (0x0) /* 000: PA[x] pin */
+#define SYSCFG_EXTICR_PORTB (0x1) /* 001: PB[x] pin */
+#define SYSCFG_EXTICR_PORTC (0x2) /* 010: PC[x] pin */
+#define SYSCFG_EXTICR_PORTD (0x3) /* 011: PD[x] pin */
+#define SYSCFG_EXTICR_PORTE (0x4) /* 100: PE[x] pin */
+#define SYSCFG_EXTICR_PORTH (0x7) /* 111: PH[x] pin */
+
+#define SYSCFG_EXTICR_PORT_MASK (0x7)
+#define SYSCFG_EXTICR_EXTI_SHIFT(g) (((g) & 0x3) << 2)
+#define SYSCFG_EXTICR_EXTI_MASK(g) (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g)))
+
+#define SYSCFG_EXTICR1_EXTI0_SHIFT (0) /* Bits 0-2: EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI0_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT)
+#define SYSCFG_EXTICR1_EXTI1_SHIFT (4) /* Bits 4-6: EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI1_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT)
+#define SYSCFG_EXTICR1_EXTI2_SHIFT (8) /* Bits 8-10: EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI2_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT)
+#define SYSCFG_EXTICR1_EXTI3_SHIFT (12) /* Bits 12-14: EXTI 3 configuration */
+#define SYSCFG_EXTICR1_EXTI3_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT)
+
+#define SYSCFG_EXTICR2_EXTI4_SHIFT (0) /* Bits 0-2: EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI4_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT)
+#define SYSCFG_EXTICR2_EXTI5_SHIFT (4) /* Bits 4-6: EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI5_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT)
+#define SYSCFG_EXTICR2_EXTI6_SHIFT (8) /* Bits 8-10: EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI6_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT)
+#define SYSCFG_EXTICR2_EXTI7_SHIFT (12) /* Bits 12-14: EXTI 7 configuration */
+#define SYSCFG_EXTICR2_EXTI7_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT)
+
+#define SYSCFG_EXTICR3_EXTI8_SHIFT (0) /* Bits 0-2: EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI8_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT)
+#define SYSCFG_EXTICR3_EXTI9_SHIFT (4) /* Bits 4-6: EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI9_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT)
+#define SYSCFG_EXTICR3_EXTI10_SHIFT (8) /* Bits 8-10: EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI10_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT)
+#define SYSCFG_EXTICR3_EXTI11_SHIFT (12) /* Bits 12-14: EXTI 11 configuration */
+#define SYSCFG_EXTICR3_EXTI11_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT)
+
+#define SYSCFG_EXTICR4_EXTI12_SHIFT (0) /* Bits 0-2: EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI12_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT)
+#define SYSCFG_EXTICR4_EXTI13_SHIFT (4) /* Bits 4-6: EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI13_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT)
+#define SYSCFG_EXTICR4_EXTI14_SHIFT (8) /* Bits 8-10: EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI14_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT)
+#define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-14: EXTI 15 configuration */
+#define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT)
+
+/* SYSCFG SRAM2 control and status register */
+
+#define SYSCFG_SCSR_SRAM2ER (1 << 0) /* Bit 0: SRAM2 and PKA RAM Erase */
+#define SYSCFG_SCSR_SRAM2BSY (1 << 1) /* Bit 1: SRAM2 and PKA RAM busy by erase operation */
+#define SYSCFG_SCSR_C2RFD (1 << 31) /* Bit 31: CPU2 SRAM fetch disable */
+
+/* SYSCFG configuration register 2 */
+
+#define SYSCFG_CFGR2_CLL (1 << 0) /* Bit 0: LOCKUP (Hardfault) output enable */
+#define SYSCFG_CFGR2_SPL (1 << 1) /* Bit 1: SRAM2 parity lock enable */
+#define SYSCFG_CFGR2_PVDL (1 << 2) /* Bit 2: PVD lock enable */
+#define SYSCFG_CFGR2_ECCL (1 << 3) /* Bit 3: ECC lock enable */
+#define SYSCFG_CFGR2_SPF (1 << 8) /* Bit 8: SRAM2 parity error flag */
+
+/* SYSCFG SRAM2 write protection register 1 */
+
+#define SYSCFG_SWPR1_PWP(x) (1 << (x)) /* Bits 0-31: SRAM2 1Kb page x = 0..31 write protection */
+
+/* SYSCFG SRAM2 key register */
+
+#define SYSCFG_SKR_SHIFT (0)
+#define SYSCFG_SKR_MASK (0xff << SYSCFG_SKR_SHIFT)
+#define SYSCFG_SKR_KEY1 0xca
+#define SYSCFG_SKR_KEY2 0x53
+
+/* SYSCFG SRAM2 write protection register 2 */
+
+#define SYSCFG_SWPR2_PWP(x) (1 << ((x) - 32)) /* Bits 0-31: SRAM2 1Kb page x = 32..63 write protection */
+
+/* SYSCFG Interrupt mask register 1 */
+
+#define SYSCFG_IMR1_EXTIIM(n) (1 << ((n) + 16)) /* EXTI[n] interrupt mask, n = 5..15 */
+
+#define SYSCFG_IMR1_TIM1IM (1 << 13) /* Bit 13: TIM1 interrupt mask */
+#define SYSCFG_IMR1_TIM16IM (1 << 14) /* Bit 14: TIM16 interrupt mask */
+#define SYSCFG_IMR1_TIM17IM (1 << 15) /* Bit 15: TIM17 interrupt mask */
+
+/* SYSCFG Interrupt mask register 2 */
+
+#define SYSCFG_IMR2_PVM1IM (1 << 16) /* Bit 16: PVM1 interrupt mask */
+#define SYSCFG_IMR2_PVM3IM (1 << 18) /* Bit 18: PVM3 interrupt mask */
+#define SYSCFG_IMR2_PVDIM (1 << 20) /* Bit 20: PVD interrupt mask */
+
+/* SYSCFG CPU2 Interrupt mask register 1 */
+
+#define SYSCFG_C2IMR1_RTCSTLSECSSIM (1 << 0) /* Bit 0: CPU2 RTC, STAMP, TAMP, LSECSS interrupt mask */
+#define SYSCFG_C2IMR1_RTCWKUPIM (1 << 3) /* Bit 3: CPU2 RTC Wakeup interrupt mask */
+#define SYSCFG_C2IMR1_RTCALRMIM (1 << 4) /* Bit 4: CPU2 RTC Alarm interrupt mask */
+#define SYSCFG_C2IMR1_RCCIM (1 << 5) /* Bit 5: CPU2 RCC interrupt mask */
+#define SYSCFG_C2IMR1_FLASHIM (1 << 6) /* Bit 6: CPU2 FLASH interrupt mask */
+#define SYSCFG_C2IMR1_PKAIM (1 << 8) /* Bit 8: CPU2 PKA interrupt mask */
+#define SYSCFG_C2IMR1_RNGIM (1 << 9) /* Bit 9: CPU2 RNG interrupt mask */
+#define SYSCFG_C2IMR1_AES1IM (1 << 10) /* Bit 10: CPU2 AES1 interrupt mask */
+#define SYSCFG_C2IMR1_COMPIM (1 << 11) /* Bit 11: CPU2 COMP interrupt mask */
+#define SYSCFG_C2IMR1_ADCIM (1 << 12) /* Bit 12: CPU2 ADC interrupt mask */
+
+#define SYSCFG_C2IMR1_EXTIIM(n) (1 << ((n) + 16)) /* CPU2 EXTI[n] interrupt mask, n = 0..15 */
+
+/* SYSCFG CPU2 Interrupt mask register 2 */
+
+#define SYSCFG_C2IMR2_DMA1IM(n) (1 << ((n) - 1)) /* CPU2 DMA1[n] interrupt mask, n = 1..7 */
+
+#define SYSCFG_C2IMR2_DMA2IM(n) (1 << ((n) + 7)) /* CPU2 DMA2[n] interrupt mask, n = 1..7 */
+
+#define SYSCFG_C2IMR2_DMAMUX1IM (1 << 15) /* Bit 15: CPU2 DMAMUX1 interrupt mask */
+#define SYSCFG_C2IMR2_PVM1IM (1 << 16) /* Bit 16: CPU2 PVM1 interrupt mask */
+#define SYSCFG_C2IMR2_PVM3IM (1 << 18) /* Bit 18: CPU2 PVM3 interrupt mask */
+#define SYSCFG_C2IMR2_PVDIM (1 << 20) /* Bit 20: CPU2 PVD interrupt mask */
+#define SYSCFG_C2IMR2_TSCIM (1 << 21) /* Bit 21: CPU2 TSC interrupt mask */
+#define SYSCFG_C2IMR2_LCDIM (1 << 22) /* Bit 22: CPU2 LCD interrupt mask */
+
+/* SYSCFG Secure IP control register */
+
+#define SYSCFG_SIPCR_SAES1 (1 << 0) /* Bit 0: AES1 KEY[7:0] Security enable */
+#define SYSCFG_SIPCR_SAES2 (1 << 1) /* Bit 1: AES2 Security enable */
+#define SYSCFG_SIPCR_SPKA (1 << 2) /* Bit 2: PKA Security enable */
+#define SYSCFG_SIPCR_SRNG (1 << 3) /* Bit 3: RNG Security enable */
+
+#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_SYSCFG_H */
diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_tim.h b/arch/arm/src/stm32wb/hardware/stm32wb_tim.h
new file mode 100644
index 0000000000..385f1dd170
--- /dev/null
+++ b/arch/arm/src/stm32wb/hardware/stm32wb_tim.h
@@ -0,0 +1,1385 @@
+/****************************************************************************
+ * arch/arm/src/stm32wb/hardware/stm32wb_tim.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_TIM_H
+#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_TIM_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define STM32WB_TIM_CR1_OFFSET 0x0000 /* Control register 1 */
+#define STM32WB_TIM_CR2_OFFSET 0x0004 /* Control register 2 */
+#define STM32WB_TIM_SMCR_OFFSET 0x0008 /* Slave mode control register (TIM1, TIM2) */
+#define STM32WB_TIM_DIER_OFFSET 0x000c /* DMA / Interrupt enable register */
+#define STM32WB_TIM_SR_OFFSET 0x0010 /* Status register */
+#define STM32WB_TIM_EGR_OFFSET 0x0014 /* Event generation register */
+#define STM32WB_TIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 */
+#define STM32WB_TIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (TIM1, TIM2) */
+#define STM32WB_TIM_CCER_OFFSET 0x0020 /* Capture/compare enable register */
+#define STM32WB_TIM_CNT_OFFSET 0x0024 /* Counter */
+#define STM32WB_TIM_PSC_OFFSET 0x0028 /* Prescaler */
+#define STM32WB_TIM_ARR_OFFSET 0x002c /* Auto-reload register */
+#define STM32WB_TIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM1, TIM16/TIM17) */
+#define STM32WB_TIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 */
+#define STM32WB_TIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (TIM1, TIM2) */
+#define STM32WB_TIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (TIM1, TIM2) */
+#define STM32WB_TIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (TIM1, TIM2) */
+#define STM32WB_TIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM1, TIM16/17) */
+#define STM32WB_TIM_DCR_OFFSET 0x0048 /* DMA control register */
+#define STM32WB_TIM_DMAR_OFFSET 0x004c /* DMA address for burst mode */
+#define STM32WB_TIM_OR1_OFFSET 0x0050 /* Option register 1 */
+#define STM32WB_TIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (TIM1) */
+#define STM32WB_TIM_CCR5_OFFSET 0x0058 /* Capture/compare register 5 (TIM1) */
+#define STM32WB_TIM_CCR6_OFFSET 0x005C /* Capture/compare register 6 (TIM1) */
+#define STM32WB_TIM_AF1_OFFSET 0x0060 /* Alternate function register 1 */
+#define STM32WB_TIM_AF2_OFFSET 0x0064 /* Alternate function register 2 (TIM1) */
+#define STM32WB_TIM_TISEL_OFFSET 0x0068 /* Input selector register */
+
+/* Register Addresses *******************************************************/
+
+/* Advanced Timer TIM1 */
+
+#define STM32WB_TIM1_CR1 (STM32WB_TIM1_BASE + STM32WB_TIM_CR1_OFFSET)
+#define STM32WB_TIM1_CR2 (STM32WB_TIM1_BASE + STM32WB_TIM_CR2_OFFSET)
+#define STM32WB_TIM1_SMCR (STM32WB_TIM1_BASE + STM32WB_TIM_SMCR_OFFSET)
+#define STM32WB_TIM1_DIER (STM32WB_TIM1_BASE + STM32WB_TIM_DIER_OFFSET)
+#define STM32WB_TIM1_SR (STM32WB_TIM1_BASE + STM32WB_TIM_SR_OFFSET)
+#define STM32WB_TIM1_EGR (STM32WB_TIM1_BASE + STM32WB_TIM_EGR_OFFSET)
+#define STM32WB_TIM1_CCMR1 (STM32WB_TIM1_BASE + STM32WB_TIM_CCMR1_OFFSET)
+#define STM32WB_TIM1_CCMR2 (STM32WB_TIM1_BASE + STM32WB_TIM_CCMR2_OFFSET)
+#define STM32WB_TIM1_CCER (STM32WB_TIM1_BASE + STM32WB_TIM_CCER_OFFSET)
+#define STM32WB_TIM1_CNT (STM32WB_TIM1_BASE + STM32WB_TIM_CNT_OFFSET)
+#define STM32WB_TIM1_PSC (STM32WB_TIM1_BASE + STM32WB_TIM_PSC_OFFSET)
+#define STM32WB_TIM1_ARR (STM32WB_TIM1_BASE + STM32WB_TIM_ARR_OFFSET)
+#define STM32WB_TIM1_RCR (STM32WB_TIM1_BASE + STM32WB_TIM_RCR_OFFSET)
+#define STM32WB_TIM1_CCR1 (STM32WB_TIM1_BASE + STM32WB_TIM_CCR1_OFFSET)
+#define STM32WB_TIM1_CCR2 (STM32WB_TIM1_BASE + STM32WB_TIM_CCR2_OFFSET)
+#define STM32WB_TIM1_CCR3 (STM32WB_TIM1_BASE + STM32WB_TIM_CCR3_OFFSET)
+#define STM32WB_TIM1_CCR4 (STM32WB_TIM1_BASE + STM32WB_TIM_CCR4_OFFSET)
+#define STM32WB_TIM1_BDTR (STM32WB_TIM1_BASE + STM32WB_TIM_BDTR_OFFSET)
+#define STM32WB_TIM1_DCR (STM32WB_TIM1_BASE + STM32WB_TIM_DCR_OFFSET)
+#define STM32WB_TIM1_DMAR (STM32WB_TIM1_BASE + STM32WB_TIM_DMAR_OFFSET)
+#define STM32WB_TIM1_OR1 (STM32WB_TIM1_BASE + STM32WB_TIM_OR1_OFFSET)
+#define STM32WB_TIM1_CCMR3 (STM32WB_TIM1_BASE + STM32WB_TIM_CCMR3_OFFSET)
+#define STM32WB_TIM1_CCR5 (STM32WB_TIM1_BASE + STM32WB_TIM_CCR5_OFFSET)
+#define STM32WB_TIM1_CCR6 (STM32WB_TIM1_BASE + STM32WB_TIM_CCR6_OFFSET)
+#define STM32WB_TIM1_AF1 (STM32WB_TIM1_BASE + STM32WB_TIM_AF1_OFFSET)
+#define STM32WB_TIM1_AF2 (STM32WB_TIM1_BASE + STM32WB_TIM_AF2_OFFSET)
+#define STM32WB_TIM1_TISEL (STM32WB_TIM1_BASE + STM32WB_TIM_TISEL_OFFSET)
+
+/* General 32-bit Timer TIM2 */
+
+#define STM32WB_TIM2_CR1 (STM32WB_TIM2_BASE + STM32WB_TIM_CR1_OFFSET)
+#define STM32WB_TIM2_CR2 (STM32WB_TIM2_BASE + STM32WB_TIM_CR2_OFFSET)
+#define STM32WB_TIM2_SMCR (STM32WB_TIM2_BASE + STM32WB_TIM_SMCR_OFFSET)
+#define STM32WB_TIM2_DIER (STM32WB_TIM2_BASE + STM32WB_TIM_DIER_OFFSET)
+#define STM32WB_TIM2_SR (STM32WB_TIM2_BASE + STM32WB_TIM_SR_OFFSET)
+#define STM32WB_TIM2_EGR (STM32WB_TIM2_BASE + STM32WB_TIM_EGR_OFFSET)
+#define STM32WB_TIM2_CCMR1 (STM32WB_TIM2_BASE + STM32WB_TIM_CCMR1_OFFSET)
+#define STM32WB_TIM2_CCMR2 (STM32WB_TIM2_BASE + STM32WB_TIM_CCMR2_OFFSET)
+#define STM32WB_TIM2_CCER (STM32WB_TIM2_BASE + STM32WB_TIM_CCER_OFFSET)
+#define STM32WB_TIM2_CNT (STM32WB_TIM2_BASE + STM32WB_TIM_CNT_OFFSET)
+#define STM32WB_TIM2_PSC (STM32WB_TIM2_BASE + STM32WB_TIM_PSC_OFFSET)
+#define STM32WB_TIM2_ARR (STM32WB_TIM2_BASE + STM32WB_TIM_ARR_OFFSET)
+#define STM32WB_TIM2_CCR1 (STM32WB_TIM2_BASE + STM32WB_TIM_CCR1_OFFSET)
+#define STM32WB_TIM2_CCR2 (STM32WB_TIM2_BASE + STM32WB_TIM_CCR2_OFFSET)
+#define STM32WB_TIM2_CCR3 (STM32WB_TIM2_BASE + STM32WB_TIM_CCR3_OFFSET)
+#define STM32WB_TIM2_CCR4 (STM32WB_TIM2_BASE + STM32WB_TIM_CCR4_OFFSET)
+#define STM32WB_TIM2_DCR (STM32WB_TIM2_BASE + STM32WB_TIM_DCR_OFFSET)
+#define STM32WB_TIM2_DMAR (STM32WB_TIM2_BASE + STM32WB_TIM_DMAR_OFFSET)
+#define STM32WB_TIM2_OR1 (STM32WB_TIM2_BASE + STM32WB_TIM_OR1_OFFSET)
+#define STM32WB_TIM2_AF1 (STM32WB_TIM2_BASE + STM32WB_TIM_AF1_OFFSET)
+#define STM32WB_TIM2_TISEL (STM32WB_TIM2_BASE + STM32WB_TIM_TISEL_OFFSET)
+
+/* General Timers TIM16/TIM17 */
+
+#define STM32WB_TIM16_CR1 (STM32WB_TIM16_BASE + STM32WB_TIM_CR1_OFFSET)
+#define STM32WB_TIM16_CR2 (STM32WB_TIM16_BASE + STM32WB_TIM_CR2_OFFSET)
+#define STM32WB_TIM16_DIER (STM32WB_TIM16_BASE + STM32WB_TIM_DIER_OFFSET)
+#define STM32WB_TIM16_SR (STM32WB_TIM16_BASE + STM32WB_TIM_SR_OFFSET)
+#define STM32WB_TIM16_EGR (STM32WB_TIM16_BASE + STM32WB_TIM_EGR_OFFSET)
+#define STM32WB_TIM16_CCMR1 (STM32WB_TIM16_BASE + STM32WB_TIM_CCMR1_OFFSET)
+#define STM32WB_TIM16_CCER (STM32WB_TIM16_BASE + STM32WB_TIM_CCER_OFFSET)
+#define STM32WB_TIM16_CNT (STM32WB_TIM16_BASE + STM32WB_TIM_CNT_OFFSET)
+#define STM32WB_TIM16_PSC (STM32WB_TIM16_BASE + STM32WB_TIM_PSC_OFFSET)
+#define STM32WB_TIM16_ARR (STM32WB_TIM16_BASE + STM32WB_TIM_ARR_OFFSET)
+#define STM32WB_TIM16_RCR (STM32WB_TIM16_BASE + STM32WB_TIM_RCR_OFFSET)
+#define STM32WB_TIM16_CCR1 (STM32WB_TIM16_BASE + STM32WB_TIM_CCR1_OFFSET)
+#define STM32WB_TIM16_BDTR (STM32WB_TIM16_BASE + STM32WB_TIM_BDTR_OFFSET)
+#define STM32WB_TIM16_DCR (STM32WB_TIM16_BASE + STM32WB_TIM_DCR_OFFSET)
+#define STM32WB_TIM16_DMAR (STM32WB_TIM16_BASE + STM32WB_TIM_DMAR_OFFSET)
+#define STM32WB_TIM16_OR1 (STM32WB_TIM16_BASE + STM32WB_TIM_OR1_OFFSET)
+#define STM32WB_TIM16_AF1 (STM32WB_TIM16_BASE + STM32WB_TIM_AF1_OFFSET)
+#define STM32WB_TIM16_TISEL (STM32WB_TIM16_BASE + STM32WB_TIM_TISEL_OFFSET)
+
+#define STM32WB_TIM17_CR1 (STM32WB_TIM17_BASE + STM32WB_TIM_CR1_OFFSET)
+#define STM32WB_TIM17_CR2 (STM32WB_TIM17_BASE + STM32WB_TIM_CR2_OFFSET)
+#define STM32WB_TIM17_DIER (STM32WB_TIM17_BASE + STM32WB_TIM_DIER_OFFSET)
+#define STM32WB_TIM17_SR (STM32WB_TIM17_BASE + STM32WB_TIM_SR_OFFSET)
+#define STM32WB_TIM17_EGR (STM32WB_TIM17_BASE + STM32WB_TIM_EGR_OFFSET)
+#define STM32WB_TIM17_CCMR1 (STM32WB_TIM17_BASE + STM32WB_TIM_CCMR1_OFFSET)
+#define STM32WB_TIM17_CCER (STM32WB_TIM17_BASE + STM32WB_TIM_CCER_OFFSET)
+#define STM32WB_TIM17_CNT (STM32WB_TIM17_BASE + STM32WB_TIM_CNT_OFFSET)
+#define STM32WB_TIM17_PSC (STM32WB_TIM17_BASE + STM32WB_TIM_PSC_OFFSET)
+#define STM32WB_TIM17_ARR (STM32WB_TIM17_BASE + STM32WB_TIM_ARR_OFFSET)
+#define STM32WB_TIM17_RCR (STM32WB_TIM17_BASE + STM32WB_TIM_RCR_OFFSET)
+#define STM32WB_TIM17_CCR1 (STM32WB_TIM17_BASE + STM32WB_TIM_CCR1_OFFSET)
+#define STM32WB_TIM17_BDTR (STM32WB_TIM17_BASE + STM32WB_TIM_BDTR_OFFSET)
+#define STM32WB_TIM17_DCR (STM32WB_TIM17_BASE + STM32WB_TIM_DCR_OFFSET)
+#define STM32WB_TIM17_DMAR (STM32WB_TIM17_BASE + STM32WB_TIM_DMAR_OFFSET)
+#define STM32WB_TIM17_OR1 (STM32WB_TIM17_BASE + STM32WB_TIM_OR1_OFFSET)
+#define STM32WB_TIM17_AF1 (STM32WB_TIM17_BASE + STM32WB_TIM_AF1_OFFSET)
+#define STM32WB_TIM17_TISEL (STM32WB_TIM17_BASE + STM32WB_TIM_TISEL_OFFSET)
+
+/* Register Value Constants *************************************************/
+
+/* Digital Filter options */
+
+#define STM32WB_DF_NOFILT (0x0) /* 0000: No filter */
+#define STM32WB_DF_FCKINTn2 (0x1) /* 0001: fSAMPLING = fCK_INT, N=2 */
+#define STM32WB_DF_FCKINTn4 (0x2) /* 0010: fSAMPLING = fCK_INT, N=4 */
+#define STM32WB_DF_FCKINTn8 (0x3) /* 0011: fSAMPLING = fCK_INT, N=8 */
+#define STM32WB_DF_FDTSd2n6 (0x4) /* 0100: fSAMPLING = fDTS/2, N=6 */
+#define STM32WB_DF_FDTSd2n8 (0x5) /* 0101: fSAMPLING = fDTS/2, N=8 */
+#define STM32WB_DF_FDTSd4n6 (0x6) /* 0110: fSAMPLING = fDTS/4, N=6 */
+#define STM32WB_DF_FDTSd4n8 (0x7) /* 0111: fSAMPLING = fDTS/4, N=8 */
+#define STM32WB_DF_FDTSd8n6 (0x8) /* 1000: fSAMPLING = fDTS/8, N=6 */
+#define STM32WB_DF_FDTSd8n8 (0x9) /* 1001: fSAMPLING = fDTS/8, N=8 */
+#define STM32WB_DF_FDTSd16n5 (0xa) /* 1010: fSAMPLING = fDTS/16, N=5 */
+#define STM32WB_DF_FDTSd16n6 (0xb) /* 1011: fSAMPLING = fDTS/16, N=6 */
+#define STM32WB_DF_FDTSd16n8 (0xc) /* 1100: fSAMPLING = fDTS/16, N=8 */
+#define STM32WB_DF_FDTSd32n5 (0xd) /* 1101: fSAMPLING = fDTS/32, N=5 */
+#define STM32WB_DF_FDTSd32n6 (0xe) /* 1110: fSAMPLING = fDTS/32, N=6 */
+#define STM32WB_DF_FDTSd32n8 (0xf) /* 1111: fSAMPLING = fDTS/32, N=8 */
+
+/* Register Bitfield Definitions ********************************************/
+
+/* Control register 1 */
+
+#define TIM1_CR1_CEN (1 << 0) /* Bit 0: Counter enable */
+#define TIM1_CR1_UDIS (1 << 1) /* Bit 1: Update disable */
+#define TIM1_CR1_URS (1 << 2) /* Bit 2: Update request source */
+# define TIM1_CR1_URS_CNT_UP_DMA (0 << 2) /* 0: Counter overflow/underflow, Update from slave or UG, DMA */
+# define TIM1_CR1_URS_CNT_DMA (1 << 2) /* 1: Counter overflow/underflow or DMA */
+
+#define TIM1_CR1_OPM (1 << 3) /* Bit 3: One pulse mode */
+#define TIM1_CR1_DIR (1 << 4) /* Bit 4: Counter direction */
+# define TIM1_CR1_DIR_UP (0 << 4) /* 0: Upcounter mode */
+# define TIM1_CR1_DIR_DOWN (1 << 4) /* 1: Downcounter mode */
+
+#define TIM1_CR1_CMS_SHIFT (5) /* Bits 5-6: Center-aligned mode selection */
+#define TIM1_CR1_CMS_MASK (0x3 << TIM1_CR1_CMS_SHIFT)
+# define TIM1_CR1_CMS_EDGE (0x0 << TIM1_CR1_CMS_SHIFT) /* 00: Edge-aligned mode */
+# define TIM1_CR1_CMS_CNTR1 (0x1 << TIM1_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */
+# define TIM1_CR1_CMS_CNTR2 (0x2 << TIM1_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */
+# define TIM1_CR1_CMS_CNTR3 (0x3 << TIM1_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */
+
+#define TIM1_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */
+#define TIM1_CR1_CKD_SHIFT (8) /* Bits 8-9: Clock division */
+#define TIM1_CR1_CKD_MASK (0x3 << TIM1_CR1_CKD_SHIFT)
+# define TIM1_CR1_CKD_TCKINT (0x0 << TIM1_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */
+# define TIM1_CR1_CKD_2TCKINT (0x1 << TIM1_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */
+# define TIM1_CR1_CKD_4TCKINT (0x2 << TIM1_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */
+
+#define TIM1_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remap enable */
+
+#define TIM2_CR1_CEN (1 << 0) /* Bit 0: Counter enable */
+#define TIM2_CR1_UDIS (1 << 1) /* Bit 1: Update disable */
+#define TIM2_CR1_URS (1 << 2) /* Bit 2: Update request source */
+# define TIM2_CR1_URS_CNT_UP_DMA (0 << 2) /* 0: Counter overflow/underflow, Update from slave or UG, DMA */
+# define TIM2_CR1_URS_CNT_DMA (1 << 2) /* 1: Counter overflow/underflow or DMA */
+
+#define TIM2_CR1_OPM (1 << 3) /* Bit 3: One pulse mode */
+#define TIM2_CR1_DIR (1 << 4) /* Bit 4: Counter direction */
+# define TIM2_CR1_DIR_UP (0 << 4) /* 0: Upcounter mode */
+# define TIM2_CR1_DIR_DOWN (1 << 4) /* 1: Downcounter mode */
+
+#define TIM2_CR1_CMS_SHIFT (5) /* Bits 5-6: Center-aligned mode selection */
+#define TIM2_CR1_CMS_MASK (0x3 << TIM2_CR1_CMS_SHIFT)
+# define TIM2_CR1_CMS_EDGE (0x0 << TIM2_CR1_CMS_SHIFT) /* 00: Edge-aligned mode */
+# define TIM2_CR1_CMS_CNTR1 (0x1 << TIM2_CR1_CMS_SHIFT) /* 01: Center-aligned mode 1 */
+# define TIM2_CR1_CMS_CNTR2 (0x2 << TIM2_CR1_CMS_SHIFT) /* 10: Center-aligned mode 2 */
+# define TIM2_CR1_CMS_CNTR3 (0x3 << TIM2_CR1_CMS_SHIFT) /* 11: Center-aligned mode 3 */
+
+#define TIM2_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */
+#define TIM2_CR1_CKD_SHIFT (8) /* Bits 8-9: Clock division */
+#define TIM2_CR1_CKD_MASK (0x3 << TIM2_CR1_CKD_SHIFT)
+# define TIM2_CR1_CKD_TCKINT (0x0 << TIM2_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */
+# define TIM2_CR1_CKD_2TCKINT (0x1 << TIM2_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */
+# define TIM2_CR1_CKD_4TCKINT (0x2 << TIM2_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */
+
+#define TIM2_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remap enable */
+
+#define TIM16_CR1_CEN (1 << 0) /* Bit 0: Counter enable */
+#define TIM16_CR1_UDIS (1 << 1) /* Bit 1: Update disable */
+#define TIM16_CR1_URS (1 << 2) /* Bit 2: Update request source */
+# define TIM16_CR1_URS_CNT_UP_DMA (0 << 2) /* 0: Counter overflow/underflow, Update from slave or UG, DMA */
+# define TIM16_CR1_URS_CNT_DMA (1 << 2) /* 1: Counter overflow/underflow or DMA */
+
+#define TIM16_CR1_OPM (1 << 3) /* Bit 3: One pulse mode */
+#define TIM16_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */
+#define TIM16_CR1_CKD_SHIFT (8) /* Bits 8-9: Clock division */
+#define TIM16_CR1_CKD_MASK (0x3 << TIM16_CR1_CKD_SHIFT)
+# define TIM16_CR1_CKD_TCKINT (0x0 << TIM16_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */
+# define TIM16_CR1_CKD_2TCKINT (0x1 << TIM16_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */
+# define TIM16_CR1_CKD_4TCKINT (0x2 << TIM16_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */
+
+#define TIM16_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remap enable */
+
+#define TIM17_CR1_CEN (1 << 0) /* Bit 0: Counter enable */
+#define TIM17_CR1_UDIS (1 << 1) /* Bit 1: Update disable */
+#define TIM17_CR1_URS (1 << 2) /* Bit 2: Update request source */
+# define TIM17_CR1_URS_CNT_UP_DMA (0 << 2) /* 0: Counter overflow/underflow, Update from slave or UG, DMA */
+# define TIM17_CR1_URS_CNT_DMA (1 << 2) /* 1: Counter overflow/underflow or DMA */
+
+#define TIM17_CR1_OPM (1 << 3) /* Bit 3: One pulse mode */
+#define TIM17_CR1_ARPE (1 << 7) /* Bit 7: Auto-reload preload enable */
+#define TIM17_CR1_CKD_SHIFT (8) /* Bits 8-9: Clock division */
+#define TIM17_CR1_CKD_MASK (0x3 << TIM17_CR1_CKD_SHIFT)
+# define TIM17_CR1_CKD_TCKINT (0x0 << TIM17_CR1_CKD_SHIFT) /* 00: tDTS=tCK_INT */
+# define TIM17_CR1_CKD_2TCKINT (0x1 << TIM17_CR1_CKD_SHIFT) /* 01: tDTS=2*tCK_INT */
+# define TIM17_CR1_CKD_4TCKINT (0x2 << TIM17_CR1_CKD_SHIFT) /* 10: tDTS=4*tCK_INT */
+
+#define TIM17_CR1_UIFREMAP (1 << 11) /* Bit 11: UIF status bit remap enable */
+
+/* Control register 2 */
+
+#define TIM1_CR2_CCPC (1 << 0) /* Bit 0: Capture/Compare preloaded control (enable bit) */
+#define TIM1_CR2_CCUS (1 << 2) /* Bit 2: Capture/Compare control Update selection */
+# define TIM1_CR2_CCUS_COMG (0 << 2) /* 0: updated by setting COMG bit only */
+# define TIM1_CR2_CCUS_COMG_TRGI (1 << 2) /* 1: updated by setting COMG or TRGI rising edge */
+
+#define TIM1_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA selection */
+# define TIM1_CR2_CCDS_CCE (0 << 3) /* 0: CCx event triggers DMA request */
+# define TIM1_CR2_CCDS_UPDE (1 << 3) /* 1: Update event triggers DMA request */
+
+#define TIM1_CR2_MMS_SHIFT (4) /* Bits 4-6: Master mode selection */
+#define TIM1_CR2_MMS_MASK (0x7 << TIM1_CR2_MMS_SHIFT)
+# define TIM1_CR2_MMS_RESET (0x0 << TIM1_CR2_MMS_SHIFT) /* 000: Reset - TIMx_EGR UG bit is TRGO */
+# define TIM1_CR2_MMS_ENABLE (0x1 << TIM1_CR2_MMS_SHIFT) /* 001: Enable - CNT_EN is TRGO */
+# define TIM1_CR2_MMS_UPDATE (0x2 << TIM1_CR2_MMS_SHIFT) /* 010: Update event is TRGO */
+# define TIM1_CR2_MMS_COMPP (0x3 << TIM1_CR2_MMS_SHIFT) /* 011: Compare Pulse - CC1IF flag */
+# define TIM1_CR2_MMS_OC1REF (0x4 << TIM1_CR2_MMS_SHIFT) /* 100: Compare OC1REF is TRGO */
+# define TIM1_CR2_MMS_OC2REF (0x5 << TIM1_CR2_MMS_SHIFT) /* 101: Compare OC2REF is TRGO */
+# define TIM1_CR2_MMS_OC3REF (0x6 << TIM1_CR2_MMS_SHIFT) /* 110: Compare OC3REF is TRGO */
+# define TIM1_CR2_MMS_OC4REF (0x7 << TIM1_CR2_MMS_SHIFT) /* 111: Compare OC4REF is TRGO */
+
+#define TIM1_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection */
+# define TIM1_CR2_TI1S_CH1 (0 << 7) /* 0: CH1 pin connected to TI1 input */
+# define TIM1_CR2_TI1S_CH1CH2CH3 (1 << 7) /* 1: CH1, CH2, CH3 pins connected to TI1 input (XOR logic) */
+
+#define TIM1_CR2_OIS1 (1 << 8) /* Bit 8: Output Idle state 1 (OC1 output) */
+#define TIM1_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) */
+#define TIM1_CR2_OIS2 (1 << 10) /* Bit 10: Output Idle state 2 (OC2 output) */
+#define TIM1_CR2_OIS2N (1 << 11) /* Bit 11: Output Idle state 2 (OC2N output) */
+#define TIM1_CR2_OIS3 (1 << 12) /* Bit 12: Output Idle state 3 (OC3 output) */
+#define TIM1_CR2_OIS3N (1 << 13) /* Bit 13: Output Idle state 3 (OC3N output) */
+#define TIM1_CR2_OIS4 (1 << 14) /* Bit 14: Output Idle state 4 (OC4 output) */
+#define TIM1_CR2_OIS5 (1 << 16) /* Bit 16: Output Idle state 5 (OC5 output) */
+#define TIM1_CR2_OIS6 (1 << 18) /* Bit 18: Output Idle state 6 (OC6 output) */
+#define TIM1_CR2_MMS2_SHIFT (20) /* Bits 20-23: Master Mode Selection 2 */
+#define TIM1_CR2_MMS2_MASK (0xf << TIM1_CR2_MMS2_SHIFT)
+# define TIM1_CR2_MMS2_RESET (0x0 << TIM1_CR2_MMS2_SHIFT) /* 0000: Reset - TIMx_EGR UG bit is TRG9 */
+# define TIM1_CR2_MMS2_ENABLE (0x1 << TIM1_CR2_MMS2_SHIFT) /* 0001: Enable - CNT_EN is TRGO2 */
+# define TIM1_CR2_MMS2_UPDATE (0x2 << TIM1_CR2_MMS2_SHIFT) /* 0010: Update event is TRGO2 */
+# define TIM1_CR2_MMS2_COMPP (0x3 << TIM1_CR2_MMS2_SHIFT) /* 0011: Compare Pulse - CC1IF flag */
+# define TIM1_CR2_MMS2_OC1REF (0x4 << TIM1_CR2_MMS2_SHIFT) /* 0100: Compare OC1REF is TRGO2 */
+# define TIM1_CR2_MMS2_OC2REF (0x5 << TIM1_CR2_MMS2_SHIFT) /* 0101: Compare OC2REF is TRGO2 */
+# define TIM1_CR2_MMS2_OC3REF (0x6 << TIM1_CR2_MMS2_SHIFT) /* 0110: Compare OC3REF is TRGO2 */
+# define TIM1_CR2_MMS2_OC4REF (0x7 << TIM1_CR2_MMS2_SHIFT) /* 0111: Compare OC4REF is TRGO2 */
+# define TIM1_CR2_MMS2_OC5REF (0x8 << TIM1_CR2_MMS2_SHIFT) /* 1000: Compare OC5REF is TRGO2 */
+# define TIM1_CR2_MMS2_OC6REF (0x9 << TIM1_CR2_MMS2_SHIFT) /* 1001: Compare OC6REF is TRGO2 */
+# define TIM1_CR2_MMS2_CMPOC4 (0xa << TIM1_CR2_MMS2_SHIFT) /* 1010: Compare pulse - OC4REF edge is TRGO2 */
+# define TIM1_CR2_MMS2_CMPOC6 (0xb << TIM1_CR2_MMS2_SHIFT) /* 1011: Compare pulse - OC6REF edge is TRGO2 */
+# define TIM1_CR2_MMS2_CMPOC4R6R (0xc << TIM1_CR2_MMS2_SHIFT) /* 1100: Compare pulse - OC4REF/OC6REF rising */
+# define TIM1_CR2_MMS2_CMPOC4R6F (0xd << TIM1_CR2_MMS2_SHIFT) /* 1101: Compare pulse - OC4REF rising/OC6REF falling */
+# define TIM1_CR2_MMS2_CMPOC5R6R (0xe << TIM1_CR2_MMS2_SHIFT) /* 1110: Compare pulse - OC5REF/OC6REF rising */
+# define TIM1_CR2_MMS2_CMPOC5R6F (0xf << TIM1_CR2_MMS2_SHIFT) /* 1111: Compare pulse - OC5REF rising/OC6REF falling */
+
+#define TIM2_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA selection */
+# define TIM2_CR2_CCDS_CCE (0 << 3) /* 0: CCx event triggers DMA request */
+# define TIM2_CR2_CCDS_UPDE (1 << 3) /* 1: Update event triggers DMA request */
+
+#define TIM2_CR2_MMS_SHIFT (4) /* Bits 4-6: Master mode selection */
+#define TIM2_CR2_MMS_MASK (0x7 << TIM2_CR2_MMS_SHIFT)
+# define TIM2_CR2_MMS_RESET (0x0 << TIM2_CR2_MMS_SHIFT) /* 000: Reset - TIMx_EGR UG bit is TRGO */
+# define TIM2_CR2_MMS_ENABLE (0x1 << TIM2_CR2_MMS_SHIFT) /* 001: Enable - CNT_EN is TRGO */
+# define TIM2_CR2_MMS_UPDATE (0x2 << TIM2_CR2_MMS_SHIFT) /* 010: Update event is TRGO */
+# define TIM2_CR2_MMS_COMPP (0x3 << TIM2_CR2_MMS_SHIFT) /* 011: Compare Pulse - CC1IF flag */
+# define TIM2_CR2_MMS_OC1REF (0x4 << TIM2_CR2_MMS_SHIFT) /* 100: Compare OC1REF is TRGO */
+# define TIM2_CR2_MMS_OC2REF (0x5 << TIM2_CR2_MMS_SHIFT) /* 101: Compare OC2REF is TRGO */
+# define TIM2_CR2_MMS_OC3REF (0x6 << TIM2_CR2_MMS_SHIFT) /* 110: Compare OC3REF is TRGO */
+# define TIM2_CR2_MMS_OC4REF (0x7 << TIM2_CR2_MMS_SHIFT) /* 111: Compare OC4REF is TRGO */
+
+#define TIM2_CR2_TI1S (1 << 7) /* Bit 7: TI1 Selection */
+# define TIM2_CR2_TI1S_CH1 (0 << 7) /* 0: CH1 pin connected to TI1 input */
+# define TIM2_CR2_TI1S_CH1CH2CH3 (1 << 7) /* 1: CH1, CH2, CH3 pins connected to TI1 input (XOR logic) */
+
+#define TIM16_CR2_CCPC (1 << 0) /* Bit 0: Capture/Compare preloaded control (enable bit) */
+#define TIM16_CR2_CCUS (1 << 2) /* Bit 2: Capture/Compare control Update selection */
+# define TIM16_CR2_CCUS_COMG (0 << 2) /* 0: updated by setting COMG bit only */
+# define TIM16_CR2_CCUS_COMG_TRGI (1 << 2) /* 1: updated by setting COMG or TRGI rising edge */
+
+#define TIM16_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA selection */
+# define TIM16_CR2_CCDS_CCE (0 << 3) /* 0: CCx event triggers DMA request */
+# define TIM16_CR2_CCDS_UPDE (1 << 3) /* 1: Update event triggers DMA request */
+
+#define TIM16_CR2_OIS1 (1 << 8) /* Bit 8: Output Idle state 1 (OC1 output) */
+#define TIM16_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) */
+
+#define TIM17_CR2_CCPC (1 << 0) /* Bit 0: Capture/Compare preloaded control (enable bit) */
+#define TIM17_CR2_CCUS (1 << 2) /* Bit 2: Capture/Compare control Update selection */
+# define TIM17_CR2_CCUS_COMG (0 << 2) /* 0: updated by setting COMG bit only */
+# define TIM17_CR2_CCUS_COMG_TRGI (1 << 2) /* 1: updated by setting COMG or TRGI rising edge */
+
+#define TIM17_CR2_CCDS (1 << 3) /* Bit 3: Capture/Compare DMA selection */
+# define TIM17_CR2_CCDS_CCE (0 << 3) /* 0: CCx event triggers DMA request */
+# define TIM17_CR2_CCDS_UPDE (1 << 3) /* 1: Update event triggers DMA request */
+
+#define TIM17_CR2_OIS1 (1 << 8) /* Bit 8: Output Idle state 1 (OC1 output) */
+#define TIM17_CR2_OIS1N (1 << 9) /* Bit 9: Output Idle state 1 (OC1N output) */
+
+/* Slave mode control register */
+
+#define TIM1_SMCR_SMS_LO_SHIFT (0) /* Bits 0-2: Slave mode selection, bits [2:0] */
+#define TIM1_SMCR_SMS_HI_SHIFT (16) /* Bit 16: Slave mode selection, bits [3] */
+#define TIM1_SMCR_SMS_BITS(h,l) (((h) << TIM1_SMCR_SMS_HI_SHIFT) | ((l) << TIM1_SMCR_SMS_LO_SHIFT))
+#define TIM1_SMCR_SMS_MASK TIM1_SMCR_SMS_BITS(0x1, 0x7)
+# define TIM1_SMCR_DISAB TIM1_SMCR_SMS_BITS(0x0, 0x0) /* 0,000: Slave mode disabled */
+# define TIM1_SMCR_ENCMD1 TIM1_SMCR_SMS_BITS(0x0, 0x1) /* 0,001: Encoder mode 1 */
+# define TIM1_SMCR_ENCMD2 TIM1_SMCR_SMS_BITS(0x0, 0x2) /* 0,010: Encoder mode 2 */
+# define TIM1_SMCR_ENCMD3 TIM1_SMCR_SMS_BITS(0x0, 0x3) /* 0,011: Encoder mode 3 */
+# define TIM1_SMCR_RESET TIM1_SMCR_SMS_BITS(0x0, 0x4) /* 0,100: Reset Mode */
+# define TIM1_SMCR_GATED TIM1_SMCR_SMS_BITS(0x0, 0x5) /* 0,101: Gated Mode */
+# define TIM1_SMCR_TRIGGER TIM1_SMCR_SMS_BITS(0x0, 0x6) /* 0,110: Trigger Mode */
+# define TIM1_SMCR_EXTCLK1 TIM1_SMCR_SMS_BITS(0x0, 0x7) /* 0,111: External Clock Mode 1 */
+# define TIM1_SMCR_SMS_COMBINED TIM1_SMCR_SMS_BITS(0x1, 0x0) /* 1,000: Combined Reset and Trigger mode */
+
+#define TIM1_SMCR_OCCS (1 << 3) /* Bit 3: OCREF clear selection */
+# define TIM1_SMCR_OCCS_CLR (0 << 3) /* 0: OCREF clear triggered by CLR input */
+# define TIM1_SMCR_OCCS_ETRF (1 << 3) /* 1: OCREF clear triggered by ETRF */
+
+#define TIM1_SMCR_TS_LO_SHIFT (4) /* Bits 4-6: Trigger selection, bits [2:0] */
+#define TIM1_SMCR_TS_HI_SHIFT (20) /* Bits 20-21: Trigger selection, bits [1:0] */
+#define TIM1_SMCR_TS_BITS(h,l) (((h) << TIM1_SMCR_TS_HI_SHIFT) | ((l) << TIM1_SMCR_TS_LO_SHIFT))
+#define TIM1_SMCR_TS_MASK TIM1_SMCR_TS_BITS(0x3, 0x7)
+# define TIM1_SMCR_ITR0 TIM1_SMCR_TS_BITS(0x0, 0x0) /* 00,000: Internal trigger 0 (ITR0) */
+# define TIM1_SMCR_ITR1 TIM1_SMCR_TS_BITS(0x0, 0x1) /* 00,001: Internal trigger 1 (ITR1) */
+# define TIM1_SMCR_ITR2 TIM1_SMCR_TS_BITS(0x0, 0x2) /* 00,010: Internal trigger 2 (ITR2) */
+# define TIM1_SMCR_ITR3 TIM1_SMCR_TS_BITS(0x0, 0x3) /* 00,011: Internal trigger 3 (ITR3) */
+# define TIM1_SMCR_T1FED TIM1_SMCR_TS_BITS(0x0, 0x4) /* 00,100: TI1 Edge detector (TI1F_ED) */
+# define TIM1_SMCR_TI1FP1 TIM1_SMCR_TS_BITS(0x0, 0x5) /* 00,101: Filtered timer input 1 (TI1FP1) */
+# define TIM1_SMCR_T12FP2 TIM1_SMCR_TS_BITS(0x0, 0x6) /* 00,110: Filtered timer input 2 (TI2FP2) */
+# define TIM1_SMCR_ETRF TIM1_SMCR_TS_BITS(0x0, 0x7) /* 00,111: External trigger input (ETRF) */
+
+#define TIM1_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */
+#define TIM1_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */
+#define TIM1_SMCR_ETF_MASK (0xf << TIM1_SMCR_ETF_SHIFT)
+# define TIM1_SMCR_ETF(f) ((f) << TIM1_SMCR_ETF_SHIFT) /* f = STM32WB_DF_[digital filter option] */
+
+#define TIM1_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */
+#define TIM1_SMCR_ETPS_MASK (0x3 << TIM1_SMCR_ETPS_SHIFT)
+# define TIM1_SMCR_PSCOFF (0x0 << TIM1_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */
+# define TIM1_SMCR_ETRPd2 (0x1 << TIM1_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */
+# define TIM1_SMCR_ETRPd4 (0x2 << TIM1_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */
+# define TIM1_SMCR_ETRPd8 (0x3 << TIM1_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */
+
+#define TIM1_SMCR_ECE (1 << 14) /* Bit 14: External clock enable */
+#define TIM1_SMCR_ETP (1 << 15) /* Bit 15: External trigger polarity */
+# define TIM1_SMCR_ETP_HIGH (0 << 15) /* 0: ETR is non-inverted, active at high level or rising edge */
+# define TIM1_SMCR_ETP_LOW (1 << 15) /* 1: ETR is inverted, active at low level or falling edge */
+
+#define TIM2_SMCR_SMS_LO_SHIFT (0) /* Bits 0-2: Slave mode selection, bits [2:0] */
+#define TIM2_SMCR_SMS_HI_SHIFT (16) /* Bit 16: Slave mode selection, bits [3] */
+#define TIM2_SMCR_SMS_BITS(h,l) (((h) << TIM2_SMCR_SMS_HI_SHIFT) | ((l) << TIM2_SMCR_SMS_LO_SHIFT))
+#define TIM2_SMCR_SMS_MASK TIM2_SMCR_SMS_BITS(0x1, 0x7)
+# define TIM2_SMCR_DISAB TIM2_SMCR_SMS_BITS(0x0, 0x0) /* 0,000: Slave mode disabled */
+# define TIM2_SMCR_ENCMD1 TIM2_SMCR_SMS_BITS(0x0, 0x1) /* 0,001: Encoder mode 1 */
+# define TIM2_SMCR_ENCMD2 TIM2_SMCR_SMS_BITS(0x0, 0x2) /* 0,010: Encoder mode 2 */
+# define TIM2_SMCR_ENCMD3 TIM2_SMCR_SMS_BITS(0x0, 0x3) /* 0,011: Encoder mode 3 */
+# define TIM2_SMCR_RESET TIM2_SMCR_SMS_BITS(0x0, 0x4) /* 0,100: Reset Mode */
+# define TIM2_SMCR_GATED TIM2_SMCR_SMS_BITS(0x0, 0x5) /* 0,101: Gated Mode */
+# define TIM2_SMCR_TRIGGER TIM2_SMCR_SMS_BITS(0x0, 0x6) /* 0,110: Trigger Mode */
+# define TIM2_SMCR_EXTCLK1 TIM2_SMCR_SMS_BITS(0x0, 0x7) /* 0,111: External Clock Mode 1 */
+# define TIM2_SMCR_SMS_COMBINED TIM2_SMCR_SMS_BITS(0x1, 0x0) /* 1,000: Combined Reset and Trigger mode */
+
+#define TIM2_SMCR_OCCS (1 << 3) /* Bit 3: OCREF clear selection */
+# define TIM2_SMCR_OCCS_CLR (0 << 3) /* 0: OCREF clear triggered by CLR input */
+# define TIM2_SMCR_OCCS_ETRF (1 << 3) /* 1: OCREF clear triggered by ETRF */
+
+#define TIM2_SMCR_TS_LO_SHIFT (4) /* Bits 4-6: Trigger selection, bits [2:0] */
+#define TIM2_SMCR_TS_HI_SHIFT (20) /* Bits 20-21: Trigger selection, bits [1:0] */
+#define TIM2_SMCR_TS_BITS(h,l) (((h) << TIM2_SMCR_TS_HI_SHIFT) | ((l) << TIM2_SMCR_TS_LO_SHIFT))
+#define TIM2_SMCR_TS_MASK TIM2_SMCR_TS_BITS(0x3, 0x7)
+# define TIM2_SMCR_ITR0 TIM2_SMCR_TS_BITS(0x0, 0x0) /* 00,000: Internal trigger 0 (ITR0) */
+# define TIM2_SMCR_ITR1 TIM2_SMCR_TS_BITS(0x0, 0x1) /* 00,001: Internal trigger 1 (ITR1) */
+# define TIM2_SMCR_ITR2 TIM2_SMCR_TS_BITS(0x0, 0x2) /* 00,010: Internal trigger 2 (ITR2) */
+# define TIM2_SMCR_ITR3 TIM2_SMCR_TS_BITS(0x0, 0x3) /* 00,011: Internal trigger 3 (ITR3) */
+# define TIM2_SMCR_T1FED TIM2_SMCR_TS_BITS(0x0, 0x4) /* 00,100: TI1 Edge detector (TI1F_ED) */
+# define TIM2_SMCR_TI1FP1 TIM2_SMCR_TS_BITS(0x0, 0x5) /* 00,101: Filtered timer Input 1 (TI1FP1) */
+# define TIM2_SMCR_T12FP2 TIM2_SMCR_TS_BITS(0x0, 0x6) /* 00,110: Filtered timer Input 2 (TI2FP2) */
+# define TIM2_SMCR_ETRF TIM2_SMCR_TS_BITS(0x0, 0x7) /* 00,111: External trigger input (ETRF) */
+# define TIM2_SMCR_ITR4 TIM2_SMCR_TS_BITS(0x1, 0x0) /* 01,000: Internal trigger 4 (ITR4) */
+# define TIM2_SMCR_ITR5 TIM2_SMCR_TS_BITS(0x1, 0x1) /* 01,001: Internal trigger 5 (ITR5) */
+# define TIM2_SMCR_ITR6 TIM2_SMCR_TS_BITS(0x1, 0x2) /* 01,010: Internal trigger 6 (ITR6) */
+# define TIM2_SMCR_ITR7 TIM2_SMCR_TS_BITS(0x1, 0x3) /* 01,011: Internal trigger 7 (ITR7) */
+# define TIM2_SMCR_ITR8 TIM2_SMCR_TS_BITS(0x1, 0x4) /* 01,100: Internal trigger 8 (ITR8) */
+
+#define TIM2_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */
+#define TIM2_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */
+#define TIM2_SMCR_ETF_MASK (0xf << TIM2_SMCR_ETF_SHIFT)
+# define TIM2_SMCR_ETF(f) ((f) << TIM2_SMCR_ETF_SHIFT) /* f = STM32WB_DF_[digital filter option] */
+
+#define TIM2_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */
+#define TIM2_SMCR_ETPS_MASK (0x3 << TIM2_SMCR_ETPS_SHIFT)
+# define TIM2_SMCR_PSCOFF (0x0 << TIM2_SMCR_ETPS_SHIFT) /* 00: Prescaler OFF */
+# define TIM2_SMCR_ETRPd2 (0x1 << TIM2_SMCR_ETPS_SHIFT) /* 01: ETRP frequency divided by 2 */
+# define TIM2_SMCR_ETRPd4 (0x2 << TIM2_SMCR_ETPS_SHIFT) /* 10: ETRP frequency divided by 4 */
+# define TIM2_SMCR_ETRPd8 (0x3 << TIM2_SMCR_ETPS_SHIFT) /* 11: ETRP frequency divided by 8 */
+
+#define TIM2_SMCR_ECE (1 << 14) /* Bit 14: External clock enable */
+#define TIM2_SMCR_ETP (1 << 15) /* Bit 15: External trigger polarity */
+# define TIM2_SMCR_ETP_HIGH (0 << 15) /* 0: ETR is non-inverted, active at high level or rising edge */
+# define TIM2_SMCR_ETP_LOW (1 << 15) /* 1: ETR is inverted, active at low level or falling edge */
+
+/* Timer DMA / Interrupt enable register */
+
+#define TIM1_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */
+#define TIM1_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */
+#define TIM1_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable */
+#define TIM1_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable */
+#define TIM1_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable */
+#define TIM1_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable */
+#define TIM1_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable */
+#define TIM1_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable */
+#define TIM1_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */
+#define TIM1_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */
+#define TIM1_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable */
+#define TIM1_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable */
+#define TIM1_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable */
+#define TIM1_DIER_COMDE (1 << 13) /* Bit 13: COM DMA request enable */
+#define TIM1_DIER_TDE (1 << 14) /* Bit 14: Trigger DMA request enable */
+
+#define TIM2_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */
+#define TIM2_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */
+#define TIM2_DIER_CC2IE (1 << 2) /* Bit 2: Capture/Compare 2 interrupt enable */
+#define TIM2_DIER_CC3IE (1 << 3) /* Bit 3: Capture/Compare 3 interrupt enable */
+#define TIM2_DIER_CC4IE (1 << 4) /* Bit 4: Capture/Compare 4 interrupt enable */
+#define TIM2_DIER_TIE (1 << 6) /* Bit 6: Trigger interrupt enable */
+#define TIM2_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */
+#define TIM2_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */
+#define TIM2_DIER_CC2DE (1 << 10) /* Bit 10: Capture/Compare 2 DMA request enable */
+#define TIM2_DIER_CC3DE (1 << 11) /* Bit 11: Capture/Compare 3 DMA request enable */
+#define TIM2_DIER_CC4DE (1 << 12) /* Bit 12: Capture/Compare 4 DMA request enable */
+
+#define TIM16_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */
+#define TIM16_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */
+#define TIM16_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable */
+#define TIM16_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable */
+#define TIM16_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */
+#define TIM16_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */
+
+#define TIM17_DIER_UIE (1 << 0) /* Bit 0: Update interrupt enable */
+#define TIM17_DIER_CC1IE (1 << 1) /* Bit 1: Capture/Compare 1 interrupt enable */
+#define TIM17_DIER_COMIE (1 << 5) /* Bit 5: COM interrupt enable */
+#define TIM17_DIER_BIE (1 << 7) /* Bit 7: Break interrupt enable */
+#define TIM17_DIER_UDE (1 << 8) /* Bit 8: Update DMA request enable */
+#define TIM17_DIER_CC1DE (1 << 9) /* Bit 9: Capture/Compare 1 DMA request enable */
+
+/* Status register */
+
+#define TIM1_SR_UIF (1 << 0) /* Bit 0: Update interrupt Flag */
+#define TIM1_SR_CC1IF (1 << 1) /* Bit 1: Capture/Compare 1 interrupt Flag */
+#define TIM1_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt Flag */
+#define TIM1_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt Flag */
+#define TIM1_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt Flag */
+#define TIM1_SR_COMIF (1 << 5) /* Bit 5: COM interrupt Flag */
+#define TIM1_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag */
+#define TIM1_SR_BIF (1 << 7) /* Bit 7: Break interrupt Flag */
+#define TIM1_SR_B2IF (1 << 8) /* Bit 8: Break 2 interrupt Flag */
+#define TIM1_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */
+#define TIM1_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture Flag */
+#define TIM1_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag */
+#define TIM1_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag */
+#define TIM1_SR_SBIF (1 << 13) /* Bit 13: System break interrupt Flag */
+#define TIM1_SR_CC5IF (1 << 16) /* Bit 16: Compare 5 interrupt flag */
+#define TIM1_SR_CC6IF (1 << 17) /* Bit 17: Compare 6 interrupt flag */
+
+#define TIM2_SR_UIF (1 << 0) /* Bit 0: Update interrupt Flag */
+#define TIM2_SR_CC1IF (1 << 1) /* Bit 1: Capture/Compare 1 interrupt Flag */
+#define TIM2_SR_CC2IF (1 << 2) /* Bit 2: Capture/Compare 2 interrupt Flag */
+#define TIM2_SR_CC3IF (1 << 3) /* Bit 3: Capture/Compare 3 interrupt Flag */
+#define TIM2_SR_CC4IF (1 << 4) /* Bit 4: Capture/Compare 4 interrupt Flag */
+#define TIM2_SR_TIF (1 << 6) /* Bit 6: Trigger interrupt Flag */
+#define TIM2_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */
+#define TIM2_SR_CC2OF (1 << 10) /* Bit 10: Capture/Compare 2 Overcapture Flag */
+#define TIM2_SR_CC3OF (1 << 11) /* Bit 11: Capture/Compare 3 Overcapture Flag */
+#define TIM2_SR_CC4OF (1 << 12) /* Bit 12: Capture/Compare 4 Overcapture Flag */
+
+#define TIM16_SR_UIF (1 << 0) /* Bit 0: Update interrupt Flag */
+#define TIM16_SR_CC1IF (1 << 1) /* Bit 1: Capture/Compare 1 interrupt Flag */
+#define TIM16_SR_COMIF (1 << 5) /* Bit 5: COM interrupt Flag */
+#define TIM16_SR_BIF (1 << 7) /* Bit 7: Break interrupt Flag */
+#define TIM16_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */
+
+#define TIM17_SR_UIF (1 << 0) /* Bit 0: Update interrupt Flag */
+#define TIM17_SR_CC1IF (1 << 1) /* Bit 1: Capture/Compare 1 interrupt Flag */
+#define TIM17_SR_COMIF (1 << 5) /* Bit 5: COM interrupt Flag */
+#define TIM17_SR_BIF (1 << 7) /* Bit 7: Break interrupt Flag */
+#define TIM17_SR_CC1OF (1 << 9) /* Bit 9: Capture/Compare 1 Overcapture Flag */
+
+/* Event generation register */
+
+#define TIM1_EGR_UG (1 << 0) /* Bit 0: Update Generation */
+#define TIM1_EGR_CC1G (1 << 1) /* Bit 1: Capture/Compare 1 Generation */
+#define TIM1_EGR_CC2G (1 << 2) /* Bit 2: Capture/Compare 2 Generation */
+#define TIM1_EGR_CC3G (1 << 3) /* Bit 3: Capture/Compare 3 Generation */
+#define TIM1_EGR_CC4G (1 << 4) /* Bit 4: Capture/Compare 4 Generation */
+#define TIM1_EGR_COMG (1 << 5) /* Bit 5: Capture/Compare Control Update Generation */
+#define TIM1_EGR_TG (1 << 6) /* Bit 6: Trigger Generation */
+#define TIM1_EGR_BG (1 << 7) /* Bit 7: Break Generation */
+#define TIM1_EGR_B2G (1 << 8) /* Bit 8: Break 2 Generation */
+
+#define TIM2_EGR_UG (1 << 0) /* Bit 0: Update Generation */
+#define TIM2_EGR_CC1G (1 << 1) /* Bit 1: Capture/Compare 1 Generation */
+#define TIM2_EGR_CC2G (1 << 2) /* Bit 2: Capture/Compare 2 Generation */
+#define TIM2_EGR_CC3G (1 << 3) /* Bit 3: Capture/Compare 3 Generation */
+#define TIM2_EGR_CC4G (1 << 4) /* Bit 4: Capture/Compare 4 Generation */
+#define TIM2_EGR_TG (1 << 6) /* Bit 6: Trigger Generation */
+
+#define TIM16_EGR_UG (1 << 0) /* Bit 0: Update Generation */
+#define TIM16_EGR_CC1G (1 << 1) /* Bit 1: Capture/Compare 1 Generation */
+#define TIM16_EGR_COMG (1 << 5) /* Bit 5: Capture/Compare Control Update Generation */
+#define TIM16_EGR_BG (1 << 7) /* Bit 7: Break Generation */
+
+#define TIM17_EGR_UG (1 << 0) /* Bit 0: Update Generation */
+#define TIM17_EGR_CC1G (1 << 1) /* Bit 1: Capture/Compare 1 Generation */
+#define TIM17_EGR_COMG (1 << 5) /* Bit 5: Capture/Compare Control Update Generation */
+#define TIM17_EGR_BG (1 << 7) /* Bit 7: Break Generation */
+
+/* Capture/compare mode registers - capture/compare mode selection */
+
+#define TIM1_CCMR1_CC1S_SHIFT (0) /* Bits 0-1: Capture/Compare 1 Selection */
+#define TIM1_CCMR1_CC1S_MASK (0x3 << TIM1_CCMR1_CC1S_SHIFT)
+# define TIM1_CCMR1_CC1S_CCOUT (0x0 << TIM1_CCMR1_CC1S_SHIFT) /* 00: CC1 channel output */
+# define TIM1_CCMR1_CC1S_CCIN1 (0x1 << TIM1_CCMR1_CC1S_SHIFT) /* 01: CC1 channel input, IC1 is TI1 */
+# define TIM1_CCMR1_CC1S_CCIN2 (0x2 << TIM1_CCMR1_CC1S_SHIFT) /* 10: CC1 channel input, IC1 is TI2 */
+# define TIM1_CCMR1_CC1S_CCINTRC (0x3 << TIM1_CCMR1_CC1S_SHIFT) /* 11: CC1 channel input, IC1 is TRC */
+
+#define TIM1_CCMR1_CC2S_SHIFT (8) /* Bits 8-9: Capture/Compare 2 Selection */
+#define TIM1_CCMR1_CC2S_MASK (0x3 << TIM1_CCMR1_CC2S_SHIFT)
+# define TIM1_CCMR1_CC2S_CCOUT (0x0 << TIM1_CCMR1_CC2S_SHIFT) /* 00: CC2 channel output */
+# define TIM1_CCMR1_CC2S_CCIN1 (0x1 << TIM1_CCMR1_CC2S_SHIFT) /* 01: CC2 channel input, IC2 is TI2 */
+# define TIM1_CCMR1_CC2S_CCIN2 (0x2 << TIM1_CCMR1_CC2S_SHIFT) /* 10: CC2 channel input, IC2 is TI1 */
+# define TIM1_CCMR1_CC2S_CCINTRC (0x3 << TIM1_CCMR1_CC2S_SHIFT) /* 11: CC2 channel input, IC2 is TRC */
+
+#define TIM1_CCMR2_CC3S_SHIFT (0) /* Bits 0-1: Capture/Compare 3 Selection */
+#define TIM1_CCMR2_CC3S_MASK (0x3 << TIM1_CCMR2_CC3S_SHIFT)
+# define TIM1_CCMR2_CC3S_CCOUT (0x0 << TIM1_CCMR2_CC3S_SHIFT) /* 00: CC3 channel output */
+# define TIM1_CCMR2_CC3S_CCIN1 (0x1 << TIM1_CCMR2_CC3S_SHIFT) /* 01: CC3 channel input, IC3 is TI3 */
+# define TIM1_CCMR2_CC3S_CCIN2 (0x2 << TIM1_CCMR2_CC3S_SHIFT) /* 10: CC3 channel input, IC3 is TI4 */
+# define TIM1_CCMR2_CC3S_CCINTRC (0x3 << TIM1_CCMR2_CC3S_SHIFT) /* 11: CC3 channel input, IC3 is TRC */
+
+#define TIM1_CCMR2_CC4S_SHIFT (8) /* Bits 8-9: Capture/Compare 4 Selection */
+#define TIM1_CCMR2_CC4S_MASK (0x3 << TIM1_CCMR2_CC4S_SHIFT)
+# define TIM1_CCMR2_CC4S_CCOUT (0x0 << TIM1_CCMR2_CC4S_SHIFT) /* 00: CC4 channel output */
+# define TIM1_CCMR2_CC4S_CCIN1 (0x1 << TIM1_CCMR2_CC4S_SHIFT) /* 01: CC4 channel input, IC4 is TI4 */
+# define TIM1_CCMR2_CC4S_CCIN2 (0x2 << TIM1_CCMR2_CC4S_SHIFT) /* 10: CC4 channel input, IC4 is TI3 */
+# define TIM1_CCMR2_CC4S_CCINTRC (0x3 << TIM1_CCMR2_CC4S_SHIFT) /* 11: CC4 channel input, IC4 is TRC */
+
+#define TIM2_CCMR1_CC1S_SHIFT (0) /* Bits 0-1: Capture/Compare 1 Selection */
+#define TIM2_CCMR1_CC1S_MASK (0x3 << TIM2_CCMR1_CC1S_SHIFT)
+# define TIM2_CCMR1_CC1S_CCOUT (0x0 << TIM2_CCMR1_CC1S_SHIFT) /* 00: CC1 channel output */
+# define TIM2_CCMR1_CC1S_CCIN1 (0x1 << TIM2_CCMR1_CC1S_SHIFT) /* 01: CC1 channel input, IC1 is TI1 */
+# define TIM2_CCMR1_CC1S_CCIN2 (0x2 << TIM2_CCMR1_CC1S_SHIFT) /* 10: CC1 channel input, IC1 is TI2 */
+# define TIM2_CCMR1_CC1S_CCINTRC (0x3 << TIM2_CCMR1_CC1S_SHIFT) /* 11: CC1 channel input, IC1 is TRC */
+
+#define TIM2_CCMR1_CC2S_SHIFT (8) /* Bits 8-9: Capture/Compare 2 Selection */
+#define TIM2_CCMR1_CC2S_MASK (0x3 << TIM2_CCMR1_CC2S_SHIFT)
+# define TIM2_CCMR1_CC2S_CCOUT (0x0 << TIM2_CCMR1_CC2S_SHIFT) /* 00: CC2 channel output */
+# define TIM2_CCMR1_CC2S_CCIN1 (0x1 << TIM2_CCMR1_CC2S_SHIFT) /* 01: CC2 channel input, IC2 is TI2 */
+# define TIM2_CCMR1_CC2S_CCIN2 (0x2 << TIM2_CCMR1_CC2S_SHIFT) /* 10: CC2 channel input, IC2 is TI1 */
+# define TIM2_CCMR1_CC2S_CCINTRC (0x3 << TIM2_CCMR1_CC2S_SHIFT) /* 11: CC2 channel input, IC2 is TRC */
+
+#define TIM2_CCMR2_CC3S_SHIFT (0) /* Bits 0-1: Capture/Compare 3 Selection */
+#define TIM2_CCMR2_CC3S_MASK (0x3 << TIM2_CCMR2_CC3S_SHIFT)
+# define TIM2_CCMR2_CC3S_CCOUT (0x0 << TIM2_CCMR2_CC3S_SHIFT) /* 00: CC3 channel output */
+# define TIM2_CCMR2_CC3S_CCIN1 (0x1 << TIM2_CCMR2_CC3S_SHIFT) /* 01: CC3 channel input, IC3 is TI3 */
+# define TIM2_CCMR2_CC3S_CCIN2 (0x2 << TIM2_CCMR2_CC3S_SHIFT) /* 10: CC3 channel input, IC3 is TI4 */
+# define TIM2_CCMR2_CC3S_CCINTRC (0x3 << TIM2_CCMR2_CC3S_SHIFT) /* 11: CC3 channel input, IC3 is TRC */
+
+#define TIM2_CCMR2_CC4S_SHIFT (8) /* Bits 8-9: Capture/Compare 4 Selection */
+#define TIM2_CCMR2_CC4S_MASK (0x3 << TIM2_CCMR2_CC4S_SHIFT)
+# define TIM2_CCMR2_CC4S_CCOUT (0x0 << TIM2_CCMR2_CC4S_SHIFT) /* 00: CC4 channel output */
+# define TIM2_CCMR2_CC4S_CCIN1 (0x1 << TIM2_CCMR2_CC4S_SHIFT) /* 01: CC4 channel input, IC4 is TI4 */
+# define TIM2_CCMR2_CC4S_CCIN2 (0x2 << TIM2_CCMR2_CC4S_SHIFT) /* 10: CC4 channel input, IC4 is TI3 */
+# define TIM2_CCMR2_CC4S_CCINTRC (0x3 << TIM2_CCMR2_CC4S_SHIFT) /* 11: CC4 channel input, IC4 is TRC */
+
+#define TIM16_CCMR1_CC1S_SHIFT (0) /* Bits 0-1: Capture/Compare 1 Selection */
+#define TIM16_CCMR1_CC1S_MASK (0x3 << TIM16_CCMR1_CC1S_SHIFT)
+# define TIM16_CCMR1_CC1S_CCOUT (0x0 << TIM16_CCMR1_CC1S_SHIFT) /* 00: CC1 channel output */
+# define TIM16_CCMR1_CC1S_CCIN1 (0x1 << TIM16_CCMR1_CC1S_SHIFT) /* 01: CC1 channel input, IC1 is TI1 */
+
+#define TIM17_CCMR1_CC1S_SHIFT (0) /* Bits 0-1: Capture/Compare 1 Selection */
+#define TIM17_CCMR1_CC1S_MASK (0x3 << TIM17_CCMR1_CC1S_SHIFT)
+# define TIM17_CCMR1_CC1S_CCOUT (0x0 << TIM17_CCMR1_CC1S_SHIFT) /* 00: CC1 channel output */
+# define TIM17_CCMR1_CC1S_CCIN1 (0x1 << TIM17_CCMR1_CC1S_SHIFT) /* 01: CC1 channel input, IC1 is TI1 */
+
+/* Capture/compare mode registers - Output compare mode */
+
+#define TIM1_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */
+#define TIM1_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */
+#define TIM1_CCMR1_OC1M_LO_SHIFT (4) /* Bits 4-6: Output Compare 1 Mode, bits [2:0] */
+#define TIM1_CCMR1_OC1M_HI_SHIFT (16) /* Bit 16: Output Compare 1 Mode, bits [3] */
+#define TIM1_CCMR1_OC1M_BITS(h,l) (((h) << TIM1_CCMR1_OC1M_HI_SHIFT) | ((l) << TIM1_CCMR1_OC1M_LO_SHIFT))
+#define TIM1_CCMR1_OC1M_MASK TIM1_CCMR1_OC1M_BITS(0x1, 0x7)
+# define TIM1_CCMR1_OC1M_FRZN TIM1_CCMR1_OC1M_BITS(0x0, 0x0) /* 0,000: Frozen */
+# define TIM1_CCMR1_OC1M_CHACT TIM1_CCMR1_OC1M_BITS(0x0, 0x1) /* 0,001: Channel 1 active on match */
+# define TIM1_CCMR1_OC1M_CHINACT TIM1_CCMR1_OC1M_BITS(0x0, 0x2) /* 0,010: Channel 1 inactive on match */
+# define TIM1_CCMR1_OC1M_OCREFTOG TIM1_CCMR1_OC1M_BITS(0x0, 0x3) /* 0,011: OC1REF toggle TIM_CNT=TIM_CCR1 */
+# define TIM1_CCMR1_OC1M_OCREFLO TIM1_CCMR1_OC1M_BITS(0x0, 0x4) /* 0,100: OC1REF forced low */
+# define TIM1_CCMR1_OC1M_OCREFHI TIM1_CCMR1_OC1M_BITS(0x0, 0x5) /* 0,101: OC1REF forced high */
+# define TIM1_CCMR1_OC1M_PWM1 TIM1_CCMR1_OC1M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */
+# define TIM1_CCMR1_OC1M_PWM2 TIM1_CCMR1_OC1M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */
+# define TIM1_CCMR1_OC1M_OPM1 TIM1_CCMR1_OC1M_BITS(0x1, 0x0) /* 1,000: OPM mode 1 */
+# define TIM1_CCMR1_OC1M_OPM2 TIM1_CCMR1_OC1M_BITS(0x1, 0x1) /* 1,001: OPM mode 2 */
+# define TIM1_CCMR1_OC1M_COMBINED1 TIM1_CCMR1_OC1M_BITS(0x1, 0x4) /* 1,100: Combined PWM mode 1 */
+# define TIM1_CCMR1_OC1M_COMBINED2 TIM1_CCMR1_OC1M_BITS(0x1, 0x5) /* 1,101: Combined PWM mode 2 */
+# define TIM1_CCMR1_OC1M_ASYMM1 TIM1_CCMR1_OC1M_BITS(0x1, 0x6) /* 1,110: Asymmetric PWM mode 1 */
+# define TIM1_CCMR1_OC1M_ASYMM2 TIM1_CCMR1_OC1M_BITS(0x1, 0x7) /* 1,111: Asymmetric PWM mode 2 */
+
+#define TIM1_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1 Clear Enable */
+
+#define TIM1_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */
+#define TIM1_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */
+#define TIM1_CCMR1_OC2M_LO_SHIFT (12) /* Bits 12-14: Output Compare 2 Mode, bits [2:0] */
+#define TIM1_CCMR1_OC2M_HI_SHIFT (24) /* Bit 24: Output Compare 2 Mode, bits [3] */
+#define TIM1_CCMR1_OC2M_BITS(h,l) (((h) << TIM1_CCMR1_OC2M_HI_SHIFT) | ((l) << TIM1_CCMR1_OC2M_LO_SHIFT))
+#define TIM1_CCMR1_OC2M_MASK TIM1_CCMR1_OC2M_BITS(0x1, 0x7)
+# define TIM1_CCMR1_OC2M_FRZN TIM1_CCMR1_OC2M_BITS(0x0, 0x0) /* 0,000: Frozen */
+# define TIM1_CCMR1_OC2M_CHACT TIM1_CCMR1_OC2M_BITS(0x0, 0x1) /* 0,001: Channel 2 active on match */
+# define TIM1_CCMR1_OC2M_CHINACT TIM1_CCMR1_OC2M_BITS(0x0, 0x2) /* 0,010: Channel 2 inactive on match */
+# define TIM1_CCMR1_OC2M_OCREFTOG TIM1_CCMR1_OC2M_BITS(0x0, 0x3) /* 0,011: OC2REF toggle TIM_CNT=TIM_CCR2 */
+# define TIM1_CCMR1_OC2M_OCREFLO TIM1_CCMR1_OC2M_BITS(0x0, 0x4) /* 0,100: OC2REF forced low */
+# define TIM1_CCMR1_OC2M_OCREFHI TIM1_CCMR1_OC2M_BITS(0x0, 0x5) /* 0,101: OC2REF forced high */
+# define TIM1_CCMR1_OC2M_PWM1 TIM1_CCMR1_OC2M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */
+# define TIM1_CCMR1_OC2M_PWM2 TIM1_CCMR1_OC2M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */
+# define TIM1_CCMR1_OC2M_OPM1 TIM1_CCMR1_OC2M_BITS(0x1, 0x0) /* 1,000: OPM mode 1 */
+# define TIM1_CCMR1_OC2M_OPM2 TIM1_CCMR1_OC2M_BITS(0x1, 0x1) /* 1,001: OPM mode 2 */
+# define TIM1_CCMR1_OC2M_COMBINED1 TIM1_CCMR1_OC2M_BITS(0x1, 0x4) /* 1,100: Combined PWM mode 1 */
+# define TIM1_CCMR1_OC2M_COMBINED2 TIM1_CCMR1_OC2M_BITS(0x1, 0x5) /* 1,101: Combined PWM mode 2 */
+# define TIM1_CCMR1_OC2M_ASYMM1 TIM1_CCMR1_OC2M_BITS(0x1, 0x6) /* 1,110: Asymmetric PWM mode 1 */
+# define TIM1_CCMR1_OC2M_ASYMM2 TIM1_CCMR1_OC2M_BITS(0x1, 0x7) /* 1,111: Asymmetric PWM mode 2 */
+
+#define TIM1_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */
+
+#define TIM1_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */
+#define TIM1_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */
+#define TIM1_CCMR2_OC3M_LO_SHIFT (4) /* Bits 4-6: Output Compare 3 Mode, bits [2:0] */
+#define TIM1_CCMR2_OC3M_HI_SHIFT (16) /* Bit 16: Output Compare 3 Mode, bits [3] */
+#define TIM1_CCMR2_OC3M_BITS(h,l) (((h) << TIM1_CCMR2_OC3M_HI_SHIFT) | ((l) << TIM1_CCMR2_OC3M_LO_SHIFT))
+#define TIM1_CCMR2_OC3M_MASK TIM1_CCMR2_OC3M_BITS(0x1, 0x7)
+# define TIM1_CCMR2_OC3M_FRZN TIM1_CCMR2_OC3M_BITS(0x0, 0x0) /* 0,000: Frozen */
+# define TIM1_CCMR2_OC3M_CHACT TIM1_CCMR2_OC3M_BITS(0x0, 0x1) /* 0,001: Channel 3 active on match */
+# define TIM1_CCMR2_OC3M_CHINACT TIM1_CCMR2_OC3M_BITS(0x0, 0x2) /* 0,010: Channel 3 inactive on match */
+# define TIM1_CCMR2_OC3M_OCREFTOG TIM1_CCMR2_OC3M_BITS(0x0, 0x3) /* 0,011: OC3REF toggle TIM_CNT=TIM_CCR3 */
+# define TIM1_CCMR2_OC3M_OCREFLO TIM1_CCMR2_OC3M_BITS(0x0, 0x4) /* 0,100: OC3REF forced low */
+# define TIM1_CCMR2_OC3M_OCREFHI TIM1_CCMR2_OC3M_BITS(0x0, 0x5) /* 0,101: OC3REF forced high */
+# define TIM1_CCMR2_OC3M_PWM1 TIM1_CCMR2_OC3M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */
+# define TIM1_CCMR2_OC3M_PWM2 TIM1_CCMR2_OC3M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */
+# define TIM1_CCMR2_OC3M_OPM1 TIM1_CCMR2_OC3M_BITS(0x1, 0x0) /* 1,000: OPM mode 1 */
+# define TIM1_CCMR2_OC3M_OPM2 TIM1_CCMR2_OC3M_BITS(0x1, 0x1) /* 1,001: OPM mode 2 */
+# define TIM1_CCMR2_OC3M_COMBINED1 TIM1_CCMR2_OC3M_BITS(0x1, 0x4) /* 1,100: Combined PWM mode 1 */
+# define TIM1_CCMR2_OC3M_COMBINED2 TIM1_CCMR2_OC3M_BITS(0x1, 0x5) /* 1,101: Combined PWM mode 2 */
+# define TIM1_CCMR2_OC3M_ASYMM1 TIM1_CCMR2_OC3M_BITS(0x1, 0x6) /* 1,110: Asymmetric PWM mode 1 */
+# define TIM1_CCMR2_OC3M_ASYMM2 TIM1_CCMR2_OC3M_BITS(0x1, 0x7) /* 1,111: Asymmetric PWM mode 2 */
+
+#define TIM1_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */
+
+#define TIM1_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */
+#define TIM1_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */
+#define TIM1_CCMR2_OC4M_LO_SHIFT (12) /* Bits 12-14: Output Compare 4 Mode, bits [2:0] */
+#define TIM1_CCMR2_OC4M_HI_SHIFT (24) /* Bit 24: Output Compare 4 Mode, bits [3] */
+#define TIM1_CCMR2_OC4M_BITS(h,l) (((h) << TIM1_CCMR2_OC4M_HI_SHIFT) | ((l) << TIM1_CCMR2_OC4M_LO_SHIFT))
+#define TIM1_CCMR2_OC4M_MASK TIM1_CCMR2_OC4M_BITS(0x1, 0x7)
+# define TIM1_CCMR2_OC4M_FRZN TIM1_CCMR2_OC4M_BITS(0x0, 0x0) /* 0,000: Frozen */
+# define TIM1_CCMR2_OC4M_CHACT TIM1_CCMR2_OC4M_BITS(0x0, 0x1) /* 0,001: Channel 4 active on match */
+# define TIM1_CCMR2_OC4M_CHINACT TIM1_CCMR2_OC4M_BITS(0x0, 0x2) /* 0,010: Channel 4 inactive on match */
+# define TIM1_CCMR2_OC4M_OCREFTOG TIM1_CCMR2_OC4M_BITS(0x0, 0x3) /* 0,011: OC4REF toggle TIM_CNT=TIM_CCR4 */
+# define TIM1_CCMR2_OC4M_OCREFLO TIM1_CCMR2_OC4M_BITS(0x0, 0x4) /* 0,100: OC4REF forced low */
+# define TIM1_CCMR2_OC4M_OCREFHI TIM1_CCMR2_OC4M_BITS(0x0, 0x5) /* 0,101: OC4REF forced high */
+# define TIM1_CCMR2_OC4M_PWM1 TIM1_CCMR2_OC4M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */
+# define TIM1_CCMR2_OC4M_PWM2 TIM1_CCMR2_OC4M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */
+# define TIM1_CCMR2_OC4M_OPM1 TIM1_CCMR2_OC4M_BITS(0x1, 0x0) /* 1,000: OPM mode 1 */
+# define TIM1_CCMR2_OC4M_OPM2 TIM1_CCMR2_OC4M_BITS(0x1, 0x1) /* 1,001: OPM mode 2 */
+# define TIM1_CCMR2_OC4M_COMBINED1 TIM1_CCMR2_OC4M_BITS(0x1, 0x4) /* 1,100: Combined PWM mode 1 */
+# define TIM1_CCMR2_OC4M_COMBINED2 TIM1_CCMR2_OC4M_BITS(0x1, 0x5) /* 1,101: Combined PWM mode 2 */
+# define TIM1_CCMR2_OC4M_ASYMM1 TIM1_CCMR2_OC4M_BITS(0x1, 0x6) /* 1,110: Asymmetric PWM mode 1 */
+# define TIM1_CCMR2_OC4M_ASYMM2 TIM1_CCMR2_OC4M_BITS(0x1, 0x7) /* 1,111: Asymmetric PWM mode 2 */
+
+#define TIM1_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */
+
+#define TIM1_CCMR3_OC5FE (1 << 2) /* Bit 2: Output Compare 5 Fast enable */
+#define TIM1_CCMR3_OC5PE (1 << 3) /* Bit 3: Output Compare 5 Preload enable */
+#define TIM1_CCMR3_OC5M_LO_SHIFT (4) /* Bits 4-6: Output Compare 5 Mode, bits [2:0] */
+#define TIM1_CCMR3_OC5M_HI_SHIFT (16) /* Bit 16: Output Compare 5 Mode, bits [3] */
+#define TIM1_CCMR3_OC5M_BITS(h,l) (((h) << TIM1_CCMR3_OC5M_HI_SHIFT) | ((l) << TIM1_CCMR3_OC5M_LO_SHIFT))
+#define TIM1_CCMR3_OC5M_MASK TIM1_CCMR3_OC5M_BITS(0x1, 0x7)
+# define TIM1_CCMR3_OC5M_FRZN TIM1_CCMR3_OC5M_BITS(0x0, 0x0) /* 0,000: Frozen */
+# define TIM1_CCMR3_OC5M_CHACT TIM1_CCMR3_OC5M_BITS(0x0, 0x1) /* 0,001: Channel 5 active on match */
+# define TIM1_CCMR3_OC5M_CHINACT TIM1_CCMR3_OC5M_BITS(0x0, 0x2) /* 0,010: Channel 5 inactive on match */
+# define TIM1_CCMR3_OC5M_OCREFTOG TIM1_CCMR3_OC5M_BITS(0x0, 0x3) /* 0,011: OC5REF toggle TIM_CNT=TIM_CCR5 */
+# define TIM1_CCMR3_OC5M_OCREFLO TIM1_CCMR3_OC5M_BITS(0x0, 0x4) /* 0,100: OC5REF forced low */
+# define TIM1_CCMR3_OC5M_OCREFHI TIM1_CCMR3_OC5M_BITS(0x0, 0x5) /* 0,101: OC5REF forced high */
+# define TIM1_CCMR3_OC5M_PWM1 TIM1_CCMR3_OC5M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */
+# define TIM1_CCMR3_OC5M_PWM2 TIM1_CCMR3_OC5M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */
+# define TIM1_CCMR3_OC5M_OPM1 TIM1_CCMR3_OC5M_BITS(0x1, 0x0) /* 1,000: OPM mode 1 */
+# define TIM1_CCMR3_OC5M_OPM2 TIM1_CCMR3_OC5M_BITS(0x1, 0x1) /* 1,001: OPM mode 2 */
+# define TIM1_CCMR3_OC5M_COMBINED1 TIM1_CCMR3_OC5M_BITS(0x1, 0x4) /* 1,100: Combined PWM mode 1 */
+# define TIM1_CCMR3_OC5M_COMBINED2 TIM1_CCMR3_OC5M_BITS(0x1, 0x5) /* 1,101: Combined PWM mode 2 */
+# define TIM1_CCMR3_OC5M_ASYMM1 TIM1_CCMR3_OC5M_BITS(0x1, 0x6) /* 1,110: Asymmetric PWM mode 1 */
+# define TIM1_CCMR3_OC5M_ASYMM2 TIM1_CCMR3_OC5M_BITS(0x1, 0x7) /* 1,111: Asymmetric PWM mode 2 */
+
+#define TIM1_CCMR3_OC5CE (1 << 7) /* Bit 7: Output Compare 5 Clear Enable */
+
+#define TIM1_CCMR3_OC6FE (1 << 10) /* Bit 10: Output Compare 6 Fast enable */
+#define TIM1_CCMR3_OC6PE (1 << 11) /* Bit 11: Output Compare 6 Preload enable */
+#define TIM1_CCMR3_OC6M_LO_SHIFT (12) /* Bits 12-14: Output Compare 6 Mode, bits [2:0] */
+#define TIM1_CCMR3_OC6M_HI_SHIFT (24) /* Bit 24: Output Compare 6 Mode, bits [3] */
+#define TIM1_CCMR3_OC6M_BITS(h,l) (((h) << TIM1_CCMR3_OC6M_HI_SHIFT) | ((l) << TIM1_CCMR3_OC6M_LO_SHIFT))
+#define TIM1_CCMR3_OC6M_MASK TIM1_CCMR3_OC6M_BITS(0x1, 0x7)
+# define TIM1_CCMR3_OC6M_FRZN TIM1_CCMR3_OC6M_BITS(0x0, 0x0) /* 0,000: Frozen */
+# define TIM1_CCMR3_OC6M_CHACT TIM1_CCMR3_OC6M_BITS(0x0, 0x1) /* 0,001: Channel 6 active on match */
+# define TIM1_CCMR3_OC6M_CHINACT TIM1_CCMR3_OC6M_BITS(0x0, 0x2) /* 0,010: Channel 6 inactive on match */
+# define TIM1_CCMR3_OC6M_OCREFTOG TIM1_CCMR3_OC6M_BITS(0x0, 0x3) /* 0,011: OC6REF toggle TIM_CNT=TIM_CCR6 */
+# define TIM1_CCMR3_OC6M_OCREFLO TIM1_CCMR3_OC6M_BITS(0x0, 0x4) /* 0,100: OC6REF forced low */
+# define TIM1_CCMR3_OC6M_OCREFHI TIM1_CCMR3_OC6M_BITS(0x0, 0x5) /* 0,101: OC6REF forced high */
+# define TIM1_CCMR3_OC6M_PWM1 TIM1_CCMR3_OC6M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */
+# define TIM1_CCMR3_OC6M_PWM2 TIM1_CCMR3_OC6M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */
+# define TIM1_CCMR3_OC6M_OPM1 TIM1_CCMR3_OC6M_BITS(0x1, 0x0) /* 1,000: OPM mode 1 */
+# define TIM1_CCMR3_OC6M_OPM2 TIM1_CCMR3_OC6M_BITS(0x1, 0x1) /* 1,001: OPM mode 2 */
+# define TIM1_CCMR3_OC6M_COMBINED1 TIM1_CCMR3_OC6M_BITS(0x1, 0x4) /* 1,100: Combined PWM mode 1 */
+# define TIM1_CCMR3_OC6M_COMBINED2 TIM1_CCMR3_OC6M_BITS(0x1, 0x5) /* 1,101: Combined PWM mode 2 */
+# define TIM1_CCMR3_OC6M_ASYMM1 TIM1_CCMR3_OC6M_BITS(0x1, 0x6) /* 1,110: Asymmetric PWM mode 1 */
+# define TIM1_CCMR3_OC6M_ASYMM2 TIM1_CCMR3_OC6M_BITS(0x1, 0x7) /* 1,111: Asymmetric PWM mode 2 */
+
+#define TIM1_CCMR3_OC6CE (1 << 15) /* Bit 15: Output Compare 6 Clear Enable */
+
+#define TIM2_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */
+#define TIM2_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */
+#define TIM2_CCMR1_OC1M_LO_SHIFT (4) /* Bits 4-6: Output Compare 1 Mode, bits [2:0] */
+#define TIM2_CCMR1_OC1M_HI_SHIFT (16) /* Bit 16: Output Compare 1 Mode, bits [3] */
+#define TIM2_CCMR1_OC1M_BITS(h,l) (((h) << TIM2_CCMR1_OC1M_HI_SHIFT) | ((l) << TIM2_CCMR1_OC1M_LO_SHIFT))
+#define TIM2_CCMR1_OC1M_MASK TIM2_CCMR1_OC1M_BITS(0x1, 0x7)
+# define TIM2_CCMR1_OC1M_FRZN TIM2_CCMR1_OC1M_BITS(0x0, 0x0) /* 0,000: Frozen */
+# define TIM2_CCMR1_OC1M_CHACT TIM2_CCMR1_OC1M_BITS(0x0, 0x1) /* 0,001: Channel 1 active on match */
+# define TIM2_CCMR1_OC1M_CHINACT TIM2_CCMR1_OC1M_BITS(0x0, 0x2) /* 0,010: Channel 1 inactive on match */
+# define TIM2_CCMR1_OC1M_OCREFTOG TIM2_CCMR1_OC1M_BITS(0x0, 0x3) /* 0,011: OC1REF toggle TIM_CNT=TIM_CCR1 */
+# define TIM2_CCMR1_OC1M_OCREFLO TIM2_CCMR1_OC1M_BITS(0x0, 0x4) /* 0,100: OC1REF forced low */
+# define TIM2_CCMR1_OC1M_OCREFHI TIM2_CCMR1_OC1M_BITS(0x0, 0x5) /* 0,101: OC1REF forced high */
+# define TIM2_CCMR1_OC1M_PWM1 TIM2_CCMR1_OC1M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */
+# define TIM2_CCMR1_OC1M_PWM2 TIM2_CCMR1_OC1M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */
+# define TIM2_CCMR1_OC1M_OPM1 TIM2_CCMR1_OC1M_BITS(0x1, 0x0) /* 1,000: OPM mode 1 */
+# define TIM2_CCMR1_OC1M_OPM2 TIM2_CCMR1_OC1M_BITS(0x1, 0x1) /* 1,001: OPM mode 2 */
+# define TIM2_CCMR1_OC1M_COMBINED1 TIM2_CCMR1_OC1M_BITS(0x1, 0x4) /* 1,100: Combined PWM mode 1 */
+# define TIM2_CCMR1_OC1M_COMBINED2 TIM2_CCMR1_OC1M_BITS(0x1, 0x5) /* 1,101: Combined PWM mode 2 */
+# define TIM2_CCMR1_OC1M_ASYMM1 TIM2_CCMR1_OC1M_BITS(0x1, 0x6) /* 1,110: Asymmetric PWM mode 1 */
+# define TIM2_CCMR1_OC1M_ASYMM2 TIM2_CCMR1_OC1M_BITS(0x1, 0x7) /* 1,111: Asymmetric PWM mode 2 */
+
+#define TIM2_CCMR1_OC1CE (1 << 7) /* Bit 7: Output Compare 1 Clear Enable */
+
+#define TIM2_CCMR1_OC2FE (1 << 10) /* Bit 10: Output Compare 2 Fast enable */
+#define TIM2_CCMR1_OC2PE (1 << 11) /* Bit 11: Output Compare 2 Preload enable */
+#define TIM2_CCMR1_OC2M_LO_SHIFT (12) /* Bits 12-14: Output Compare 2 Mode, bits [2:0] */
+#define TIM2_CCMR1_OC2M_HI_SHIFT (24) /* Bit 24: Output Compare 2 Mode, bits [3] */
+#define TIM2_CCMR1_OC2M_BITS(h,l) (((h) << TIM2_CCMR1_OC2M_HI_SHIFT) | ((l) << TIM2_CCMR1_OC2M_LO_SHIFT))
+#define TIM2_CCMR1_OC2M_MASK TIM2_CCMR1_OC2M_BITS(0x1, 0x7)
+# define TIM2_CCMR1_OC2M_FRZN TIM2_CCMR1_OC2M_BITS(0x0, 0x0) /* 0,000: Frozen */
+# define TIM2_CCMR1_OC2M_CHACT TIM2_CCMR1_OC2M_BITS(0x0, 0x1) /* 0,001: Channel 2 active on match */
+# define TIM2_CCMR1_OC2M_CHINACT TIM2_CCMR1_OC2M_BITS(0x0, 0x2) /* 0,010: Channel 2 inactive on match */
+# define TIM2_CCMR1_OC2M_OCREFTOG TIM2_CCMR1_OC2M_BITS(0x0, 0x3) /* 0,011: OC2REF toggle TIM_CNT=TIM_CCR2 */
+# define TIM2_CCMR1_OC2M_OCREFLO TIM2_CCMR1_OC2M_BITS(0x0, 0x4) /* 0,100: OC2REF forced low */
+# define TIM2_CCMR1_OC2M_OCREFHI TIM2_CCMR1_OC2M_BITS(0x0, 0x5) /* 0,101: OC2REF forced high */
+# define TIM2_CCMR1_OC2M_PWM1 TIM2_CCMR1_OC2M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */
+# define TIM2_CCMR1_OC2M_PWM2 TIM2_CCMR1_OC2M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */
+# define TIM2_CCMR1_OC2M_OPM1 TIM2_CCMR1_OC2M_BITS(0x1, 0x0) /* 1,000: OPM mode 1 */
+# define TIM2_CCMR1_OC2M_OPM2 TIM2_CCMR1_OC2M_BITS(0x1, 0x1) /* 1,001: OPM mode 2 */
+# define TIM2_CCMR1_OC2M_COMBINED1 TIM2_CCMR1_OC2M_BITS(0x1, 0x4) /* 1,100: Combined PWM mode 1 */
+# define TIM2_CCMR1_OC2M_COMBINED2 TIM2_CCMR1_OC2M_BITS(0x1, 0x5) /* 1,101: Combined PWM mode 2 */
+# define TIM2_CCMR1_OC2M_ASYMM1 TIM2_CCMR1_OC2M_BITS(0x1, 0x6) /* 1,110: Asymmetric PWM mode 1 */
+# define TIM2_CCMR1_OC2M_ASYMM2 TIM2_CCMR1_OC2M_BITS(0x1, 0x7) /* 1,111: Asymmetric PWM mode 2 */
+
+#define TIM2_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */
+
+#define TIM2_CCMR2_OC3FE (1 << 2) /* Bit 2: Output Compare 3 Fast enable */
+#define TIM2_CCMR2_OC3PE (1 << 3) /* Bit 3: Output Compare 3 Preload enable */
+#define TIM2_CCMR2_OC3M_LO_SHIFT (4) /* Bits 4-6: Output Compare 3 Mode, bits [2:0] */
+#define TIM2_CCMR2_OC3M_HI_SHIFT (16) /* Bit 16: Output Compare 3 Mode, bits [3] */
+#define TIM2_CCMR2_OC3M_BITS(h,l) (((h) << TIM2_CCMR2_OC3M_HI_SHIFT) | ((l) << TIM2_CCMR2_OC3M_LO_SHIFT))
+#define TIM2_CCMR2_OC3M_MASK TIM2_CCMR2_OC3M_BITS(0x1, 0x7)
+# define TIM2_CCMR2_OC3M_FRZN TIM2_CCMR2_OC3M_BITS(0x0, 0x0) /* 0,000: Frozen */
+# define TIM2_CCMR2_OC3M_CHACT TIM2_CCMR2_OC3M_BITS(0x0, 0x1) /* 0,001: Channel 3 active on match */
+# define TIM2_CCMR2_OC3M_CHINACT TIM2_CCMR2_OC3M_BITS(0x0, 0x2) /* 0,010: Channel 3 inactive on match */
+# define TIM2_CCMR2_OC3M_OCREFTOG TIM2_CCMR2_OC3M_BITS(0x0, 0x3) /* 0,011: OC3REF toggle TIM_CNT=TIM_CCR3 */
+# define TIM2_CCMR2_OC3M_OCREFLO TIM2_CCMR2_OC3M_BITS(0x0, 0x4) /* 0,100: OC3REF forced low */
+# define TIM2_CCMR2_OC3M_OCREFHI TIM2_CCMR2_OC3M_BITS(0x0, 0x5) /* 0,101: OC3REF forced high */
+# define TIM2_CCMR2_OC3M_PWM1 TIM2_CCMR2_OC3M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */
+# define TIM2_CCMR2_OC3M_PWM2 TIM2_CCMR2_OC3M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */
+# define TIM2_CCMR2_OC3M_OPM1 TIM2_CCMR2_OC3M_BITS(0x1, 0x0) /* 1,000: OPM mode 1 */
+# define TIM2_CCMR2_OC3M_OPM2 TIM2_CCMR2_OC3M_BITS(0x1, 0x1) /* 1,001: OPM mode 2 */
+# define TIM2_CCMR2_OC3M_COMBINED1 TIM2_CCMR2_OC3M_BITS(0x1, 0x4) /* 1,100: Combined PWM mode 1 */
+# define TIM2_CCMR2_OC3M_COMBINED2 TIM2_CCMR2_OC3M_BITS(0x1, 0x5) /* 1,101: Combined PWM mode 2 */
+# define TIM2_CCMR2_OC3M_ASYMM1 TIM2_CCMR2_OC3M_BITS(0x1, 0x6) /* 1,110: Asymmetric PWM mode 1 */
+# define TIM2_CCMR2_OC3M_ASYMM2 TIM2_CCMR2_OC3M_BITS(0x1, 0x7) /* 1,111: Asymmetric PWM mode 2 */
+
+#define TIM2_CCMR2_OC3CE (1 << 7) /* Bit 7: Output Compare 3 Clear Enable */
+
+#define TIM2_CCMR2_OC4FE (1 << 10) /* Bit 10: Output Compare 4 Fast enable */
+#define TIM2_CCMR2_OC4PE (1 << 11) /* Bit 11: Output Compare 4 Preload enable */
+#define TIM2_CCMR2_OC4M_LO_SHIFT (12) /* Bits 12-14: Output Compare 4 Mode, bits [2:0] */
+#define TIM2_CCMR2_OC4M_HI_SHIFT (24) /* Bit 24: Output Compare 4 Mode, bits [3] */
+#define TIM2_CCMR2_OC4M_BITS(h,l) (((h) << TIM2_CCMR2_OC4M_HI_SHIFT) | ((l) << TIM2_CCMR2_OC4M_LO_SHIFT))
+#define TIM2_CCMR2_OC4M_MASK TIM2_CCMR2_OC4M_BITS(0x1, 0x7)
+# define TIM2_CCMR2_OC4M_FRZN TIM2_CCMR2_OC4M_BITS(0x0, 0x0) /* 0,000: Frozen */
+# define TIM2_CCMR2_OC4M_CHACT TIM2_CCMR2_OC4M_BITS(0x0, 0x1) /* 0,001: Channel 4 active on match */
+# define TIM2_CCMR2_OC4M_CHINACT TIM2_CCMR2_OC4M_BITS(0x0, 0x2) /* 0,010: Channel 4 inactive on match */
+# define TIM2_CCMR2_OC4M_OCREFTOG TIM2_CCMR2_OC4M_BITS(0x0, 0x3) /* 0,011: OC4REF toggle TIM_CNT=TIM_CCR4 */
+# define TIM2_CCMR2_OC4M_OCREFLO TIM2_CCMR2_OC4M_BITS(0x0, 0x4) /* 0,100: OC4REF forced low */
+# define TIM2_CCMR2_OC4M_OCREFHI TIM2_CCMR2_OC4M_BITS(0x0, 0x5) /* 0,101: OC4REF forced high */
+# define TIM2_CCMR2_OC4M_PWM1 TIM2_CCMR2_OC4M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */
+# define TIM2_CCMR2_OC4M_PWM2 TIM2_CCMR2_OC4M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */
+# define TIM2_CCMR2_OC4M_OPM1 TIM2_CCMR2_OC4M_BITS(0x1, 0x0) /* 1,000: OPM mode 1 */
+# define TIM2_CCMR2_OC4M_OPM2 TIM2_CCMR2_OC4M_BITS(0x1, 0x1) /* 1,001: OPM mode 2 */
+# define TIM2_CCMR2_OC4M_COMBINED1 TIM2_CCMR2_OC4M_BITS(0x1, 0x4) /* 1,100: Combined PWM mode 1 */
+# define TIM2_CCMR2_OC4M_COMBINED2 TIM2_CCMR2_OC4M_BITS(0x1, 0x5) /* 1,101: Combined PWM mode 2 */
+# define TIM2_CCMR2_OC4M_ASYMM1 TIM2_CCMR2_OC4M_BITS(0x1, 0x6) /* 1,110: Asymmetric PWM mode 1 */
+# define TIM2_CCMR2_OC4M_ASYMM2 TIM2_CCMR2_OC4M_BITS(0x1, 0x7) /* 1,111: Asymmetric PWM mode 2 */
+
+#define TIM2_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */
+
+#define TIM16_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */
+#define TIM16_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */
+#define TIM16_CCMR1_OC1M_LO_SHIFT (4) /* Bits 4-6: Output Compare 1 Mode, bits [2:0] */
+#define TIM16_CCMR1_OC1M_HI_SHIFT (16) /* Bit 16: Output Compare 1 Mode, bits [3] */
+#define TIM16_CCMR1_OC1M_BITS(h,l) (((h) << TIM16_CCMR1_OC1M_HI_SHIFT) | ((l) << TIM16_CCMR1_OC1M_LO_SHIFT))
+#define TIM16_CCMR1_OC1M_MASK TIM16_CCMR1_OC1M_BITS(0x1, 0x7)
+# define TIM16_CCMR1_OC1M_FRZN TIM16_CCMR1_OC1M_BITS(0x0, 0x0) /* 0,000: Frozen */
+# define TIM16_CCMR1_OC1M_CHACT TIM16_CCMR1_OC1M_BITS(0x0, 0x1) /* 0,001: Channel 1 active on match */
+# define TIM16_CCMR1_OC1M_CHINACT TIM16_CCMR1_OC1M_BITS(0x0, 0x2) /* 0,010: Channel 1 inactive on match */
+# define TIM16_CCMR1_OC1M_OCREFTOG TIM16_CCMR1_OC1M_BITS(0x0, 0x3) /* 0,011: OC1REF toggle TIM_CNT=TIM_CCR1 */
+# define TIM16_CCMR1_OC1M_OCREFLO TIM16_CCMR1_OC1M_BITS(0x0, 0x4) /* 0,100: OC1REF forced low */
+# define TIM16_CCMR1_OC1M_OCREFHI TIM16_CCMR1_OC1M_BITS(0x0, 0x5) /* 0,101: OC1REF forced high */
+# define TIM16_CCMR1_OC1M_PWM1 TIM16_CCMR1_OC1M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */
+# define TIM16_CCMR1_OC1M_PWM2 TIM16_CCMR1_OC1M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */
+
+#define TIM17_CCMR1_OC1FE (1 << 2) /* Bit 2: Output Compare 1 Fast enable */
+#define TIM17_CCMR1_OC1PE (1 << 3) /* Bit 3: Output Compare 1 Preload enable */
+#define TIM17_CCMR1_OC1M_LO_SHIFT (4) /* Bits 4-6: Output Compare 1 Mode, bits [2:0] */
+#define TIM17_CCMR1_OC1M_HI_SHIFT (16) /* Bit 16: Output Compare 1 Mode, bits [3] */
+#define TIM17_CCMR1_OC1M_BITS(h,l) (((h) << TIM17_CCMR1_OC1M_HI_SHIFT) | ((l) << TIM17_CCMR1_OC1M_LO_SHIFT))
+#define TIM17_CCMR1_OC1M_MASK TIM17_CCMR1_OC1M_BITS(0x1, 0x7)
+# define TIM17_CCMR1_OC1M_FRZN TIM17_CCMR1_OC1M_BITS(0x0, 0x0) /* 0,000: Frozen */
+# define TIM17_CCMR1_OC1M_CHACT TIM17_CCMR1_OC1M_BITS(0x0, 0x1) /* 0,001: Channel 1 active on match */
+# define TIM17_CCMR1_OC1M_CHINACT TIM17_CCMR1_OC1M_BITS(0x0, 0x2) /* 0,010: Channel 1 inactive on match */
+# define TIM17_CCMR1_OC1M_OCREFTOG TIM17_CCMR1_OC1M_BITS(0x0, 0x3) /* 0,011: OC1REF toggle TIM_CNT=TIM_CCR1 */
+# define TIM17_CCMR1_OC1M_OCREFLO TIM17_CCMR1_OC1M_BITS(0x0, 0x4) /* 0,100: OC1REF forced low */
+# define TIM17_CCMR1_OC1M_OCREFHI TIM17_CCMR1_OC1M_BITS(0x0, 0x5) /* 0,101: OC1REF forced high */
+# define TIM17_CCMR1_OC1M_PWM1 TIM17_CCMR1_OC1M_BITS(0x0, 0x6) /* 0,110: PWM mode 1 */
+# define TIM17_CCMR1_OC1M_PWM2 TIM17_CCMR1_OC1M_BITS(0x0, 0x7) /* 0,111: PWM mode 2 */
+
+/* Capture/compare mode registers -- Input Capture mode */
+
+#define TIM1_CCMR1_IC1PSC_SHIFT (2) /* Bits 2-3: Input Capture 1 Prescaler */
+#define TIM1_CCMR1_IC1PSC_MASK (0x3 << TIM1_CCMR1_IC1PSC_SHIFT)
+# define TIM1_CCMR1_IC1PSC_NOPSC (0x0 << TIM1_CCMR1_IC1PSC_SHIFT) /* 00: no prescaler, capture each edge */
+# define TIM1_CCMR1_IC1PSC_EVERY2 (0x1 << TIM1_CCMR1_IC1PSC_SHIFT) /* 01: capture once every 2 events */
+# define TIM1_CCMR1_IC1PSC_EVERY4 (0x2 << TIM1_CCMR1_IC1PSC_SHIFT) /* 10: capture once every 4 events */
+# define TIM1_CCMR1_IC1PSC_EVERY8 (0x3 << TIM1_CCMR1_IC1PSC_SHIFT) /* 11: capture once every 8 events */
+
+#define TIM1_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */
+#define TIM1_CCMR1_IC1F_MASK (0xf << TIM1_CCMR1_IC1F_SHIFT)
+# define TIM1_CCMR1_IC1F(f) ((f) << TIM1_CCMR1_IC1F_SHIFT) /* f = STM32WB_DF_[digital filter option] */
+
+#define TIM1_CCMR1_IC2PSC_SHIFT (10) /* Bits 10-11: Input Capture 2 Prescaler */
+#define TIM1_CCMR1_IC2PSC_MASK (0x3 << TIM1_CCMR1_IC2PSC_SHIFT)
+# define TIM1_CCMR1_IC2PSC_NOPSC (0x0 << TIM1_CCMR1_IC2PSC_SHIFT) /* 00: no prescaler, capture each edge */
+# define TIM1_CCMR1_IC2PSC_EVERY2 (0x1 << TIM1_CCMR1_IC2PSC_SHIFT) /* 01: capture once every 2 events */
+# define TIM1_CCMR1_IC2PSC_EVERY4 (0x2 << TIM1_CCMR1_IC2PSC_SHIFT) /* 10: capture once every 4 events */
+# define TIM1_CCMR1_IC2PSC_EVERY8 (0x3 << TIM1_CCMR1_IC2PSC_SHIFT) /* 11: capture once every 8 events */
+
+#define TIM1_CCMR1_IC2F_SHIFT (12) /* Bits 12-15: Input Capture 2 Filter */
+#define TIM1_CCMR1_IC2F_MASK (0xf << TIM1_CCMR1_IC2F_SHIFT)
+# define TIM1_CCMR1_IC2F(f) ((f) << TIM1_CCMR1_IC2F_SHIFT) /* f = STM32WB_DF_[digital filter option] */
+
+#define TIM1_CCMR2_IC3PSC_SHIFT (2) /* Bits 2-3: Input Capture 3 Prescaler */
+#define TIM1_CCMR2_IC3PSC_MASK (0x3 << TIM1_CCMR2_IC3PSC_SHIFT)
+# define TIM1_CCMR2_IC3PSC_NOPSC (0x0 << TIM1_CCMR2_IC3PSC_SHIFT) /* 00: no prescaler, capture each edge */
+# define TIM1_CCMR2_IC3PSC_EVERY2 (0x1 << TIM1_CCMR2_IC3PSC_SHIFT) /* 01: capture once every 2 events */
+# define TIM1_CCMR2_IC3PSC_EVERY4 (0x2 << TIM1_CCMR2_IC3PSC_SHIFT) /* 10: capture once every 4 events */
+# define TIM1_CCMR2_IC3PSC_EVERY8 (0x3 << TIM1_CCMR2_IC3PSC_SHIFT) /* 11: capture once every 8 events */
+
+#define TIM1_CCMR2_IC3F_SHIFT (4) /* Bits 4-7: Input Capture 3 Filter */
+#define TIM1_CCMR2_IC3F_MASK (0xf << TIM1_CCMR2_IC3F_SHIFT)
+# define TIM1_CCMR2_IC3F(f) ((f) << TIM1_CCMR2_IC3F_SHIFT) /* f = STM32WB_DF_[digital filter option] */
+
+#define TIM1_CCMR2_IC4PSC_SHIFT (10) /* Bits 10-11: Input Capture 4 Prescaler */
+#define TIM1_CCMR2_IC4PSC_MASK (0x3 << TIM1_CCMR2_IC4PSC_SHIFT)
+# define TIM1_CCMR2_IC4PSC_NOPSC (0x0 << TIM1_CCMR2_IC4PSC_SHIFT) /* 00: no prescaler, capture each edge */
+# define TIM1_CCMR2_IC4PSC_EVERY2 (0x1 << TIM1_CCMR2_IC4PSC_SHIFT) /* 01: capture once every 2 events */
+# define TIM1_CCMR2_IC4PSC_EVERY4 (0x2 << TIM1_CCMR2_IC4PSC_SHIFT) /* 10: capture once every 4 events */
+# define TIM1_CCMR2_IC4PSC_EVERY8 (0x3 << TIM1_CCMR2_IC4PSC_SHIFT) /* 11: capture once every 8 events */
+
+#define TIM1_CCMR2_IC4F_SHIFT (12) /* Bits 12-15: Input Capture 4 Filter */
+#define TIM1_CCMR2_IC4F_MASK (0xf << TIM1_CCMR2_IC4F_SHIFT)
+# define TIM1_CCMR2_IC4F(f) ((f) << TIM1_CCMR2_IC4F_SHIFT) /* f = STM32WB_DF_[digital filter option] */
+
+#define TIM2_CCMR1_IC1PSC_SHIFT (2) /* Bits 2-3: Input Capture 1 Prescaler */
+#define TIM2_CCMR1_IC1PSC_MASK (0x3 << TIM2_CCMR1_IC1PSC_SHIFT)
+# define TIM2_CCMR1_IC1PSC_NOPSC (0x0 << TIM2_CCMR1_IC1PSC_SHIFT) /* 00: no prescaler, capture each edge */
+# define TIM2_CCMR1_IC1PSC_EVERY2 (0x1 << TIM2_CCMR1_IC1PSC_SHIFT) /* 01: capture once every 2 events */
+# define TIM2_CCMR1_IC1PSC_EVERY4 (0x2 << TIM2_CCMR1_IC1PSC_SHIFT) /* 10: capture once every 4 events */
+# define TIM2_CCMR1_IC1PSC_EVERY8 (0x3 << TIM2_CCMR1_IC1PSC_SHIFT) /* 11: capture once every 8 events */
+
+#define TIM2_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */
+#define TIM2_CCMR1_IC1F_MASK (0xf << TIM2_CCMR1_IC1F_SHIFT)
+# define TIM2_CCMR1_IC1F(f) ((f) << TIM2_CCMR1_IC1F_SHIFT) /* f = STM32WB_DF_[digital filter option] */
+
+#define TIM2_CCMR1_IC2PSC_SHIFT (10) /* Bits 10-11: Input Capture 2 Prescaler */
+#define TIM2_CCMR1_IC2PSC_MASK (0x3 << TIM2_CCMR1_IC2PSC_SHIFT)
+# define TIM2_CCMR1_IC2PSC_NOPSC (0x0 << TIM2_CCMR1_IC2PSC_SHIFT) /* 00: no prescaler, capture each edge */
+# define TIM2_CCMR1_IC2PSC_EVERY2 (0x1 << TIM2_CCMR1_IC2PSC_SHIFT) /* 01: capture once every 2 events */
+# define TIM2_CCMR1_IC2PSC_EVERY4 (0x2 << TIM2_CCMR1_IC2PSC_SHIFT) /* 10: capture once every 4 events */
+# define TIM2_CCMR1_IC2PSC_EVERY8 (0x3 << TIM2_CCMR1_IC2PSC_SHIFT) /* 11: capture once every 8 events */
+
+#define TIM2_CCMR1_IC2F_SHIFT (12) /* Bits 12-15: Input Capture 2 Filter */
+#define TIM2_CCMR1_IC2F_MASK (0xf << TIM2_CCMR1_IC2F_SHIFT)
+# define TIM2_CCMR1_IC2F(f) ((f) << TIM2_CCMR1_IC2F_SHIFT) /* f = STM32WB_DF_[digital filter option] */
+
+#define TIM2_CCMR2_IC3PSC_SHIFT (2) /* Bits 2-3: Input Capture 3 Prescaler */
+#define TIM2_CCMR2_IC3PSC_MASK (0x3 << TIM2_CCMR2_IC3PSC_SHIFT)
+# define TIM2_CCMR2_IC3PSC_NOPSC (0x0 << TIM2_CCMR2_IC3PSC_SHIFT) /* 00: no prescaler, capture each edge */
+# define TIM2_CCMR2_IC3PSC_EVERY2 (0x1 << TIM2_CCMR2_IC3PSC_SHIFT) /* 01: capture once every 2 events */
+# define TIM2_CCMR2_IC3PSC_EVERY4 (0x2 << TIM2_CCMR2_IC3PSC_SHIFT) /* 10: capture once every 4 events */
+# define TIM2_CCMR2_IC3PSC_EVERY8 (0x3 << TIM2_CCMR2_IC3PSC_SHIFT) /* 11: capture once every 8 events */
+
+#define TIM2_CCMR2_IC3F_SHIFT (4) /* Bits 4-7: Input Capture 3 Filter */
+#define TIM2_CCMR2_IC3F_MASK (0xf << TIM2_CCMR2_IC3F_SHIFT)
+# define TIM2_CCMR2_IC3F(f) ((f) << TIM2_CCMR2_IC3F_SHIFT) /* f = STM32WB_DF_[digital filter option] */
+
+#define TIM2_CCMR2_IC4PSC_SHIFT (10) /* Bits 10-11: Input Capture 4 Prescaler */
+#define TIM2_CCMR2_IC4PSC_MASK (0x3 << TIM2_CCMR2_IC4PSC_SHIFT)
+# define TIM2_CCMR2_IC4PSC_NOPSC (0x0 << TIM2_CCMR2_IC4PSC_SHIFT) /* 00: no prescaler, capture each edge */
+# define TIM2_CCMR2_IC4PSC_EVERY2 (0x1 << TIM2_CCMR2_IC4PSC_SHIFT) /* 01: capture once every 2 events */
+# define TIM2_CCMR2_IC4PSC_EVERY4 (0x2 << TIM2_CCMR2_IC4PSC_SHIFT) /* 10: capture once every 4 events */
+# define TIM2_CCMR2_IC4PSC_EVERY8 (0x3 << TIM2_CCMR2_IC4PSC_SHIFT) /* 11: capture once every 8 events */
+
+#define TIM2_CCMR2_IC4F_SHIFT (12) /* Bits 12-15: Input Capture 4 Filter */
+#define TIM2_CCMR2_IC4F_MASK (0xf << TIM2_CCMR2_IC4F_SHIFT)
+# define TIM2_CCMR2_IC4F(f) ((f) << TIM2_CCMR2_IC4F_SHIFT) /* f = STM32WB_DF_[digital filter option] */
+
+#define TIM16_CCMR1_IC1PSC_SHIFT (2) /* Bits 2-3: Input Capture 1 Prescaler */
+#define TIM16_CCMR1_IC1PSC_MASK (0x3 << TIM16_CCMR1_IC1PSC_SHIFT)
+# define TIM16_CCMR1_IC1PSC_NOPSC (0x0 << TIM16_CCMR1_IC1PSC_SHIFT) /* 00: no prescaler, capture each edge */
+# define TIM16_CCMR1_IC1PSC_EVERY2 (0x1 << TIM16_CCMR1_IC1PSC_SHIFT) /* 01: capture once every 2 events */
+# define TIM16_CCMR1_IC1PSC_EVERY4 (0x2 << TIM16_CCMR1_IC1PSC_SHIFT) /* 10: capture once every 4 events */
+# define TIM16_CCMR1_IC1PSC_EVERY8 (0x3 << TIM16_CCMR1_IC1PSC_SHIFT) /* 11: capture once every 8 events */
+
+#define TIM16_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */
+#define TIM16_CCMR1_IC1F_MASK (0xf << TIM16_CCMR1_IC1F_SHIFT)
+# define TIM16_CCMR1_IC1F(f) ((f) << TIM16_CCMR1_IC1F_SHIFT) /* f = STM32WB_DF_[digital filter option] */
+
+#define TIM17_CCMR1_IC1PSC_SHIFT (2) /* Bits 2-3: Input Capture 1 Prescaler */
+#define TIM17_CCMR1_IC1PSC_MASK (0x3 << TIM17_CCMR1_IC1PSC_SHIFT)
+# define TIM17_CCMR1_IC1PSC_NOPSC (0x0 << TIM17_CCMR1_IC1PSC_SHIFT) /* 00: no prescaler, capture each edge */
+# define TIM17_CCMR1_IC1PSC_EVERY2 (0x1 << TIM17_CCMR1_IC1PSC_SHIFT) /* 01: capture once every 2 events */
+# define TIM17_CCMR1_IC1PSC_EVERY4 (0x2 << TIM17_CCMR1_IC1PSC_SHIFT) /* 10: capture once every 4 events */
+# define TIM17_CCMR1_IC1PSC_EVERY8 (0x3 << TIM17_CCMR1_IC1PSC_SHIFT) /* 11: capture once every 8 events */
+
+#define TIM17_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */
+#define TIM17_CCMR1_IC1F_MASK (0xf << TIM17_CCMR1_IC1F_SHIFT)
+# define TIM17_CCMR1_IC1F(f) ((f) << TIM17_CCMR1_IC1F_SHIFT) /* f = STM32WB_DF_[digital filter option] */
+
+/* Capture/compare enable register */
+
+#define TIM1_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */
+#define TIM1_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output polarity */
+#define TIM1_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 complementary output enable */
+#define TIM1_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 complementary output polarity */
+#define TIM1_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable */
+#define TIM1_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output polarity */
+#define TIM1_CCER_CC2NE (1 << 6) /* Bit 6: Capture/Compare 2 complementary output enable */
+#define TIM1_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 complementary output polarity */
+#define TIM1_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable */
+#define TIM1_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output polarity */
+#define TIM1_CCER_CC3NE (1 << 10) /* Bit 10: Capture/Compare 3 complementary output enable */
+#define TIM1_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 complementary output polarity */
+#define TIM1_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable */
+#define TIM1_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output polarity */
+#define TIM1_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 complementary output polarity */
+#define TIM1_CCER_CC5E (1 << 16) /* Bit 16: Capture/Compare 5 output enable */
+#define TIM1_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output polarity */
+#define TIM1_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */
+#define TIM1_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output polarity */
+
+#define TIM2_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */
+#define TIM2_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output polarity */
+#define TIM2_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 complementary output polarity */
+#define TIM2_CCER_CC2E (1 << 4) /* Bit 4: Capture/Compare 2 output enable */
+#define TIM2_CCER_CC2P (1 << 5) /* Bit 5: Capture/Compare 2 output polarity */
+#define TIM2_CCER_CC2NP (1 << 7) /* Bit 7: Capture/Compare 2 complementary output polarity */
+#define TIM2_CCER_CC3E (1 << 8) /* Bit 8: Capture/Compare 3 output enable */
+#define TIM2_CCER_CC3P (1 << 9) /* Bit 9: Capture/Compare 3 output polarity */
+#define TIM2_CCER_CC3NP (1 << 11) /* Bit 11: Capture/Compare 3 complementary output polarity */
+#define TIM2_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable */
+#define TIM2_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output polarity */
+#define TIM2_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 complementary output polarity */
+
+#define TIM16_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */
+#define TIM16_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output polarity */
+#define TIM16_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 complementary output enable */
+#define TIM16_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 complementary output polarity */
+
+#define TIM17_CCER_CC1E (1 << 0) /* Bit 0: Capture/Compare 1 output enable */
+#define TIM17_CCER_CC1P (1 << 1) /* Bit 1: Capture/Compare 1 output polarity */
+#define TIM17_CCER_CC1NE (1 << 2) /* Bit 2: Capture/Compare 1 complementary output enable */
+#define TIM17_CCER_CC1NP (1 << 3) /* Bit 3: Capture/Compare 1 complementary output polarity */
+
+/* Counter register */
+
+#define TIM1_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */
+#define TIM1_CNT_MASK (0xffff << TIM1_CNT_SHIFT)
+#define TIM1_CNT_UIFCPY (1 << 31) /* Bit 31: UIF copy */
+
+#define TIM2_CNT_SHIFT (0) /* Bits 0-32: Timer counter value, UIFREMAP = 0 */
+ /* Bits 0-31: Timer counter value, UIFREMAP = 1 */
+#define TIM2_CNT_MASK (0xffffffff << TIM2_CNT_SHIFT)
+#define TIM2_CNT_MASK31 (0x7fffffff << TIM2_CNT_SHIFT)
+
+#define TIM2_CNT_UIFCPY (1 << 31) /* Bit 31: UIF copy, if UIFREMAP = 1 */
+
+#define TIM16_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */
+#define TIM16_CNT_MASK (0xffff << TIM16_CNT_SHIFT)
+#define TIM16_CNT_UIFCPY (1 << 31) /* Bit 31: UIF copy */
+
+#define TIM17_CNT_SHIFT (0) /* Bits 0-15: Timer counter value */
+#define TIM17_CNT_MASK (0xffff << TIM17_CNT_SHIFT)
+#define TIM17_CNT_UIFCPY (1 << 31) /* Bit 31: UIF copy */
+
+/* Prescaler register */
+
+#define TIM1_PSC_SHIFT (0) /* Bits 0-15: Timer prescaler value */
+#define TIM1_PSC_MASK (0xffff << TIM1_PSC_SHIFT)
+
+#define TIM2_PSC_SHIFT (0) /* Bits 0-15: Timer prescaler value */
+#define TIM2_PSC_MASK (0xffff << TIM2_PSC_SHIFT)
+
+#define TIM16_PSC_SHIFT (0) /* Bits 0-15: Timer prescaler value */
+#define TIM16_PSC_MASK (0xffff << TIM16_PSC_SHIFT)
+
+#define TIM17_PSC_SHIFT (0) /* Bits 0-15: Timer prescaler value */
+#define TIM17_PSC_MASK (0xffff << TIM17_PSC_SHIFT)
+
+/* Auto-reload register */
+
+#define TIM1_ARR_SHIFT (0) /* Bits 0-15: Timer auto-reload value */
+#define TIM1_ARR_MASK (0xffff << TIM1_ARR_SHIFT)
+
+#define TIM2_ARR_SHIFT (0) /* Bits 0-31: Timer auto-reload value */
+#define TIM2_ARR_MASK (0xffffffff << TIM2_ARR_SHIFT)
+
+#define TIM16_ARR_SHIFT (0) /* Bits 0-15: Timer auto-reload value */
+#define TIM16_ARR_MASK (0xffff << TIM16_ARR_SHIFT)
+
+#define TIM17_ARR_SHIFT (0) /* Bits 0-15: Timer auto-reload value */
+#define TIM17_ARR_MASK (0xffff << TIM17_ARR_SHIFT)
+
+/* Repetition counter register */
+
+#define TIM1_RCR_SHIFT (0) /* Bits 0-15: Repetition Counter Value */
+#define TIM1_RCR_MASK (0xffff << TIM1_RCR_SHIFT)
+
+#define TIM16_RCR_SHIFT (0) /* Bits 0-7: Repetition Counter Value */
+#define TIM16_RCR_MASK (0xff << TIM16_RCR_SHIFT)
+
+#define TIM17_RCR_SHIFT (0) /* Bits 0-7: Repetition Counter Value */
+#define TIM17_RCR_MASK (0xff << TIM17_RCR_SHIFT)
+
+/* Capture/compare registers */
+
+#define TIM1_CCR1_SHIFT (0) /* Bits 0-15: Capture/Compare 1 value */
+#define TIM1_CCR1_MASK (0xffff << TIM1_CCR1_SHIFT)
+#define TIM1_CCR2_SHIFT (0) /* Bits 0-15: Capture/Compare 2 value */
+#define TIM1_CCR2_MASK (0xffff << TIM1_CCR2_SHIFT)
+#define TIM1_CCR3_SHIFT (0) /* Bits 0-15: Capture/Compare 3 value */
+#define TIM1_CCR3_MASK (0xffff << TIM1_CCR3_SHIFT)
+#define TIM1_CCR4_SHIFT (0) /* Bits 0-15: Capture/Compare 4 value */
+#define TIM1_CCR4_MASK (0xffff << TIM1_CCR4_SHIFT)
+#define TIM1_CCR5_SHIFT (0) /* Bits 0-15: Capture/Compare 5 value */
+#define TIM1_CCR5_MASK (0xffff << TIM1_CCR5_SHIFT)
+#define TIM1_CCR5_GC5C1 (1 << 29) /* Bit 29: Group Channel 5 and Channel 1 */
+#define TIM1_CCR5_GC5C2 (1 << 30) /* Bit 30: Group Channel 5 and Channel 2 */
+#define TIM1_CCR5_GC5C3 (1 << 31) /* Bit 31: Group Channel 5 and Channel 3 */
+#define TIM1_CCR6_SHIFT (0) /* Bits 0-15: Capture/Compare 6 value */
+#define TIM1_CCR6_MASK (0xffff << TIM1_CCR6_SHIFT)
+
+#define TIM2_CCR1_SHIFT (0) /* Bits 0-31: Capture/Compare 1 value */
+#define TIM2_CCR1_MASK (0xffffffff << TIM2_CCR1_SHIFT)
+#define TIM2_CCR2_SHIFT (0) /* Bits 0-31: Capture/Compare 2 value */
+#define TIM2_CCR2_MASK (0xffffffff << TIM2_CCR2_SHIFT)
+#define TIM2_CCR3_SHIFT (0) /* Bits 0-31: Capture/Compare 3 value */
+#define TIM2_CCR3_MASK (0xffffffff << TIM2_CCR3_SHIFT)
+#define TIM2_CCR4_SHIFT (0) /* Bits 0-31: Capture/Compare 4 value */
+#define TIM2_CCR4_MASK (0xffffffff << TIM2_CCR4_SHIFT)
+
+#define TIM16_CCR1_SHIFT (0) /* Bits 0-15: Capture/Compare 1 value */
+#define TIM16_CCR1_MASK (0xffff << TIM16_CCR1_SHIFT)
+
+#define TIM17_CCR1_SHIFT (0) /* Bits 0-15: Capture/Compare 1 value */
+#define TIM17_CCR1_MASK (0xffff << TIM17_CCR1_SHIFT)
+
+/* Break and dead-time register */
+
+#define TIM1_BDTR_DTG_SHIFT (0) /* Bits 7:0 [7:0]: Dead-Time Generator set-up */
+#define TIM1_BDTR_DTG_MASK (0xff << TIM1_BDTR_DTG_SHIFT)
+#define TIM1_BDTR_LOCK_SHIFT (8) /* Bits 9:8 [1:0]: Lock Configuration */
+#define TIM1_BDTR_LOCK_MASK (0x3 << TIM1_BDTR_LOCK_SHIFT)
+# define TIM1_BDTR_LOCKOFF (0x0 << TIM1_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */
+# define TIM1_BDTR_LOCK1 (0x1 << TIM1_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */
+# define TIM1_BDTR_LOCK2 (0x2 << TIM1_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */
+# define TIM1_BDTR_LOCK3 (0x3 << TIM1_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */
+
+#define TIM1_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */
+#define TIM1_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */
+#define TIM1_BDTR_BKE (1 << 12) /* Bit 12: Break enable */
+#define TIM1_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */
+#define TIM1_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */
+#define TIM1_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */
+#define TIM1_BDTR_BKF_SHIFT (16) /* Bits 16-19: Break filter */
+#define TIM1_BDTR_BKF_MASK (0xf << TIM1_BDTR_BKF_SHIFT)
+# define TIM1_BDTR_BKF(f) ((f) << TIM1_BDTR_BKF_SHIFT) /* f = STM32WB_DF_[digital filter option] */
+
+#define TIM1_BDTR_BK2F_SHIFT (20) /* Bits 20-23: Break 2 filter */
+#define TIM1_BDTR_BK2F_MASK (0xf << TIM1_BDTR_BK2F_SHIFT)
+# define TIM1_BDTR_BK2F(f) ((f) << TIM1_BDTR_BK2F_SHIFT) /* f = STM32WB_DF_[digital filter option] */
+
+#define TIM1_BDTR_BK2E (1 << 24) /* Bit 24: Break 2 enable */
+#define TIM1_BDTR_BK2P (1 << 25) /* Bit 25: Break 2 polarity */
+#define TIM1_BDTR_BKDSRM (1 << 26) /* Bit 26: Break Disarm */
+#define TIM1_BDTR_BK2DSRM (1 << 27) /* Bit 27: Break 2 Disarm */
+#define TIM1_BDTR_BKBID (1 << 28) /* Bit 28: Break Bidirectional */
+#define TIM1_BDTR_BK2BID (1 << 29) /* Bit 29: Break 2 Bidirectional */
+
+#define TIM16_BDTR_DTG_SHIFT (0) /* Bits 7:0 [7:0]: Dead-Time Generator set-up */
+#define TIM16_BDTR_DTG_MASK (0xff << TIM16_BDTR_DTG_SHIFT)
+#define TIM16_BDTR_LOCK_SHIFT (8) /* Bits 9:8 [1:0]: Lock Configuration */
+#define TIM16_BDTR_LOCK_MASK (0x3 << TIM16_BDTR_LOCK_SHIFT)
+# define TIM16_BDTR_LOCKOFF (0x0 << TIM16_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */
+# define TIM16_BDTR_LOCK1 (0x1 << TIM16_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */
+# define TIM16_BDTR_LOCK2 (0x2 << TIM16_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */
+# define TIM16_BDTR_LOCK3 (0x3 << TIM16_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */
+
+#define TIM16_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */
+#define TIM16_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */
+#define TIM16_BDTR_BKE (1 << 12) /* Bit 12: Break enable */
+#define TIM16_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */
+#define TIM16_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */
+#define TIM16_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */
+#define TIM16_BDTR_BKDSRM (1 << 26) /* Bit 26: Break Disarm */
+#define TIM16_BDTR_BKBID (1 << 28) /* Bit 28: Break Bidirectional */
+
+#define TIM17_BDTR_DTG_SHIFT (0) /* Bits 7:0 [7:0]: Dead-Time Generator set-up */
+#define TIM17_BDTR_DTG_MASK (0xff << TIM17_BDTR_DTG_SHIFT)
+#define TIM17_BDTR_LOCK_SHIFT (8) /* Bits 9:8 [1:0]: Lock Configuration */
+#define TIM17_BDTR_LOCK_MASK (0x3 << TIM17_BDTR_LOCK_SHIFT)
+# define TIM17_BDTR_LOCKOFF (0x0 << TIM17_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */
+# define TIM17_BDTR_LOCK1 (0x1 << TIM17_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */
+# define TIM17_BDTR_LOCK2 (0x2 << TIM17_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */
+# define TIM17_BDTR_LOCK3 (0x3 << TIM17_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */
+
+#define TIM17_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */
+#define TIM17_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */
+#define TIM17_BDTR_BKE (1 << 12) /* Bit 12: Break enable */
+#define TIM17_BDTR_BKP (1 << 13) /* Bit 13: Break Polarity */
+#define TIM17_BDTR_AOE (1 << 14) /* Bit 14: Automatic Output enable */
+#define TIM17_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */
+#define TIM17_BDTR_BKDSRM (1 << 26) /* Bit 26: Break Disarm */
+#define TIM17_BDTR_BKBID (1 << 28) /* Bit 28: Break Bidirectional */
+
+/* DMA control register */
+
+#define TIM1_DCR_DBA_SHIFT (0) /* Bits 0-4: DMA Base Address */
+#define TIM1_DCR_DBA_MASK (0x1f << TIM1_DCR_DBA_SHIFT)
+#define TIM1_DCR_DBL_SHIFT (8) /* Bits 8-12: DMA Burst Length */
+#define TIM1_DCR_DBL_MASK (0x1f << TIM1_DCR_DBL_SHIFT)
+# define TIM1_DCR_DBL(n) (((n)-1) << ATIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */
+
+#define TIM2_DCR_DBA_SHIFT (0) /* Bits 0-4: DMA Base Address */
+#define TIM2_DCR_DBA_MASK (0x1f << TIM2_DCR_DBA_SHIFT)
+#define TIM2_DCR_DBL_SHIFT (8) /* Bits 8-12: DMA Burst Length */
+#define TIM2_DCR_DBL_MASK (0x1f << TIM2_DCR_DBL_SHIFT)
+# define TIM2_DCR_DBL(n) (((n)-1) << ATIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */
+
+#define TIM16_DCR_DBA_SHIFT (0) /* Bits 0-4: DMA Base Address */
+#define TIM16_DCR_DBA_MASK (0x1f << TIM16_DCR_DBA_SHIFT)
+#define TIM16_DCR_DBL_SHIFT (8) /* Bits 8-12: DMA Burst Length */
+#define TIM16_DCR_DBL_MASK (0x1f << TIM16_DCR_DBL_SHIFT)
+# define TIM16_DCR_DBL(n) (((n)-1) << ATIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */
+
+#define TIM17_DCR_DBA_SHIFT (0) /* Bits 0-4: DMA Base Address */
+#define TIM17_DCR_DBA_MASK (0x1f << TIM17_DCR_DBA_SHIFT)
+#define TIM17_DCR_DBL_SHIFT (8) /* Bits 8-12: DMA Burst Length */
+#define TIM17_DCR_DBL_MASK (0x1f << TIM17_DCR_DBL_SHIFT)
+# define TIM17_DCR_DBL(n) (((n)-1) << ATIM_DCR_DBL_SHIFT) /* n transfers, n = 1..18 */
+
+/* DMA address register */
+
+#define TIM1_DMAR_SHIFT (0) /* Bits 0-31: DMA register for burst accesses */
+#define TIM1_DMAR_MASK (0xffffffff << TIM1_DMAR_SHIFT)
+
+#define TIM2_DMAR_SHIFT (0) /* Bits 0-15: DMA register for burst accesses */
+#define TIM2_DMAR_MASK (0xffff << TIM2_DMAR_SHIFT)
+
+#define TIM16_DMAR_SHIFT (0) /* Bits 0-15: DMA register for burst accesses */
+#define TIM16_DMAR_MASK (0xffff << TIM16_DMAR_SHIFT)
+
+#define TIM17_DMAR_SHIFT (0) /* Bits 0-15: DMA register for burst accesses */
+#define TIM17_DMAR_MASK (0xffff << TIM17_DMAR_SHIFT)
+
+/* Option register 1 */
+
+#define TIM1_OR1_ETR_ADC_RMP_SHIFT (0) /* Bits 0-1: TIM1 ETR to ADC AWD remap */
+#define TIM1_OR1_ETR_ADC_RMP_MASK (0x3 << TIM1_OR1_ETR_ADC_RMP_SHIFT)
+# define TIM1_OR1_ETR_ADC_RMP_NC (0x0 << TIM1_OR1_ETR_ADC_RMP_SHIFT) /* 00: ETR not connected to ADC AWD */
+# define TIM1_OR1_ETR_ADC_RMP_AWD1 (0x1 << TIM1_OR1_ETR_ADC_RMP_SHIFT) /* 01: ETR connected to ADC AWD1 */
+# define TIM1_OR1_ETR_ADC_RMP_AWD2 (0x2 << TIM1_OR1_ETR_ADC_RMP_SHIFT) /* 10: ETR connected to ADC AWD2 */
+# define TIM1_OR1_ETR_ADC_RMP_AWD3 (0x3 << TIM1_OR1_ETR_ADC_RMP_SHIFT) /* 11: ETR connected to ADC AWD3 */
+
+#define TIM1_OR1_TI1_RMP (1 << 4) /* Bit 4: Input capture 1 remap */
+# define TIM1_OR1_TI1_RMP_IO (0 << 4) /* 0: TIM1 Input capture 1 is connected to I/O */
+# define TIM1_OR1_TI1_RMP_CMP1OUT (1 << 4) /* 1: TIM1 Input capture 1 is connected to COMP1 output */
+
+#define TIM2_OR1_ITR_RMP (1 << 0) /* Bit 0: Internal trigger remap */
+# define TIM2_OR1_ITR_RMP_NC (0 << 0) /* 0: TIM2 Internal trigger ITR2 is not connected */
+# define TIM2_OR1_ITR_RMP_USB_SOF (1 << 0) /* 1: TIM2 Internal trigger ITR2 is connected to USB SOF */
+
+#define TIM2_OR1_ETR_RMP (1 << 1) /* Bit 1: External trigger 1 remap */
+# define TIM2_OR1_ETR_RMP_GPIO (0 << 1) /* 0: TIM2 ETR2 is connected to GPIO */
+# define TIM2_OR1_ETR_RMP_LSE (1 << 1) /* 1: LSE internal clock is connected to TIM2 ETR */
+
+#define TIM2_OR1_TI4_RMP_SHIFT (2) /* Bits 2-3: Timer input 4 remap */
+#define TIM2_OR1_TI4_RMP_MASK (0x3 << TIM2_OR1_TI4_RMP_SHIFT)
+# define TIM2_OR1_TI4_RMP_GPIO (0x0 << TIM2_OR1_TI4_RMP_SHIFT) /* 00: TI4 connected to GPIO */
+# define TIM2_OR1_TI4_RMP_CMP1OUT (0x1 << TIM2_OR1_TI4_RMP_SHIFT) /* 01: TI4 connected to COMP1 output */
+# define TIM2_OR1_TI4_RMP_CMP2OUT (0x2 << TIM2_OR1_TI4_RMP_SHIFT) /* 10: TI4 connected to COMP2 output */
+# define TIM2_OR1_TI4_RMP_CMP1CMP2 (0x3 << TIM2_OR1_TI4_RMP_SHIFT) /* 11: TI4 connected to OR between COMP1-2 */
+
+#define TIM16_OR1_TI1_RMP_SHIFT (0) /* Bits 0-1: TIM16 input 1 connection */
+#define TIM16_OR1_TI1_RMP_MASK (0x3 << TIM16_OR1_TI1_RMP_SHIFT)
+# define TIM16_OR1_TI1_RMP_GPIO (0x0 << TIM16_OR1_TI1_RMP_SHIFT) /* 00: TI1 connected to GPIO */
+# define TIM16_OR1_TI1_RMP_LSI (0x1 << TIM16_OR1_TI1_RMP_SHIFT) /* 01: TI1 connected to LSI */
+# define TIM16_OR1_TI1_RMP_LSE (0x2 << TIM16_OR1_TI1_RMP_SHIFT) /* 10: TI1 connected to LSE */
+# define TIM16_OR1_TI1_RMP_RTCWKUP (0x3 << TIM16_OR1_TI1_RMP_SHIFT) /* 11: TI1 connected to RTC wake-up interrupt */
+
+#define TIM17_OR1_TI1_RMP_SHIFT (0) /* Bits 0-1: TIM17 input 1 connection */
+#define TIM17_OR1_TI1_RMP_MASK (0x3 << TIM17_OR1_TI1_RMP_SHIFT)
+# define TIM17_OR1_TI1_RMP_GPIO (0x0 << TIM17_OR1_TI1_RMP_SHIFT) /* 00: TI1 connected to GPIO */
+# define TIM17_OR1_TI1_RMP_MSI (0x1 << TIM17_OR1_TI1_RMP_SHIFT) /* 01: TI1 connected to MSI */
+# define TIM17_OR1_TI1_RMP_HSEd32 (0x2 << TIM17_OR1_TI1_RMP_SHIFT) /* 10: TI1 connected to HSE/32 */
+# define TIM17_OR1_TI1_RMP_MCO (0x3 << TIM17_OR1_TI1_RMP_SHIFT) /* 11: TI1 connected to MCO */
+
+/* Alternate function registers */
+
+#define TIM1_AF1_BKINE (1 << 0) /* Bit 0: BRK BKIN input enable */
+#define TIM1_AF1_BKCMP1E (1 << 1) /* Bit 1: BRK COMP1 enable */
+#define TIM1_AF1_BKCMP2E (1 << 2) /* Bit 2: BRK COMP2 enable */
+#define TIM1_AF1_BKINP (1 << 9) /* Bit 9: BRK BKIN input polarity */
+#define TIM1_AF1_BKCMP1P (1 << 10) /* Bit 10: BRK COMP1 input polarity */
+#define TIM1_AF1_BKCMP2P (1 << 11) /* Bit 11: BRK COMP2 input polarity */
+#define TIM1_AF1_ETRSEL_SHIFT (14) /* Bits 14-17: ETR source selection */
+#define TIM1_AF1_ETRSEL_MASK (0xf << TIM1_AF1_ETRSEL_SHIFT)
+# define TIM1_AF1_ETRSEL_LEGACY (0x0 << TIM1_AF1_ETRSEL_SHIFT) /* 0000: ETR legacy mode */
+# define TIM1_AF1_ETRSEL_CMP1OUT (0x1 << TIM1_AF1_ETRSEL_SHIFT) /* 0001: COMP1 output */
+# define TIM1_AF1_ETRSEL_CMP2OUT (0x2 << TIM1_AF1_ETRSEL_SHIFT) /* 0010: COMP2 output */
+
+#define TIM1_AF2_BK2INE (1 << 0) /* Bit 0: BRK2 BKIN input enable */
+#define TIM1_AF2_BK2CMP1E (1 << 1) /* Bit 1: BRK2 COMP1 enable */
+#define TIM1_AF2_BK2CMP2E (1 << 2) /* Bit 2: BRK2 COMP2 enable */
+#define TIM1_AF2_BK2INP (1 << 9) /* Bit 9: BRK2 BKIN input polarity */
+#define TIM1_AF2_BK2CMP1P (1 << 10) /* Bit 10: BRK2 COMP1 input polarity */
+#define TIM1_AF2_BK2CMP2P (1 << 11) /* Bit 11: BRK2 COMP2 input polarity */
+
+#define TIM2_AF1_ETRSEL_SHIFT (14) /* Bits 14-17: ETR source selection */
+#define TIM2_AF1_ETRSEL_MASK (0xf << TIM2_AF1_ETRSEL_SHIFT)
+# define TIM2_AF1_ETRSEL_GPIO_LSE (0x0 << TIM2_AF1_ETRSEL_SHIFT) /* 0000: GPIO or LSE clock */
+# define TIM2_AF1_ETRSEL_CMP1OUT (0x1 << TIM2_AF1_ETRSEL_SHIFT) /* 0001: COMP1 output */
+# define TIM2_AF1_ETRSEL_CMP2OUT (0x2 << TIM2_AF1_ETRSEL_SHIFT) /* 0010: COMP2 output */
+
+#define TIM16_AF1_BKINE (1 << 0) /* Bit 0: BRK BKIN input enable */
+#define TIM16_AF1_BKCMP1E (1 << 1) /* Bit 1: BRK COMP1 enable */
+#define TIM16_AF1_BKCMP2E (1 << 2) /* Bit 2: BRK COMP2 enable */
+#define TIM16_AF1_BKINP (1 << 9) /* Bit 9: BRK BKIN input polarity */
+#define TIM16_AF1_BKCMP1P (1 << 10) /* Bit 10: BRK COMP1 input polarity */
+#define TIM16_AF1_BKCMP2P (1 << 11) /* Bit 11: BRK COMP2 input polarity */
+
+#define TIM17_AF1_BKINE (1 << 0) /* Bit 0: BRK BKIN input enable */
+#define TIM17_AF1_BKCMP1E (1 << 1) /* Bit 1: BRK COMP1 enable */
+#define TIM17_AF1_BKCMP2E (1 << 2) /* Bit 2: BRK COMP2 enable */
+#define TIM17_AF1_BKINP (1 << 9) /* Bit 9: BRK BKIN input polarity */
+#define TIM17_AF1_BKCMP1P (1 << 10) /* Bit 10: BRK COMP1 input polarity */
+#define TIM17_AF1_BKCMP2P (1 << 11) /* Bit 11: BRK COMP2 input polarity */
+
+/* Timer input selection register */
+
+#define TIM1_TISEL_TI1SEL_SHIFT (0) /* Bits 0-3: selects TI1[0] to TI1[15] input */
+#define TIM1_TISEL_TI1SEL_MASK (0xf << TIM1_TISEL_TI1SEL_SHIFT)
+# define TIM1_TISEL_TI1SEL_CH1 (0x0 << TIM1_TISEL_TI1SEL_SHIFT) /* 0000: CH1 input */
+
+#define TIM1_TISEL_TI2SEL_SHIFT (8) /* Bits 8-11: selects TI2[0] to TI2[15] input */
+#define TIM1_TISEL_TI2SEL_MASK (0xf << TIM1_TISEL_TI2SEL_SHIFT)
+# define TIM1_TISEL_TI2SEL_CH2 (0x0 << TIM1_TISEL_TI2SEL_SHIFT) /* 0000: CH2 input */
+
+#define TIM1_TISEL_TI3SEL_SHIFT (16) /* Bits 16-19: selects TI3[0] to TI3[15] input */
+#define TIM1_TISEL_TI3SEL_MASK (0xf << TIM1_TISEL_TI3SEL_SHIFT)
+# define TIM1_TISEL_TI3SEL_CH3 (0x0 << TIM1_TISEL_TI3SEL_SHIFT) /* 0000: CH3 input */
+
+#define TIM1_TISEL_TI4SEL_SHIFT (24) /* Bits 24-27: selects TI4[0] to TI4[15] input */
+#define TIM1_TISEL_TI4SEL_MASK (0xf << TIM1_TISEL_TI4SEL_SHIFT)
+# define TIM1_TISEL_TI4SEL_CH4 (0x0 << TIM1_TISEL_TI4SEL_SHIFT) /* 0000: CH4 input */
+
+#define TIM2_TISEL_TI1SEL_SHIFT (0) /* Bits 0-3: selects TI1[0] to TI1[15] input */
+#define TIM2_TISEL_TI1SEL_MASK (0xf << TIM2_TISEL_TI1SEL_SHIFT)
+# define TIM2_TISEL_TI1SEL_CH1 (0x0 << TIM2_TISEL_TI1SEL_SHIFT) /* 0000: CH1 input */
+
+#define TIM2_TISEL_TI2SEL_SHIFT (8) /* Bits 8-11: selects TI2[0] to TI2[15] input */
+#define TIM2_TISEL_TI2SEL_MASK (0xf << TIM2_TISEL_TI2SEL_SHIFT)
+# define TIM2_TISEL_TI2SEL_CH2 (0x0 << TIM2_TISEL_TI2SEL_SHIFT) /* 0000: CH2 input */
+
+#define TIM16_TISEL_TI1SEL_SHIFT (0) /* Bits 0-3: selects TI1[0] to TI1[15] input */
+#define TIM16_TISEL_TI1SEL_MASK (0xf << TIM16_TISEL_TI1SEL_SHIFT)
+# define TIM16_TISEL_TI1SEL_CH1 (0x0 << TIM16_TISEL_TI1SEL_SHIFT) /* 0000: CH1 input */
+
+#define TIM17_TISEL_TI1SEL_SHIFT (0) /* Bits 0-3: selects TI1[0] to TI1[15] input */
+#define TIM17_TISEL_TI1SEL_MASK (0xf << TIM17_TISEL_TI1SEL_SHIFT)
+# define TIM17_TISEL_TI1SEL_CH1 (0x0 << TIM17_TISEL_TI1SEL_SHIFT) /* 0000: CH1 input */
+
+#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_TIM_H */
diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_uart.h b/arch/arm/src/stm32wb/hardware/stm32wb_uart.h
new file mode 100644
index 0000000000..39624fd724
--- /dev/null
+++ b/arch/arm/src/stm32wb/hardware/stm32wb_uart.h
@@ -0,0 +1,339 @@
+/****************************************************************************
+ * arch/arm/src/stm32wb/hardware/stm32wb_uart.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_UART_H
+#define __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_UART_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define STM32WB_USART_CR1_OFFSET 0x0000 /* Control Register 1 */
+#define STM32WB_USART_CR2_OFFSET 0x0004 /* Control Register 2 */
+#define STM32WB_USART_CR3_OFFSET 0x0008 /* Control Register 3 */
+#define STM32WB_USART_BRR_OFFSET 0x000c /* Baud Rate Register */
+#define STM32WB_USART_GTPR_OFFSET 0x0010 /* Guard Time and Prescaler Register */
+#define STM32WB_USART_RTOR_OFFSET 0x0014 /* Receiver Timeout Register */
+#define STM32WB_USART_RQR_OFFSET 0x0018 /* Request Register */
+#define STM32WB_USART_ISR_OFFSET 0x001c /* Interrupt and Status Register */
+#define STM32WB_USART_ICR_OFFSET 0x0020 /* Interrupt flag Clear Register */
+#define STM32WB_USART_RDR_OFFSET 0x0024 /* Receive Data Register */
+#define STM32WB_USART_TDR_OFFSET 0x0028 /* Transmit Data Register */
+#define STM32WB_USART_PRESC_OFFSET 0x002c /* Prescaler Register */
+
+/* Register Addresses *******************************************************/
+
+#if STM32WB_NUSART > 0
+# define STM32WB_USART1_CR1 (STM32WB_USART1_BASE + STM32WB_USART_CR1_OFFSET)
+# define STM32WB_USART1_CR2 (STM32WB_USART1_BASE + STM32WB_USART_CR2_OFFSET)
+# define STM32WB_USART1_CR3 (STM32WB_USART1_BASE + STM32WB_USART_CR3_OFFSET)
+# define STM32WB_USART1_BRR (STM32WB_USART1_BASE + STM32WB_USART_BRR_OFFSET)
+# define STM32WB_USART1_GTPR (STM32WB_USART1_BASE + STM32WB_USART_GTPR_OFFSET)
+# define STM32WB_USART1_RTOR (STM32WB_USART1_BASE + STM32WB_USART_RTOR_OFFSET)
+# define STM32WB_USART1_RQR (STM32WB_USART1_BASE + STM32WB_USART_RQR_OFFSET)
+# define STM32WB_USART1_ISR (STM32WB_USART1_BASE + STM32WB_USART_ISR_OFFSET)
+# define STM32WB_USART1_ICR (STM32WB_USART1_BASE + STM32WB_USART_ICR_OFFSET)
+# define STM32WB_USART1_RDR (STM32WB_USART1_BASE + STM32WB_USART_RDR_OFFSET)
+# define STM32WB_USART1_TDR (STM32WB_USART1_BASE + STM32WB_USART_TDR_OFFSET)
+# define STM32WB_USART1_PRESC (STM32WB_USART1_BASE + STM32WB_USART_PRESC_OFFSET)
+#endif
+
+/* Register Bitfield Definitions ********************************************/
+
+/* Control Register 1 */
+
+#define USART_CR1_UE (1 << 0) /* Bit 0: USART Enable */
+#define USART_CR1_UESM (1 << 1) /* Bit 1: USART Enable in low power Mode */
+#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */
+#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */
+#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */
+#define USART_CR1_RXFNEIE (1 << 5) /* Bit 5: in FIFO mode - Rx FIFO Not Empty Interrupt Enable */
+#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: in Non-FIFO mode - Rx Data Register Not Empty Interrupt Enable */
+#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */
+#define USART_CR1_TXFNFIE (1 << 7) /* Bit 7: in FIFO mode - Tx FIFO Not Full Interrupt Enable */
+#define USART_CR1_TXEIE (1 << 7) /* Bit 7: in Non-FIFO mode - Tx Data Register Empty Interrupt Enable */
+#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */
+#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */
+#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */
+#define USART_CR1_WAKE (1 << 11) /* Bit 11: Receiver Wakeup method */
+#define USART_CR1_M0 (1 << 12) /* Bit 12: Word length - Bit 0 */
+#define USART_CR1_MME (1 << 13) /* Bit 13: Mute Mode Enable */
+#define USART_CR1_CMIE (1 << 14) /* Bit 14: Character match interrupt enable */
+#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling by 8-bit or 16-bit mode */
+
+#define USART_CR1_DEDT_SHIFT (16) /* Bits 20:16 - Driver Enable Deassertion Time, in 1/16ths or 1/8ths bit time */
+#define USART_CR1_DEDT_MASK (0x1f << USART_CR1_DEDT_SHIFT)
+# define USART_CR1_DEDT(n) (((n) << USART_CR1_DEDT_SHIFT) & USART_CR1_DEDT_MASK)
+
+#define USART_CR1_DEAT_SHIFT (21) /* Bits 25:21 - Driver Enable Assertion Time, in 1/16ths or 1/8ths bit time */
+#define USART_CR1_DEAT_MASK (0x1f << USART_CR1_DEAT_SHIFT)
+# define USART_CR1_DEAT(n) (((n) << USART_CR1_DEAT_SHIFT) & USART_CR1_DEAT_MASK)
+
+#define USART_CR1_RTOIE (1 << 26) /* Bit 26: Receive Time Out interrupt enable */
+#define USART_CR1_EOBIE (1 << 27) /* Bit 27: End of Block interrupt enable */
+#define USART_CR1_M1 (1 << 28) /* Bit 28: Word length - Bit 1 */
+#define USART_CR1_FIFOEN (1 << 29) /* Bit 29: FIFO mode enable */
+#define USART_CR1_TXFEIE (1 << 30) /* Bit 30: TXFIFO empty interrupt enable */
+#define USART_CR1_RXFFIE (1 << 31) /* Bit 31: RXFIFO Full interrupt enable */
+#define USART_CR1_M_MASK (USART_CR1_M0 | USART_CR1_M1)
+
+#define USART_CR1_ALLINTS \
+ (USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | USART_CR1_TXEIE | \
+ USART_CR1_PEIE | USART_CR1_CMIE | USART_CR1_RTOIE | USART_CR1_EOBIE | \
+ USART_CR1_TXFEIE | USART_CR1_RXFFIE)
+
+/* Control Register 2 */
+
+#define USART_CR2_SLVEN (1 << 0) /* Bit 0: Synchronous Slave Mode Enable */
+#define USART_CR2_DIS_NSS (1 << 3) /* Bit 3: Slave Select (NSS) Pin Ignore For SPI */
+#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: 7-Bit / 4-Bit Address Detection */
+#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */
+#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
+#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */
+#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */
+#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */
+
+#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: Stop bits */
+#define USART_CR2_STOP_MASK (0x3 << USART_CR2_STOP_SHIFT)
+# define USART_CR2_STOP1 (0x0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */
+# define USART_CR2_STOP0p5 (0x1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bits */
+# define USART_CR2_STOP2 (0x2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
+# define USART_CR2_STOP1p5 (0x3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bits */
+
+#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN Mode Enable */
+#define USART_CR2_SWAP (1 << 15) /* Bit 15: Swap TX/RX Pins */
+#define USART_CR2_RXINV (1 << 16) /* Bit 16: RX Pin Active Level Inversion */
+#define USART_CR2_TXINV (1 << 17) /* Bit 17: TX Pin Active Level Inversion */
+#define USART_CR2_DATAINV (1 << 18) /* Bit 18: Binary Data Inversion */
+#define USART_CR2_MSBFIRST (1 << 19) /* Bit 19: MSB First */
+#define USART_CR2_ABREN (1 << 20) /* Bit 20: Auto Baud-Rate Enable */
+
+#define USART_CR2_ABRMOD_SHIFT (21) /* Bits 22-21: Auto Baud-Rate detection mode */
+#define USART_CR2_ABRMOD_MASK (0x3 << USART_CR2_ABRMOD_SHIFT)
+# define USART_CR2_ABRMOD_STARTBIT (0x0 << USART_CR2_ABRMOD_SHIFT) /* 00: Measurement of Start Bit */
+# define USART_CR2_ABRMOD_FALLEDGE (0x1 << USART_CR2_ABRMOD_SHIFT) /* 01: Falling Edge to Falling Edge */
+# define USART_CR2_ABRMOD_7F_FRAME (0x2 << USART_CR2_ABRMOD_SHIFT) /* 10: 0x7f Frame detection */
+# define USART_CR2_ABRMOD_55_FRAME (0x3 << USART_CR2_ABRMOD_SHIFT) /* 11: 0x55 Frame detection */
+
+#define USART_CR2_RTOEN (1 << 23) /* Bit 23: Receiver Time-Out Enable */
+
+#define USART_CR2_ADD_SHIFT (24) /* Bits 31-24: Address of the USART Node */
+#define USART_CR2_ADD_MASK (0xff << USART_CR2_ADD_SHIFT)
+
+/* Control Register 3 */
+
+#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */
+#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA Mode Enable */
+#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */
+#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */
+#define USART_CR3_NACK (1 << 4) /* Bit 4: SmartCard NACK Enable */
+#define USART_CR3_SCEN (1 << 5) /* Bit 5: SmartCard Mode Enable */
+#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */
+#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */
+#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */
+#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
+#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
+#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One Sample Bit Method Enable */
+#define USART_CR3_OVRDIS (1 << 12) /* Bit 12: Overrun Disable */
+#define USART_CR3_DDRE (1 << 13) /* Bit 13: DMA Disable on Reception Error */
+#define USART_CR3_DEM (1 << 14) /* Bit 14: Driver Enable Mode */
+#define USART_CR3_DEP (1 << 15) /* Bit 15: Driver Enable Polarity selection */
+
+#define USART_CR3_SCARCNT_SHIFT (17) /* Bits 19-17: SmartCard Auto-Retry Count */
+#define USART_CR3_SCARCNT_MASK (0x7 << USART_CR3_SCARCNT_SHIFT)
+# define USART_CR3_SCARCNT(n) (((n) << USART_CR3_SCARCNT_SHIFT) & USART_CR3_SCARCNT_MASK)
+
+#define USART_CR3_WUS_SHIFT (20) /* Bits 21-20: Wake Up From Low Power Mode Interrupt Flag Selection) */
+#define USART_CR3_WUS_MASK (0x3 << USART_CR3_WUS_SHIFT)
+# define USART_CR3_WUS_ADDR (0x0 << USART_CR3_WUS_SHIFT) /* 00: On Address Match */
+# define USART_CR3_WUS_STARTBIT (0x2 << USART_CR3_WUS_SHIFT) /* 10: On Start Bit Detection */
+# define USART_CR3_WUS_RXFNE (0x3 << USART_CR3_WUS_SHIFT) /* 11: On RXNE/RXFNE */
+
+#define USART_CR3_WUFIE (1 << 22) /* Bit 22: Wake Up From Low Power Mode Interrupt Enable */
+#define USART_CR3_TXFTIE (1 << 23) /* Bit 23: Transmit FIFO Threshold Interrupt Enable */
+#define USART_CR3_TCBGTIE (1 << 24) /* Bit 24: Transmit Complete Before Guard Time Interrupt Enable */
+
+#define USART_CR3_RXFTCFG_SHIFT (25) /* Bits 27-25 Receive FIFO Threshold Configuration */
+#define USART_CR3_RXFTCFG_MASK (0x7 << USART_CR3_RXFTCFG_SHIFT)
+# define USART_CR3_RXFTCFG_1_8 (0x0 << USART_CR3_RXFTCFG_SHIFT) /* 000: Rx FIFO Reaches 1/8Th Depth */
+# define USART_CR3_RXFTCFG_1_4 (0x1 << USART_CR3_RXFTCFG_SHIFT) /* 001: Rx FIFO Reaches 1/4Th Depth */
+# define USART_CR3_RXFTCFG_1_2 (0x2 << USART_CR3_RXFTCFG_SHIFT) /* 010: Rx FIFO Reaches 1/2 Depth */
+# define USART_CR3_RXFTCFG_3_4 (0x3 << USART_CR3_RXFTCFG_SHIFT) /* 011: Rx FIFO Reaches 3/4Ths Depth */
+# define USART_CR3_RXFTCFG_7_8 (0x4 << USART_CR3_RXFTCFG_SHIFT) /* 100: Rx FIFO Reaches 7/8Ths Depth */
+# define USART_CR3_RXFTCFG_FULL (0x5 << USART_CR3_RXFTCFG_SHIFT) /* 101: Rx FIFO Is Full */
+
+#define USART_CR3_RXFTIE (1 << 28) /* Bit 28: Receive FIFO Threshold Interrupt Enable */
+
+#define USART_CR3_TXFTCFG_SHIFT (29) /* Bits 31-29: Transmit FIFO Threshold Configuration */
+#define USART_CR3_TXFTCFG_MASK (0x7 << USART_CR3_TXFTCFG_SHIFT)
+# define USART_CR3_TXFTCFG_1_8 (0x0 << USART_CR3_TXFTCFG_SHIFT) /* 000: Tx FIFO Reaches 1/8Th Depth */
+# define USART_CR3_TXFTCFG_1_4 (0x1 << USART_CR3_TXFTCFG_SHIFT) /* 001: Tx FIFO Reaches 1/4Th Depth */
+# define USART_CR3_TXFTCFG_1_2 (0x2 << USART_CR3_TXFTCFG_SHIFT) /* 010: Tx FIFO Reaches 1/2 Depth */
+# define USART_CR3_TXFTCFG_3_4 (0x3 << USART_CR3_TXFTCFG_SHIFT) /* 011: Tx FIFO Reaches 3/4Ths Depth */
+# define USART_CR3_TXFTCFG_7_8 (0x4 << USART_CR3_TXFTCFG_SHIFT) /* 100: Tx FIFO Reaches 7/8Ths Depth */
+# define USART_CR3_TXFTCFG_FULL (0x5 << USART_CR3_TXFTCFG_SHIFT) /* 101: Tx FIFO Is Empty */
+
+/* Baud Rate Register (USART) */
+
+#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */
+#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT)
+
+#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */
+#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT)
+
+/* Baud Rate Register (LPUART) */
+
+#define LPUART_BRR_SHIFT (0) /* Bits 19-0: LPUART baud rate */
+#define LPUART_BRR_MASK (0xfffff << LPUART_BRR_SHIFT)
+#define LPUART_BRR_MIN (0x300) /* Minimum value permitted for BRR register */
+
+/* Guard Time and Prescaler Register */
+
+#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */
+#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
+# define USART_GTPR_PSC(n) (((n) << USART_GTPR_PSC_SHIFT) & USART_GTPR_PSC_MASK)
+
+#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard Time value */
+#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
+# define USART_GTPR_GT(n) (((n) << USART_GTPR_GT_SHIFT) & USART_GTPR_GT_MASK)
+
+/* Receiver Timeout Register */
+
+#define USART_RTOR_RTO_SHIFT (0) /* Bits 23-0: Receiver Time Out value */
+#define USART_RTOR_RTO_MASK (0xffffff << USART_RTOR_RTO_SHIFT)
+# define USART_RTOR_RTO(n) (((n) << USART_RTOR_RTO_SHIFT) & USART_RTOR_RTO_MASK)
+
+#define USART_RTOR_BLEN_SHIFT (24) /* Bits 31-24: Block Length */
+#define USART_RTOR_BLEN_MASK (0xff << USART_RTOR_BLEN_SHIFT)
+# define USART_RTOR_BLEN(n) (((n) << USART_RTOR_BLEN_SHIFT) & USART_RTOR_BLEN_MASK)
+
+/* Request Register */
+
+#define USART_RQR_ABRRQ (1 << 0) /* Bit 0 - Auto-Baud Rate Request */
+#define USART_RQR_SBKRQ (1 << 1) /* Bit 1 - Send Break Request */
+#define USART_RQR_MMRQ (1 << 2) /* Bit 2 - Mute Mode Request */
+#define USART_RQR_RXFRQ (1 << 3) /* Bit 3 - Receive Data Flush Request */
+#define USART_RQR_TXFRQ (1 << 4) /* Bit 4 - Transmit Data Flush Request */
+
+/* Interrupt and Status Register */
+
+#define USART_ISR_PE (1 << 0) /* Bit 0 - Parity Error */
+#define USART_ISR_FE (1 << 1) /* Bit 1 - Framing Error */
+#define USART_ISR_NE (1 << 2) /* Bit 2 - Noise Detected Flag */
+#define USART_ISR_ORE (1 << 3) /* Bit 3 - Overrun Error */
+#define USART_ISR_IDLE (1 << 4) /* Bit 4 - Idle Line Detected */
+#define USART_ISR_RXFNE (1 << 5) /* Bit 5 (When FIFO in use) - Rx FIFO Not Empty */
+#define USART_ISR_RXNE (1 << 5) /* Bit 5 (When FIFO not in use) - Rx Data Register Not Empty */
+#define USART_ISR_TC (1 << 6) /* Bit 6 - Transmission Complete */
+#define USART_ISR_TXFNF (1 << 7) /* Bit 7 (When FIFO in use) - Tx FIFO Not Full */
+#define USART_ISR_TXE (1 << 7) /* Bit 7 (When FIFO not in use) - Tx Data Register Empty */
+#define USART_ISR_LBDF (1 << 8) /* Bit 8 - LIN Break Detection Flag */
+#define USART_ISR_CTSIF (1 << 9) /* Bit 9 - CTS Interrupt Flag */
+#define USART_ISR_CTS (1 << 10) /* Bit 10 - CTS Flag */
+#define USART_ISR_RTOF (1 << 11) /* Bit 11 - Receiver Time Out */
+#define USART_ISR_EOBF (1 << 12) /* Bit 12 - End of Block Flag */
+#define USART_ISR_UDR (1 << 13) /* Bit 13 - SPI Slave Underrun Error Flag */
+#define USART_ISR_ABRE (1 << 14) /* Bit 14 - Auto Baud Rate Error */
+#define USART_ISR_ABRF (1 << 15) /* Bit 15 - Auto Baud Rate Flag */
+#define USART_ISR_BUSY (1 << 16) /* Bit 16 - Busy Flag */
+#define USART_ISR_CMF (1 << 17) /* Bit 17 - Character Match Flag */
+#define USART_ISR_SBKF (1 << 18) /* Bit 18 - Send Break Flag */
+#define USART_ISR_RWU (1 << 19) /* Bit 19 - Receive Wake Up From Mute Mode Flag */
+#define USART_ISR_WUF (1 << 20) /* Bit 20 - Wake Up From Stop Mode Flag */
+#define USART_ISR_TEACK (1 << 21) /* Bit 21 - Transmit Enable Acknowledge Flag */
+#define USART_ISR_REACK (1 << 22) /* Bit 22 - Receive Enable Acknowledge Flag */
+#define USART_ISR_TXFE (1 << 23) /* Bit 23 (When FIFO in use) - Tx FIFO Empty */
+#define USART_ISR_RXFF (1 << 24) /* Bit 24 (When FIFO in use) - Rx FIFO Full */
+#define USART_ISR_TCBGT (1 << 25) /* Bit 25 - Transmission Complete Before Guard Time Completion */
+#define USART_ISR_RXFT (1 << 26) /* Bit 26 (When FIFO in use) - Rx FIFO Threshold Flag */
+#define USART_ISR_TXFT (1 << 27) /* Bit 27 (When FIFO in use) - Tx FIFO Threshold Fla */
+#define USART_ISR_ALLBITS (0x0fffffff)
+
+/* Interrupt Flag Clear Register */
+
+#define USART_ICR_PECF (1 << 0) /* Bit 0 - Parity Error Clear Flag */
+#define USART_ICR_FECF (1 << 1) /* Bit 1 - Framing Error Clear Flag */
+#define USART_ICR_NCF (1 << 2) /* Bit 2 - Noise detected Clear Flag */
+#define USART_ICR_ORECF (1 << 3) /* Bit 3 - OverRun Error Clear Flag */
+#define USART_ICR_IDLECF (1 << 4) /* Bit 4 - Idle Line Detected Clear Flag */
+#define USART_ICR_TXFECF (1 << 5) /* Bit 5 - Tx FIFO Empty Clear Flag */
+#define USART_ICR_TCCF (1 << 6) /* Bit 6 - Transmission Complete Clear Flag */
+#define USART_ICR_TCBGTCF (1 << 7) /* Bit 7 - Transmission Complete Before Guard Time Clear Flag */
+#define USART_ICR_LBDCF (1 << 8) /* Bit 8 - LIN Break Detection Clear Flag */
+#define USART_ICR_CTSCF (1 << 9) /* Bit 9 - CTS Interrupt Clear Flag */
+#define USART_ICR_RTOCF (1 << 11) /* Bit 11 - Receiver Timeout Clear Flag */
+#define USART_ICR_EOBCF (1 << 12) /* Bit 12 - End of Block Clear Flag */
+#define USART_ICR_UDRCF (1 << 13) /* Bit 13 - SPI Slave Underrun Clear Flag */
+#define USART_ICR_CMCF (1 << 17) /* Bit 17 - Character Match Clear Flag */
+#define USART_ICR_WUCF (1 << 20) /* Bit 20 - Wake Up From Stop Mode Clear Flag */
+
+/* Receive Data Register */
+
+#define USART_RDR_SHIFT (0) /* Bits 8-0: Receive Data value */
+#define USART_RDR_MASK (0x1ff << USART_RDR_SHIFT)
+# define USART_RDR(n) (((n) << USART_RDR_SHIFT) & USART_RDR_MASK)
+
+/* Transmit Data Register */
+
+#define USART_TDR_SHIFT (0) /* Bits 8-0: Transmit Data value */
+#define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT)
+# define USART_TDR(n) (((n) << USART_TDR_SHIFT) & USART_TDR_MASK)
+
+/* Prescaler Register */
+
+#define USART_PRESC_PRESCALER_SHIFT (0) /* Bits 3-0: Clock Prescaler */
+#define USART_PRESC_PRESCALER_MASK (0xf << USART_PRESC_PRESCALER_SHIFT)
+#define USART_PRESC_PRESCALER_1 (0x0 << USART_PRESC_PRESCALER_SHIFT) /* 0000: not divided */
+#define USART_PRESC_PRESCALER_2 (0x1 << USART_PRESC_PRESCALER_SHIFT) /* 0001: divided by 2 */
+#define USART_PRESC_PRESCALER_4 (0x2 << USART_PRESC_PRESCALER_SHIFT) /* 0010: divided by 4 */
+#define USART_PRESC_PRESCALER_6 (0x3 << USART_PRESC_PRESCALER_SHIFT) /* 0011: divided by 6 */
+#define USART_PRESC_PRESCALER_8 (0x4 << USART_PRESC_PRESCALER_SHIFT) /* 0100: divided by 8 */
+#define USART_PRESC_PRESCALER_10 (0x5 << USART_PRESC_PRESCALER_SHIFT) /* 0101: divided by 10 */
+#define USART_PRESC_PRESCALER_12 (0x6 << USART_PRESC_PRESCALER_SHIFT) /* 0110: divided by 12 */
+#define USART_PRESC_PRESCALER_16 (0x7 << USART_PRESC_PRESCALER_SHIFT) /* 0111: divided by 16 */
+#define USART_PRESC_PRESCALER_32 (0x8 << USART_PRESC_PRESCALER_SHIFT) /* 1000: divided by 32 */
+#define USART_PRESC_PRESCALER_64 (0x9 << USART_PRESC_PRESCALER_SHIFT) /* 1001: divided by 64 */
+#define USART_PRESC_PRESCALER_128 (0xa << USART_PRESC_PRESCALER_SHIFT) /* 1010: divided by 128 */
+#define USART_PRESC_PRESCALER_256 (0xb << USART_PRESC_PRESCALER_SHIFT) /* 1011: divided by 256 */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_UART_H */
diff --git a/arch/arm/src/stm32wb/stm32wb.h b/arch/arm/src/stm32wb/stm32wb.h
new file mode 100644
index 0000000000..4e86f4f84f
--- /dev/null
+++ b/arch/arm/src/stm32wb/stm32wb.h
@@ -0,0 +1,43 @@
+/****************************************************************************
+ * arch/arm/src/stm32wb/stm32wb.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_H
+#define __ARCH_ARM_SRC_STM32WB_STM32WB_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "arm_internal.h"
+
+/* Peripherals **************************************************************/
+
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_H */
diff --git a/arch/arm/src/stm32wb/stm32wb_allocateheap.c b/arch/arm/src/stm32wb/stm32wb_allocateheap.c
new file mode 100644
index 0000000000..9cba74e993
--- /dev/null
+++ b/arch/arm/src/stm32wb/stm32wb_allocateheap.c
@@ -0,0 +1,324 @@
+/****************************************************************************
+ * arch/arm/src/stm32wb/stm32wb_allocateheap.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <nuttx/kmalloc.h>
+#include <nuttx/userspace.h>
+#include <arch/board/board.h>
+
+#include "arm_internal.h"
+#include "mpu.h"
+#include "chip.h"
+#include "stm32wb_mpuinit.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Internal SRAM is available in all members of the STM32WB family. The
+ * following definitions must be provided to specify the size and
+ * location of internal (system) SRAM1, SRAM2a and SRAM2b:
+ *
+ * SRAM1_START 0x20000000
+ * SRAM1_END
+ * SRAM2A_START 0x20030000
+ * SRAM2A_END
+ * SRAM2B_START 0x20038000
+ * SRAM2B_END
+ */
+
+/* Set the range of system SRAM1 */
+
+#define SRAM1_START STM32WB_SRAM1_BASE
+#define SRAM1_END (SRAM1_START + STM32WB_SRAM1_SIZE)
+
+/* Set the range of SRAM2a as well, requires a second memory region */
+
+#ifdef CONFIG_STM32WB_SRAM2A_HEAP
+# define SRAM2A_START (STM32WB_SRAM2A_BASE + CONFIG_STM32WB_SRAM2A_USER_BASE_OFFSET)
+# define SRAM2A_END (SRAM2A_START + CONFIG_STM32WB_SRAM2A_USER_SIZE)
+#endif
+
+/* Set the range of SRAM2b as well, requires a third memory region */
+
+#ifdef CONFIG_STM32WB_SRAM2B_HEAP
+# define SRAM2B_START STM32WB_SRAM2B_BASE
+# define SRAM2B_END (SRAM2B_START + CONFIG_STM32WB_SRAM2B_USER_SIZE)
+#endif
+
+/* Some sanity checking. If multiple memory regions are defined, verify
+ * that CONFIG_MM_REGIONS is set to match the number of memory regions
+ * that we have been asked to add to the heap.
+ */
+
+#ifdef CONFIG_STM32WB_SRAM2A_HEAP
+# if SRAM2A_END > STM32WB_SRAM2A_BASE + STM32WB_SRAM2A_SIZE
+# error "SRAM2a heap memory region is out of it's physical address space"
+# endif
+#endif
+
+#ifdef CONFIG_STM32WB_SRAM2B_HEAP
+# if SRAM2B_END > STM32WB_SRAM2B_BASE + STM32WB_SRAM2B_SIZE
+# error "SRAM2b heap memory region is out of it's physical address space"
+# endif
+#endif
+
+#if CONFIG_MM_REGIONS < defined(CONFIG_STM32WB_SRAM2A_HEAP) + \
+ defined(CONFIG_STM32WB_SRAM2B_HEAP) + 1
+# error "You need more memory manager regions to support selected heap components"
+#endif
+
+#if CONFIG_MM_REGIONS > defined(CONFIG_STM32WB_SRAM2A_HEAP) + \
+ defined(CONFIG_STM32WB_SRAM2B_HEAP) + 1
+# warning "CONFIG_MM_REGIONS large enough but I do not know what some of the region(s) are"
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_heap_color
+ *
+ * Description:
+ * Set heap memory to a known, non-zero state to checking heap usage.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_HEAP_COLORATION
+static inline void up_heap_color(void *start, size_t size)
+{
+ memset(start, HEAP_COLOR, size);
+}
+#else
+# define up_heap_color(start,size)
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_allocate_heap
+ *
+ * Description:
+ * This function will be called to dynamically set aside the heap region.
+ *
+ * For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and
+ * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the
+ * size of the unprotected, user-space heap.
+ *
+ * If a protected kernel-space heap is provided, the kernel heap must be
+ * allocated (and protected) by an analogous up_allocate_kheap().
+ *
+ * The following memory map is assumed for the flat build:
+ *
+ * .data region. Size determined at link time.
+ * .bss region Size determined at link time.
+ * IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE.
+ * Heap. Extends to the end of SRAM.
+ *
+ * The following memory map is assumed for the kernel build:
+ *
+ * Kernel .data region. Size determined at link time.
+ * Kernel .bss region Size determined at link time.
+ * Kernel IDLE thread stack. Size determined by
+ * CONFIG_IDLETHREAD_STACKSIZE.
+ * Padding for alignment
+ * User .data region. Size determined at link time.
+ * User .bss region Size determined at link time.
+ * Kernel heap. Size determined by CONFIG_MM_KERNEL_HEAPSIZE.
+ * User heap. Extends to the end of SRAM.
+ *
+ ****************************************************************************/
+
+void up_allocate_heap(void **heap_start, size_t *heap_size)
+{
+#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
+ /* Get the unaligned size and position of the user-space heap.
+ * This heap begins after the user-space .bss section at an offset
+ * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
+ */
+
+ uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend +
+ CONFIG_MM_KERNEL_HEAPSIZE;
+ size_t usize = SRAM1_END - ubase;
+ int log2;
+
+ DEBUGASSERT(ubase < (uintptr_t)SRAM1_END);
+
+ /* Adjust that size to account for MPU alignment requirements.
+ * NOTE that there is an implicit assumption that the SRAM1_END
+ * is aligned to the MPU requirement.
+ */
+
+ log2 = (int)mpu_log2regionfloor(usize);
+ DEBUGASSERT((SRAM1_END & ((1 << log2) - 1)) == 0);
+
+ usize = (1 << log2);
+ ubase = SRAM1_END - usize;
+
+ /* Return the user-space heap settings */
+
+ board_autoled_on(LED_HEAPALLOCATE);
+ *heap_start = (void *)ubase;
+ *heap_size = usize;
+
+ /* Colorize the heap for debug */
+
+ up_heap_color((void *)ubase, usize);
+
+ /* Allow user-mode access to the user heap memory */
+
+ stm32wb_mpu_uheap((uintptr_t)ubase, usize);
+#else
+
+ /* Return the heap settings */
+
+ board_autoled_on(LED_HEAPALLOCATE);
+ *heap_start = (void *)g_idle_topstack;
+ *heap_size = SRAM1_END - g_idle_topstack;
+
+ /* Colorize the heap for debug */
+
+ up_heap_color(*heap_start, *heap_size);
+#endif
+}
+
+/****************************************************************************
+ * Name: up_allocate_kheap
+ *
+ * Description:
+ * For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and
+ * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function allocates
+ * (and protects) the kernel-space heap.
+ *
+ ****************************************************************************/
+
+#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
+void up_allocate_kheap(void **heap_start, size_t *heap_size)
+{
+ /* Get the unaligned size and position of the user-space heap.
+ * This heap begins after the user-space .bss section at an offset
+ * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
+ */
+
+ uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend +
+ CONFIG_MM_KERNEL_HEAPSIZE;
+ size_t usize = SRAM1_END - ubase;
+ int log2;
+
+ DEBUGASSERT(ubase < (uintptr_t)SRAM1_END);
+
+ /* Adjust that size to account for MPU alignment requirements.
+ * NOTE that there is an implicit assumption that the SRAM1_END
+ * is aligned to the MPU requirement.
+ */
+
+ log2 = (int)mpu_log2regionfloor(usize);
+ DEBUGASSERT((SRAM1_END & ((1 << log2) - 1)) == 0);
+
+ usize = (1 << log2);
+ ubase = SRAM1_END - usize;
+
+ /* Return the kernel heap settings (i.e., the part of the heap region
+ * that was not dedicated to the user heap).
+ */
+
+ *heap_start = (void *)USERSPACE->us_bssend;
+ *heap_size = ubase - (uintptr_t)USERSPACE->us_bssend;
+}
+#endif
+
+/****************************************************************************
+ * Name: arm_addregion
+ *
+ * Description:
+ * Memory may be added in non-contiguous chunks. Additional chunks are
+ * added by calling this function.
+ *
+ ****************************************************************************/
+
+#if CONFIG_MM_REGIONS > 1
+void arm_addregion(void)
+{
+ /* SRAM2a and SRAM2b memories contain a secure section, which cannot be
+ * read nor written by CPU1. The secure start address for each memory can
+ * be read from the option bytes SBRSA (SRAM2a) and SNBRSA (SRAM2b).
+ * The beginning of the SRAM2a memory is used for communication in between
+ * the 2 cores. SRAM2b is all secure for any CPU2 firmware supporting the
+ * Thread protocol. So the available memory for the user application may
+ * vary between different versions of the RF stack and can be obtained
+ * from the release notes for STM32WB coprocessor wireless binaries.
+ */
+
+#ifdef CONFIG_STM32WB_SRAM2A_HEAP
+
+#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
+
+ /* Allow user-mode access to the SRAM2a heap */
+
+ stm32wb_mpu_uheap((uintptr_t)SRAM2A_START, SRAM2A_END - SRAM2A_START);
+
+#endif
+
+ /* Colorize the heap for debug */
+
+ up_heap_color((void *)SRAM2A_START, SRAM2A_END - SRAM2A_START);
+
+ /* Add the SRAM2a user heap region. */
+
+ kumm_addregion((void *)SRAM2A_START, SRAM2A_END - SRAM2A_START);
+
+#endif /* CONFIG_STM32WB_SRAM2A_HEAP */
+
+#ifdef CONFIG_STM32WB_SRAM2B_HEAP
+
+#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
+
+ /* Allow user-mode access to the SRAM2b heap */
+
+ stm32wb_mpu_uheap((uintptr_t)SRAM2B_START, SRAM2B_END - SRAM2B_START);
+
+#endif
+
+ /* Colorize the heap for debug */
+
+ up_heap_color((void *)SRAM2B_START, SRAM2B_END - SRAM2B_START);
+
+ /* Add the SRAM2b user heap region. */
+
+ kumm_addregion((void *)SRAM2B_START, SRAM2B_END - SRAM2B_START);
+
+#endif /* CONFIG_STM32WB_SRAM2B_HEAP */
+}
+#endif
diff --git a/arch/arm/src/stm32wb/stm32wb_dma.c b/arch/arm/src/stm32wb/stm32wb_dma.c
new file mode 100644
index 0000000000..97d4119329
--- /dev/null
+++ b/arch/arm/src/stm32wb/stm32wb_dma.c
@@ -0,0 +1,1404 @@
+/****************************************************************************
+ * arch/arm/src/stm32wb/stm32wb_dma.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+
+#include "arm_internal.h"
+#include "sched/sched.h"
+#include "stm32wb_dma.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef CONFIG_STM32WB_DMAMUX
+# error "Configuration error, CONFIG_STM32WB_DMAMUX not defined!"
+#endif
+
+#define DMAMUX_NUM 1
+#define DMA_CONTROLLERS 2
+
+#ifdef CONFIG_STM32WB_DMA1
+# define DMA1_NCHAN 7
+#else
+# define DMA1_NCHAN 0
+#endif
+#ifdef CONFIG_STM32WB_DMA2
+# define DMA2_NCHAN 7
+#else
+# define DMA2_NCHAN 0
+#endif
+
+#define DMA1_FIRST (0)
+#define DMA1_LAST (DMA1_FIRST+DMA1_NCHAN)
+#define DMA2_FIRST (DMA1_LAST)
+#define DMA2_LAST (DMA2_FIRST+DMA2_NCHAN)
+
+/* All available DMA channels */
+
+#define DMA_NCHANNELS (DMA1_NCHAN+DMA2_NCHAN)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* This structure described one DMAMUX device */
+
+struct stm32wb_dmamux_s
+{
+ uint8_t id; /* DMAMUX id */
+ uint8_t nchan; /* DMAMUX channels */
+ uint32_t base; /* DMAMUX base address */
+};
+
+typedef const struct stm32wb_dmamux_s *DMA_MUX;
+
+/* This structure describes one DMA controller */
+
+struct stm32wb_dma_s
+{
+ uint8_t first; /* Offset in stm32wb_dmach_s array */
+ uint8_t nchan; /* Number of channels */
+ uint8_t dmamux_offset; /* DMAMUX channel offset */
+ uint32_t base; /* Base address */
+ DMA_MUX dmamux; /* DMAMUX associated with controller */
+};
+
+/* This structure describes one DMA channel (DMA1, DMA2) */
+
+struct stm32wb_dmach_s
+{
+ bool used; /* Channel in use */
+ uint8_t dmamux_req; /* Configured DMAMUX input request */
+ uint8_t ctrl; /* DMA controller */
+ uint8_t chan; /* DMA channel channel id */
+ uint8_t irq; /* DMA channel IRQ number */
+ uint8_t shift; /* IFCR bit shift value */
+ uint32_t base; /* DMA register channel base address */
+ dma_callback_t callback; /* Callback invoked when the DMA completes */
+ void *arg; /* Argument passed to callback function */
+};
+
+typedef struct stm32wb_dmach_s *DMA_CHANNEL;
+
+/* DMA operations */
+
+struct stm32wb_dma_ops_s
+{
+ /* Disable the DMA transfer */
+
+ void (*dma_disable)(DMA_CHANNEL dmachan);
+
+ /* DMA interrupt */
+
+ int (*dma_interrupt)(int irq, void *context, void *arg);
+
+ /* Setup the DMA */
+
+ void (*dma_setup)(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
+ size_t ntransfers, uint32_t ccr);
+
+ /* Start the DMA */
+
+ void (*dma_start)(DMA_HANDLE handle, dma_callback_t callback,
+ void *arg, bool half);
+
+ /* Read remaining DMA bytes */
+
+ size_t (*dma_residual)(DMA_HANDLE handle);
+
+ /* Check the DMA configuration */
+
+ bool (*dma_capable)(uint32_t maddr, uint32_t count, uint32_t ccr);
+
+#ifdef CONFIG_DEBUG_DMA_INFO
+ /* Sample the DMA registers */
+
+ void (*dma_sample)(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs);
+
+ /* Dump the DMA registers */
+
+ void (*dma_dump)(DMA_HANDLE handle,
+ const struct stm32wb_dmaregs_s *regs,
+ const char *msg);
+#endif
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+#if defined(CONFIG_STM32WB_DMA1) || defined(CONFIG_STM32WB_DMA2)
+static void stm32wb_dma12_disable(DMA_CHANNEL dmachan);
+static int stm32wb_dma12_interrupt(int irq, void *context, void *arg);
+static void stm32wb_dma12_setup(DMA_HANDLE handle, uint32_t paddr,
+ uint32_t maddr, size_t ntransfers,
+ uint32_t ccr);
+static void stm32wb_dma12_start(DMA_HANDLE handle, dma_callback_t callback,
+ void *arg, bool half);
+static size_t stm32wb_dma12_residual(DMA_HANDLE handle);
+#ifdef CONFIG_DEBUG_DMA_INFO
+static void stm32wb_dma12_sample(DMA_HANDLE handle,
+ struct stm32wb_dmaregs_s *regs);
+static void stm32wb_dma12_dump(DMA_HANDLE handle,
+ const struct stm32wb_dmaregs_s *regs,
+ const char *msg);
+#endif
+#endif
+
+static uint32_t dmachan_getbase(DMA_CHANNEL dmachan);
+static uint32_t dmabase_getreg(DMA_CHANNEL dmachan, uint32_t offset);
+static void dmabase_putreg(DMA_CHANNEL dmachan, uint32_t offset,
+ uint32_t value);
+static uint32_t dmachan_getreg(DMA_CHANNEL dmachan, uint32_t offset);
+static void dmachan_putreg(DMA_CHANNEL dmachan, uint32_t offset,
+ uint32_t value);
+static void dmamux_putreg(DMA_MUX dmamux, uint32_t offset, uint32_t value);
+#ifdef CONFIG_DEBUG_DMA_INFO
+static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset);
+static void stm32wb_dmamux_sample(DMA_MUX dmamux, uint8_t chan,
+ struct stm32wb_dmaregs_s *regs);
+static void stm32wb_dmamux_dump(DMA_MUX dmamux, uint8_t channel,
+ const struct stm32wb_dmaregs_s *regs);
+#endif
+static DMA_CHANNEL stm32wb_dma_channel_get(uint8_t channel,
+ uint8_t controller);
+static void stm32wb_gdma_limits_get(uint8_t controller, uint8_t *first,
+ uint8_t *last);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Operations specific to DMA controller */
+
+static const struct stm32wb_dma_ops_s g_dma_ops[DMA_CONTROLLERS] =
+{
+#ifdef CONFIG_STM32WB_DMA1
+ /* 0 - DMA1 */
+
+ {
+ .dma_disable = stm32wb_dma12_disable,
+ .dma_interrupt = stm32wb_dma12_interrupt,
+ .dma_setup = stm32wb_dma12_setup,
+ .dma_start = stm32wb_dma12_start,
+ .dma_residual = stm32wb_dma12_residual,
+#ifdef CONFIG_DEBUG_DMA_INFO
+ .dma_sample = stm32wb_dma12_sample,
+ .dma_dump = stm32wb_dma12_dump,
+#endif
+ },
+#else
+ {
+ NULL
+ },
+#endif
+
+#ifdef CONFIG_STM32WB_DMA2
+ /* 1 - DMA2 */
+
+ {
+ .dma_disable = stm32wb_dma12_disable,
+ .dma_interrupt = stm32wb_dma12_interrupt,
+ .dma_setup = stm32wb_dma12_setup,
+ .dma_start = stm32wb_dma12_start,
+ .dma_residual = stm32wb_dma12_residual,
+#ifdef CONFIG_DEBUG_DMA_INFO
+ .dma_sample = stm32wb_dma12_sample,
+ .dma_dump = stm32wb_dma12_dump,
+#endif
+ }
+#else
+ {
+ NULL
+ }
+#endif
+};
+
+/* This array describes the state of DMAMUX controller */
+
+static const struct stm32wb_dmamux_s g_dmamux[DMAMUX_NUM] =
+{
+ {
+ .id = 1,
+ .nchan = 14, /* 0-6 - DMA1, 7-13 - DMA2 */
+ .base = STM32WB_DMAMUX1_BASE
+ }
+};
+
+/* This array describes the state of each controller */
+
+static const struct stm32wb_dma_s g_dma[DMA_NCHANNELS] =
+{
+ /* 0 - DMA1 */
+
+ {
+ .base = STM32WB_DMA1_BASE,
+ .first = DMA1_FIRST,
+ .nchan = DMA1_NCHAN,
+ .dmamux = &g_dmamux[DMAMUX1], /* DMAMUX1 channels 0-6 */
+ .dmamux_offset = 0
+ },
+
+ /* 1 - DMA2 */
+
+ {
+ .base = STM32WB_DMA2_BASE,
+ .first = DMA2_FIRST,
+ .nchan = DMA2_NCHAN,
+ .dmamux = &g_dmamux[DMAMUX1], /* DMAMUX1 channels 7-13 */
+ .dmamux_offset = 7
+ }
+};
+
+/* This array describes the state of each DMA channel. */
+
+static struct stm32wb_dmach_s g_dmach[DMA_NCHANNELS] =
+{
+#ifdef CONFIG_STM32WB_DMA1
+ /* DMA1 */
+
+ {
+ .ctrl = DMA1,
+ .chan = 0,
+ .irq = STM32WB_IRQ_DMA1CH1,
+ .shift = DMA_CHAN_SHIFT(0),
+ .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(0),
+ },
+
+ {
+ .ctrl = DMA1,
+ .chan = 1,
+ .irq = STM32WB_IRQ_DMA1CH2,
+ .shift = DMA_CHAN_SHIFT(1),
+ .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(1),
+ },
+
+ {
+ .ctrl = DMA1,
+ .chan = 2,
+ .irq = STM32WB_IRQ_DMA1CH3,
+ .shift = DMA_CHAN_SHIFT(2),
+ .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(2),
+ },
+
+ {
+ .ctrl = DMA1,
+ .chan = 3,
+ .irq = STM32WB_IRQ_DMA1CH4,
+ .shift = DMA_CHAN_SHIFT(3),
+ .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(3),
+ },
+
+ {
+ .ctrl = DMA1,
+ .chan = 4,
+ .irq = STM32WB_IRQ_DMA1CH5,
+ .shift = DMA_CHAN_SHIFT(4),
+ .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(4),
+ },
+
+ {
+ .ctrl = DMA1,
+ .chan = 5,
+ .irq = STM32WB_IRQ_DMA1CH6,
+ .shift = DMA_CHAN_SHIFT(5),
+ .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(5),
+ },
+
+ {
+ .ctrl = DMA1,
+ .chan = 6,
+ .irq = STM32WB_IRQ_DMA1CH7,
+ .shift = DMA_CHAN_SHIFT(6),
+ .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(6),
+ },
+#endif
+
+#ifdef CONFIG_STM32WB_DMA2
+ /* DMA2 */
+
+ {
+ .ctrl = DMA2,
+ .chan = 0,
+ .irq = STM32WB_IRQ_DMA2CH1,
+ .shift = DMA_CHAN_SHIFT(0),
+ .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(0),
+ },
+
+ {
+ .ctrl = DMA2,
+ .chan = 1,
+ .irq = STM32WB_IRQ_DMA2CH2,
+ .shift = DMA_CHAN_SHIFT(1),
+ .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(1),
+ },
+
+ {
+ .ctrl = DMA2,
+ .chan = 2,
+ .irq = STM32WB_IRQ_DMA2CH3,
+ .shift = DMA_CHAN_SHIFT(2),
+ .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(2),
+ },
+
+ {
+ .ctrl = DMA2,
+ .chan = 3,
+ .irq = STM32WB_IRQ_DMA2CH4,
+ .shift = DMA_CHAN_SHIFT(3),
+ .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(3),
+ },
+
+ {
+ .ctrl = DMA2,
+ .chan = 4,
+ .irq = STM32WB_IRQ_DMA2CH5,
+ .shift = DMA_CHAN_SHIFT(4),
+ .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(4),
+ },
+
+ {
+ .ctrl = DMA2,
+ .chan = 5,
+ .irq = STM32WB_IRQ_DMA2CH6,
+ .shift = DMA_CHAN_SHIFT(5),
+ .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(5),
+ },
+
+ {
+ .ctrl = DMA2,
+ .chan = 6,
+ .irq = STM32WB_IRQ_DMA2CH7,
+ .shift = DMA_CHAN_SHIFT(6),
+ .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(6),
+ },
+#endif
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * DMA register access functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: dmachan_getbase
+ *
+ * Description:
+ * Get base DMA address for dmachan
+ *
+ ****************************************************************************/
+
+static uint32_t dmachan_getbase(DMA_CHANNEL dmachan)
+{
+ uint8_t controller = dmachan->ctrl;
+
+ return g_dma[controller].base;
+}
+
+/****************************************************************************
+ * Name: dmabase_getreg
+ *
+ * Description:
+ * Get non-channel register from DMA controller
+ *
+ ****************************************************************************/
+
+static uint32_t dmabase_getreg(DMA_CHANNEL dmachan, uint32_t offset)
+{
+ uint32_t dmabase = dmachan_getbase(dmachan);
+
+ return getreg32(dmabase + offset);
+}
+
+/****************************************************************************
+ * Name: dmabase_putreg
+ *
+ * Description:
+ * Write to non-channel register in DMA controller
+ *
+ ****************************************************************************/
+
+static void dmabase_putreg(DMA_CHANNEL dmachan, uint32_t offset,
+ uint32_t value)
+{
+ uint32_t dmabase = dmachan_getbase(dmachan);
+
+ putreg32(value, dmabase + offset);
+}
+
+/****************************************************************************
+ * Name: dmachan_getreg
+ *
+ * Description:
+ * Get channel register.
+ *
+ ****************************************************************************/
+
+static uint32_t dmachan_getreg(DMA_CHANNEL dmachan, uint32_t offset)
+{
+ return getreg32(dmachan->base + offset);
+}
+
+/****************************************************************************
+ * Name: dmachan_putreg
+ *
+ * Description:
+ * Write to channel register.
+ *
+ ****************************************************************************/
+
+static void dmachan_putreg(DMA_CHANNEL dmachan, uint32_t offset,
+ uint32_t value)
+{
+ putreg32(value, dmachan->base + offset);
+}
+
+/****************************************************************************
+ * Name: dmamux_getreg
+ *
+ * Description:
+ * Write to DMAMUX
+ *
+ ****************************************************************************/
+
+static void dmamux_putreg(DMA_MUX dmamux, uint32_t offset, uint32_t value)
+{
+ putreg32(value, dmamux->base + offset);
+}
+
+/****************************************************************************
+ * Name: dmamux_getreg
+ *
+ * Description:
+ * Get DMAMUX register.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_DMA_INFO
+static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset)
+{
+ return getreg32(dmamux->base + offset);
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32wb_dma_channel_get
+ *
+ * Description:
+ * Get the g_dmach table entry associated with a given DMA controller
+ * and channel number.
+ *
+ ****************************************************************************/
+
+static DMA_CHANNEL stm32wb_dma_channel_get(uint8_t channel,
+ uint8_t controller)
+{
+ uint8_t first = 0;
+ uint8_t nchan = 0;
+
+ /* Get limits for g_dma array */
+
+ stm32wb_gdma_limits_get(controller, &first, &nchan);
+
+ DEBUGASSERT(channel <= nchan);
+
+ return &g_dmach[first + channel];
+}
+
+/****************************************************************************
+ * Name: stm32wb_gdma_limits_get
+ *
+ * Description:
+ * Get g_dma array limits for a given DMA controller.
+ *
+ ****************************************************************************/
+
+static void stm32wb_gdma_limits_get(uint8_t controller, uint8_t *first,
+ uint8_t *nchan)
+{
+ DEBUGASSERT(first != NULL);
+ DEBUGASSERT(nchan != NULL);
+
+ DEBUGASSERT(controller >= DMA1 && controller <= DMA2);
+
+ *first = g_dma[controller].first;
+ *nchan = g_dma[controller].nchan;
+}
+
+/****************************************************************************
+ * DMA controller functions
+ ****************************************************************************/
+
+#if defined(CONFIG_STM32WB_DMA1) || defined(CONFIG_STM32WB_DMA2)
+
+/****************************************************************************
+ * Name: stm32wb_dma12_disable
+ *
+ * Description:
+ * Disable DMA channel (DMA1/DMA2)
+ *
+ ****************************************************************************/
+
+static void stm32wb_dma12_disable(DMA_CHANNEL dmachan)
+{
+ uint32_t regval;
+
+ DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2);
+
+ /* Disable all interrupts at the DMA controller */
+
+ regval = dmachan_getreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET);
+ regval &= ~DMA_CCR_ALLINTS;
+
+ /* Disable the DMA channel */
+
+ regval &= ~DMA_CCR_EN;
+ dmachan_putreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET, regval);
+
+ /* Clear pending channel interrupts */
+
+ dmabase_putreg(dmachan, STM32WB_DMA_IFCR_OFFSET,
+ DMA_ISR_CHAN_MASK(dmachan->chan));
+}
+
+/****************************************************************************
+ * Name: stm32wb_dma12_interrupt
+ *
+ * Description:
+ * DMA channel interrupt handler
+ *
+ ****************************************************************************/
+
+static int stm32wb_dma12_interrupt(int irq, void *context, void *arg)
+{
+ DMA_CHANNEL dmachan;
+ uint32_t isr;
+ uint8_t channel;
+ uint8_t controller;
+
+ /* Get the channel and the controller that generated the interrupt */
+
+ if (0)
+ {
+ }
+#ifdef CONFIG_STM32WB_DMA1
+ else if (irq >= STM32WB_IRQ_DMA1CH1 && irq <= STM32WB_IRQ_DMA1CH7)
+ {
+ channel = irq - STM32WB_IRQ_DMA1CH1;
+ controller = DMA1;
+ }
+#endif
+#ifdef CONFIG_STM32WB_DMA2
+ else if (irq >= STM32WB_IRQ_DMA2CH1 && irq <= STM32WB_IRQ_DMA2CH5)
+ {
+ channel = irq - STM32WB_IRQ_DMA2CH1;
+ controller = DMA2;
+ }
+ else if (irq >= STM32WB_IRQ_DMA2CH6 && irq <= STM32WB_IRQ_DMA2CH7)
+ {
+ channel = irq - STM32WB_IRQ_DMA2CH6 + (6 - 1);
+ controller = DMA2;
+ }
+#endif
+ else
+ {
+ DEBUGPANIC();
+ return OK;
+ }
+
+ /* Get the channel structure from the stream and controller numbers */
+
+ dmachan = stm32wb_dma_channel_get(channel, controller);
+
+ /* Get the interrupt status (for this channel only) */
+
+ isr = dmabase_getreg(dmachan, STM32WB_DMA_ISR_OFFSET) &
+ DMA_ISR_CHAN_MASK(dmachan->chan);
+
+ /* Invoke the callback */
+
+ if (dmachan->callback)
+ {
+ dmachan->callback(dmachan, isr >> DMA_ISR_CHAN_SHIFT(dmachan->chan),
+ dmachan->arg);
+ }
+
+ /* Clear the interrupts we are handling */
+
+ dmabase_putreg(dmachan, STM32WB_DMA_IFCR_OFFSET, isr);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: stm32wb_dma12_setup
+ *
+ * Description:
+ * Configure DMA before using
+ *
+ ****************************************************************************/
+
+static void stm32wb_dma12_setup(DMA_HANDLE handle, uint32_t paddr,
+ uint32_t maddr, size_t ntransfers,
+ uint32_t ccr)
+{
+ DMA_CHANNEL dmachan = (DMA_CHANNEL)handle;
+ uint32_t regval;
+
+ DEBUGASSERT(handle != NULL);
+ DEBUGASSERT(ntransfers < 65536);
+
+ DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2);
+
+ dmainfo("paddr: %08" PRIx32 " maddr: %08" PRIx32
+ " ntransfers: %zd ccr: %08" PRIx32 "\n",
+ paddr, maddr, ntransfers, ccr);
+
+#ifdef CONFIG_STM32WB_DMACAPABLE
+ DEBUGASSERT(g_dma_ops[dmachan->ctrl].dma_capable(maddr, ntransfers, ccr));
+#endif
+
+ /* Then DMA_CNDTRx register can only be modified if the DMA channel is
+ * disabled.
+ */
+
+ regval = dmachan_getreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET);
+ regval &= ~(DMA_CCR_EN);
+ dmachan_putreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET, regval);
+
+ /* Set the peripheral register address in the DMA_CPARx register. The data
+ * will be moved from/to this address to/from the memory after the
+ * peripheral event.
+ */
+
+ dmachan_putreg(dmachan, STM32WB_DMACHAN_CPAR_OFFSET, paddr);
+
+ /* Set the memory address in the DMA_CMARx register. The data will be
+ * written to or read from this memory after the peripheral event.
+ */
+
+ dmachan_putreg(dmachan, STM32WB_DMACHAN_CMAR_OFFSET, maddr);
+
+ /* Configure the total number of data to be transferred in the DMA_CNDTRx
+ * register. After each peripheral event, this value will be decremented.
+ */
+
+ dmachan_putreg(dmachan, STM32WB_DMACHAN_CNDTR_OFFSET, ntransfers);
+
+ /* Configure the channel priority using the PL[1:0] bits in the DMA_CCRx
+ * register. Configure data transfer direction, circular mode, peripheral
+ * & memory incremented mode, peripheral & memory data size, and interrupt
+ * after half and/or full transfer in the DMA_CCRx register.
+ */
+
+ regval = dmachan_getreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET);
+ regval &= ~(DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK |
+ DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC |
+ DMA_CCR_CIRC | DMA_CCR_DIR);
+ ccr &= (DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK |
+ DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC |
+ DMA_CCR_CIRC | DMA_CCR_DIR);
+ regval |= ccr;
+ dmachan_putreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET, regval);
+}
+
+/****************************************************************************
+ * Name: stm32wb_dma12_start
+ *
+ * Description:
+ * Start the standard DMA transfer
+ ****************************************************************************/
+
+static void stm32wb_dma12_start(DMA_HANDLE handle, dma_callback_t callback,
+ void *arg, bool half)
+{
+ DMA_CHANNEL dmachan = (DMA_CHANNEL)handle;
+ uint32_t ccr;
+
+ DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2);
+
+ /* Save the callback info. This will be invoked when the DMA completes */
+
+ dmachan->callback = callback;
+ dmachan->arg = arg;
+
+ /* Activate the channel by setting the ENABLE bit in the DMA_CCRx register.
+ * As soon as the channel is enabled, it can serve any DMA request from the
+ * peripheral connected on the channel.
+ */
+
+ ccr = dmachan_getreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET);
+ ccr |= DMA_CCR_EN;
+
+ /* In normal mode, interrupt at either half or full completion. In circular
+ * mode, always interrupt on buffer wrap, and optionally interrupt at the
+ * halfway point.
+ */
+
+ if ((ccr & DMA_CCR_CIRC) == 0)
+ {
+ /* Once half of the bytes are transferred, the half-transfer flag
+ * (HTIF) is set and an interrupt is generated if the Half-Transfer
+ * Interrupt Enable bit (HTIE) is set. At the end of the transfer,
+ * the Transfer Complete Flag (TCIF) is set and an interrupt is
+ * generated if the Transfer Complete Interrupt Enable bit (TCIE)
+ * is set.
+ */
+
+ ccr |= (half ? (DMA_CCR_HTIE | DMA_CCR_TEIE) :
+ (DMA_CCR_TCIE | DMA_CCR_TEIE));
+ }
+ else
+ {
+ /* In nonstop mode, when the transfer completes it immediately resets
+ * and starts again. The transfer-complete interrupt is thus always
+ * enabled, and the half-complete interrupt can be used in circular
+ * mode to determine when the buffer is half-full, or in
+ * double-buffered mode to determine when one of the two buffers
+ * is full.
+ */
+
+ ccr |= (half ? DMA_CCR_HTIE : 0) | DMA_CCR_TCIE | DMA_CCR_TEIE;
+ }
+
+ dmachan_putreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET, ccr);
+}
+
+/****************************************************************************
+ * Name: stm32wb_dma12_residual
+ ****************************************************************************/
+
+static size_t stm32wb_dma12_residual(DMA_HANDLE handle)
+{
+ DMA_CHANNEL dmachan = (DMA_CHANNEL)handle;
+
+ DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2);
+
+ return dmachan_getreg(dmachan, STM32WB_DMACHAN_CNDTR_OFFSET);
+}
+
+/****************************************************************************
+ * Name: stm32wb_dma12_sample
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_DMA_INFO
+void stm32wb_dma12_sample(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs)
+{
+ DMA_CHANNEL dmachan = (DMA_CHANNEL)handle;
+ irqstate_t flags;
+
+ flags = enter_critical_section();
+
+ regs->isr = dmabase_getreg(dmachan, STM32WB_DMA_ISR_OFFSET);
+ regs->ccr = dmachan_getreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET);
+ regs->cndtr = dmachan_getreg(dmachan, STM32WB_DMACHAN_CNDTR_OFFSET);
+ regs->cpar = dmachan_getreg(dmachan, STM32WB_DMACHAN_CPAR_OFFSET);
+ regs->cmar = dmachan_getreg(dmachan, STM32WB_DMACHAN_CMAR_OFFSET);
+
+ stm32wb_dmamux_sample(g_dma[dmachan->ctrl].dmamux,
+ dmachan->chan + g_dma[dmachan->ctrl].dmamux_offset,
+ regs);
+
+ leave_critical_section(flags);
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32wb_dma12_dump
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_DMA_INFO
+static void stm32wb_dma12_dump(DMA_HANDLE handle,
+ const struct stm32wb_dmaregs_s *regs,
+ const char *msg)
+{
+ DMA_CHANNEL dmachan = (DMA_CHANNEL)handle;
+
+ DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2);
+
+ uint32_t dmabase = dmachan_getbase(dmachan);
+
+ dmainfo("DMA%d Registers: %s\n",
+ dmachan->ctrl + 1,
+ msg);
+ dmainfo(" ISR[%08x]: %08x\n",
+ dmabase + STM32WB_DMA_ISR_OFFSET,
+ regs->isr);
+ dmainfo(" CCR[%08x]: %08x\n",
+ dmachan->base + STM32WB_DMACHAN_CCR_OFFSET,
+ regs->ccr);
+ dmainfo(" CNDTR[%08x]: %08x\n",
+ dmachan->base + STM32WB_DMACHAN_CNDTR_OFFSET,
+ regs->cndtr);
+ dmainfo(" CPAR[%08x]: %08x\n",
+ dmachan->base + STM32WB_DMACHAN_CPAR_OFFSET,
+ regs->cpar);
+ dmainfo(" CMAR[%08x]: %08x\n",
+ dmachan->base + STM32WB_DMACHAN_CMAR_OFFSET,
+ regs->cmar);
+
+ stm32wb_dmamux_dump(g_dma[dmachan->ctrl].dmamux,
+ dmachan->chan + g_dma[dmachan->ctrl].dmamux_offset,
+ regs);
+}
+#endif
+
+#endif /* CONFIG_STM32WB_DMA1 || CONFIG_STM32WB_DMA2 */
+
+/****************************************************************************
+ * Name: stm32wb_dmamux_sample
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_DMA_INFO
+static void stm32wb_dmamux_sample(DMA_MUX dmamux, uint8_t chan,
+ struct stm32wb_dmaregs_s *regs)
+{
+ regs->dmamux.ccr = dmamux_getreg(dmamux, STM32WB_DMAMUX_CXCR_OFFSET(chan));
+ regs->dmamux.csr = dmamux_getreg(dmamux, STM32WB_DMAMUX_CSR_OFFSET);
+ regs->dmamux.rg0cr = dmamux_getreg(dmamux, STM32WB_DMAMUX_RG0CR_OFFSET);
+ regs->dmamux.rg1cr = dmamux_getreg(dmamux, STM32WB_DMAMUX_RG1CR_OFFSET);
+ regs->dmamux.rg2cr = dmamux_getreg(dmamux, STM32WB_DMAMUX_RG2CR_OFFSET);
+ regs->dmamux.rg3cr = dmamux_getreg(dmamux, STM32WB_DMAMUX_RG3CR_OFFSET);
+ regs->dmamux.rgsr = dmamux_getreg(dmamux, STM32WB_DMAMUX_RGSR_OFFSET);
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32wb_dmamux_dump
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_DMA_INFO
+static void stm32wb_dmamux_dump(DMA_MUX dmamux, uint8_t channel,
+ const struct stm32wb_dmaregs_s *regs)
+{
+ dmainfo("DMAMUX%d CH=%d\n", dmamux->id, channel);
+ dmainfo(" CCR[%08x]: %08x\n",
+ dmamux->base + STM32WB_DMAMUX_CXCR_OFFSET(channel),
+ regs->dmamux.ccr);
+ dmainfo(" CSR[%08x]: %08x\n",
+ dmamux->base + STM32WB_DMAMUX_CSR_OFFSET, regs->dmamux.csr);
+ dmainfo(" RG0CR[%08x]: %08x\n",
+ dmamux->base + STM32WB_DMAMUX_RG0CR_OFFSET, regs->dmamux.rg0cr);
+ dmainfo(" RG1CR[%08x]: %08x\n",
+ dmamux->base + STM32WB_DMAMUX_RG1CR_OFFSET, regs->dmamux.rg1cr);
+ dmainfo(" RG2CR[%08x]: %08x\n",
+ dmamux->base + STM32WB_DMAMUX_RG2CR_OFFSET, regs->dmamux.rg2cr);
+ dmainfo(" RG3CR[%08x]: %08x\n",
+ dmamux->base + STM32WB_DMAMUX_RG3CR_OFFSET, regs->dmamux.rg3cr);
+ dmainfo(" RGSR[%08x]: %08x\n",
+ dmamux->base + STM32WB_DMAMUX_RGSR_OFFSET, regs->dmamux.rgsr);
+};
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm_dma_initialize
+ *
+ * Description:
+ * Initialize the DMA subsystem (DMA1, DMA2)
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void weak_function arm_dma_initialize(void)
+{
+ DMA_CHANNEL dmachan;
+ uint8_t controller;
+ int channel;
+
+ dmainfo("Initialize DMA\n");
+
+ /* Initialize DMA channels */
+
+ for (channel = 0; channel < DMA_NCHANNELS; channel++)
+ {
+ dmachan = &g_dmach[channel];
+
+ /* Initialize flag */
+
+ dmachan->used = false;
+
+ /* Get DMA controller associated with channel */
+
+ controller = dmachan->ctrl;
+
+ DEBUGASSERT(controller >= DMA1 && controller <= DMA2);
+
+ /* Attach standard DMA interrupt vectors */
+
+ irq_attach(dmachan->irq, g_dma_ops[controller].dma_interrupt,
+ dmachan);
+
+ /* Disable the DMA channel */
+
+ g_dma_ops[controller].dma_disable(dmachan);
+
+ /* Enable the IRQ at the NVIC (still disabled at the DMA controller) */
+
+ up_enable_irq(dmachan->irq);
+ }
+}
+
+/****************************************************************************
+ * Name: stm32wb_dmachannel
+ *
+ * Description:
+ * Allocate a DMA channel. This function gives the caller mutually
+ * exclusive access to the DMA channel specified by the 'dmamap' argument.
+ * It is common for both DMA controllers (DMA1 and DMA2).
+ *
+ * Input Parameters:
+ * dmamap - Identifies the stream/channel resource. For the STM32WB, this
+ * is a bit-encoded value as provided by the DMAMAP_* definitions
+ * in hardware/stm32wb_dmamux.h
+ *
+ * Returned Value:
+ * One success, this function returns a non-NULL, void* DMA channel
+ * handle. NULL is returned on any failure. This function can fail only
+ * if no DMA channel is available.
+ *
+ * Assumptions:
+ * - The caller does not hold he DMA channel.
+ * - The caller can wait for the DMA channel to be freed if it is no
+ * available.
+ *
+ ****************************************************************************/
+
+DMA_HANDLE stm32wb_dmachannel(unsigned int dmamap)
+{
+ DMA_CHANNEL dmachan;
+ uint8_t dmamux_req;
+ irqstate_t flags;
+ uint8_t controller;
+ uint8_t first = 0;
+ uint8_t nchan = 0;
+ int item = -1;
+ int i;
+
+ /* Get DMA controller from encoded DMAMAP value */
+
+ controller = DMAMAP_CONTROLLER(dmamap);
+ DEBUGASSERT(controller >= DMA1 && controller <= DMA2);
+
+ /* Get DMAMUX channel from encoded DMAMAP value */
+
+ dmamux_req = DMAMAP_REQUEST(dmamap);
+
+ /* Get g_dma array limits for given controller */
+
+ stm32wb_gdma_limits_get(controller, &first, &nchan);
+
+ /* Find available channel for given controller */
+
+ flags = enter_critical_section();
+ for (i = first; i < first + nchan; i++)
+ {
+ if (!g_dmach[i].used)
+ {
+ item = i;
+ g_dmach[i].used = true;
+ g_dmach[i].dmamux_req = dmamux_req;
+ break;
+ }
+ }
+
+ leave_critical_section(flags);
+
+ dmainfo("ctrl=%d item=%d\n", controller, item);
+
+ if (item == -1)
+ {
+ dmainfo("No available DMA chan for CTRL=%d\n",
+ controller);
+
+ /* No available channel */
+
+ return NULL;
+ }
+
+ /* Assign DMA item */
+
+ dmachan = &g_dmach[item];
+
+ dmainfo("Get g_dmach[%d] CTRL=%d CH=%d\n", i, controller, dmachan->chan);
+
+ /* Be sure that we have proper DMA controller */
+
+ DEBUGASSERT(dmachan->ctrl == controller);
+
+ return (DMA_HANDLE)dmachan;
+}
+
+/****************************************************************************
+ * Name: stm32wb_dmafree
+ *
+ * Description:
+ * Release a DMA channel and unmap DMAMUX if required.
+ *
+ * NOTE: The 'handle' used in this argument must NEVER be used again
+ * until stm32wb_dmachannel() is called again to re-gain access to the
+ * channel.
+ *
+ * Returned Value:
+ * None
+ *
+ * Assumptions:
+ * - The caller holds the DMA channel.
+ * - There is no DMA in progress
+ *
+ ****************************************************************************/
+
+void stm32wb_dmafree(DMA_HANDLE handle)
+{
+ DMA_CHANNEL dmachan = (DMA_CHANNEL)handle;
+ uint8_t controller;
+ irqstate_t flags;
+
+ DEBUGASSERT(handle != NULL);
+
+ /* Get DMA controller */
+
+ controller = dmachan->ctrl;
+ DEBUGASSERT(controller >= DMA1 && controller <= DMA2);
+
+ dmainfo("Free g_dmach[%d] CTRL=%d CH=%d\n", dmachan - g_dmach, controller,
+ dmachan->chan);
+ UNUSED(controller);
+
+ /* Release the channel */
+
+ flags = enter_critical_section();
+ dmachan->used = false;
+ dmachan->dmamux_req = 0;
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: stm32wb_dmasetup
+ *
+ * Description:
+ * Configure DMA before using
+ *
+ ****************************************************************************/
+
+void stm32wb_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
+ size_t ntransfers, uint32_t ccr)
+{
+ DMA_CHANNEL dmachan = (DMA_CHANNEL)handle;
+ uint8_t controller;
+
+ DEBUGASSERT(handle != NULL);
+
+ /* Get DMA controller */
+
+ controller = dmachan->ctrl;
+ DEBUGASSERT(controller >= DMA1 && controller <= DMA2);
+
+ g_dma_ops[controller].dma_setup(handle, paddr, maddr, ntransfers, ccr);
+}
+
+/****************************************************************************
+ * Name: stm32wb_dmastart
+ *
+ * Description:
+ * Start the DMA transfer
+ *
+ * Assumptions:
+ * - DMA handle allocated by stm32wb_dmachannel()
+ * - No DMA in progress
+ *
+ ****************************************************************************/
+
+void stm32wb_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg,
+ bool half)
+{
+ DMA_CHANNEL dmachan = (DMA_CHANNEL)handle;
+ DMA_MUX dmamux;
+ uint32_t regval;
+ uint8_t dmamux_chan;
+ uint8_t controller;
+
+ DEBUGASSERT(handle != NULL);
+
+ /* Get DMA controller */
+
+ controller = dmachan->ctrl;
+ DEBUGASSERT(controller >= DMA1 && controller <= DMA2);
+
+ /* Recommended channel configure procedure in reference manual:
+ * 1. Set and configure the DMA channel y, except enabling the channel y.
+ * 2. Set and configure the related DMAMUX y channel.
+ * 3. Last, activate the DMA channel y.
+ */
+
+ /* Get DMAMUX associated with DMA controller */
+
+ dmamux = g_dma[controller].dmamux;
+ dmamux_chan = dmachan->chan + g_dma[controller].dmamux_offset;
+
+ /* DMAMUX Set DMA channel source */
+
+ regval = dmachan->dmamux_req << DMAMUX_CCR_DMAREQID_SHIFT;
+ dmamux_putreg(dmamux, STM32WB_DMAMUX_CXCR_OFFSET(dmamux_chan), regval);
+
+ /* Enable DMA channel */
+
+ g_dma_ops[controller].dma_start(handle, callback, arg, half);
+}
+
+/****************************************************************************
+ * Name: stm32wb_dmastop
+ *
+ * Description:
+ * Cancel the DMA. After stm32wb_dmastop() is called, the DMA channel is
+ * reset and stm32wb_dmasetup() must be called before stm32wb_dmastart()
+ * can be called again
+ *
+ * Assumptions:
+ * - DMA handle allocated by stm32wb_dmachannel()
+ *
+ ****************************************************************************/
+
+void stm32wb_dmastop(DMA_HANDLE handle)
+{
+ DMA_CHANNEL dmachan = (DMA_CHANNEL)handle;
+ DMA_MUX dmamux;
+ uint8_t dmamux_chan;
+ uint8_t controller;
+
+ DEBUGASSERT(handle != NULL);
+
+ /* Get DMA controller */
+
+ controller = dmachan->ctrl;
+ DEBUGASSERT(controller >= DMA1 && controller <= DMA2);
+
+ /* Get DMAMUX associated with DMA controller */
+
+ dmamux = g_dma[controller].dmamux;
+ dmamux_chan = dmachan->chan + g_dma[controller].dmamux_offset;
+
+ /* Disable DMA channel */
+
+ g_dma_ops[controller].dma_disable(dmachan);
+
+ /* DMAMUX Clear DMA channel source */
+
+ dmamux_putreg(dmamux, STM32WB_DMAMUX_CXCR_OFFSET(dmamux_chan), 0);
+}
+
+/****************************************************************************
+ * Name: stm32wb_dmaresidual
+ *
+ * Description:
+ * Read the DMA bytes-remaining register.
+ *
+ * Assumptions:
+ * - DMA handle allocated by stm32wb_dmachannel()
+ *
+ ****************************************************************************/
+
+size_t stm32wb_dmaresidual(DMA_HANDLE handle)
+{
+ DMA_CHANNEL dmachan = (DMA_CHANNEL)handle;
+ uint8_t controller;
+
+ DEBUGASSERT(handle != NULL);
+
+ /* Get DMA controller */
+
+ controller = dmachan->ctrl;
+ DEBUGASSERT(controller >= DMA1 && controller <= DMA2);
+
+ return g_dma_ops[controller].dma_residual(handle);
+}
+
+/****************************************************************************
+ * Name: stm32wb_dmacapable
+ *
+ * Description:
+ * Check if the DMA controller can transfer data to/from given memory
+ * address. This depends on the internal connections in the ARM bus matrix
+ * of the processor. Note that this only applies to memory addresses, it
+ * will return false for any peripheral address.
+ *
+ * Input Parameters:
+ * cfg - DMA transfer configuration
+ *
+ * Returned Value:
+ * True, if transfer is possible.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_STM32WB_DMACAPABLE
+bool stm32wb_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr)
+{
+ unsigned int msize_shift;
+ uint32_t transfer_size;
+ uint32_t mend;
+
+ /* Verify that the address conforms to the memory transfer size.
+ * Transfers to/from memory performed by the DMA controller are
+ * required to be aligned to their size.
+ *
+ * Datasheet 3.13 claims
+ * "Access to Flash, SRAM, APB and AHB peripherals as source
+ * and destination"
+ */
+
+ switch (ccr & DMA_CCR_MSIZE_MASK)
+ {
+ case DMA_CCR_MSIZE_8BITS:
+ msize_shift = 0;
+ break;
+
+ case DMA_CCR_MSIZE_16BITS:
+ msize_shift = 1;
+ break;
+
+ case DMA_CCR_MSIZE_32BITS:
+ msize_shift = 2;
+ break;
+
+ default:
+ return false;
+ }
+
+ transfer_size = 1 << msize_shift;
+
+ if ((maddr & (transfer_size - 1)) != 0)
+ {
+ return false;
+ }
+
+ /* Verify that the transfer is to a memory region that supports DMA. */
+
+ mend = maddr + (count << msize_shift) - 1;
+
+ if ((maddr & STM32WB_REGION_MASK) != (mend & STM32WB_REGION_MASK))
+ {
+ return false;
+ }
+
+ switch (maddr & STM32WB_REGION_MASK)
+ {
+ case STM32WB_PERIPH_BASE:
+ case STM32WB_FSMC_BASE:
+ case STM32WB_FSMC_BANK1:
+ case STM32WB_FSMC_BANK2:
+ case STM32WB_FSMC_BANK3:
+ case STM32WB_QSPI_BANK:
+ case STM32WB_SRAM_BASE:
+ case STM32WB_SRAM2_BASE:
+ case STM32WB_SRAM3_BASE:
+ case STM32WB_CODE_BASE:
+
+ /* All RAM and flash is supported */
+
+ return true;
+
+ default:
+
+ /* Everything else is unsupported by DMA */
+
+ return false;
+ }
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32wb_dmasample
+ *
+ * Description:
+ * Sample DMA register contents
+ *
+ * Assumptions:
+ * - DMA handle allocated by stm32wb_dmachannel()
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_DMA_INFO
+void stm32wb_dmasample(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs)
+{
+ DMA_CHANNEL dmachan = (DMA_CHANNEL)handle;
+ uint8_t controller;
+
+ DEBUGASSERT(handle != NULL);
+
+ /* Get DMA controller */
+
+ controller = dmachan->ctrl;
+ DEBUGASSERT(controller >= DMA1 && controller <= DMA2);
+
+ g_dma_ops[controller].dma_sample(handle, regs);
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32wb_dmadump
+ *
+ * Description:
+ * Dump previously sampled DMA register contents
+ *
+ * Assumptions:
+ * - DMA handle allocated by stm32wb_dmachannel()
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_DMA_INFO
+void stm32wb_dmadump(DMA_HANDLE handle, const struct stm32wb_dmaregs_s *regs,
+ const char *msg)
+{
+ DMA_CHANNEL dmachan = (DMA_CHANNEL)handle;
+ uint8_t controller;
+
+ DEBUGASSERT(handle != NULL);
+
+ /* Get DMA controller */
+
+ controller = dmachan->ctrl;
+ DEBUGASSERT(controller >= DMA1 && controller <= DMA2);
+
+ dmainfo("DMA %d CH%d Registers: %s\n", dmachan->ctrl, dmachan->ctrl, msg);
+
+ g_dma_ops[controller].dma_dump(handle, regs, msg);
+}
+#endif
diff --git a/arch/arm/src/stm32wb/stm32wb_dma.h b/arch/arm/src/stm32wb/stm32wb_dma.h
new file mode 100644
index 0000000000..547beac1f4
--- /dev/null
+++ b/arch/arm/src/stm32wb/stm32wb_dma.h
@@ -0,0 +1,281 @@
+/****************************************************************************
+ * arch/arm/src/stm32wb/stm32wb_dma.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32WB_STM32WB_DMA_H
+#define __ARCH_ARM_SRC_STM32WB_STM32WB_DMA_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+
+#include "chip.h"
+
+#include "hardware/stm32wb_dma.h"
+#include "hardware/stm32wb_dmamux.h"
+
+/* These definitions provide the bit encoding of the 'status' parameter
+ * passed to the DMA callback function (see dma_callback_t).
+ */
+
+# define DMA_STATUS_TEIF DMA_CHAN_TEIF_BIT /* Channel Transfer Error */
+# define DMA_STATUS_HTIF DMA_CHAN_HTIF_BIT /* Channel Half Transfer */
+# define DMA_STATUS_TCIF DMA_CHAN_TCIF_BIT /* Channel Transfer Complete */
+
+#define DMA_STATUS_ERROR (DMA_STATUS_TEIF)
+#define DMA_STATUS_SUCCESS (DMA_STATUS_TCIF | DMA_STATUS_HTIF)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/* DMA_HANDLE provides an opaque reference that can be used to represent a
+ * DMA channel.
+ */
+
+typedef void *DMA_HANDLE;
+
+/* Description:
+ * This is the type of the callback that is used to inform the user of the
+ * completion of the DMA.
+ *
+ * Input Parameters:
+ * handle - Refers to the DMA channel
+ * status - A bit encoded value that provides the completion status. See
+ * the DMASTATUS_* definitions above.
+ * arg - A user-provided value that was provided when
+ * stm32lwb_dmastart() was called.
+ */
+
+typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg);
+
+#ifdef CONFIG_DEBUG_DMA_INFO
+struct stm32wb_dmaregs_s
+{
+ uint32_t isr; /* Interrupt Status Register; each channel gets 4 bits */
+ uint32_t ccr; /* Channel Configuration Register; determines functionality */
+ uint32_t cndtr; /* Channel Count Register; determines number of transfers */
+ uint32_t cpar; /* Channel Peripheral Address Register; determines start */
+ uint32_t cmar; /* Channel Memory Address Register; determines start */
+#ifndef CONFIG_STM32WB_HAVE_DMAMUX
+ uint32_t cselr; /* Channel Selection Register; chooses peripheral bound */
+#else
+ struct
+ {
+ uint32_t ccr; /* Channel Configuration Register */
+ uint32_t csr; /* Channel Status Register */
+ uint32_t rg0cr; /* Request Generator Channel 0 Configuration Register */
+ uint32_t rg1cr; /* Request Generator Channel 1 Configuration Register */
+ uint32_t rg2cr; /* Request Generator Channel 2 Configuration Register */
+ uint32_t rg3cr; /* Request Generator Channel 3 Configuration Register */
+ uint32_t rgsr; /* Request Generator Interrupt Status Register */
+ } dmamux;
+#endif
+};
+#endif
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_dmachannel
+ *
+ * Description:
+ * Allocate a DMA channel. This function gives the caller mutually
+ * exclusive access to the DMA channel specified by the 'dmamap' argument.
+ * It is common for both DMA controllers (DMA1 and DMA2).
+ *
+ * Input Parameters:
+ * dmamap - Identifies the stream/channel resource. For the STM32WB, this
+ * is a bit-encoded value as provided by the DMAMAP_* definitions in
+ * hardware/stm32wb_dmamux.h
+ *
+ * Returned Value:
+ * On success, this function returns a non-NULL, void* DMA channel handle.
+ * NULL is returned on any failure. This function can fail only if no DMA
+ * channel is available.
+ *
+ * Assumptions:
+ * - The caller does not hold he DMA channel.
+ * - The caller can wait for the DMA channel to be freed if it is no
+ * available.
+ *
+ ****************************************************************************/
+
+DMA_HANDLE stm32wb_dmachannel(unsigned int dmamap);
+
+/****************************************************************************
+ * Name: stm32wb_dmafree
+ *
+ * Description:
+ * Release a DMA channel. If another thread is waiting for this DMA
+ * channel in a call to stm32wb_dmachannel, then this function will
+ * re-assign the DMA channel to that thread and wake it up.
+ *
+ * NOTE: The 'handle' used in this argument must NEVER be used again
+ * until stm32wb_dmachannel() is called again to re-gain access to
+ * the channel.
+ *
+ * Returned Value:
+ * None
+ *
+ * Assumptions:
+ * - The caller holds the DMA channel.
+ * - There is no DMA in progress
+ *
+ ****************************************************************************/
+
+void stm32wb_dmafree(DMA_HANDLE handle);
+
+/****************************************************************************
+ * Name: stm32wb_dmasetup
+ *
+ * Description:
+ * Configure DMA before using
+ *
+ ****************************************************************************/
+
+void stm32wb_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
+ size_t ntransfers, uint32_t ccr);
+
+/****************************************************************************
+ * Name: stm32wb_dmastart
+ *
+ * Description:
+ * Start the DMA transfer
+ *
+ * Assumptions:
+ * - DMA handle allocated by stm32wb_dmachannel()
+ * - No DMA in progress
+ *
+ ****************************************************************************/
+
+void stm32wb_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg,
+ bool half);
+
+/****************************************************************************
+ * Name: stm32wb_dmastop
+ *
+ * Description:
+ * Cancel the DMA. After stm32wb_dmastop() is called, the DMA channel is
+ * reset and stm32wb_dmasetup() must be called before stm32wb_dmastart()
+ * can be called again
+ *
+ * Assumptions:
+ * - DMA handle allocated by stm32wb_dmachannel()
+ *
+ ****************************************************************************/
+
+void stm32wb_dmastop(DMA_HANDLE handle);
+
+/****************************************************************************
+ * Name: stm32wb_dmaresidual
+ *
+ * Description:
+ * Returns the number of bytes remaining to be transferred
+ *
+ * Assumptions:
+ * - DMA handle allocated by stm32wb_dmachannel()
+ *
+ ****************************************************************************/
+
+size_t stm32wb_dmaresidual(DMA_HANDLE handle);
+
+/****************************************************************************
+ * Name: stm32wb_dmacapable
+ *
+ * Description:
+ * Check if the DMA controller can transfer data to/from given memory
+ * address with the given configuration. This depends on the internal
+ * connections in the ARM bus matrix of the processor. Note that this
+ * only applies to memory addresses, it will return false for any
+ * peripheral address.
+ *
+ * Returned Value:
+ * True, if transfer is possible.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_STM32WB_DMACAPABLE
+bool stm32wb_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr);
+#else
+# define stm32wb_dmacapable(maddr, count, ccr) (true)
+#endif
+
+/****************************************************************************
+ * Name: stm32wb_dmasample
+ *
+ * Description:
+ * Sample DMA register contents
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