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Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2022/07/06 16:10:55 UTC
[GitHub] [incubator-nuttx] hartmannathan commented on a diff in pull request #6478: arch: arm64: ARMv8-A support for NuttX
hartmannathan commented on code in PR #6478:
URL: https://github.com/apache/incubator-nuttx/pull/6478#discussion_r915017817
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boards/arm64/qemu/qemu-a53/src/qemu_appinit.c:
##########
@@ -0,0 +1,75 @@
+/****************************************************************************
+ * boards/arm64/qemu/qemu-a53/src/qemu_appinit.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+
+#include <nuttx/board.h>
+
+#include "qemu-a53.h"
+
+#ifdef CONFIG_BOARDCTL
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_app_initialize
+ *
+ * Description:
+ * Perform application specific initialization. This function is never
+ * called directly from application code, but only indirectly via the
+ * (non-standard) boardctl() interface using the command BOARDIOC_INIT.
+ *
+ * Input Parameters:
+ * arg - The boardctl() argument is passed to the board_app_initialize()
+ * implementation without modification. The argument has no
+ * meaning to NuttX; the meaning of the argument is a contract
+ * between the board-specific initialization logic and the
+ * matching application logic. The value could be such things as a
+ * mode enumeration value, a set of DIP switch switch settings, a
+ * pointer to configuration data read from a file or serial FLASH,
+ * or whatever you would like to do with it. Every implementation
+ * should accept zero/NULL as a default configuration.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned on
+ * any failure to indicate the nature of the failure.
+ *
+ ****************************************************************************/
+
+int board_app_initialize(uintptr_t arg)
+{
Review Comment:
Add:
`UNUSED(arg);`
##########
boards/arm64/qemu/qemu-a53/README.txt:
##########
@@ -0,0 +1,297 @@
+README.txt
+==========
+
+This board configuration will use QEMU to emulate a generic Cortex-A53
+hardware platform and provides support for these devices:
+
+ - GICv3 interrupt controller
+ - ARM Generic Timer
+ - PL011 UART controller
+
+Contents
+========
+ - Getting Started
+ - Status
+ - Platform Features
+ - Debugging with QEMU
+ - FPU Support and Performance
+ - SMP Support
+ - References
+
+Getting Started
+===============
+
+1. Compile Toolchain
+ 1.1 Host environment
+ GNU/Linux: Ubuntu 18.04 or greater
+ 1.2 Download and Install
+ $ wget https://developer.arm.com/-/media/Files/downloads/gnu/11.2-2022.02/binrel/gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf.tar.xz
+ $ xz -d gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf.tar.xz
+ $ tar xf gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf.tar
+
+ Put gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf/bin/ to your host PATH environment variable, like:
+ $ export PATH=$PATH:/opt/software/arm/linaro-toolchain/gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf/bin
+ check the toolchain:
+ $ aarch64-none-elf-gcc -v
+
+2. Install QEMU
+ In Ubuntu 18.04(or greater), install qemu:
+ $ sudo apt-get install qemu-system-arm qemu-efi-aarch64 qemu-utils
+ And make sure install is properly:
+ $ qemu-system-aarch64 --help
+
+3. Configuring and running
+ 3.1 Single Core
+ Configuring NuttX and compile:
+ $ ./tools/configure.sh -l qemu-a53:nsh
+ $ make
+ Runing with qemu
+ $ qemu-system-aarch64 -cpu cortex-a53 -nographic \
+ -machine virt,virtualization=on,gic-version=3 \
+ -net none -chardev stdio,id=con,mux=on -serial chardev:con \
+ -mon chardev=con,mode=readline -kernel ./nuttx
+
+ 3.2 SMP
+ Configuring NuttX and compile:
+ $ ./tools/configure.sh -l qemu-a53:nsh_smp
+ $ make
+ Runing with qemu
+ $ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
+ -machine virt,virtualization=on,gic-version=3 \
+ -net none -chardev stdio,id=con,mux=on -serial chardev:con \
+ -mon chardev=con,mode=readline -kernel ./nuttx
+
+ Note:
+ 1. Make sure the aarch64-none-elf toolchain install PATH has been add to environment variable
+ 2. To quit QEMU, type Ctrl + X
+ 3. Nuttx default core number is 4, and Changing CONFIG_SMP_NCPUS > 4 and setting qemu command
+ option -smp will boot more core. for qemu, core limit is 32.
+
+Status
+======
+2022-06-12:
+
+1. SMP is supprt at QEMU. add psci interface, armv8 cache operation(data cache)
+ and smccc support. the system will run into nsh shell, SMP test is PASS, but
+ ostest crash at signal testing
+
+
+2022-05-22:
+ Arm64 support version for NuttX is Ready, These Features supported:
+
+1. Cotex-a53 single core support: With the supporting of GICv3,
+ Arch timer, PL101 UART, The system can run into nsh shell.
+ Running ostest seem PASSED.
+2. qemu-a53 board configuration support: qemu-a53 board can been
+ configuring and compiling, And runing with qemu-system-aarch64
+ at Ubuntu 18.04.
+3. FPU support for armv8-a: FPU context switching in NEON/floating-point
+ TRAP was supported. FPU registers saving at vfork and independent
+ FPU context for signal rountine was considered but more testing
+ need to be do.
Review Comment:
s/need to be do/needs to be done/
##########
arch/arm64/src/common/arm64_arch_timer.c:
##########
@@ -0,0 +1,245 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch_timer.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <nuttx/spinlock.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_arch_timer.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+#define MIN_DELAY (1000)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static uint64_t last_cycle;
+static uint64_t cycle_per_tick;
+static uint32_t arch_timer_rate;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static inline void arm64_arch_timer_set_compare(uint64_t value)
+{
+ write_sysreg(value, cntv_cval_el0);
+}
+
+static inline void arm64_arch_timer_enable(unsigned char enable)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (enable)
+ {
+ value |= CNTV_CTL_ENABLE_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_ENABLE_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline void arm64_arch_timer_set_irq_mask(bool mask)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (mask)
+ {
+ value |= CNTV_CTL_IMASK_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_IMASK_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline uint64_t arm64_arch_timer_count(void)
+{
+ return read_sysreg(cntvct_el0);
+}
+
+static inline uint32_t arm64_arch_timer_get_cntfrq(void)
+{
+ return read_sysreg(cntfrq_el0);
+}
+
+#ifdef CONFIG_SCHED_TICKLESS
+static void arm64_arch_timer_compare_isr(int irq, uint64_t *regs, void *arg)
Review Comment:
Should be:
`static int arm64_arch_timer_compare_isr(int irq, FAR void *context, FAR void *arg)`
At top of function, add:
`regs = (uint64_t) context;`
At end of function, add:
`return OK;`
##########
arch/arm64/src/common/arm64_arch_timer.c:
##########
@@ -0,0 +1,245 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch_timer.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <nuttx/spinlock.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_arch_timer.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+#define MIN_DELAY (1000)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static uint64_t last_cycle;
+static uint64_t cycle_per_tick;
+static uint32_t arch_timer_rate;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static inline void arm64_arch_timer_set_compare(uint64_t value)
+{
+ write_sysreg(value, cntv_cval_el0);
+}
+
+static inline void arm64_arch_timer_enable(unsigned char enable)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (enable)
+ {
+ value |= CNTV_CTL_ENABLE_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_ENABLE_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline void arm64_arch_timer_set_irq_mask(bool mask)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (mask)
+ {
+ value |= CNTV_CTL_IMASK_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_IMASK_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline uint64_t arm64_arch_timer_count(void)
+{
+ return read_sysreg(cntvct_el0);
+}
+
+static inline uint32_t arm64_arch_timer_get_cntfrq(void)
+{
+ return read_sysreg(cntfrq_el0);
+}
+
+#ifdef CONFIG_SCHED_TICKLESS
+static void arm64_arch_timer_compare_isr(int irq, uint64_t *regs, void *arg)
+{
+ irqstate_t flags;
+ uint64_t curr_cycle;
+ uint32_t delta_ticks;
+
+ flags = spin_lock_irqsave(&g_arch_timer_lock);
+
+ curr_cycle = arm64_arch_timer_count();
+ delta_ticks = (uint32_t)((curr_cycle - last_cycle) / cycle_per_tick);
+
+ last_cycle += delta_ticks * cycle_per_tick;
+
+ arm_arch_timer_set_irq_mask(true);
+
+ spin_unlock_irqrestore(&g_arch_timer_lock, flags);
+
+ nxsched_process_timer();
+}
+
+#else
+
+static void arm64_arch_timer_compare_isr(int irq, uint64_t *regs, void *arg)
+{
+ uint64_t curr_cycle;
+ uint32_t delta_ticks;
+ uint64_t next_cycle;
+
+ curr_cycle = arm64_arch_timer_count();
+ delta_ticks = (uint32_t)((curr_cycle - last_cycle) / cycle_per_tick);
+
+ last_cycle += delta_ticks * cycle_per_tick;
+
+ next_cycle = last_cycle + cycle_per_tick;
+
+ if ((uint64_t)(next_cycle - curr_cycle) < MIN_DELAY)
+ {
+ next_cycle += cycle_per_tick;
+ }
+
+ arm64_arch_timer_set_compare(next_cycle);
+ arm64_arch_timer_set_irq_mask(false);
+
+ nxsched_process_timer();
+}
+
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_SMP
+/* Notes:
+ *
+ * The origin design for ARMv8-A timer is assigned private timer to
+ * every PE(CPU core), the ARM_ARCH_TIMER_IRQ is a PPI so it's
+ * should be enable at every core.
+ *
+ * But for NuttX, it's design only for primary core to handle timer
+ * interrupt and call nxsched_process_timer at timer tick mode.
+ * So we need only enable timer for primary core
+ *
+ * IMX6 use GPT which is a SPI rather than generic timer to handle
+ * timer interrupt
+ */
+
+void arm64_smp_timer_init(void)
+{
+ uint64_t curr_cycle;
+
+ /* set the initial status of timer0 of each secondary core */
+
+ curr_cycle = arm64_arch_timer_count();
+
+ arm64_arch_timer_set_compare(curr_cycle + cycle_per_tick);
+ arm64_arch_timer_enable(true);
+ up_enable_irq(ARM_ARCH_TIMER_IRQ);
+ arm64_arch_timer_set_irq_mask(false);
+}
+
+#endif
+
+uint64_t arch_counter_read(void)
+{
+ return arm64_arch_timer_count();
+}
+
+void arch_timer_delay(long mini_sec)
+{
+ unsigned int timeout;
+ volatile unsigned int new_counter;
+ unsigned int clock = mini_sec * arch_timer_rate / 1000;
+
+ if (mini_sec == 0 || mini_sec > 2000)
+ {
+ sinfo("delay must !=0 or < 2000ms \n");
+ return;
+ }
+
+ timeout = arch_counter_read() + clock;
+ do
+ {
+ new_counter = arch_counter_read();
+ arch_nop();
+ }
+ while (new_counter < timeout);
+}
+
+/****************************************************************************
+ * Name: up_timer_initialize
+ *
+ * Description:
+ *
+ ****************************************************************************/
+
+void up_timer_initialize(void)
+{
+ uint64_t curr_cycle;
+
+ arch_timer_rate = arm64_arch_timer_get_cntfrq();
+ cycle_per_tick = ((uint64_t)arch_timer_rate / (uint64_t)TICK_PER_SEC);
+
+ sinfo("%s: cp15 timer(s) running at %lu.%02luMHz, cycle %ld\n", __func__,
+ (unsigned long)arch_timer_rate / 1000000,
+ (unsigned long)(arch_timer_rate / 10000) % 100, cycle_per_tick);
+
+ irq_attach(ARM_ARCH_TIMER_IRQ, (xcpt_t)arm64_arch_timer_compare_isr, 0);
Review Comment:
Will not need typecast to (xcpt_t) after above changes.
##########
arch/arm64/src/common/arm64_arch_timer.c:
##########
@@ -0,0 +1,245 @@
+/****************************************************************************
+ * arch/arm64/src/common/arm64_arch_timer.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <debug.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <arch/irq.h>
+#include <arch/chip/chip.h>
+#include <nuttx/spinlock.h>
+
+#include "arm64_arch.h"
+#include "arm64_internal.h"
+#include "arm64_gic.h"
+#include "arm64_arch_timer.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+#define MIN_DELAY (1000)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static uint64_t last_cycle;
+static uint64_t cycle_per_tick;
+static uint32_t arch_timer_rate;
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static inline void arm64_arch_timer_set_compare(uint64_t value)
+{
+ write_sysreg(value, cntv_cval_el0);
+}
+
+static inline void arm64_arch_timer_enable(unsigned char enable)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (enable)
+ {
+ value |= CNTV_CTL_ENABLE_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_ENABLE_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline void arm64_arch_timer_set_irq_mask(bool mask)
+{
+ uint64_t value;
+
+ value = read_sysreg(cntv_ctl_el0);
+
+ if (mask)
+ {
+ value |= CNTV_CTL_IMASK_BIT;
+ }
+ else
+ {
+ value &= ~CNTV_CTL_IMASK_BIT;
+ }
+
+ write_sysreg(value, cntv_ctl_el0);
+}
+
+static inline uint64_t arm64_arch_timer_count(void)
+{
+ return read_sysreg(cntvct_el0);
+}
+
+static inline uint32_t arm64_arch_timer_get_cntfrq(void)
+{
+ return read_sysreg(cntfrq_el0);
+}
+
+#ifdef CONFIG_SCHED_TICKLESS
+static void arm64_arch_timer_compare_isr(int irq, uint64_t *regs, void *arg)
+{
+ irqstate_t flags;
+ uint64_t curr_cycle;
+ uint32_t delta_ticks;
+
+ flags = spin_lock_irqsave(&g_arch_timer_lock);
+
+ curr_cycle = arm64_arch_timer_count();
+ delta_ticks = (uint32_t)((curr_cycle - last_cycle) / cycle_per_tick);
+
+ last_cycle += delta_ticks * cycle_per_tick;
+
+ arm_arch_timer_set_irq_mask(true);
+
+ spin_unlock_irqrestore(&g_arch_timer_lock, flags);
+
+ nxsched_process_timer();
+}
+
+#else
+
+static void arm64_arch_timer_compare_isr(int irq, uint64_t *regs, void *arg)
Review Comment:
Same as tickless version of this function:
Should be:
`static int arm64_arch_timer_compare_isr(int irq, FAR void *context, FAR void *arg)`
At top of function, add:
`regs = (uint64_t) context;`
At end of function, add:
`return OK;`
##########
boards/arm64/qemu/qemu-a53/README.txt:
##########
@@ -0,0 +1,297 @@
+README.txt
+==========
+
+This board configuration will use QEMU to emulate a generic Cortex-A53
+hardware platform and provides support for these devices:
+
+ - GICv3 interrupt controller
+ - ARM Generic Timer
+ - PL011 UART controller
+
+Contents
+========
+ - Getting Started
+ - Status
+ - Platform Features
+ - Debugging with QEMU
+ - FPU Support and Performance
+ - SMP Support
+ - References
+
+Getting Started
+===============
+
+1. Compile Toolchain
+ 1.1 Host environment
+ GNU/Linux: Ubuntu 18.04 or greater
+ 1.2 Download and Install
+ $ wget https://developer.arm.com/-/media/Files/downloads/gnu/11.2-2022.02/binrel/gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf.tar.xz
+ $ xz -d gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf.tar.xz
+ $ tar xf gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf.tar
+
+ Put gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf/bin/ to your host PATH environment variable, like:
+ $ export PATH=$PATH:/opt/software/arm/linaro-toolchain/gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf/bin
+ check the toolchain:
+ $ aarch64-none-elf-gcc -v
+
+2. Install QEMU
+ In Ubuntu 18.04(or greater), install qemu:
+ $ sudo apt-get install qemu-system-arm qemu-efi-aarch64 qemu-utils
+ And make sure install is properly:
+ $ qemu-system-aarch64 --help
+
+3. Configuring and running
+ 3.1 Single Core
+ Configuring NuttX and compile:
+ $ ./tools/configure.sh -l qemu-a53:nsh
+ $ make
+ Runing with qemu
+ $ qemu-system-aarch64 -cpu cortex-a53 -nographic \
+ -machine virt,virtualization=on,gic-version=3 \
+ -net none -chardev stdio,id=con,mux=on -serial chardev:con \
+ -mon chardev=con,mode=readline -kernel ./nuttx
+
+ 3.2 SMP
+ Configuring NuttX and compile:
+ $ ./tools/configure.sh -l qemu-a53:nsh_smp
+ $ make
+ Runing with qemu
+ $ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
+ -machine virt,virtualization=on,gic-version=3 \
+ -net none -chardev stdio,id=con,mux=on -serial chardev:con \
+ -mon chardev=con,mode=readline -kernel ./nuttx
+
+ Note:
+ 1. Make sure the aarch64-none-elf toolchain install PATH has been add to environment variable
+ 2. To quit QEMU, type Ctrl + X
+ 3. Nuttx default core number is 4, and Changing CONFIG_SMP_NCPUS > 4 and setting qemu command
+ option -smp will boot more core. for qemu, core limit is 32.
+
+Status
+======
+2022-06-12:
+
+1. SMP is supprt at QEMU. add psci interface, armv8 cache operation(data cache)
Review Comment:
s/supprt/support/
##########
boards/arm64/qemu/qemu-a53/README.txt:
##########
@@ -0,0 +1,297 @@
+README.txt
+==========
+
+This board configuration will use QEMU to emulate a generic Cortex-A53
+hardware platform and provides support for these devices:
+
+ - GICv3 interrupt controller
+ - ARM Generic Timer
+ - PL011 UART controller
+
+Contents
+========
+ - Getting Started
+ - Status
+ - Platform Features
+ - Debugging with QEMU
+ - FPU Support and Performance
+ - SMP Support
+ - References
+
+Getting Started
+===============
+
+1. Compile Toolchain
+ 1.1 Host environment
+ GNU/Linux: Ubuntu 18.04 or greater
+ 1.2 Download and Install
+ $ wget https://developer.arm.com/-/media/Files/downloads/gnu/11.2-2022.02/binrel/gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf.tar.xz
+ $ xz -d gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf.tar.xz
+ $ tar xf gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf.tar
+
+ Put gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf/bin/ to your host PATH environment variable, like:
+ $ export PATH=$PATH:/opt/software/arm/linaro-toolchain/gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf/bin
+ check the toolchain:
+ $ aarch64-none-elf-gcc -v
+
+2. Install QEMU
+ In Ubuntu 18.04(or greater), install qemu:
+ $ sudo apt-get install qemu-system-arm qemu-efi-aarch64 qemu-utils
+ And make sure install is properly:
+ $ qemu-system-aarch64 --help
+
+3. Configuring and running
+ 3.1 Single Core
+ Configuring NuttX and compile:
+ $ ./tools/configure.sh -l qemu-a53:nsh
+ $ make
+ Runing with qemu
Review Comment:
s/Runing/Running/g
##########
boards/arm64/qemu/qemu-a53/README.txt:
##########
@@ -0,0 +1,297 @@
+README.txt
+==========
+
+This board configuration will use QEMU to emulate a generic Cortex-A53
+hardware platform and provides support for these devices:
+
+ - GICv3 interrupt controller
+ - ARM Generic Timer
+ - PL011 UART controller
+
+Contents
+========
+ - Getting Started
+ - Status
+ - Platform Features
+ - Debugging with QEMU
+ - FPU Support and Performance
+ - SMP Support
+ - References
+
+Getting Started
+===============
+
+1. Compile Toolchain
+ 1.1 Host environment
+ GNU/Linux: Ubuntu 18.04 or greater
+ 1.2 Download and Install
+ $ wget https://developer.arm.com/-/media/Files/downloads/gnu/11.2-2022.02/binrel/gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf.tar.xz
+ $ xz -d gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf.tar.xz
+ $ tar xf gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf.tar
+
+ Put gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf/bin/ to your host PATH environment variable, like:
+ $ export PATH=$PATH:/opt/software/arm/linaro-toolchain/gcc-arm-11.2-2022.02-x86_64-aarch64-none-elf/bin
+ check the toolchain:
+ $ aarch64-none-elf-gcc -v
+
+2. Install QEMU
+ In Ubuntu 18.04(or greater), install qemu:
+ $ sudo apt-get install qemu-system-arm qemu-efi-aarch64 qemu-utils
+ And make sure install is properly:
+ $ qemu-system-aarch64 --help
+
+3. Configuring and running
+ 3.1 Single Core
+ Configuring NuttX and compile:
+ $ ./tools/configure.sh -l qemu-a53:nsh
+ $ make
+ Runing with qemu
+ $ qemu-system-aarch64 -cpu cortex-a53 -nographic \
+ -machine virt,virtualization=on,gic-version=3 \
+ -net none -chardev stdio,id=con,mux=on -serial chardev:con \
+ -mon chardev=con,mode=readline -kernel ./nuttx
+
+ 3.2 SMP
+ Configuring NuttX and compile:
+ $ ./tools/configure.sh -l qemu-a53:nsh_smp
+ $ make
+ Runing with qemu
+ $ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \
+ -machine virt,virtualization=on,gic-version=3 \
+ -net none -chardev stdio,id=con,mux=on -serial chardev:con \
+ -mon chardev=con,mode=readline -kernel ./nuttx
+
+ Note:
+ 1. Make sure the aarch64-none-elf toolchain install PATH has been add to environment variable
+ 2. To quit QEMU, type Ctrl + X
+ 3. Nuttx default core number is 4, and Changing CONFIG_SMP_NCPUS > 4 and setting qemu command
+ option -smp will boot more core. for qemu, core limit is 32.
+
+Status
+======
+2022-06-12:
+
+1. SMP is supprt at QEMU. add psci interface, armv8 cache operation(data cache)
+ and smccc support. the system will run into nsh shell, SMP test is PASS, but
+ ostest crash at signal testing
+
+
+2022-05-22:
+ Arm64 support version for NuttX is Ready, These Features supported:
+
+1. Cotex-a53 single core support: With the supporting of GICv3,
+ Arch timer, PL101 UART, The system can run into nsh shell.
+ Running ostest seem PASSED.
+2. qemu-a53 board configuration support: qemu-a53 board can been
+ configuring and compiling, And runing with qemu-system-aarch64
+ at Ubuntu 18.04.
+3. FPU support for armv8-a: FPU context switching in NEON/floating-point
+ TRAP was supported. FPU registers saving at vfork and independent
+ FPU context for signal rountine was considered but more testing
Review Comment:
s/rountine/routine/g
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