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Posted to commits@nuttx.apache.org by ac...@apache.org on 2023/06/14 19:15:05 UTC
[nuttx] branch master updated: riscv/barrier: Define more granular memory barriers
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new 9b5746cb5f riscv/barrier: Define more granular memory barriers
9b5746cb5f is described below
commit 9b5746cb5f38548ddf8eaa9efc82a34413478d15
Author: Ville Juven <vi...@unikie.com>
AuthorDate: Wed Jun 14 14:19:29 2023 +0300
riscv/barrier: Define more granular memory barriers
Separate barriers for full (memory + I/O) and local memory (cache) flushing.
---
arch/risc-v/include/barriers.h | 20 ++++++++++++++------
arch/risc-v/src/common/riscv_addrenv.c | 4 +---
arch/risc-v/src/common/riscv_mmu.h | 3 ++-
arch/risc-v/src/common/riscv_mtimer.c | 2 +-
arch/risc-v/src/common/riscv_percpu.c | 2 +-
arch/risc-v/src/mpfs/mpfs_gpio.c | 2 +-
arch/risc-v/src/nuttsbi/sbi_mscratch.c | 2 +-
arch/risc-v/src/nuttsbi/sbi_mtimer.c | 2 +-
8 files changed, 22 insertions(+), 15 deletions(-)
diff --git a/arch/risc-v/include/barriers.h b/arch/risc-v/include/barriers.h
index 580e3ea2ef..3ba9d73218 100644
--- a/arch/risc-v/include/barriers.h
+++ b/arch/risc-v/include/barriers.h
@@ -21,12 +21,20 @@
#ifndef __ARCH_RISCV_INCLUDE_BARRIERS_H
#define __ARCH_RISCV_INCLUDE_BARRIERS_H
-/* Common memory barriers:
- * __DMB() is used to synchronize external devices (I/O domain mainly)
- * __ISB() is used to synchronize the instruction and data streams
- */
+/* Common memory barriers (p=predecessor, s=successor) */
-#define __DMB() __asm__ __volatile__ ("fence" ::: "memory")
-#define __ISB() __asm__ __volatile__ ("fence.i" ::: "memory")
+#define __FENCE(p, s) __asm__ __volatile__ ("fence "#p", "#s ::: "memory")
+
+/* __DMB() is used to flush local data caches (memory) */
+
+#define __DMB() __FENCE(rw, rw)
+
+/* __MB() is a full memory barrier */
+
+#define __MB() __FENCE(iorw, iorw)
+
+/* __ISB() is used to synchronize the instruction and data streams */
+
+#define __ISB() __asm__ __volatile__ ("fence.i" ::: "memory")
#endif /* __ARCH_RISCV_INCLUDE_BARRIERS_H */
diff --git a/arch/risc-v/src/common/riscv_addrenv.c b/arch/risc-v/src/common/riscv_addrenv.c
index 44adfe3a58..95fe0473f8 100644
--- a/arch/risc-v/src/common/riscv_addrenv.c
+++ b/arch/risc-v/src/common/riscv_addrenv.c
@@ -736,10 +736,8 @@ int up_addrenv_select(const arch_addrenv_t *addrenv)
int up_addrenv_coherent(const arch_addrenv_t *addrenv)
{
- /* Flush the instruction and data caches */
+ /* Nothing needs to be done */
- __ISB();
- __DMB();
return OK;
}
diff --git a/arch/risc-v/src/common/riscv_mmu.h b/arch/risc-v/src/common/riscv_mmu.h
index fbc5a68828..0c0c6b5373 100644
--- a/arch/risc-v/src/common/riscv_mmu.h
+++ b/arch/risc-v/src/common/riscv_mmu.h
@@ -187,7 +187,8 @@ static inline void mmu_write_satp(uintptr_t reg)
(
"csrw satp, %0\n"
"sfence.vma x0, x0\n"
- "fence\n"
+ "fence rw, rw\n"
+ "fence.i\n"
:
: "rK" (reg)
: "memory"
diff --git a/arch/risc-v/src/common/riscv_mtimer.c b/arch/risc-v/src/common/riscv_mtimer.c
index dff7998d75..eb6ceaf842 100644
--- a/arch/risc-v/src/common/riscv_mtimer.c
+++ b/arch/risc-v/src/common/riscv_mtimer.c
@@ -124,7 +124,7 @@ static void riscv_mtimer_set_mtimecmp(struct riscv_mtimer_lowerhalf_s *priv,
/* Make sure it sticks */
- __DMB();
+ __MB();
}
#else
static uint64_t riscv_mtimer_get_mtime(struct riscv_mtimer_lowerhalf_s *priv)
diff --git a/arch/risc-v/src/common/riscv_percpu.c b/arch/risc-v/src/common/riscv_percpu.c
index 850a1d222a..458682746a 100644
--- a/arch/risc-v/src/common/riscv_percpu.c
+++ b/arch/risc-v/src/common/riscv_percpu.c
@@ -147,7 +147,7 @@ void riscv_percpu_add_hart(uintptr_t hartid)
/* Make sure it sticks */
- __DMB();
+ __MB();
}
/****************************************************************************
diff --git a/arch/risc-v/src/mpfs/mpfs_gpio.c b/arch/risc-v/src/mpfs/mpfs_gpio.c
index c280e0eb24..6e4562b252 100644
--- a/arch/risc-v/src/mpfs/mpfs_gpio.c
+++ b/arch/risc-v/src/mpfs/mpfs_gpio.c
@@ -100,7 +100,7 @@ static struct gpio_callback_s g_mss_gpio_callbacks[GPIO_BANK0_NUM_PINS +
static void mpfs_gpio_irq_clear(int bank, int pin)
{
putreg32(1 << pin, g_gpio_base[bank] + MPFS_GPIO_INTR_OFFSET);
- __DMB();
+ __MB();
}
/****************************************************************************
diff --git a/arch/risc-v/src/nuttsbi/sbi_mscratch.c b/arch/risc-v/src/nuttsbi/sbi_mscratch.c
index 7010678a69..21913c21b8 100644
--- a/arch/risc-v/src/nuttsbi/sbi_mscratch.c
+++ b/arch/risc-v/src/nuttsbi/sbi_mscratch.c
@@ -81,5 +81,5 @@ void sbi_mscratch_assign(uintptr_t hartid)
/* Make sure mscratch is updated before continuing */
- __DMB();
+ __MB();
}
diff --git a/arch/risc-v/src/nuttsbi/sbi_mtimer.c b/arch/risc-v/src/nuttsbi/sbi_mtimer.c
index a6771bdbf5..4fae0db2b2 100644
--- a/arch/risc-v/src/nuttsbi/sbi_mtimer.c
+++ b/arch/risc-v/src/nuttsbi/sbi_mtimer.c
@@ -96,5 +96,5 @@ void sbi_set_mtimecmp(uint64_t value)
/* Make sure it sticks */
- __DMB();
+ __MB();
}