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Posted to commits@mynewt.apache.org by ad...@apache.org on 2016/06/15 22:04:06 UTC
[23/51] [partial] incubator-mynewt-site git commit: Fixed broken
Quick Start link and added OpenOCD option for Arduino Primo debugging
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/lpcspifi.c
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diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/lpcspifi.c b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/lpcspifi.c
new file mode 100755
index 0000000..6390149
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/lpcspifi.c
@@ -0,0 +1,982 @@
+/***************************************************************************
+ * Copyright (C) 2012 by George Harris *
+ * george@luminairecoffee.com *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "imp.h"
+#include "spi.h"
+#include <jtag/jtag.h>
+#include <helper/time_support.h>
+#include <target/algorithm.h>
+#include <target/armv7m.h>
+
+/* Offsets from ssp_base into config & data registers */
+#define SSP_CR0 (0x00) /* Control register 0 */
+#define SSP_CR1 (0x04) /* Control register 1 */
+#define SSP_DATA (0x08) /* Data register (TX and RX) */
+#define SSP_SR (0x0C) /* Status register */
+#define SSP_CPSR (0x10) /* Clock prescale register */
+
+/* Status register fields */
+#define SSP_BSY (0x00000010)
+
+/* Timeout in ms */
+#define SSP_CMD_TIMEOUT (100)
+#define SSP_PROBE_TIMEOUT (100)
+#define SSP_MAX_TIMEOUT (3000)
+
+/* Size of the stack to alloc in the working area for the execution of
+ * the ROM spifi_init() function */
+#define SPIFI_INIT_STACK_SIZE 512
+
+struct lpcspifi_flash_bank {
+ int probed;
+ uint32_t ssp_base;
+ uint32_t io_base;
+ uint32_t ioconfig_base;
+ uint32_t bank_num;
+ uint32_t max_spi_clock_mhz;
+ const struct flash_device *dev;
+};
+
+struct lpcspifi_target {
+ char *name;
+ uint32_t tap_idcode;
+ uint32_t spifi_base;
+ uint32_t ssp_base;
+ uint32_t io_base;
+ uint32_t ioconfig_base; /* base address for the port word pin registers */
+};
+
+static const struct lpcspifi_target target_devices[] = {
+ /* name, tap_idcode, spifi_base, ssp_base, io_base, ioconfig_base */
+ { "LPC43xx/18xx", 0x4ba00477, 0x14000000, 0x40083000, 0x400F4000, 0x40086000 },
+ { NULL, 0, 0, 0, 0, 0 }
+};
+
+/* flash_bank lpcspifi <base> <size> <chip_width> <bus_width> <target>
+ */
+FLASH_BANK_COMMAND_HANDLER(lpcspifi_flash_bank_command)
+{
+ struct lpcspifi_flash_bank *lpcspifi_info;
+
+ if (CMD_ARGC < 6)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ lpcspifi_info = malloc(sizeof(struct lpcspifi_flash_bank));
+ if (lpcspifi_info == NULL) {
+ LOG_ERROR("not enough memory");
+ return ERROR_FAIL;
+ }
+
+ bank->driver_priv = lpcspifi_info;
+ lpcspifi_info->probed = 0;
+
+ return ERROR_OK;
+}
+
+static inline int ioconfig_write_reg(struct target *target, uint32_t ioconfig_base, uint32_t offset, uint32_t value)
+{
+ return target_write_u32(target, ioconfig_base + offset, value);
+}
+
+static inline int ssp_write_reg(struct target *target, uint32_t ssp_base, uint32_t offset, uint32_t value)
+{
+ return target_write_u32(target, ssp_base + offset, value);
+}
+
+static inline int io_write_reg(struct target *target, uint32_t io_base, uint32_t offset, uint32_t value)
+{
+ return target_write_u32(target, io_base + offset, value);
+}
+
+static inline int ssp_read_reg(struct target *target, uint32_t ssp_base, uint32_t offset, uint32_t *value)
+{
+ return target_read_u32(target, ssp_base + offset, value);
+}
+
+static int ssp_setcs(struct target *target, uint32_t io_base, unsigned int value)
+{
+ return io_write_reg(target, io_base, 0x12ac, value ? 0xffffffff : 0x00000000);
+}
+
+/* Poll the SSP busy flag. When this comes back as 0, the transfer is complete
+ * and the controller is idle. */
+static int poll_ssp_busy(struct target *target, uint32_t ssp_base, int timeout)
+{
+ long long endtime;
+ uint32_t value;
+ int retval;
+
+ retval = ssp_read_reg(target, ssp_base, SSP_SR, &value);
+ if ((retval == ERROR_OK) && (value & SSP_BSY) == 0)
+ return ERROR_OK;
+ else if (retval != ERROR_OK)
+ return retval;
+
+ endtime = timeval_ms() + timeout;
+ do {
+ alive_sleep(1);
+ retval = ssp_read_reg(target, ssp_base, SSP_SR, &value);
+ if ((retval == ERROR_OK) && (value & SSP_BSY) == 0)
+ return ERROR_OK;
+ else if (retval != ERROR_OK)
+ return retval;
+ } while (timeval_ms() < endtime);
+
+ LOG_ERROR("Timeout while polling BSY");
+ return ERROR_FLASH_OPERATION_FAILED;
+}
+
+/* Un-initialize the ssp module and initialize the SPIFI module */
+static int lpcspifi_set_hw_mode(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ struct lpcspifi_flash_bank *lpcspifi_info = bank->driver_priv;
+ uint32_t ssp_base = lpcspifi_info->ssp_base;
+ struct armv7m_algorithm armv7m_info;
+ struct working_area *spifi_init_algorithm;
+ struct reg_param reg_params[2];
+ int retval = ERROR_OK;
+
+ LOG_DEBUG("Uninitializing LPC43xx SSP");
+ /* Turn off the SSP module */
+ retval = ssp_write_reg(target, ssp_base, SSP_CR1, 0x00000000);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* see contrib/loaders/flash/lpcspifi_init.S for src */
+ static const uint8_t spifi_init_code[] = {
+ 0x4f, 0xea, 0x00, 0x08, 0xa1, 0xb0, 0x00, 0xaf,
+ 0x4f, 0xf4, 0xc0, 0x43, 0xc4, 0xf2, 0x08, 0x03,
+ 0x4f, 0xf0, 0xf3, 0x02, 0xc3, 0xf8, 0x8c, 0x21,
+ 0x4f, 0xf4, 0xc0, 0x43, 0xc4, 0xf2, 0x08, 0x03,
+ 0x4f, 0xf4, 0xc0, 0x42, 0xc4, 0xf2, 0x08, 0x02,
+ 0x4f, 0xf4, 0xc0, 0x41, 0xc4, 0xf2, 0x08, 0x01,
+ 0x4f, 0xf4, 0xc0, 0x40, 0xc4, 0xf2, 0x08, 0x00,
+ 0x4f, 0xf0, 0xd3, 0x04, 0xc0, 0xf8, 0x9c, 0x41,
+ 0x20, 0x46, 0xc1, 0xf8, 0x98, 0x01, 0x01, 0x46,
+ 0xc2, 0xf8, 0x94, 0x11, 0xc3, 0xf8, 0x90, 0x11,
+ 0x4f, 0xf4, 0xc0, 0x43, 0xc4, 0xf2, 0x08, 0x03,
+ 0x4f, 0xf0, 0x13, 0x02, 0xc3, 0xf8, 0xa0, 0x21,
+ 0x40, 0xf2, 0x18, 0x13, 0xc1, 0xf2, 0x40, 0x03,
+ 0x1b, 0x68, 0x1c, 0x68, 0x40, 0xf2, 0xb4, 0x30,
+ 0xc1, 0xf2, 0x00, 0x00, 0x4f, 0xf0, 0x03, 0x01,
+ 0x4f, 0xf0, 0xc0, 0x02, 0x4f, 0xea, 0x08, 0x03,
+ 0xa0, 0x47, 0x00, 0xf0, 0x00, 0xb8, 0x00, 0xbe
+ };
+
+ armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
+ armv7m_info.core_mode = ARM_MODE_THREAD;
+
+
+ LOG_DEBUG("Allocating working area for SPIFI init algorithm");
+ /* Get memory for spifi initialization algorithm */
+ retval = target_alloc_working_area(target, sizeof(spifi_init_code)
+ + SPIFI_INIT_STACK_SIZE, &spifi_init_algorithm);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Insufficient working area to initialize SPIFI "\
+ "module. You must allocate at least %zdB of working "\
+ "area in order to use this driver.",
+ sizeof(spifi_init_code) + SPIFI_INIT_STACK_SIZE
+ );
+
+ return retval;
+ }
+
+ LOG_DEBUG("Writing algorithm to working area at 0x%08" PRIx32,
+ spifi_init_algorithm->address);
+ /* Write algorithm to working area */
+ retval = target_write_buffer(target,
+ spifi_init_algorithm->address,
+ sizeof(spifi_init_code),
+ spifi_init_code
+ );
+
+ if (retval != ERROR_OK) {
+ target_free_working_area(target, spifi_init_algorithm);
+ return retval;
+ }
+
+ init_reg_param(®_params[0], "r0", 32, PARAM_OUT); /* spifi clk speed */
+ /* the spifi_init() rom API makes use of the stack */
+ init_reg_param(®_params[1], "sp", 32, PARAM_OUT);
+
+ /* For now, the algorithm will set up the SPIFI module
+ * @ the IRC clock speed. In the future, it could be made
+ * a bit smarter to use other clock sources if the user has
+ * already configured them in order to speed up memory-
+ * mapped reads. */
+ buf_set_u32(reg_params[0].value, 0, 32, 12);
+ /* valid stack pointer */
+ buf_set_u32(reg_params[1].value, 0, 32, (spifi_init_algorithm->address +
+ sizeof(spifi_init_code) + SPIFI_INIT_STACK_SIZE) & ~7UL);
+
+ /* Run the algorithm */
+ LOG_DEBUG("Running SPIFI init algorithm");
+ retval = target_run_algorithm(target, 0 , NULL, 2, reg_params,
+ spifi_init_algorithm->address,
+ spifi_init_algorithm->address + sizeof(spifi_init_code) - 2,
+ 1000, &armv7m_info);
+
+ if (retval != ERROR_OK)
+ LOG_ERROR("Error executing SPIFI init algorithm");
+
+ target_free_working_area(target, spifi_init_algorithm);
+
+ destroy_reg_param(®_params[0]);
+ destroy_reg_param(®_params[1]);
+
+ return retval;
+}
+
+/* Initialize the ssp module */
+static int lpcspifi_set_sw_mode(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ struct lpcspifi_flash_bank *lpcspifi_info = bank->driver_priv;
+ uint32_t ssp_base = lpcspifi_info->ssp_base;
+ uint32_t io_base = lpcspifi_info->io_base;
+ uint32_t ioconfig_base = lpcspifi_info->ioconfig_base;
+ int retval = ERROR_OK;
+
+ /* Re-initialize SPIFI. There are a couple of errata on this, so this makes
+ sure that nothing's in an unhappy state. */
+ retval = lpcspifi_set_hw_mode(bank);
+
+ /* If we couldn't initialize hardware mode, don't even bother continuing */
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Initialize the pins */
+ retval = ioconfig_write_reg(target, ioconfig_base, 0x194, 0x00000040);
+ if (retval == ERROR_OK)
+ retval = ioconfig_write_reg(target, ioconfig_base, 0x1a0, 0x00000044);
+ if (retval == ERROR_OK)
+ retval = ioconfig_write_reg(target, ioconfig_base, 0x190, 0x00000040);
+ if (retval == ERROR_OK)
+ retval = ioconfig_write_reg(target, ioconfig_base, 0x19c, 0x000000ed);
+ if (retval == ERROR_OK)
+ retval = ioconfig_write_reg(target, ioconfig_base, 0x198, 0x000000ed);
+ if (retval == ERROR_OK)
+ retval = ioconfig_write_reg(target, ioconfig_base, 0x18c, 0x000000ea);
+
+ /* Set CS high & as an output */
+ if (retval == ERROR_OK)
+ retval = io_write_reg(target, io_base, 0x12ac, 0xffffffff);
+ if (retval == ERROR_OK)
+ retval = io_write_reg(target, io_base, 0x2014, 0x00000800);
+
+ /* Initialize the module */
+ if (retval == ERROR_OK)
+ retval = ssp_write_reg(target, ssp_base, SSP_CR0, 0x00000007);
+ if (retval == ERROR_OK)
+ retval = ssp_write_reg(target, ssp_base, SSP_CR1, 0x00000000);
+ if (retval == ERROR_OK)
+ retval = ssp_write_reg(target, ssp_base, SSP_CPSR, 0x00000008);
+ if (retval == ERROR_OK)
+ retval = ssp_write_reg(target, ssp_base, SSP_CR1, 0x00000002);
+
+ /* If something didn't work out, attempt to return SPIFI to HW mode */
+ if (retval != ERROR_OK)
+ lpcspifi_set_hw_mode(bank);
+
+ return retval;
+}
+
+/* Read the status register of the external SPI flash chip. */
+static int read_status_reg(struct flash_bank *bank, uint32_t *status)
+{
+ struct target *target = bank->target;
+ struct lpcspifi_flash_bank *lpcspifi_info = bank->driver_priv;
+ uint32_t ssp_base = lpcspifi_info->ssp_base;
+ uint32_t io_base = lpcspifi_info->io_base;
+ uint32_t value;
+ int retval = ERROR_OK;
+
+ retval = ssp_setcs(target, io_base, 0);
+ if (retval == ERROR_OK)
+ retval = ssp_write_reg(target, ssp_base, SSP_DATA, SPIFLASH_READ_STATUS);
+ if (retval == ERROR_OK)
+ retval = poll_ssp_busy(target, ssp_base, SSP_CMD_TIMEOUT);
+ if (retval == ERROR_OK)
+ retval = ssp_read_reg(target, ssp_base, SSP_DATA, &value);
+ /* Dummy write to clock in the register */
+ if (retval == ERROR_OK)
+ retval = ssp_write_reg(target, ssp_base, SSP_DATA, 0x00);
+ if (retval == ERROR_OK)
+ retval = poll_ssp_busy(target, ssp_base, SSP_CMD_TIMEOUT);
+ if (retval == ERROR_OK)
+ retval = ssp_setcs(target, io_base, 1);
+
+ if (retval == ERROR_OK)
+ retval = ssp_read_reg(target, ssp_base, SSP_DATA, &value);
+ if (retval == ERROR_OK)
+ *status = value;
+
+ return retval;
+}
+
+/* check for BSY bit in flash status register */
+/* timeout in ms */
+static int wait_till_ready(struct flash_bank *bank, int timeout)
+{
+ uint32_t status;
+ int retval;
+ long long endtime;
+
+ endtime = timeval_ms() + timeout;
+ do {
+ /* read flash status register */
+ retval = read_status_reg(bank, &status);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if ((status & SPIFLASH_BSY_BIT) == 0)
+ return ERROR_OK;
+ alive_sleep(1);
+ } while (timeval_ms() < endtime);
+
+ LOG_ERROR("timeout waiting for flash to finish write/erase operation");
+ return ERROR_FAIL;
+}
+
+/* Send "write enable" command to SPI flash chip. */
+static int lpcspifi_write_enable(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ struct lpcspifi_flash_bank *lpcspifi_info = bank->driver_priv;
+ uint32_t ssp_base = lpcspifi_info->ssp_base;
+ uint32_t io_base = lpcspifi_info->io_base;
+ uint32_t status, value;
+ int retval = ERROR_OK;
+
+ retval = ssp_setcs(target, io_base, 0);
+ if (retval == ERROR_OK)
+ retval = ssp_write_reg(target, ssp_base, SSP_DATA, SPIFLASH_WRITE_ENABLE);
+ if (retval == ERROR_OK)
+ retval = poll_ssp_busy(target, ssp_base, SSP_CMD_TIMEOUT);
+ if (retval == ERROR_OK)
+ retval = ssp_read_reg(target, ssp_base, SSP_DATA, &value);
+ if (retval == ERROR_OK)
+ retval = ssp_setcs(target, io_base, 1);
+
+ /* read flash status register */
+ if (retval == ERROR_OK)
+ retval = read_status_reg(bank, &status);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Check write enabled */
+ if ((status & SPIFLASH_WE_BIT) == 0) {
+ LOG_ERROR("Cannot enable write to flash. Status=0x%08" PRIx32, status);
+ return ERROR_FAIL;
+ }
+
+ return retval;
+}
+
+static int lpcspifi_bulk_erase(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ struct lpcspifi_flash_bank *lpcspifi_info = bank->driver_priv;
+ uint32_t ssp_base = lpcspifi_info->ssp_base;
+ uint32_t io_base = lpcspifi_info->io_base;
+ uint32_t value;
+ int retval = ERROR_OK;
+
+ retval = lpcspifi_set_sw_mode(bank);
+
+ if (retval == ERROR_OK)
+ retval = lpcspifi_write_enable(bank);
+
+ /* send SPI command "bulk erase" */
+ if (retval == ERROR_OK)
+ ssp_setcs(target, io_base, 0);
+ if (retval == ERROR_OK)
+ retval = ssp_write_reg(target, ssp_base, SSP_DATA, lpcspifi_info->dev->chip_erase_cmd);
+ if (retval == ERROR_OK)
+ retval = poll_ssp_busy(target, ssp_base, SSP_CMD_TIMEOUT);
+ if (retval == ERROR_OK)
+ retval = ssp_read_reg(target, ssp_base, SSP_DATA, &value);
+ if (retval == ERROR_OK)
+ retval = ssp_setcs(target, io_base, 1);
+
+ /* poll flash BSY for self-timed bulk erase */
+ if (retval == ERROR_OK)
+ retval = wait_till_ready(bank, bank->num_sectors*SSP_MAX_TIMEOUT);
+
+ return retval;
+}
+
+static int lpcspifi_erase(struct flash_bank *bank, int first, int last)
+{
+ struct target *target = bank->target;
+ struct lpcspifi_flash_bank *lpcspifi_info = bank->driver_priv;
+ struct reg_param reg_params[4];
+ struct armv7m_algorithm armv7m_info;
+ struct working_area *erase_algorithm;
+ int retval = ERROR_OK;
+ int sector;
+
+ LOG_DEBUG("erase from sector %d to sector %d", first, last);
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if ((first < 0) || (last < first) || (last >= bank->num_sectors)) {
+ LOG_ERROR("Flash sector invalid");
+ return ERROR_FLASH_SECTOR_INVALID;
+ }
+
+ if (!(lpcspifi_info->probed)) {
+ LOG_ERROR("Flash bank not probed");
+ return ERROR_FLASH_BANK_NOT_PROBED;
+ }
+
+ for (sector = first; sector <= last; sector++) {
+ if (bank->sectors[sector].is_protected) {
+ LOG_ERROR("Flash sector %d protected", sector);
+ return ERROR_FAIL;
+ }
+ }
+
+ /* If we're erasing the entire chip and the flash supports
+ * it, use a bulk erase instead of going sector-by-sector. */
+ if (first == 0 && last == (bank->num_sectors - 1)
+ && lpcspifi_info->dev->chip_erase_cmd != lpcspifi_info->dev->erase_cmd) {
+ LOG_DEBUG("Chip supports the bulk erase command."\
+ " Will use bulk erase instead of sector-by-sector erase.");
+ retval = lpcspifi_bulk_erase(bank);
+
+ if (retval == ERROR_OK) {
+ retval = lpcspifi_set_hw_mode(bank);
+ return retval;
+ } else
+ LOG_WARNING("Bulk flash erase failed. Falling back to sector-by-sector erase.");
+ }
+
+ retval = lpcspifi_set_hw_mode(bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* see contrib/loaders/flash/lpcspifi_erase.S for src */
+ static const uint8_t lpcspifi_flash_erase_code[] = {
+ 0x4f, 0xf4, 0xc0, 0x4a, 0xc4, 0xf2, 0x08, 0x0a,
+ 0x4f, 0xf0, 0xea, 0x08, 0xca, 0xf8, 0x8c, 0x81,
+ 0x4f, 0xf0, 0x40, 0x08, 0xca, 0xf8, 0x90, 0x81,
+ 0x4f, 0xf0, 0x40, 0x08, 0xca, 0xf8, 0x94, 0x81,
+ 0x4f, 0xf0, 0xed, 0x08, 0xca, 0xf8, 0x98, 0x81,
+ 0x4f, 0xf0, 0xed, 0x08, 0xca, 0xf8, 0x9c, 0x81,
+ 0x4f, 0xf0, 0x44, 0x08, 0xca, 0xf8, 0xa0, 0x81,
+ 0x4f, 0xf4, 0xc0, 0x4a, 0xc4, 0xf2, 0x0f, 0x0a,
+ 0x4f, 0xf4, 0x00, 0x68, 0xca, 0xf8, 0x14, 0x80,
+ 0x4f, 0xf4, 0x80, 0x4a, 0xc4, 0xf2, 0x0f, 0x0a,
+ 0x4f, 0xf0, 0xff, 0x08, 0xca, 0xf8, 0xab, 0x80,
+ 0x4f, 0xf0, 0x00, 0x0a, 0xc4, 0xf2, 0x05, 0x0a,
+ 0x4f, 0xf0, 0x00, 0x08, 0xc0, 0xf2, 0x00, 0x18,
+ 0xca, 0xf8, 0x94, 0x80, 0x4f, 0xf4, 0x00, 0x5a,
+ 0xc4, 0xf2, 0x05, 0x0a, 0x4f, 0xf0, 0x01, 0x08,
+ 0xca, 0xf8, 0x00, 0x87, 0x4f, 0xf4, 0x40, 0x5a,
+ 0xc4, 0xf2, 0x08, 0x0a, 0x4f, 0xf0, 0x07, 0x08,
+ 0xca, 0xf8, 0x00, 0x80, 0x4f, 0xf0, 0x02, 0x08,
+ 0xca, 0xf8, 0x10, 0x80, 0xca, 0xf8, 0x04, 0x80,
+ 0x00, 0xf0, 0x52, 0xf8, 0x4f, 0xf0, 0x06, 0x09,
+ 0x00, 0xf0, 0x3b, 0xf8, 0x00, 0xf0, 0x48, 0xf8,
+ 0x00, 0xf0, 0x4a, 0xf8, 0x4f, 0xf0, 0x05, 0x09,
+ 0x00, 0xf0, 0x33, 0xf8, 0x4f, 0xf0, 0x00, 0x09,
+ 0x00, 0xf0, 0x2f, 0xf8, 0x00, 0xf0, 0x3c, 0xf8,
+ 0x19, 0xf0, 0x02, 0x0f, 0x00, 0xf0, 0x45, 0x80,
+ 0x00, 0xf0, 0x3a, 0xf8, 0x4f, 0xea, 0x02, 0x09,
+ 0x00, 0xf0, 0x23, 0xf8, 0x4f, 0xea, 0x10, 0x49,
+ 0x00, 0xf0, 0x1f, 0xf8, 0x4f, 0xea, 0x10, 0x29,
+ 0x00, 0xf0, 0x1b, 0xf8, 0x4f, 0xea, 0x00, 0x09,
+ 0x00, 0xf0, 0x17, 0xf8, 0x00, 0xf0, 0x24, 0xf8,
+ 0x00, 0xf0, 0x26, 0xf8, 0x4f, 0xf0, 0x05, 0x09,
+ 0x00, 0xf0, 0x0f, 0xf8, 0x4f, 0xf0, 0x00, 0x09,
+ 0x00, 0xf0, 0x0b, 0xf8, 0x00, 0xf0, 0x18, 0xf8,
+ 0x19, 0xf0, 0x01, 0x0f, 0x7f, 0xf4, 0xf0, 0xaf,
+ 0x01, 0x39, 0xf9, 0xb1, 0x18, 0x44, 0xff, 0xf7,
+ 0xbf, 0xbf, 0x4f, 0xf4, 0x40, 0x5a, 0xc4, 0xf2,
+ 0x08, 0x0a, 0xca, 0xf8, 0x08, 0x90, 0xda, 0xf8,
+ 0x0c, 0x90, 0x19, 0xf0, 0x10, 0x0f, 0x7f, 0xf4,
+ 0xfa, 0xaf, 0xda, 0xf8, 0x08, 0x90, 0x70, 0x47,
+ 0x4f, 0xf0, 0xff, 0x08, 0x00, 0xf0, 0x02, 0xb8,
+ 0x4f, 0xf0, 0x00, 0x08, 0x4f, 0xf4, 0x80, 0x4a,
+ 0xc4, 0xf2, 0x0f, 0x0a, 0xca, 0xf8, 0xab, 0x80,
+ 0x70, 0x47, 0x00, 0x20, 0x00, 0xbe, 0xff, 0xff
+ };
+
+ armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
+ armv7m_info.core_mode = ARM_MODE_THREAD;
+
+
+ /* Get memory for spifi initialization algorithm */
+ retval = target_alloc_working_area(target, sizeof(lpcspifi_flash_erase_code),
+ &erase_algorithm);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Insufficient working area. You must configure a working"\
+ " area of at least %zdB in order to erase SPIFI flash.",
+ sizeof(lpcspifi_flash_erase_code));
+ return retval;
+ }
+
+ /* Write algorithm to working area */
+ retval = target_write_buffer(target, erase_algorithm->address,
+ sizeof(lpcspifi_flash_erase_code), lpcspifi_flash_erase_code);
+ if (retval != ERROR_OK) {
+ target_free_working_area(target, erase_algorithm);
+ return retval;
+ }
+
+ init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* Start address */
+ init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* Sector count */
+ init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* Erase command */
+ init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* Sector size */
+
+ buf_set_u32(reg_params[0].value, 0, 32, bank->sectors[first].offset);
+ buf_set_u32(reg_params[1].value, 0, 32, last - first + 1);
+ buf_set_u32(reg_params[2].value, 0, 32, lpcspifi_info->dev->erase_cmd);
+ buf_set_u32(reg_params[3].value, 0, 32, bank->sectors[first].size);
+
+ /* Run the algorithm */
+ retval = target_run_algorithm(target, 0 , NULL, 4, reg_params,
+ erase_algorithm->address,
+ erase_algorithm->address + sizeof(lpcspifi_flash_erase_code) - 4,
+ 3000*(last - first + 1), &armv7m_info);
+
+ if (retval != ERROR_OK)
+ LOG_ERROR("Error executing flash erase algorithm");
+
+ target_free_working_area(target, erase_algorithm);
+
+ destroy_reg_param(®_params[0]);
+ destroy_reg_param(®_params[1]);
+ destroy_reg_param(®_params[2]);
+ destroy_reg_param(®_params[3]);
+
+ retval = lpcspifi_set_hw_mode(bank);
+
+ return retval;
+}
+
+static int lpcspifi_protect(struct flash_bank *bank, int set,
+ int first, int last)
+{
+ int sector;
+
+ for (sector = first; sector <= last; sector++)
+ bank->sectors[sector].is_protected = set;
+ return ERROR_OK;
+}
+
+static int lpcspifi_write(struct flash_bank *bank, const uint8_t *buffer,
+ uint32_t offset, uint32_t count)
+{
+ struct target *target = bank->target;
+ struct lpcspifi_flash_bank *lpcspifi_info = bank->driver_priv;
+ uint32_t page_size, fifo_size;
+ struct working_area *fifo;
+ struct reg_param reg_params[5];
+ struct armv7m_algorithm armv7m_info;
+ struct working_area *write_algorithm;
+ int sector;
+ int retval = ERROR_OK;
+
+ LOG_DEBUG("offset=0x%08" PRIx32 " count=0x%08" PRIx32,
+ offset, count);
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (offset + count > lpcspifi_info->dev->size_in_bytes) {
+ LOG_WARNING("Writes past end of flash. Extra data discarded.");
+ count = lpcspifi_info->dev->size_in_bytes - offset;
+ }
+
+ /* Check sector protection */
+ for (sector = 0; sector < bank->num_sectors; sector++) {
+ /* Start offset in or before this sector? */
+ /* End offset in or behind this sector? */
+ if ((offset <
+ (bank->sectors[sector].offset + bank->sectors[sector].size))
+ && ((offset + count - 1) >= bank->sectors[sector].offset)
+ && bank->sectors[sector].is_protected) {
+ LOG_ERROR("Flash sector %d protected", sector);
+ return ERROR_FAIL;
+ }
+ }
+
+ page_size = lpcspifi_info->dev->pagesize;
+
+ retval = lpcspifi_set_hw_mode(bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* see contrib/loaders/flash/lpcspifi_write.S for src */
+ static const uint8_t lpcspifi_flash_write_code[] = {
+ 0x4f, 0xf4, 0xc0, 0x4a, 0xc4, 0xf2, 0x08, 0x0a,
+ 0x4f, 0xf0, 0xea, 0x08, 0xca, 0xf8, 0x8c, 0x81,
+ 0x4f, 0xf0, 0x40, 0x08, 0xca, 0xf8, 0x90, 0x81,
+ 0x4f, 0xf0, 0x40, 0x08, 0xca, 0xf8, 0x94, 0x81,
+ 0x4f, 0xf0, 0xed, 0x08, 0xca, 0xf8, 0x98, 0x81,
+ 0x4f, 0xf0, 0xed, 0x08, 0xca, 0xf8, 0x9c, 0x81,
+ 0x4f, 0xf0, 0x44, 0x08, 0xca, 0xf8, 0xa0, 0x81,
+ 0x4f, 0xf4, 0xc0, 0x4a, 0xc4, 0xf2, 0x0f, 0x0a,
+ 0x4f, 0xf4, 0x00, 0x68, 0xca, 0xf8, 0x14, 0x80,
+ 0x4f, 0xf4, 0x80, 0x4a, 0xc4, 0xf2, 0x0f, 0x0a,
+ 0x4f, 0xf0, 0xff, 0x08, 0xca, 0xf8, 0xab, 0x80,
+ 0x4f, 0xf0, 0x00, 0x0a, 0xc4, 0xf2, 0x05, 0x0a,
+ 0x4f, 0xf0, 0x00, 0x08, 0xc0, 0xf2, 0x00, 0x18,
+ 0xca, 0xf8, 0x94, 0x80, 0x4f, 0xf4, 0x00, 0x5a,
+ 0xc4, 0xf2, 0x05, 0x0a, 0x4f, 0xf0, 0x01, 0x08,
+ 0xca, 0xf8, 0x00, 0x87, 0x4f, 0xf4, 0x40, 0x5a,
+ 0xc4, 0xf2, 0x08, 0x0a, 0x4f, 0xf0, 0x07, 0x08,
+ 0xca, 0xf8, 0x00, 0x80, 0x4f, 0xf0, 0x02, 0x08,
+ 0xca, 0xf8, 0x10, 0x80, 0xca, 0xf8, 0x04, 0x80,
+ 0x4f, 0xf0, 0x00, 0x0b, 0xa3, 0x44, 0x93, 0x45,
+ 0x7f, 0xf6, 0xfc, 0xaf, 0x00, 0xf0, 0x6a, 0xf8,
+ 0x4f, 0xf0, 0x06, 0x09, 0x00, 0xf0, 0x53, 0xf8,
+ 0x00, 0xf0, 0x60, 0xf8, 0x00, 0xf0, 0x62, 0xf8,
+ 0x4f, 0xf0, 0x05, 0x09, 0x00, 0xf0, 0x4b, 0xf8,
+ 0x4f, 0xf0, 0x00, 0x09, 0x00, 0xf0, 0x47, 0xf8,
+ 0x00, 0xf0, 0x54, 0xf8, 0x19, 0xf0, 0x02, 0x0f,
+ 0x00, 0xf0, 0x5d, 0x80, 0x00, 0xf0, 0x52, 0xf8,
+ 0x4f, 0xf0, 0x02, 0x09, 0x00, 0xf0, 0x3b, 0xf8,
+ 0x4f, 0xea, 0x12, 0x49, 0x00, 0xf0, 0x37, 0xf8,
+ 0x4f, 0xea, 0x12, 0x29, 0x00, 0xf0, 0x33, 0xf8,
+ 0x4f, 0xea, 0x02, 0x09, 0x00, 0xf0, 0x2f, 0xf8,
+ 0xd0, 0xf8, 0x00, 0x80, 0xb8, 0xf1, 0x00, 0x0f,
+ 0x00, 0xf0, 0x47, 0x80, 0x47, 0x68, 0x47, 0x45,
+ 0x3f, 0xf4, 0xf6, 0xaf, 0x17, 0xf8, 0x01, 0x9b,
+ 0x00, 0xf0, 0x21, 0xf8, 0x8f, 0x42, 0x28, 0xbf,
+ 0x00, 0xf1, 0x08, 0x07, 0x47, 0x60, 0x01, 0x3b,
+ 0xbb, 0xb3, 0x02, 0xf1, 0x01, 0x02, 0x93, 0x45,
+ 0x7f, 0xf4, 0xe6, 0xaf, 0x00, 0xf0, 0x22, 0xf8,
+ 0xa3, 0x44, 0x00, 0xf0, 0x23, 0xf8, 0x4f, 0xf0,
+ 0x05, 0x09, 0x00, 0xf0, 0x0c, 0xf8, 0x4f, 0xf0,
+ 0x00, 0x09, 0x00, 0xf0, 0x08, 0xf8, 0x00, 0xf0,
+ 0x15, 0xf8, 0x19, 0xf0, 0x01, 0x0f, 0x7f, 0xf4,
+ 0xf0, 0xaf, 0xff, 0xf7, 0xa7, 0xbf, 0x4f, 0xf4,
+ 0x40, 0x5a, 0xc4, 0xf2, 0x08, 0x0a, 0xca, 0xf8,
+ 0x08, 0x90, 0xda, 0xf8, 0x0c, 0x90, 0x19, 0xf0,
+ 0x10, 0x0f, 0x7f, 0xf4, 0xfa, 0xaf, 0xda, 0xf8,
+ 0x08, 0x90, 0x70, 0x47, 0x4f, 0xf0, 0xff, 0x08,
+ 0x00, 0xf0, 0x02, 0xb8, 0x4f, 0xf0, 0x00, 0x08,
+ 0x4f, 0xf4, 0x80, 0x4a, 0xc4, 0xf2, 0x0f, 0x0a,
+ 0xca, 0xf8, 0xab, 0x80, 0x70, 0x47, 0x00, 0x20,
+ 0x50, 0x60, 0xff, 0xf7, 0xef, 0xff, 0x30, 0x46,
+ 0x00, 0xbe, 0xff, 0xff
+ };
+
+ if (target_alloc_working_area(target, sizeof(lpcspifi_flash_write_code),
+ &write_algorithm) != ERROR_OK) {
+ LOG_ERROR("Insufficient working area. You must configure"\
+ " a working area > %zdB in order to write to SPIFI flash.",
+ sizeof(lpcspifi_flash_write_code));
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ retval = target_write_buffer(target, write_algorithm->address,
+ sizeof(lpcspifi_flash_write_code),
+ lpcspifi_flash_write_code);
+ if (retval != ERROR_OK) {
+ target_free_working_area(target, write_algorithm);
+ return retval;
+ }
+
+ /* FIFO allocation */
+ fifo_size = target_get_working_area_avail(target);
+
+ if (fifo_size == 0) {
+ /* if we already allocated the writing code but failed to get fifo
+ * space, free the algorithm */
+ target_free_working_area(target, write_algorithm);
+
+ LOG_ERROR("Insufficient working area. Please allocate at least"\
+ " %zdB of working area to enable flash writes.",
+ sizeof(lpcspifi_flash_write_code) + 1
+ );
+
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ } else if (fifo_size < page_size)
+ LOG_WARNING("Working area size is limited; flash writes may be"\
+ " slow. Increase working area size to at least %zdB"\
+ " to reduce write times.",
+ (size_t)(sizeof(lpcspifi_flash_write_code) + page_size)
+ );
+ else if (fifo_size > 0x2000) /* Beyond this point, we start to get diminishing returns */
+ fifo_size = 0x2000;
+
+ if (target_alloc_working_area(target, fifo_size, &fifo) != ERROR_OK) {
+ target_free_working_area(target, write_algorithm);
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
+ armv7m_info.core_mode = ARM_MODE_THREAD;
+
+ init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
+ init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* buffer end */
+ init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* target address */
+ init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* count (halfword-16bit) */
+ init_reg_param(®_params[4], "r4", 32, PARAM_OUT); /* page size */
+
+ buf_set_u32(reg_params[0].value, 0, 32, fifo->address);
+ buf_set_u32(reg_params[1].value, 0, 32, fifo->address + fifo->size);
+ buf_set_u32(reg_params[2].value, 0, 32, offset);
+ buf_set_u32(reg_params[3].value, 0, 32, count);
+ buf_set_u32(reg_params[4].value, 0, 32, page_size);
+
+ retval = target_run_flash_async_algorithm(target, buffer, count, 1,
+ 0, NULL,
+ 5, reg_params,
+ fifo->address, fifo->size,
+ write_algorithm->address, 0,
+ &armv7m_info
+ );
+
+ if (retval != ERROR_OK)
+ LOG_ERROR("Error executing flash write algorithm");
+
+ target_free_working_area(target, fifo);
+ target_free_working_area(target, write_algorithm);
+
+ destroy_reg_param(®_params[0]);
+ destroy_reg_param(®_params[1]);
+ destroy_reg_param(®_params[2]);
+ destroy_reg_param(®_params[3]);
+ destroy_reg_param(®_params[4]);
+
+ /* Switch to HW mode before return to prompt */
+ retval = lpcspifi_set_hw_mode(bank);
+ return retval;
+}
+
+/* Return ID of flash device */
+/* On exit, SW mode is kept */
+static int lpcspifi_read_flash_id(struct flash_bank *bank, uint32_t *id)
+{
+ struct target *target = bank->target;
+ struct lpcspifi_flash_bank *lpcspifi_info = bank->driver_priv;
+ uint32_t ssp_base = lpcspifi_info->ssp_base;
+ uint32_t io_base = lpcspifi_info->io_base;
+ uint32_t value;
+ uint8_t id_buf[3] = {0, 0, 0};
+ int retval;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ LOG_DEBUG("Getting ID");
+ retval = lpcspifi_set_sw_mode(bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* poll WIP */
+ if (retval == ERROR_OK)
+ retval = wait_till_ready(bank, SSP_PROBE_TIMEOUT);
+
+ /* Send SPI command "read ID" */
+ if (retval == ERROR_OK)
+ retval = ssp_setcs(target, io_base, 0);
+ if (retval == ERROR_OK)
+ retval = ssp_write_reg(target, ssp_base, SSP_DATA, SPIFLASH_READ_ID);
+ if (retval == ERROR_OK)
+ retval = poll_ssp_busy(target, ssp_base, SSP_CMD_TIMEOUT);
+ if (retval == ERROR_OK)
+ retval = ssp_read_reg(target, ssp_base, SSP_DATA, &value);
+
+ /* Dummy write to clock in data */
+ if (retval == ERROR_OK)
+ retval = ssp_write_reg(target, ssp_base, SSP_DATA, 0x00);
+ if (retval == ERROR_OK)
+ retval = poll_ssp_busy(target, ssp_base, SSP_CMD_TIMEOUT);
+ if (retval == ERROR_OK)
+ retval = ssp_read_reg(target, ssp_base, SSP_DATA, &value);
+ if (retval == ERROR_OK)
+ id_buf[0] = value;
+
+ /* Dummy write to clock in data */
+ if (retval == ERROR_OK)
+ retval = ssp_write_reg(target, ssp_base, SSP_DATA, 0x00);
+ if (retval == ERROR_OK)
+ retval = poll_ssp_busy(target, ssp_base, SSP_CMD_TIMEOUT);
+ if (retval == ERROR_OK)
+ retval = ssp_read_reg(target, ssp_base, SSP_DATA, &value);
+ if (retval == ERROR_OK)
+ id_buf[1] = value;
+
+ /* Dummy write to clock in data */
+ if (retval == ERROR_OK)
+ retval = ssp_write_reg(target, ssp_base, SSP_DATA, 0x00);
+ if (retval == ERROR_OK)
+ retval = poll_ssp_busy(target, ssp_base, SSP_CMD_TIMEOUT);
+ if (retval == ERROR_OK)
+ retval = ssp_read_reg(target, ssp_base, SSP_DATA, &value);
+ if (retval == ERROR_OK)
+ id_buf[2] = value;
+
+ if (retval == ERROR_OK)
+ retval = ssp_setcs(target, io_base, 1);
+ if (retval == ERROR_OK)
+ *id = id_buf[2] << 16 | id_buf[1] << 8 | id_buf[0];
+
+ return retval;
+}
+
+static int lpcspifi_probe(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ struct lpcspifi_flash_bank *lpcspifi_info = bank->driver_priv;
+ uint32_t ssp_base;
+ uint32_t io_base;
+ uint32_t ioconfig_base;
+ struct flash_sector *sectors;
+ uint32_t id = 0; /* silence uninitialized warning */
+ const struct lpcspifi_target *target_device;
+ int retval;
+
+ /* If we've already probed, we should be fine to skip this time. */
+ if (lpcspifi_info->probed)
+ return ERROR_OK;
+ lpcspifi_info->probed = 0;
+
+ for (target_device = target_devices ; target_device->name ; ++target_device)
+ if (target_device->tap_idcode == target->tap->idcode)
+ break;
+ if (!target_device->name) {
+ LOG_ERROR("Device ID 0x%" PRIx32 " is not known as SPIFI capable",
+ target->tap->idcode);
+ return ERROR_FAIL;
+ }
+
+ ssp_base = target_device->ssp_base;
+ io_base = target_device->io_base;
+ ioconfig_base = target_device->ioconfig_base;
+ lpcspifi_info->ssp_base = ssp_base;
+ lpcspifi_info->io_base = io_base;
+ lpcspifi_info->ioconfig_base = ioconfig_base;
+ lpcspifi_info->bank_num = bank->bank_number;
+
+ LOG_DEBUG("Valid SPIFI on device %s at address 0x%" PRIx32,
+ target_device->name, bank->base);
+
+ /* read and decode flash ID; returns in SW mode */
+ retval = lpcspifi_read_flash_id(bank, &id);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = lpcspifi_set_hw_mode(bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ lpcspifi_info->dev = NULL;
+ for (const struct flash_device *p = flash_devices; p->name ; p++)
+ if (p->device_id == id) {
+ lpcspifi_info->dev = p;
+ break;
+ }
+
+ if (!lpcspifi_info->dev) {
+ LOG_ERROR("Unknown flash device (ID 0x%08" PRIx32 ")", id);
+ return ERROR_FAIL;
+ }
+
+ LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32 ")",
+ lpcspifi_info->dev->name, lpcspifi_info->dev->device_id);
+
+ /* Set correct size value */
+ bank->size = lpcspifi_info->dev->size_in_bytes;
+
+ /* create and fill sectors array */
+ bank->num_sectors =
+ lpcspifi_info->dev->size_in_bytes / lpcspifi_info->dev->sectorsize;
+ sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
+ if (sectors == NULL) {
+ LOG_ERROR("not enough memory");
+ return ERROR_FAIL;
+ }
+
+ for (int sector = 0; sector < bank->num_sectors; sector++) {
+ sectors[sector].offset = sector * lpcspifi_info->dev->sectorsize;
+ sectors[sector].size = lpcspifi_info->dev->sectorsize;
+ sectors[sector].is_erased = -1;
+ sectors[sector].is_protected = 0;
+ }
+
+ bank->sectors = sectors;
+
+ lpcspifi_info->probed = 1;
+ return ERROR_OK;
+}
+
+static int lpcspifi_auto_probe(struct flash_bank *bank)
+{
+ struct lpcspifi_flash_bank *lpcspifi_info = bank->driver_priv;
+ if (lpcspifi_info->probed)
+ return ERROR_OK;
+ return lpcspifi_probe(bank);
+}
+
+static int lpcspifi_protect_check(struct flash_bank *bank)
+{
+ /* Nothing to do. Protection is only handled in SW. */
+ return ERROR_OK;
+}
+
+static int get_lpcspifi_info(struct flash_bank *bank, char *buf, int buf_size)
+{
+ struct lpcspifi_flash_bank *lpcspifi_info = bank->driver_priv;
+
+ if (!(lpcspifi_info->probed)) {
+ snprintf(buf, buf_size,
+ "\nSPIFI flash bank not probed yet\n");
+ return ERROR_OK;
+ }
+
+ snprintf(buf, buf_size, "\nSPIFI flash information:\n"
+ " Device \'%s\' (ID 0x%08" PRIx32 ")\n",
+ lpcspifi_info->dev->name, lpcspifi_info->dev->device_id);
+
+ return ERROR_OK;
+}
+
+struct flash_driver lpcspifi_flash = {
+ .name = "lpcspifi",
+ .flash_bank_command = lpcspifi_flash_bank_command,
+ .erase = lpcspifi_erase,
+ .protect = lpcspifi_protect,
+ .write = lpcspifi_write,
+ .read = default_flash_read,
+ .probe = lpcspifi_probe,
+ .auto_probe = lpcspifi_auto_probe,
+ .erase_check = default_flash_blank_check,
+ .protect_check = lpcspifi_protect_check,
+ .info = get_lpcspifi_info,
+};
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/mdr.c
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/mdr.c b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/mdr.c
new file mode 100755
index 0000000..c402e64
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/mdr.c
@@ -0,0 +1,630 @@
+/***************************************************************************
+ * Copyright (C) 2005 by Dominic Rath *
+ * Dominic.Rath@gmx.de *
+ * *
+ * Copyright (C) 2008 by Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ * *
+ * Copyright (C) 2011 by Andreas Fritiofson *
+ * andreas.fritiofson@gmail.com *
+ * *
+ * Copyright (C) 2013 by Paul Fertser *
+ * fercerpav@gmail.com *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "imp.h"
+#include <helper/binarybuffer.h>
+#include <target/algorithm.h>
+#include <target/armv7m.h>
+
+#define MD_RST_CLK 0x40020000
+#define MD_PER_CLOCK (MD_RST_CLK + 0x1C)
+#define MD_PER_CLOCK_EEPROM (1 << 3)
+#define MD_PER_CLOCK_RST_CLK (1 << 4)
+
+#define FLASH_REG_BASE 0x40018000
+#define FLASH_CMD (FLASH_REG_BASE + 0x00)
+#define FLASH_ADR (FLASH_REG_BASE + 0x04)
+#define FLASH_DI (FLASH_REG_BASE + 0x08)
+#define FLASH_DO (FLASH_REG_BASE + 0x0C)
+#define FLASH_KEY (FLASH_REG_BASE + 0x10)
+
+#define FLASH_NVSTR (1 << 13)
+#define FLASH_PROG (1 << 12)
+#define FLASH_MAS1 (1 << 11)
+#define FLASH_ERASE (1 << 10)
+#define FLASH_IFREN (1 << 9)
+#define FLASH_SE (1 << 8)
+#define FLASH_YE (1 << 7)
+#define FLASH_XE (1 << 6)
+#define FLASH_RD (1 << 2)
+#define FLASH_WR (1 << 1)
+#define FLASH_CON (1 << 0)
+#define FLASH_DELAY_MASK (7 << 3)
+
+#define KEY 0x8AAA5551
+
+struct mdr_flash_bank {
+ int probed;
+ unsigned int mem_type;
+ unsigned int page_count;
+ unsigned int sec_count;
+};
+
+/* flash bank <name> mdr <base> <size> 0 0 <target#> <type> <page_count> <sec_count> */
+FLASH_BANK_COMMAND_HANDLER(mdr_flash_bank_command)
+{
+ struct mdr_flash_bank *mdr_info;
+
+ if (CMD_ARGC < 9)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ mdr_info = malloc(sizeof(struct mdr_flash_bank));
+
+ bank->driver_priv = mdr_info;
+ mdr_info->probed = 0;
+ COMMAND_PARSE_NUMBER(uint, CMD_ARGV[6], mdr_info->mem_type);
+ COMMAND_PARSE_NUMBER(uint, CMD_ARGV[7], mdr_info->page_count);
+ COMMAND_PARSE_NUMBER(uint, CMD_ARGV[8], mdr_info->sec_count);
+ return ERROR_OK;
+}
+
+static int mdr_protect_check(struct flash_bank *bank)
+{
+ return ERROR_OK;
+}
+
+static int mdr_mass_erase(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ struct mdr_flash_bank *mdr_info = bank->driver_priv;
+ uint32_t flash_cmd;
+ int retval;
+ unsigned int i;
+
+ retval = target_read_u32(target, FLASH_CMD, &flash_cmd);
+ if (retval != ERROR_OK)
+ return retval;
+
+ for (i = 0; i < mdr_info->sec_count; i++) {
+ retval = target_write_u32(target, FLASH_ADR, i << 2);
+ if (retval != ERROR_OK)
+ return retval;
+
+ flash_cmd |= FLASH_XE | FLASH_MAS1 | FLASH_ERASE;
+ retval = target_write_u32(target, FLASH_CMD, flash_cmd);
+ if (retval != ERROR_OK)
+ return retval;
+ flash_cmd |= FLASH_NVSTR;
+ retval = target_write_u32(target, FLASH_CMD, flash_cmd);
+ if (retval != ERROR_OK)
+ return retval;
+ flash_cmd &= ~FLASH_ERASE;
+ retval = target_write_u32(target, FLASH_CMD, flash_cmd);
+ if (retval != ERROR_OK)
+ return retval;
+ flash_cmd &= ~(FLASH_XE | FLASH_MAS1 | FLASH_NVSTR);
+ retval = target_write_u32(target, FLASH_CMD, flash_cmd);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ return retval;
+}
+
+static int mdr_erase(struct flash_bank *bank, int first, int last)
+{
+ struct target *target = bank->target;
+ struct mdr_flash_bank *mdr_info = bank->driver_priv;
+ int i, retval, retval2;
+ unsigned int j;
+ uint32_t flash_cmd, cur_per_clock;
+
+ if (bank->target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ retval = target_read_u32(target, MD_PER_CLOCK, &cur_per_clock);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (!(cur_per_clock & 0x10)) {
+ LOG_ERROR("Target needs reset before flash operations");
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ retval = target_write_u32(target, MD_PER_CLOCK, cur_per_clock | MD_PER_CLOCK_EEPROM);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = target_write_u32(target, FLASH_KEY, KEY);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = target_read_u32(target, FLASH_CMD, &flash_cmd);
+ if (retval != ERROR_OK)
+ goto reset_pg_and_lock;
+
+ /* Switch on register access */
+ flash_cmd = (flash_cmd & FLASH_DELAY_MASK) | FLASH_CON;
+ if (mdr_info->mem_type)
+ flash_cmd |= FLASH_IFREN;
+ retval = target_write_u32(target, FLASH_CMD, flash_cmd);
+ if (retval != ERROR_OK)
+ goto reset_pg_and_lock;
+
+ if ((first == 0) && (last == (bank->num_sectors - 1))) {
+ retval = mdr_mass_erase(bank);
+ goto reset_pg_and_lock;
+ }
+
+ unsigned int page_size = bank->size / mdr_info->page_count;
+ for (i = first; i <= last; i++) {
+ for (j = 0; j < mdr_info->sec_count; j++) {
+ retval = target_write_u32(target, FLASH_ADR, (i * page_size) | (j << 2));
+ if (retval != ERROR_OK)
+ goto reset_pg_and_lock;
+
+ flash_cmd |= FLASH_XE | FLASH_ERASE;
+ retval = target_write_u32(target, FLASH_CMD, flash_cmd);
+ if (retval != ERROR_OK)
+ goto reset_pg_and_lock;
+ flash_cmd |= FLASH_NVSTR;
+ retval = target_write_u32(target, FLASH_CMD, flash_cmd);
+ if (retval != ERROR_OK)
+ goto reset_pg_and_lock;
+ flash_cmd &= ~FLASH_ERASE;
+ retval = target_write_u32(target, FLASH_CMD, flash_cmd);
+ if (retval != ERROR_OK)
+ goto reset_pg_and_lock;
+ flash_cmd &= ~(FLASH_XE | FLASH_NVSTR);
+ retval = target_write_u32(target, FLASH_CMD, flash_cmd);
+ if (retval != ERROR_OK)
+ goto reset_pg_and_lock;
+ }
+ bank->sectors[i].is_erased = 1;
+ }
+
+reset_pg_and_lock:
+ flash_cmd &= FLASH_DELAY_MASK;
+ retval2 = target_write_u32(target, FLASH_CMD, flash_cmd);
+ if (retval == ERROR_OK)
+ retval = retval2;
+
+ retval2 = target_write_u32(target, FLASH_KEY, 0);
+ if (retval == ERROR_OK)
+ retval = retval2;
+
+ return retval;
+}
+
+static int mdr_protect(struct flash_bank *bank, int set, int first, int last)
+{
+ return ERROR_OK;
+}
+
+static int mdr_write_block(struct flash_bank *bank, const uint8_t *buffer,
+ uint32_t offset, uint32_t count)
+{
+ struct target *target = bank->target;
+ uint32_t buffer_size = 16384;
+ struct working_area *write_algorithm;
+ struct working_area *source;
+ uint32_t address = bank->base + offset;
+ struct reg_param reg_params[5];
+ struct armv7m_algorithm armv7m_info;
+ int retval = ERROR_OK;
+
+ /* see contrib/loaders/flash/mdr32fx.S for src */
+ static const uint8_t mdr32fx_flash_write_code[] = {
+ 0x07, 0x68, 0x16, 0x68, 0x00, 0x2e, 0x2e, 0xd0, 0x55, 0x68, 0xb5, 0x42,
+ 0xf9, 0xd0, 0x2e, 0x68, 0x44, 0x60, 0x86, 0x60, 0x17, 0x4e, 0x37, 0x43,
+ 0x07, 0x60, 0x05, 0x26, 0x00, 0xf0, 0x25, 0xf8, 0x15, 0x4e, 0x37, 0x43,
+ 0x07, 0x60, 0x0d, 0x26, 0x00, 0xf0, 0x1f, 0xf8, 0x80, 0x26, 0x37, 0x43,
+ 0x07, 0x60, 0x3d, 0x26, 0x00, 0xf0, 0x19, 0xf8, 0x80, 0x26, 0xb7, 0x43,
+ 0x07, 0x60, 0x0f, 0x4e, 0xb7, 0x43, 0x07, 0x60, 0x05, 0x26, 0x00, 0xf0,
+ 0x10, 0xf8, 0x0d, 0x4e, 0xb7, 0x43, 0x07, 0x60, 0x04, 0x35, 0x04, 0x34,
+ 0x9d, 0x42, 0x01, 0xd3, 0x15, 0x46, 0x08, 0x35, 0x55, 0x60, 0x01, 0x39,
+ 0x00, 0x29, 0x00, 0xd0, 0xcd, 0xe7, 0x30, 0x46, 0x00, 0xbe, 0x01, 0x3e,
+ 0x00, 0x2e, 0xfc, 0xd1, 0x70, 0x47, 0x00, 0x00, 0x40, 0x10, 0x00, 0x00,
+ 0x00, 0x20, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x40, 0x20, 0x00, 0x00
+ };
+
+ /* flash write code */
+ if (target_alloc_working_area(target, sizeof(mdr32fx_flash_write_code),
+ &write_algorithm) != ERROR_OK) {
+ LOG_WARNING("no working area available, can't do block memory writes");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ retval = target_write_buffer(target, write_algorithm->address,
+ sizeof(mdr32fx_flash_write_code), mdr32fx_flash_write_code);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* memory buffer */
+ while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
+ buffer_size /= 2;
+ buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
+ if (buffer_size <= 256) {
+ /* we already allocated the writing code, but failed to get a
+ * buffer, free the algorithm */
+ target_free_working_area(target, write_algorithm);
+
+ LOG_WARNING("no large enough working area available, can't do block memory writes");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+ }
+
+ init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
+ init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* count (32bit) */
+ init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* buffer start */
+ init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* buffer end */
+ init_reg_param(®_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
+
+ buf_set_u32(reg_params[0].value, 0, 32, FLASH_REG_BASE);
+ buf_set_u32(reg_params[1].value, 0, 32, count);
+ buf_set_u32(reg_params[2].value, 0, 32, source->address);
+ buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
+ buf_set_u32(reg_params[4].value, 0, 32, address);
+
+ armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
+ armv7m_info.core_mode = ARM_MODE_THREAD;
+
+ retval = target_run_flash_async_algorithm(target, buffer, count, 4,
+ 0, NULL,
+ 5, reg_params,
+ source->address, source->size,
+ write_algorithm->address, 0,
+ &armv7m_info);
+
+ if (retval == ERROR_FLASH_OPERATION_FAILED)
+ LOG_ERROR("flash write failed at address 0x%"PRIx32,
+ buf_get_u32(reg_params[4].value, 0, 32));
+
+ target_free_working_area(target, source);
+ target_free_working_area(target, write_algorithm);
+
+ destroy_reg_param(®_params[0]);
+ destroy_reg_param(®_params[1]);
+ destroy_reg_param(®_params[2]);
+ destroy_reg_param(®_params[3]);
+ destroy_reg_param(®_params[4]);
+
+ return retval;
+}
+
+static int mdr_write(struct flash_bank *bank, const uint8_t *buffer,
+ uint32_t offset, uint32_t count)
+{
+ struct target *target = bank->target;
+ struct mdr_flash_bank *mdr_info = bank->driver_priv;
+ uint8_t *new_buffer = NULL;
+
+ if (bank->target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (offset & 0x3) {
+ LOG_ERROR("offset 0x%" PRIx32 " breaks required 4-byte alignment", offset);
+ return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
+ }
+
+ /* If there's an odd number of bytes, the data has to be padded. Duplicate
+ * the buffer and use the normal code path with a single block write since
+ * it's probably cheaper than to special case the last odd write using
+ * discrete accesses. */
+ int rem = count % 4;
+ if (rem) {
+ new_buffer = malloc(count + rem);
+ if (new_buffer == NULL) {
+ LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
+ return ERROR_FAIL;
+ }
+ LOG_INFO("odd number of bytes to write, padding with 0xff");
+ buffer = memcpy(new_buffer, buffer, count);
+ while (rem--)
+ new_buffer[count++] = 0xff;
+ }
+
+ uint32_t flash_cmd, cur_per_clock;
+ int retval, retval2;
+
+ retval = target_read_u32(target, MD_PER_CLOCK, &cur_per_clock);
+ if (retval != ERROR_OK)
+ goto free_buffer;
+
+ if (!(cur_per_clock & MD_PER_CLOCK_RST_CLK)) {
+ /* Something's very wrong if the RST_CLK module is not clocked */
+ LOG_ERROR("Target needs reset before flash operations");
+ retval = ERROR_FLASH_OPERATION_FAILED;
+ goto free_buffer;
+ }
+
+ retval = target_write_u32(target, MD_PER_CLOCK, cur_per_clock | MD_PER_CLOCK_EEPROM);
+ if (retval != ERROR_OK)
+ goto free_buffer;
+
+ retval = target_write_u32(target, FLASH_KEY, KEY);
+ if (retval != ERROR_OK)
+ goto free_buffer;
+
+ retval = target_read_u32(target, FLASH_CMD, &flash_cmd);
+ if (retval != ERROR_OK)
+ goto reset_pg_and_lock;
+
+ /* Switch on register access */
+ flash_cmd = (flash_cmd & FLASH_DELAY_MASK) | FLASH_CON;
+ if (mdr_info->mem_type)
+ flash_cmd |= FLASH_IFREN;
+ retval = target_write_u32(target, FLASH_CMD, flash_cmd);
+ if (retval != ERROR_OK)
+ goto reset_pg_and_lock;
+
+ /* try using block write */
+ retval = mdr_write_block(bank, buffer, offset, count/4);
+
+ if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
+ /* if block write failed (no sufficient working area),
+ * we use normal (slow) single halfword accesses */
+ LOG_WARNING("Can't use block writes, falling back to single memory accesses");
+
+ unsigned int page_size = bank->size / mdr_info->page_count;
+ unsigned int page_mask = page_size - 1;
+ while (count > 0) {
+ unsigned int i, j;
+ unsigned int cur_page = offset & ~page_mask;
+ unsigned int bytes_to_write = cur_page + page_size - offset;
+ if (count < bytes_to_write)
+ bytes_to_write = count;
+
+ /*LOG_INFO("Selecting next page: %08x", cur_page);*/
+
+ for (i = 0; i < mdr_info->sec_count; i++) {
+ retval = target_write_u32(target, FLASH_ADR, offset + i*4);
+ if (retval != ERROR_OK)
+ goto reset_pg_and_lock;
+ /*LOG_INFO("Selecting page/sector: %08x", offset + i*4);*/
+
+ flash_cmd |= FLASH_XE | FLASH_PROG;
+ retval = target_write_u32(target, FLASH_CMD, flash_cmd);
+ if (retval != ERROR_OK)
+ goto reset_pg_and_lock;
+
+ flash_cmd |= FLASH_NVSTR;
+ retval = target_write_u32(target, FLASH_CMD, flash_cmd);
+ if (retval != ERROR_OK)
+ goto reset_pg_and_lock;
+
+ for (j = 0;
+ (((offset + j + i*4) & ~page_mask) == cur_page) &&
+ (j + i*4 < count);
+ j += mdr_info->sec_count*4) {
+ uint32_t value;
+ memcpy(&value, buffer + j + i*4, sizeof(uint32_t));
+ retval = target_write_u32(target, FLASH_DI, value);
+ if (retval != ERROR_OK)
+ goto reset_pg_and_lock;
+ /*LOG_INFO("Writing to addr %08x", offset + j + i*4);*/
+ retval = target_write_u32(target, FLASH_ADR, offset + j + i*4);
+ if (retval != ERROR_OK)
+ goto reset_pg_and_lock;
+
+ flash_cmd |= FLASH_YE;
+ retval = target_write_u32(target, FLASH_CMD, flash_cmd);
+ if (retval != ERROR_OK)
+ goto reset_pg_and_lock;
+ flash_cmd &= ~FLASH_YE;
+ retval = target_write_u32(target, FLASH_CMD, flash_cmd);
+ if (retval != ERROR_OK)
+ goto reset_pg_and_lock;
+ }
+ flash_cmd &= ~FLASH_NVSTR;
+ retval = target_write_u32(target, FLASH_CMD, flash_cmd);
+ if (retval != ERROR_OK)
+ goto reset_pg_and_lock;
+
+ flash_cmd &= ~(FLASH_XE | FLASH_PROG);
+ retval = target_write_u32(target, FLASH_CMD, flash_cmd);
+ if (retval != ERROR_OK)
+ goto reset_pg_and_lock;
+ }
+
+ buffer += bytes_to_write;
+ offset += bytes_to_write;
+ count -= bytes_to_write;
+ }
+ }
+
+reset_pg_and_lock:
+ flash_cmd &= FLASH_DELAY_MASK;
+ retval2 = target_write_u32(target, FLASH_CMD, flash_cmd);
+ if (retval == ERROR_OK)
+ retval = retval2;
+
+ retval2 = target_write_u32(target, FLASH_KEY, 0);
+ if (retval == ERROR_OK)
+ retval = retval2;
+
+free_buffer:
+ if (new_buffer)
+ free(new_buffer);
+
+ return retval;
+}
+
+static int mdr_read(struct flash_bank *bank, uint8_t *buffer,
+ uint32_t offset, uint32_t count)
+{
+ struct target *target = bank->target;
+ struct mdr_flash_bank *mdr_info = bank->driver_priv;
+ int retval, retval2;
+
+ if (!mdr_info->mem_type)
+ return default_flash_read(bank, buffer, offset, count);
+
+ if (bank->target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (offset & 0x3) {
+ LOG_ERROR("offset 0x%" PRIx32 " breaks required 4-byte alignment", offset);
+ return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
+ }
+
+ if (count & 0x3) {
+ LOG_ERROR("count 0x%" PRIx32 " breaks required 4-byte alignment", count);
+ return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
+ }
+
+ uint32_t flash_cmd, cur_per_clock;
+
+ retval = target_read_u32(target, MD_PER_CLOCK, &cur_per_clock);
+ if (retval != ERROR_OK)
+ goto err;
+
+ if (!(cur_per_clock & MD_PER_CLOCK_RST_CLK)) {
+ /* Something's very wrong if the RST_CLK module is not clocked */
+ LOG_ERROR("Target needs reset before flash operations");
+ retval = ERROR_FLASH_OPERATION_FAILED;
+ goto err;
+ }
+
+ retval = target_write_u32(target, MD_PER_CLOCK, cur_per_clock | MD_PER_CLOCK_EEPROM);
+ if (retval != ERROR_OK)
+ goto err;
+
+ retval = target_write_u32(target, FLASH_KEY, KEY);
+ if (retval != ERROR_OK)
+ goto err;
+
+ retval = target_read_u32(target, FLASH_CMD, &flash_cmd);
+ if (retval != ERROR_OK)
+ goto err_lock;
+
+ /* Switch on register access */
+ flash_cmd = (flash_cmd & FLASH_DELAY_MASK) | FLASH_CON | FLASH_IFREN;
+ retval = target_write_u32(target, FLASH_CMD, flash_cmd);
+ if (retval != ERROR_OK)
+ goto reset_pg_and_lock;
+
+ for (uint32_t i = 0; i < count; i += 4) {
+ retval = target_write_u32(target, FLASH_ADR, offset + i);
+ if (retval != ERROR_OK)
+ goto reset_pg_and_lock;
+
+ retval = target_write_u32(target, FLASH_CMD, flash_cmd |
+ FLASH_XE | FLASH_YE | FLASH_SE);
+ if (retval != ERROR_OK)
+ goto reset_pg_and_lock;
+
+ uint32_t buf;
+ retval = target_read_u32(target, FLASH_DO, &buf);
+ if (retval != ERROR_OK)
+ goto reset_pg_and_lock;
+
+ buf_set_u32(buffer, i * 8, 32, buf);
+
+ retval = target_write_u32(target, FLASH_CMD, flash_cmd);
+ if (retval != ERROR_OK)
+ goto reset_pg_and_lock;
+
+ }
+
+reset_pg_and_lock:
+ flash_cmd &= FLASH_DELAY_MASK;
+ retval2 = target_write_u32(target, FLASH_CMD, flash_cmd);
+ if (retval == ERROR_OK)
+ retval = retval2;
+
+err_lock:
+ retval2 = target_write_u32(target, FLASH_KEY, 0);
+ if (retval == ERROR_OK)
+ retval = retval2;
+
+err:
+ return retval;
+}
+
+static int mdr_probe(struct flash_bank *bank)
+{
+ struct mdr_flash_bank *mdr_info = bank->driver_priv;
+ unsigned int page_count, page_size, i;
+
+ page_count = mdr_info->page_count;
+ page_size = bank->size / page_count;
+
+ if (bank->sectors) {
+ free(bank->sectors);
+ bank->sectors = NULL;
+ }
+
+ bank->num_sectors = page_count;
+ bank->sectors = malloc(sizeof(struct flash_sector) * page_count);
+
+ for (i = 0; i < page_count; i++) {
+ bank->sectors[i].offset = i * page_size;
+ bank->sectors[i].size = page_size;
+ bank->sectors[i].is_erased = -1;
+ bank->sectors[i].is_protected = 0;
+ }
+
+ mdr_info->probed = 1;
+
+ return ERROR_OK;
+}
+
+static int mdr_auto_probe(struct flash_bank *bank)
+{
+ struct mdr_flash_bank *mdr_info = bank->driver_priv;
+ if (mdr_info->probed)
+ return ERROR_OK;
+ return mdr_probe(bank);
+}
+
+static int get_mdr_info(struct flash_bank *bank, char *buf, int buf_size)
+{
+ struct mdr_flash_bank *mdr_info = bank->driver_priv;
+ snprintf(buf, buf_size, "MDR32Fx - %s",
+ mdr_info->mem_type ? "info memory" : "main memory");
+
+ return ERROR_OK;
+}
+
+struct flash_driver mdr_flash = {
+ .name = "mdr",
+ .usage = "flash bank <name> mdr <base> <size> 0 0 <target#> <type> <page_count> <sec_count>\n"
+ "<type>: 0 for main memory, 1 for info memory",
+ .flash_bank_command = mdr_flash_bank_command,
+ .erase = mdr_erase,
+ .protect = mdr_protect,
+ .write = mdr_write,
+ .read = mdr_read,
+ .probe = mdr_probe,
+ .auto_probe = mdr_auto_probe,
+ .erase_check = default_flash_blank_check,
+ .protect_check = mdr_protect_check,
+ .info = get_mdr_info,
+};
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/mrvlqspi.c
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/mrvlqspi.c b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/mrvlqspi.c
new file mode 100755
index 0000000..21fc91b
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/mrvlqspi.c
@@ -0,0 +1,961 @@
+/***************************************************************************
+ * Copyright (C) 2014 by Mahavir Jain <mj...@marvell.com> *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ * *
+ ***************************************************************************/
+
+ /*
+ * This is QSPI flash controller driver for Marvell's Wireless
+ * Microcontroller platform.
+ *
+ * For more information please refer,
+ * https://origin-www.marvell.com/microcontrollers/wi-fi-microcontroller-platform/
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "imp.h"
+#include "spi.h"
+#include <helper/binarybuffer.h>
+#include <target/algorithm.h>
+#include <target/armv7m.h>
+
+#define QSPI_R_EN (0x0)
+#define QSPI_W_EN (0x1)
+#define QSPI_SS_DISABLE (0x0)
+#define QSPI_SS_ENABLE (0x1)
+#define WRITE_DISBALE (0x0)
+#define WRITE_ENABLE (0x1)
+
+#define QSPI_TIMEOUT (1000)
+#define FIFO_FLUSH_TIMEOUT (1000)
+#define BLOCK_ERASE_TIMEOUT (1000)
+#define CHIP_ERASE_TIMEOUT (10000)
+
+#define SS_EN (1 << 0)
+#define XFER_RDY (1 << 1)
+#define RFIFO_EMPTY (1 << 4)
+#define WFIFO_EMPTY (1 << 6)
+#define WFIFO_FULL (1 << 7)
+#define FIFO_FLUSH (1 << 9)
+#define RW_EN (1 << 13)
+#define XFER_STOP (1 << 14)
+#define XFER_START (1 << 15)
+#define CONF_MASK (0x7)
+#define CONF_OFFSET (10)
+
+#define INS_WRITE_ENABLE 0x06
+#define INS_WRITE_DISABLE 0x04
+#define INS_READ_STATUS 0x05
+#define INS_PAGE_PROGRAM 0x02
+
+#define CNTL 0x0 /* QSPI_BASE + 0x0 */
+#define CONF 0x4
+#define DOUT 0x8
+#define DIN 0xc
+#define INSTR 0x10
+#define ADDR 0x14
+#define RDMODE 0x18
+#define HDRCNT 0x1c
+#define DINCNT 0x20
+
+struct mrvlqspi_flash_bank {
+ int probed;
+ uint32_t reg_base;
+ uint32_t bank_num;
+ const struct flash_device *dev;
+};
+
+static inline uint32_t mrvlqspi_get_reg(struct flash_bank *bank, uint32_t reg)
+{
+ struct mrvlqspi_flash_bank *mrvlqspi_info = bank->driver_priv;
+ return reg + mrvlqspi_info->reg_base;
+}
+
+static inline int mrvlqspi_set_din_cnt(struct flash_bank *bank, uint32_t count)
+{
+ struct target *target = bank->target;
+
+ return target_write_u32(target, mrvlqspi_get_reg(bank, DINCNT), count);
+}
+
+static inline int mrvlqspi_set_addr(struct flash_bank *bank, uint32_t addr)
+{
+ struct target *target = bank->target;
+
+ return target_write_u32(target, mrvlqspi_get_reg(bank, ADDR), addr);
+}
+
+static inline int mrvlqspi_set_instr(struct flash_bank *bank, uint32_t instr)
+{
+ struct target *target = bank->target;
+
+ return target_write_u32(target, mrvlqspi_get_reg(bank, INSTR), instr);
+}
+
+static inline int mrvlqspi_set_hdr_cnt(struct flash_bank *bank, uint32_t hdr_cnt)
+{
+ struct target *target = bank->target;
+
+ return target_write_u32(target, mrvlqspi_get_reg(bank, HDRCNT), hdr_cnt);
+}
+
+static int mrvlqspi_set_conf(struct flash_bank *bank, uint32_t conf_val)
+{
+ int retval;
+ uint32_t regval;
+ struct target *target = bank->target;
+
+ retval = target_read_u32(target,
+ mrvlqspi_get_reg(bank, CONF), ®val);
+ if (retval != ERROR_OK)
+ return retval;
+
+ regval &= ~(CONF_MASK << CONF_OFFSET);
+ regval |= (conf_val << CONF_OFFSET);
+
+ return target_write_u32(target,
+ mrvlqspi_get_reg(bank, CONF), regval);
+}
+
+static int mrvlqspi_set_ss_state(struct flash_bank *bank, bool state, int timeout)
+{
+ int retval;
+ uint32_t regval;
+ struct target *target = bank->target;
+
+ retval = target_read_u32(target,
+ mrvlqspi_get_reg(bank, CNTL), ®val);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (state)
+ regval |= SS_EN;
+ else
+ regval &= ~(SS_EN);
+
+ retval = target_write_u32(target,
+ mrvlqspi_get_reg(bank, CNTL), regval);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* wait for xfer_ready to set */
+ for (;;) {
+ retval = target_read_u32(target,
+ mrvlqspi_get_reg(bank, CNTL), ®val);
+ if (retval != ERROR_OK)
+ return retval;
+ LOG_DEBUG("status: 0x%08" PRIx32, regval);
+ if ((regval & XFER_RDY) == XFER_RDY)
+ break;
+ if (timeout-- <= 0) {
+ LOG_ERROR("timed out waiting for flash");
+ return ERROR_FAIL;
+ }
+ alive_sleep(1);
+ }
+ return ERROR_OK;
+}
+
+static int mrvlqspi_start_transfer(struct flash_bank *bank, bool rw_mode)
+{
+ int retval;
+ uint32_t regval;
+ struct target *target = bank->target;
+
+ retval = mrvlqspi_set_ss_state(bank, QSPI_SS_ENABLE, QSPI_TIMEOUT);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = target_read_u32(target,
+ mrvlqspi_get_reg(bank, CONF), ®val);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (rw_mode)
+ regval |= RW_EN;
+ else
+ regval &= ~(RW_EN);
+
+ regval |= XFER_START;
+
+ retval = target_write_u32(target,
+ mrvlqspi_get_reg(bank, CONF), regval);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+}
+
+static int mrvlqspi_stop_transfer(struct flash_bank *bank)
+{
+ int retval;
+ uint32_t regval;
+ struct target *target = bank->target;
+ int timeout = QSPI_TIMEOUT;
+
+ /* wait for xfer_ready and wfifo_empty to set */
+ for (;;) {
+ retval = target_read_u32(target,
+ mrvlqspi_get_reg(bank, CNTL), ®val);
+ if (retval != ERROR_OK)
+ return retval;
+ LOG_DEBUG("status: 0x%08" PRIx32, regval);
+ if ((regval & (XFER_RDY | WFIFO_EMPTY)) ==
+ (XFER_RDY | WFIFO_EMPTY))
+ break;
+ if (timeout-- <= 0) {
+ LOG_ERROR("timed out waiting for flash");
+ return ERROR_FAIL;
+ }
+ alive_sleep(1);
+ }
+
+ retval = target_read_u32(target,
+ mrvlqspi_get_reg(bank, CONF), ®val);
+ if (retval != ERROR_OK)
+ return retval;
+
+ regval |= XFER_STOP;
+
+ retval = target_write_u32(target,
+ mrvlqspi_get_reg(bank, CONF), regval);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* wait for xfer_start to reset */
+ for (;;) {
+ retval = target_read_u32(target,
+ mrvlqspi_get_reg(bank, CONF), ®val);
+ if (retval != ERROR_OK)
+ return retval;
+ LOG_DEBUG("status: 0x%08" PRIx32, regval);
+ if ((regval & XFER_START) == 0)
+ break;
+ if (timeout-- <= 0) {
+ LOG_ERROR("timed out waiting for flash");
+ return ERROR_FAIL;
+ }
+ alive_sleep(1);
+ }
+
+ retval = mrvlqspi_set_ss_state(bank, QSPI_SS_DISABLE, QSPI_TIMEOUT);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+}
+
+static int mrvlqspi_fifo_flush(struct flash_bank *bank, int timeout)
+{
+ int retval;
+ uint32_t val;
+ struct target *target = bank->target;
+
+ retval = target_read_u32(target,
+ mrvlqspi_get_reg(bank, CONF), &val);
+ if (retval != ERROR_OK)
+ return retval;
+
+ val |= FIFO_FLUSH;
+
+ retval = target_write_u32(target,
+ mrvlqspi_get_reg(bank, CONF), val);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* wait for fifo_flush to clear */
+ for (;;) {
+ retval = target_read_u32(target,
+ mrvlqspi_get_reg(bank, CONF), &val);
+ if (retval != ERROR_OK)
+ return retval;
+ LOG_DEBUG("status: 0x%08" PRIX32, val);
+ if ((val & FIFO_FLUSH) == 0)
+ break;
+ if (timeout-- <= 0) {
+ LOG_ERROR("timed out waiting for flash");
+ return ERROR_FAIL;
+ }
+ alive_sleep(1);
+ }
+ return ERROR_OK;
+}
+
+static int mrvlqspi_read_byte(struct flash_bank *bank, uint8_t *data)
+{
+ int retval;
+ uint32_t val;
+ struct target *target = bank->target;
+
+ /* wait for rfifo_empty to reset */
+ for (;;) {
+ retval = target_read_u32(target,
+ mrvlqspi_get_reg(bank, CNTL), &val);
+ if (retval != ERROR_OK)
+ return retval;
+ LOG_DEBUG("status: 0x%08" PRIx32, val);
+ if ((val & RFIFO_EMPTY) == 0)
+ break;
+ usleep(10);
+ }
+
+ retval = target_read_u32(target,
+ mrvlqspi_get_reg(bank, DIN), &val);
+ if (retval != ERROR_OK)
+ return retval;
+
+ *data = val & 0xFF;
+
+ return ERROR_OK;
+}
+
+static int mrvlqspi_flash_busy_status(struct flash_bank *bank, int timeout)
+{
+ uint8_t val;
+ int retval;
+
+ /* Flush read/write fifo's */
+ retval = mrvlqspi_fifo_flush(bank, FIFO_FLUSH_TIMEOUT);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Set instruction/addr count value */
+ retval = mrvlqspi_set_hdr_cnt(bank, 0x1);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Read flash status register in continuous manner */
+ retval = mrvlqspi_set_din_cnt(bank, 0x0);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Set instruction */
+ retval = mrvlqspi_set_instr(bank, INS_READ_STATUS);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Set data and addr pin length */
+ retval = mrvlqspi_set_conf(bank, 0x0);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Enable read mode transfer */
+ retval = mrvlqspi_start_transfer(bank, QSPI_R_EN);
+ if (retval != ERROR_OK)
+ return retval;
+
+ for (;;) {
+ retval = mrvlqspi_read_byte(bank, &val);
+ if (retval != ERROR_OK)
+ return retval;
+ if (!(val & 0x1))
+ break;
+ if (timeout-- <= 0) {
+ LOG_ERROR("timed out waiting for flash");
+ return ERROR_FAIL;
+ }
+ alive_sleep(1);
+ }
+
+ return mrvlqspi_stop_transfer(bank);
+}
+
+static int mrvlqspi_set_write_status(struct flash_bank *bank, bool mode)
+{
+ int retval;
+ uint32_t instr;
+
+ /* Flush read/write fifo's */
+ retval = mrvlqspi_fifo_flush(bank, FIFO_FLUSH_TIMEOUT);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Set instruction/addr count value */
+ retval = mrvlqspi_set_hdr_cnt(bank, 0x1);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (mode)
+ instr = INS_WRITE_ENABLE;
+ else
+ instr = INS_WRITE_DISABLE;
+
+ /* Set instruction */
+ retval = mrvlqspi_set_instr(bank, instr);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = mrvlqspi_start_transfer(bank, QSPI_W_EN);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = mrvlqspi_stop_transfer(bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return retval;
+}
+
+static int mrvlqspi_read_id(struct flash_bank *bank, uint32_t *id)
+{
+ uint8_t id_buf[3] = {0, 0, 0};
+ int retval, i;
+
+ LOG_DEBUG("Getting ID");
+
+ /* Flush read/write fifo's */
+ retval = mrvlqspi_fifo_flush(bank, FIFO_FLUSH_TIMEOUT);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Set instruction/addr count value */
+ retval = mrvlqspi_set_hdr_cnt(bank, 0x1);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Set count for number of bytes to read */
+ retval = mrvlqspi_set_din_cnt(bank, 0x3);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Set instruction */
+ retval = mrvlqspi_set_instr(bank, SPIFLASH_READ_ID);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Set data and addr pin length */
+ retval = mrvlqspi_set_conf(bank, 0x0);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = mrvlqspi_start_transfer(bank, QSPI_R_EN);
+ if (retval != ERROR_OK)
+ return retval;
+
+ for (i = 0; i < 3; i++) {
+ retval = mrvlqspi_read_byte(bank, &id_buf[i]);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ LOG_DEBUG("ID is 0x%02" PRIx8 " 0x%02" PRIx8 " 0x%02" PRIx8,
+ id_buf[0], id_buf[1], id_buf[2]);
+ retval = mrvlqspi_set_ss_state(bank, QSPI_SS_DISABLE, QSPI_TIMEOUT);
+ if (retval != ERROR_OK)
+ return retval;
+
+ *id = id_buf[2] << 16 | id_buf[1] << 8 | id_buf[0];
+ return ERROR_OK;
+}
+
+static int mrvlqspi_block_erase(struct flash_bank *bank, uint32_t offset)
+{
+ int retval;
+ struct mrvlqspi_flash_bank *mrvlqspi_info = bank->driver_priv;
+
+ /* Set flash write enable */
+ retval = mrvlqspi_set_write_status(bank, WRITE_ENABLE);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Set instruction/addr count value */
+ retval = mrvlqspi_set_hdr_cnt(bank, (0x1 | (0x3 << 4)));
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Set read offset address */
+ retval = mrvlqspi_set_addr(bank, offset);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Set instruction */
+ retval = mrvlqspi_set_instr(bank, mrvlqspi_info->dev->erase_cmd);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = mrvlqspi_start_transfer(bank, QSPI_W_EN);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = mrvlqspi_stop_transfer(bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return mrvlqspi_flash_busy_status(bank, BLOCK_ERASE_TIMEOUT);
+}
+
+static int mrvlqspi_bulk_erase(struct flash_bank *bank)
+{
+ int retval;
+ struct mrvlqspi_flash_bank *mrvlqspi_info = bank->driver_priv;
+
+ /* Set flash write enable */
+ retval = mrvlqspi_set_write_status(bank, WRITE_ENABLE);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Set instruction */
+ retval = mrvlqspi_set_instr(bank, mrvlqspi_info->dev->chip_erase_cmd);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = mrvlqspi_start_transfer(bank, QSPI_W_EN);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = mrvlqspi_stop_transfer(bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return mrvlqspi_flash_busy_status(bank, CHIP_ERASE_TIMEOUT);
+}
+
+static int mrvlqspi_flash_erase(struct flash_bank *bank, int first, int last)
+{
+ struct target *target = bank->target;
+ struct mrvlqspi_flash_bank *mrvlqspi_info = bank->driver_priv;
+ int retval = ERROR_OK;
+ int sector;
+
+ LOG_DEBUG("erase from sector %d to sector %d", first, last);
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if ((first < 0) || (last < first) || (last >= bank->num_sectors)) {
+ LOG_ERROR("Flash sector invalid");
+ return ERROR_FLASH_SECTOR_INVALID;
+ }
+
+ if (!(mrvlqspi_info->probed)) {
+ LOG_ERROR("Flash bank not probed");
+ return ERROR_FLASH_BANK_NOT_PROBED;
+ }
+
+ for (sector = first; sector <= last; sector++) {
+ if (bank->sectors[sector].is_protected) {
+ LOG_ERROR("Flash sector %d protected", sector);
+ return ERROR_FAIL;
+ }
+ }
+
+ /* If we're erasing the entire chip and the flash supports
+ * it, use a bulk erase instead of going sector-by-sector. */
+ if (first == 0 && last == (bank->num_sectors - 1)
+ && mrvlqspi_info->dev->chip_erase_cmd !=
+ mrvlqspi_info->dev->erase_cmd) {
+ LOG_DEBUG("Chip supports the bulk erase command."\
+ " Will use bulk erase instead of sector-by-sector erase.");
+ retval = mrvlqspi_bulk_erase(bank);
+ if (retval == ERROR_OK) {
+ return retval;
+ } else
+ LOG_WARNING("Bulk flash erase failed."
+ " Falling back to sector-by-sector erase.");
+ }
+
+ for (sector = first; sector <= last; sector++) {
+ retval = mrvlqspi_block_erase(bank,
+ sector * mrvlqspi_info->dev->sectorsize);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ return retval;
+}
+
+static int mrvlqspi_flash_write(struct flash_bank *bank, const uint8_t *buffer,
+ uint32_t offset, uint32_t count)
+{
+ struct target *target = bank->target;
+ struct mrvlqspi_flash_bank *mrvlqspi_info = bank->driver_priv;
+ int retval = ERROR_OK;
+ uint32_t page_size, fifo_size;
+ struct working_area *fifo;
+ struct reg_param reg_params[6];
+ struct armv7m_algorithm armv7m_info;
+ struct working_area *write_algorithm;
+ int sector;
+
+ LOG_DEBUG("offset=0x%08" PRIx32 " count=0x%08" PRIx32,
+ offset, count);
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (offset + count > mrvlqspi_info->dev->size_in_bytes) {
+ LOG_WARNING("Writes past end of flash. Extra data discarded.");
+ count = mrvlqspi_info->dev->size_in_bytes - offset;
+ }
+
+ /* Check sector protection */
+ for (sector = 0; sector < bank->num_sectors; sector++) {
+ /* Start offset in or before this sector? */
+ /* End offset in or behind this sector? */
+ if ((offset <
+ (bank->sectors[sector].offset + bank->sectors[sector].size))
+ && ((offset + count - 1) >= bank->sectors[sector].offset)
+ && bank->sectors[sector].is_protected) {
+ LOG_ERROR("Flash sector %d protected", sector);
+ return ERROR_FAIL;
+ }
+ }
+
+ page_size = mrvlqspi_info->dev->pagesize;
+
+ /* See contrib/loaders/flash/mrvlqspi.S for src */
+ static const uint8_t mrvlqspi_flash_write_code[] = {
+ 0x4f, 0xf0, 0x00, 0x0a, 0xa2, 0x44, 0x92, 0x45,
+ 0x7f, 0xf6, 0xfc, 0xaf, 0x00, 0xf0, 0x6b, 0xf8,
+ 0x5f, 0xf0, 0x01, 0x08, 0xc5, 0xf8, 0x1c, 0x80,
+ 0x5f, 0xf0, 0x06, 0x08, 0xc5, 0xf8, 0x10, 0x80,
+ 0x5f, 0xf0, 0x01, 0x09, 0x00, 0xf0, 0x6b, 0xf8,
+ 0x00, 0xf0, 0x7d, 0xf8, 0x5f, 0xf0, 0x31, 0x08,
+ 0xc5, 0xf8, 0x1c, 0x80, 0x90, 0x46, 0xc5, 0xf8,
+ 0x14, 0x80, 0x5f, 0xf0, 0x02, 0x08, 0xc5, 0xf8,
+ 0x10, 0x80, 0x5f, 0xf0, 0x01, 0x09, 0x00, 0xf0,
+ 0x5a, 0xf8, 0xd0, 0xf8, 0x00, 0x80, 0xb8, 0xf1,
+ 0x00, 0x0f, 0x00, 0xf0, 0x8b, 0x80, 0x47, 0x68,
+ 0x47, 0x45, 0x3f, 0xf4, 0xf6, 0xaf, 0x17, 0xf8,
+ 0x01, 0x9b, 0x00, 0xf0, 0x30, 0xf8, 0x8f, 0x42,
+ 0x28, 0xbf, 0x00, 0xf1, 0x08, 0x07, 0x47, 0x60,
+ 0x01, 0x3b, 0x00, 0x2b, 0x00, 0xf0, 0x05, 0x80,
+ 0x02, 0xf1, 0x01, 0x02, 0x92, 0x45, 0x7f, 0xf4,
+ 0xe4, 0xaf, 0x00, 0xf0, 0x50, 0xf8, 0xa2, 0x44,
+ 0x00, 0xf0, 0x2d, 0xf8, 0x5f, 0xf0, 0x01, 0x08,
+ 0xc5, 0xf8, 0x1c, 0x80, 0x5f, 0xf0, 0x00, 0x08,
+ 0xc5, 0xf8, 0x20, 0x80, 0x5f, 0xf0, 0x05, 0x08,
+ 0xc5, 0xf8, 0x10, 0x80, 0x5f, 0xf0, 0x00, 0x09,
+ 0x00, 0xf0, 0x29, 0xf8, 0x00, 0xf0, 0x13, 0xf8,
+ 0x09, 0xf0, 0x01, 0x09, 0xb9, 0xf1, 0x00, 0x0f,
+ 0xf8, 0xd1, 0x00, 0xf0, 0x34, 0xf8, 0x00, 0x2b,
+ 0xa4, 0xd1, 0x00, 0xf0, 0x53, 0xb8, 0xd5, 0xf8,
+ 0x00, 0x80, 0x5f, 0xea, 0x08, 0x68, 0xfa, 0xd4,
+ 0xc5, 0xf8, 0x08, 0x90, 0x70, 0x47, 0xd5, 0xf8,
+ 0x00, 0x80, 0x5f, 0xea, 0xc8, 0x68, 0xfa, 0xd4,
+ 0xd5, 0xf8, 0x0c, 0x90, 0x70, 0x47, 0xd5, 0xf8,
+ 0x04, 0x80, 0x48, 0xf4, 0x00, 0x78, 0xc5, 0xf8,
+ 0x04, 0x80, 0xd5, 0xf8, 0x04, 0x80, 0x5f, 0xea,
+ 0x88, 0x58, 0xfa, 0xd4, 0x70, 0x47, 0xd5, 0xf8,
+ 0x00, 0x80, 0x48, 0xf0, 0x01, 0x08, 0xc5, 0xf8,
+ 0x00, 0x80, 0xd5, 0xf8, 0x00, 0x80, 0x5f, 0xea,
+ 0x88, 0x78, 0xfa, 0xd5, 0xd5, 0xf8, 0x04, 0x80,
+ 0x69, 0xf3, 0x4d, 0x38, 0x48, 0xf4, 0x00, 0x48,
+ 0xc5, 0xf8, 0x04, 0x80, 0x70, 0x47, 0xd5, 0xf8,
+ 0x00, 0x80, 0x5f, 0xea, 0x88, 0x78, 0xfa, 0xd5,
+ 0xd5, 0xf8, 0x00, 0x80, 0x5f, 0xea, 0x48, 0x68,
+ 0xfa, 0xd5, 0xd5, 0xf8, 0x04, 0x80, 0x48, 0xf4,
+ 0x80, 0x48, 0xc5, 0xf8, 0x04, 0x80, 0xd5, 0xf8,
+ 0x04, 0x80, 0x5f, 0xea, 0x08, 0x48, 0xfa, 0xd4,
+ 0xd5, 0xf8, 0x00, 0x80, 0x28, 0xf0, 0x01, 0x08,
+ 0xc5, 0xf8, 0x00, 0x80, 0xd5, 0xf8, 0x00, 0x80,
+ 0x5f, 0xea, 0x88, 0x78, 0xfa, 0xd5, 0x70, 0x47,
+ 0x00, 0x20, 0x50, 0x60, 0x30, 0x46, 0x00, 0xbe
+ };
+
+ if (target_alloc_working_area(target, sizeof(mrvlqspi_flash_write_code),
+ &write_algorithm) != ERROR_OK) {
+ LOG_ERROR("Insufficient working area. You must configure"\
+ " a working area > %zdB in order to write to SPIFI flash.",
+ sizeof(mrvlqspi_flash_write_code));
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ retval = target_write_buffer(target, write_algorithm->address,
+ sizeof(mrvlqspi_flash_write_code),
+ mrvlqspi_flash_write_code);
+ if (retval != ERROR_OK) {
+ target_free_working_area(target, write_algorithm);
+ return retval;
+ }
+
+ /* FIFO allocation */
+ fifo_size = target_get_working_area_avail(target);
+
+ if (fifo_size == 0) {
+ /* if we already allocated the writing code but failed to get fifo
+ * space, free the algorithm */
+ target_free_working_area(target, write_algorithm);
+
+ LOG_ERROR("Insufficient working area. Please allocate at least"\
+ " %zdB of working area to enable flash writes.",
+ sizeof(mrvlqspi_flash_write_code) + 1
+ );
+
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ } else if (fifo_size < page_size)
+ LOG_WARNING("Working area size is limited; flash writes may be"\
+ " slow. Increase working area size to at least %zdB"\
+ " to reduce write times.",
+ (size_t)(sizeof(mrvlqspi_flash_write_code) + page_size)
+ );
+
+ if (target_alloc_working_area(target, fifo_size, &fifo) != ERROR_OK) {
+ target_free_working_area(target, write_algorithm);
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
+ armv7m_info.core_mode = ARM_MODE_THREAD;
+
+ init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
+ init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* buffer end */
+ init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* target address */
+ init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* count (halfword-16bit) */
+ init_reg_param(®_params[4], "r4", 32, PARAM_OUT); /* page size */
+ init_reg_param(®_params[5], "r5", 32, PARAM_OUT); /* qspi base address */
+
+ buf_set_u32(reg_params[0].value, 0, 32, fifo->address);
+ buf_set_u32(reg_params[1].value, 0, 32, fifo->address + fifo->size);
+ buf_set_u32(reg_params[2].value, 0, 32, offset);
+ buf_set_u32(reg_params[3].value, 0, 32, count);
+ buf_set_u32(reg_params[4].value, 0, 32, page_size);
+ buf_set_u32(reg_params[5].value, 0, 32, (uint32_t) mrvlqspi_info->reg_base);
+
+ retval = target_run_flash_async_algorithm(target, buffer, count, 1,
+ 0, NULL,
+ 6, reg_params,
+ fifo->address, fifo->size,
+ write_algorithm->address, 0,
+ &armv7m_info
+ );
+
+ if (retval != ERROR_OK)
+ LOG_ERROR("Error executing flash write algorithm");
+
+ target_free_working_area(target, fifo);
+ target_free_working_area(target, write_algorithm);
+
+ destroy_reg_param(®_params[0]);
+ destroy_reg_param(®_params[1]);
+ destroy_reg_param(®_params[2]);
+ destroy_reg_param(®_params[3]);
+ destroy_reg_param(®_params[4]);
+ destroy_reg_param(®_params[5]);
+
+ return retval;
+}
+
+int mrvlqspi_flash_read(struct flash_bank *bank, uint8_t *buffer,
+ uint32_t offset, uint32_t count)
+{
+ struct target *target = bank->target;
+ struct mrvlqspi_flash_bank *mrvlqspi_info = bank->driver_priv;
+ int retval;
+ uint32_t i;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (!(mrvlqspi_info->probed)) {
+ LOG_ERROR("Flash bank not probed");
+ return ERROR_FLASH_BANK_NOT_PROBED;
+ }
+
+ /* Flush read/write fifo's */
+ retval = mrvlqspi_fifo_flush(bank, FIFO_FLUSH_TIMEOUT);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Set instruction/addr count value */
+ retval = mrvlqspi_set_hdr_cnt(bank, (0x1 | (0x3 << 4)));
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Set count for number of bytes to read */
+ retval = mrvlqspi_set_din_cnt(bank, count);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Set read address */
+ retval = mrvlqspi_set_addr(bank, offset);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Set instruction */
+ retval = mrvlqspi_set_instr(bank, SPIFLASH_READ);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Set data and addr pin length */
+ retval = mrvlqspi_set_conf(bank, 0x0);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = mrvlqspi_start_transfer(bank, QSPI_R_EN);
+ if (retval != ERROR_OK)
+ return retval;
+
+ for (i = 0; i < count; i++) {
+ retval = mrvlqspi_read_byte(bank, &buffer[i]);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ retval = mrvlqspi_set_ss_state(bank, QSPI_SS_DISABLE, QSPI_TIMEOUT);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+}
+
+static int mrvlqspi_probe(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ struct mrvlqspi_flash_bank *mrvlqspi_info = bank->driver_priv;
+ uint32_t id = 0;
+ int retval;
+ struct flash_sector *sectors;
+
+ /* If we've already probed, we should be fine to skip this time. */
+ if (mrvlqspi_info->probed)
+ return ERROR_OK;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ mrvlqspi_info->probed = 0;
+ mrvlqspi_info->bank_num = bank->bank_number;
+
+ /* Read flash JEDEC ID */
+ retval = mrvlqspi_read_id(bank, &id);
+ if (retval != ERROR_OK)
+ return retval;
+
+ mrvlqspi_info->dev = NULL;
+ for (const struct flash_device *p = flash_devices; p->name ; p++)
+ if (p->device_id == id) {
+ mrvlqspi_info->dev = p;
+ break;
+ }
+
+ if (!mrvlqspi_info->dev) {
+ LOG_ERROR("Unknown flash device ID 0x%08" PRIx32, id);
+ return ERROR_FAIL;
+ }
+
+ LOG_INFO("Found flash device \'%s\' ID 0x%08" PRIx32,
+ mrvlqspi_info->dev->name, mrvlqspi_info->dev->device_id);
+
+ /* Set correct size value */
+ bank->size = mrvlqspi_info->dev->size_in_bytes;
+
+ /* create and fill sectors array */
+ bank->num_sectors = mrvlqspi_info->dev->size_in_bytes /
+ mrvlqspi_info->dev->sectorsize;
+ sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
+ if (sectors == NULL) {
+ LOG_ERROR("not enough memory");
+ return ERROR_FAIL;
+ }
+
+ for (int sector = 0; sector < bank->num_sectors; sector++) {
+ sectors[sector].offset =
+ sector * mrvlqspi_info->dev->sectorsize;
+ sectors[sector].size = mrvlqspi_info->dev->sectorsize;
+ sectors[sector].is_erased = -1;
+ sectors[sector].is_protected = 0;
+ }
+
+ bank->sectors = sectors;
+ mrvlqspi_info->probed = 1;
+
+ return ERROR_OK;
+}
+
+static int mrvlqspi_auto_probe(struct flash_bank *bank)
+{
+ struct mrvlqspi_flash_bank *mrvlqspi_info = bank->driver_priv;
+ if (mrvlqspi_info->probed)
+ return ERROR_OK;
+ return mrvlqspi_probe(bank);
+}
+
+static int mrvlqspi_flash_erase_check(struct flash_bank *bank)
+{
+ /* Not implemented yet */
+ return ERROR_OK;
+}
+
+static int mrvlqspi_protect_check(struct flash_bank *bank)
+{
+ /* Not implemented yet */
+ return ERROR_OK;
+}
+
+int mrvlqspi_get_info(struct flash_bank *bank, char *buf, int buf_size)
+{
+ struct mrvlqspi_flash_bank *mrvlqspi_info = bank->driver_priv;
+
+ if (!(mrvlqspi_info->probed)) {
+ snprintf(buf, buf_size,
+ "\nQSPI flash bank not probed yet\n");
+ return ERROR_OK;
+ }
+
+ snprintf(buf, buf_size, "\nQSPI flash information:\n"
+ " Device \'%s\' ID 0x%08" PRIx32 "\n",
+ mrvlqspi_info->dev->name, mrvlqspi_info->dev->device_id);
+
+ return ERROR_OK;
+}
+
+FLASH_BANK_COMMAND_HANDLER(mrvlqspi_flash_bank_command)
+{
+ struct mrvlqspi_flash_bank *mrvlqspi_info;
+
+ if (CMD_ARGC < 7)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ mrvlqspi_info = malloc(sizeof(struct mrvlqspi_flash_bank));
+ if (mrvlqspi_info == NULL) {
+ LOG_ERROR("not enough memory");
+ return ERROR_FAIL;
+ }
+
+ /* Get QSPI controller register map base address */
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[6], mrvlqspi_info->reg_base);
+ bank->driver_priv = mrvlqspi_info;
+ mrvlqspi_info->probed = 0;
+
+ return ERROR_OK;
+}
+
+struct flash_driver mrvlqspi_flash = {
+ .name = "mrvlqspi",
+ .flash_bank_command = mrvlqspi_flash_bank_command,
+ .erase = mrvlqspi_flash_erase,
+ .protect = NULL,
+ .write = mrvlqspi_flash_write,
+ .read = mrvlqspi_flash_read,
+ .probe = mrvlqspi_probe,
+ .auto_probe = mrvlqspi_auto_probe,
+ .erase_check = mrvlqspi_flash_erase_check,
+ .protect_check = mrvlqspi_protect_check,
+ .info = mrvlqspi_get_info,
+};