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Posted to commits@tvm.apache.org by "tmoreau89 (via GitHub)" <gi...@apache.org> on 2023/01/31 21:05:23 UTC

[GitHub] [tvm] tmoreau89 commented on a diff in pull request #13844: [Hexagon] Detect and flush "dirty" cache prior to DMA read with cache bypass enabled

tmoreau89 commented on code in PR #13844:
URL: https://github.com/apache/tvm/pull/13844#discussion_r1092480482


##########
src/tir/transforms/lower_async_dma.cc:
##########
@@ -192,19 +198,33 @@ class AsyncDMALowerer : public StmtExprMutator {
       // save queue ID for inspection in `wait` transform
       queue_ids_.insert(queue_id);
 
-      return Evaluate(Call(DataType::Int(32), builtin::dma_copy(),
-                           {queue_id,
-                            Call(DataType::Handle(), builtin::address_of(),
-                                 {BufferLoad(bufferstorenode->buffer, store_index)}),
-                            Call(DataType::Handle(), builtin::address_of(),
-                                 {BufferLoad(bufferloadnode->buffer, load_index)}),
-                            for_loop->extent * bufferloadnode->dtype.bytes(), dma_bypass_cache_}));
+      auto call_dma_copy =
+          Evaluate(Call(DataType::Int(32), builtin::dma_copy(),
+                        {queue_id,
+                         Call(DataType::Handle(), builtin::address_of(),
+                              {BufferLoad(bufferstorenode->buffer, store_index)}),
+                         Call(DataType::Handle(), builtin::address_of(),
+                              {BufferLoad(bufferloadnode->buffer, load_index)}),
+                         for_loop->extent * bufferloadnode->dtype.bytes(), dma_bypass_cache_}));
+
+      // if the buffer we are about to DMA was modified by the primfunc
+      // then we need to flush the buffer from the cache prior to the DMA

Review Comment:
   Definitely fine with getting this PR merged first before we plan to make broader changes. Janet's proposed plan seems quite sound.



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