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Posted to commits@mynewt.apache.org by GitBox <gi...@apache.org> on 2019/04/12 07:05:32 UTC
[GitHub] [mynewt-core] mkiiskila commented on a change in pull request
#1758: da1469x: Add some power saving (M33 deep sleep + power rails)
mkiiskila commented on a change in pull request #1758: da1469x: Add some power saving (M33 deep sleep + power rails)
URL: https://github.com/apache/mynewt-core/pull/1758#discussion_r274780248
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File path: hw/mcu/dialog/da1469x/src/arch/cortex_m33/da1469x_m33_sleep.S
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@@ -0,0 +1,251 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+ .syntax unified
+ .arch armv7-m
+
+ .section sleep_state, "aw"
+ .align 3
+ .globl da1469x_m33_sleep_state
+ .type da1469x_m33_sleep_state, %object
+da1469x_m33_sleep_state:
+.saved_primask:
+ .space 4 /* PRIMASK */
+.saved_msp:
+ .space 4 /* MSP */
+.saved_psp:
+ .space 4 /* PSP */
+.saved_control:
+ .space 4 /* CONTROL */
+.saved_regs:
+ .space 40 /* R4-R12, LR */
+.saved_nvic:
+ .space 8 /* ISER[0..1] */
+ .space 40 /* IPR[0..39] */
+.saved_scb:
+ .space 28 /* SCR, CCR, SHPR[0..11], CPACR */
+.saved_fpu:
+ .space 8 /* FPCCR, FPDSCR */
+
+ .size da1469x_m33_sleep_state, . - da1469x_m33_sleep_state
+
+ .equ CLK_AMBA_REG, 0x50000000
+ .equ RESET_STAT_REG, 0x500000BC
+ .equ NVIC_BASE, 0xE000E100
+ .equ NVIC_IPR_OFFSET, 0x300
+ .equ SCB_BASE, 0xE000ED00
+ .equ SCB_SCR_OFFSET, 0x010
+ .equ SCB_SHCSR_OFFSET, 0x024
+ .equ SCB_CPACR_OFFSET, 0x088
+ .equ FPU_BASE, 0xE000EF30
+ .equ FPU_FPCCR_OFFSET, 0x004
+ .equ FPU_FPDSCR_OFFSET, 0x00C
+ .equ QSPIC_BASE, 0x38000000
+ .equ QSPIC_CTRLBUS_OFFSET, 0x000
+ .equ QSPIC_CTRLMOD_OFFSET, 0x004
+ .equ QSPIC_WRITEDATA_OFFSET, 0x018
+
+ .equ SCB_CPACR_MASK, 0x00F00000 /* CP10 and CP11 */
+ .equ SCB_SHCSR_MASK, 0x000F0000 /* xxxFAULTENA */
+ .equ FPU_FPCCR_MASK, 0xF0000000 /* ASPEN, LSPEN, LSPENS, CLRONRET */
+
+ .section .text_ram
+ .thumb
+ .thumb_func
+ .align 2
+ .globl da1469x_m33_sleep
+ .type da1469x_m33_sleep, %function
+da1469x_m33_sleep:
+ ldr r3, =da1469x_m33_sleep_state
+
+/* Disable interrupts and save original PRIMASK */
+ mrs r0, PRIMASK
+ cpsid i
+ stmia r3!, {r0}
+
+/* Save MSP, PSP, CONTROL and general purpose registers */
+ mrs r0, MSP
+ mrs r1, PSP
+ mrs r2, CONTROL
+ stmia r3!, {r0-r2,r4-r12, lr}
+
+/* Save NVIC state (ISER[0..1] and IPR[0..39]) */
+ ldr r0, =NVIC_BASE
+ add r1, r0, NVIC_IPR_OFFSET
+ ldmia r0!, {r4-r5}
+ stmia r3!, {r4-r5}
+ ldmia r1!, {r2, r4-r12}
+ stmia r3!, {r2, r4-r12}
+
+/* Save SCB state (SCR, CCR, SHPR and SHCSR) */
+ ldr r0, =(SCB_BASE + SCB_SCR_OFFSET)
+ ldmia r0!, {r4-r9}
+ and r9, r9, #(SCB_SHCSR_MASK)
+ ldr r10, [r1, #(SCB_CPACR_OFFSET - SCB_SCR_OFFSET)]
+ and r10, r10, #(SCB_CPACR_MASK)
+ stmia r3!, {r4-r10}
+
+/* Save NVIC state (FPCCR and FPDSCR) */
Review comment:
#if MYNEWT_VAL(HARDFLOAT) ?
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