[GitHub] [incubator-nuttx] hartmannathan commented on pull request #2473: [DRAFT] Stm32g4 add adc

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hartmannathan commented on pull request #2473:
URL: https://github.com/apache/incubator-nuttx/pull/2473#issuecomment-738410736


   @davids5 , @raiden00pl -
   
   Suggestions/thoughts wanted:
   
   The STM32G4xx family has a slightly newer IP version of the ADC. It resembles stm32_adc_v2 but has enough differences that I think adding more ifdef to stm32_adc_v2 will create a maintenance nightmare.
   
   Which do you think is best?
   
   - Call this file stm32_adc_v3?
   - Call this file stm32_adc_v2g4?
   - Merge this file into stm32_adc_v2 with additional ifdef?
   
   Here is a summary of the differences between stm32_adc_v2 and this new file for STM32G4xx family:
   
   - Addition of ADC5
   - Common ADC345 instead of ADC34
   - Addition of GCOMP register
   - CR register: ADVREGEN field is only 1 bit wide instead of 2, but there is a new field, DEEPPWD.
   - CFGR register: EXTSEL is 5 bits instead of 4; ALIGN at bit 15 instead of bit 5; addition of JQDIS bit.
   - SMPR1, SMPR2 registers: All sample time options are different: instead of 1.5, 2.5, 4.5, 7.5, 19.5, 61.5, 181.5, or 601.5 cycles, STM32G4 provides these options: 2.5, 6.5, 12.5, 24.5, 47.5, 92.5, 247.5, and 640.5 cycles.
   - Addition of Channel 0, i.e., SMPR1_SMP0.
   - TR1 register: addition of AWDFILT field.
   - JSQR register: JSQ2, JSQ3, and JSQ4 bitfields are at different positions: instead of at bits 14, 20, 26, they are at bits 15, 21, 27.
   - OFR1 thru OFR4 registers: Addition of OFR_OFFSETPOS and OFR_SATEN bits.
   - AWD2CR, AWD3CR, and DIFSEL registers: Additional bit for Channel 0.
   


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